kona.c 226 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <sound/core.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/info.h>
  22. #include <soc/snd_event.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <soc/swr-common.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include "asoc/msm-cdc-pinctrl.h"
  30. #include "asoc/wcd-mbhc-v2.h"
  31. #include "codecs/wcd938x/wcd938x-mbhc.h"
  32. #include "codecs/wsa881x.h"
  33. #include "codecs/wcd938x/wcd938x.h"
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include <dt-bindings/sound/audio-codec-port-types.h>
  36. #include "codecs/bolero/wsa-macro.h"
  37. #include "kona-port-config.h"
  38. #define DRV_NAME "kona-asoc-snd"
  39. #define __CHIPSET__ "KONA "
  40. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define WCD9XXX_MBHC_DEF_RLOADS 5
  55. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  56. #define CODEC_EXT_CLK_RATE 9600000
  57. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  58. #define DEV_NAME_STR_LEN 32
  59. #define WCD_MBHC_HS_V_MAX 1600
  60. #define TDM_CHANNEL_MAX 8
  61. #define DEV_NAME_STR_LEN 32
  62. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  63. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  64. #define WSA8810_NAME_1 "wsa881x.20170211"
  65. #define WSA8810_NAME_2 "wsa881x.20170212"
  66. #define WCN_CDC_SLIM_RX_CH_MAX 2
  67. #define WCN_CDC_SLIM_TX_CH_MAX 2
  68. #define WCN_CDC_SLIM_TX_CH_MAX_LITO 3
  69. enum {
  70. TDM_0 = 0,
  71. TDM_1,
  72. TDM_2,
  73. TDM_3,
  74. TDM_4,
  75. TDM_5,
  76. TDM_6,
  77. TDM_7,
  78. TDM_PORT_MAX,
  79. };
  80. enum {
  81. TDM_PRI = 0,
  82. TDM_SEC,
  83. TDM_TERT,
  84. TDM_QUAT,
  85. TDM_QUIN,
  86. TDM_SEN,
  87. TDM_INTERFACE_MAX,
  88. };
  89. enum {
  90. PRIM_AUX_PCM = 0,
  91. SEC_AUX_PCM,
  92. TERT_AUX_PCM,
  93. QUAT_AUX_PCM,
  94. QUIN_AUX_PCM,
  95. SEN_AUX_PCM,
  96. AUX_PCM_MAX,
  97. };
  98. enum {
  99. PRIM_MI2S = 0,
  100. SEC_MI2S,
  101. TERT_MI2S,
  102. QUAT_MI2S,
  103. QUIN_MI2S,
  104. SEN_MI2S,
  105. MI2S_MAX,
  106. };
  107. enum {
  108. WSA_CDC_DMA_RX_0 = 0,
  109. WSA_CDC_DMA_RX_1,
  110. RX_CDC_DMA_RX_0,
  111. RX_CDC_DMA_RX_1,
  112. RX_CDC_DMA_RX_2,
  113. RX_CDC_DMA_RX_3,
  114. RX_CDC_DMA_RX_5,
  115. CDC_DMA_RX_MAX,
  116. };
  117. enum {
  118. WSA_CDC_DMA_TX_0 = 0,
  119. WSA_CDC_DMA_TX_1,
  120. WSA_CDC_DMA_TX_2,
  121. TX_CDC_DMA_TX_0,
  122. TX_CDC_DMA_TX_3,
  123. TX_CDC_DMA_TX_4,
  124. VA_CDC_DMA_TX_0,
  125. VA_CDC_DMA_TX_1,
  126. VA_CDC_DMA_TX_2,
  127. CDC_DMA_TX_MAX,
  128. };
  129. enum {
  130. SLIM_RX_7 = 0,
  131. SLIM_RX_MAX,
  132. };
  133. enum {
  134. SLIM_TX_7 = 0,
  135. SLIM_TX_8,
  136. SLIM_TX_MAX,
  137. };
  138. enum {
  139. AFE_LOOPBACK_TX_IDX = 0,
  140. AFE_LOOPBACK_TX_IDX_MAX,
  141. };
  142. struct msm_asoc_mach_data {
  143. struct snd_info_entry *codec_root;
  144. int usbc_en2_gpio; /* used by gpio driver API */
  145. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  146. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  147. struct device_node *dmic45_gpio_p; /* used by pinctrl API */
  148. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  149. atomic_t mi2s_gpio_ref_count[MI2S_MAX]; /* used by pinctrl API */
  150. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  151. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  152. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  153. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  154. bool is_afe_config_done;
  155. struct device_node *fsa_handle;
  156. };
  157. struct tdm_port {
  158. u32 mode;
  159. u32 channel;
  160. };
  161. enum {
  162. EXT_DISP_RX_IDX_DP = 0,
  163. EXT_DISP_RX_IDX_DP1,
  164. EXT_DISP_RX_IDX_MAX,
  165. };
  166. struct msm_wsa881x_dev_info {
  167. struct device_node *of_node;
  168. u32 index;
  169. };
  170. struct aux_codec_dev_info {
  171. struct device_node *of_node;
  172. u32 index;
  173. };
  174. struct dev_config {
  175. u32 sample_rate;
  176. u32 bit_format;
  177. u32 channels;
  178. };
  179. /* Default configuration of slimbus channels */
  180. static struct dev_config slim_rx_cfg[] = {
  181. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  182. };
  183. static struct dev_config slim_tx_cfg[] = {
  184. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  185. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  186. };
  187. /* Default configuration of external display BE */
  188. static struct dev_config ext_disp_rx_cfg[] = {
  189. [EXT_DISP_RX_IDX_DP] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  190. [EXT_DISP_RX_IDX_DP1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  191. };
  192. static struct dev_config usb_rx_cfg = {
  193. .sample_rate = SAMPLING_RATE_48KHZ,
  194. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  195. .channels = 2,
  196. };
  197. static struct dev_config usb_tx_cfg = {
  198. .sample_rate = SAMPLING_RATE_48KHZ,
  199. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  200. .channels = 1,
  201. };
  202. static struct dev_config proxy_rx_cfg = {
  203. .sample_rate = SAMPLING_RATE_48KHZ,
  204. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  205. .channels = 2,
  206. };
  207. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  208. {
  209. AFE_API_VERSION_I2S_CONFIG,
  210. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  211. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  212. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  213. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  214. 0,
  215. },
  216. {
  217. AFE_API_VERSION_I2S_CONFIG,
  218. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  219. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  220. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  221. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  222. 0,
  223. },
  224. {
  225. AFE_API_VERSION_I2S_CONFIG,
  226. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  227. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  228. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  229. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  230. 0,
  231. },
  232. {
  233. AFE_API_VERSION_I2S_CONFIG,
  234. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  235. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  236. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  237. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  238. 0,
  239. },
  240. {
  241. AFE_API_VERSION_I2S_CONFIG,
  242. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  243. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  244. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  245. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  246. 0,
  247. },
  248. {
  249. AFE_API_VERSION_I2S_CONFIG,
  250. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  251. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  252. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  253. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  254. 0,
  255. },
  256. };
  257. struct mi2s_conf {
  258. struct mutex lock;
  259. u32 ref_cnt;
  260. u32 msm_is_mi2s_master;
  261. };
  262. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  263. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  264. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  265. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  266. };
  267. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  268. /* Default configuration of TDM channels */
  269. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  270. { /* PRI TDM */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  279. },
  280. { /* SEC TDM */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  289. },
  290. { /* TERT TDM */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  299. },
  300. { /* QUAT TDM */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  309. },
  310. { /* QUIN TDM */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  315. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  316. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  317. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  318. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  319. },
  320. { /* SEN TDM */
  321. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  322. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  323. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  324. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  325. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  326. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  327. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  328. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  329. },
  330. };
  331. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  332. { /* PRI TDM */
  333. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  334. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  335. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  336. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  337. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  338. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  339. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  340. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  341. },
  342. { /* SEC TDM */
  343. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  344. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  345. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  346. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  347. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  348. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  349. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  350. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  351. },
  352. { /* TERT TDM */
  353. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  354. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  355. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  356. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  357. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  358. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  359. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  360. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  361. },
  362. { /* QUAT TDM */
  363. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  364. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  365. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  366. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  367. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  368. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  369. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  370. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  371. },
  372. { /* QUIN TDM */
  373. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  374. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  375. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  376. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  377. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  378. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  379. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  380. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  381. },
  382. { /* SEN TDM */
  383. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  384. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  385. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  386. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  387. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  388. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  389. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  390. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  391. },
  392. };
  393. /* Default configuration of AUX PCM channels */
  394. static struct dev_config aux_pcm_rx_cfg[] = {
  395. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  399. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  400. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  401. };
  402. static struct dev_config aux_pcm_tx_cfg[] = {
  403. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  404. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  405. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  406. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  407. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  408. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  409. };
  410. /* Default configuration of MI2S channels */
  411. static struct dev_config mi2s_rx_cfg[] = {
  412. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  413. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  414. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  415. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  416. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  417. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  418. };
  419. static struct dev_config mi2s_tx_cfg[] = {
  420. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  421. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  422. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  423. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  424. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  425. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  426. };
  427. /* Default configuration of Codec DMA Interface RX */
  428. static struct dev_config cdc_dma_rx_cfg[] = {
  429. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  430. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  431. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  432. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  433. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  434. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  435. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  436. };
  437. /* Default configuration of Codec DMA Interface TX */
  438. static struct dev_config cdc_dma_tx_cfg[] = {
  439. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  440. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  441. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  442. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  443. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  444. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  445. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  446. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  447. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  448. };
  449. static struct dev_config afe_loopback_tx_cfg[] = {
  450. [AFE_LOOPBACK_TX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  451. };
  452. static int msm_vi_feed_tx_ch = 2;
  453. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  454. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  455. "S32_LE"};
  456. static char const *cdc80_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"};
  457. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  458. "Six", "Seven", "Eight"};
  459. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  460. "KHZ_16", "KHZ_22P05",
  461. "KHZ_32", "KHZ_44P1", "KHZ_48",
  462. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  463. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  464. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  465. "Five", "Six", "Seven",
  466. "Eight"};
  467. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  468. "KHZ_48", "KHZ_176P4",
  469. "KHZ_352P8"};
  470. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  471. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  472. "Five", "Six", "Seven", "Eight"};
  473. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  474. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  475. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  476. "KHZ_48", "KHZ_96", "KHZ_192"};
  477. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  478. "Five", "Six", "Seven",
  479. "Eight"};
  480. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  481. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  482. "Five", "Six", "Seven",
  483. "Eight"};
  484. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  485. "KHZ_16", "KHZ_22P05",
  486. "KHZ_32", "KHZ_44P1", "KHZ_48",
  487. "KHZ_88P2", "KHZ_96",
  488. "KHZ_176P4", "KHZ_192",
  489. "KHZ_352P8", "KHZ_384"};
  490. static char const *cdc80_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  491. "KHZ_16", "KHZ_22P05",
  492. "KHZ_32", "KHZ_44P1", "KHZ_48",
  493. "KHZ_88P2", "KHZ_96",
  494. "KHZ_176P4", "KHZ_192"};
  495. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
  496. "S24_3LE"};
  497. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  498. "KHZ_192", "KHZ_32", "KHZ_44P1",
  499. "KHZ_88P2", "KHZ_176P4"};
  500. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  501. "KHZ_44P1", "KHZ_48",
  502. "KHZ_88P2", "KHZ_96"};
  503. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  504. "KHZ_44P1", "KHZ_48",
  505. "KHZ_88P2", "KHZ_96"};
  506. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  507. "KHZ_44P1", "KHZ_48",
  508. "KHZ_88P2", "KHZ_96"};
  509. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  510. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  559. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  562. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  563. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  564. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  565. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  566. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  567. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  568. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  569. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  570. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  571. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  572. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  573. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  574. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  575. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  576. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  577. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  578. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  579. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  580. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  581. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  582. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  583. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  584. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  585. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  586. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  587. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  588. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  589. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  590. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  591. cdc_dma_sample_rate_text);
  592. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  593. cdc_dma_sample_rate_text);
  594. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  595. cdc_dma_sample_rate_text);
  596. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  597. cdc_dma_sample_rate_text);
  598. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  599. cdc_dma_sample_rate_text);
  600. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  601. cdc_dma_sample_rate_text);
  602. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  603. cdc_dma_sample_rate_text);
  604. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  605. cdc_dma_sample_rate_text);
  606. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  607. cdc_dma_sample_rate_text);
  608. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  609. cdc_dma_sample_rate_text);
  610. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  611. cdc_dma_sample_rate_text);
  612. /* WCD9380 */
  613. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_format, cdc80_bit_format_text);
  614. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_format, cdc80_bit_format_text);
  615. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_format, cdc80_bit_format_text);
  616. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_format, cdc80_bit_format_text);
  617. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_format, cdc80_bit_format_text);
  618. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_sample_rate,
  619. cdc80_dma_sample_rate_text);
  620. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_sample_rate,
  621. cdc80_dma_sample_rate_text);
  622. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_sample_rate,
  623. cdc80_dma_sample_rate_text);
  624. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_sample_rate,
  625. cdc80_dma_sample_rate_text);
  626. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_sample_rate,
  627. cdc80_dma_sample_rate_text);
  628. /* WCD9385 */
  629. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_format, bit_format_text);
  630. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_format, bit_format_text);
  631. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_format, bit_format_text);
  632. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_format, bit_format_text);
  633. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_format, bit_format_text);
  634. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_sample_rate,
  635. cdc_dma_sample_rate_text);
  636. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_sample_rate,
  637. cdc_dma_sample_rate_text);
  638. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_sample_rate,
  639. cdc_dma_sample_rate_text);
  640. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_sample_rate,
  641. cdc_dma_sample_rate_text);
  642. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_sample_rate,
  643. cdc_dma_sample_rate_text);
  644. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  645. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  646. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  647. ext_disp_sample_rate_text);
  648. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  649. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  650. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  651. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  652. static bool is_initial_boot;
  653. static bool codec_reg_done;
  654. static struct snd_soc_aux_dev *msm_aux_dev;
  655. static struct snd_soc_codec_conf *msm_codec_conf;
  656. static struct snd_soc_card snd_soc_card_kona_msm;
  657. static int dmic_0_1_gpio_cnt;
  658. static int dmic_2_3_gpio_cnt;
  659. static int dmic_4_5_gpio_cnt;
  660. static void *def_wcd_mbhc_cal(void);
  661. /*
  662. * Need to report LINEIN
  663. * if R/L channel impedance is larger than 5K ohm
  664. */
  665. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  666. .read_fw_bin = false,
  667. .calibration = NULL,
  668. .detect_extn_cable = true,
  669. .mono_stero_detection = false,
  670. .swap_gnd_mic = NULL,
  671. .hs_ext_micbias = true,
  672. .key_code[0] = KEY_MEDIA,
  673. .key_code[1] = KEY_VOICECOMMAND,
  674. .key_code[2] = KEY_VOLUMEUP,
  675. .key_code[3] = KEY_VOLUMEDOWN,
  676. .key_code[4] = 0,
  677. .key_code[5] = 0,
  678. .key_code[6] = 0,
  679. .key_code[7] = 0,
  680. .linein_th = 5000,
  681. .moisture_en = false,
  682. .mbhc_micbias = MIC_BIAS_2,
  683. .anc_micbias = MIC_BIAS_2,
  684. .enable_anc_mic_detect = false,
  685. .moisture_duty_cycle_en = true,
  686. };
  687. static inline int param_is_mask(int p)
  688. {
  689. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  690. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  691. }
  692. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  693. int n)
  694. {
  695. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  696. }
  697. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  698. unsigned int bit)
  699. {
  700. if (bit >= SNDRV_MASK_MAX)
  701. return;
  702. if (param_is_mask(n)) {
  703. struct snd_mask *m = param_to_mask(p, n);
  704. m->bits[0] = 0;
  705. m->bits[1] = 0;
  706. m->bits[bit >> 5] |= (1 << (bit & 31));
  707. }
  708. }
  709. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  710. struct snd_ctl_elem_value *ucontrol)
  711. {
  712. int sample_rate_val = 0;
  713. switch (usb_rx_cfg.sample_rate) {
  714. case SAMPLING_RATE_384KHZ:
  715. sample_rate_val = 12;
  716. break;
  717. case SAMPLING_RATE_352P8KHZ:
  718. sample_rate_val = 11;
  719. break;
  720. case SAMPLING_RATE_192KHZ:
  721. sample_rate_val = 10;
  722. break;
  723. case SAMPLING_RATE_176P4KHZ:
  724. sample_rate_val = 9;
  725. break;
  726. case SAMPLING_RATE_96KHZ:
  727. sample_rate_val = 8;
  728. break;
  729. case SAMPLING_RATE_88P2KHZ:
  730. sample_rate_val = 7;
  731. break;
  732. case SAMPLING_RATE_48KHZ:
  733. sample_rate_val = 6;
  734. break;
  735. case SAMPLING_RATE_44P1KHZ:
  736. sample_rate_val = 5;
  737. break;
  738. case SAMPLING_RATE_32KHZ:
  739. sample_rate_val = 4;
  740. break;
  741. case SAMPLING_RATE_22P05KHZ:
  742. sample_rate_val = 3;
  743. break;
  744. case SAMPLING_RATE_16KHZ:
  745. sample_rate_val = 2;
  746. break;
  747. case SAMPLING_RATE_11P025KHZ:
  748. sample_rate_val = 1;
  749. break;
  750. case SAMPLING_RATE_8KHZ:
  751. default:
  752. sample_rate_val = 0;
  753. break;
  754. }
  755. ucontrol->value.integer.value[0] = sample_rate_val;
  756. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  757. usb_rx_cfg.sample_rate);
  758. return 0;
  759. }
  760. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  761. struct snd_ctl_elem_value *ucontrol)
  762. {
  763. switch (ucontrol->value.integer.value[0]) {
  764. case 12:
  765. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  766. break;
  767. case 11:
  768. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  769. break;
  770. case 10:
  771. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  772. break;
  773. case 9:
  774. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  775. break;
  776. case 8:
  777. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  778. break;
  779. case 7:
  780. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  781. break;
  782. case 6:
  783. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  784. break;
  785. case 5:
  786. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  787. break;
  788. case 4:
  789. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  790. break;
  791. case 3:
  792. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  793. break;
  794. case 2:
  795. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  796. break;
  797. case 1:
  798. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  799. break;
  800. case 0:
  801. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  802. break;
  803. default:
  804. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  805. break;
  806. }
  807. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  808. __func__, ucontrol->value.integer.value[0],
  809. usb_rx_cfg.sample_rate);
  810. return 0;
  811. }
  812. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  813. struct snd_ctl_elem_value *ucontrol)
  814. {
  815. int sample_rate_val = 0;
  816. switch (usb_tx_cfg.sample_rate) {
  817. case SAMPLING_RATE_384KHZ:
  818. sample_rate_val = 12;
  819. break;
  820. case SAMPLING_RATE_352P8KHZ:
  821. sample_rate_val = 11;
  822. break;
  823. case SAMPLING_RATE_192KHZ:
  824. sample_rate_val = 10;
  825. break;
  826. case SAMPLING_RATE_176P4KHZ:
  827. sample_rate_val = 9;
  828. break;
  829. case SAMPLING_RATE_96KHZ:
  830. sample_rate_val = 8;
  831. break;
  832. case SAMPLING_RATE_88P2KHZ:
  833. sample_rate_val = 7;
  834. break;
  835. case SAMPLING_RATE_48KHZ:
  836. sample_rate_val = 6;
  837. break;
  838. case SAMPLING_RATE_44P1KHZ:
  839. sample_rate_val = 5;
  840. break;
  841. case SAMPLING_RATE_32KHZ:
  842. sample_rate_val = 4;
  843. break;
  844. case SAMPLING_RATE_22P05KHZ:
  845. sample_rate_val = 3;
  846. break;
  847. case SAMPLING_RATE_16KHZ:
  848. sample_rate_val = 2;
  849. break;
  850. case SAMPLING_RATE_11P025KHZ:
  851. sample_rate_val = 1;
  852. break;
  853. case SAMPLING_RATE_8KHZ:
  854. sample_rate_val = 0;
  855. break;
  856. default:
  857. sample_rate_val = 6;
  858. break;
  859. }
  860. ucontrol->value.integer.value[0] = sample_rate_val;
  861. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  862. usb_tx_cfg.sample_rate);
  863. return 0;
  864. }
  865. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  866. struct snd_ctl_elem_value *ucontrol)
  867. {
  868. switch (ucontrol->value.integer.value[0]) {
  869. case 12:
  870. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  871. break;
  872. case 11:
  873. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  874. break;
  875. case 10:
  876. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  877. break;
  878. case 9:
  879. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  880. break;
  881. case 8:
  882. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  883. break;
  884. case 7:
  885. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  886. break;
  887. case 6:
  888. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  889. break;
  890. case 5:
  891. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  892. break;
  893. case 4:
  894. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  895. break;
  896. case 3:
  897. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  898. break;
  899. case 2:
  900. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  901. break;
  902. case 1:
  903. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  904. break;
  905. case 0:
  906. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  907. break;
  908. default:
  909. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  910. break;
  911. }
  912. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  913. __func__, ucontrol->value.integer.value[0],
  914. usb_tx_cfg.sample_rate);
  915. return 0;
  916. }
  917. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  918. struct snd_ctl_elem_value *ucontrol)
  919. {
  920. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  921. afe_loopback_tx_cfg[0].channels);
  922. ucontrol->value.enumerated.item[0] =
  923. afe_loopback_tx_cfg[0].channels - 1;
  924. return 0;
  925. }
  926. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  927. struct snd_ctl_elem_value *ucontrol)
  928. {
  929. afe_loopback_tx_cfg[0].channels =
  930. ucontrol->value.enumerated.item[0] + 1;
  931. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  932. afe_loopback_tx_cfg[0].channels);
  933. return 1;
  934. }
  935. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  936. struct snd_ctl_elem_value *ucontrol)
  937. {
  938. switch (usb_rx_cfg.bit_format) {
  939. case SNDRV_PCM_FORMAT_S32_LE:
  940. ucontrol->value.integer.value[0] = 3;
  941. break;
  942. case SNDRV_PCM_FORMAT_S24_3LE:
  943. ucontrol->value.integer.value[0] = 2;
  944. break;
  945. case SNDRV_PCM_FORMAT_S24_LE:
  946. ucontrol->value.integer.value[0] = 1;
  947. break;
  948. case SNDRV_PCM_FORMAT_S16_LE:
  949. default:
  950. ucontrol->value.integer.value[0] = 0;
  951. break;
  952. }
  953. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  954. __func__, usb_rx_cfg.bit_format,
  955. ucontrol->value.integer.value[0]);
  956. return 0;
  957. }
  958. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  959. struct snd_ctl_elem_value *ucontrol)
  960. {
  961. int rc = 0;
  962. switch (ucontrol->value.integer.value[0]) {
  963. case 3:
  964. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  965. break;
  966. case 2:
  967. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  968. break;
  969. case 1:
  970. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  971. break;
  972. case 0:
  973. default:
  974. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  975. break;
  976. }
  977. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  978. __func__, usb_rx_cfg.bit_format,
  979. ucontrol->value.integer.value[0]);
  980. return rc;
  981. }
  982. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  983. struct snd_ctl_elem_value *ucontrol)
  984. {
  985. switch (usb_tx_cfg.bit_format) {
  986. case SNDRV_PCM_FORMAT_S32_LE:
  987. ucontrol->value.integer.value[0] = 3;
  988. break;
  989. case SNDRV_PCM_FORMAT_S24_3LE:
  990. ucontrol->value.integer.value[0] = 2;
  991. break;
  992. case SNDRV_PCM_FORMAT_S24_LE:
  993. ucontrol->value.integer.value[0] = 1;
  994. break;
  995. case SNDRV_PCM_FORMAT_S16_LE:
  996. default:
  997. ucontrol->value.integer.value[0] = 0;
  998. break;
  999. }
  1000. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1001. __func__, usb_tx_cfg.bit_format,
  1002. ucontrol->value.integer.value[0]);
  1003. return 0;
  1004. }
  1005. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1006. struct snd_ctl_elem_value *ucontrol)
  1007. {
  1008. int rc = 0;
  1009. switch (ucontrol->value.integer.value[0]) {
  1010. case 3:
  1011. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1012. break;
  1013. case 2:
  1014. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1015. break;
  1016. case 1:
  1017. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1018. break;
  1019. case 0:
  1020. default:
  1021. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1022. break;
  1023. }
  1024. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1025. __func__, usb_tx_cfg.bit_format,
  1026. ucontrol->value.integer.value[0]);
  1027. return rc;
  1028. }
  1029. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1030. struct snd_ctl_elem_value *ucontrol)
  1031. {
  1032. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1033. usb_rx_cfg.channels);
  1034. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1035. return 0;
  1036. }
  1037. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1038. struct snd_ctl_elem_value *ucontrol)
  1039. {
  1040. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1041. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1042. return 1;
  1043. }
  1044. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1045. struct snd_ctl_elem_value *ucontrol)
  1046. {
  1047. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1048. usb_tx_cfg.channels);
  1049. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1050. return 0;
  1051. }
  1052. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1053. struct snd_ctl_elem_value *ucontrol)
  1054. {
  1055. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1056. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1057. return 1;
  1058. }
  1059. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  1060. struct snd_ctl_elem_value *ucontrol)
  1061. {
  1062. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  1063. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  1064. ucontrol->value.integer.value[0]);
  1065. return 0;
  1066. }
  1067. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1068. struct snd_ctl_elem_value *ucontrol)
  1069. {
  1070. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1071. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1072. return 1;
  1073. }
  1074. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  1075. {
  1076. int idx = 0;
  1077. if (strnstr(kcontrol->id.name, "Display Port RX",
  1078. sizeof("Display Port RX"))) {
  1079. idx = EXT_DISP_RX_IDX_DP;
  1080. } else if (strnstr(kcontrol->id.name, "Display Port1 RX",
  1081. sizeof("Display Port1 RX"))) {
  1082. idx = EXT_DISP_RX_IDX_DP1;
  1083. } else {
  1084. pr_err("%s: unsupported BE: %s\n",
  1085. __func__, kcontrol->id.name);
  1086. idx = -EINVAL;
  1087. }
  1088. return idx;
  1089. }
  1090. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  1091. struct snd_ctl_elem_value *ucontrol)
  1092. {
  1093. int idx = ext_disp_get_port_idx(kcontrol);
  1094. if (idx < 0)
  1095. return idx;
  1096. switch (ext_disp_rx_cfg[idx].bit_format) {
  1097. case SNDRV_PCM_FORMAT_S24_3LE:
  1098. ucontrol->value.integer.value[0] = 2;
  1099. break;
  1100. case SNDRV_PCM_FORMAT_S24_LE:
  1101. ucontrol->value.integer.value[0] = 1;
  1102. break;
  1103. case SNDRV_PCM_FORMAT_S16_LE:
  1104. default:
  1105. ucontrol->value.integer.value[0] = 0;
  1106. break;
  1107. }
  1108. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1109. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1110. ucontrol->value.integer.value[0]);
  1111. return 0;
  1112. }
  1113. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  1114. struct snd_ctl_elem_value *ucontrol)
  1115. {
  1116. int idx = ext_disp_get_port_idx(kcontrol);
  1117. if (idx < 0)
  1118. return idx;
  1119. switch (ucontrol->value.integer.value[0]) {
  1120. case 2:
  1121. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1122. break;
  1123. case 1:
  1124. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1125. break;
  1126. case 0:
  1127. default:
  1128. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1129. break;
  1130. }
  1131. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1132. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1133. ucontrol->value.integer.value[0]);
  1134. return 0;
  1135. }
  1136. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  1137. struct snd_ctl_elem_value *ucontrol)
  1138. {
  1139. int idx = ext_disp_get_port_idx(kcontrol);
  1140. if (idx < 0)
  1141. return idx;
  1142. ucontrol->value.integer.value[0] =
  1143. ext_disp_rx_cfg[idx].channels - 2;
  1144. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1145. idx, ext_disp_rx_cfg[idx].channels);
  1146. return 0;
  1147. }
  1148. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  1149. struct snd_ctl_elem_value *ucontrol)
  1150. {
  1151. int idx = ext_disp_get_port_idx(kcontrol);
  1152. if (idx < 0)
  1153. return idx;
  1154. ext_disp_rx_cfg[idx].channels =
  1155. ucontrol->value.integer.value[0] + 2;
  1156. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1157. idx, ext_disp_rx_cfg[idx].channels);
  1158. return 1;
  1159. }
  1160. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1161. struct snd_ctl_elem_value *ucontrol)
  1162. {
  1163. int sample_rate_val;
  1164. int idx = ext_disp_get_port_idx(kcontrol);
  1165. if (idx < 0)
  1166. return idx;
  1167. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1168. case SAMPLING_RATE_176P4KHZ:
  1169. sample_rate_val = 6;
  1170. break;
  1171. case SAMPLING_RATE_88P2KHZ:
  1172. sample_rate_val = 5;
  1173. break;
  1174. case SAMPLING_RATE_44P1KHZ:
  1175. sample_rate_val = 4;
  1176. break;
  1177. case SAMPLING_RATE_32KHZ:
  1178. sample_rate_val = 3;
  1179. break;
  1180. case SAMPLING_RATE_192KHZ:
  1181. sample_rate_val = 2;
  1182. break;
  1183. case SAMPLING_RATE_96KHZ:
  1184. sample_rate_val = 1;
  1185. break;
  1186. case SAMPLING_RATE_48KHZ:
  1187. default:
  1188. sample_rate_val = 0;
  1189. break;
  1190. }
  1191. ucontrol->value.integer.value[0] = sample_rate_val;
  1192. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1193. idx, ext_disp_rx_cfg[idx].sample_rate);
  1194. return 0;
  1195. }
  1196. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1197. struct snd_ctl_elem_value *ucontrol)
  1198. {
  1199. int idx = ext_disp_get_port_idx(kcontrol);
  1200. if (idx < 0)
  1201. return idx;
  1202. switch (ucontrol->value.integer.value[0]) {
  1203. case 6:
  1204. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
  1205. break;
  1206. case 5:
  1207. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
  1208. break;
  1209. case 4:
  1210. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
  1211. break;
  1212. case 3:
  1213. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
  1214. break;
  1215. case 2:
  1216. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1217. break;
  1218. case 1:
  1219. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1220. break;
  1221. case 0:
  1222. default:
  1223. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1224. break;
  1225. }
  1226. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1227. __func__, ucontrol->value.integer.value[0], idx,
  1228. ext_disp_rx_cfg[idx].sample_rate);
  1229. return 0;
  1230. }
  1231. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1232. struct snd_ctl_elem_value *ucontrol)
  1233. {
  1234. pr_debug("%s: proxy_rx channels = %d\n",
  1235. __func__, proxy_rx_cfg.channels);
  1236. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1237. return 0;
  1238. }
  1239. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1240. struct snd_ctl_elem_value *ucontrol)
  1241. {
  1242. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1243. pr_debug("%s: proxy_rx channels = %d\n",
  1244. __func__, proxy_rx_cfg.channels);
  1245. return 1;
  1246. }
  1247. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1248. struct tdm_port *port)
  1249. {
  1250. if (port) {
  1251. if (strnstr(kcontrol->id.name, "PRI",
  1252. sizeof(kcontrol->id.name))) {
  1253. port->mode = TDM_PRI;
  1254. } else if (strnstr(kcontrol->id.name, "SEC",
  1255. sizeof(kcontrol->id.name))) {
  1256. port->mode = TDM_SEC;
  1257. } else if (strnstr(kcontrol->id.name, "TERT",
  1258. sizeof(kcontrol->id.name))) {
  1259. port->mode = TDM_TERT;
  1260. } else if (strnstr(kcontrol->id.name, "QUAT",
  1261. sizeof(kcontrol->id.name))) {
  1262. port->mode = TDM_QUAT;
  1263. } else if (strnstr(kcontrol->id.name, "QUIN",
  1264. sizeof(kcontrol->id.name))) {
  1265. port->mode = TDM_QUIN;
  1266. } else if (strnstr(kcontrol->id.name, "SEN",
  1267. sizeof(kcontrol->id.name))) {
  1268. port->mode = TDM_SEN;
  1269. } else {
  1270. pr_err("%s: unsupported mode in: %s\n",
  1271. __func__, kcontrol->id.name);
  1272. return -EINVAL;
  1273. }
  1274. if (strnstr(kcontrol->id.name, "RX_0",
  1275. sizeof(kcontrol->id.name)) ||
  1276. strnstr(kcontrol->id.name, "TX_0",
  1277. sizeof(kcontrol->id.name))) {
  1278. port->channel = TDM_0;
  1279. } else if (strnstr(kcontrol->id.name, "RX_1",
  1280. sizeof(kcontrol->id.name)) ||
  1281. strnstr(kcontrol->id.name, "TX_1",
  1282. sizeof(kcontrol->id.name))) {
  1283. port->channel = TDM_1;
  1284. } else if (strnstr(kcontrol->id.name, "RX_2",
  1285. sizeof(kcontrol->id.name)) ||
  1286. strnstr(kcontrol->id.name, "TX_2",
  1287. sizeof(kcontrol->id.name))) {
  1288. port->channel = TDM_2;
  1289. } else if (strnstr(kcontrol->id.name, "RX_3",
  1290. sizeof(kcontrol->id.name)) ||
  1291. strnstr(kcontrol->id.name, "TX_3",
  1292. sizeof(kcontrol->id.name))) {
  1293. port->channel = TDM_3;
  1294. } else if (strnstr(kcontrol->id.name, "RX_4",
  1295. sizeof(kcontrol->id.name)) ||
  1296. strnstr(kcontrol->id.name, "TX_4",
  1297. sizeof(kcontrol->id.name))) {
  1298. port->channel = TDM_4;
  1299. } else if (strnstr(kcontrol->id.name, "RX_5",
  1300. sizeof(kcontrol->id.name)) ||
  1301. strnstr(kcontrol->id.name, "TX_5",
  1302. sizeof(kcontrol->id.name))) {
  1303. port->channel = TDM_5;
  1304. } else if (strnstr(kcontrol->id.name, "RX_6",
  1305. sizeof(kcontrol->id.name)) ||
  1306. strnstr(kcontrol->id.name, "TX_6",
  1307. sizeof(kcontrol->id.name))) {
  1308. port->channel = TDM_6;
  1309. } else if (strnstr(kcontrol->id.name, "RX_7",
  1310. sizeof(kcontrol->id.name)) ||
  1311. strnstr(kcontrol->id.name, "TX_7",
  1312. sizeof(kcontrol->id.name))) {
  1313. port->channel = TDM_7;
  1314. } else {
  1315. pr_err("%s: unsupported channel in: %s\n",
  1316. __func__, kcontrol->id.name);
  1317. return -EINVAL;
  1318. }
  1319. } else {
  1320. return -EINVAL;
  1321. }
  1322. return 0;
  1323. }
  1324. static int tdm_get_sample_rate(int value)
  1325. {
  1326. int sample_rate = 0;
  1327. switch (value) {
  1328. case 0:
  1329. sample_rate = SAMPLING_RATE_8KHZ;
  1330. break;
  1331. case 1:
  1332. sample_rate = SAMPLING_RATE_16KHZ;
  1333. break;
  1334. case 2:
  1335. sample_rate = SAMPLING_RATE_32KHZ;
  1336. break;
  1337. case 3:
  1338. sample_rate = SAMPLING_RATE_48KHZ;
  1339. break;
  1340. case 4:
  1341. sample_rate = SAMPLING_RATE_176P4KHZ;
  1342. break;
  1343. case 5:
  1344. sample_rate = SAMPLING_RATE_352P8KHZ;
  1345. break;
  1346. default:
  1347. sample_rate = SAMPLING_RATE_48KHZ;
  1348. break;
  1349. }
  1350. return sample_rate;
  1351. }
  1352. static int tdm_get_sample_rate_val(int sample_rate)
  1353. {
  1354. int sample_rate_val = 0;
  1355. switch (sample_rate) {
  1356. case SAMPLING_RATE_8KHZ:
  1357. sample_rate_val = 0;
  1358. break;
  1359. case SAMPLING_RATE_16KHZ:
  1360. sample_rate_val = 1;
  1361. break;
  1362. case SAMPLING_RATE_32KHZ:
  1363. sample_rate_val = 2;
  1364. break;
  1365. case SAMPLING_RATE_48KHZ:
  1366. sample_rate_val = 3;
  1367. break;
  1368. case SAMPLING_RATE_176P4KHZ:
  1369. sample_rate_val = 4;
  1370. break;
  1371. case SAMPLING_RATE_352P8KHZ:
  1372. sample_rate_val = 5;
  1373. break;
  1374. default:
  1375. sample_rate_val = 3;
  1376. break;
  1377. }
  1378. return sample_rate_val;
  1379. }
  1380. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1381. struct snd_ctl_elem_value *ucontrol)
  1382. {
  1383. struct tdm_port port;
  1384. int ret = tdm_get_port_idx(kcontrol, &port);
  1385. if (ret) {
  1386. pr_err("%s: unsupported control: %s\n",
  1387. __func__, kcontrol->id.name);
  1388. } else {
  1389. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1390. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1391. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1392. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1393. ucontrol->value.enumerated.item[0]);
  1394. }
  1395. return ret;
  1396. }
  1397. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1398. struct snd_ctl_elem_value *ucontrol)
  1399. {
  1400. struct tdm_port port;
  1401. int ret = tdm_get_port_idx(kcontrol, &port);
  1402. if (ret) {
  1403. pr_err("%s: unsupported control: %s\n",
  1404. __func__, kcontrol->id.name);
  1405. } else {
  1406. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1407. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1408. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1409. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1410. ucontrol->value.enumerated.item[0]);
  1411. }
  1412. return ret;
  1413. }
  1414. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1415. struct snd_ctl_elem_value *ucontrol)
  1416. {
  1417. struct tdm_port port;
  1418. int ret = tdm_get_port_idx(kcontrol, &port);
  1419. if (ret) {
  1420. pr_err("%s: unsupported control: %s\n",
  1421. __func__, kcontrol->id.name);
  1422. } else {
  1423. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1424. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1425. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1426. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1427. ucontrol->value.enumerated.item[0]);
  1428. }
  1429. return ret;
  1430. }
  1431. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1432. struct snd_ctl_elem_value *ucontrol)
  1433. {
  1434. struct tdm_port port;
  1435. int ret = tdm_get_port_idx(kcontrol, &port);
  1436. if (ret) {
  1437. pr_err("%s: unsupported control: %s\n",
  1438. __func__, kcontrol->id.name);
  1439. } else {
  1440. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1441. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1442. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1443. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1444. ucontrol->value.enumerated.item[0]);
  1445. }
  1446. return ret;
  1447. }
  1448. static int tdm_get_format(int value)
  1449. {
  1450. int format = 0;
  1451. switch (value) {
  1452. case 0:
  1453. format = SNDRV_PCM_FORMAT_S16_LE;
  1454. break;
  1455. case 1:
  1456. format = SNDRV_PCM_FORMAT_S24_LE;
  1457. break;
  1458. case 2:
  1459. format = SNDRV_PCM_FORMAT_S32_LE;
  1460. break;
  1461. default:
  1462. format = SNDRV_PCM_FORMAT_S16_LE;
  1463. break;
  1464. }
  1465. return format;
  1466. }
  1467. static int tdm_get_format_val(int format)
  1468. {
  1469. int value = 0;
  1470. switch (format) {
  1471. case SNDRV_PCM_FORMAT_S16_LE:
  1472. value = 0;
  1473. break;
  1474. case SNDRV_PCM_FORMAT_S24_LE:
  1475. value = 1;
  1476. break;
  1477. case SNDRV_PCM_FORMAT_S32_LE:
  1478. value = 2;
  1479. break;
  1480. default:
  1481. value = 0;
  1482. break;
  1483. }
  1484. return value;
  1485. }
  1486. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1487. struct snd_ctl_elem_value *ucontrol)
  1488. {
  1489. struct tdm_port port;
  1490. int ret = tdm_get_port_idx(kcontrol, &port);
  1491. if (ret) {
  1492. pr_err("%s: unsupported control: %s\n",
  1493. __func__, kcontrol->id.name);
  1494. } else {
  1495. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1496. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1497. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1498. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1499. ucontrol->value.enumerated.item[0]);
  1500. }
  1501. return ret;
  1502. }
  1503. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1504. struct snd_ctl_elem_value *ucontrol)
  1505. {
  1506. struct tdm_port port;
  1507. int ret = tdm_get_port_idx(kcontrol, &port);
  1508. if (ret) {
  1509. pr_err("%s: unsupported control: %s\n",
  1510. __func__, kcontrol->id.name);
  1511. } else {
  1512. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1513. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1514. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1515. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1516. ucontrol->value.enumerated.item[0]);
  1517. }
  1518. return ret;
  1519. }
  1520. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1521. struct snd_ctl_elem_value *ucontrol)
  1522. {
  1523. struct tdm_port port;
  1524. int ret = tdm_get_port_idx(kcontrol, &port);
  1525. if (ret) {
  1526. pr_err("%s: unsupported control: %s\n",
  1527. __func__, kcontrol->id.name);
  1528. } else {
  1529. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1530. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1531. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1532. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1533. ucontrol->value.enumerated.item[0]);
  1534. }
  1535. return ret;
  1536. }
  1537. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1538. struct snd_ctl_elem_value *ucontrol)
  1539. {
  1540. struct tdm_port port;
  1541. int ret = tdm_get_port_idx(kcontrol, &port);
  1542. if (ret) {
  1543. pr_err("%s: unsupported control: %s\n",
  1544. __func__, kcontrol->id.name);
  1545. } else {
  1546. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1547. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1548. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1549. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1550. ucontrol->value.enumerated.item[0]);
  1551. }
  1552. return ret;
  1553. }
  1554. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1555. struct snd_ctl_elem_value *ucontrol)
  1556. {
  1557. struct tdm_port port;
  1558. int ret = tdm_get_port_idx(kcontrol, &port);
  1559. if (ret) {
  1560. pr_err("%s: unsupported control: %s\n",
  1561. __func__, kcontrol->id.name);
  1562. } else {
  1563. ucontrol->value.enumerated.item[0] =
  1564. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1565. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1566. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1567. ucontrol->value.enumerated.item[0]);
  1568. }
  1569. return ret;
  1570. }
  1571. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1572. struct snd_ctl_elem_value *ucontrol)
  1573. {
  1574. struct tdm_port port;
  1575. int ret = tdm_get_port_idx(kcontrol, &port);
  1576. if (ret) {
  1577. pr_err("%s: unsupported control: %s\n",
  1578. __func__, kcontrol->id.name);
  1579. } else {
  1580. tdm_rx_cfg[port.mode][port.channel].channels =
  1581. ucontrol->value.enumerated.item[0] + 1;
  1582. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1583. tdm_rx_cfg[port.mode][port.channel].channels,
  1584. ucontrol->value.enumerated.item[0] + 1);
  1585. }
  1586. return ret;
  1587. }
  1588. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1589. struct snd_ctl_elem_value *ucontrol)
  1590. {
  1591. struct tdm_port port;
  1592. int ret = tdm_get_port_idx(kcontrol, &port);
  1593. if (ret) {
  1594. pr_err("%s: unsupported control: %s\n",
  1595. __func__, kcontrol->id.name);
  1596. } else {
  1597. ucontrol->value.enumerated.item[0] =
  1598. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1599. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1600. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1601. ucontrol->value.enumerated.item[0]);
  1602. }
  1603. return ret;
  1604. }
  1605. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1606. struct snd_ctl_elem_value *ucontrol)
  1607. {
  1608. struct tdm_port port;
  1609. int ret = tdm_get_port_idx(kcontrol, &port);
  1610. if (ret) {
  1611. pr_err("%s: unsupported control: %s\n",
  1612. __func__, kcontrol->id.name);
  1613. } else {
  1614. tdm_tx_cfg[port.mode][port.channel].channels =
  1615. ucontrol->value.enumerated.item[0] + 1;
  1616. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1617. tdm_tx_cfg[port.mode][port.channel].channels,
  1618. ucontrol->value.enumerated.item[0] + 1);
  1619. }
  1620. return ret;
  1621. }
  1622. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1623. {
  1624. int idx = 0;
  1625. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1626. sizeof("PRIM_AUX_PCM"))) {
  1627. idx = PRIM_AUX_PCM;
  1628. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1629. sizeof("SEC_AUX_PCM"))) {
  1630. idx = SEC_AUX_PCM;
  1631. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1632. sizeof("TERT_AUX_PCM"))) {
  1633. idx = TERT_AUX_PCM;
  1634. } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  1635. sizeof("QUAT_AUX_PCM"))) {
  1636. idx = QUAT_AUX_PCM;
  1637. } else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  1638. sizeof("QUIN_AUX_PCM"))) {
  1639. idx = QUIN_AUX_PCM;
  1640. } else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  1641. sizeof("SEN_AUX_PCM"))) {
  1642. idx = SEN_AUX_PCM;
  1643. } else {
  1644. pr_err("%s: unsupported port: %s\n",
  1645. __func__, kcontrol->id.name);
  1646. idx = -EINVAL;
  1647. }
  1648. return idx;
  1649. }
  1650. static int aux_pcm_get_sample_rate(int value)
  1651. {
  1652. int sample_rate = 0;
  1653. switch (value) {
  1654. case 1:
  1655. sample_rate = SAMPLING_RATE_16KHZ;
  1656. break;
  1657. case 0:
  1658. default:
  1659. sample_rate = SAMPLING_RATE_8KHZ;
  1660. break;
  1661. }
  1662. return sample_rate;
  1663. }
  1664. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1665. {
  1666. int sample_rate_val = 0;
  1667. switch (sample_rate) {
  1668. case SAMPLING_RATE_16KHZ:
  1669. sample_rate_val = 1;
  1670. break;
  1671. case SAMPLING_RATE_8KHZ:
  1672. default:
  1673. sample_rate_val = 0;
  1674. break;
  1675. }
  1676. return sample_rate_val;
  1677. }
  1678. static int mi2s_auxpcm_get_format(int value)
  1679. {
  1680. int format = 0;
  1681. switch (value) {
  1682. case 0:
  1683. format = SNDRV_PCM_FORMAT_S16_LE;
  1684. break;
  1685. case 1:
  1686. format = SNDRV_PCM_FORMAT_S24_LE;
  1687. break;
  1688. case 2:
  1689. format = SNDRV_PCM_FORMAT_S24_3LE;
  1690. break;
  1691. case 3:
  1692. format = SNDRV_PCM_FORMAT_S32_LE;
  1693. break;
  1694. default:
  1695. format = SNDRV_PCM_FORMAT_S16_LE;
  1696. break;
  1697. }
  1698. return format;
  1699. }
  1700. static int mi2s_auxpcm_get_format_value(int format)
  1701. {
  1702. int value = 0;
  1703. switch (format) {
  1704. case SNDRV_PCM_FORMAT_S16_LE:
  1705. value = 0;
  1706. break;
  1707. case SNDRV_PCM_FORMAT_S24_LE:
  1708. value = 1;
  1709. break;
  1710. case SNDRV_PCM_FORMAT_S24_3LE:
  1711. value = 2;
  1712. break;
  1713. case SNDRV_PCM_FORMAT_S32_LE:
  1714. value = 3;
  1715. break;
  1716. default:
  1717. value = 0;
  1718. break;
  1719. }
  1720. return value;
  1721. }
  1722. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1723. struct snd_ctl_elem_value *ucontrol)
  1724. {
  1725. int idx = aux_pcm_get_port_idx(kcontrol);
  1726. if (idx < 0)
  1727. return idx;
  1728. ucontrol->value.enumerated.item[0] =
  1729. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1730. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1731. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1732. ucontrol->value.enumerated.item[0]);
  1733. return 0;
  1734. }
  1735. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1736. struct snd_ctl_elem_value *ucontrol)
  1737. {
  1738. int idx = aux_pcm_get_port_idx(kcontrol);
  1739. if (idx < 0)
  1740. return idx;
  1741. aux_pcm_rx_cfg[idx].sample_rate =
  1742. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1743. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1744. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1745. ucontrol->value.enumerated.item[0]);
  1746. return 0;
  1747. }
  1748. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1749. struct snd_ctl_elem_value *ucontrol)
  1750. {
  1751. int idx = aux_pcm_get_port_idx(kcontrol);
  1752. if (idx < 0)
  1753. return idx;
  1754. ucontrol->value.enumerated.item[0] =
  1755. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1756. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1757. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1758. ucontrol->value.enumerated.item[0]);
  1759. return 0;
  1760. }
  1761. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1762. struct snd_ctl_elem_value *ucontrol)
  1763. {
  1764. int idx = aux_pcm_get_port_idx(kcontrol);
  1765. if (idx < 0)
  1766. return idx;
  1767. aux_pcm_tx_cfg[idx].sample_rate =
  1768. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1769. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1770. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1771. ucontrol->value.enumerated.item[0]);
  1772. return 0;
  1773. }
  1774. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1775. struct snd_ctl_elem_value *ucontrol)
  1776. {
  1777. int idx = aux_pcm_get_port_idx(kcontrol);
  1778. if (idx < 0)
  1779. return idx;
  1780. ucontrol->value.enumerated.item[0] =
  1781. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1782. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1783. idx, aux_pcm_rx_cfg[idx].bit_format,
  1784. ucontrol->value.enumerated.item[0]);
  1785. return 0;
  1786. }
  1787. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1788. struct snd_ctl_elem_value *ucontrol)
  1789. {
  1790. int idx = aux_pcm_get_port_idx(kcontrol);
  1791. if (idx < 0)
  1792. return idx;
  1793. aux_pcm_rx_cfg[idx].bit_format =
  1794. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1795. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1796. idx, aux_pcm_rx_cfg[idx].bit_format,
  1797. ucontrol->value.enumerated.item[0]);
  1798. return 0;
  1799. }
  1800. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1801. struct snd_ctl_elem_value *ucontrol)
  1802. {
  1803. int idx = aux_pcm_get_port_idx(kcontrol);
  1804. if (idx < 0)
  1805. return idx;
  1806. ucontrol->value.enumerated.item[0] =
  1807. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1808. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1809. idx, aux_pcm_tx_cfg[idx].bit_format,
  1810. ucontrol->value.enumerated.item[0]);
  1811. return 0;
  1812. }
  1813. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1814. struct snd_ctl_elem_value *ucontrol)
  1815. {
  1816. int idx = aux_pcm_get_port_idx(kcontrol);
  1817. if (idx < 0)
  1818. return idx;
  1819. aux_pcm_tx_cfg[idx].bit_format =
  1820. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1821. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1822. idx, aux_pcm_tx_cfg[idx].bit_format,
  1823. ucontrol->value.enumerated.item[0]);
  1824. return 0;
  1825. }
  1826. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  1827. {
  1828. int idx = 0;
  1829. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  1830. sizeof("PRIM_MI2S_RX"))) {
  1831. idx = PRIM_MI2S;
  1832. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  1833. sizeof("SEC_MI2S_RX"))) {
  1834. idx = SEC_MI2S;
  1835. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  1836. sizeof("TERT_MI2S_RX"))) {
  1837. idx = TERT_MI2S;
  1838. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  1839. sizeof("QUAT_MI2S_RX"))) {
  1840. idx = QUAT_MI2S;
  1841. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  1842. sizeof("QUIN_MI2S_RX"))) {
  1843. idx = QUIN_MI2S;
  1844. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  1845. sizeof("SEN_MI2S_RX"))) {
  1846. idx = SEN_MI2S;
  1847. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1848. sizeof("PRIM_MI2S_TX"))) {
  1849. idx = PRIM_MI2S;
  1850. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1851. sizeof("SEC_MI2S_TX"))) {
  1852. idx = SEC_MI2S;
  1853. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1854. sizeof("TERT_MI2S_TX"))) {
  1855. idx = TERT_MI2S;
  1856. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1857. sizeof("QUAT_MI2S_TX"))) {
  1858. idx = QUAT_MI2S;
  1859. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  1860. sizeof("QUIN_MI2S_TX"))) {
  1861. idx = QUIN_MI2S;
  1862. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  1863. sizeof("SEN_MI2S_TX"))) {
  1864. idx = SEN_MI2S;
  1865. } else {
  1866. pr_err("%s: unsupported channel: %s\n",
  1867. __func__, kcontrol->id.name);
  1868. idx = -EINVAL;
  1869. }
  1870. return idx;
  1871. }
  1872. static int mi2s_get_sample_rate(int value)
  1873. {
  1874. int sample_rate = 0;
  1875. switch (value) {
  1876. case 0:
  1877. sample_rate = SAMPLING_RATE_8KHZ;
  1878. break;
  1879. case 1:
  1880. sample_rate = SAMPLING_RATE_11P025KHZ;
  1881. break;
  1882. case 2:
  1883. sample_rate = SAMPLING_RATE_16KHZ;
  1884. break;
  1885. case 3:
  1886. sample_rate = SAMPLING_RATE_22P05KHZ;
  1887. break;
  1888. case 4:
  1889. sample_rate = SAMPLING_RATE_32KHZ;
  1890. break;
  1891. case 5:
  1892. sample_rate = SAMPLING_RATE_44P1KHZ;
  1893. break;
  1894. case 6:
  1895. sample_rate = SAMPLING_RATE_48KHZ;
  1896. break;
  1897. case 7:
  1898. sample_rate = SAMPLING_RATE_96KHZ;
  1899. break;
  1900. case 8:
  1901. sample_rate = SAMPLING_RATE_192KHZ;
  1902. break;
  1903. default:
  1904. sample_rate = SAMPLING_RATE_48KHZ;
  1905. break;
  1906. }
  1907. return sample_rate;
  1908. }
  1909. static int mi2s_get_sample_rate_val(int sample_rate)
  1910. {
  1911. int sample_rate_val = 0;
  1912. switch (sample_rate) {
  1913. case SAMPLING_RATE_8KHZ:
  1914. sample_rate_val = 0;
  1915. break;
  1916. case SAMPLING_RATE_11P025KHZ:
  1917. sample_rate_val = 1;
  1918. break;
  1919. case SAMPLING_RATE_16KHZ:
  1920. sample_rate_val = 2;
  1921. break;
  1922. case SAMPLING_RATE_22P05KHZ:
  1923. sample_rate_val = 3;
  1924. break;
  1925. case SAMPLING_RATE_32KHZ:
  1926. sample_rate_val = 4;
  1927. break;
  1928. case SAMPLING_RATE_44P1KHZ:
  1929. sample_rate_val = 5;
  1930. break;
  1931. case SAMPLING_RATE_48KHZ:
  1932. sample_rate_val = 6;
  1933. break;
  1934. case SAMPLING_RATE_96KHZ:
  1935. sample_rate_val = 7;
  1936. break;
  1937. case SAMPLING_RATE_192KHZ:
  1938. sample_rate_val = 8;
  1939. break;
  1940. default:
  1941. sample_rate_val = 6;
  1942. break;
  1943. }
  1944. return sample_rate_val;
  1945. }
  1946. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1947. struct snd_ctl_elem_value *ucontrol)
  1948. {
  1949. int idx = mi2s_get_port_idx(kcontrol);
  1950. if (idx < 0)
  1951. return idx;
  1952. ucontrol->value.enumerated.item[0] =
  1953. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1954. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1955. idx, mi2s_rx_cfg[idx].sample_rate,
  1956. ucontrol->value.enumerated.item[0]);
  1957. return 0;
  1958. }
  1959. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1960. struct snd_ctl_elem_value *ucontrol)
  1961. {
  1962. int idx = mi2s_get_port_idx(kcontrol);
  1963. if (idx < 0)
  1964. return idx;
  1965. mi2s_rx_cfg[idx].sample_rate =
  1966. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1967. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1968. idx, mi2s_rx_cfg[idx].sample_rate,
  1969. ucontrol->value.enumerated.item[0]);
  1970. return 0;
  1971. }
  1972. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1973. struct snd_ctl_elem_value *ucontrol)
  1974. {
  1975. int idx = mi2s_get_port_idx(kcontrol);
  1976. if (idx < 0)
  1977. return idx;
  1978. ucontrol->value.enumerated.item[0] =
  1979. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1980. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1981. idx, mi2s_tx_cfg[idx].sample_rate,
  1982. ucontrol->value.enumerated.item[0]);
  1983. return 0;
  1984. }
  1985. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1986. struct snd_ctl_elem_value *ucontrol)
  1987. {
  1988. int idx = mi2s_get_port_idx(kcontrol);
  1989. if (idx < 0)
  1990. return idx;
  1991. mi2s_tx_cfg[idx].sample_rate =
  1992. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1993. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1994. idx, mi2s_tx_cfg[idx].sample_rate,
  1995. ucontrol->value.enumerated.item[0]);
  1996. return 0;
  1997. }
  1998. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1999. struct snd_ctl_elem_value *ucontrol)
  2000. {
  2001. int idx = mi2s_get_port_idx(kcontrol);
  2002. if (idx < 0)
  2003. return idx;
  2004. ucontrol->value.enumerated.item[0] =
  2005. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2006. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2007. idx, mi2s_rx_cfg[idx].bit_format,
  2008. ucontrol->value.enumerated.item[0]);
  2009. return 0;
  2010. }
  2011. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2012. struct snd_ctl_elem_value *ucontrol)
  2013. {
  2014. int idx = mi2s_get_port_idx(kcontrol);
  2015. if (idx < 0)
  2016. return idx;
  2017. mi2s_rx_cfg[idx].bit_format =
  2018. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2019. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2020. idx, mi2s_rx_cfg[idx].bit_format,
  2021. ucontrol->value.enumerated.item[0]);
  2022. return 0;
  2023. }
  2024. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2025. struct snd_ctl_elem_value *ucontrol)
  2026. {
  2027. int idx = mi2s_get_port_idx(kcontrol);
  2028. if (idx < 0)
  2029. return idx;
  2030. ucontrol->value.enumerated.item[0] =
  2031. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2032. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2033. idx, mi2s_tx_cfg[idx].bit_format,
  2034. ucontrol->value.enumerated.item[0]);
  2035. return 0;
  2036. }
  2037. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2038. struct snd_ctl_elem_value *ucontrol)
  2039. {
  2040. int idx = mi2s_get_port_idx(kcontrol);
  2041. if (idx < 0)
  2042. return idx;
  2043. mi2s_tx_cfg[idx].bit_format =
  2044. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2045. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2046. idx, mi2s_tx_cfg[idx].bit_format,
  2047. ucontrol->value.enumerated.item[0]);
  2048. return 0;
  2049. }
  2050. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2051. struct snd_ctl_elem_value *ucontrol)
  2052. {
  2053. int idx = mi2s_get_port_idx(kcontrol);
  2054. if (idx < 0)
  2055. return idx;
  2056. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2057. idx, mi2s_rx_cfg[idx].channels);
  2058. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2059. return 0;
  2060. }
  2061. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2062. struct snd_ctl_elem_value *ucontrol)
  2063. {
  2064. int idx = mi2s_get_port_idx(kcontrol);
  2065. if (idx < 0)
  2066. return idx;
  2067. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2068. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2069. idx, mi2s_rx_cfg[idx].channels);
  2070. return 1;
  2071. }
  2072. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2073. struct snd_ctl_elem_value *ucontrol)
  2074. {
  2075. int idx = mi2s_get_port_idx(kcontrol);
  2076. if (idx < 0)
  2077. return idx;
  2078. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2079. idx, mi2s_tx_cfg[idx].channels);
  2080. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2081. return 0;
  2082. }
  2083. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2084. struct snd_ctl_elem_value *ucontrol)
  2085. {
  2086. int idx = mi2s_get_port_idx(kcontrol);
  2087. if (idx < 0)
  2088. return idx;
  2089. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2090. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2091. idx, mi2s_tx_cfg[idx].channels);
  2092. return 1;
  2093. }
  2094. static int msm_get_port_id(int be_id)
  2095. {
  2096. int afe_port_id = 0;
  2097. switch (be_id) {
  2098. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2099. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2100. break;
  2101. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2102. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2103. break;
  2104. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2105. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2106. break;
  2107. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2108. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2109. break;
  2110. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2111. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2112. break;
  2113. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2114. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2115. break;
  2116. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2117. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2118. break;
  2119. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2120. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2121. break;
  2122. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2123. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  2124. break;
  2125. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2126. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  2127. break;
  2128. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  2129. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  2130. break;
  2131. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  2132. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  2133. break;
  2134. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2135. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  2136. break;
  2137. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2138. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_1;
  2139. break;
  2140. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2141. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_2;
  2142. break;
  2143. default:
  2144. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  2145. afe_port_id = -EINVAL;
  2146. }
  2147. return afe_port_id;
  2148. }
  2149. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2150. {
  2151. u32 bit_per_sample = 0;
  2152. switch (bit_format) {
  2153. case SNDRV_PCM_FORMAT_S32_LE:
  2154. case SNDRV_PCM_FORMAT_S24_3LE:
  2155. case SNDRV_PCM_FORMAT_S24_LE:
  2156. bit_per_sample = 32;
  2157. break;
  2158. case SNDRV_PCM_FORMAT_S16_LE:
  2159. default:
  2160. bit_per_sample = 16;
  2161. break;
  2162. }
  2163. return bit_per_sample;
  2164. }
  2165. static void update_mi2s_clk_val(int dai_id, int stream)
  2166. {
  2167. u32 bit_per_sample = 0;
  2168. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2169. bit_per_sample =
  2170. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2171. mi2s_clk[dai_id].clk_freq_in_hz =
  2172. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2173. } else {
  2174. bit_per_sample =
  2175. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2176. mi2s_clk[dai_id].clk_freq_in_hz =
  2177. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2178. }
  2179. }
  2180. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2181. {
  2182. int ret = 0;
  2183. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2184. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2185. int port_id = 0;
  2186. int index = cpu_dai->id;
  2187. port_id = msm_get_port_id(rtd->dai_link->id);
  2188. if (port_id < 0) {
  2189. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2190. ret = port_id;
  2191. goto err;
  2192. }
  2193. if (enable) {
  2194. update_mi2s_clk_val(index, substream->stream);
  2195. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2196. mi2s_clk[index].clk_freq_in_hz);
  2197. }
  2198. mi2s_clk[index].enable = enable;
  2199. ret = afe_set_lpass_clock_v2(port_id,
  2200. &mi2s_clk[index]);
  2201. if (ret < 0) {
  2202. dev_err(rtd->card->dev,
  2203. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2204. __func__, port_id, ret);
  2205. goto err;
  2206. }
  2207. err:
  2208. return ret;
  2209. }
  2210. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  2211. {
  2212. int idx = 0;
  2213. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  2214. sizeof("WSA_CDC_DMA_RX_0")))
  2215. idx = WSA_CDC_DMA_RX_0;
  2216. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  2217. sizeof("WSA_CDC_DMA_RX_0")))
  2218. idx = WSA_CDC_DMA_RX_1;
  2219. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  2220. sizeof("RX_CDC_DMA_RX_0")))
  2221. idx = RX_CDC_DMA_RX_0;
  2222. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  2223. sizeof("RX_CDC_DMA_RX_1")))
  2224. idx = RX_CDC_DMA_RX_1;
  2225. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  2226. sizeof("RX_CDC_DMA_RX_2")))
  2227. idx = RX_CDC_DMA_RX_2;
  2228. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  2229. sizeof("RX_CDC_DMA_RX_3")))
  2230. idx = RX_CDC_DMA_RX_3;
  2231. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  2232. sizeof("RX_CDC_DMA_RX_5")))
  2233. idx = RX_CDC_DMA_RX_5;
  2234. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  2235. sizeof("WSA_CDC_DMA_TX_0")))
  2236. idx = WSA_CDC_DMA_TX_0;
  2237. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  2238. sizeof("WSA_CDC_DMA_TX_1")))
  2239. idx = WSA_CDC_DMA_TX_1;
  2240. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  2241. sizeof("WSA_CDC_DMA_TX_2")))
  2242. idx = WSA_CDC_DMA_TX_2;
  2243. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  2244. sizeof("TX_CDC_DMA_TX_0")))
  2245. idx = TX_CDC_DMA_TX_0;
  2246. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  2247. sizeof("TX_CDC_DMA_TX_3")))
  2248. idx = TX_CDC_DMA_TX_3;
  2249. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  2250. sizeof("TX_CDC_DMA_TX_4")))
  2251. idx = TX_CDC_DMA_TX_4;
  2252. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  2253. sizeof("VA_CDC_DMA_TX_0")))
  2254. idx = VA_CDC_DMA_TX_0;
  2255. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  2256. sizeof("VA_CDC_DMA_TX_1")))
  2257. idx = VA_CDC_DMA_TX_1;
  2258. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  2259. sizeof("VA_CDC_DMA_TX_2")))
  2260. idx = VA_CDC_DMA_TX_2;
  2261. else {
  2262. pr_err("%s: unsupported channel: %s\n",
  2263. __func__, kcontrol->id.name);
  2264. return -EINVAL;
  2265. }
  2266. return idx;
  2267. }
  2268. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  2269. struct snd_ctl_elem_value *ucontrol)
  2270. {
  2271. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2272. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2273. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2274. return ch_num;
  2275. }
  2276. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2277. cdc_dma_rx_cfg[ch_num].channels - 1);
  2278. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  2279. return 0;
  2280. }
  2281. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  2282. struct snd_ctl_elem_value *ucontrol)
  2283. {
  2284. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2285. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2286. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2287. return ch_num;
  2288. }
  2289. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2290. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2291. cdc_dma_rx_cfg[ch_num].channels);
  2292. return 1;
  2293. }
  2294. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  2295. struct snd_ctl_elem_value *ucontrol)
  2296. {
  2297. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2298. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2299. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2300. return ch_num;
  2301. }
  2302. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  2303. case SNDRV_PCM_FORMAT_S32_LE:
  2304. ucontrol->value.integer.value[0] = 3;
  2305. break;
  2306. case SNDRV_PCM_FORMAT_S24_3LE:
  2307. ucontrol->value.integer.value[0] = 2;
  2308. break;
  2309. case SNDRV_PCM_FORMAT_S24_LE:
  2310. ucontrol->value.integer.value[0] = 1;
  2311. break;
  2312. case SNDRV_PCM_FORMAT_S16_LE:
  2313. default:
  2314. ucontrol->value.integer.value[0] = 0;
  2315. break;
  2316. }
  2317. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2318. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2319. ucontrol->value.integer.value[0]);
  2320. return 0;
  2321. }
  2322. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  2323. struct snd_ctl_elem_value *ucontrol)
  2324. {
  2325. int rc = 0;
  2326. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2327. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2328. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2329. return ch_num;
  2330. }
  2331. switch (ucontrol->value.integer.value[0]) {
  2332. case 3:
  2333. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2334. break;
  2335. case 2:
  2336. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2337. break;
  2338. case 1:
  2339. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2340. break;
  2341. case 0:
  2342. default:
  2343. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2344. break;
  2345. }
  2346. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2347. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2348. ucontrol->value.integer.value[0]);
  2349. return rc;
  2350. }
  2351. static int cdc_dma_get_sample_rate_val(int sample_rate)
  2352. {
  2353. int sample_rate_val = 0;
  2354. switch (sample_rate) {
  2355. case SAMPLING_RATE_8KHZ:
  2356. sample_rate_val = 0;
  2357. break;
  2358. case SAMPLING_RATE_11P025KHZ:
  2359. sample_rate_val = 1;
  2360. break;
  2361. case SAMPLING_RATE_16KHZ:
  2362. sample_rate_val = 2;
  2363. break;
  2364. case SAMPLING_RATE_22P05KHZ:
  2365. sample_rate_val = 3;
  2366. break;
  2367. case SAMPLING_RATE_32KHZ:
  2368. sample_rate_val = 4;
  2369. break;
  2370. case SAMPLING_RATE_44P1KHZ:
  2371. sample_rate_val = 5;
  2372. break;
  2373. case SAMPLING_RATE_48KHZ:
  2374. sample_rate_val = 6;
  2375. break;
  2376. case SAMPLING_RATE_88P2KHZ:
  2377. sample_rate_val = 7;
  2378. break;
  2379. case SAMPLING_RATE_96KHZ:
  2380. sample_rate_val = 8;
  2381. break;
  2382. case SAMPLING_RATE_176P4KHZ:
  2383. sample_rate_val = 9;
  2384. break;
  2385. case SAMPLING_RATE_192KHZ:
  2386. sample_rate_val = 10;
  2387. break;
  2388. case SAMPLING_RATE_352P8KHZ:
  2389. sample_rate_val = 11;
  2390. break;
  2391. case SAMPLING_RATE_384KHZ:
  2392. sample_rate_val = 12;
  2393. break;
  2394. default:
  2395. sample_rate_val = 6;
  2396. break;
  2397. }
  2398. return sample_rate_val;
  2399. }
  2400. static int cdc_dma_get_sample_rate(int value)
  2401. {
  2402. int sample_rate = 0;
  2403. switch (value) {
  2404. case 0:
  2405. sample_rate = SAMPLING_RATE_8KHZ;
  2406. break;
  2407. case 1:
  2408. sample_rate = SAMPLING_RATE_11P025KHZ;
  2409. break;
  2410. case 2:
  2411. sample_rate = SAMPLING_RATE_16KHZ;
  2412. break;
  2413. case 3:
  2414. sample_rate = SAMPLING_RATE_22P05KHZ;
  2415. break;
  2416. case 4:
  2417. sample_rate = SAMPLING_RATE_32KHZ;
  2418. break;
  2419. case 5:
  2420. sample_rate = SAMPLING_RATE_44P1KHZ;
  2421. break;
  2422. case 6:
  2423. sample_rate = SAMPLING_RATE_48KHZ;
  2424. break;
  2425. case 7:
  2426. sample_rate = SAMPLING_RATE_88P2KHZ;
  2427. break;
  2428. case 8:
  2429. sample_rate = SAMPLING_RATE_96KHZ;
  2430. break;
  2431. case 9:
  2432. sample_rate = SAMPLING_RATE_176P4KHZ;
  2433. break;
  2434. case 10:
  2435. sample_rate = SAMPLING_RATE_192KHZ;
  2436. break;
  2437. case 11:
  2438. sample_rate = SAMPLING_RATE_352P8KHZ;
  2439. break;
  2440. case 12:
  2441. sample_rate = SAMPLING_RATE_384KHZ;
  2442. break;
  2443. default:
  2444. sample_rate = SAMPLING_RATE_48KHZ;
  2445. break;
  2446. }
  2447. return sample_rate;
  2448. }
  2449. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2450. struct snd_ctl_elem_value *ucontrol)
  2451. {
  2452. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2453. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2454. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2455. return ch_num;
  2456. }
  2457. ucontrol->value.enumerated.item[0] =
  2458. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2459. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2460. cdc_dma_rx_cfg[ch_num].sample_rate);
  2461. return 0;
  2462. }
  2463. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2464. struct snd_ctl_elem_value *ucontrol)
  2465. {
  2466. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2467. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2468. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2469. return ch_num;
  2470. }
  2471. cdc_dma_rx_cfg[ch_num].sample_rate =
  2472. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2473. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2474. __func__, ucontrol->value.enumerated.item[0],
  2475. cdc_dma_rx_cfg[ch_num].sample_rate);
  2476. return 0;
  2477. }
  2478. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2479. struct snd_ctl_elem_value *ucontrol)
  2480. {
  2481. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2482. if (ch_num < 0) {
  2483. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2484. return ch_num;
  2485. }
  2486. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2487. cdc_dma_tx_cfg[ch_num].channels);
  2488. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2489. return 0;
  2490. }
  2491. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2492. struct snd_ctl_elem_value *ucontrol)
  2493. {
  2494. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2495. if (ch_num < 0) {
  2496. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2497. return ch_num;
  2498. }
  2499. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2500. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2501. cdc_dma_tx_cfg[ch_num].channels);
  2502. return 1;
  2503. }
  2504. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2505. struct snd_ctl_elem_value *ucontrol)
  2506. {
  2507. int sample_rate_val;
  2508. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2509. if (ch_num < 0) {
  2510. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2511. return ch_num;
  2512. }
  2513. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2514. case SAMPLING_RATE_384KHZ:
  2515. sample_rate_val = 12;
  2516. break;
  2517. case SAMPLING_RATE_352P8KHZ:
  2518. sample_rate_val = 11;
  2519. break;
  2520. case SAMPLING_RATE_192KHZ:
  2521. sample_rate_val = 10;
  2522. break;
  2523. case SAMPLING_RATE_176P4KHZ:
  2524. sample_rate_val = 9;
  2525. break;
  2526. case SAMPLING_RATE_96KHZ:
  2527. sample_rate_val = 8;
  2528. break;
  2529. case SAMPLING_RATE_88P2KHZ:
  2530. sample_rate_val = 7;
  2531. break;
  2532. case SAMPLING_RATE_48KHZ:
  2533. sample_rate_val = 6;
  2534. break;
  2535. case SAMPLING_RATE_44P1KHZ:
  2536. sample_rate_val = 5;
  2537. break;
  2538. case SAMPLING_RATE_32KHZ:
  2539. sample_rate_val = 4;
  2540. break;
  2541. case SAMPLING_RATE_22P05KHZ:
  2542. sample_rate_val = 3;
  2543. break;
  2544. case SAMPLING_RATE_16KHZ:
  2545. sample_rate_val = 2;
  2546. break;
  2547. case SAMPLING_RATE_11P025KHZ:
  2548. sample_rate_val = 1;
  2549. break;
  2550. case SAMPLING_RATE_8KHZ:
  2551. sample_rate_val = 0;
  2552. break;
  2553. default:
  2554. sample_rate_val = 6;
  2555. break;
  2556. }
  2557. ucontrol->value.integer.value[0] = sample_rate_val;
  2558. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2559. cdc_dma_tx_cfg[ch_num].sample_rate);
  2560. return 0;
  2561. }
  2562. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2563. struct snd_ctl_elem_value *ucontrol)
  2564. {
  2565. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2566. if (ch_num < 0) {
  2567. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2568. return ch_num;
  2569. }
  2570. switch (ucontrol->value.integer.value[0]) {
  2571. case 12:
  2572. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2573. break;
  2574. case 11:
  2575. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2576. break;
  2577. case 10:
  2578. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2579. break;
  2580. case 9:
  2581. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2582. break;
  2583. case 8:
  2584. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2585. break;
  2586. case 7:
  2587. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2588. break;
  2589. case 6:
  2590. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2591. break;
  2592. case 5:
  2593. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2594. break;
  2595. case 4:
  2596. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2597. break;
  2598. case 3:
  2599. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2600. break;
  2601. case 2:
  2602. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2603. break;
  2604. case 1:
  2605. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2606. break;
  2607. case 0:
  2608. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2609. break;
  2610. default:
  2611. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2612. break;
  2613. }
  2614. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2615. __func__, ucontrol->value.integer.value[0],
  2616. cdc_dma_tx_cfg[ch_num].sample_rate);
  2617. return 0;
  2618. }
  2619. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2620. struct snd_ctl_elem_value *ucontrol)
  2621. {
  2622. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2623. if (ch_num < 0) {
  2624. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2625. return ch_num;
  2626. }
  2627. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2628. case SNDRV_PCM_FORMAT_S32_LE:
  2629. ucontrol->value.integer.value[0] = 3;
  2630. break;
  2631. case SNDRV_PCM_FORMAT_S24_3LE:
  2632. ucontrol->value.integer.value[0] = 2;
  2633. break;
  2634. case SNDRV_PCM_FORMAT_S24_LE:
  2635. ucontrol->value.integer.value[0] = 1;
  2636. break;
  2637. case SNDRV_PCM_FORMAT_S16_LE:
  2638. default:
  2639. ucontrol->value.integer.value[0] = 0;
  2640. break;
  2641. }
  2642. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2643. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2644. ucontrol->value.integer.value[0]);
  2645. return 0;
  2646. }
  2647. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2648. struct snd_ctl_elem_value *ucontrol)
  2649. {
  2650. int rc = 0;
  2651. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2652. if (ch_num < 0) {
  2653. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2654. return ch_num;
  2655. }
  2656. switch (ucontrol->value.integer.value[0]) {
  2657. case 3:
  2658. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2659. break;
  2660. case 2:
  2661. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2662. break;
  2663. case 1:
  2664. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2665. break;
  2666. case 0:
  2667. default:
  2668. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2669. break;
  2670. }
  2671. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2672. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2673. ucontrol->value.integer.value[0]);
  2674. return rc;
  2675. }
  2676. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2677. {
  2678. int idx = 0;
  2679. switch (be_id) {
  2680. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  2681. idx = WSA_CDC_DMA_RX_0;
  2682. break;
  2683. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  2684. idx = WSA_CDC_DMA_TX_0;
  2685. break;
  2686. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  2687. idx = WSA_CDC_DMA_RX_1;
  2688. break;
  2689. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  2690. idx = WSA_CDC_DMA_TX_1;
  2691. break;
  2692. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  2693. idx = WSA_CDC_DMA_TX_2;
  2694. break;
  2695. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2696. idx = RX_CDC_DMA_RX_0;
  2697. break;
  2698. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2699. idx = RX_CDC_DMA_RX_1;
  2700. break;
  2701. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2702. idx = RX_CDC_DMA_RX_2;
  2703. break;
  2704. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2705. idx = RX_CDC_DMA_RX_3;
  2706. break;
  2707. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2708. idx = RX_CDC_DMA_RX_5;
  2709. break;
  2710. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2711. idx = TX_CDC_DMA_TX_0;
  2712. break;
  2713. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2714. idx = TX_CDC_DMA_TX_3;
  2715. break;
  2716. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2717. idx = TX_CDC_DMA_TX_4;
  2718. break;
  2719. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2720. idx = VA_CDC_DMA_TX_0;
  2721. break;
  2722. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2723. idx = VA_CDC_DMA_TX_1;
  2724. break;
  2725. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2726. idx = VA_CDC_DMA_TX_2;
  2727. break;
  2728. default:
  2729. idx = RX_CDC_DMA_RX_0;
  2730. break;
  2731. }
  2732. return idx;
  2733. }
  2734. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2735. struct snd_ctl_elem_value *ucontrol)
  2736. {
  2737. /*
  2738. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2739. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2740. * value.
  2741. */
  2742. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2743. case SAMPLING_RATE_96KHZ:
  2744. ucontrol->value.integer.value[0] = 5;
  2745. break;
  2746. case SAMPLING_RATE_88P2KHZ:
  2747. ucontrol->value.integer.value[0] = 4;
  2748. break;
  2749. case SAMPLING_RATE_48KHZ:
  2750. ucontrol->value.integer.value[0] = 3;
  2751. break;
  2752. case SAMPLING_RATE_44P1KHZ:
  2753. ucontrol->value.integer.value[0] = 2;
  2754. break;
  2755. case SAMPLING_RATE_16KHZ:
  2756. ucontrol->value.integer.value[0] = 1;
  2757. break;
  2758. case SAMPLING_RATE_8KHZ:
  2759. default:
  2760. ucontrol->value.integer.value[0] = 0;
  2761. break;
  2762. }
  2763. pr_debug("%s: sample rate = %d\n", __func__,
  2764. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2765. return 0;
  2766. }
  2767. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2768. struct snd_ctl_elem_value *ucontrol)
  2769. {
  2770. switch (ucontrol->value.integer.value[0]) {
  2771. case 1:
  2772. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2773. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2774. break;
  2775. case 2:
  2776. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2777. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2778. break;
  2779. case 3:
  2780. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2781. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2782. break;
  2783. case 4:
  2784. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2785. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2786. break;
  2787. case 5:
  2788. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2789. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2790. break;
  2791. case 0:
  2792. default:
  2793. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2794. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2795. break;
  2796. }
  2797. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2798. __func__,
  2799. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2800. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2801. ucontrol->value.enumerated.item[0]);
  2802. return 0;
  2803. }
  2804. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2805. struct snd_ctl_elem_value *ucontrol)
  2806. {
  2807. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2808. case SAMPLING_RATE_96KHZ:
  2809. ucontrol->value.integer.value[0] = 5;
  2810. break;
  2811. case SAMPLING_RATE_88P2KHZ:
  2812. ucontrol->value.integer.value[0] = 4;
  2813. break;
  2814. case SAMPLING_RATE_48KHZ:
  2815. ucontrol->value.integer.value[0] = 3;
  2816. break;
  2817. case SAMPLING_RATE_44P1KHZ:
  2818. ucontrol->value.integer.value[0] = 2;
  2819. break;
  2820. case SAMPLING_RATE_16KHZ:
  2821. ucontrol->value.integer.value[0] = 1;
  2822. break;
  2823. case SAMPLING_RATE_8KHZ:
  2824. default:
  2825. ucontrol->value.integer.value[0] = 0;
  2826. break;
  2827. }
  2828. pr_debug("%s: sample rate rx = %d\n", __func__,
  2829. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2830. return 0;
  2831. }
  2832. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  2833. struct snd_ctl_elem_value *ucontrol)
  2834. {
  2835. switch (ucontrol->value.integer.value[0]) {
  2836. case 1:
  2837. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2838. break;
  2839. case 2:
  2840. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2841. break;
  2842. case 3:
  2843. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2844. break;
  2845. case 4:
  2846. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2847. break;
  2848. case 5:
  2849. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2850. break;
  2851. case 0:
  2852. default:
  2853. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2854. break;
  2855. }
  2856. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  2857. __func__,
  2858. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2859. ucontrol->value.enumerated.item[0]);
  2860. return 0;
  2861. }
  2862. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  2863. struct snd_ctl_elem_value *ucontrol)
  2864. {
  2865. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  2866. case SAMPLING_RATE_96KHZ:
  2867. ucontrol->value.integer.value[0] = 5;
  2868. break;
  2869. case SAMPLING_RATE_88P2KHZ:
  2870. ucontrol->value.integer.value[0] = 4;
  2871. break;
  2872. case SAMPLING_RATE_48KHZ:
  2873. ucontrol->value.integer.value[0] = 3;
  2874. break;
  2875. case SAMPLING_RATE_44P1KHZ:
  2876. ucontrol->value.integer.value[0] = 2;
  2877. break;
  2878. case SAMPLING_RATE_16KHZ:
  2879. ucontrol->value.integer.value[0] = 1;
  2880. break;
  2881. case SAMPLING_RATE_8KHZ:
  2882. default:
  2883. ucontrol->value.integer.value[0] = 0;
  2884. break;
  2885. }
  2886. pr_debug("%s: sample rate tx = %d\n", __func__,
  2887. slim_tx_cfg[SLIM_TX_7].sample_rate);
  2888. return 0;
  2889. }
  2890. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  2891. struct snd_ctl_elem_value *ucontrol)
  2892. {
  2893. switch (ucontrol->value.integer.value[0]) {
  2894. case 1:
  2895. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2896. break;
  2897. case 2:
  2898. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2899. break;
  2900. case 3:
  2901. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2902. break;
  2903. case 4:
  2904. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2905. break;
  2906. case 5:
  2907. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2908. break;
  2909. case 0:
  2910. default:
  2911. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2912. break;
  2913. }
  2914. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  2915. __func__,
  2916. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2917. ucontrol->value.enumerated.item[0]);
  2918. return 0;
  2919. }
  2920. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  2921. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2922. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2923. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2924. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2925. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  2926. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2927. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  2928. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2929. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  2930. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2931. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  2932. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2933. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  2934. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2935. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2936. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2937. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2938. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2939. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2940. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2941. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  2942. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2943. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  2944. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2945. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  2946. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2947. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2948. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2949. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2950. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2951. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  2952. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2953. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2954. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2955. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2956. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2957. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2958. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2959. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2960. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2961. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  2962. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2963. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  2964. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2965. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  2966. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2967. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2968. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2969. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2970. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2971. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  2972. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2973. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2974. wsa_cdc_dma_rx_0_sample_rate,
  2975. cdc_dma_rx_sample_rate_get,
  2976. cdc_dma_rx_sample_rate_put),
  2977. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2978. wsa_cdc_dma_rx_1_sample_rate,
  2979. cdc_dma_rx_sample_rate_get,
  2980. cdc_dma_rx_sample_rate_put),
  2981. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2982. wsa_cdc_dma_tx_0_sample_rate,
  2983. cdc_dma_tx_sample_rate_get,
  2984. cdc_dma_tx_sample_rate_put),
  2985. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2986. wsa_cdc_dma_tx_1_sample_rate,
  2987. cdc_dma_tx_sample_rate_get,
  2988. cdc_dma_tx_sample_rate_put),
  2989. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2990. wsa_cdc_dma_tx_2_sample_rate,
  2991. cdc_dma_tx_sample_rate_get,
  2992. cdc_dma_tx_sample_rate_put),
  2993. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  2994. tx_cdc_dma_tx_0_sample_rate,
  2995. cdc_dma_tx_sample_rate_get,
  2996. cdc_dma_tx_sample_rate_put),
  2997. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  2998. tx_cdc_dma_tx_3_sample_rate,
  2999. cdc_dma_tx_sample_rate_get,
  3000. cdc_dma_tx_sample_rate_put),
  3001. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  3002. tx_cdc_dma_tx_4_sample_rate,
  3003. cdc_dma_tx_sample_rate_get,
  3004. cdc_dma_tx_sample_rate_put),
  3005. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3006. va_cdc_dma_tx_0_sample_rate,
  3007. cdc_dma_tx_sample_rate_get,
  3008. cdc_dma_tx_sample_rate_put),
  3009. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3010. va_cdc_dma_tx_1_sample_rate,
  3011. cdc_dma_tx_sample_rate_get,
  3012. cdc_dma_tx_sample_rate_put),
  3013. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  3014. va_cdc_dma_tx_2_sample_rate,
  3015. cdc_dma_tx_sample_rate_get,
  3016. cdc_dma_tx_sample_rate_put),
  3017. };
  3018. static const struct snd_kcontrol_new msm_int_wcd9380_snd_controls[] = {
  3019. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc80_dma_rx_0_format,
  3020. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3021. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc80_dma_rx_1_format,
  3022. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3023. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc80_dma_rx_2_format,
  3024. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3025. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc80_dma_rx_3_format,
  3026. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3027. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc80_dma_rx_5_format,
  3028. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3029. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  3030. rx_cdc80_dma_rx_0_sample_rate,
  3031. cdc_dma_rx_sample_rate_get,
  3032. cdc_dma_rx_sample_rate_put),
  3033. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  3034. rx_cdc80_dma_rx_1_sample_rate,
  3035. cdc_dma_rx_sample_rate_get,
  3036. cdc_dma_rx_sample_rate_put),
  3037. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  3038. rx_cdc80_dma_rx_2_sample_rate,
  3039. cdc_dma_rx_sample_rate_get,
  3040. cdc_dma_rx_sample_rate_put),
  3041. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  3042. rx_cdc80_dma_rx_3_sample_rate,
  3043. cdc_dma_rx_sample_rate_get,
  3044. cdc_dma_rx_sample_rate_put),
  3045. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  3046. rx_cdc80_dma_rx_5_sample_rate,
  3047. cdc_dma_rx_sample_rate_get,
  3048. cdc_dma_rx_sample_rate_put),
  3049. };
  3050. static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = {
  3051. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc85_dma_rx_0_format,
  3052. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3053. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc85_dma_rx_1_format,
  3054. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3055. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc85_dma_rx_2_format,
  3056. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3057. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc85_dma_rx_3_format,
  3058. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3059. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc85_dma_rx_5_format,
  3060. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3061. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  3062. rx_cdc85_dma_rx_0_sample_rate,
  3063. cdc_dma_rx_sample_rate_get,
  3064. cdc_dma_rx_sample_rate_put),
  3065. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  3066. rx_cdc85_dma_rx_1_sample_rate,
  3067. cdc_dma_rx_sample_rate_get,
  3068. cdc_dma_rx_sample_rate_put),
  3069. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  3070. rx_cdc85_dma_rx_2_sample_rate,
  3071. cdc_dma_rx_sample_rate_get,
  3072. cdc_dma_rx_sample_rate_put),
  3073. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  3074. rx_cdc85_dma_rx_3_sample_rate,
  3075. cdc_dma_rx_sample_rate_get,
  3076. cdc_dma_rx_sample_rate_put),
  3077. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  3078. rx_cdc85_dma_rx_5_sample_rate,
  3079. cdc_dma_rx_sample_rate_get,
  3080. cdc_dma_rx_sample_rate_put),
  3081. };
  3082. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  3083. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3084. usb_audio_rx_sample_rate_get,
  3085. usb_audio_rx_sample_rate_put),
  3086. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3087. usb_audio_tx_sample_rate_get,
  3088. usb_audio_tx_sample_rate_put),
  3089. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3090. tdm_rx_sample_rate_get,
  3091. tdm_rx_sample_rate_put),
  3092. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3093. tdm_rx_sample_rate_get,
  3094. tdm_rx_sample_rate_put),
  3095. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3096. tdm_rx_sample_rate_get,
  3097. tdm_rx_sample_rate_put),
  3098. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3099. tdm_rx_sample_rate_get,
  3100. tdm_rx_sample_rate_put),
  3101. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3102. tdm_rx_sample_rate_get,
  3103. tdm_rx_sample_rate_put),
  3104. SOC_ENUM_EXT("SEN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3105. tdm_rx_sample_rate_get,
  3106. tdm_rx_sample_rate_put),
  3107. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3108. tdm_tx_sample_rate_get,
  3109. tdm_tx_sample_rate_put),
  3110. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3111. tdm_tx_sample_rate_get,
  3112. tdm_tx_sample_rate_put),
  3113. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3114. tdm_tx_sample_rate_get,
  3115. tdm_tx_sample_rate_put),
  3116. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3117. tdm_tx_sample_rate_get,
  3118. tdm_tx_sample_rate_put),
  3119. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3120. tdm_tx_sample_rate_get,
  3121. tdm_tx_sample_rate_put),
  3122. SOC_ENUM_EXT("SEN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3123. tdm_tx_sample_rate_get,
  3124. tdm_tx_sample_rate_put),
  3125. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3126. aux_pcm_rx_sample_rate_get,
  3127. aux_pcm_rx_sample_rate_put),
  3128. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3129. aux_pcm_rx_sample_rate_get,
  3130. aux_pcm_rx_sample_rate_put),
  3131. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3132. aux_pcm_rx_sample_rate_get,
  3133. aux_pcm_rx_sample_rate_put),
  3134. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3135. aux_pcm_rx_sample_rate_get,
  3136. aux_pcm_rx_sample_rate_put),
  3137. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3138. aux_pcm_rx_sample_rate_get,
  3139. aux_pcm_rx_sample_rate_put),
  3140. SOC_ENUM_EXT("SEN_AUX_PCM_RX SampleRate", sen_aux_pcm_rx_sample_rate,
  3141. aux_pcm_rx_sample_rate_get,
  3142. aux_pcm_rx_sample_rate_put),
  3143. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3144. aux_pcm_tx_sample_rate_get,
  3145. aux_pcm_tx_sample_rate_put),
  3146. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3147. aux_pcm_tx_sample_rate_get,
  3148. aux_pcm_tx_sample_rate_put),
  3149. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3150. aux_pcm_tx_sample_rate_get,
  3151. aux_pcm_tx_sample_rate_put),
  3152. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3153. aux_pcm_tx_sample_rate_get,
  3154. aux_pcm_tx_sample_rate_put),
  3155. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3156. aux_pcm_tx_sample_rate_get,
  3157. aux_pcm_tx_sample_rate_put),
  3158. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3159. aux_pcm_tx_sample_rate_get,
  3160. aux_pcm_tx_sample_rate_put),
  3161. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3162. mi2s_rx_sample_rate_get,
  3163. mi2s_rx_sample_rate_put),
  3164. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3165. mi2s_rx_sample_rate_get,
  3166. mi2s_rx_sample_rate_put),
  3167. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3168. mi2s_rx_sample_rate_get,
  3169. mi2s_rx_sample_rate_put),
  3170. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3171. mi2s_rx_sample_rate_get,
  3172. mi2s_rx_sample_rate_put),
  3173. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3174. mi2s_rx_sample_rate_get,
  3175. mi2s_rx_sample_rate_put),
  3176. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3177. mi2s_rx_sample_rate_get,
  3178. mi2s_rx_sample_rate_put),
  3179. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3180. mi2s_tx_sample_rate_get,
  3181. mi2s_tx_sample_rate_put),
  3182. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3183. mi2s_tx_sample_rate_get,
  3184. mi2s_tx_sample_rate_put),
  3185. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3186. mi2s_tx_sample_rate_get,
  3187. mi2s_tx_sample_rate_put),
  3188. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3189. mi2s_tx_sample_rate_get,
  3190. mi2s_tx_sample_rate_put),
  3191. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3192. mi2s_tx_sample_rate_get,
  3193. mi2s_tx_sample_rate_put),
  3194. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3195. mi2s_tx_sample_rate_get,
  3196. mi2s_tx_sample_rate_put),
  3197. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3198. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3199. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3200. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3201. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3202. tdm_rx_format_get,
  3203. tdm_rx_format_put),
  3204. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3205. tdm_rx_format_get,
  3206. tdm_rx_format_put),
  3207. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3208. tdm_rx_format_get,
  3209. tdm_rx_format_put),
  3210. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3211. tdm_rx_format_get,
  3212. tdm_rx_format_put),
  3213. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3214. tdm_rx_format_get,
  3215. tdm_rx_format_put),
  3216. SOC_ENUM_EXT("SEN_TDM_RX_0 Format", tdm_rx_format,
  3217. tdm_rx_format_get,
  3218. tdm_rx_format_put),
  3219. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3220. tdm_tx_format_get,
  3221. tdm_tx_format_put),
  3222. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3223. tdm_tx_format_get,
  3224. tdm_tx_format_put),
  3225. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3226. tdm_tx_format_get,
  3227. tdm_tx_format_put),
  3228. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3229. tdm_tx_format_get,
  3230. tdm_tx_format_put),
  3231. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3232. tdm_tx_format_get,
  3233. tdm_tx_format_put),
  3234. SOC_ENUM_EXT("SEN_TDM_TX_0 Format", tdm_tx_format,
  3235. tdm_tx_format_get,
  3236. tdm_tx_format_put),
  3237. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3238. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3239. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3240. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3241. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3242. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3243. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3244. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3245. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3246. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3247. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3248. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3249. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3250. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3251. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3252. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3253. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3254. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3255. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3256. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3257. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3258. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3259. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3260. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3261. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3262. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3263. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3264. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3265. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3266. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3267. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3268. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3269. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3270. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3271. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3272. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3273. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3274. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3275. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3276. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3277. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3278. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3279. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3280. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3281. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3282. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3283. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3284. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3285. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3286. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3287. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3288. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3289. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3290. proxy_rx_ch_get, proxy_rx_ch_put),
  3291. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3292. tdm_rx_ch_get,
  3293. tdm_rx_ch_put),
  3294. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3295. tdm_rx_ch_get,
  3296. tdm_rx_ch_put),
  3297. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3298. tdm_rx_ch_get,
  3299. tdm_rx_ch_put),
  3300. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3301. tdm_rx_ch_get,
  3302. tdm_rx_ch_put),
  3303. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3304. tdm_rx_ch_get,
  3305. tdm_rx_ch_put),
  3306. SOC_ENUM_EXT("SEN_TDM_RX_0 Channels", tdm_rx_chs,
  3307. tdm_rx_ch_get,
  3308. tdm_rx_ch_put),
  3309. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3310. tdm_tx_ch_get,
  3311. tdm_tx_ch_put),
  3312. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3313. tdm_tx_ch_get,
  3314. tdm_tx_ch_put),
  3315. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3316. tdm_tx_ch_get,
  3317. tdm_tx_ch_put),
  3318. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3319. tdm_tx_ch_get,
  3320. tdm_tx_ch_put),
  3321. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3322. tdm_tx_ch_get,
  3323. tdm_tx_ch_put),
  3324. SOC_ENUM_EXT("SEN_TDM_TX_0 Channels", tdm_tx_chs,
  3325. tdm_tx_ch_get,
  3326. tdm_tx_ch_put),
  3327. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3328. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3329. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3330. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3331. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3332. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3333. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3334. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3335. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3336. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3337. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3338. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3339. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3340. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3341. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3342. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3343. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3344. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3345. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3346. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3347. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3348. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3349. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3350. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3351. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  3352. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  3353. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  3354. ext_disp_rx_format_get, ext_disp_rx_format_put),
  3355. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  3356. ext_disp_rx_sample_rate_get,
  3357. ext_disp_rx_sample_rate_put),
  3358. SOC_ENUM_EXT("Display Port1 RX Channels", ext_disp_rx_chs,
  3359. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  3360. SOC_ENUM_EXT("Display Port1 RX Bit Format", ext_disp_rx_format,
  3361. ext_disp_rx_format_get, ext_disp_rx_format_put),
  3362. SOC_ENUM_EXT("Display Port1 RX SampleRate", ext_disp_rx_sample_rate,
  3363. ext_disp_rx_sample_rate_get,
  3364. ext_disp_rx_sample_rate_put),
  3365. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3366. msm_bt_sample_rate_get,
  3367. msm_bt_sample_rate_put),
  3368. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  3369. msm_bt_sample_rate_rx_get,
  3370. msm_bt_sample_rate_rx_put),
  3371. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  3372. msm_bt_sample_rate_tx_get,
  3373. msm_bt_sample_rate_tx_put),
  3374. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  3375. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  3376. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3377. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3378. };
  3379. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3380. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3381. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3382. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3383. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3384. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3385. aux_pcm_rx_sample_rate_get,
  3386. aux_pcm_rx_sample_rate_put),
  3387. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3388. aux_pcm_tx_sample_rate_get,
  3389. aux_pcm_tx_sample_rate_put),
  3390. };
  3391. static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
  3392. {
  3393. int idx;
  3394. switch (be_id) {
  3395. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3396. idx = EXT_DISP_RX_IDX_DP;
  3397. break;
  3398. case MSM_BACKEND_DAI_DISPLAY_PORT_RX_1:
  3399. idx = EXT_DISP_RX_IDX_DP1;
  3400. break;
  3401. default:
  3402. pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
  3403. idx = -EINVAL;
  3404. break;
  3405. }
  3406. return idx;
  3407. }
  3408. static int kona_send_island_va_config(int32_t be_id)
  3409. {
  3410. int rc = 0;
  3411. int port_id = 0xFFFF;
  3412. port_id = msm_get_port_id(be_id);
  3413. if (port_id < 0) {
  3414. pr_err("%s: Invalid island interface, be_id: %d\n",
  3415. __func__, be_id);
  3416. rc = -EINVAL;
  3417. } else {
  3418. /*
  3419. * send island mode config
  3420. * This should be the first configuration
  3421. */
  3422. rc = afe_send_port_island_mode(port_id);
  3423. if (rc)
  3424. pr_err("%s: afe send island mode failed %d\n",
  3425. __func__, rc);
  3426. }
  3427. return rc;
  3428. }
  3429. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3430. struct snd_pcm_hw_params *params)
  3431. {
  3432. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3433. struct snd_interval *rate = hw_param_interval(params,
  3434. SNDRV_PCM_HW_PARAM_RATE);
  3435. struct snd_interval *channels = hw_param_interval(params,
  3436. SNDRV_PCM_HW_PARAM_CHANNELS);
  3437. int idx = 0, rc = 0;
  3438. pr_debug("%s: format = %d, rate = %d\n",
  3439. __func__, params_format(params), params_rate(params));
  3440. switch (dai_link->id) {
  3441. case MSM_BACKEND_DAI_USB_RX:
  3442. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3443. usb_rx_cfg.bit_format);
  3444. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3445. channels->min = channels->max = usb_rx_cfg.channels;
  3446. break;
  3447. case MSM_BACKEND_DAI_USB_TX:
  3448. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3449. usb_tx_cfg.bit_format);
  3450. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3451. channels->min = channels->max = usb_tx_cfg.channels;
  3452. break;
  3453. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3454. case MSM_BACKEND_DAI_DISPLAY_PORT_RX_1:
  3455. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  3456. if (idx < 0) {
  3457. pr_err("%s: Incorrect ext disp idx %d\n",
  3458. __func__, idx);
  3459. rc = idx;
  3460. goto done;
  3461. }
  3462. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3463. ext_disp_rx_cfg[idx].bit_format);
  3464. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  3465. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  3466. break;
  3467. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3468. channels->min = channels->max = proxy_rx_cfg.channels;
  3469. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3470. break;
  3471. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3472. channels->min = channels->max =
  3473. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3474. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3475. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3476. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3477. break;
  3478. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3479. channels->min = channels->max =
  3480. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3481. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3482. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3483. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3484. break;
  3485. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3486. channels->min = channels->max =
  3487. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3488. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3489. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3490. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3491. break;
  3492. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3493. channels->min = channels->max =
  3494. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3495. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3496. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3497. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3498. break;
  3499. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3500. channels->min = channels->max =
  3501. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3502. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3503. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3504. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3505. break;
  3506. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3507. channels->min = channels->max =
  3508. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3509. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3510. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3511. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3512. break;
  3513. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3514. channels->min = channels->max =
  3515. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3516. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3517. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3518. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3519. break;
  3520. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3521. channels->min = channels->max =
  3522. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3523. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3524. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3525. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3526. break;
  3527. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3528. channels->min = channels->max =
  3529. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3530. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3531. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3532. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3533. break;
  3534. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3535. channels->min = channels->max =
  3536. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3537. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3538. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3539. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3540. break;
  3541. case MSM_BACKEND_DAI_SEN_TDM_RX_0:
  3542. channels->min = channels->max =
  3543. tdm_rx_cfg[TDM_SEN][TDM_0].channels;
  3544. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3545. tdm_rx_cfg[TDM_SEN][TDM_0].bit_format);
  3546. rate->min = rate->max = tdm_rx_cfg[TDM_SEN][TDM_0].sample_rate;
  3547. break;
  3548. case MSM_BACKEND_DAI_SEN_TDM_TX_0:
  3549. channels->min = channels->max =
  3550. tdm_tx_cfg[TDM_SEN][TDM_0].channels;
  3551. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3552. tdm_tx_cfg[TDM_SEN][TDM_0].bit_format);
  3553. rate->min = rate->max = tdm_tx_cfg[TDM_SEN][TDM_0].sample_rate;
  3554. break;
  3555. case MSM_BACKEND_DAI_AUXPCM_RX:
  3556. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3557. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3558. rate->min = rate->max =
  3559. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3560. channels->min = channels->max =
  3561. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3562. break;
  3563. case MSM_BACKEND_DAI_AUXPCM_TX:
  3564. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3565. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3566. rate->min = rate->max =
  3567. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3568. channels->min = channels->max =
  3569. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3570. break;
  3571. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3572. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3573. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3574. rate->min = rate->max =
  3575. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3576. channels->min = channels->max =
  3577. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3578. break;
  3579. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3580. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3581. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3582. rate->min = rate->max =
  3583. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3584. channels->min = channels->max =
  3585. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3586. break;
  3587. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3588. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3589. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3590. rate->min = rate->max =
  3591. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3592. channels->min = channels->max =
  3593. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3594. break;
  3595. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3596. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3597. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3598. rate->min = rate->max =
  3599. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3600. channels->min = channels->max =
  3601. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3602. break;
  3603. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3604. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3605. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3606. rate->min = rate->max =
  3607. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3608. channels->min = channels->max =
  3609. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3610. break;
  3611. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3612. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3613. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3614. rate->min = rate->max =
  3615. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3616. channels->min = channels->max =
  3617. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3618. break;
  3619. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3620. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3621. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3622. rate->min = rate->max =
  3623. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3624. channels->min = channels->max =
  3625. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3626. break;
  3627. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3628. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3629. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3630. rate->min = rate->max =
  3631. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3632. channels->min = channels->max =
  3633. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3634. break;
  3635. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3636. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3637. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3638. rate->min = rate->max =
  3639. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3640. channels->min = channels->max =
  3641. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3642. break;
  3643. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3644. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3645. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3646. rate->min = rate->max =
  3647. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3648. channels->min = channels->max =
  3649. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3650. break;
  3651. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3652. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3653. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3654. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3655. channels->min = channels->max =
  3656. mi2s_rx_cfg[PRIM_MI2S].channels;
  3657. break;
  3658. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3659. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3660. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3661. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3662. channels->min = channels->max =
  3663. mi2s_tx_cfg[PRIM_MI2S].channels;
  3664. break;
  3665. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3666. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3667. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3668. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3669. channels->min = channels->max =
  3670. mi2s_rx_cfg[SEC_MI2S].channels;
  3671. break;
  3672. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3673. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3674. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3675. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3676. channels->min = channels->max =
  3677. mi2s_tx_cfg[SEC_MI2S].channels;
  3678. break;
  3679. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3680. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3681. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3682. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3683. channels->min = channels->max =
  3684. mi2s_rx_cfg[TERT_MI2S].channels;
  3685. break;
  3686. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3687. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3688. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3689. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3690. channels->min = channels->max =
  3691. mi2s_tx_cfg[TERT_MI2S].channels;
  3692. break;
  3693. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3694. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3695. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3696. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3697. channels->min = channels->max =
  3698. mi2s_rx_cfg[QUAT_MI2S].channels;
  3699. break;
  3700. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3701. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3702. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3703. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3704. channels->min = channels->max =
  3705. mi2s_tx_cfg[QUAT_MI2S].channels;
  3706. break;
  3707. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3708. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3709. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3710. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3711. channels->min = channels->max =
  3712. mi2s_rx_cfg[QUIN_MI2S].channels;
  3713. break;
  3714. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3715. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3716. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3717. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3718. channels->min = channels->max =
  3719. mi2s_tx_cfg[QUIN_MI2S].channels;
  3720. break;
  3721. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3722. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3723. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3724. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  3725. channels->min = channels->max =
  3726. mi2s_rx_cfg[SEN_MI2S].channels;
  3727. break;
  3728. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  3729. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3730. mi2s_tx_cfg[SEN_MI2S].bit_format);
  3731. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  3732. channels->min = channels->max =
  3733. mi2s_tx_cfg[SEN_MI2S].channels;
  3734. break;
  3735. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3736. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3737. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3738. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3739. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3740. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3741. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3742. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3743. cdc_dma_rx_cfg[idx].bit_format);
  3744. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3745. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3746. break;
  3747. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3748. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3749. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3750. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3751. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3752. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3753. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3754. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3755. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3756. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3757. cdc_dma_tx_cfg[idx].bit_format);
  3758. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3759. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3760. break;
  3761. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3762. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3763. SNDRV_PCM_FORMAT_S32_LE);
  3764. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3765. channels->min = channels->max = msm_vi_feed_tx_ch;
  3766. break;
  3767. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3768. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3769. slim_rx_cfg[SLIM_RX_7].bit_format);
  3770. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3771. channels->min = channels->max =
  3772. slim_rx_cfg[SLIM_RX_7].channels;
  3773. break;
  3774. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3775. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3776. channels->min = channels->max =
  3777. slim_tx_cfg[SLIM_TX_7].channels;
  3778. break;
  3779. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3780. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3781. channels->min = channels->max =
  3782. slim_tx_cfg[SLIM_TX_8].channels;
  3783. break;
  3784. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3785. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3786. afe_loopback_tx_cfg[idx].bit_format);
  3787. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3788. channels->min = channels->max =
  3789. afe_loopback_tx_cfg[idx].channels;
  3790. break;
  3791. default:
  3792. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3793. break;
  3794. }
  3795. done:
  3796. return rc;
  3797. }
  3798. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3799. {
  3800. struct snd_soc_card *card = component->card;
  3801. struct msm_asoc_mach_data *pdata =
  3802. snd_soc_card_get_drvdata(card);
  3803. if (!pdata->fsa_handle)
  3804. return false;
  3805. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3806. }
  3807. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3808. {
  3809. int value = 0;
  3810. bool ret = false;
  3811. struct snd_soc_card *card;
  3812. struct msm_asoc_mach_data *pdata;
  3813. if (!component) {
  3814. pr_err("%s component is NULL\n", __func__);
  3815. return false;
  3816. }
  3817. card = component->card;
  3818. pdata = snd_soc_card_get_drvdata(card);
  3819. if (!pdata)
  3820. return false;
  3821. if (wcd_mbhc_cfg.enable_usbc_analog)
  3822. return msm_usbc_swap_gnd_mic(component, active);
  3823. /* if usbc is not defined, swap using us_euro_gpio_p */
  3824. if (pdata->us_euro_gpio_p) {
  3825. value = msm_cdc_pinctrl_get_state(
  3826. pdata->us_euro_gpio_p);
  3827. if (value)
  3828. msm_cdc_pinctrl_select_sleep_state(
  3829. pdata->us_euro_gpio_p);
  3830. else
  3831. msm_cdc_pinctrl_select_active_state(
  3832. pdata->us_euro_gpio_p);
  3833. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  3834. __func__, value, !value);
  3835. ret = true;
  3836. }
  3837. return ret;
  3838. }
  3839. static int kona_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  3840. struct snd_pcm_hw_params *params)
  3841. {
  3842. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3843. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3844. int ret = 0;
  3845. int slot_width = 32;
  3846. int channels, slots;
  3847. unsigned int slot_mask, rate, clk_freq;
  3848. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  3849. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  3850. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  3851. switch (cpu_dai->id) {
  3852. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3853. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3854. break;
  3855. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3856. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3857. break;
  3858. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3859. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3860. break;
  3861. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3862. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3863. break;
  3864. case AFE_PORT_ID_QUINARY_TDM_RX:
  3865. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3866. break;
  3867. case AFE_PORT_ID_SENARY_TDM_RX:
  3868. slots = tdm_rx_cfg[TDM_SEN][TDM_0].channels;
  3869. break;
  3870. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3871. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3872. break;
  3873. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3874. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3875. break;
  3876. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3877. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3878. break;
  3879. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3880. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3881. break;
  3882. case AFE_PORT_ID_QUINARY_TDM_TX:
  3883. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3884. break;
  3885. case AFE_PORT_ID_SENARY_TDM_TX:
  3886. slots = tdm_tx_cfg[TDM_SEN][TDM_0].channels;
  3887. break;
  3888. default:
  3889. pr_err("%s: dai id 0x%x not supported\n",
  3890. __func__, cpu_dai->id);
  3891. return -EINVAL;
  3892. }
  3893. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3894. /*2 slot config - bits 0 and 1 set for the first two slots */
  3895. slot_mask = 0x0000FFFF >> (16 - slots);
  3896. channels = slots;
  3897. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  3898. __func__, slot_width, slots);
  3899. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  3900. slots, slot_width);
  3901. if (ret < 0) {
  3902. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  3903. __func__, ret);
  3904. goto end;
  3905. }
  3906. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3907. 0, NULL, channels, slot_offset);
  3908. if (ret < 0) {
  3909. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  3910. __func__, ret);
  3911. goto end;
  3912. }
  3913. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3914. /*2 slot config - bits 0 and 1 set for the first two slots */
  3915. slot_mask = 0x0000FFFF >> (16 - slots);
  3916. channels = slots;
  3917. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  3918. __func__, slot_width, slots);
  3919. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  3920. slots, slot_width);
  3921. if (ret < 0) {
  3922. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  3923. __func__, ret);
  3924. goto end;
  3925. }
  3926. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3927. channels, slot_offset, 0, NULL);
  3928. if (ret < 0) {
  3929. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  3930. __func__, ret);
  3931. goto end;
  3932. }
  3933. } else {
  3934. ret = -EINVAL;
  3935. pr_err("%s: invalid use case, err:%d\n",
  3936. __func__, ret);
  3937. goto end;
  3938. }
  3939. rate = params_rate(params);
  3940. clk_freq = rate * slot_width * slots;
  3941. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  3942. if (ret < 0)
  3943. pr_err("%s: failed to set tdm clk, err:%d\n",
  3944. __func__, ret);
  3945. end:
  3946. return ret;
  3947. }
  3948. static int msm_get_tdm_mode(u32 port_id)
  3949. {
  3950. int tdm_mode;
  3951. switch (port_id) {
  3952. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3953. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3954. tdm_mode = TDM_PRI;
  3955. break;
  3956. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3957. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3958. tdm_mode = TDM_SEC;
  3959. break;
  3960. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3961. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3962. tdm_mode = TDM_TERT;
  3963. break;
  3964. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3965. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3966. tdm_mode = TDM_QUAT;
  3967. break;
  3968. case AFE_PORT_ID_QUINARY_TDM_RX:
  3969. case AFE_PORT_ID_QUINARY_TDM_TX:
  3970. tdm_mode = TDM_QUIN;
  3971. break;
  3972. case AFE_PORT_ID_SENARY_TDM_RX:
  3973. case AFE_PORT_ID_SENARY_TDM_TX:
  3974. tdm_mode = TDM_SEN;
  3975. break;
  3976. default:
  3977. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  3978. tdm_mode = -EINVAL;
  3979. }
  3980. return tdm_mode;
  3981. }
  3982. static int kona_tdm_snd_startup(struct snd_pcm_substream *substream)
  3983. {
  3984. int ret = 0;
  3985. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3986. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3987. struct snd_soc_card *card = rtd->card;
  3988. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3989. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3990. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3991. ret = -EINVAL;
  3992. pr_err("%s: Invalid TDM interface %d\n",
  3993. __func__, ret);
  3994. return ret;
  3995. }
  3996. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3997. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3998. == 0) {
  3999. ret = msm_cdc_pinctrl_select_active_state(
  4000. pdata->mi2s_gpio_p[tdm_mode]);
  4001. if (ret) {
  4002. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  4003. __func__, ret);
  4004. goto done;
  4005. }
  4006. }
  4007. atomic_inc(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  4008. }
  4009. done:
  4010. return ret;
  4011. }
  4012. static void kona_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4013. {
  4014. int ret = 0;
  4015. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4016. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4017. struct snd_soc_card *card = rtd->card;
  4018. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4019. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4020. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  4021. ret = -EINVAL;
  4022. pr_err("%s: Invalid TDM interface %d\n",
  4023. __func__, ret);
  4024. return;
  4025. }
  4026. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4027. atomic_dec(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  4028. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  4029. == 0) {
  4030. ret = msm_cdc_pinctrl_select_sleep_state(
  4031. pdata->mi2s_gpio_p[tdm_mode]);
  4032. if (ret)
  4033. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  4034. __func__, ret);
  4035. }
  4036. }
  4037. }
  4038. static int kona_aux_snd_startup(struct snd_pcm_substream *substream)
  4039. {
  4040. int ret = 0;
  4041. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4042. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4043. struct snd_soc_card *card = rtd->card;
  4044. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4045. u32 aux_mode = cpu_dai->id - 1;
  4046. if (aux_mode >= AUX_PCM_MAX) {
  4047. ret = -EINVAL;
  4048. pr_err("%s: Invalid AUX interface %d\n",
  4049. __func__, ret);
  4050. return ret;
  4051. }
  4052. if (pdata->mi2s_gpio_p[aux_mode]) {
  4053. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  4054. == 0) {
  4055. ret = msm_cdc_pinctrl_select_active_state(
  4056. pdata->mi2s_gpio_p[aux_mode]);
  4057. if (ret) {
  4058. pr_err("%s: AUX GPIO pinctrl set active failed with %d\n",
  4059. __func__, ret);
  4060. goto done;
  4061. }
  4062. }
  4063. atomic_inc(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  4064. }
  4065. done:
  4066. return ret;
  4067. }
  4068. static void kona_aux_snd_shutdown(struct snd_pcm_substream *substream)
  4069. {
  4070. int ret = 0;
  4071. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4072. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4073. struct snd_soc_card *card = rtd->card;
  4074. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4075. u32 aux_mode = cpu_dai->id - 1;
  4076. if (aux_mode >= AUX_PCM_MAX) {
  4077. pr_err("%s: Invalid AUX interface %d\n",
  4078. __func__, ret);
  4079. return;
  4080. }
  4081. if (pdata->mi2s_gpio_p[aux_mode]) {
  4082. atomic_dec(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  4083. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  4084. == 0) {
  4085. ret = msm_cdc_pinctrl_select_sleep_state(
  4086. pdata->mi2s_gpio_p[aux_mode]);
  4087. if (ret)
  4088. pr_err("%s: AUX GPIO pinctrl set sleep failed with %d\n",
  4089. __func__, ret);
  4090. }
  4091. }
  4092. }
  4093. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  4094. {
  4095. int ret = 0;
  4096. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4097. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4098. switch (dai_link->id) {
  4099. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4100. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4101. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4102. ret = kona_send_island_va_config(dai_link->id);
  4103. if (ret)
  4104. pr_err("%s: send island va cfg failed, err: %d\n",
  4105. __func__, ret);
  4106. break;
  4107. }
  4108. return ret;
  4109. }
  4110. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4111. struct snd_pcm_hw_params *params)
  4112. {
  4113. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4114. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4115. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4116. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4117. int ret = 0;
  4118. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4119. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4120. u32 user_set_tx_ch = 0;
  4121. u32 user_set_rx_ch = 0;
  4122. u32 ch_id;
  4123. ret = snd_soc_dai_get_channel_map(codec_dai,
  4124. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4125. &rx_ch_cdc_dma);
  4126. if (ret < 0) {
  4127. pr_err("%s: failed to get codec chan map, err:%d\n",
  4128. __func__, ret);
  4129. goto err;
  4130. }
  4131. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4132. switch (dai_link->id) {
  4133. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4134. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4135. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  4136. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  4137. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  4138. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  4139. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  4140. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  4141. {
  4142. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4143. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4144. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4145. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4146. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4147. user_set_rx_ch, &rx_ch_cdc_dma);
  4148. if (ret < 0) {
  4149. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4150. __func__, ret);
  4151. goto err;
  4152. }
  4153. }
  4154. break;
  4155. }
  4156. } else {
  4157. switch (dai_link->id) {
  4158. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4159. {
  4160. user_set_tx_ch = msm_vi_feed_tx_ch;
  4161. }
  4162. break;
  4163. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4164. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4165. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  4166. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  4167. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  4168. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4169. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4170. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4171. {
  4172. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4173. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4174. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4175. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4176. }
  4177. break;
  4178. }
  4179. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4180. &tx_ch_cdc_dma, 0, 0);
  4181. if (ret < 0) {
  4182. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4183. __func__, ret);
  4184. goto err;
  4185. }
  4186. }
  4187. err:
  4188. return ret;
  4189. }
  4190. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4191. {
  4192. cpumask_t mask;
  4193. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4194. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4195. cpumask_clear(&mask);
  4196. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4197. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4198. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4199. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4200. pm_qos_add_request(&substream->latency_pm_qos_req,
  4201. PM_QOS_CPU_DMA_LATENCY,
  4202. MSM_LL_QOS_VALUE);
  4203. return 0;
  4204. }
  4205. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4206. {
  4207. int ret = 0;
  4208. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4209. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4210. int index = cpu_dai->id;
  4211. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4212. struct snd_soc_card *card = rtd->card;
  4213. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4214. dev_dbg(rtd->card->dev,
  4215. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4216. __func__, substream->name, substream->stream,
  4217. cpu_dai->name, cpu_dai->id);
  4218. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4219. ret = -EINVAL;
  4220. dev_err(rtd->card->dev,
  4221. "%s: CPU DAI id (%d) out of range\n",
  4222. __func__, cpu_dai->id);
  4223. goto err;
  4224. }
  4225. /*
  4226. * Mutex protection in case the same MI2S
  4227. * interface using for both TX and RX so
  4228. * that the same clock won't be enable twice.
  4229. */
  4230. mutex_lock(&mi2s_intf_conf[index].lock);
  4231. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4232. /* Check if msm needs to provide the clock to the interface */
  4233. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4234. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4235. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4236. }
  4237. ret = msm_mi2s_set_sclk(substream, true);
  4238. if (ret < 0) {
  4239. dev_err(rtd->card->dev,
  4240. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4241. __func__, ret);
  4242. goto clean_up;
  4243. }
  4244. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4245. if (ret < 0) {
  4246. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4247. __func__, index, ret);
  4248. goto clk_off;
  4249. }
  4250. if (pdata->mi2s_gpio_p[index]) {
  4251. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4252. == 0) {
  4253. ret = msm_cdc_pinctrl_select_active_state(
  4254. pdata->mi2s_gpio_p[index]);
  4255. if (ret) {
  4256. pr_err("%s: MI2S GPIO pinctrl set active failed with %d\n",
  4257. __func__, ret);
  4258. goto clk_off;
  4259. }
  4260. }
  4261. atomic_inc(&(pdata->mi2s_gpio_ref_count[index]));
  4262. }
  4263. }
  4264. clk_off:
  4265. if (ret < 0)
  4266. msm_mi2s_set_sclk(substream, false);
  4267. clean_up:
  4268. if (ret < 0)
  4269. mi2s_intf_conf[index].ref_cnt--;
  4270. mutex_unlock(&mi2s_intf_conf[index].lock);
  4271. err:
  4272. return ret;
  4273. }
  4274. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4275. {
  4276. int ret = 0;
  4277. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4278. int index = rtd->cpu_dai->id;
  4279. struct snd_soc_card *card = rtd->card;
  4280. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4281. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4282. substream->name, substream->stream);
  4283. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4284. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4285. return;
  4286. }
  4287. mutex_lock(&mi2s_intf_conf[index].lock);
  4288. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4289. if (pdata->mi2s_gpio_p[index]) {
  4290. atomic_dec(&(pdata->mi2s_gpio_ref_count[index]));
  4291. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4292. == 0) {
  4293. ret = msm_cdc_pinctrl_select_sleep_state(
  4294. pdata->mi2s_gpio_p[index]);
  4295. if (ret)
  4296. pr_err("%s: MI2S GPIO pinctrl set sleep failed with %d\n",
  4297. __func__, ret);
  4298. }
  4299. }
  4300. ret = msm_mi2s_set_sclk(substream, false);
  4301. if (ret < 0)
  4302. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4303. __func__, index, ret);
  4304. }
  4305. mutex_unlock(&mi2s_intf_conf[index].lock);
  4306. }
  4307. static int msm_wcn_hw_params_lito(struct snd_pcm_substream *substream,
  4308. struct snd_pcm_hw_params *params)
  4309. {
  4310. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4311. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4312. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4313. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4314. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO];
  4315. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4316. int ret = 0;
  4317. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4318. codec_dai->name, codec_dai->id);
  4319. ret = snd_soc_dai_get_channel_map(codec_dai,
  4320. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4321. if (ret) {
  4322. dev_err(rtd->dev,
  4323. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4324. __func__, ret);
  4325. goto err;
  4326. }
  4327. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4328. __func__, tx_ch_cnt, dai_link->id);
  4329. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4330. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4331. if (ret)
  4332. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4333. __func__, ret);
  4334. err:
  4335. return ret;
  4336. }
  4337. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4338. struct snd_pcm_hw_params *params)
  4339. {
  4340. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4341. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4342. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4343. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4344. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4345. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4346. int ret = 0;
  4347. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4348. codec_dai->name, codec_dai->id);
  4349. ret = snd_soc_dai_get_channel_map(codec_dai,
  4350. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4351. if (ret) {
  4352. dev_err(rtd->dev,
  4353. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4354. __func__, ret);
  4355. goto err;
  4356. }
  4357. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4358. __func__, tx_ch_cnt, dai_link->id);
  4359. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4360. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4361. if (ret)
  4362. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4363. __func__, ret);
  4364. err:
  4365. return ret;
  4366. }
  4367. static struct snd_soc_ops kona_aux_be_ops = {
  4368. .startup = kona_aux_snd_startup,
  4369. .shutdown = kona_aux_snd_shutdown
  4370. };
  4371. static struct snd_soc_ops kona_tdm_be_ops = {
  4372. .hw_params = kona_tdm_snd_hw_params,
  4373. .startup = kona_tdm_snd_startup,
  4374. .shutdown = kona_tdm_snd_shutdown
  4375. };
  4376. static struct snd_soc_ops msm_mi2s_be_ops = {
  4377. .startup = msm_mi2s_snd_startup,
  4378. .shutdown = msm_mi2s_snd_shutdown,
  4379. };
  4380. static struct snd_soc_ops msm_fe_qos_ops = {
  4381. .prepare = msm_fe_qos_prepare,
  4382. };
  4383. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4384. .startup = msm_snd_cdc_dma_startup,
  4385. .hw_params = msm_snd_cdc_dma_hw_params,
  4386. };
  4387. static struct snd_soc_ops msm_wcn_ops = {
  4388. .hw_params = msm_wcn_hw_params,
  4389. };
  4390. static struct snd_soc_ops msm_wcn_ops_lito = {
  4391. .hw_params = msm_wcn_hw_params_lito,
  4392. };
  4393. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  4394. struct snd_kcontrol *kcontrol, int event)
  4395. {
  4396. struct msm_asoc_mach_data *pdata = NULL;
  4397. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  4398. int ret = 0;
  4399. u32 dmic_idx;
  4400. int *dmic_gpio_cnt;
  4401. struct device_node *dmic_gpio;
  4402. char *wname;
  4403. wname = strpbrk(w->name, "012345");
  4404. if (!wname) {
  4405. dev_err(component->dev, "%s: widget not found\n", __func__);
  4406. return -EINVAL;
  4407. }
  4408. ret = kstrtouint(wname, 10, &dmic_idx);
  4409. if (ret < 0) {
  4410. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  4411. __func__);
  4412. return -EINVAL;
  4413. }
  4414. pdata = snd_soc_card_get_drvdata(component->card);
  4415. switch (dmic_idx) {
  4416. case 0:
  4417. case 1:
  4418. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  4419. dmic_gpio = pdata->dmic01_gpio_p;
  4420. break;
  4421. case 2:
  4422. case 3:
  4423. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  4424. dmic_gpio = pdata->dmic23_gpio_p;
  4425. break;
  4426. case 4:
  4427. case 5:
  4428. dmic_gpio_cnt = &dmic_4_5_gpio_cnt;
  4429. dmic_gpio = pdata->dmic45_gpio_p;
  4430. break;
  4431. default:
  4432. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  4433. __func__);
  4434. return -EINVAL;
  4435. }
  4436. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  4437. __func__, event, dmic_idx, *dmic_gpio_cnt);
  4438. switch (event) {
  4439. case SND_SOC_DAPM_PRE_PMU:
  4440. (*dmic_gpio_cnt)++;
  4441. if (*dmic_gpio_cnt == 1) {
  4442. ret = msm_cdc_pinctrl_select_active_state(
  4443. dmic_gpio);
  4444. if (ret < 0) {
  4445. pr_err("%s: gpio set cannot be activated %sd",
  4446. __func__, "dmic_gpio");
  4447. return ret;
  4448. }
  4449. }
  4450. break;
  4451. case SND_SOC_DAPM_POST_PMD:
  4452. (*dmic_gpio_cnt)--;
  4453. if (*dmic_gpio_cnt == 0) {
  4454. ret = msm_cdc_pinctrl_select_sleep_state(
  4455. dmic_gpio);
  4456. if (ret < 0) {
  4457. pr_err("%s: gpio set cannot be de-activated %sd",
  4458. __func__, "dmic_gpio");
  4459. return ret;
  4460. }
  4461. }
  4462. break;
  4463. default:
  4464. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  4465. return -EINVAL;
  4466. }
  4467. return 0;
  4468. }
  4469. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  4470. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  4471. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  4472. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  4473. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  4474. SND_SOC_DAPM_MIC("Analog Mic5", NULL),
  4475. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  4476. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  4477. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  4478. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  4479. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  4480. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  4481. SND_SOC_DAPM_MIC("Digital Mic6", NULL),
  4482. SND_SOC_DAPM_MIC("Digital Mic7", NULL),
  4483. };
  4484. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4485. {
  4486. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4487. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160};
  4488. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4489. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4490. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4491. }
  4492. static int msm_wcn_init_lito(struct snd_soc_pcm_runtime *rtd)
  4493. {
  4494. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4495. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO] = {159, 160, 161};
  4496. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4497. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4498. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4499. }
  4500. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4501. {
  4502. int ret = -EINVAL;
  4503. struct snd_soc_component *component;
  4504. struct snd_soc_dapm_context *dapm;
  4505. struct snd_card *card;
  4506. struct snd_info_entry *entry;
  4507. struct snd_soc_component *aux_comp;
  4508. struct msm_asoc_mach_data *pdata =
  4509. snd_soc_card_get_drvdata(rtd->card);
  4510. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4511. if (!component) {
  4512. pr_err("%s: could not find component for bolero_codec\n",
  4513. __func__);
  4514. return ret;
  4515. }
  4516. dapm = snd_soc_component_get_dapm(component);
  4517. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  4518. ARRAY_SIZE(msm_int_snd_controls));
  4519. if (ret < 0) {
  4520. pr_err("%s: add_component_controls failed: %d\n",
  4521. __func__, ret);
  4522. return ret;
  4523. }
  4524. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  4525. ARRAY_SIZE(msm_common_snd_controls));
  4526. if (ret < 0) {
  4527. pr_err("%s: add common snd controls failed: %d\n",
  4528. __func__, ret);
  4529. return ret;
  4530. }
  4531. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  4532. ARRAY_SIZE(msm_int_dapm_widgets));
  4533. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4534. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4535. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4536. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4537. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4538. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4539. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4540. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4541. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  4542. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  4543. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4544. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4545. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
  4546. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4547. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4548. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4549. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4550. snd_soc_dapm_sync(dapm);
  4551. /*
  4552. * Send speaker configuration only for WSA8810.
  4553. * Default configuration is for WSA8815.
  4554. */
  4555. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4556. __func__, rtd->card->num_aux_devs);
  4557. if (rtd->card->num_aux_devs &&
  4558. !list_empty(&rtd->card->component_dev_list)) {
  4559. list_for_each_entry(aux_comp,
  4560. &rtd->card->aux_comp_list,
  4561. card_aux_list) {
  4562. if (aux_comp->name != NULL && (
  4563. !strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4564. !strcmp(aux_comp->name, WSA8810_NAME_2))) {
  4565. wsa_macro_set_spkr_mode(component,
  4566. WSA_MACRO_SPKR_MODE_1);
  4567. wsa_macro_set_spkr_gain_offset(component,
  4568. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4569. }
  4570. }
  4571. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map),
  4572. sm_port_map);
  4573. }
  4574. card = rtd->card->snd_card;
  4575. if (!pdata->codec_root) {
  4576. entry = snd_info_create_subdir(card->module, "codecs",
  4577. card->proc_root);
  4578. if (!entry) {
  4579. pr_debug("%s: Cannot create codecs module entry\n",
  4580. __func__);
  4581. ret = 0;
  4582. goto err;
  4583. }
  4584. pdata->codec_root = entry;
  4585. }
  4586. bolero_info_create_codec_entry(pdata->codec_root, component);
  4587. bolero_register_wake_irq(component, false);
  4588. codec_reg_done = true;
  4589. return 0;
  4590. err:
  4591. return ret;
  4592. }
  4593. static void *def_wcd_mbhc_cal(void)
  4594. {
  4595. void *wcd_mbhc_cal;
  4596. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  4597. u16 *btn_high;
  4598. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  4599. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  4600. if (!wcd_mbhc_cal)
  4601. return NULL;
  4602. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  4603. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  4604. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  4605. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  4606. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  4607. btn_high[0] = 75;
  4608. btn_high[1] = 150;
  4609. btn_high[2] = 237;
  4610. btn_high[3] = 500;
  4611. btn_high[4] = 500;
  4612. btn_high[5] = 500;
  4613. btn_high[6] = 500;
  4614. btn_high[7] = 500;
  4615. return wcd_mbhc_cal;
  4616. }
  4617. /* Digital audio interface glue - connects codec <---> CPU */
  4618. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4619. /* FrontEnd DAI Links */
  4620. {/* hw:x,0 */
  4621. .name = MSM_DAILINK_NAME(Media1),
  4622. .stream_name = "MultiMedia1",
  4623. .cpu_dai_name = "MultiMedia1",
  4624. .platform_name = "msm-pcm-dsp.0",
  4625. .dynamic = 1,
  4626. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4627. .dpcm_playback = 1,
  4628. .dpcm_capture = 1,
  4629. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4630. SND_SOC_DPCM_TRIGGER_POST},
  4631. .codec_dai_name = "snd-soc-dummy-dai",
  4632. .codec_name = "snd-soc-dummy",
  4633. .ignore_suspend = 1,
  4634. /* this dainlink has playback support */
  4635. .ignore_pmdown_time = 1,
  4636. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4637. },
  4638. {/* hw:x,1 */
  4639. .name = MSM_DAILINK_NAME(Media2),
  4640. .stream_name = "MultiMedia2",
  4641. .cpu_dai_name = "MultiMedia2",
  4642. .platform_name = "msm-pcm-dsp.0",
  4643. .dynamic = 1,
  4644. .dpcm_playback = 1,
  4645. .dpcm_capture = 1,
  4646. .codec_dai_name = "snd-soc-dummy-dai",
  4647. .codec_name = "snd-soc-dummy",
  4648. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4649. SND_SOC_DPCM_TRIGGER_POST},
  4650. .ignore_suspend = 1,
  4651. /* this dainlink has playback support */
  4652. .ignore_pmdown_time = 1,
  4653. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4654. },
  4655. {/* hw:x,2 */
  4656. .name = "VoiceMMode1",
  4657. .stream_name = "VoiceMMode1",
  4658. .cpu_dai_name = "VoiceMMode1",
  4659. .platform_name = "msm-pcm-voice",
  4660. .dynamic = 1,
  4661. .dpcm_playback = 1,
  4662. .dpcm_capture = 1,
  4663. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4664. SND_SOC_DPCM_TRIGGER_POST},
  4665. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4666. .ignore_suspend = 1,
  4667. .ignore_pmdown_time = 1,
  4668. .codec_dai_name = "snd-soc-dummy-dai",
  4669. .codec_name = "snd-soc-dummy",
  4670. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4671. },
  4672. {/* hw:x,3 */
  4673. .name = "MSM VoIP",
  4674. .stream_name = "VoIP",
  4675. .cpu_dai_name = "VoIP",
  4676. .platform_name = "msm-voip-dsp",
  4677. .dynamic = 1,
  4678. .dpcm_playback = 1,
  4679. .dpcm_capture = 1,
  4680. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4681. SND_SOC_DPCM_TRIGGER_POST},
  4682. .codec_dai_name = "snd-soc-dummy-dai",
  4683. .codec_name = "snd-soc-dummy",
  4684. .ignore_suspend = 1,
  4685. /* this dainlink has playback support */
  4686. .ignore_pmdown_time = 1,
  4687. .id = MSM_FRONTEND_DAI_VOIP,
  4688. },
  4689. {/* hw:x,4 */
  4690. .name = MSM_DAILINK_NAME(ULL),
  4691. .stream_name = "MultiMedia3",
  4692. .cpu_dai_name = "MultiMedia3",
  4693. .platform_name = "msm-pcm-dsp.2",
  4694. .dynamic = 1,
  4695. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4696. .dpcm_playback = 1,
  4697. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4698. SND_SOC_DPCM_TRIGGER_POST},
  4699. .codec_dai_name = "snd-soc-dummy-dai",
  4700. .codec_name = "snd-soc-dummy",
  4701. .ignore_suspend = 1,
  4702. /* this dainlink has playback support */
  4703. .ignore_pmdown_time = 1,
  4704. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4705. },
  4706. {/* hw:x,5 */
  4707. .name = "MSM AFE-PCM RX",
  4708. .stream_name = "AFE-PROXY RX",
  4709. .cpu_dai_name = "msm-dai-q6-dev.241",
  4710. .codec_name = "msm-stub-codec.1",
  4711. .codec_dai_name = "msm-stub-rx",
  4712. .platform_name = "msm-pcm-afe",
  4713. .dpcm_playback = 1,
  4714. .ignore_suspend = 1,
  4715. /* this dainlink has playback support */
  4716. .ignore_pmdown_time = 1,
  4717. },
  4718. {/* hw:x,6 */
  4719. .name = "MSM AFE-PCM TX",
  4720. .stream_name = "AFE-PROXY TX",
  4721. .cpu_dai_name = "msm-dai-q6-dev.240",
  4722. .codec_name = "msm-stub-codec.1",
  4723. .codec_dai_name = "msm-stub-tx",
  4724. .platform_name = "msm-pcm-afe",
  4725. .dpcm_capture = 1,
  4726. .ignore_suspend = 1,
  4727. },
  4728. {/* hw:x,7 */
  4729. .name = MSM_DAILINK_NAME(Compress1),
  4730. .stream_name = "Compress1",
  4731. .cpu_dai_name = "MultiMedia4",
  4732. .platform_name = "msm-compress-dsp",
  4733. .dynamic = 1,
  4734. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4735. .dpcm_playback = 1,
  4736. .dpcm_capture = 1,
  4737. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4738. SND_SOC_DPCM_TRIGGER_POST},
  4739. .codec_dai_name = "snd-soc-dummy-dai",
  4740. .codec_name = "snd-soc-dummy",
  4741. .ignore_suspend = 1,
  4742. .ignore_pmdown_time = 1,
  4743. /* this dainlink has playback support */
  4744. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4745. },
  4746. /* Hostless PCM purpose */
  4747. {/* hw:x,8 */
  4748. .name = "AUXPCM Hostless",
  4749. .stream_name = "AUXPCM Hostless",
  4750. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4751. .platform_name = "msm-pcm-hostless",
  4752. .dynamic = 1,
  4753. .dpcm_playback = 1,
  4754. .dpcm_capture = 1,
  4755. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4756. SND_SOC_DPCM_TRIGGER_POST},
  4757. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4758. .ignore_suspend = 1,
  4759. /* this dainlink has playback support */
  4760. .ignore_pmdown_time = 1,
  4761. .codec_dai_name = "snd-soc-dummy-dai",
  4762. .codec_name = "snd-soc-dummy",
  4763. },
  4764. {/* hw:x,9 */
  4765. .name = MSM_DAILINK_NAME(LowLatency),
  4766. .stream_name = "MultiMedia5",
  4767. .cpu_dai_name = "MultiMedia5",
  4768. .platform_name = "msm-pcm-dsp.1",
  4769. .dynamic = 1,
  4770. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4771. .dpcm_playback = 1,
  4772. .dpcm_capture = 1,
  4773. .codec_dai_name = "snd-soc-dummy-dai",
  4774. .codec_name = "snd-soc-dummy",
  4775. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4776. SND_SOC_DPCM_TRIGGER_POST},
  4777. .ignore_suspend = 1,
  4778. /* this dainlink has playback support */
  4779. .ignore_pmdown_time = 1,
  4780. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4781. .ops = &msm_fe_qos_ops,
  4782. },
  4783. {/* hw:x,10 */
  4784. .name = "Listen 1 Audio Service",
  4785. .stream_name = "Listen 1 Audio Service",
  4786. .cpu_dai_name = "LSM1",
  4787. .platform_name = "msm-lsm-client",
  4788. .dynamic = 1,
  4789. .dpcm_capture = 1,
  4790. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4791. SND_SOC_DPCM_TRIGGER_POST },
  4792. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4793. .ignore_suspend = 1,
  4794. .codec_dai_name = "snd-soc-dummy-dai",
  4795. .codec_name = "snd-soc-dummy",
  4796. .id = MSM_FRONTEND_DAI_LSM1,
  4797. },
  4798. /* Multiple Tunnel instances */
  4799. {/* hw:x,11 */
  4800. .name = MSM_DAILINK_NAME(Compress2),
  4801. .stream_name = "Compress2",
  4802. .cpu_dai_name = "MultiMedia7",
  4803. .platform_name = "msm-compress-dsp",
  4804. .dynamic = 1,
  4805. .dpcm_playback = 1,
  4806. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4807. SND_SOC_DPCM_TRIGGER_POST},
  4808. .codec_dai_name = "snd-soc-dummy-dai",
  4809. .codec_name = "snd-soc-dummy",
  4810. .ignore_suspend = 1,
  4811. .ignore_pmdown_time = 1,
  4812. /* this dainlink has playback support */
  4813. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4814. },
  4815. {/* hw:x,12 */
  4816. .name = MSM_DAILINK_NAME(MultiMedia10),
  4817. .stream_name = "MultiMedia10",
  4818. .cpu_dai_name = "MultiMedia10",
  4819. .platform_name = "msm-pcm-dsp.1",
  4820. .dynamic = 1,
  4821. .dpcm_playback = 1,
  4822. .dpcm_capture = 1,
  4823. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4824. SND_SOC_DPCM_TRIGGER_POST},
  4825. .codec_dai_name = "snd-soc-dummy-dai",
  4826. .codec_name = "snd-soc-dummy",
  4827. .ignore_suspend = 1,
  4828. .ignore_pmdown_time = 1,
  4829. /* this dainlink has playback support */
  4830. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4831. },
  4832. {/* hw:x,13 */
  4833. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4834. .stream_name = "MM_NOIRQ",
  4835. .cpu_dai_name = "MultiMedia8",
  4836. .platform_name = "msm-pcm-dsp-noirq",
  4837. .dynamic = 1,
  4838. .dpcm_playback = 1,
  4839. .dpcm_capture = 1,
  4840. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4841. SND_SOC_DPCM_TRIGGER_POST},
  4842. .codec_dai_name = "snd-soc-dummy-dai",
  4843. .codec_name = "snd-soc-dummy",
  4844. .ignore_suspend = 1,
  4845. .ignore_pmdown_time = 1,
  4846. /* this dainlink has playback support */
  4847. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4848. .ops = &msm_fe_qos_ops,
  4849. },
  4850. /* HDMI Hostless */
  4851. {/* hw:x,14 */
  4852. .name = "HDMI_RX_HOSTLESS",
  4853. .stream_name = "HDMI_RX_HOSTLESS",
  4854. .cpu_dai_name = "HDMI_HOSTLESS",
  4855. .platform_name = "msm-pcm-hostless",
  4856. .dynamic = 1,
  4857. .dpcm_playback = 1,
  4858. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4859. SND_SOC_DPCM_TRIGGER_POST},
  4860. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4861. .ignore_suspend = 1,
  4862. .ignore_pmdown_time = 1,
  4863. .codec_dai_name = "snd-soc-dummy-dai",
  4864. .codec_name = "snd-soc-dummy",
  4865. },
  4866. {/* hw:x,15 */
  4867. .name = "VoiceMMode2",
  4868. .stream_name = "VoiceMMode2",
  4869. .cpu_dai_name = "VoiceMMode2",
  4870. .platform_name = "msm-pcm-voice",
  4871. .dynamic = 1,
  4872. .dpcm_playback = 1,
  4873. .dpcm_capture = 1,
  4874. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4875. SND_SOC_DPCM_TRIGGER_POST},
  4876. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4877. .ignore_suspend = 1,
  4878. .ignore_pmdown_time = 1,
  4879. .codec_dai_name = "snd-soc-dummy-dai",
  4880. .codec_name = "snd-soc-dummy",
  4881. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4882. },
  4883. /* LSM FE */
  4884. {/* hw:x,16 */
  4885. .name = "Listen 2 Audio Service",
  4886. .stream_name = "Listen 2 Audio Service",
  4887. .cpu_dai_name = "LSM2",
  4888. .platform_name = "msm-lsm-client",
  4889. .dynamic = 1,
  4890. .dpcm_capture = 1,
  4891. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4892. SND_SOC_DPCM_TRIGGER_POST },
  4893. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4894. .ignore_suspend = 1,
  4895. .codec_dai_name = "snd-soc-dummy-dai",
  4896. .codec_name = "snd-soc-dummy",
  4897. .id = MSM_FRONTEND_DAI_LSM2,
  4898. },
  4899. {/* hw:x,17 */
  4900. .name = "Listen 3 Audio Service",
  4901. .stream_name = "Listen 3 Audio Service",
  4902. .cpu_dai_name = "LSM3",
  4903. .platform_name = "msm-lsm-client",
  4904. .dynamic = 1,
  4905. .dpcm_capture = 1,
  4906. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4907. SND_SOC_DPCM_TRIGGER_POST },
  4908. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4909. .ignore_suspend = 1,
  4910. .codec_dai_name = "snd-soc-dummy-dai",
  4911. .codec_name = "snd-soc-dummy",
  4912. .id = MSM_FRONTEND_DAI_LSM3,
  4913. },
  4914. {/* hw:x,18 */
  4915. .name = "Listen 4 Audio Service",
  4916. .stream_name = "Listen 4 Audio Service",
  4917. .cpu_dai_name = "LSM4",
  4918. .platform_name = "msm-lsm-client",
  4919. .dynamic = 1,
  4920. .dpcm_capture = 1,
  4921. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4922. SND_SOC_DPCM_TRIGGER_POST },
  4923. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4924. .ignore_suspend = 1,
  4925. .codec_dai_name = "snd-soc-dummy-dai",
  4926. .codec_name = "snd-soc-dummy",
  4927. .id = MSM_FRONTEND_DAI_LSM4,
  4928. },
  4929. {/* hw:x,19 */
  4930. .name = "Listen 5 Audio Service",
  4931. .stream_name = "Listen 5 Audio Service",
  4932. .cpu_dai_name = "LSM5",
  4933. .platform_name = "msm-lsm-client",
  4934. .dynamic = 1,
  4935. .dpcm_capture = 1,
  4936. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4937. SND_SOC_DPCM_TRIGGER_POST },
  4938. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4939. .ignore_suspend = 1,
  4940. .codec_dai_name = "snd-soc-dummy-dai",
  4941. .codec_name = "snd-soc-dummy",
  4942. .id = MSM_FRONTEND_DAI_LSM5,
  4943. },
  4944. {/* hw:x,20 */
  4945. .name = "Listen 6 Audio Service",
  4946. .stream_name = "Listen 6 Audio Service",
  4947. .cpu_dai_name = "LSM6",
  4948. .platform_name = "msm-lsm-client",
  4949. .dynamic = 1,
  4950. .dpcm_capture = 1,
  4951. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4952. SND_SOC_DPCM_TRIGGER_POST },
  4953. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4954. .ignore_suspend = 1,
  4955. .codec_dai_name = "snd-soc-dummy-dai",
  4956. .codec_name = "snd-soc-dummy",
  4957. .id = MSM_FRONTEND_DAI_LSM6,
  4958. },
  4959. {/* hw:x,21 */
  4960. .name = "Listen 7 Audio Service",
  4961. .stream_name = "Listen 7 Audio Service",
  4962. .cpu_dai_name = "LSM7",
  4963. .platform_name = "msm-lsm-client",
  4964. .dynamic = 1,
  4965. .dpcm_capture = 1,
  4966. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4967. SND_SOC_DPCM_TRIGGER_POST },
  4968. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4969. .ignore_suspend = 1,
  4970. .codec_dai_name = "snd-soc-dummy-dai",
  4971. .codec_name = "snd-soc-dummy",
  4972. .id = MSM_FRONTEND_DAI_LSM7,
  4973. },
  4974. {/* hw:x,22 */
  4975. .name = "Listen 8 Audio Service",
  4976. .stream_name = "Listen 8 Audio Service",
  4977. .cpu_dai_name = "LSM8",
  4978. .platform_name = "msm-lsm-client",
  4979. .dynamic = 1,
  4980. .dpcm_capture = 1,
  4981. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4982. SND_SOC_DPCM_TRIGGER_POST },
  4983. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4984. .ignore_suspend = 1,
  4985. .codec_dai_name = "snd-soc-dummy-dai",
  4986. .codec_name = "snd-soc-dummy",
  4987. .id = MSM_FRONTEND_DAI_LSM8,
  4988. },
  4989. {/* hw:x,23 */
  4990. .name = MSM_DAILINK_NAME(Media9),
  4991. .stream_name = "MultiMedia9",
  4992. .cpu_dai_name = "MultiMedia9",
  4993. .platform_name = "msm-pcm-dsp.0",
  4994. .dynamic = 1,
  4995. .dpcm_playback = 1,
  4996. .dpcm_capture = 1,
  4997. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4998. SND_SOC_DPCM_TRIGGER_POST},
  4999. .codec_dai_name = "snd-soc-dummy-dai",
  5000. .codec_name = "snd-soc-dummy",
  5001. .ignore_suspend = 1,
  5002. /* this dainlink has playback support */
  5003. .ignore_pmdown_time = 1,
  5004. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5005. },
  5006. {/* hw:x,24 */
  5007. .name = MSM_DAILINK_NAME(Compress4),
  5008. .stream_name = "Compress4",
  5009. .cpu_dai_name = "MultiMedia11",
  5010. .platform_name = "msm-compress-dsp",
  5011. .dynamic = 1,
  5012. .dpcm_playback = 1,
  5013. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5014. SND_SOC_DPCM_TRIGGER_POST},
  5015. .codec_dai_name = "snd-soc-dummy-dai",
  5016. .codec_name = "snd-soc-dummy",
  5017. .ignore_suspend = 1,
  5018. .ignore_pmdown_time = 1,
  5019. /* this dainlink has playback support */
  5020. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5021. },
  5022. {/* hw:x,25 */
  5023. .name = MSM_DAILINK_NAME(Compress5),
  5024. .stream_name = "Compress5",
  5025. .cpu_dai_name = "MultiMedia12",
  5026. .platform_name = "msm-compress-dsp",
  5027. .dynamic = 1,
  5028. .dpcm_playback = 1,
  5029. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5030. SND_SOC_DPCM_TRIGGER_POST},
  5031. .codec_dai_name = "snd-soc-dummy-dai",
  5032. .codec_name = "snd-soc-dummy",
  5033. .ignore_suspend = 1,
  5034. .ignore_pmdown_time = 1,
  5035. /* this dainlink has playback support */
  5036. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5037. },
  5038. {/* hw:x,26 */
  5039. .name = MSM_DAILINK_NAME(Compress6),
  5040. .stream_name = "Compress6",
  5041. .cpu_dai_name = "MultiMedia13",
  5042. .platform_name = "msm-compress-dsp",
  5043. .dynamic = 1,
  5044. .dpcm_playback = 1,
  5045. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5046. SND_SOC_DPCM_TRIGGER_POST},
  5047. .codec_dai_name = "snd-soc-dummy-dai",
  5048. .codec_name = "snd-soc-dummy",
  5049. .ignore_suspend = 1,
  5050. .ignore_pmdown_time = 1,
  5051. /* this dainlink has playback support */
  5052. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5053. },
  5054. {/* hw:x,27 */
  5055. .name = MSM_DAILINK_NAME(Compress7),
  5056. .stream_name = "Compress7",
  5057. .cpu_dai_name = "MultiMedia14",
  5058. .platform_name = "msm-compress-dsp",
  5059. .dynamic = 1,
  5060. .dpcm_playback = 1,
  5061. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5062. SND_SOC_DPCM_TRIGGER_POST},
  5063. .codec_dai_name = "snd-soc-dummy-dai",
  5064. .codec_name = "snd-soc-dummy",
  5065. .ignore_suspend = 1,
  5066. .ignore_pmdown_time = 1,
  5067. /* this dainlink has playback support */
  5068. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5069. },
  5070. {/* hw:x,28 */
  5071. .name = MSM_DAILINK_NAME(Compress8),
  5072. .stream_name = "Compress8",
  5073. .cpu_dai_name = "MultiMedia15",
  5074. .platform_name = "msm-compress-dsp",
  5075. .dynamic = 1,
  5076. .dpcm_playback = 1,
  5077. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5078. SND_SOC_DPCM_TRIGGER_POST},
  5079. .codec_dai_name = "snd-soc-dummy-dai",
  5080. .codec_name = "snd-soc-dummy",
  5081. .ignore_suspend = 1,
  5082. .ignore_pmdown_time = 1,
  5083. /* this dainlink has playback support */
  5084. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5085. },
  5086. {/* hw:x,29 */
  5087. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5088. .stream_name = "MM_NOIRQ_2",
  5089. .cpu_dai_name = "MultiMedia16",
  5090. .platform_name = "msm-pcm-dsp-noirq",
  5091. .dynamic = 1,
  5092. .dpcm_playback = 1,
  5093. .dpcm_capture = 1,
  5094. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5095. SND_SOC_DPCM_TRIGGER_POST},
  5096. .codec_dai_name = "snd-soc-dummy-dai",
  5097. .codec_name = "snd-soc-dummy",
  5098. .ignore_suspend = 1,
  5099. .ignore_pmdown_time = 1,
  5100. /* this dainlink has playback support */
  5101. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5102. .ops = &msm_fe_qos_ops,
  5103. },
  5104. {/* hw:x,30 */
  5105. .name = "CDC_DMA Hostless",
  5106. .stream_name = "CDC_DMA Hostless",
  5107. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5108. .platform_name = "msm-pcm-hostless",
  5109. .dynamic = 1,
  5110. .dpcm_playback = 1,
  5111. .dpcm_capture = 1,
  5112. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5113. SND_SOC_DPCM_TRIGGER_POST},
  5114. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5115. .ignore_suspend = 1,
  5116. /* this dailink has playback support */
  5117. .ignore_pmdown_time = 1,
  5118. .codec_dai_name = "snd-soc-dummy-dai",
  5119. .codec_name = "snd-soc-dummy",
  5120. },
  5121. {/* hw:x,31 */
  5122. .name = "TX3_CDC_DMA Hostless",
  5123. .stream_name = "TX3_CDC_DMA Hostless",
  5124. .cpu_dai_name = "TX3_CDC_DMA_HOSTLESS",
  5125. .platform_name = "msm-pcm-hostless",
  5126. .dynamic = 1,
  5127. .dpcm_capture = 1,
  5128. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5129. SND_SOC_DPCM_TRIGGER_POST},
  5130. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5131. .ignore_suspend = 1,
  5132. .codec_dai_name = "snd-soc-dummy-dai",
  5133. .codec_name = "snd-soc-dummy",
  5134. },
  5135. {/* hw:x,32 */
  5136. .name = "Tertiary MI2S TX_Hostless",
  5137. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  5138. .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
  5139. .platform_name = "msm-pcm-hostless",
  5140. .dynamic = 1,
  5141. .dpcm_capture = 1,
  5142. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5143. SND_SOC_DPCM_TRIGGER_POST},
  5144. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5145. .ignore_suspend = 1,
  5146. .ignore_pmdown_time = 1,
  5147. .codec_dai_name = "snd-soc-dummy-dai",
  5148. .codec_name = "snd-soc-dummy",
  5149. },
  5150. };
  5151. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5152. {/* hw:x,33 */
  5153. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5154. .stream_name = "WSA CDC DMA0 Capture",
  5155. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5156. .platform_name = "msm-pcm-hostless",
  5157. .codec_name = "bolero_codec",
  5158. .codec_dai_name = "wsa_macro_vifeedback",
  5159. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5160. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5161. .ignore_suspend = 1,
  5162. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5163. .ops = &msm_cdc_dma_be_ops,
  5164. },
  5165. };
  5166. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5167. {/* hw:x,34 */
  5168. .name = MSM_DAILINK_NAME(ASM Loopback),
  5169. .stream_name = "MultiMedia6",
  5170. .cpu_dai_name = "MultiMedia6",
  5171. .platform_name = "msm-pcm-loopback",
  5172. .dynamic = 1,
  5173. .dpcm_playback = 1,
  5174. .dpcm_capture = 1,
  5175. .codec_dai_name = "snd-soc-dummy-dai",
  5176. .codec_name = "snd-soc-dummy",
  5177. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5178. SND_SOC_DPCM_TRIGGER_POST},
  5179. .ignore_suspend = 1,
  5180. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5181. .ignore_pmdown_time = 1,
  5182. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5183. },
  5184. {/* hw:x,35 */
  5185. .name = "USB Audio Hostless",
  5186. .stream_name = "USB Audio Hostless",
  5187. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5188. .platform_name = "msm-pcm-hostless",
  5189. .dynamic = 1,
  5190. .dpcm_playback = 1,
  5191. .dpcm_capture = 1,
  5192. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5193. SND_SOC_DPCM_TRIGGER_POST},
  5194. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5195. .ignore_suspend = 1,
  5196. .ignore_pmdown_time = 1,
  5197. .codec_dai_name = "snd-soc-dummy-dai",
  5198. .codec_name = "snd-soc-dummy",
  5199. },
  5200. {/* hw:x,36 */
  5201. .name = "SLIMBUS_7 Hostless",
  5202. .stream_name = "SLIMBUS_7 Hostless",
  5203. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5204. .platform_name = "msm-pcm-hostless",
  5205. .dynamic = 1,
  5206. .dpcm_capture = 1,
  5207. .dpcm_playback = 1,
  5208. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5209. SND_SOC_DPCM_TRIGGER_POST},
  5210. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5211. .ignore_suspend = 1,
  5212. .ignore_pmdown_time = 1,
  5213. .codec_dai_name = "snd-soc-dummy-dai",
  5214. .codec_name = "snd-soc-dummy",
  5215. },
  5216. {/* hw:x,37 */
  5217. .name = "Compress Capture",
  5218. .stream_name = "Compress9",
  5219. .cpu_dai_name = "MultiMedia17",
  5220. .platform_name = "msm-compress-dsp",
  5221. .dynamic = 1,
  5222. .dpcm_capture = 1,
  5223. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5224. SND_SOC_DPCM_TRIGGER_POST},
  5225. .codec_dai_name = "snd-soc-dummy-dai",
  5226. .codec_name = "snd-soc-dummy",
  5227. .ignore_suspend = 1,
  5228. .ignore_pmdown_time = 1,
  5229. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  5230. },
  5231. {/* hw:x,38 */
  5232. .name = "SLIMBUS_8 Hostless",
  5233. .stream_name = "SLIMBUS_8 Hostless",
  5234. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5235. .platform_name = "msm-pcm-hostless",
  5236. .dynamic = 1,
  5237. .dpcm_capture = 1,
  5238. .dpcm_playback = 1,
  5239. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5240. SND_SOC_DPCM_TRIGGER_POST},
  5241. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5242. .ignore_suspend = 1,
  5243. .ignore_pmdown_time = 1,
  5244. .codec_dai_name = "snd-soc-dummy-dai",
  5245. .codec_name = "snd-soc-dummy",
  5246. },
  5247. {/* hw:x,39 */
  5248. .name = LPASS_BE_TX_CDC_DMA_TX_5,
  5249. .stream_name = "TX CDC DMA5 Capture",
  5250. .cpu_dai_name = "msm-dai-cdc-dma-dev.45115",
  5251. .platform_name = "msm-pcm-hostless",
  5252. .codec_name = "bolero_codec",
  5253. .codec_dai_name = "tx_macro_tx3",
  5254. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_5,
  5255. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5256. .ignore_suspend = 1,
  5257. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5258. .ops = &msm_cdc_dma_be_ops,
  5259. },
  5260. };
  5261. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5262. /* Backend AFE DAI Links */
  5263. {
  5264. .name = LPASS_BE_AFE_PCM_RX,
  5265. .stream_name = "AFE Playback",
  5266. .cpu_dai_name = "msm-dai-q6-dev.224",
  5267. .platform_name = "msm-pcm-routing",
  5268. .codec_name = "msm-stub-codec.1",
  5269. .codec_dai_name = "msm-stub-rx",
  5270. .no_pcm = 1,
  5271. .dpcm_playback = 1,
  5272. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5273. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5274. /* this dainlink has playback support */
  5275. .ignore_pmdown_time = 1,
  5276. .ignore_suspend = 1,
  5277. },
  5278. {
  5279. .name = LPASS_BE_AFE_PCM_TX,
  5280. .stream_name = "AFE Capture",
  5281. .cpu_dai_name = "msm-dai-q6-dev.225",
  5282. .platform_name = "msm-pcm-routing",
  5283. .codec_name = "msm-stub-codec.1",
  5284. .codec_dai_name = "msm-stub-tx",
  5285. .no_pcm = 1,
  5286. .dpcm_capture = 1,
  5287. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5288. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5289. .ignore_suspend = 1,
  5290. },
  5291. /* Incall Record Uplink BACK END DAI Link */
  5292. {
  5293. .name = LPASS_BE_INCALL_RECORD_TX,
  5294. .stream_name = "Voice Uplink Capture",
  5295. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5296. .platform_name = "msm-pcm-routing",
  5297. .codec_name = "msm-stub-codec.1",
  5298. .codec_dai_name = "msm-stub-tx",
  5299. .no_pcm = 1,
  5300. .dpcm_capture = 1,
  5301. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5302. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5303. .ignore_suspend = 1,
  5304. },
  5305. /* Incall Record Downlink BACK END DAI Link */
  5306. {
  5307. .name = LPASS_BE_INCALL_RECORD_RX,
  5308. .stream_name = "Voice Downlink Capture",
  5309. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5310. .platform_name = "msm-pcm-routing",
  5311. .codec_name = "msm-stub-codec.1",
  5312. .codec_dai_name = "msm-stub-tx",
  5313. .no_pcm = 1,
  5314. .dpcm_capture = 1,
  5315. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5316. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5317. .ignore_suspend = 1,
  5318. },
  5319. /* Incall Music BACK END DAI Link */
  5320. {
  5321. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5322. .stream_name = "Voice Farend Playback",
  5323. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5324. .platform_name = "msm-pcm-routing",
  5325. .codec_name = "msm-stub-codec.1",
  5326. .codec_dai_name = "msm-stub-rx",
  5327. .no_pcm = 1,
  5328. .dpcm_playback = 1,
  5329. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5330. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5331. .ignore_suspend = 1,
  5332. .ignore_pmdown_time = 1,
  5333. },
  5334. /* Incall Music 2 BACK END DAI Link */
  5335. {
  5336. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5337. .stream_name = "Voice2 Farend Playback",
  5338. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5339. .platform_name = "msm-pcm-routing",
  5340. .codec_name = "msm-stub-codec.1",
  5341. .codec_dai_name = "msm-stub-rx",
  5342. .no_pcm = 1,
  5343. .dpcm_playback = 1,
  5344. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5345. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5346. .ignore_suspend = 1,
  5347. .ignore_pmdown_time = 1,
  5348. },
  5349. {
  5350. .name = LPASS_BE_USB_AUDIO_RX,
  5351. .stream_name = "USB Audio Playback",
  5352. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5353. .platform_name = "msm-pcm-routing",
  5354. .codec_name = "msm-stub-codec.1",
  5355. .codec_dai_name = "msm-stub-rx",
  5356. .dynamic_be = 1,
  5357. .no_pcm = 1,
  5358. .dpcm_playback = 1,
  5359. .id = MSM_BACKEND_DAI_USB_RX,
  5360. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5361. .ignore_pmdown_time = 1,
  5362. .ignore_suspend = 1,
  5363. },
  5364. {
  5365. .name = LPASS_BE_USB_AUDIO_TX,
  5366. .stream_name = "USB Audio Capture",
  5367. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5368. .platform_name = "msm-pcm-routing",
  5369. .codec_name = "msm-stub-codec.1",
  5370. .codec_dai_name = "msm-stub-tx",
  5371. .no_pcm = 1,
  5372. .dpcm_capture = 1,
  5373. .id = MSM_BACKEND_DAI_USB_TX,
  5374. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5375. .ignore_suspend = 1,
  5376. },
  5377. {
  5378. .name = LPASS_BE_PRI_TDM_RX_0,
  5379. .stream_name = "Primary TDM0 Playback",
  5380. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5381. .platform_name = "msm-pcm-routing",
  5382. .codec_name = "msm-stub-codec.1",
  5383. .codec_dai_name = "msm-stub-rx",
  5384. .no_pcm = 1,
  5385. .dpcm_playback = 1,
  5386. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5387. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5388. .ops = &kona_tdm_be_ops,
  5389. .ignore_suspend = 1,
  5390. .ignore_pmdown_time = 1,
  5391. },
  5392. {
  5393. .name = LPASS_BE_PRI_TDM_TX_0,
  5394. .stream_name = "Primary TDM0 Capture",
  5395. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5396. .platform_name = "msm-pcm-routing",
  5397. .codec_name = "msm-stub-codec.1",
  5398. .codec_dai_name = "msm-stub-tx",
  5399. .no_pcm = 1,
  5400. .dpcm_capture = 1,
  5401. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5402. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5403. .ops = &kona_tdm_be_ops,
  5404. .ignore_suspend = 1,
  5405. },
  5406. {
  5407. .name = LPASS_BE_SEC_TDM_RX_0,
  5408. .stream_name = "Secondary TDM0 Playback",
  5409. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5410. .platform_name = "msm-pcm-routing",
  5411. .codec_name = "msm-stub-codec.1",
  5412. .codec_dai_name = "msm-stub-rx",
  5413. .no_pcm = 1,
  5414. .dpcm_playback = 1,
  5415. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5416. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5417. .ops = &kona_tdm_be_ops,
  5418. .ignore_suspend = 1,
  5419. .ignore_pmdown_time = 1,
  5420. },
  5421. {
  5422. .name = LPASS_BE_SEC_TDM_TX_0,
  5423. .stream_name = "Secondary TDM0 Capture",
  5424. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5425. .platform_name = "msm-pcm-routing",
  5426. .codec_name = "msm-stub-codec.1",
  5427. .codec_dai_name = "msm-stub-tx",
  5428. .no_pcm = 1,
  5429. .dpcm_capture = 1,
  5430. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5431. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5432. .ops = &kona_tdm_be_ops,
  5433. .ignore_suspend = 1,
  5434. },
  5435. {
  5436. .name = LPASS_BE_TERT_TDM_RX_0,
  5437. .stream_name = "Tertiary TDM0 Playback",
  5438. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5439. .platform_name = "msm-pcm-routing",
  5440. .codec_name = "msm-stub-codec.1",
  5441. .codec_dai_name = "msm-stub-rx",
  5442. .no_pcm = 1,
  5443. .dpcm_playback = 1,
  5444. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5445. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5446. .ops = &kona_tdm_be_ops,
  5447. .ignore_suspend = 1,
  5448. .ignore_pmdown_time = 1,
  5449. },
  5450. {
  5451. .name = LPASS_BE_TERT_TDM_TX_0,
  5452. .stream_name = "Tertiary TDM0 Capture",
  5453. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5454. .platform_name = "msm-pcm-routing",
  5455. .codec_name = "msm-stub-codec.1",
  5456. .codec_dai_name = "msm-stub-tx",
  5457. .no_pcm = 1,
  5458. .dpcm_capture = 1,
  5459. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5460. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5461. .ops = &kona_tdm_be_ops,
  5462. .ignore_suspend = 1,
  5463. },
  5464. {
  5465. .name = LPASS_BE_QUAT_TDM_RX_0,
  5466. .stream_name = "Quaternary TDM0 Playback",
  5467. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5468. .platform_name = "msm-pcm-routing",
  5469. .codec_name = "msm-stub-codec.1",
  5470. .codec_dai_name = "msm-stub-rx",
  5471. .no_pcm = 1,
  5472. .dpcm_playback = 1,
  5473. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5474. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5475. .ops = &kona_tdm_be_ops,
  5476. .ignore_suspend = 1,
  5477. .ignore_pmdown_time = 1,
  5478. },
  5479. {
  5480. .name = LPASS_BE_QUAT_TDM_TX_0,
  5481. .stream_name = "Quaternary TDM0 Capture",
  5482. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5483. .platform_name = "msm-pcm-routing",
  5484. .codec_name = "msm-stub-codec.1",
  5485. .codec_dai_name = "msm-stub-tx",
  5486. .no_pcm = 1,
  5487. .dpcm_capture = 1,
  5488. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5489. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5490. .ops = &kona_tdm_be_ops,
  5491. .ignore_suspend = 1,
  5492. },
  5493. {
  5494. .name = LPASS_BE_QUIN_TDM_RX_0,
  5495. .stream_name = "Quinary TDM0 Playback",
  5496. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5497. .platform_name = "msm-pcm-routing",
  5498. .codec_name = "msm-stub-codec.1",
  5499. .codec_dai_name = "msm-stub-rx",
  5500. .no_pcm = 1,
  5501. .dpcm_playback = 1,
  5502. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5503. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5504. .ops = &kona_tdm_be_ops,
  5505. .ignore_suspend = 1,
  5506. .ignore_pmdown_time = 1,
  5507. },
  5508. {
  5509. .name = LPASS_BE_QUIN_TDM_TX_0,
  5510. .stream_name = "Quinary TDM0 Capture",
  5511. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5512. .platform_name = "msm-pcm-routing",
  5513. .codec_name = "msm-stub-codec.1",
  5514. .codec_dai_name = "msm-stub-tx",
  5515. .no_pcm = 1,
  5516. .dpcm_capture = 1,
  5517. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5518. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5519. .ops = &kona_tdm_be_ops,
  5520. .ignore_suspend = 1,
  5521. },
  5522. {
  5523. .name = LPASS_BE_SEN_TDM_RX_0,
  5524. .stream_name = "Senary TDM0 Playback",
  5525. .cpu_dai_name = "msm-dai-q6-tdm.36944",
  5526. .platform_name = "msm-pcm-routing",
  5527. .codec_name = "msm-stub-codec.1",
  5528. .codec_dai_name = "msm-stub-rx",
  5529. .no_pcm = 1,
  5530. .dpcm_playback = 1,
  5531. .id = MSM_BACKEND_DAI_SEN_TDM_RX_0,
  5532. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5533. .ops = &kona_tdm_be_ops,
  5534. .ignore_suspend = 1,
  5535. .ignore_pmdown_time = 1,
  5536. },
  5537. {
  5538. .name = LPASS_BE_SEN_TDM_TX_0,
  5539. .stream_name = "Senary TDM0 Capture",
  5540. .cpu_dai_name = "msm-dai-q6-tdm.36945",
  5541. .platform_name = "msm-pcm-routing",
  5542. .codec_name = "msm-stub-codec.1",
  5543. .codec_dai_name = "msm-stub-tx",
  5544. .no_pcm = 1,
  5545. .dpcm_capture = 1,
  5546. .id = MSM_BACKEND_DAI_SEN_TDM_TX_0,
  5547. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5548. .ops = &kona_tdm_be_ops,
  5549. .ignore_suspend = 1,
  5550. },
  5551. };
  5552. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5553. {
  5554. .name = LPASS_BE_SLIMBUS_7_RX,
  5555. .stream_name = "Slimbus7 Playback",
  5556. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5557. .platform_name = "msm-pcm-routing",
  5558. .codec_name = "btfmslim_slave",
  5559. /* BT codec driver determines capabilities based on
  5560. * dai name, bt codecdai name should always contains
  5561. * supported usecase information
  5562. */
  5563. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5564. .no_pcm = 1,
  5565. .dpcm_playback = 1,
  5566. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5567. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5568. .init = &msm_wcn_init,
  5569. .ops = &msm_wcn_ops,
  5570. /* dai link has playback support */
  5571. .ignore_pmdown_time = 1,
  5572. .ignore_suspend = 1,
  5573. },
  5574. {
  5575. .name = LPASS_BE_SLIMBUS_7_TX,
  5576. .stream_name = "Slimbus7 Capture",
  5577. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5578. .platform_name = "msm-pcm-routing",
  5579. .codec_name = "btfmslim_slave",
  5580. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5581. .no_pcm = 1,
  5582. .dpcm_capture = 1,
  5583. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5584. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5585. .ops = &msm_wcn_ops,
  5586. .ignore_suspend = 1,
  5587. },
  5588. };
  5589. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  5590. {
  5591. .name = LPASS_BE_SLIMBUS_7_RX,
  5592. .stream_name = "Slimbus7 Playback",
  5593. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5594. .platform_name = "msm-pcm-routing",
  5595. .codec_name = "btfmslim_slave",
  5596. /* BT codec driver determines capabilities based on
  5597. * dai name, bt codecdai name should always contains
  5598. * supported usecase information
  5599. */
  5600. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5601. .no_pcm = 1,
  5602. .dpcm_playback = 1,
  5603. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5604. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5605. .init = &msm_wcn_init_lito,
  5606. .ops = &msm_wcn_ops_lito,
  5607. /* dai link has playback support */
  5608. .ignore_pmdown_time = 1,
  5609. .ignore_suspend = 1,
  5610. },
  5611. {
  5612. .name = LPASS_BE_SLIMBUS_7_TX,
  5613. .stream_name = "Slimbus7 Capture",
  5614. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5615. .platform_name = "msm-pcm-routing",
  5616. .codec_name = "btfmslim_slave",
  5617. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5618. .no_pcm = 1,
  5619. .dpcm_capture = 1,
  5620. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5621. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5622. .ops = &msm_wcn_ops_lito,
  5623. .ignore_suspend = 1,
  5624. },
  5625. {
  5626. .name = LPASS_BE_SLIMBUS_8_TX,
  5627. .stream_name = "Slimbus8 Capture",
  5628. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5629. .platform_name = "msm-pcm-routing",
  5630. .codec_name = "btfmslim_slave",
  5631. .codec_dai_name = "btfm_fm_slim_tx",
  5632. .no_pcm = 1,
  5633. .dpcm_capture = 1,
  5634. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5635. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5636. .ops = &msm_wcn_ops_lito,
  5637. .ignore_suspend = 1,
  5638. },
  5639. };
  5640. static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
  5641. /* DISP PORT BACK END DAI Link */
  5642. {
  5643. .name = LPASS_BE_DISPLAY_PORT,
  5644. .stream_name = "Display Port Playback",
  5645. .cpu_dai_name = "msm-dai-q6-dp.0",
  5646. .platform_name = "msm-pcm-routing",
  5647. .codec_name = "msm-ext-disp-audio-codec-rx",
  5648. .codec_dai_name = "msm_dp_audio_codec_rx_dai",
  5649. .no_pcm = 1,
  5650. .dpcm_playback = 1,
  5651. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
  5652. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5653. .ignore_pmdown_time = 1,
  5654. .ignore_suspend = 1,
  5655. },
  5656. /* DISP PORT 1 BACK END DAI Link */
  5657. {
  5658. .name = LPASS_BE_DISPLAY_PORT1,
  5659. .stream_name = "Display Port1 Playback",
  5660. .cpu_dai_name = "msm-dai-q6-dp.1",
  5661. .platform_name = "msm-pcm-routing",
  5662. .codec_name = "msm-ext-disp-audio-codec-rx",
  5663. .codec_dai_name = "msm_dp_audio_codec_rx1_dai",
  5664. .no_pcm = 1,
  5665. .dpcm_playback = 1,
  5666. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX_1,
  5667. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5668. .ignore_pmdown_time = 1,
  5669. .ignore_suspend = 1,
  5670. },
  5671. };
  5672. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5673. {
  5674. .name = LPASS_BE_PRI_MI2S_RX,
  5675. .stream_name = "Primary MI2S Playback",
  5676. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5677. .platform_name = "msm-pcm-routing",
  5678. .codec_name = "msm-stub-codec.1",
  5679. .codec_dai_name = "msm-stub-rx",
  5680. .no_pcm = 1,
  5681. .dpcm_playback = 1,
  5682. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5683. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5684. .ops = &msm_mi2s_be_ops,
  5685. .ignore_suspend = 1,
  5686. .ignore_pmdown_time = 1,
  5687. },
  5688. {
  5689. .name = LPASS_BE_PRI_MI2S_TX,
  5690. .stream_name = "Primary MI2S Capture",
  5691. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5692. .platform_name = "msm-pcm-routing",
  5693. .codec_name = "msm-stub-codec.1",
  5694. .codec_dai_name = "msm-stub-tx",
  5695. .no_pcm = 1,
  5696. .dpcm_capture = 1,
  5697. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5698. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5699. .ops = &msm_mi2s_be_ops,
  5700. .ignore_suspend = 1,
  5701. },
  5702. {
  5703. .name = LPASS_BE_SEC_MI2S_RX,
  5704. .stream_name = "Secondary MI2S Playback",
  5705. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5706. .platform_name = "msm-pcm-routing",
  5707. .codec_name = "msm-stub-codec.1",
  5708. .codec_dai_name = "msm-stub-rx",
  5709. .no_pcm = 1,
  5710. .dpcm_playback = 1,
  5711. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5712. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5713. .ops = &msm_mi2s_be_ops,
  5714. .ignore_suspend = 1,
  5715. .ignore_pmdown_time = 1,
  5716. },
  5717. {
  5718. .name = LPASS_BE_SEC_MI2S_TX,
  5719. .stream_name = "Secondary MI2S Capture",
  5720. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5721. .platform_name = "msm-pcm-routing",
  5722. .codec_name = "msm-stub-codec.1",
  5723. .codec_dai_name = "msm-stub-tx",
  5724. .no_pcm = 1,
  5725. .dpcm_capture = 1,
  5726. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5727. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5728. .ops = &msm_mi2s_be_ops,
  5729. .ignore_suspend = 1,
  5730. },
  5731. {
  5732. .name = LPASS_BE_TERT_MI2S_RX,
  5733. .stream_name = "Tertiary MI2S Playback",
  5734. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5735. .platform_name = "msm-pcm-routing",
  5736. .codec_name = "msm-stub-codec.1",
  5737. .codec_dai_name = "msm-stub-rx",
  5738. .no_pcm = 1,
  5739. .dpcm_playback = 1,
  5740. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5741. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5742. .ops = &msm_mi2s_be_ops,
  5743. .ignore_suspend = 1,
  5744. .ignore_pmdown_time = 1,
  5745. },
  5746. {
  5747. .name = LPASS_BE_TERT_MI2S_TX,
  5748. .stream_name = "Tertiary MI2S Capture",
  5749. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5750. .platform_name = "msm-pcm-routing",
  5751. .codec_name = "msm-stub-codec.1",
  5752. .codec_dai_name = "msm-stub-tx",
  5753. .no_pcm = 1,
  5754. .dpcm_capture = 1,
  5755. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5756. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5757. .ops = &msm_mi2s_be_ops,
  5758. .ignore_suspend = 1,
  5759. },
  5760. {
  5761. .name = LPASS_BE_QUAT_MI2S_RX,
  5762. .stream_name = "Quaternary MI2S Playback",
  5763. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5764. .platform_name = "msm-pcm-routing",
  5765. .codec_name = "msm-stub-codec.1",
  5766. .codec_dai_name = "msm-stub-rx",
  5767. .no_pcm = 1,
  5768. .dpcm_playback = 1,
  5769. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5770. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5771. .ops = &msm_mi2s_be_ops,
  5772. .ignore_suspend = 1,
  5773. .ignore_pmdown_time = 1,
  5774. },
  5775. {
  5776. .name = LPASS_BE_QUAT_MI2S_TX,
  5777. .stream_name = "Quaternary MI2S Capture",
  5778. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5779. .platform_name = "msm-pcm-routing",
  5780. .codec_name = "msm-stub-codec.1",
  5781. .codec_dai_name = "msm-stub-tx",
  5782. .no_pcm = 1,
  5783. .dpcm_capture = 1,
  5784. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5785. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5786. .ops = &msm_mi2s_be_ops,
  5787. .ignore_suspend = 1,
  5788. },
  5789. {
  5790. .name = LPASS_BE_QUIN_MI2S_RX,
  5791. .stream_name = "Quinary MI2S Playback",
  5792. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5793. .platform_name = "msm-pcm-routing",
  5794. .codec_name = "msm-stub-codec.1",
  5795. .codec_dai_name = "msm-stub-rx",
  5796. .no_pcm = 1,
  5797. .dpcm_playback = 1,
  5798. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5799. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5800. .ops = &msm_mi2s_be_ops,
  5801. .ignore_suspend = 1,
  5802. .ignore_pmdown_time = 1,
  5803. },
  5804. {
  5805. .name = LPASS_BE_QUIN_MI2S_TX,
  5806. .stream_name = "Quinary MI2S Capture",
  5807. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5808. .platform_name = "msm-pcm-routing",
  5809. .codec_name = "msm-stub-codec.1",
  5810. .codec_dai_name = "msm-stub-tx",
  5811. .no_pcm = 1,
  5812. .dpcm_capture = 1,
  5813. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5814. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5815. .ops = &msm_mi2s_be_ops,
  5816. .ignore_suspend = 1,
  5817. },
  5818. {
  5819. .name = LPASS_BE_SENARY_MI2S_RX,
  5820. .stream_name = "Senary MI2S Playback",
  5821. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  5822. .platform_name = "msm-pcm-routing",
  5823. .codec_name = "msm-stub-codec.1",
  5824. .codec_dai_name = "msm-stub-rx",
  5825. .no_pcm = 1,
  5826. .dpcm_playback = 1,
  5827. .id = MSM_BACKEND_DAI_SENARY_MI2S_RX,
  5828. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5829. .ops = &msm_mi2s_be_ops,
  5830. .ignore_suspend = 1,
  5831. .ignore_pmdown_time = 1,
  5832. },
  5833. {
  5834. .name = LPASS_BE_SENARY_MI2S_TX,
  5835. .stream_name = "Senary MI2S Capture",
  5836. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  5837. .platform_name = "msm-pcm-routing",
  5838. .codec_name = "msm-stub-codec.1",
  5839. .codec_dai_name = "msm-stub-tx",
  5840. .no_pcm = 1,
  5841. .dpcm_capture = 1,
  5842. .id = MSM_BACKEND_DAI_SENARY_MI2S_TX,
  5843. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5844. .ops = &msm_mi2s_be_ops,
  5845. .ignore_suspend = 1,
  5846. },
  5847. };
  5848. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5849. /* Primary AUX PCM Backend DAI Links */
  5850. {
  5851. .name = LPASS_BE_AUXPCM_RX,
  5852. .stream_name = "AUX PCM Playback",
  5853. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5854. .platform_name = "msm-pcm-routing",
  5855. .codec_name = "msm-stub-codec.1",
  5856. .codec_dai_name = "msm-stub-rx",
  5857. .no_pcm = 1,
  5858. .dpcm_playback = 1,
  5859. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5860. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5861. .ops = &kona_aux_be_ops,
  5862. .ignore_pmdown_time = 1,
  5863. .ignore_suspend = 1,
  5864. },
  5865. {
  5866. .name = LPASS_BE_AUXPCM_TX,
  5867. .stream_name = "AUX PCM Capture",
  5868. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5869. .platform_name = "msm-pcm-routing",
  5870. .codec_name = "msm-stub-codec.1",
  5871. .codec_dai_name = "msm-stub-tx",
  5872. .no_pcm = 1,
  5873. .dpcm_capture = 1,
  5874. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5875. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5876. .ops = &kona_aux_be_ops,
  5877. .ignore_suspend = 1,
  5878. },
  5879. /* Secondary AUX PCM Backend DAI Links */
  5880. {
  5881. .name = LPASS_BE_SEC_AUXPCM_RX,
  5882. .stream_name = "Sec AUX PCM Playback",
  5883. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5884. .platform_name = "msm-pcm-routing",
  5885. .codec_name = "msm-stub-codec.1",
  5886. .codec_dai_name = "msm-stub-rx",
  5887. .no_pcm = 1,
  5888. .dpcm_playback = 1,
  5889. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5890. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5891. .ops = &kona_aux_be_ops,
  5892. .ignore_pmdown_time = 1,
  5893. .ignore_suspend = 1,
  5894. },
  5895. {
  5896. .name = LPASS_BE_SEC_AUXPCM_TX,
  5897. .stream_name = "Sec AUX PCM Capture",
  5898. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5899. .platform_name = "msm-pcm-routing",
  5900. .codec_name = "msm-stub-codec.1",
  5901. .codec_dai_name = "msm-stub-tx",
  5902. .no_pcm = 1,
  5903. .dpcm_capture = 1,
  5904. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5905. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5906. .ops = &kona_aux_be_ops,
  5907. .ignore_suspend = 1,
  5908. },
  5909. /* Tertiary AUX PCM Backend DAI Links */
  5910. {
  5911. .name = LPASS_BE_TERT_AUXPCM_RX,
  5912. .stream_name = "Tert AUX PCM Playback",
  5913. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5914. .platform_name = "msm-pcm-routing",
  5915. .codec_name = "msm-stub-codec.1",
  5916. .codec_dai_name = "msm-stub-rx",
  5917. .no_pcm = 1,
  5918. .dpcm_playback = 1,
  5919. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5920. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5921. .ops = &kona_aux_be_ops,
  5922. .ignore_suspend = 1,
  5923. },
  5924. {
  5925. .name = LPASS_BE_TERT_AUXPCM_TX,
  5926. .stream_name = "Tert AUX PCM Capture",
  5927. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5928. .platform_name = "msm-pcm-routing",
  5929. .codec_name = "msm-stub-codec.1",
  5930. .codec_dai_name = "msm-stub-tx",
  5931. .no_pcm = 1,
  5932. .dpcm_capture = 1,
  5933. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5934. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5935. .ops = &kona_aux_be_ops,
  5936. .ignore_suspend = 1,
  5937. },
  5938. /* Quaternary AUX PCM Backend DAI Links */
  5939. {
  5940. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5941. .stream_name = "Quat AUX PCM Playback",
  5942. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5943. .platform_name = "msm-pcm-routing",
  5944. .codec_name = "msm-stub-codec.1",
  5945. .codec_dai_name = "msm-stub-rx",
  5946. .no_pcm = 1,
  5947. .dpcm_playback = 1,
  5948. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5949. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5950. .ops = &kona_aux_be_ops,
  5951. .ignore_suspend = 1,
  5952. },
  5953. {
  5954. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5955. .stream_name = "Quat AUX PCM Capture",
  5956. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5957. .platform_name = "msm-pcm-routing",
  5958. .codec_name = "msm-stub-codec.1",
  5959. .codec_dai_name = "msm-stub-tx",
  5960. .no_pcm = 1,
  5961. .dpcm_capture = 1,
  5962. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5963. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5964. .ops = &kona_aux_be_ops,
  5965. .ignore_suspend = 1,
  5966. },
  5967. /* Quinary AUX PCM Backend DAI Links */
  5968. {
  5969. .name = LPASS_BE_QUIN_AUXPCM_RX,
  5970. .stream_name = "Quin AUX PCM Playback",
  5971. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5972. .platform_name = "msm-pcm-routing",
  5973. .codec_name = "msm-stub-codec.1",
  5974. .codec_dai_name = "msm-stub-rx",
  5975. .no_pcm = 1,
  5976. .dpcm_playback = 1,
  5977. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  5978. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5979. .ops = &kona_aux_be_ops,
  5980. .ignore_suspend = 1,
  5981. },
  5982. {
  5983. .name = LPASS_BE_QUIN_AUXPCM_TX,
  5984. .stream_name = "Quin AUX PCM Capture",
  5985. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5986. .platform_name = "msm-pcm-routing",
  5987. .codec_name = "msm-stub-codec.1",
  5988. .codec_dai_name = "msm-stub-tx",
  5989. .no_pcm = 1,
  5990. .dpcm_capture = 1,
  5991. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  5992. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5993. .ops = &kona_aux_be_ops,
  5994. .ignore_suspend = 1,
  5995. },
  5996. /* Senary AUX PCM Backend DAI Links */
  5997. {
  5998. .name = LPASS_BE_SEN_AUXPCM_RX,
  5999. .stream_name = "Sen AUX PCM Playback",
  6000. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  6001. .platform_name = "msm-pcm-routing",
  6002. .codec_name = "msm-stub-codec.1",
  6003. .codec_dai_name = "msm-stub-rx",
  6004. .no_pcm = 1,
  6005. .dpcm_playback = 1,
  6006. .id = MSM_BACKEND_DAI_SEN_AUXPCM_RX,
  6007. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6008. .ops = &kona_aux_be_ops,
  6009. .ignore_suspend = 1,
  6010. },
  6011. {
  6012. .name = LPASS_BE_SEN_AUXPCM_TX,
  6013. .stream_name = "Sen AUX PCM Capture",
  6014. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  6015. .platform_name = "msm-pcm-routing",
  6016. .codec_name = "msm-stub-codec.1",
  6017. .codec_dai_name = "msm-stub-tx",
  6018. .no_pcm = 1,
  6019. .dpcm_capture = 1,
  6020. .id = MSM_BACKEND_DAI_SEN_AUXPCM_TX,
  6021. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6022. .ops = &kona_aux_be_ops,
  6023. .ignore_suspend = 1,
  6024. },
  6025. };
  6026. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6027. /* WSA CDC DMA Backend DAI Links */
  6028. {
  6029. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6030. .stream_name = "WSA CDC DMA0 Playback",
  6031. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6032. .platform_name = "msm-pcm-routing",
  6033. .codec_name = "bolero_codec",
  6034. .codec_dai_name = "wsa_macro_rx1",
  6035. .no_pcm = 1,
  6036. .dpcm_playback = 1,
  6037. .init = &msm_int_audrx_init,
  6038. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6039. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6040. .ignore_pmdown_time = 1,
  6041. .ignore_suspend = 1,
  6042. .ops = &msm_cdc_dma_be_ops,
  6043. },
  6044. {
  6045. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6046. .stream_name = "WSA CDC DMA1 Playback",
  6047. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6048. .platform_name = "msm-pcm-routing",
  6049. .codec_name = "bolero_codec",
  6050. .codec_dai_name = "wsa_macro_rx_mix",
  6051. .no_pcm = 1,
  6052. .dpcm_playback = 1,
  6053. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6054. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6055. .ignore_pmdown_time = 1,
  6056. .ignore_suspend = 1,
  6057. .ops = &msm_cdc_dma_be_ops,
  6058. },
  6059. {
  6060. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6061. .stream_name = "WSA CDC DMA1 Capture",
  6062. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6063. .platform_name = "msm-pcm-routing",
  6064. .codec_name = "bolero_codec",
  6065. .codec_dai_name = "wsa_macro_echo",
  6066. .no_pcm = 1,
  6067. .dpcm_capture = 1,
  6068. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6069. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6070. .ignore_suspend = 1,
  6071. .ops = &msm_cdc_dma_be_ops,
  6072. },
  6073. };
  6074. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  6075. /* RX CDC DMA Backend DAI Links */
  6076. {
  6077. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  6078. .stream_name = "RX CDC DMA0 Playback",
  6079. .cpu_dai_name = "msm-dai-cdc-dma-dev.45104",
  6080. .platform_name = "msm-pcm-routing",
  6081. .codec_name = "bolero_codec",
  6082. .codec_dai_name = "rx_macro_rx1",
  6083. .dynamic_be = 1,
  6084. .no_pcm = 1,
  6085. .dpcm_playback = 1,
  6086. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  6087. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6088. .ignore_pmdown_time = 1,
  6089. .ignore_suspend = 1,
  6090. .ops = &msm_cdc_dma_be_ops,
  6091. },
  6092. {
  6093. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  6094. .stream_name = "RX CDC DMA1 Playback",
  6095. .cpu_dai_name = "msm-dai-cdc-dma-dev.45106",
  6096. .platform_name = "msm-pcm-routing",
  6097. .codec_name = "bolero_codec",
  6098. .codec_dai_name = "rx_macro_rx2",
  6099. .dynamic_be = 1,
  6100. .no_pcm = 1,
  6101. .dpcm_playback = 1,
  6102. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  6103. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6104. .ignore_pmdown_time = 1,
  6105. .ignore_suspend = 1,
  6106. .ops = &msm_cdc_dma_be_ops,
  6107. },
  6108. {
  6109. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  6110. .stream_name = "RX CDC DMA2 Playback",
  6111. .cpu_dai_name = "msm-dai-cdc-dma-dev.45108",
  6112. .platform_name = "msm-pcm-routing",
  6113. .codec_name = "bolero_codec",
  6114. .codec_dai_name = "rx_macro_rx3",
  6115. .dynamic_be = 1,
  6116. .no_pcm = 1,
  6117. .dpcm_playback = 1,
  6118. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  6119. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6120. .ignore_pmdown_time = 1,
  6121. .ignore_suspend = 1,
  6122. .ops = &msm_cdc_dma_be_ops,
  6123. },
  6124. {
  6125. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  6126. .stream_name = "RX CDC DMA3 Playback",
  6127. .cpu_dai_name = "msm-dai-cdc-dma-dev.45110",
  6128. .platform_name = "msm-pcm-routing",
  6129. .codec_name = "bolero_codec",
  6130. .codec_dai_name = "rx_macro_rx4",
  6131. .dynamic_be = 1,
  6132. .no_pcm = 1,
  6133. .dpcm_playback = 1,
  6134. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  6135. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6136. .ignore_pmdown_time = 1,
  6137. .ignore_suspend = 1,
  6138. .ops = &msm_cdc_dma_be_ops,
  6139. },
  6140. /* TX CDC DMA Backend DAI Links */
  6141. {
  6142. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  6143. .stream_name = "TX CDC DMA3 Capture",
  6144. .cpu_dai_name = "msm-dai-cdc-dma-dev.45111",
  6145. .platform_name = "msm-pcm-routing",
  6146. .codec_name = "bolero_codec",
  6147. .codec_dai_name = "tx_macro_tx1",
  6148. .no_pcm = 1,
  6149. .dpcm_capture = 1,
  6150. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  6151. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6152. .ignore_suspend = 1,
  6153. .ops = &msm_cdc_dma_be_ops,
  6154. },
  6155. {
  6156. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  6157. .stream_name = "TX CDC DMA4 Capture",
  6158. .cpu_dai_name = "msm-dai-cdc-dma-dev.45113",
  6159. .platform_name = "msm-pcm-routing",
  6160. .codec_name = "bolero_codec",
  6161. .codec_dai_name = "tx_macro_tx2",
  6162. .no_pcm = 1,
  6163. .dpcm_capture = 1,
  6164. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  6165. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6166. .ignore_suspend = 1,
  6167. .ops = &msm_cdc_dma_be_ops,
  6168. },
  6169. };
  6170. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6171. {
  6172. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6173. .stream_name = "VA CDC DMA0 Capture",
  6174. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6175. .platform_name = "msm-pcm-routing",
  6176. .codec_name = "bolero_codec",
  6177. .codec_dai_name = "va_macro_tx1",
  6178. .no_pcm = 1,
  6179. .dpcm_capture = 1,
  6180. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6181. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6182. .ignore_suspend = 1,
  6183. .ops = &msm_cdc_dma_be_ops,
  6184. },
  6185. {
  6186. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6187. .stream_name = "VA CDC DMA1 Capture",
  6188. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6189. .platform_name = "msm-pcm-routing",
  6190. .codec_name = "bolero_codec",
  6191. .codec_dai_name = "va_macro_tx2",
  6192. .no_pcm = 1,
  6193. .dpcm_capture = 1,
  6194. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6195. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6196. .ignore_suspend = 1,
  6197. .ops = &msm_cdc_dma_be_ops,
  6198. },
  6199. {
  6200. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  6201. .stream_name = "VA CDC DMA2 Capture",
  6202. .cpu_dai_name = "msm-dai-cdc-dma-dev.45093",
  6203. .platform_name = "msm-pcm-routing",
  6204. .codec_name = "bolero_codec",
  6205. .codec_dai_name = "va_macro_tx3",
  6206. .no_pcm = 1,
  6207. .dpcm_capture = 1,
  6208. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  6209. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6210. .ignore_suspend = 1,
  6211. .ops = &msm_cdc_dma_be_ops,
  6212. },
  6213. };
  6214. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  6215. {
  6216. .name = LPASS_BE_AFE_LOOPBACK_TX,
  6217. .stream_name = "AFE Loopback Capture",
  6218. .cpu_dai_name = "msm-dai-q6-dev.24577",
  6219. .platform_name = "msm-pcm-routing",
  6220. .codec_name = "msm-stub-codec.1",
  6221. .codec_dai_name = "msm-stub-tx",
  6222. .no_pcm = 1,
  6223. .dpcm_capture = 1,
  6224. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  6225. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6226. .ignore_pmdown_time = 1,
  6227. .ignore_suspend = 1,
  6228. },
  6229. };
  6230. static struct snd_soc_dai_link msm_kona_dai_links[
  6231. ARRAY_SIZE(msm_common_dai_links) +
  6232. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6233. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6234. ARRAY_SIZE(msm_common_be_dai_links) +
  6235. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6236. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6237. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6238. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  6239. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6240. ARRAY_SIZE(ext_disp_be_dai_link) +
  6241. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6242. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  6243. ARRAY_SIZE(msm_wcn_btfm_be_dai_links)];
  6244. static int msm_populate_dai_link_component_of_node(
  6245. struct snd_soc_card *card)
  6246. {
  6247. int i, index, ret = 0;
  6248. struct device *cdev = card->dev;
  6249. struct snd_soc_dai_link *dai_link = card->dai_link;
  6250. struct device_node *np;
  6251. if (!cdev) {
  6252. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  6253. return -ENODEV;
  6254. }
  6255. for (i = 0; i < card->num_links; i++) {
  6256. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6257. continue;
  6258. /* populate platform_of_node for snd card dai links */
  6259. if (dai_link[i].platform_name &&
  6260. !dai_link[i].platform_of_node) {
  6261. index = of_property_match_string(cdev->of_node,
  6262. "asoc-platform-names",
  6263. dai_link[i].platform_name);
  6264. if (index < 0) {
  6265. dev_err(cdev, "%s: No match found for platform name: %s\n",
  6266. __func__, dai_link[i].platform_name);
  6267. ret = index;
  6268. goto err;
  6269. }
  6270. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6271. index);
  6272. if (!np) {
  6273. dev_err(cdev, "%s: retrieving phandle for platform %s, index %d failed\n",
  6274. __func__, dai_link[i].platform_name,
  6275. index);
  6276. ret = -ENODEV;
  6277. goto err;
  6278. }
  6279. dai_link[i].platform_of_node = np;
  6280. dai_link[i].platform_name = NULL;
  6281. }
  6282. /* populate cpu_of_node for snd card dai links */
  6283. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6284. index = of_property_match_string(cdev->of_node,
  6285. "asoc-cpu-names",
  6286. dai_link[i].cpu_dai_name);
  6287. if (index >= 0) {
  6288. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6289. index);
  6290. if (!np) {
  6291. dev_err(cdev, "%s: retrieving phandle for cpu dai %s failed\n",
  6292. __func__,
  6293. dai_link[i].cpu_dai_name);
  6294. ret = -ENODEV;
  6295. goto err;
  6296. }
  6297. dai_link[i].cpu_of_node = np;
  6298. dai_link[i].cpu_dai_name = NULL;
  6299. }
  6300. }
  6301. /* populate codec_of_node for snd card dai links */
  6302. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6303. index = of_property_match_string(cdev->of_node,
  6304. "asoc-codec-names",
  6305. dai_link[i].codec_name);
  6306. if (index < 0)
  6307. continue;
  6308. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6309. index);
  6310. if (!np) {
  6311. dev_err(cdev, "%s: retrieving phandle for codec %s failed\n",
  6312. __func__, dai_link[i].codec_name);
  6313. ret = -ENODEV;
  6314. goto err;
  6315. }
  6316. dai_link[i].codec_of_node = np;
  6317. dai_link[i].codec_name = NULL;
  6318. }
  6319. }
  6320. err:
  6321. return ret;
  6322. }
  6323. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  6324. {
  6325. int ret = -EINVAL;
  6326. struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  6327. if (!component) {
  6328. pr_err("* %s: No match for msm-stub-codec component\n", __func__);
  6329. return ret;
  6330. }
  6331. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  6332. ARRAY_SIZE(msm_snd_controls));
  6333. if (ret < 0) {
  6334. dev_err(component->dev,
  6335. "%s: add_codec_controls failed, err = %d\n",
  6336. __func__, ret);
  6337. return ret;
  6338. }
  6339. return ret;
  6340. }
  6341. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  6342. struct snd_pcm_hw_params *params)
  6343. {
  6344. return 0;
  6345. }
  6346. static struct snd_soc_ops msm_stub_be_ops = {
  6347. .hw_params = msm_snd_stub_hw_params,
  6348. };
  6349. struct snd_soc_card snd_soc_card_stub_msm = {
  6350. .name = "kona-stub-snd-card",
  6351. };
  6352. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6353. /* FrontEnd DAI Links */
  6354. {
  6355. .name = "MSMSTUB Media1",
  6356. .stream_name = "MultiMedia1",
  6357. .cpu_dai_name = "MultiMedia1",
  6358. .platform_name = "msm-pcm-dsp.0",
  6359. .dynamic = 1,
  6360. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6361. .dpcm_playback = 1,
  6362. .dpcm_capture = 1,
  6363. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6364. SND_SOC_DPCM_TRIGGER_POST},
  6365. .codec_dai_name = "snd-soc-dummy-dai",
  6366. .codec_name = "snd-soc-dummy",
  6367. .ignore_suspend = 1,
  6368. /* this dainlink has playback support */
  6369. .ignore_pmdown_time = 1,
  6370. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6371. },
  6372. };
  6373. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6374. /* Backend DAI Links */
  6375. {
  6376. .name = LPASS_BE_AUXPCM_RX,
  6377. .stream_name = "AUX PCM Playback",
  6378. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6379. .platform_name = "msm-pcm-routing",
  6380. .codec_name = "msm-stub-codec.1",
  6381. .codec_dai_name = "msm-stub-rx",
  6382. .no_pcm = 1,
  6383. .dpcm_playback = 1,
  6384. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6385. .init = &msm_audrx_stub_init,
  6386. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6387. .ignore_pmdown_time = 1,
  6388. .ignore_suspend = 1,
  6389. .ops = &msm_stub_be_ops,
  6390. },
  6391. {
  6392. .name = LPASS_BE_AUXPCM_TX,
  6393. .stream_name = "AUX PCM Capture",
  6394. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6395. .platform_name = "msm-pcm-routing",
  6396. .codec_name = "msm-stub-codec.1",
  6397. .codec_dai_name = "msm-stub-tx",
  6398. .no_pcm = 1,
  6399. .dpcm_capture = 1,
  6400. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6401. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6402. .ignore_suspend = 1,
  6403. .ops = &msm_stub_be_ops,
  6404. },
  6405. };
  6406. static struct snd_soc_dai_link msm_stub_dai_links[
  6407. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6408. ARRAY_SIZE(msm_stub_be_dai_links)];
  6409. static const struct of_device_id kona_asoc_machine_of_match[] = {
  6410. { .compatible = "qcom,kona-asoc-snd",
  6411. .data = "codec"},
  6412. { .compatible = "qcom,kona-asoc-snd-stub",
  6413. .data = "stub_codec"},
  6414. {},
  6415. };
  6416. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6417. {
  6418. struct snd_soc_card *card = NULL;
  6419. struct snd_soc_dai_link *dailink = NULL;
  6420. int len_1 = 0;
  6421. int len_2 = 0;
  6422. int total_links = 0;
  6423. int rc = 0;
  6424. u32 mi2s_audio_intf = 0;
  6425. u32 auxpcm_audio_intf = 0;
  6426. u32 val = 0;
  6427. u32 wcn_btfm_intf = 0;
  6428. const struct of_device_id *match;
  6429. match = of_match_node(kona_asoc_machine_of_match, dev->of_node);
  6430. if (!match) {
  6431. dev_err(dev, "%s: No DT match found for sound card\n",
  6432. __func__);
  6433. return NULL;
  6434. }
  6435. if (!strcmp(match->data, "codec")) {
  6436. card = &snd_soc_card_kona_msm;
  6437. memcpy(msm_kona_dai_links + total_links,
  6438. msm_common_dai_links,
  6439. sizeof(msm_common_dai_links));
  6440. total_links += ARRAY_SIZE(msm_common_dai_links);
  6441. memcpy(msm_kona_dai_links + total_links,
  6442. msm_bolero_fe_dai_links,
  6443. sizeof(msm_bolero_fe_dai_links));
  6444. total_links +=
  6445. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6446. memcpy(msm_kona_dai_links + total_links,
  6447. msm_common_misc_fe_dai_links,
  6448. sizeof(msm_common_misc_fe_dai_links));
  6449. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6450. memcpy(msm_kona_dai_links + total_links,
  6451. msm_common_be_dai_links,
  6452. sizeof(msm_common_be_dai_links));
  6453. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6454. memcpy(msm_kona_dai_links + total_links,
  6455. msm_wsa_cdc_dma_be_dai_links,
  6456. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6457. total_links +=
  6458. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6459. memcpy(msm_kona_dai_links + total_links,
  6460. msm_rx_tx_cdc_dma_be_dai_links,
  6461. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  6462. total_links +=
  6463. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
  6464. memcpy(msm_kona_dai_links + total_links,
  6465. msm_va_cdc_dma_be_dai_links,
  6466. sizeof(msm_va_cdc_dma_be_dai_links));
  6467. total_links +=
  6468. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6469. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6470. &mi2s_audio_intf);
  6471. if (rc) {
  6472. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6473. __func__);
  6474. } else {
  6475. if (mi2s_audio_intf) {
  6476. memcpy(msm_kona_dai_links + total_links,
  6477. msm_mi2s_be_dai_links,
  6478. sizeof(msm_mi2s_be_dai_links));
  6479. total_links +=
  6480. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6481. }
  6482. }
  6483. rc = of_property_read_u32(dev->of_node,
  6484. "qcom,auxpcm-audio-intf",
  6485. &auxpcm_audio_intf);
  6486. if (rc) {
  6487. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6488. __func__);
  6489. } else {
  6490. if (auxpcm_audio_intf) {
  6491. memcpy(msm_kona_dai_links + total_links,
  6492. msm_auxpcm_be_dai_links,
  6493. sizeof(msm_auxpcm_be_dai_links));
  6494. total_links +=
  6495. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6496. }
  6497. }
  6498. rc = of_property_read_u32(dev->of_node,
  6499. "qcom,ext-disp-audio-rx", &val);
  6500. if (!rc && val) {
  6501. dev_dbg(dev, "%s(): ext disp audio support present\n",
  6502. __func__);
  6503. memcpy(msm_kona_dai_links + total_links,
  6504. ext_disp_be_dai_link,
  6505. sizeof(ext_disp_be_dai_link));
  6506. total_links += ARRAY_SIZE(ext_disp_be_dai_link);
  6507. }
  6508. rc = of_property_read_u32(dev->of_node, "qcom,wcn-bt", &val);
  6509. if (!rc && val) {
  6510. dev_dbg(dev, "%s(): WCN BT support present\n",
  6511. __func__);
  6512. memcpy(msm_kona_dai_links + total_links,
  6513. msm_wcn_be_dai_links,
  6514. sizeof(msm_wcn_be_dai_links));
  6515. total_links += ARRAY_SIZE(msm_wcn_be_dai_links);
  6516. }
  6517. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  6518. &val);
  6519. if (!rc && val) {
  6520. memcpy(msm_kona_dai_links + total_links,
  6521. msm_afe_rxtx_lb_be_dai_link,
  6522. sizeof(msm_afe_rxtx_lb_be_dai_link));
  6523. total_links +=
  6524. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  6525. }
  6526. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  6527. &wcn_btfm_intf);
  6528. if (rc) {
  6529. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  6530. __func__);
  6531. } else {
  6532. if (wcn_btfm_intf) {
  6533. memcpy(msm_kona_dai_links + total_links,
  6534. msm_wcn_btfm_be_dai_links,
  6535. sizeof(msm_wcn_btfm_be_dai_links));
  6536. total_links +=
  6537. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  6538. }
  6539. }
  6540. dailink = msm_kona_dai_links;
  6541. } else if(!strcmp(match->data, "stub_codec")) {
  6542. card = &snd_soc_card_stub_msm;
  6543. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  6544. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  6545. memcpy(msm_stub_dai_links,
  6546. msm_stub_fe_dai_links,
  6547. sizeof(msm_stub_fe_dai_links));
  6548. memcpy(msm_stub_dai_links + len_1,
  6549. msm_stub_be_dai_links,
  6550. sizeof(msm_stub_be_dai_links));
  6551. dailink = msm_stub_dai_links;
  6552. total_links = len_2;
  6553. }
  6554. if (card) {
  6555. card->dai_link = dailink;
  6556. card->num_links = total_links;
  6557. }
  6558. return card;
  6559. }
  6560. static int msm_wsa881x_init(struct snd_soc_component *component)
  6561. {
  6562. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6563. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6564. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6565. SPKR_L_BOOST, SPKR_L_VI};
  6566. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6567. SPKR_R_BOOST, SPKR_R_VI};
  6568. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6569. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6570. struct msm_asoc_mach_data *pdata;
  6571. struct snd_soc_dapm_context *dapm;
  6572. struct snd_card *card;
  6573. struct snd_info_entry *entry;
  6574. int ret = 0;
  6575. if (!component) {
  6576. pr_err("%s component is NULL\n", __func__);
  6577. return -EINVAL;
  6578. }
  6579. card = component->card->snd_card;
  6580. dapm = snd_soc_component_get_dapm(component);
  6581. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6582. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  6583. __func__, component->name);
  6584. wsa881x_set_channel_map(component, &spkleft_ports[0],
  6585. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6586. &ch_rate[0], &spkleft_port_types[0]);
  6587. if (dapm->component) {
  6588. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6589. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6590. }
  6591. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6592. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  6593. __func__, component->name);
  6594. wsa881x_set_channel_map(component, &spkright_ports[0],
  6595. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6596. &ch_rate[0], &spkright_port_types[0]);
  6597. if (dapm->component) {
  6598. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6599. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6600. }
  6601. } else {
  6602. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  6603. component->name);
  6604. ret = -EINVAL;
  6605. goto err;
  6606. }
  6607. pdata = snd_soc_card_get_drvdata(component->card);
  6608. if (!pdata->codec_root) {
  6609. entry = snd_info_create_subdir(card->module, "codecs",
  6610. card->proc_root);
  6611. if (!entry) {
  6612. pr_err("%s: Cannot create codecs module entry\n",
  6613. __func__);
  6614. ret = 0;
  6615. goto err;
  6616. }
  6617. pdata->codec_root = entry;
  6618. }
  6619. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6620. component);
  6621. err:
  6622. return ret;
  6623. }
  6624. static int msm_aux_codec_init(struct snd_soc_component *component)
  6625. {
  6626. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  6627. int ret = 0;
  6628. int codec_variant = -1;
  6629. void *mbhc_calibration;
  6630. struct snd_info_entry *entry;
  6631. struct snd_card *card = component->card->snd_card;
  6632. struct msm_asoc_mach_data *pdata;
  6633. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  6634. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  6635. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  6636. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  6637. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  6638. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  6639. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  6640. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  6641. snd_soc_dapm_sync(dapm);
  6642. pdata = snd_soc_card_get_drvdata(component->card);
  6643. if (!pdata->codec_root) {
  6644. entry = snd_info_create_subdir(card->module, "codecs",
  6645. card->proc_root);
  6646. if (!entry) {
  6647. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  6648. __func__);
  6649. ret = 0;
  6650. goto mbhc_cfg_cal;
  6651. }
  6652. pdata->codec_root = entry;
  6653. }
  6654. wcd938x_info_create_codec_entry(pdata->codec_root, component);
  6655. codec_variant = wcd938x_get_codec_variant(component);
  6656. dev_dbg(component->dev, "%s: variant %d\n", __func__, codec_variant);
  6657. if (codec_variant == WCD9380)
  6658. ret = snd_soc_add_component_controls(component,
  6659. msm_int_wcd9380_snd_controls,
  6660. ARRAY_SIZE(msm_int_wcd9380_snd_controls));
  6661. else if (codec_variant == WCD9385)
  6662. ret = snd_soc_add_component_controls(component,
  6663. msm_int_wcd9385_snd_controls,
  6664. ARRAY_SIZE(msm_int_wcd9385_snd_controls));
  6665. if (ret < 0) {
  6666. dev_err(component->dev, "%s: add codec specific snd controls failed: %d\n",
  6667. __func__, ret);
  6668. return ret;
  6669. }
  6670. mbhc_cfg_cal:
  6671. mbhc_calibration = def_wcd_mbhc_cal();
  6672. if (!mbhc_calibration)
  6673. return -ENOMEM;
  6674. wcd_mbhc_cfg.calibration = mbhc_calibration;
  6675. ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  6676. if (ret) {
  6677. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  6678. __func__, ret);
  6679. goto err_hs_detect;
  6680. }
  6681. return 0;
  6682. err_hs_detect:
  6683. kfree(mbhc_calibration);
  6684. return ret;
  6685. }
  6686. static int msm_init_aux_dev(struct platform_device *pdev,
  6687. struct snd_soc_card *card)
  6688. {
  6689. struct device_node *wsa_of_node;
  6690. struct device_node *aux_codec_of_node;
  6691. u32 wsa_max_devs;
  6692. u32 wsa_dev_cnt;
  6693. u32 codec_max_aux_devs = 0;
  6694. u32 codec_aux_dev_cnt = 0;
  6695. int i;
  6696. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6697. struct aux_codec_dev_info *aux_cdc_dev_info;
  6698. const char *auxdev_name_prefix[1];
  6699. char *dev_name_str = NULL;
  6700. int found = 0;
  6701. int codecs_found = 0;
  6702. int ret = 0;
  6703. /* Get maximum WSA device count for this platform */
  6704. ret = of_property_read_u32(pdev->dev.of_node,
  6705. "qcom,wsa-max-devs", &wsa_max_devs);
  6706. if (ret) {
  6707. dev_info(&pdev->dev,
  6708. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6709. __func__, pdev->dev.of_node->full_name, ret);
  6710. wsa_max_devs = 0;
  6711. goto codec_aux_dev;
  6712. }
  6713. if (wsa_max_devs == 0) {
  6714. dev_warn(&pdev->dev,
  6715. "%s: Max WSA devices is 0 for this target?\n",
  6716. __func__);
  6717. goto codec_aux_dev;
  6718. }
  6719. /* Get count of WSA device phandles for this platform */
  6720. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6721. "qcom,wsa-devs", NULL);
  6722. if (wsa_dev_cnt == -ENOENT) {
  6723. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6724. __func__);
  6725. goto err;
  6726. } else if (wsa_dev_cnt <= 0) {
  6727. dev_err(&pdev->dev,
  6728. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6729. __func__, wsa_dev_cnt);
  6730. ret = -EINVAL;
  6731. goto err;
  6732. }
  6733. /*
  6734. * Expect total phandles count to be NOT less than maximum possible
  6735. * WSA count. However, if it is less, then assign same value to
  6736. * max count as well.
  6737. */
  6738. if (wsa_dev_cnt < wsa_max_devs) {
  6739. dev_dbg(&pdev->dev,
  6740. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6741. __func__, wsa_max_devs, wsa_dev_cnt);
  6742. wsa_max_devs = wsa_dev_cnt;
  6743. }
  6744. /* Make sure prefix string passed for each WSA device */
  6745. ret = of_property_count_strings(pdev->dev.of_node,
  6746. "qcom,wsa-aux-dev-prefix");
  6747. if (ret != wsa_dev_cnt) {
  6748. dev_err(&pdev->dev,
  6749. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6750. __func__, wsa_dev_cnt, ret);
  6751. ret = -EINVAL;
  6752. goto err;
  6753. }
  6754. /*
  6755. * Alloc mem to store phandle and index info of WSA device, if already
  6756. * registered with ALSA core
  6757. */
  6758. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6759. sizeof(struct msm_wsa881x_dev_info),
  6760. GFP_KERNEL);
  6761. if (!wsa881x_dev_info) {
  6762. ret = -ENOMEM;
  6763. goto err;
  6764. }
  6765. /*
  6766. * search and check whether all WSA devices are already
  6767. * registered with ALSA core or not. If found a node, store
  6768. * the node and the index in a local array of struct for later
  6769. * use.
  6770. */
  6771. for (i = 0; i < wsa_dev_cnt; i++) {
  6772. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6773. "qcom,wsa-devs", i);
  6774. if (unlikely(!wsa_of_node)) {
  6775. /* we should not be here */
  6776. dev_err(&pdev->dev,
  6777. "%s: wsa dev node is not present\n",
  6778. __func__);
  6779. ret = -EINVAL;
  6780. goto err;
  6781. }
  6782. if (soc_find_component(wsa_of_node, NULL)) {
  6783. /* WSA device registered with ALSA core */
  6784. wsa881x_dev_info[found].of_node = wsa_of_node;
  6785. wsa881x_dev_info[found].index = i;
  6786. found++;
  6787. if (found == wsa_max_devs)
  6788. break;
  6789. }
  6790. }
  6791. if (found < wsa_max_devs) {
  6792. dev_dbg(&pdev->dev,
  6793. "%s: failed to find %d components. Found only %d\n",
  6794. __func__, wsa_max_devs, found);
  6795. return -EPROBE_DEFER;
  6796. }
  6797. dev_info(&pdev->dev,
  6798. "%s: found %d wsa881x devices registered with ALSA core\n",
  6799. __func__, found);
  6800. codec_aux_dev:
  6801. /* Get maximum aux codec device count for this platform */
  6802. ret = of_property_read_u32(pdev->dev.of_node,
  6803. "qcom,codec-max-aux-devs",
  6804. &codec_max_aux_devs);
  6805. if (ret) {
  6806. dev_err(&pdev->dev,
  6807. "%s: codec-max-aux-devs property missing in DT %s, ret = %d\n",
  6808. __func__, pdev->dev.of_node->full_name, ret);
  6809. codec_max_aux_devs = 0;
  6810. goto aux_dev_register;
  6811. }
  6812. if (codec_max_aux_devs == 0) {
  6813. dev_dbg(&pdev->dev,
  6814. "%s: Max aux codec devices is 0 for this target?\n",
  6815. __func__);
  6816. goto aux_dev_register;
  6817. }
  6818. /* Get count of aux codec device phandles for this platform */
  6819. codec_aux_dev_cnt = of_count_phandle_with_args(
  6820. pdev->dev.of_node,
  6821. "qcom,codec-aux-devs", NULL);
  6822. if (codec_aux_dev_cnt == -ENOENT) {
  6823. dev_warn(&pdev->dev, "%s: No aux codec defined in DT.\n",
  6824. __func__);
  6825. goto err;
  6826. } else if (codec_aux_dev_cnt <= 0) {
  6827. dev_err(&pdev->dev,
  6828. "%s: Error reading aux codec device from DT, dev_cnt=%d\n",
  6829. __func__, codec_aux_dev_cnt);
  6830. ret = -EINVAL;
  6831. goto err;
  6832. }
  6833. /*
  6834. * Expect total phandles count to be NOT less than maximum possible
  6835. * AUX device count. However, if it is less, then assign same value to
  6836. * max count as well.
  6837. */
  6838. if (codec_aux_dev_cnt < codec_max_aux_devs) {
  6839. dev_dbg(&pdev->dev,
  6840. "%s: codec_max_aux_devs = %d cannot exceed codec_aux_dev_cnt = %d\n",
  6841. __func__, codec_max_aux_devs,
  6842. codec_aux_dev_cnt);
  6843. codec_max_aux_devs = codec_aux_dev_cnt;
  6844. }
  6845. /*
  6846. * Alloc mem to store phandle and index info of aux codec
  6847. * if already registered with ALSA core
  6848. */
  6849. aux_cdc_dev_info = devm_kcalloc(&pdev->dev, codec_aux_dev_cnt,
  6850. sizeof(struct aux_codec_dev_info),
  6851. GFP_KERNEL);
  6852. if (!aux_cdc_dev_info) {
  6853. ret = -ENOMEM;
  6854. goto err;
  6855. }
  6856. /*
  6857. * search and check whether all aux codecs are already
  6858. * registered with ALSA core or not. If found a node, store
  6859. * the node and the index in a local array of struct for later
  6860. * use.
  6861. */
  6862. for (i = 0; i < codec_aux_dev_cnt; i++) {
  6863. aux_codec_of_node = of_parse_phandle(pdev->dev.of_node,
  6864. "qcom,codec-aux-devs", i);
  6865. if (unlikely(!aux_codec_of_node)) {
  6866. /* we should not be here */
  6867. dev_err(&pdev->dev,
  6868. "%s: aux codec dev node is not present\n",
  6869. __func__);
  6870. ret = -EINVAL;
  6871. goto err;
  6872. }
  6873. if (soc_find_component(aux_codec_of_node, NULL)) {
  6874. /* AUX codec registered with ALSA core */
  6875. aux_cdc_dev_info[codecs_found].of_node =
  6876. aux_codec_of_node;
  6877. aux_cdc_dev_info[codecs_found].index = i;
  6878. codecs_found++;
  6879. }
  6880. }
  6881. if (codecs_found < codec_aux_dev_cnt) {
  6882. dev_dbg(&pdev->dev,
  6883. "%s: failed to find %d components. Found only %d\n",
  6884. __func__, codec_aux_dev_cnt, codecs_found);
  6885. return -EPROBE_DEFER;
  6886. }
  6887. dev_info(&pdev->dev,
  6888. "%s: found %d AUX codecs registered with ALSA core\n",
  6889. __func__, codecs_found);
  6890. aux_dev_register:
  6891. card->num_aux_devs = wsa_max_devs + codec_aux_dev_cnt;
  6892. card->num_configs = wsa_max_devs + codec_aux_dev_cnt;
  6893. /* Alloc array of AUX devs struct */
  6894. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6895. sizeof(struct snd_soc_aux_dev),
  6896. GFP_KERNEL);
  6897. if (!msm_aux_dev) {
  6898. ret = -ENOMEM;
  6899. goto err;
  6900. }
  6901. /* Alloc array of codec conf struct */
  6902. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_configs,
  6903. sizeof(struct snd_soc_codec_conf),
  6904. GFP_KERNEL);
  6905. if (!msm_codec_conf) {
  6906. ret = -ENOMEM;
  6907. goto err;
  6908. }
  6909. for (i = 0; i < wsa_max_devs; i++) {
  6910. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6911. GFP_KERNEL);
  6912. if (!dev_name_str) {
  6913. ret = -ENOMEM;
  6914. goto err;
  6915. }
  6916. ret = of_property_read_string_index(pdev->dev.of_node,
  6917. "qcom,wsa-aux-dev-prefix",
  6918. wsa881x_dev_info[i].index,
  6919. auxdev_name_prefix);
  6920. if (ret) {
  6921. dev_err(&pdev->dev,
  6922. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  6923. __func__, ret);
  6924. ret = -EINVAL;
  6925. goto err;
  6926. }
  6927. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  6928. msm_aux_dev[i].name = dev_name_str;
  6929. msm_aux_dev[i].codec_name = NULL;
  6930. msm_aux_dev[i].codec_of_node =
  6931. wsa881x_dev_info[i].of_node;
  6932. msm_aux_dev[i].init = msm_wsa881x_init;
  6933. msm_codec_conf[i].dev_name = NULL;
  6934. msm_codec_conf[i].name_prefix = auxdev_name_prefix[0];
  6935. msm_codec_conf[i].of_node =
  6936. wsa881x_dev_info[i].of_node;
  6937. }
  6938. for (i = 0; i < codec_aux_dev_cnt; i++) {
  6939. msm_aux_dev[wsa_max_devs + i].name = NULL;
  6940. msm_aux_dev[wsa_max_devs + i].codec_name = NULL;
  6941. msm_aux_dev[wsa_max_devs + i].codec_of_node =
  6942. aux_cdc_dev_info[i].of_node;
  6943. msm_aux_dev[wsa_max_devs + i].init = msm_aux_codec_init;
  6944. msm_codec_conf[wsa_max_devs + i].dev_name = NULL;
  6945. msm_codec_conf[wsa_max_devs + i].name_prefix =
  6946. NULL;
  6947. msm_codec_conf[wsa_max_devs + i].of_node =
  6948. aux_cdc_dev_info[i].of_node;
  6949. }
  6950. card->codec_conf = msm_codec_conf;
  6951. card->aux_dev = msm_aux_dev;
  6952. err:
  6953. return ret;
  6954. }
  6955. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  6956. {
  6957. int count = 0;
  6958. u32 mi2s_master_slave[MI2S_MAX];
  6959. int ret = 0;
  6960. for (count = 0; count < MI2S_MAX; count++) {
  6961. mutex_init(&mi2s_intf_conf[count].lock);
  6962. mi2s_intf_conf[count].ref_cnt = 0;
  6963. }
  6964. ret = of_property_read_u32_array(pdev->dev.of_node,
  6965. "qcom,msm-mi2s-master",
  6966. mi2s_master_slave, MI2S_MAX);
  6967. if (ret) {
  6968. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  6969. __func__);
  6970. } else {
  6971. for (count = 0; count < MI2S_MAX; count++) {
  6972. mi2s_intf_conf[count].msm_is_mi2s_master =
  6973. mi2s_master_slave[count];
  6974. }
  6975. }
  6976. }
  6977. static void msm_i2s_auxpcm_deinit(void)
  6978. {
  6979. int count = 0;
  6980. for (count = 0; count < MI2S_MAX; count++) {
  6981. mutex_destroy(&mi2s_intf_conf[count].lock);
  6982. mi2s_intf_conf[count].ref_cnt = 0;
  6983. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  6984. }
  6985. }
  6986. static int kona_ssr_enable(struct device *dev, void *data)
  6987. {
  6988. struct platform_device *pdev = to_platform_device(dev);
  6989. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6990. int ret = 0;
  6991. if (!card) {
  6992. dev_err(dev, "%s: card is NULL\n", __func__);
  6993. ret = -EINVAL;
  6994. goto err;
  6995. }
  6996. if (!strcmp(card->name, "kona-stub-snd-card")) {
  6997. /* TODO */
  6998. dev_dbg(dev, "%s: TODO \n", __func__);
  6999. }
  7000. snd_soc_card_change_online_state(card, 1);
  7001. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  7002. err:
  7003. return ret;
  7004. }
  7005. static void kona_ssr_disable(struct device *dev, void *data)
  7006. {
  7007. struct platform_device *pdev = to_platform_device(dev);
  7008. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7009. if (!card) {
  7010. dev_err(dev, "%s: card is NULL\n", __func__);
  7011. return;
  7012. }
  7013. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  7014. snd_soc_card_change_online_state(card, 0);
  7015. if (!strcmp(card->name, "kona-stub-snd-card")) {
  7016. /* TODO */
  7017. dev_dbg(dev, "%s: TODO \n", __func__);
  7018. }
  7019. }
  7020. static const struct snd_event_ops kona_ssr_ops = {
  7021. .enable = kona_ssr_enable,
  7022. .disable = kona_ssr_disable,
  7023. };
  7024. static int msm_audio_ssr_compare(struct device *dev, void *data)
  7025. {
  7026. struct device_node *node = data;
  7027. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  7028. __func__, dev->of_node, node);
  7029. return (dev->of_node && dev->of_node == node);
  7030. }
  7031. static int msm_audio_ssr_register(struct device *dev)
  7032. {
  7033. struct device_node *np = dev->of_node;
  7034. struct snd_event_clients *ssr_clients = NULL;
  7035. struct device_node *node = NULL;
  7036. int ret = 0;
  7037. int i = 0;
  7038. for (i = 0; ; i++) {
  7039. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  7040. if (!node)
  7041. break;
  7042. snd_event_mstr_add_client(&ssr_clients,
  7043. msm_audio_ssr_compare, node);
  7044. }
  7045. ret = snd_event_master_register(dev, &kona_ssr_ops,
  7046. ssr_clients, NULL);
  7047. if (!ret)
  7048. snd_event_notify(dev, SND_EVENT_UP);
  7049. return ret;
  7050. }
  7051. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7052. {
  7053. struct snd_soc_card *card = NULL;
  7054. struct msm_asoc_mach_data *pdata = NULL;
  7055. const char *mbhc_audio_jack_type = NULL;
  7056. int ret = 0;
  7057. uint index = 0;
  7058. if (!pdev->dev.of_node) {
  7059. dev_err(&pdev->dev, "%s: No platform supplied from device tree\n", __func__);
  7060. return -EINVAL;
  7061. }
  7062. pdata = devm_kzalloc(&pdev->dev,
  7063. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7064. if (!pdata)
  7065. return -ENOMEM;
  7066. card = populate_snd_card_dailinks(&pdev->dev);
  7067. if (!card) {
  7068. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7069. ret = -EINVAL;
  7070. goto err;
  7071. }
  7072. card->dev = &pdev->dev;
  7073. platform_set_drvdata(pdev, card);
  7074. snd_soc_card_set_drvdata(card, pdata);
  7075. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7076. if (ret) {
  7077. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  7078. __func__, ret);
  7079. goto err;
  7080. }
  7081. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7082. if (ret) {
  7083. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  7084. __func__, ret);
  7085. goto err;
  7086. }
  7087. ret = msm_populate_dai_link_component_of_node(card);
  7088. if (ret) {
  7089. ret = -EPROBE_DEFER;
  7090. goto err;
  7091. }
  7092. ret = msm_init_aux_dev(pdev, card);
  7093. if (ret)
  7094. goto err;
  7095. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7096. if (ret == -EPROBE_DEFER) {
  7097. if (codec_reg_done)
  7098. ret = -EINVAL;
  7099. goto err;
  7100. } else if (ret) {
  7101. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  7102. __func__, ret);
  7103. goto err;
  7104. }
  7105. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  7106. __func__, card->name);
  7107. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7108. "qcom,hph-en1-gpio", 0);
  7109. if (!pdata->hph_en1_gpio_p) {
  7110. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  7111. __func__, "qcom,hph-en1-gpio",
  7112. pdev->dev.of_node->full_name);
  7113. }
  7114. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7115. "qcom,hph-en0-gpio", 0);
  7116. if (!pdata->hph_en0_gpio_p) {
  7117. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  7118. __func__, "qcom,hph-en0-gpio",
  7119. pdev->dev.of_node->full_name);
  7120. }
  7121. ret = of_property_read_string(pdev->dev.of_node,
  7122. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  7123. if (ret) {
  7124. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  7125. __func__, "qcom,mbhc-audio-jack-type",
  7126. pdev->dev.of_node->full_name);
  7127. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  7128. } else {
  7129. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  7130. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  7131. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  7132. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  7133. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  7134. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  7135. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  7136. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  7137. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  7138. } else {
  7139. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  7140. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  7141. }
  7142. }
  7143. /*
  7144. * Parse US-Euro gpio info from DT. Report no error if us-euro
  7145. * entry is not found in DT file as some targets do not support
  7146. * US-Euro detection
  7147. */
  7148. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7149. "qcom,us-euro-gpios", 0);
  7150. if (!pdata->us_euro_gpio_p) {
  7151. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  7152. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  7153. } else {
  7154. dev_dbg(&pdev->dev, "%s detected\n",
  7155. "qcom,us-euro-gpios");
  7156. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  7157. }
  7158. if (wcd_mbhc_cfg.enable_usbc_analog)
  7159. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  7160. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  7161. "fsa4480-i2c-handle", 0);
  7162. if (!pdata->fsa_handle)
  7163. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  7164. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  7165. msm_i2s_auxpcm_init(pdev);
  7166. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7167. "qcom,cdc-dmic01-gpios",
  7168. 0);
  7169. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7170. "qcom,cdc-dmic23-gpios",
  7171. 0);
  7172. pdata->dmic45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7173. "qcom,cdc-dmic45-gpios",
  7174. 0);
  7175. if (pdata->dmic01_gpio_p)
  7176. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic01_gpio_p, false);
  7177. if (pdata->dmic23_gpio_p)
  7178. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic23_gpio_p, false);
  7179. if (pdata->dmic45_gpio_p)
  7180. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic45_gpio_p, false);
  7181. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7182. "qcom,pri-mi2s-gpios", 0);
  7183. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7184. "qcom,sec-mi2s-gpios", 0);
  7185. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7186. "qcom,tert-mi2s-gpios", 0);
  7187. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7188. "qcom,quat-mi2s-gpios", 0);
  7189. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7190. "qcom,quin-mi2s-gpios", 0);
  7191. pdata->mi2s_gpio_p[SEN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7192. "qcom,sen-mi2s-gpios", 0);
  7193. for (index = PRIM_MI2S; index < MI2S_MAX; index++)
  7194. atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0);
  7195. ret = msm_audio_ssr_register(&pdev->dev);
  7196. if (ret)
  7197. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  7198. __func__, ret);
  7199. is_initial_boot = true;
  7200. return 0;
  7201. err:
  7202. devm_kfree(&pdev->dev, pdata);
  7203. return ret;
  7204. }
  7205. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7206. {
  7207. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7208. snd_event_master_deregister(&pdev->dev);
  7209. snd_soc_unregister_card(card);
  7210. msm_i2s_auxpcm_deinit();
  7211. return 0;
  7212. }
  7213. static struct platform_driver kona_asoc_machine_driver = {
  7214. .driver = {
  7215. .name = DRV_NAME,
  7216. .owner = THIS_MODULE,
  7217. .pm = &snd_soc_pm_ops,
  7218. .of_match_table = kona_asoc_machine_of_match,
  7219. .suppress_bind_attrs = true,
  7220. },
  7221. .probe = msm_asoc_machine_probe,
  7222. .remove = msm_asoc_machine_remove,
  7223. };
  7224. module_platform_driver(kona_asoc_machine_driver);
  7225. MODULE_DESCRIPTION("ALSA SoC msm");
  7226. MODULE_LICENSE("GPL v2");
  7227. MODULE_ALIAS("platform:" DRV_NAME);
  7228. MODULE_DEVICE_TABLE(of, kona_asoc_machine_of_match);