dp_tx.c 107 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053
  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #define DP_TX_QUEUE_MASK 0x3
  33. /* TODO Add support in TSO */
  34. #define DP_DESC_NUM_FRAG(x) 0
  35. /* disable TQM_BYPASS */
  36. #define TQM_BYPASS_WAR 0
  37. /* invalid peer id for reinject*/
  38. #define DP_INVALID_PEER 0XFFFE
  39. /*mapping between hal encrypt type and cdp_sec_type*/
  40. #define MAX_CDP_SEC_TYPE 12
  41. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  42. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  43. HAL_TX_ENCRYPT_TYPE_WEP_128,
  44. HAL_TX_ENCRYPT_TYPE_WEP_104,
  45. HAL_TX_ENCRYPT_TYPE_WEP_40,
  46. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  47. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  48. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  49. HAL_TX_ENCRYPT_TYPE_WAPI,
  50. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  51. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  52. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  53. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  54. /**
  55. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  56. * @vdev: DP Virtual device handle
  57. * @nbuf: Buffer pointer
  58. * @queue: queue ids container for nbuf
  59. *
  60. * TX packet queue has 2 instances, software descriptors id and dma ring id
  61. * Based on tx feature and hardware configuration queue id combination could be
  62. * different.
  63. * For example -
  64. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  65. * With no XPS,lock based resource protection, Descriptor pool ids are different
  66. * for each vdev, dma ring id will be same as single pdev id
  67. *
  68. * Return: None
  69. */
  70. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  71. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  72. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  73. {
  74. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  75. queue->desc_pool_id = queue_offset;
  76. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  77. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  78. "%s, pool_id:%d ring_id: %d",
  79. __func__, queue->desc_pool_id, queue->ring_id);
  80. return;
  81. }
  82. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #endif
  95. #if defined(FEATURE_TSO)
  96. /**
  97. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  98. *
  99. * @soc - core txrx main context
  100. * @seg_desc - tso segment descriptor
  101. * @num_seg_desc - tso number segment descriptor
  102. */
  103. static void dp_tx_tso_unmap_segment(
  104. struct dp_soc *soc,
  105. struct qdf_tso_seg_elem_t *seg_desc,
  106. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  107. {
  108. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  109. if (qdf_unlikely(!seg_desc)) {
  110. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  111. __func__, __LINE__);
  112. qdf_assert(0);
  113. } else if (qdf_unlikely(!num_seg_desc)) {
  114. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  115. __func__, __LINE__);
  116. qdf_assert(0);
  117. } else {
  118. bool is_last_seg;
  119. /* no tso segment left to do dma unmap */
  120. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  121. return;
  122. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  123. true : false;
  124. qdf_nbuf_unmap_tso_segment(soc->osdev,
  125. seg_desc, is_last_seg);
  126. num_seg_desc->num_seg.tso_cmn_num_seg--;
  127. }
  128. }
  129. /**
  130. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  131. * back to the freelist
  132. *
  133. * @soc - soc device handle
  134. * @tx_desc - Tx software descriptor
  135. */
  136. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  137. struct dp_tx_desc_s *tx_desc)
  138. {
  139. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  140. if (qdf_unlikely(!tx_desc->tso_desc)) {
  141. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  142. "%s %d TSO desc is NULL!",
  143. __func__, __LINE__);
  144. qdf_assert(0);
  145. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  147. "%s %d TSO num desc is NULL!",
  148. __func__, __LINE__);
  149. qdf_assert(0);
  150. } else {
  151. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  152. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  153. /* Add the tso num segment into the free list */
  154. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  155. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  156. tx_desc->tso_num_desc);
  157. tx_desc->tso_num_desc = NULL;
  158. }
  159. /* Add the tso segment into the free list*/
  160. dp_tx_tso_desc_free(soc,
  161. tx_desc->pool_id, tx_desc->tso_desc);
  162. tx_desc->tso_desc = NULL;
  163. }
  164. }
  165. #else
  166. static void dp_tx_tso_unmap_segment(
  167. struct dp_soc *soc,
  168. struct qdf_tso_seg_elem_t *seg_desc,
  169. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  170. {
  171. }
  172. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  173. struct dp_tx_desc_s *tx_desc)
  174. {
  175. }
  176. #endif
  177. /**
  178. * dp_tx_desc_release() - Release Tx Descriptor
  179. * @tx_desc : Tx Descriptor
  180. * @desc_pool_id: Descriptor Pool ID
  181. *
  182. * Deallocate all resources attached to Tx descriptor and free the Tx
  183. * descriptor.
  184. *
  185. * Return:
  186. */
  187. static void
  188. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  189. {
  190. struct dp_pdev *pdev = tx_desc->pdev;
  191. struct dp_soc *soc;
  192. uint8_t comp_status = 0;
  193. qdf_assert(pdev);
  194. soc = pdev->soc;
  195. if (tx_desc->frm_type == dp_tx_frm_tso)
  196. dp_tx_tso_desc_release(soc, tx_desc);
  197. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  198. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  199. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  200. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  201. qdf_atomic_dec(&pdev->num_tx_outstanding);
  202. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  203. qdf_atomic_dec(&pdev->num_tx_exception);
  204. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  205. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  206. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  207. soc->hal_soc);
  208. else
  209. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  210. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  211. "Tx Completion Release desc %d status %d outstanding %d",
  212. tx_desc->id, comp_status,
  213. qdf_atomic_read(&pdev->num_tx_outstanding));
  214. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  215. return;
  216. }
  217. /**
  218. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  219. * @vdev: DP vdev Handle
  220. * @nbuf: skb
  221. *
  222. * Prepares and fills HTT metadata in the frame pre-header for special frames
  223. * that should be transmitted using varying transmit parameters.
  224. * There are 2 VDEV modes that currently needs this special metadata -
  225. * 1) Mesh Mode
  226. * 2) DSRC Mode
  227. *
  228. * Return: HTT metadata size
  229. *
  230. */
  231. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  232. uint32_t *meta_data)
  233. {
  234. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  235. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  236. uint8_t htt_desc_size;
  237. /* Size rounded of multiple of 8 bytes */
  238. uint8_t htt_desc_size_aligned;
  239. uint8_t *hdr = NULL;
  240. /*
  241. * Metadata - HTT MSDU Extension header
  242. */
  243. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  244. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  245. if (vdev->mesh_vdev) {
  246. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  247. htt_desc_size_aligned)) {
  248. DP_STATS_INC(vdev,
  249. tx_i.dropped.headroom_insufficient, 1);
  250. return 0;
  251. }
  252. /* Fill and add HTT metaheader */
  253. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  254. if (hdr == NULL) {
  255. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  256. "Error in filling HTT metadata");
  257. return 0;
  258. }
  259. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  260. } else if (vdev->opmode == wlan_op_mode_ocb) {
  261. /* Todo - Add support for DSRC */
  262. }
  263. return htt_desc_size_aligned;
  264. }
  265. /**
  266. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  267. * @tso_seg: TSO segment to process
  268. * @ext_desc: Pointer to MSDU extension descriptor
  269. *
  270. * Return: void
  271. */
  272. #if defined(FEATURE_TSO)
  273. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  274. void *ext_desc)
  275. {
  276. uint8_t num_frag;
  277. uint32_t tso_flags;
  278. /*
  279. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  280. * tcp_flag_mask
  281. *
  282. * Checksum enable flags are set in TCL descriptor and not in Extension
  283. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  284. */
  285. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  286. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  287. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  288. tso_seg->tso_flags.ip_len);
  289. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  290. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  291. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  292. uint32_t lo = 0;
  293. uint32_t hi = 0;
  294. qdf_dmaaddr_to_32s(
  295. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  296. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  297. tso_seg->tso_frags[num_frag].length);
  298. }
  299. return;
  300. }
  301. #else
  302. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  303. void *ext_desc)
  304. {
  305. return;
  306. }
  307. #endif
  308. #if defined(FEATURE_TSO)
  309. /**
  310. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  311. * allocated and free them
  312. *
  313. * @soc: soc handle
  314. * @free_seg: list of tso segments
  315. * @msdu_info: msdu descriptor
  316. *
  317. * Return - void
  318. */
  319. static void dp_tx_free_tso_seg_list(
  320. struct dp_soc *soc,
  321. struct qdf_tso_seg_elem_t *free_seg,
  322. struct dp_tx_msdu_info_s *msdu_info)
  323. {
  324. struct qdf_tso_seg_elem_t *next_seg;
  325. while (free_seg) {
  326. next_seg = free_seg->next;
  327. dp_tx_tso_desc_free(soc,
  328. msdu_info->tx_queue.desc_pool_id,
  329. free_seg);
  330. free_seg = next_seg;
  331. }
  332. }
  333. /**
  334. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  335. * allocated and free them
  336. *
  337. * @soc: soc handle
  338. * @free_num_seg: list of tso number segments
  339. * @msdu_info: msdu descriptor
  340. * Return - void
  341. */
  342. static void dp_tx_free_tso_num_seg_list(
  343. struct dp_soc *soc,
  344. struct qdf_tso_num_seg_elem_t *free_num_seg,
  345. struct dp_tx_msdu_info_s *msdu_info)
  346. {
  347. struct qdf_tso_num_seg_elem_t *next_num_seg;
  348. while (free_num_seg) {
  349. next_num_seg = free_num_seg->next;
  350. dp_tso_num_seg_free(soc,
  351. msdu_info->tx_queue.desc_pool_id,
  352. free_num_seg);
  353. free_num_seg = next_num_seg;
  354. }
  355. }
  356. /**
  357. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  358. * do dma unmap for each segment
  359. *
  360. * @soc: soc handle
  361. * @free_seg: list of tso segments
  362. * @num_seg_desc: tso number segment descriptor
  363. *
  364. * Return - void
  365. */
  366. static void dp_tx_unmap_tso_seg_list(
  367. struct dp_soc *soc,
  368. struct qdf_tso_seg_elem_t *free_seg,
  369. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  370. {
  371. struct qdf_tso_seg_elem_t *next_seg;
  372. if (qdf_unlikely(!num_seg_desc)) {
  373. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  374. return;
  375. }
  376. while (free_seg) {
  377. next_seg = free_seg->next;
  378. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  379. free_seg = next_seg;
  380. }
  381. }
  382. /**
  383. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  384. * free the tso segments descriptor and
  385. * tso num segments descriptor
  386. *
  387. * @soc: soc handle
  388. * @msdu_info: msdu descriptor
  389. * @tso_seg_unmap: flag to show if dma unmap is necessary
  390. *
  391. * Return - void
  392. */
  393. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  394. struct dp_tx_msdu_info_s *msdu_info,
  395. bool tso_seg_unmap)
  396. {
  397. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  398. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  399. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  400. tso_info->tso_num_seg_list;
  401. /* do dma unmap for each segment */
  402. if (tso_seg_unmap)
  403. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  404. /* free all tso number segment descriptor though looks only have 1 */
  405. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  406. /* free all tso segment descriptor */
  407. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  408. }
  409. /**
  410. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  411. * @vdev: virtual device handle
  412. * @msdu: network buffer
  413. * @msdu_info: meta data associated with the msdu
  414. *
  415. * Return: QDF_STATUS_SUCCESS success
  416. */
  417. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  418. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  419. {
  420. struct qdf_tso_seg_elem_t *tso_seg;
  421. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  422. struct dp_soc *soc = vdev->pdev->soc;
  423. struct qdf_tso_info_t *tso_info;
  424. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  425. tso_info = &msdu_info->u.tso_info;
  426. tso_info->curr_seg = NULL;
  427. tso_info->tso_seg_list = NULL;
  428. tso_info->num_segs = num_seg;
  429. msdu_info->frm_type = dp_tx_frm_tso;
  430. tso_info->tso_num_seg_list = NULL;
  431. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  432. while (num_seg) {
  433. tso_seg = dp_tx_tso_desc_alloc(
  434. soc, msdu_info->tx_queue.desc_pool_id);
  435. if (tso_seg) {
  436. tso_seg->next = tso_info->tso_seg_list;
  437. tso_info->tso_seg_list = tso_seg;
  438. num_seg--;
  439. } else {
  440. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  441. __func__);
  442. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  443. return QDF_STATUS_E_NOMEM;
  444. }
  445. }
  446. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  447. tso_num_seg = dp_tso_num_seg_alloc(soc,
  448. msdu_info->tx_queue.desc_pool_id);
  449. if (tso_num_seg) {
  450. tso_num_seg->next = tso_info->tso_num_seg_list;
  451. tso_info->tso_num_seg_list = tso_num_seg;
  452. } else {
  453. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  454. __func__);
  455. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  456. return QDF_STATUS_E_NOMEM;
  457. }
  458. msdu_info->num_seg =
  459. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  460. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  461. msdu_info->num_seg);
  462. if (!(msdu_info->num_seg)) {
  463. /*
  464. * Free allocated TSO seg desc and number seg desc,
  465. * do unmap for segments if dma map has done.
  466. */
  467. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  468. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  469. return QDF_STATUS_E_INVAL;
  470. }
  471. tso_info->curr_seg = tso_info->tso_seg_list;
  472. return QDF_STATUS_SUCCESS;
  473. }
  474. #else
  475. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  476. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  477. {
  478. return QDF_STATUS_E_NOMEM;
  479. }
  480. #endif
  481. /**
  482. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  483. * @vdev: DP Vdev handle
  484. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  485. * @desc_pool_id: Descriptor Pool ID
  486. *
  487. * Return:
  488. */
  489. static
  490. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  491. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  492. {
  493. uint8_t i;
  494. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  495. struct dp_tx_seg_info_s *seg_info;
  496. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  497. struct dp_soc *soc = vdev->pdev->soc;
  498. /* Allocate an extension descriptor */
  499. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  500. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  501. if (!msdu_ext_desc) {
  502. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  503. return NULL;
  504. }
  505. if (msdu_info->exception_fw &&
  506. qdf_unlikely(vdev->mesh_vdev)) {
  507. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  508. &msdu_info->meta_data[0],
  509. sizeof(struct htt_tx_msdu_desc_ext2_t));
  510. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  511. }
  512. switch (msdu_info->frm_type) {
  513. case dp_tx_frm_sg:
  514. case dp_tx_frm_me:
  515. case dp_tx_frm_raw:
  516. seg_info = msdu_info->u.sg_info.curr_seg;
  517. /* Update the buffer pointers in MSDU Extension Descriptor */
  518. for (i = 0; i < seg_info->frag_cnt; i++) {
  519. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  520. seg_info->frags[i].paddr_lo,
  521. seg_info->frags[i].paddr_hi,
  522. seg_info->frags[i].len);
  523. }
  524. break;
  525. case dp_tx_frm_tso:
  526. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  527. &cached_ext_desc[0]);
  528. break;
  529. default:
  530. break;
  531. }
  532. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  533. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  534. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  535. msdu_ext_desc->vaddr);
  536. return msdu_ext_desc;
  537. }
  538. /**
  539. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  540. *
  541. * @skb: skb to be traced
  542. * @msdu_id: msdu_id of the packet
  543. * @vdev_id: vdev_id of the packet
  544. *
  545. * Return: None
  546. */
  547. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  548. uint8_t vdev_id)
  549. {
  550. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  551. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  552. DPTRACE(qdf_dp_trace_ptr(skb,
  553. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  554. QDF_TRACE_DEFAULT_PDEV_ID,
  555. qdf_nbuf_data_addr(skb),
  556. sizeof(qdf_nbuf_data(skb)),
  557. msdu_id, vdev_id));
  558. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  559. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  560. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  561. msdu_id, QDF_TX));
  562. }
  563. /**
  564. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  565. * @vdev: DP vdev handle
  566. * @nbuf: skb
  567. * @desc_pool_id: Descriptor pool ID
  568. * @meta_data: Metadata to the fw
  569. * @tx_exc_metadata: Handle that holds exception path metadata
  570. * Allocate and prepare Tx descriptor with msdu information.
  571. *
  572. * Return: Pointer to Tx Descriptor on success,
  573. * NULL on failure
  574. */
  575. static
  576. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  577. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  578. struct dp_tx_msdu_info_s *msdu_info,
  579. struct cdp_tx_exception_metadata *tx_exc_metadata)
  580. {
  581. uint8_t align_pad;
  582. uint8_t is_exception = 0;
  583. uint8_t htt_hdr_size;
  584. struct ether_header *eh;
  585. struct dp_tx_desc_s *tx_desc;
  586. struct dp_pdev *pdev = vdev->pdev;
  587. struct dp_soc *soc = pdev->soc;
  588. /* Allocate software Tx descriptor */
  589. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  590. if (qdf_unlikely(!tx_desc)) {
  591. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  592. return NULL;
  593. }
  594. /* Flow control/Congestion Control counters */
  595. qdf_atomic_inc(&pdev->num_tx_outstanding);
  596. /* Initialize the SW tx descriptor */
  597. tx_desc->nbuf = nbuf;
  598. tx_desc->frm_type = dp_tx_frm_std;
  599. tx_desc->tx_encap_type = (tx_exc_metadata ?
  600. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  601. tx_desc->vdev = vdev;
  602. tx_desc->pdev = pdev;
  603. tx_desc->msdu_ext_desc = NULL;
  604. tx_desc->pkt_offset = 0;
  605. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  606. /* Reset the control block */
  607. qdf_nbuf_reset_ctxt(nbuf);
  608. /*
  609. * For special modes (vdev_type == ocb or mesh), data frames should be
  610. * transmitted using varying transmit parameters (tx spec) which include
  611. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  612. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  613. * These frames are sent as exception packets to firmware.
  614. *
  615. * HW requirement is that metadata should always point to a
  616. * 8-byte aligned address. So we add alignment pad to start of buffer.
  617. * HTT Metadata should be ensured to be multiple of 8-bytes,
  618. * to get 8-byte aligned start address along with align_pad added
  619. *
  620. * |-----------------------------|
  621. * | |
  622. * |-----------------------------| <-----Buffer Pointer Address given
  623. * | | ^ in HW descriptor (aligned)
  624. * | HTT Metadata | |
  625. * | | |
  626. * | | | Packet Offset given in descriptor
  627. * | | |
  628. * |-----------------------------| |
  629. * | Alignment Pad | v
  630. * |-----------------------------| <----- Actual buffer start address
  631. * | SKB Data | (Unaligned)
  632. * | |
  633. * | |
  634. * | |
  635. * | |
  636. * | |
  637. * |-----------------------------|
  638. */
  639. if (qdf_unlikely((msdu_info->exception_fw)) ||
  640. (vdev->opmode == wlan_op_mode_ocb)) {
  641. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  642. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  643. DP_STATS_INC(vdev,
  644. tx_i.dropped.headroom_insufficient, 1);
  645. goto failure;
  646. }
  647. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  648. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  649. "qdf_nbuf_push_head failed");
  650. goto failure;
  651. }
  652. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  653. msdu_info->meta_data);
  654. if (htt_hdr_size == 0)
  655. goto failure;
  656. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  657. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  658. is_exception = 1;
  659. }
  660. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  661. qdf_nbuf_map(soc->osdev, nbuf,
  662. QDF_DMA_TO_DEVICE))) {
  663. /* Handle failure */
  664. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  665. "qdf_nbuf_map failed");
  666. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  667. goto failure;
  668. }
  669. if (qdf_unlikely(vdev->nawds_enabled)) {
  670. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  671. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  672. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  673. is_exception = 1;
  674. }
  675. }
  676. #if !TQM_BYPASS_WAR
  677. if (is_exception || tx_exc_metadata)
  678. #endif
  679. {
  680. /* Temporary WAR due to TQM VP issues */
  681. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  682. qdf_atomic_inc(&pdev->num_tx_exception);
  683. }
  684. return tx_desc;
  685. failure:
  686. dp_tx_desc_release(tx_desc, desc_pool_id);
  687. return NULL;
  688. }
  689. /**
  690. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  691. * @vdev: DP vdev handle
  692. * @nbuf: skb
  693. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  694. * @desc_pool_id : Descriptor Pool ID
  695. *
  696. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  697. * information. For frames wth fragments, allocate and prepare
  698. * an MSDU extension descriptor
  699. *
  700. * Return: Pointer to Tx Descriptor on success,
  701. * NULL on failure
  702. */
  703. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  704. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  705. uint8_t desc_pool_id)
  706. {
  707. struct dp_tx_desc_s *tx_desc;
  708. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  709. struct dp_pdev *pdev = vdev->pdev;
  710. struct dp_soc *soc = pdev->soc;
  711. /* Allocate software Tx descriptor */
  712. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  713. if (!tx_desc) {
  714. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  715. return NULL;
  716. }
  717. /* Flow control/Congestion Control counters */
  718. qdf_atomic_inc(&pdev->num_tx_outstanding);
  719. /* Initialize the SW tx descriptor */
  720. tx_desc->nbuf = nbuf;
  721. tx_desc->frm_type = msdu_info->frm_type;
  722. tx_desc->tx_encap_type = vdev->tx_encap_type;
  723. tx_desc->vdev = vdev;
  724. tx_desc->pdev = pdev;
  725. tx_desc->pkt_offset = 0;
  726. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  727. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  728. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  729. /* Reset the control block */
  730. qdf_nbuf_reset_ctxt(nbuf);
  731. /* Handle scattered frames - TSO/SG/ME */
  732. /* Allocate and prepare an extension descriptor for scattered frames */
  733. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  734. if (!msdu_ext_desc) {
  735. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  736. "%s Tx Extension Descriptor Alloc Fail",
  737. __func__);
  738. goto failure;
  739. }
  740. #if TQM_BYPASS_WAR
  741. /* Temporary WAR due to TQM VP issues */
  742. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  743. qdf_atomic_inc(&pdev->num_tx_exception);
  744. #endif
  745. if (qdf_unlikely(msdu_info->exception_fw))
  746. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  747. tx_desc->msdu_ext_desc = msdu_ext_desc;
  748. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  749. return tx_desc;
  750. failure:
  751. dp_tx_desc_release(tx_desc, desc_pool_id);
  752. return NULL;
  753. }
  754. /**
  755. * dp_tx_prepare_raw() - Prepare RAW packet TX
  756. * @vdev: DP vdev handle
  757. * @nbuf: buffer pointer
  758. * @seg_info: Pointer to Segment info Descriptor to be prepared
  759. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  760. * descriptor
  761. *
  762. * Return:
  763. */
  764. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  765. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  766. {
  767. qdf_nbuf_t curr_nbuf = NULL;
  768. uint16_t total_len = 0;
  769. qdf_dma_addr_t paddr;
  770. int32_t i;
  771. int32_t mapped_buf_num = 0;
  772. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  773. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  774. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  775. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  776. if (vdev->raw_mode_war &&
  777. (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS))
  778. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  779. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  780. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  781. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  782. QDF_DMA_TO_DEVICE)) {
  783. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  784. "%s dma map error ", __func__);
  785. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  786. mapped_buf_num = i;
  787. goto error;
  788. }
  789. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  790. seg_info->frags[i].paddr_lo = paddr;
  791. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  792. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  793. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  794. total_len += qdf_nbuf_len(curr_nbuf);
  795. }
  796. seg_info->frag_cnt = i;
  797. seg_info->total_len = total_len;
  798. seg_info->next = NULL;
  799. sg_info->curr_seg = seg_info;
  800. msdu_info->frm_type = dp_tx_frm_raw;
  801. msdu_info->num_seg = 1;
  802. return nbuf;
  803. error:
  804. i = 0;
  805. while (nbuf) {
  806. curr_nbuf = nbuf;
  807. if (i < mapped_buf_num) {
  808. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  809. i++;
  810. }
  811. nbuf = qdf_nbuf_next(nbuf);
  812. qdf_nbuf_free(curr_nbuf);
  813. }
  814. return NULL;
  815. }
  816. /**
  817. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  818. * @soc: DP Soc Handle
  819. * @vdev: DP vdev handle
  820. * @tx_desc: Tx Descriptor Handle
  821. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  822. * @fw_metadata: Metadata to send to Target Firmware along with frame
  823. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  824. * @tx_exc_metadata: Handle that holds exception path meta data
  825. *
  826. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  827. * from software Tx descriptor
  828. *
  829. * Return:
  830. */
  831. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  832. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  833. uint16_t fw_metadata, uint8_t ring_id,
  834. struct cdp_tx_exception_metadata
  835. *tx_exc_metadata)
  836. {
  837. uint8_t type;
  838. uint16_t length;
  839. void *hal_tx_desc, *hal_tx_desc_cached;
  840. qdf_dma_addr_t dma_addr;
  841. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  842. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  843. tx_exc_metadata->sec_type : vdev->sec_type);
  844. /* Return Buffer Manager ID */
  845. uint8_t bm_id = ring_id;
  846. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  847. hal_tx_desc_cached = (void *) cached_desc;
  848. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  849. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  850. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  851. type = HAL_TX_BUF_TYPE_EXT_DESC;
  852. dma_addr = tx_desc->msdu_ext_desc->paddr;
  853. } else {
  854. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  855. type = HAL_TX_BUF_TYPE_BUFFER;
  856. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  857. }
  858. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  859. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  860. dma_addr, bm_id, tx_desc->id,
  861. type, soc->hal_soc);
  862. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  863. return QDF_STATUS_E_RESOURCES;
  864. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  865. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  866. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  867. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  868. vdev->pdev->lmac_id);
  869. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  870. vdev->search_type);
  871. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  872. vdev->bss_ast_hash);
  873. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  874. vdev->dscp_tid_map_id);
  875. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  876. sec_type_map[sec_type]);
  877. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  878. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  879. __func__, length, type, (uint64_t)dma_addr,
  880. tx_desc->pkt_offset, tx_desc->id);
  881. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  882. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  883. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  884. vdev->hal_desc_addr_search_flags);
  885. /* verify checksum offload configuration*/
  886. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  887. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  888. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  889. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  890. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  891. }
  892. if (tid != HTT_TX_EXT_TID_INVALID)
  893. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  894. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  895. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  896. /* Sync cached descriptor with HW */
  897. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  898. if (!hal_tx_desc) {
  899. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  900. "%s TCL ring full ring_id:%d", __func__, ring_id);
  901. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  902. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  903. return QDF_STATUS_E_RESOURCES;
  904. }
  905. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  906. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  907. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  908. return QDF_STATUS_SUCCESS;
  909. }
  910. /**
  911. * dp_cce_classify() - Classify the frame based on CCE rules
  912. * @vdev: DP vdev handle
  913. * @nbuf: skb
  914. *
  915. * Classify frames based on CCE rules
  916. * Return: bool( true if classified,
  917. * else false)
  918. */
  919. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  920. {
  921. struct ether_header *eh = NULL;
  922. uint16_t ether_type;
  923. qdf_llc_t *llcHdr;
  924. qdf_nbuf_t nbuf_clone = NULL;
  925. qdf_dot3_qosframe_t *qos_wh = NULL;
  926. /* for mesh packets don't do any classification */
  927. if (qdf_unlikely(vdev->mesh_vdev))
  928. return false;
  929. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  930. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  931. ether_type = eh->ether_type;
  932. llcHdr = (qdf_llc_t *)(nbuf->data +
  933. sizeof(struct ether_header));
  934. } else {
  935. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  936. /* For encrypted packets don't do any classification */
  937. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  938. return false;
  939. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  940. if (qdf_unlikely(
  941. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  942. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  943. ether_type = *(uint16_t *)(nbuf->data
  944. + QDF_IEEE80211_4ADDR_HDR_LEN
  945. + sizeof(qdf_llc_t)
  946. - sizeof(ether_type));
  947. llcHdr = (qdf_llc_t *)(nbuf->data +
  948. QDF_IEEE80211_4ADDR_HDR_LEN);
  949. } else {
  950. ether_type = *(uint16_t *)(nbuf->data
  951. + QDF_IEEE80211_3ADDR_HDR_LEN
  952. + sizeof(qdf_llc_t)
  953. - sizeof(ether_type));
  954. llcHdr = (qdf_llc_t *)(nbuf->data +
  955. QDF_IEEE80211_3ADDR_HDR_LEN);
  956. }
  957. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  958. && (ether_type ==
  959. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  960. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  961. return true;
  962. }
  963. }
  964. return false;
  965. }
  966. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  967. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  968. sizeof(*llcHdr));
  969. nbuf_clone = qdf_nbuf_clone(nbuf);
  970. if (qdf_unlikely(nbuf_clone)) {
  971. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  972. if (ether_type == htons(ETHERTYPE_8021Q)) {
  973. qdf_nbuf_pull_head(nbuf_clone,
  974. sizeof(qdf_net_vlanhdr_t));
  975. }
  976. }
  977. } else {
  978. if (ether_type == htons(ETHERTYPE_8021Q)) {
  979. nbuf_clone = qdf_nbuf_clone(nbuf);
  980. if (qdf_unlikely(nbuf_clone)) {
  981. qdf_nbuf_pull_head(nbuf_clone,
  982. sizeof(qdf_net_vlanhdr_t));
  983. }
  984. }
  985. }
  986. if (qdf_unlikely(nbuf_clone))
  987. nbuf = nbuf_clone;
  988. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  989. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  990. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  991. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  992. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  993. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  994. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  995. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  996. if (qdf_unlikely(nbuf_clone != NULL))
  997. qdf_nbuf_free(nbuf_clone);
  998. return true;
  999. }
  1000. if (qdf_unlikely(nbuf_clone != NULL))
  1001. qdf_nbuf_free(nbuf_clone);
  1002. return false;
  1003. }
  1004. /**
  1005. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1006. * @vdev: DP vdev handle
  1007. * @nbuf: skb
  1008. *
  1009. * Extract the DSCP or PCP information from frame and map into TID value.
  1010. * Software based TID classification is required when more than 2 DSCP-TID
  1011. * mapping tables are needed.
  1012. * Hardware supports 2 DSCP-TID mapping tables
  1013. *
  1014. * Return: void
  1015. */
  1016. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1017. struct dp_tx_msdu_info_s *msdu_info)
  1018. {
  1019. uint8_t tos = 0, dscp_tid_override = 0;
  1020. uint8_t *hdr_ptr, *L3datap;
  1021. uint8_t is_mcast = 0;
  1022. struct ether_header *eh = NULL;
  1023. qdf_ethervlan_header_t *evh = NULL;
  1024. uint16_t ether_type;
  1025. qdf_llc_t *llcHdr;
  1026. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1027. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1028. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1029. return;
  1030. /* for mesh packets don't do any classification */
  1031. if (qdf_unlikely(vdev->mesh_vdev))
  1032. return;
  1033. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1034. eh = (struct ether_header *) nbuf->data;
  1035. hdr_ptr = eh->ether_dhost;
  1036. L3datap = hdr_ptr + sizeof(struct ether_header);
  1037. } else {
  1038. qdf_dot3_qosframe_t *qos_wh =
  1039. (qdf_dot3_qosframe_t *) nbuf->data;
  1040. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1041. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1042. return;
  1043. }
  1044. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1045. ether_type = eh->ether_type;
  1046. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  1047. /*
  1048. * Check if packet is dot3 or eth2 type.
  1049. */
  1050. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1051. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  1052. sizeof(*llcHdr));
  1053. if (ether_type == htons(ETHERTYPE_8021Q)) {
  1054. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1055. sizeof(*llcHdr);
  1056. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  1057. + sizeof(*llcHdr) +
  1058. sizeof(qdf_net_vlanhdr_t));
  1059. } else {
  1060. L3datap = hdr_ptr + sizeof(struct ether_header) +
  1061. sizeof(*llcHdr);
  1062. }
  1063. } else {
  1064. if (ether_type == htons(ETHERTYPE_8021Q)) {
  1065. evh = (qdf_ethervlan_header_t *) eh;
  1066. ether_type = evh->ether_type;
  1067. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1068. }
  1069. }
  1070. /*
  1071. * Find priority from IP TOS DSCP field
  1072. */
  1073. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1074. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1075. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1076. /* Only for unicast frames */
  1077. if (!is_mcast) {
  1078. /* send it on VO queue */
  1079. msdu_info->tid = DP_VO_TID;
  1080. }
  1081. } else {
  1082. /*
  1083. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1084. * from TOS byte.
  1085. */
  1086. tos = ip->ip_tos;
  1087. dscp_tid_override = 1;
  1088. }
  1089. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1090. /* TODO
  1091. * use flowlabel
  1092. *igmpmld cases to be handled in phase 2
  1093. */
  1094. unsigned long ver_pri_flowlabel;
  1095. unsigned long pri;
  1096. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1097. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1098. DP_IPV6_PRIORITY_SHIFT;
  1099. tos = pri;
  1100. dscp_tid_override = 1;
  1101. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1102. msdu_info->tid = DP_VO_TID;
  1103. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1104. /* Only for unicast frames */
  1105. if (!is_mcast) {
  1106. /* send ucast arp on VO queue */
  1107. msdu_info->tid = DP_VO_TID;
  1108. }
  1109. }
  1110. /*
  1111. * Assign all MCAST packets to BE
  1112. */
  1113. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1114. if (is_mcast) {
  1115. tos = 0;
  1116. dscp_tid_override = 1;
  1117. }
  1118. }
  1119. if (dscp_tid_override == 1) {
  1120. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1121. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1122. }
  1123. return;
  1124. }
  1125. #ifdef CONVERGED_TDLS_ENABLE
  1126. /**
  1127. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1128. * @tx_desc: TX descriptor
  1129. *
  1130. * Return: None
  1131. */
  1132. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1133. {
  1134. if (tx_desc->vdev) {
  1135. if (tx_desc->vdev->is_tdls_frame) {
  1136. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1137. tx_desc->vdev->is_tdls_frame = false;
  1138. }
  1139. }
  1140. }
  1141. /**
  1142. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1143. * @tx_desc: TX descriptor
  1144. * @vdev: datapath vdev handle
  1145. *
  1146. * Return: None
  1147. */
  1148. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1149. struct dp_vdev *vdev)
  1150. {
  1151. struct hal_tx_completion_status ts = {0};
  1152. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1153. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1154. if (vdev->tx_non_std_data_callback.func) {
  1155. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1156. vdev->tx_non_std_data_callback.func(
  1157. vdev->tx_non_std_data_callback.ctxt,
  1158. nbuf, ts.status);
  1159. return;
  1160. }
  1161. }
  1162. #endif
  1163. /**
  1164. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1165. * @vdev: DP vdev handle
  1166. * @nbuf: skb
  1167. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1168. * @meta_data: Metadata to the fw
  1169. * @tx_q: Tx queue to be used for this Tx frame
  1170. * @peer_id: peer_id of the peer in case of NAWDS frames
  1171. * @tx_exc_metadata: Handle that holds exception path metadata
  1172. *
  1173. * Return: NULL on success,
  1174. * nbuf when it fails to send
  1175. */
  1176. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1177. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1178. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1179. {
  1180. struct dp_pdev *pdev = vdev->pdev;
  1181. struct dp_soc *soc = pdev->soc;
  1182. struct dp_tx_desc_s *tx_desc;
  1183. QDF_STATUS status;
  1184. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1185. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1186. uint16_t htt_tcl_metadata = 0;
  1187. uint8_t tid = msdu_info->tid;
  1188. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1189. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1190. msdu_info, tx_exc_metadata);
  1191. if (!tx_desc) {
  1192. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1193. "%s Tx_desc prepare Fail vdev %pK queue %d",
  1194. __func__, vdev, tx_q->desc_pool_id);
  1195. return nbuf;
  1196. }
  1197. if (qdf_unlikely(soc->cce_disable)) {
  1198. if (dp_cce_classify(vdev, nbuf) == true) {
  1199. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1200. tid = DP_VO_TID;
  1201. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1202. }
  1203. }
  1204. dp_tx_update_tdls_flags(tx_desc);
  1205. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1206. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1207. "%s %d : HAL RING Access Failed -- %pK",
  1208. __func__, __LINE__, hal_srng);
  1209. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1210. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1211. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1212. goto fail_return;
  1213. }
  1214. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1215. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1216. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1217. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1218. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1219. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1220. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1221. peer_id);
  1222. } else
  1223. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1224. if (msdu_info->exception_fw) {
  1225. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1226. }
  1227. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1228. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1229. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1230. if (status != QDF_STATUS_SUCCESS) {
  1231. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1232. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1233. __func__, tx_desc, tx_q->ring_id);
  1234. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1235. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1236. goto fail_return;
  1237. }
  1238. nbuf = NULL;
  1239. fail_return:
  1240. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1241. hal_srng_access_end(soc->hal_soc, hal_srng);
  1242. hif_pm_runtime_put(soc->hif_handle);
  1243. } else {
  1244. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1245. }
  1246. return nbuf;
  1247. }
  1248. /**
  1249. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1250. * @vdev: DP vdev handle
  1251. * @nbuf: skb
  1252. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1253. *
  1254. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1255. *
  1256. * Return: NULL on success,
  1257. * nbuf when it fails to send
  1258. */
  1259. #if QDF_LOCK_STATS
  1260. static noinline
  1261. #else
  1262. static
  1263. #endif
  1264. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1265. struct dp_tx_msdu_info_s *msdu_info)
  1266. {
  1267. uint8_t i;
  1268. struct dp_pdev *pdev = vdev->pdev;
  1269. struct dp_soc *soc = pdev->soc;
  1270. struct dp_tx_desc_s *tx_desc;
  1271. bool is_cce_classified = false;
  1272. QDF_STATUS status;
  1273. uint16_t htt_tcl_metadata = 0;
  1274. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1275. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1276. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1277. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1278. "%s %d : HAL RING Access Failed -- %pK",
  1279. __func__, __LINE__, hal_srng);
  1280. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1281. return nbuf;
  1282. }
  1283. if (qdf_unlikely(soc->cce_disable)) {
  1284. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1285. if (is_cce_classified) {
  1286. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1287. msdu_info->tid = DP_VO_TID;
  1288. }
  1289. }
  1290. if (msdu_info->frm_type == dp_tx_frm_me)
  1291. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1292. i = 0;
  1293. /* Print statement to track i and num_seg */
  1294. /*
  1295. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1296. * descriptors using information in msdu_info
  1297. */
  1298. while (i < msdu_info->num_seg) {
  1299. /*
  1300. * Setup Tx descriptor for an MSDU, and MSDU extension
  1301. * descriptor
  1302. */
  1303. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1304. tx_q->desc_pool_id);
  1305. if (!tx_desc) {
  1306. if (msdu_info->frm_type == dp_tx_frm_me) {
  1307. dp_tx_me_free_buf(pdev,
  1308. (void *)(msdu_info->u.sg_info
  1309. .curr_seg->frags[0].vaddr));
  1310. }
  1311. goto done;
  1312. }
  1313. if (msdu_info->frm_type == dp_tx_frm_me) {
  1314. tx_desc->me_buffer =
  1315. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1316. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1317. }
  1318. if (is_cce_classified)
  1319. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1320. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1321. if (msdu_info->exception_fw) {
  1322. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1323. }
  1324. /*
  1325. * Enqueue the Tx MSDU descriptor to HW for transmit
  1326. */
  1327. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1328. htt_tcl_metadata, tx_q->ring_id, NULL);
  1329. if (status != QDF_STATUS_SUCCESS) {
  1330. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1331. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1332. __func__, tx_desc, tx_q->ring_id);
  1333. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1334. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1335. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1336. goto done;
  1337. }
  1338. /*
  1339. * TODO
  1340. * if tso_info structure can be modified to have curr_seg
  1341. * as first element, following 2 blocks of code (for TSO and SG)
  1342. * can be combined into 1
  1343. */
  1344. /*
  1345. * For frames with multiple segments (TSO, ME), jump to next
  1346. * segment.
  1347. */
  1348. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1349. if (msdu_info->u.tso_info.curr_seg->next) {
  1350. msdu_info->u.tso_info.curr_seg =
  1351. msdu_info->u.tso_info.curr_seg->next;
  1352. /*
  1353. * If this is a jumbo nbuf, then increment the number of
  1354. * nbuf users for each additional segment of the msdu.
  1355. * This will ensure that the skb is freed only after
  1356. * receiving tx completion for all segments of an nbuf
  1357. */
  1358. qdf_nbuf_inc_users(nbuf);
  1359. /* Check with MCL if this is needed */
  1360. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1361. }
  1362. }
  1363. /*
  1364. * For Multicast-Unicast converted packets,
  1365. * each converted frame (for a client) is represented as
  1366. * 1 segment
  1367. */
  1368. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1369. (msdu_info->frm_type == dp_tx_frm_me)) {
  1370. if (msdu_info->u.sg_info.curr_seg->next) {
  1371. msdu_info->u.sg_info.curr_seg =
  1372. msdu_info->u.sg_info.curr_seg->next;
  1373. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1374. }
  1375. }
  1376. i++;
  1377. }
  1378. nbuf = NULL;
  1379. done:
  1380. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1381. hal_srng_access_end(soc->hal_soc, hal_srng);
  1382. hif_pm_runtime_put(soc->hif_handle);
  1383. } else {
  1384. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1385. }
  1386. return nbuf;
  1387. }
  1388. /**
  1389. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1390. * for SG frames
  1391. * @vdev: DP vdev handle
  1392. * @nbuf: skb
  1393. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1394. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1395. *
  1396. * Return: NULL on success,
  1397. * nbuf when it fails to send
  1398. */
  1399. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1400. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1401. {
  1402. uint32_t cur_frag, nr_frags;
  1403. qdf_dma_addr_t paddr;
  1404. struct dp_tx_sg_info_s *sg_info;
  1405. sg_info = &msdu_info->u.sg_info;
  1406. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1407. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1408. QDF_DMA_TO_DEVICE)) {
  1409. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1410. "dma map error");
  1411. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1412. qdf_nbuf_free(nbuf);
  1413. return NULL;
  1414. }
  1415. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1416. seg_info->frags[0].paddr_lo = paddr;
  1417. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1418. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1419. seg_info->frags[0].vaddr = (void *) nbuf;
  1420. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1421. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1422. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1423. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1424. "frag dma map error");
  1425. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1426. qdf_nbuf_free(nbuf);
  1427. return NULL;
  1428. }
  1429. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1430. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1431. seg_info->frags[cur_frag + 1].paddr_hi =
  1432. ((uint64_t) paddr) >> 32;
  1433. seg_info->frags[cur_frag + 1].len =
  1434. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1435. }
  1436. seg_info->frag_cnt = (cur_frag + 1);
  1437. seg_info->total_len = qdf_nbuf_len(nbuf);
  1438. seg_info->next = NULL;
  1439. sg_info->curr_seg = seg_info;
  1440. msdu_info->frm_type = dp_tx_frm_sg;
  1441. msdu_info->num_seg = 1;
  1442. return nbuf;
  1443. }
  1444. #ifdef MESH_MODE_SUPPORT
  1445. /**
  1446. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1447. and prepare msdu_info for mesh frames.
  1448. * @vdev: DP vdev handle
  1449. * @nbuf: skb
  1450. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1451. *
  1452. * Return: NULL on failure,
  1453. * nbuf when extracted successfully
  1454. */
  1455. static
  1456. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1457. struct dp_tx_msdu_info_s *msdu_info)
  1458. {
  1459. struct meta_hdr_s *mhdr;
  1460. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1461. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1462. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1463. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1464. msdu_info->exception_fw = 0;
  1465. goto remove_meta_hdr;
  1466. }
  1467. msdu_info->exception_fw = 1;
  1468. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1469. meta_data->host_tx_desc_pool = 1;
  1470. meta_data->update_peer_cache = 1;
  1471. meta_data->learning_frame = 1;
  1472. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1473. meta_data->power = mhdr->power;
  1474. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1475. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1476. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1477. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1478. meta_data->dyn_bw = 1;
  1479. meta_data->valid_pwr = 1;
  1480. meta_data->valid_mcs_mask = 1;
  1481. meta_data->valid_nss_mask = 1;
  1482. meta_data->valid_preamble_type = 1;
  1483. meta_data->valid_retries = 1;
  1484. meta_data->valid_bw_info = 1;
  1485. }
  1486. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1487. meta_data->encrypt_type = 0;
  1488. meta_data->valid_encrypt_type = 1;
  1489. meta_data->learning_frame = 0;
  1490. }
  1491. meta_data->valid_key_flags = 1;
  1492. meta_data->key_flags = (mhdr->keyix & 0x3);
  1493. remove_meta_hdr:
  1494. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1495. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1496. "qdf_nbuf_pull_head failed");
  1497. qdf_nbuf_free(nbuf);
  1498. return NULL;
  1499. }
  1500. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1501. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1502. else
  1503. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1504. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1505. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1506. " tid %d to_fw %d",
  1507. __func__, msdu_info->meta_data[0],
  1508. msdu_info->meta_data[1],
  1509. msdu_info->meta_data[2],
  1510. msdu_info->meta_data[3],
  1511. msdu_info->meta_data[4],
  1512. msdu_info->meta_data[5],
  1513. msdu_info->tid, msdu_info->exception_fw);
  1514. return nbuf;
  1515. }
  1516. #else
  1517. static
  1518. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1519. struct dp_tx_msdu_info_s *msdu_info)
  1520. {
  1521. return nbuf;
  1522. }
  1523. #endif
  1524. #ifdef DP_FEATURE_NAWDS_TX
  1525. /**
  1526. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1527. * @vdev: dp_vdev handle
  1528. * @nbuf: skb
  1529. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1530. * @tx_q: Tx queue to be used for this Tx frame
  1531. * @meta_data: Meta date for mesh
  1532. * @peer_id: peer_id of the peer in case of NAWDS frames
  1533. *
  1534. * return: NULL on success nbuf on failure
  1535. */
  1536. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1537. struct dp_tx_msdu_info_s *msdu_info)
  1538. {
  1539. struct dp_peer *peer = NULL;
  1540. struct dp_soc *soc = vdev->pdev->soc;
  1541. struct dp_ast_entry *ast_entry = NULL;
  1542. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1543. uint16_t peer_id = HTT_INVALID_PEER;
  1544. struct dp_peer *sa_peer = NULL;
  1545. qdf_nbuf_t nbuf_copy;
  1546. qdf_spin_lock_bh(&(soc->ast_lock));
  1547. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1548. (soc,
  1549. (uint8_t *)(eh->ether_shost),
  1550. vdev->pdev->pdev_id);
  1551. if (ast_entry)
  1552. sa_peer = ast_entry->peer;
  1553. qdf_spin_unlock_bh(&(soc->ast_lock));
  1554. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1555. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1556. (peer->nawds_enabled)) {
  1557. if (sa_peer == peer) {
  1558. QDF_TRACE(QDF_MODULE_ID_DP,
  1559. QDF_TRACE_LEVEL_DEBUG,
  1560. " %s: broadcast multicast packet",
  1561. __func__);
  1562. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1563. continue;
  1564. }
  1565. nbuf_copy = qdf_nbuf_copy(nbuf);
  1566. if (!nbuf_copy) {
  1567. QDF_TRACE(QDF_MODULE_ID_DP,
  1568. QDF_TRACE_LEVEL_ERROR,
  1569. "nbuf copy failed");
  1570. }
  1571. peer_id = peer->peer_ids[0];
  1572. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1573. msdu_info, peer_id, NULL);
  1574. if (nbuf_copy != NULL) {
  1575. qdf_nbuf_free(nbuf_copy);
  1576. continue;
  1577. }
  1578. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1579. 1, qdf_nbuf_len(nbuf));
  1580. }
  1581. }
  1582. if (peer_id == HTT_INVALID_PEER)
  1583. return nbuf;
  1584. return NULL;
  1585. }
  1586. #endif
  1587. /**
  1588. * dp_check_exc_metadata() - Checks if parameters are valid
  1589. * @tx_exc - holds all exception path parameters
  1590. *
  1591. * Returns true when all the parameters are valid else false
  1592. *
  1593. */
  1594. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1595. {
  1596. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1597. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1598. tx_exc->sec_type > cdp_num_sec_types) {
  1599. return false;
  1600. }
  1601. return true;
  1602. }
  1603. /**
  1604. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1605. * @vap_dev: DP vdev handle
  1606. * @nbuf: skb
  1607. * @tx_exc_metadata: Handle that holds exception path meta data
  1608. *
  1609. * Entry point for Core Tx layer (DP_TX) invoked from
  1610. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1611. *
  1612. * Return: NULL on success,
  1613. * nbuf when it fails to send
  1614. */
  1615. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1616. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1617. {
  1618. struct ether_header *eh = NULL;
  1619. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1620. struct dp_tx_msdu_info_s msdu_info;
  1621. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1622. msdu_info.tid = tx_exc_metadata->tid;
  1623. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1624. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1625. "%s , skb %pM",
  1626. __func__, nbuf->data);
  1627. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1628. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1629. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1630. "Invalid parameters in exception path");
  1631. goto fail;
  1632. }
  1633. /* Basic sanity checks for unsupported packets */
  1634. /* MESH mode */
  1635. if (qdf_unlikely(vdev->mesh_vdev)) {
  1636. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1637. "Mesh mode is not supported in exception path");
  1638. goto fail;
  1639. }
  1640. /* TSO or SG */
  1641. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1642. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1643. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1644. "TSO and SG are not supported in exception path");
  1645. goto fail;
  1646. }
  1647. /* RAW */
  1648. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1649. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1650. "Raw frame is not supported in exception path");
  1651. goto fail;
  1652. }
  1653. /* Mcast enhancement*/
  1654. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1655. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1656. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1657. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1658. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1659. }
  1660. }
  1661. /*
  1662. * Get HW Queue to use for this frame.
  1663. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1664. * dedicated for data and 1 for command.
  1665. * "queue_id" maps to one hardware ring.
  1666. * With each ring, we also associate a unique Tx descriptor pool
  1667. * to minimize lock contention for these resources.
  1668. */
  1669. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1670. /* Single linear frame */
  1671. /*
  1672. * If nbuf is a simple linear frame, use send_single function to
  1673. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1674. * SRNG. There is no need to setup a MSDU extension descriptor.
  1675. */
  1676. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1677. tx_exc_metadata->peer_id, tx_exc_metadata);
  1678. return nbuf;
  1679. fail:
  1680. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1681. "pkt send failed");
  1682. return nbuf;
  1683. }
  1684. /**
  1685. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1686. * @vap_dev: DP vdev handle
  1687. * @nbuf: skb
  1688. *
  1689. * Entry point for Core Tx layer (DP_TX) invoked from
  1690. * hard_start_xmit in OSIF/HDD
  1691. *
  1692. * Return: NULL on success,
  1693. * nbuf when it fails to send
  1694. */
  1695. #ifdef MESH_MODE_SUPPORT
  1696. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1697. {
  1698. struct meta_hdr_s *mhdr;
  1699. qdf_nbuf_t nbuf_mesh = NULL;
  1700. qdf_nbuf_t nbuf_clone = NULL;
  1701. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1702. uint8_t no_enc_frame = 0;
  1703. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1704. if (nbuf_mesh == NULL) {
  1705. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1706. "qdf_nbuf_unshare failed");
  1707. return nbuf;
  1708. }
  1709. nbuf = nbuf_mesh;
  1710. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1711. if ((vdev->sec_type != cdp_sec_type_none) &&
  1712. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1713. no_enc_frame = 1;
  1714. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1715. !no_enc_frame) {
  1716. nbuf_clone = qdf_nbuf_clone(nbuf);
  1717. if (nbuf_clone == NULL) {
  1718. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1719. "qdf_nbuf_clone failed");
  1720. return nbuf;
  1721. }
  1722. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1723. }
  1724. if (nbuf_clone) {
  1725. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1726. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1727. } else {
  1728. qdf_nbuf_free(nbuf_clone);
  1729. }
  1730. }
  1731. if (no_enc_frame)
  1732. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1733. else
  1734. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1735. nbuf = dp_tx_send(vap_dev, nbuf);
  1736. if ((nbuf == NULL) && no_enc_frame) {
  1737. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1738. }
  1739. return nbuf;
  1740. }
  1741. #else
  1742. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1743. {
  1744. return dp_tx_send(vap_dev, nbuf);
  1745. }
  1746. #endif
  1747. /**
  1748. * dp_tx_send() - Transmit a frame on a given VAP
  1749. * @vap_dev: DP vdev handle
  1750. * @nbuf: skb
  1751. *
  1752. * Entry point for Core Tx layer (DP_TX) invoked from
  1753. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1754. * cases
  1755. *
  1756. * Return: NULL on success,
  1757. * nbuf when it fails to send
  1758. */
  1759. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1760. {
  1761. struct ether_header *eh = NULL;
  1762. struct dp_tx_msdu_info_s msdu_info;
  1763. struct dp_tx_seg_info_s seg_info;
  1764. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1765. uint16_t peer_id = HTT_INVALID_PEER;
  1766. qdf_nbuf_t nbuf_mesh = NULL;
  1767. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1768. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1769. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1770. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1771. "%s , skb %pM",
  1772. __func__, nbuf->data);
  1773. /*
  1774. * Set Default Host TID value to invalid TID
  1775. * (TID override disabled)
  1776. */
  1777. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1778. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1779. if (qdf_unlikely(vdev->mesh_vdev)) {
  1780. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1781. &msdu_info);
  1782. if (nbuf_mesh == NULL) {
  1783. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1784. "Extracting mesh metadata failed");
  1785. return nbuf;
  1786. }
  1787. nbuf = nbuf_mesh;
  1788. }
  1789. /*
  1790. * Get HW Queue to use for this frame.
  1791. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1792. * dedicated for data and 1 for command.
  1793. * "queue_id" maps to one hardware ring.
  1794. * With each ring, we also associate a unique Tx descriptor pool
  1795. * to minimize lock contention for these resources.
  1796. */
  1797. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1798. /*
  1799. * TCL H/W supports 2 DSCP-TID mapping tables.
  1800. * Table 1 - Default DSCP-TID mapping table
  1801. * Table 2 - 1 DSCP-TID override table
  1802. *
  1803. * If we need a different DSCP-TID mapping for this vap,
  1804. * call tid_classify to extract DSCP/ToS from frame and
  1805. * map to a TID and store in msdu_info. This is later used
  1806. * to fill in TCL Input descriptor (per-packet TID override).
  1807. */
  1808. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1809. /*
  1810. * Classify the frame and call corresponding
  1811. * "prepare" function which extracts the segment (TSO)
  1812. * and fragmentation information (for TSO , SG, ME, or Raw)
  1813. * into MSDU_INFO structure which is later used to fill
  1814. * SW and HW descriptors.
  1815. */
  1816. if (qdf_nbuf_is_tso(nbuf)) {
  1817. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1818. "%s TSO frame %pK", __func__, vdev);
  1819. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1820. qdf_nbuf_len(nbuf));
  1821. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1822. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1823. qdf_nbuf_len(nbuf));
  1824. return nbuf;
  1825. }
  1826. goto send_multiple;
  1827. }
  1828. /* SG */
  1829. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1830. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1831. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1832. "%s non-TSO SG frame %pK", __func__, vdev);
  1833. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1834. qdf_nbuf_len(nbuf));
  1835. goto send_multiple;
  1836. }
  1837. #ifdef ATH_SUPPORT_IQUE
  1838. /* Mcast to Ucast Conversion*/
  1839. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1840. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1841. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1842. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1843. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1844. "%s Mcast frm for ME %pK", __func__, vdev);
  1845. DP_STATS_INC_PKT(vdev,
  1846. tx_i.mcast_en.mcast_pkt, 1,
  1847. qdf_nbuf_len(nbuf));
  1848. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1849. QDF_STATUS_SUCCESS) {
  1850. return NULL;
  1851. }
  1852. }
  1853. }
  1854. #endif
  1855. /* RAW */
  1856. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1857. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1858. if (nbuf == NULL)
  1859. return NULL;
  1860. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1861. "%s Raw frame %pK", __func__, vdev);
  1862. goto send_multiple;
  1863. }
  1864. /* Single linear frame */
  1865. /*
  1866. * If nbuf is a simple linear frame, use send_single function to
  1867. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1868. * SRNG. There is no need to setup a MSDU extension descriptor.
  1869. */
  1870. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1871. return nbuf;
  1872. send_multiple:
  1873. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1874. return nbuf;
  1875. }
  1876. /**
  1877. * dp_tx_reinject_handler() - Tx Reinject Handler
  1878. * @tx_desc: software descriptor head pointer
  1879. * @status : Tx completion status from HTT descriptor
  1880. *
  1881. * This function reinjects frames back to Target.
  1882. * Todo - Host queue needs to be added
  1883. *
  1884. * Return: none
  1885. */
  1886. static
  1887. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1888. {
  1889. struct dp_vdev *vdev;
  1890. struct dp_peer *peer = NULL;
  1891. uint32_t peer_id = HTT_INVALID_PEER;
  1892. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1893. qdf_nbuf_t nbuf_copy = NULL;
  1894. struct dp_tx_msdu_info_s msdu_info;
  1895. struct dp_peer *sa_peer = NULL;
  1896. struct dp_ast_entry *ast_entry = NULL;
  1897. struct dp_soc *soc = NULL;
  1898. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1899. #ifdef WDS_VENDOR_EXTENSION
  1900. int is_mcast = 0, is_ucast = 0;
  1901. int num_peers_3addr = 0;
  1902. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1903. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1904. #endif
  1905. vdev = tx_desc->vdev;
  1906. soc = vdev->pdev->soc;
  1907. qdf_assert(vdev);
  1908. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1909. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1910. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1911. "%s Tx reinject path", __func__);
  1912. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1913. qdf_nbuf_len(tx_desc->nbuf));
  1914. qdf_spin_lock_bh(&(soc->ast_lock));
  1915. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1916. (soc,
  1917. (uint8_t *)(eh->ether_shost),
  1918. vdev->pdev->pdev_id);
  1919. if (ast_entry)
  1920. sa_peer = ast_entry->peer;
  1921. qdf_spin_unlock_bh(&(soc->ast_lock));
  1922. #ifdef WDS_VENDOR_EXTENSION
  1923. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1924. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1925. } else {
  1926. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1927. }
  1928. is_ucast = !is_mcast;
  1929. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1930. if (peer->bss_peer)
  1931. continue;
  1932. /* Detect wds peers that use 3-addr framing for mcast.
  1933. * if there are any, the bss_peer is used to send the
  1934. * the mcast frame using 3-addr format. all wds enabled
  1935. * peers that use 4-addr framing for mcast frames will
  1936. * be duplicated and sent as 4-addr frames below.
  1937. */
  1938. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1939. num_peers_3addr = 1;
  1940. break;
  1941. }
  1942. }
  1943. #endif
  1944. if (qdf_unlikely(vdev->mesh_vdev)) {
  1945. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1946. } else {
  1947. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1948. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1949. #ifdef WDS_VENDOR_EXTENSION
  1950. /*
  1951. * . if 3-addr STA, then send on BSS Peer
  1952. * . if Peer WDS enabled and accept 4-addr mcast,
  1953. * send mcast on that peer only
  1954. * . if Peer WDS enabled and accept 4-addr ucast,
  1955. * send ucast on that peer only
  1956. */
  1957. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1958. (peer->wds_enabled &&
  1959. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1960. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1961. #else
  1962. ((peer->bss_peer &&
  1963. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1964. peer->nawds_enabled)) {
  1965. #endif
  1966. peer_id = DP_INVALID_PEER;
  1967. if (peer->nawds_enabled) {
  1968. peer_id = peer->peer_ids[0];
  1969. if (sa_peer == peer) {
  1970. QDF_TRACE(
  1971. QDF_MODULE_ID_DP,
  1972. QDF_TRACE_LEVEL_DEBUG,
  1973. " %s: multicast packet",
  1974. __func__);
  1975. DP_STATS_INC(peer,
  1976. tx.nawds_mcast_drop, 1);
  1977. continue;
  1978. }
  1979. }
  1980. nbuf_copy = qdf_nbuf_copy(nbuf);
  1981. if (!nbuf_copy) {
  1982. QDF_TRACE(QDF_MODULE_ID_DP,
  1983. QDF_TRACE_LEVEL_DEBUG,
  1984. FL("nbuf copy failed"));
  1985. break;
  1986. }
  1987. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1988. nbuf_copy,
  1989. &msdu_info,
  1990. peer_id,
  1991. NULL);
  1992. if (nbuf_copy) {
  1993. QDF_TRACE(QDF_MODULE_ID_DP,
  1994. QDF_TRACE_LEVEL_DEBUG,
  1995. FL("pkt send failed"));
  1996. qdf_nbuf_free(nbuf_copy);
  1997. } else {
  1998. if (peer_id != DP_INVALID_PEER)
  1999. DP_STATS_INC_PKT(peer,
  2000. tx.nawds_mcast,
  2001. 1, qdf_nbuf_len(nbuf));
  2002. }
  2003. }
  2004. }
  2005. }
  2006. if (vdev->nawds_enabled) {
  2007. peer_id = DP_INVALID_PEER;
  2008. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2009. 1, qdf_nbuf_len(nbuf));
  2010. nbuf = dp_tx_send_msdu_single(vdev,
  2011. nbuf,
  2012. &msdu_info,
  2013. peer_id, NULL);
  2014. if (nbuf) {
  2015. QDF_TRACE(QDF_MODULE_ID_DP,
  2016. QDF_TRACE_LEVEL_DEBUG,
  2017. FL("pkt send failed"));
  2018. qdf_nbuf_free(nbuf);
  2019. }
  2020. } else
  2021. qdf_nbuf_free(nbuf);
  2022. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2023. }
  2024. /**
  2025. * dp_tx_inspect_handler() - Tx Inspect Handler
  2026. * @tx_desc: software descriptor head pointer
  2027. * @status : Tx completion status from HTT descriptor
  2028. *
  2029. * Handles Tx frames sent back to Host for inspection
  2030. * (ProxyARP)
  2031. *
  2032. * Return: none
  2033. */
  2034. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2035. {
  2036. struct dp_soc *soc;
  2037. struct dp_pdev *pdev = tx_desc->pdev;
  2038. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2039. "%s Tx inspect path",
  2040. __func__);
  2041. qdf_assert(pdev);
  2042. soc = pdev->soc;
  2043. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2044. qdf_nbuf_len(tx_desc->nbuf));
  2045. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2046. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2047. }
  2048. #ifdef FEATURE_PERPKT_INFO
  2049. /**
  2050. * dp_get_completion_indication_for_stack() - send completion to stack
  2051. * @soc : dp_soc handle
  2052. * @pdev: dp_pdev handle
  2053. * @peer: dp peer handle
  2054. * @ts: transmit completion status structure
  2055. * @netbuf: Buffer pointer for free
  2056. *
  2057. * This function is used for indication whether buffer needs to be
  2058. * sent to stack for freeing or not
  2059. */
  2060. QDF_STATUS
  2061. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2062. struct dp_pdev *pdev,
  2063. struct dp_peer *peer,
  2064. struct hal_tx_completion_status *ts,
  2065. qdf_nbuf_t netbuf)
  2066. {
  2067. struct tx_capture_hdr *ppdu_hdr;
  2068. uint16_t peer_id = ts->peer_id;
  2069. uint32_t ppdu_id = ts->ppdu_id;
  2070. uint8_t first_msdu = ts->first_msdu;
  2071. uint8_t last_msdu = ts->last_msdu;
  2072. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  2073. return QDF_STATUS_E_NOSUPPORT;
  2074. if (!peer) {
  2075. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2076. FL("Peer Invalid"));
  2077. return QDF_STATUS_E_INVAL;
  2078. }
  2079. if (pdev->mcopy_mode) {
  2080. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2081. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2082. return QDF_STATUS_E_INVAL;
  2083. }
  2084. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2085. pdev->m_copy_id.tx_peer_id = peer_id;
  2086. }
  2087. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2088. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2089. FL("No headroom"));
  2090. return QDF_STATUS_E_NOMEM;
  2091. }
  2092. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2093. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2094. IEEE80211_ADDR_LEN);
  2095. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2096. IEEE80211_ADDR_LEN);
  2097. ppdu_hdr->ppdu_id = ppdu_id;
  2098. ppdu_hdr->peer_id = peer_id;
  2099. ppdu_hdr->first_msdu = first_msdu;
  2100. ppdu_hdr->last_msdu = last_msdu;
  2101. return QDF_STATUS_SUCCESS;
  2102. }
  2103. /**
  2104. * dp_send_completion_to_stack() - send completion to stack
  2105. * @soc : dp_soc handle
  2106. * @pdev: dp_pdev handle
  2107. * @peer_id: peer_id of the peer for which completion came
  2108. * @ppdu_id: ppdu_id
  2109. * @netbuf: Buffer pointer for free
  2110. *
  2111. * This function is used to send completion to stack
  2112. * to free buffer
  2113. */
  2114. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2115. uint16_t peer_id, uint32_t ppdu_id,
  2116. qdf_nbuf_t netbuf)
  2117. {
  2118. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2119. netbuf, peer_id,
  2120. WDI_NO_VAL, pdev->pdev_id);
  2121. }
  2122. #else
  2123. static QDF_STATUS
  2124. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2125. struct dp_pdev *pdev,
  2126. struct dp_peer *peer,
  2127. struct hal_tx_completion_status *ts,
  2128. qdf_nbuf_t netbuf)
  2129. {
  2130. return QDF_STATUS_E_NOSUPPORT;
  2131. }
  2132. static void
  2133. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2134. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2135. {
  2136. }
  2137. #endif
  2138. /**
  2139. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2140. * @soc: Soc handle
  2141. * @desc: software Tx descriptor to be processed
  2142. *
  2143. * Return: none
  2144. */
  2145. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2146. struct dp_tx_desc_s *desc)
  2147. {
  2148. struct dp_vdev *vdev = desc->vdev;
  2149. qdf_nbuf_t nbuf = desc->nbuf;
  2150. /* If it is TDLS mgmt, don't unmap or free the frame */
  2151. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2152. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2153. /* 0 : MSDU buffer, 1 : MLE */
  2154. if (desc->msdu_ext_desc) {
  2155. /* TSO free */
  2156. if (hal_tx_ext_desc_get_tso_enable(
  2157. desc->msdu_ext_desc->vaddr)) {
  2158. /* unmap eash TSO seg before free the nbuf */
  2159. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2160. desc->tso_num_desc);
  2161. qdf_nbuf_free(nbuf);
  2162. return;
  2163. }
  2164. }
  2165. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2166. if (qdf_likely(!vdev->mesh_vdev))
  2167. qdf_nbuf_free(nbuf);
  2168. else {
  2169. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2170. qdf_nbuf_free(nbuf);
  2171. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2172. } else
  2173. vdev->osif_tx_free_ext((nbuf));
  2174. }
  2175. }
  2176. /**
  2177. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2178. * @vdev: pointer to dp dev handler
  2179. * @status : Tx completion status from HTT descriptor
  2180. *
  2181. * Handles MEC notify event sent from fw to Host
  2182. *
  2183. * Return: none
  2184. */
  2185. #ifdef FEATURE_WDS
  2186. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2187. {
  2188. struct dp_soc *soc;
  2189. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2190. struct dp_peer *peer;
  2191. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2192. if (!vdev->mec_enabled)
  2193. return;
  2194. /* MEC required only in STA mode */
  2195. if (vdev->opmode != wlan_op_mode_sta)
  2196. return;
  2197. soc = vdev->pdev->soc;
  2198. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2199. peer = TAILQ_FIRST(&vdev->peer_list);
  2200. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2201. if (!peer) {
  2202. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2203. FL("peer is NULL"));
  2204. return;
  2205. }
  2206. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2207. "%s Tx MEC Handler",
  2208. __func__);
  2209. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2210. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2211. status[(DP_MAC_ADDR_LEN - 2) + i];
  2212. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2213. dp_peer_add_ast(soc,
  2214. peer,
  2215. mac_addr,
  2216. CDP_TXRX_AST_TYPE_MEC,
  2217. flags);
  2218. }
  2219. #endif
  2220. #ifdef MESH_MODE_SUPPORT
  2221. /**
  2222. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2223. * in mesh meta header
  2224. * @tx_desc: software descriptor head pointer
  2225. * @ts: pointer to tx completion stats
  2226. * Return: none
  2227. */
  2228. static
  2229. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2230. struct hal_tx_completion_status *ts)
  2231. {
  2232. struct meta_hdr_s *mhdr;
  2233. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2234. if (!tx_desc->msdu_ext_desc) {
  2235. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2236. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2237. "netbuf %pK offset %d",
  2238. netbuf, tx_desc->pkt_offset);
  2239. return;
  2240. }
  2241. }
  2242. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2243. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2244. "netbuf %pK offset %d", netbuf,
  2245. sizeof(struct meta_hdr_s));
  2246. return;
  2247. }
  2248. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2249. mhdr->rssi = ts->ack_frame_rssi;
  2250. mhdr->channel = tx_desc->pdev->operating_channel;
  2251. }
  2252. #else
  2253. static
  2254. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2255. struct hal_tx_completion_status *ts)
  2256. {
  2257. }
  2258. #endif
  2259. /**
  2260. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2261. * @peer: Handle to DP peer
  2262. * @ts: pointer to HAL Tx completion stats
  2263. *
  2264. * Return: None
  2265. */
  2266. static inline void
  2267. dp_tx_update_peer_stats(struct dp_peer *peer,
  2268. struct hal_tx_completion_status *ts, uint32_t length)
  2269. {
  2270. struct dp_pdev *pdev = peer->vdev->pdev;
  2271. struct dp_soc *soc = pdev->soc;
  2272. uint8_t mcs, pkt_type;
  2273. mcs = ts->mcs;
  2274. pkt_type = ts->pkt_type;
  2275. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2276. dp_err("Release source is not from TQM");
  2277. return;
  2278. }
  2279. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2280. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2281. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2282. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2283. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2284. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2285. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2286. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2287. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2288. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2289. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2290. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2291. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2292. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2293. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2294. return;
  2295. }
  2296. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2297. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2298. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2299. /*
  2300. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2301. * Return from here if HTT PPDU events are enabled.
  2302. */
  2303. if (!(soc->process_tx_status))
  2304. return;
  2305. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2306. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2307. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2308. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2309. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2310. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2311. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2312. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2313. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2314. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2315. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2316. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2317. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2318. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2319. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2320. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2321. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2322. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2323. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2324. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2325. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2326. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2327. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2328. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2329. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2330. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2331. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2332. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2333. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2334. &peer->stats, ts->peer_id,
  2335. UPDATE_PEER_STATS, pdev->pdev_id);
  2336. #endif
  2337. }
  2338. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2339. /**
  2340. * dp_tx_flow_pool_lock() - take flow pool lock
  2341. * @soc: core txrx main context
  2342. * @tx_desc: tx desc
  2343. *
  2344. * Return: None
  2345. */
  2346. static inline
  2347. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2348. struct dp_tx_desc_s *tx_desc)
  2349. {
  2350. struct dp_tx_desc_pool_s *pool;
  2351. uint8_t desc_pool_id;
  2352. desc_pool_id = tx_desc->pool_id;
  2353. pool = &soc->tx_desc[desc_pool_id];
  2354. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2355. }
  2356. /**
  2357. * dp_tx_flow_pool_unlock() - release flow pool lock
  2358. * @soc: core txrx main context
  2359. * @tx_desc: tx desc
  2360. *
  2361. * Return: None
  2362. */
  2363. static inline
  2364. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2365. struct dp_tx_desc_s *tx_desc)
  2366. {
  2367. struct dp_tx_desc_pool_s *pool;
  2368. uint8_t desc_pool_id;
  2369. desc_pool_id = tx_desc->pool_id;
  2370. pool = &soc->tx_desc[desc_pool_id];
  2371. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2372. }
  2373. #else
  2374. static inline
  2375. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2376. {
  2377. }
  2378. static inline
  2379. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2380. {
  2381. }
  2382. #endif
  2383. /**
  2384. * dp_tx_notify_completion() - Notify tx completion for this desc
  2385. * @soc: core txrx main context
  2386. * @tx_desc: tx desc
  2387. * @netbuf: buffer
  2388. *
  2389. * Return: none
  2390. */
  2391. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2392. struct dp_tx_desc_s *tx_desc,
  2393. qdf_nbuf_t netbuf)
  2394. {
  2395. void *osif_dev;
  2396. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2397. qdf_assert(tx_desc);
  2398. dp_tx_flow_pool_lock(soc, tx_desc);
  2399. if (!tx_desc->vdev ||
  2400. !tx_desc->vdev->osif_vdev) {
  2401. dp_tx_flow_pool_unlock(soc, tx_desc);
  2402. return;
  2403. }
  2404. osif_dev = tx_desc->vdev->osif_vdev;
  2405. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2406. dp_tx_flow_pool_unlock(soc, tx_desc);
  2407. if (tx_compl_cbk)
  2408. tx_compl_cbk(netbuf, osif_dev);
  2409. }
  2410. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2411. * @pdev: pdev handle
  2412. * @tid: tid value
  2413. * @txdesc_ts: timestamp from txdesc
  2414. * @ppdu_id: ppdu id
  2415. *
  2416. * Return: none
  2417. */
  2418. #ifdef FEATURE_PERPKT_INFO
  2419. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2420. uint8_t tid,
  2421. uint64_t txdesc_ts,
  2422. uint32_t ppdu_id)
  2423. {
  2424. uint64_t delta_ms;
  2425. struct cdp_tx_sojourn_stats *sojourn_stats;
  2426. if (pdev->enhanced_stats_en == 0)
  2427. return;
  2428. if (pdev->sojourn_stats.ppdu_seq_id == 0)
  2429. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2430. if (ppdu_id != pdev->sojourn_stats.ppdu_seq_id) {
  2431. if (!pdev->sojourn_buf)
  2432. return;
  2433. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2434. qdf_nbuf_data(pdev->sojourn_buf);
  2435. qdf_mem_copy(sojourn_stats, &pdev->sojourn_stats,
  2436. sizeof(struct cdp_tx_sojourn_stats));
  2437. qdf_mem_zero(&pdev->sojourn_stats,
  2438. sizeof(struct cdp_tx_sojourn_stats));
  2439. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2440. pdev->sojourn_buf, HTT_INVALID_PEER,
  2441. WDI_NO_VAL, pdev->pdev_id);
  2442. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2443. }
  2444. if (tid == HTT_INVALID_TID)
  2445. return;
  2446. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2447. txdesc_ts;
  2448. qdf_ewma_tx_lag_add(&pdev->sojourn_stats.avg_sojourn_msdu[tid],
  2449. delta_ms);
  2450. pdev->sojourn_stats.sum_sojourn_msdu[tid] += delta_ms;
  2451. pdev->sojourn_stats.num_msdus[tid]++;
  2452. }
  2453. #else
  2454. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2455. uint8_t tid,
  2456. uint64_t txdesc_ts,
  2457. uint32_t ppdu_id)
  2458. {
  2459. }
  2460. #endif
  2461. /**
  2462. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2463. * @soc: DP Soc handle
  2464. * @tx_desc: software Tx descriptor
  2465. * @ts : Tx completion status from HAL/HTT descriptor
  2466. *
  2467. * Return: none
  2468. */
  2469. static inline void
  2470. dp_tx_comp_process_desc(struct dp_soc *soc,
  2471. struct dp_tx_desc_s *desc,
  2472. struct hal_tx_completion_status *ts,
  2473. struct dp_peer *peer)
  2474. {
  2475. /*
  2476. * m_copy/tx_capture modes are not supported for
  2477. * scatter gather packets
  2478. */
  2479. if (!(desc->msdu_ext_desc) &&
  2480. (dp_get_completion_indication_for_stack(soc, desc->pdev,
  2481. peer, ts, desc->nbuf)
  2482. == QDF_STATUS_SUCCESS)) {
  2483. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2484. QDF_DMA_TO_DEVICE);
  2485. dp_send_completion_to_stack(soc, desc->pdev, ts->peer_id,
  2486. ts->ppdu_id, desc->nbuf);
  2487. } else {
  2488. dp_tx_comp_free_buf(soc, desc);
  2489. }
  2490. }
  2491. /**
  2492. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2493. * @tx_desc: software descriptor head pointer
  2494. * @ts: Tx completion status
  2495. * @peer: peer handle
  2496. *
  2497. * Return: none
  2498. */
  2499. static inline
  2500. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2501. struct hal_tx_completion_status *ts,
  2502. struct dp_peer *peer)
  2503. {
  2504. uint32_t length;
  2505. struct dp_soc *soc = NULL;
  2506. struct dp_vdev *vdev = tx_desc->vdev;
  2507. struct ether_header *eh =
  2508. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2509. if (!vdev) {
  2510. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2511. "invalid vdev");
  2512. goto out;
  2513. }
  2514. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2515. "-------------------- \n"
  2516. "Tx Completion Stats: \n"
  2517. "-------------------- \n"
  2518. "ack_frame_rssi = %d \n"
  2519. "first_msdu = %d \n"
  2520. "last_msdu = %d \n"
  2521. "msdu_part_of_amsdu = %d \n"
  2522. "rate_stats valid = %d \n"
  2523. "bw = %d \n"
  2524. "pkt_type = %d \n"
  2525. "stbc = %d \n"
  2526. "ldpc = %d \n"
  2527. "sgi = %d \n"
  2528. "mcs = %d \n"
  2529. "ofdma = %d \n"
  2530. "tones_in_ru = %d \n"
  2531. "tsf = %d \n"
  2532. "ppdu_id = %d \n"
  2533. "transmit_cnt = %d \n"
  2534. "tid = %d \n"
  2535. "peer_id = %d\n",
  2536. ts->ack_frame_rssi, ts->first_msdu,
  2537. ts->last_msdu, ts->msdu_part_of_amsdu,
  2538. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2539. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2540. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2541. ts->transmit_cnt, ts->tid, ts->peer_id);
  2542. soc = vdev->pdev->soc;
  2543. /* Update SoC level stats */
  2544. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2545. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2546. /* Update per-packet stats for mesh mode */
  2547. if (qdf_unlikely(vdev->mesh_vdev) &&
  2548. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2549. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2550. length = qdf_nbuf_len(tx_desc->nbuf);
  2551. /* Update peer level stats */
  2552. if (!peer) {
  2553. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2554. "peer is null or deletion in progress");
  2555. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2556. goto out;
  2557. }
  2558. if (qdf_likely(!peer->bss_peer)) {
  2559. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2560. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2561. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2562. } else {
  2563. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2564. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2565. if ((peer->vdev->tx_encap_type ==
  2566. htt_cmn_pkt_type_ethernet) &&
  2567. IEEE80211_IS_BROADCAST(eh->ether_dhost)) {
  2568. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2569. }
  2570. }
  2571. }
  2572. dp_tx_update_peer_stats(peer, ts, length);
  2573. out:
  2574. return;
  2575. }
  2576. /**
  2577. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2578. * @soc: core txrx main context
  2579. * @comp_head: software descriptor head pointer
  2580. *
  2581. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2582. * and release the software descriptors after processing is complete
  2583. *
  2584. * Return: none
  2585. */
  2586. static void
  2587. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2588. struct dp_tx_desc_s *comp_head)
  2589. {
  2590. struct dp_tx_desc_s *desc;
  2591. struct dp_tx_desc_s *next;
  2592. struct hal_tx_completion_status ts = {0};
  2593. struct dp_peer *peer;
  2594. DP_HIST_INIT();
  2595. desc = comp_head;
  2596. while (desc) {
  2597. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2598. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2599. dp_tx_comp_process_tx_status(desc, &ts, peer);
  2600. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2601. if (peer)
  2602. dp_peer_unref_del_find_by_id(peer);
  2603. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2604. next = desc->next;
  2605. dp_tx_desc_release(desc, desc->pool_id);
  2606. desc = next;
  2607. }
  2608. DP_TX_HIST_STATS_PER_PDEV();
  2609. }
  2610. /**
  2611. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2612. * @tx_desc: software descriptor head pointer
  2613. * @status : Tx completion status from HTT descriptor
  2614. *
  2615. * This function will process HTT Tx indication messages from Target
  2616. *
  2617. * Return: none
  2618. */
  2619. static
  2620. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2621. {
  2622. uint8_t tx_status;
  2623. struct dp_pdev *pdev;
  2624. struct dp_vdev *vdev;
  2625. struct dp_soc *soc;
  2626. struct hal_tx_completion_status ts = {0};
  2627. uint32_t *htt_desc = (uint32_t *)status;
  2628. struct dp_peer *peer;
  2629. qdf_assert(tx_desc->pdev);
  2630. pdev = tx_desc->pdev;
  2631. vdev = tx_desc->vdev;
  2632. soc = pdev->soc;
  2633. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2634. switch (tx_status) {
  2635. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2636. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2637. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2638. {
  2639. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2640. ts.peer_id =
  2641. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2642. htt_desc[2]);
  2643. ts.tid =
  2644. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2645. htt_desc[2]);
  2646. } else {
  2647. ts.peer_id = HTT_INVALID_PEER;
  2648. ts.tid = HTT_INVALID_TID;
  2649. }
  2650. ts.ppdu_id =
  2651. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2652. htt_desc[1]);
  2653. ts.ack_frame_rssi =
  2654. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2655. htt_desc[1]);
  2656. ts.first_msdu = 1;
  2657. ts.last_msdu = 1;
  2658. if (tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)
  2659. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2660. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2661. if (qdf_likely(peer))
  2662. dp_peer_unref_del_find_by_id(peer);
  2663. dp_tx_comp_process_tx_status(tx_desc, &ts, peer);
  2664. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2665. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2666. break;
  2667. }
  2668. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2669. {
  2670. dp_tx_reinject_handler(tx_desc, status);
  2671. break;
  2672. }
  2673. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2674. {
  2675. dp_tx_inspect_handler(tx_desc, status);
  2676. break;
  2677. }
  2678. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2679. {
  2680. dp_tx_mec_handler(vdev, status);
  2681. break;
  2682. }
  2683. default:
  2684. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2685. "%s Invalid HTT tx_status %d\n",
  2686. __func__, tx_status);
  2687. break;
  2688. }
  2689. }
  2690. /**
  2691. * dp_tx_comp_handler() - Tx completion handler
  2692. * @soc: core txrx main context
  2693. * @ring_id: completion ring id
  2694. * @quota: No. of packets/descriptors that can be serviced in one loop
  2695. *
  2696. * This function will collect hardware release ring element contents and
  2697. * handle descriptor contents. Based on contents, free packet or handle error
  2698. * conditions
  2699. *
  2700. * Return: none
  2701. */
  2702. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2703. {
  2704. void *tx_comp_hal_desc;
  2705. uint8_t buffer_src;
  2706. uint8_t pool_id;
  2707. uint32_t tx_desc_id;
  2708. struct dp_tx_desc_s *tx_desc = NULL;
  2709. struct dp_tx_desc_s *head_desc = NULL;
  2710. struct dp_tx_desc_s *tail_desc = NULL;
  2711. uint32_t num_processed;
  2712. uint32_t count;
  2713. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2714. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2715. "%s %d : HAL RING Access Failed -- %pK",
  2716. __func__, __LINE__, hal_srng);
  2717. return 0;
  2718. }
  2719. num_processed = 0;
  2720. count = 0;
  2721. /* Find head descriptor from completion ring */
  2722. while (qdf_likely(tx_comp_hal_desc =
  2723. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2724. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2725. /* If this buffer was not released by TQM or FW, then it is not
  2726. * Tx completion indication, assert */
  2727. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2728. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2729. QDF_TRACE(QDF_MODULE_ID_DP,
  2730. QDF_TRACE_LEVEL_FATAL,
  2731. "Tx comp release_src != TQM | FW");
  2732. qdf_assert_always(0);
  2733. }
  2734. /* Get descriptor id */
  2735. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2736. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2737. DP_TX_DESC_ID_POOL_OS;
  2738. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2739. continue;
  2740. /* Find Tx descriptor */
  2741. tx_desc = dp_tx_desc_find(soc, pool_id,
  2742. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2743. DP_TX_DESC_ID_PAGE_OS,
  2744. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2745. DP_TX_DESC_ID_OFFSET_OS);
  2746. /*
  2747. * If the descriptor is already freed in vdev_detach,
  2748. * continue to next descriptor
  2749. */
  2750. if (!tx_desc->vdev) {
  2751. QDF_TRACE(QDF_MODULE_ID_DP,
  2752. QDF_TRACE_LEVEL_INFO,
  2753. "Descriptor freed in vdev_detach %d",
  2754. tx_desc_id);
  2755. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2756. count++;
  2757. continue;
  2758. }
  2759. /*
  2760. * If the release source is FW, process the HTT status
  2761. */
  2762. if (qdf_unlikely(buffer_src ==
  2763. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2764. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2765. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2766. htt_tx_status);
  2767. dp_tx_process_htt_completion(tx_desc,
  2768. htt_tx_status);
  2769. } else {
  2770. /* Pool id is not matching. Error */
  2771. if (tx_desc->pool_id != pool_id) {
  2772. QDF_TRACE(QDF_MODULE_ID_DP,
  2773. QDF_TRACE_LEVEL_FATAL,
  2774. "Tx Comp pool id %d not matched %d",
  2775. pool_id, tx_desc->pool_id);
  2776. qdf_assert_always(0);
  2777. }
  2778. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2779. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2780. QDF_TRACE(QDF_MODULE_ID_DP,
  2781. QDF_TRACE_LEVEL_FATAL,
  2782. "Txdesc invalid, flgs = %x,id = %d",
  2783. tx_desc->flags, tx_desc_id);
  2784. qdf_assert_always(0);
  2785. }
  2786. /* First ring descriptor on the cycle */
  2787. if (!head_desc) {
  2788. head_desc = tx_desc;
  2789. tail_desc = tx_desc;
  2790. }
  2791. tail_desc->next = tx_desc;
  2792. tx_desc->next = NULL;
  2793. tail_desc = tx_desc;
  2794. /* Collect hw completion contents */
  2795. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2796. &tx_desc->comp, 1);
  2797. }
  2798. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2799. /*
  2800. * Processed packet count is more than given quota
  2801. * stop to processing
  2802. */
  2803. if ((num_processed >= quota))
  2804. break;
  2805. count++;
  2806. }
  2807. hal_srng_access_end(soc->hal_soc, hal_srng);
  2808. /* Process the reaped descriptors */
  2809. if (head_desc)
  2810. dp_tx_comp_process_desc_list(soc, head_desc);
  2811. return num_processed;
  2812. }
  2813. #ifdef CONVERGED_TDLS_ENABLE
  2814. /**
  2815. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2816. *
  2817. * @data_vdev - which vdev should transmit the tx data frames
  2818. * @tx_spec - what non-standard handling to apply to the tx data frames
  2819. * @msdu_list - NULL-terminated list of tx MSDUs
  2820. *
  2821. * Return: NULL on success,
  2822. * nbuf when it fails to send
  2823. */
  2824. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2825. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2826. {
  2827. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2828. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2829. vdev->is_tdls_frame = true;
  2830. return dp_tx_send(vdev_handle, msdu_list);
  2831. }
  2832. #endif
  2833. /**
  2834. * dp_tx_vdev_attach() - attach vdev to dp tx
  2835. * @vdev: virtual device instance
  2836. *
  2837. * Return: QDF_STATUS_SUCCESS: success
  2838. * QDF_STATUS_E_RESOURCES: Error return
  2839. */
  2840. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2841. {
  2842. /*
  2843. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2844. */
  2845. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2846. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2847. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2848. vdev->vdev_id);
  2849. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2850. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2851. /*
  2852. * Set HTT Extension Valid bit to 0 by default
  2853. */
  2854. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2855. dp_tx_vdev_update_search_flags(vdev);
  2856. return QDF_STATUS_SUCCESS;
  2857. }
  2858. #ifdef FEATURE_WDS
  2859. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  2860. {
  2861. struct dp_soc *soc = vdev->pdev->soc;
  2862. /*
  2863. * If AST index override support is available (HKv2 etc),
  2864. * DA search flag be enabled always
  2865. *
  2866. * If AST index override support is not available (HKv1),
  2867. * DA search flag should be used for all modes except QWRAP
  2868. */
  2869. if (soc->ast_override_support || !vdev->proxysta_vdev)
  2870. return true;
  2871. return false;
  2872. }
  2873. #else
  2874. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  2875. {
  2876. return false;
  2877. }
  2878. #endif
  2879. /**
  2880. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2881. * @vdev: virtual device instance
  2882. *
  2883. * Return: void
  2884. *
  2885. */
  2886. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2887. {
  2888. struct dp_soc *soc = vdev->pdev->soc;
  2889. /*
  2890. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2891. * for TDLS link
  2892. *
  2893. * Enable AddrY (SA based search) only for non-WDS STA and
  2894. * ProxySTA VAP (in HKv1) modes.
  2895. *
  2896. * In all other VAP modes, only DA based search should be
  2897. * enabled
  2898. */
  2899. if (vdev->opmode == wlan_op_mode_sta &&
  2900. vdev->tdls_link_connected)
  2901. vdev->hal_desc_addr_search_flags =
  2902. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2903. else if ((vdev->opmode == wlan_op_mode_sta) &&
  2904. !dp_tx_da_search_override(vdev))
  2905. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2906. else
  2907. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2908. /* Set search type only when peer map v2 messaging is enabled
  2909. * as we will have the search index (AST hash) only when v2 is
  2910. * enabled
  2911. */
  2912. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  2913. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  2914. else
  2915. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  2916. }
  2917. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2918. /* dp_tx_desc_flush() - release resources associated
  2919. * to tx_desc
  2920. * @vdev: virtual device instance
  2921. *
  2922. * This function will free all outstanding Tx buffers,
  2923. * including ME buffer for which either free during
  2924. * completion didn't happened or completion is not
  2925. * received.
  2926. */
  2927. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2928. {
  2929. uint8_t i;
  2930. uint32_t j;
  2931. uint32_t num_desc, page_id, offset;
  2932. uint16_t num_desc_per_page;
  2933. struct dp_soc *soc = vdev->pdev->soc;
  2934. struct dp_tx_desc_s *tx_desc = NULL;
  2935. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2936. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  2937. tx_desc_pool = &soc->tx_desc[i];
  2938. if (!(tx_desc_pool->pool_size) ||
  2939. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  2940. !(tx_desc_pool->desc_pages.cacheable_pages))
  2941. continue;
  2942. num_desc = tx_desc_pool->pool_size;
  2943. num_desc_per_page =
  2944. tx_desc_pool->desc_pages.num_element_per_page;
  2945. for (j = 0; j < num_desc; j++) {
  2946. page_id = j / num_desc_per_page;
  2947. offset = j % num_desc_per_page;
  2948. if (qdf_unlikely(!(tx_desc_pool->
  2949. desc_pages.cacheable_pages)))
  2950. break;
  2951. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  2952. if (tx_desc && (tx_desc->vdev == vdev) &&
  2953. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2954. dp_tx_comp_free_buf(soc, tx_desc);
  2955. dp_tx_desc_release(tx_desc, i);
  2956. }
  2957. }
  2958. }
  2959. }
  2960. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2961. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2962. {
  2963. uint8_t i, num_pool;
  2964. uint32_t j;
  2965. uint32_t num_desc, page_id, offset;
  2966. uint16_t num_desc_per_page;
  2967. struct dp_soc *soc = vdev->pdev->soc;
  2968. struct dp_tx_desc_s *tx_desc = NULL;
  2969. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2970. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2971. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2972. for (i = 0; i < num_pool; i++) {
  2973. tx_desc_pool = &soc->tx_desc[i];
  2974. if (!tx_desc_pool->desc_pages.cacheable_pages)
  2975. continue;
  2976. num_desc_per_page =
  2977. tx_desc_pool->desc_pages.num_element_per_page;
  2978. for (j = 0; j < num_desc; j++) {
  2979. page_id = j / num_desc_per_page;
  2980. offset = j % num_desc_per_page;
  2981. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  2982. if (tx_desc && (tx_desc->vdev == vdev) &&
  2983. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2984. dp_tx_comp_free_buf(soc, tx_desc);
  2985. dp_tx_desc_release(tx_desc, i);
  2986. }
  2987. }
  2988. }
  2989. }
  2990. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2991. /**
  2992. * dp_tx_vdev_detach() - detach vdev from dp tx
  2993. * @vdev: virtual device instance
  2994. *
  2995. * Return: QDF_STATUS_SUCCESS: success
  2996. * QDF_STATUS_E_RESOURCES: Error return
  2997. */
  2998. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2999. {
  3000. dp_tx_desc_flush(vdev);
  3001. return QDF_STATUS_SUCCESS;
  3002. }
  3003. /**
  3004. * dp_tx_pdev_attach() - attach pdev to dp tx
  3005. * @pdev: physical device instance
  3006. *
  3007. * Return: QDF_STATUS_SUCCESS: success
  3008. * QDF_STATUS_E_RESOURCES: Error return
  3009. */
  3010. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3011. {
  3012. struct dp_soc *soc = pdev->soc;
  3013. /* Initialize Flow control counters */
  3014. qdf_atomic_init(&pdev->num_tx_exception);
  3015. qdf_atomic_init(&pdev->num_tx_outstanding);
  3016. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3017. /* Initialize descriptors in TCL Ring */
  3018. hal_tx_init_data_ring(soc->hal_soc,
  3019. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3020. }
  3021. return QDF_STATUS_SUCCESS;
  3022. }
  3023. /**
  3024. * dp_tx_pdev_detach() - detach pdev from dp tx
  3025. * @pdev: physical device instance
  3026. *
  3027. * Return: QDF_STATUS_SUCCESS: success
  3028. * QDF_STATUS_E_RESOURCES: Error return
  3029. */
  3030. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3031. {
  3032. dp_tx_me_exit(pdev);
  3033. return QDF_STATUS_SUCCESS;
  3034. }
  3035. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3036. /* Pools will be allocated dynamically */
  3037. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3038. int num_desc)
  3039. {
  3040. uint8_t i;
  3041. for (i = 0; i < num_pool; i++) {
  3042. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3043. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3044. }
  3045. return 0;
  3046. }
  3047. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3048. {
  3049. uint8_t i;
  3050. for (i = 0; i < num_pool; i++)
  3051. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3052. }
  3053. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3054. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3055. int num_desc)
  3056. {
  3057. uint8_t i;
  3058. /* Allocate software Tx descriptor pools */
  3059. for (i = 0; i < num_pool; i++) {
  3060. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3061. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3062. "%s Tx Desc Pool alloc %d failed %pK",
  3063. __func__, i, soc);
  3064. return ENOMEM;
  3065. }
  3066. }
  3067. return 0;
  3068. }
  3069. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3070. {
  3071. uint8_t i;
  3072. for (i = 0; i < num_pool; i++) {
  3073. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3074. if (dp_tx_desc_pool_free(soc, i)) {
  3075. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3076. "%s Tx Desc Pool Free failed", __func__);
  3077. }
  3078. }
  3079. }
  3080. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3081. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3082. /**
  3083. * dp_tso_attach_wifi3() - TSO attach handler
  3084. * @txrx_soc: Opaque Dp handle
  3085. *
  3086. * Reserve TSO descriptor buffers
  3087. *
  3088. * Return: QDF_STATUS_E_FAILURE on failure or
  3089. * QDF_STATUS_SUCCESS on success
  3090. */
  3091. static
  3092. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3093. {
  3094. return dp_tso_soc_attach(txrx_soc);
  3095. }
  3096. /**
  3097. * dp_tso_detach_wifi3() - TSO Detach handler
  3098. * @txrx_soc: Opaque Dp handle
  3099. *
  3100. * Deallocate TSO descriptor buffers
  3101. *
  3102. * Return: QDF_STATUS_E_FAILURE on failure or
  3103. * QDF_STATUS_SUCCESS on success
  3104. */
  3105. static
  3106. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3107. {
  3108. return dp_tso_soc_detach(txrx_soc);
  3109. }
  3110. #else
  3111. static
  3112. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3113. {
  3114. return QDF_STATUS_SUCCESS;
  3115. }
  3116. static
  3117. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3118. {
  3119. return QDF_STATUS_SUCCESS;
  3120. }
  3121. #endif
  3122. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3123. {
  3124. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3125. uint8_t i;
  3126. uint8_t num_pool;
  3127. uint32_t num_desc;
  3128. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3129. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3130. for (i = 0; i < num_pool; i++)
  3131. dp_tx_tso_desc_pool_free(soc, i);
  3132. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3133. __func__, num_pool, num_desc);
  3134. for (i = 0; i < num_pool; i++)
  3135. dp_tx_tso_num_seg_pool_free(soc, i);
  3136. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3137. __func__, num_pool, num_desc);
  3138. return QDF_STATUS_SUCCESS;
  3139. }
  3140. /**
  3141. * dp_tso_attach() - TSO attach handler
  3142. * @txrx_soc: Opaque Dp handle
  3143. *
  3144. * Reserve TSO descriptor buffers
  3145. *
  3146. * Return: QDF_STATUS_E_FAILURE on failure or
  3147. * QDF_STATUS_SUCCESS on success
  3148. */
  3149. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3150. {
  3151. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3152. uint8_t i;
  3153. uint8_t num_pool;
  3154. uint32_t num_desc;
  3155. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3156. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3157. for (i = 0; i < num_pool; i++) {
  3158. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3159. dp_err("TSO Desc Pool alloc %d failed %pK",
  3160. i, soc);
  3161. return QDF_STATUS_E_FAILURE;
  3162. }
  3163. }
  3164. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3165. __func__, num_pool, num_desc);
  3166. for (i = 0; i < num_pool; i++) {
  3167. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3168. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3169. i, soc);
  3170. return QDF_STATUS_E_FAILURE;
  3171. }
  3172. }
  3173. return QDF_STATUS_SUCCESS;
  3174. }
  3175. /**
  3176. * dp_tx_soc_detach() - detach soc from dp tx
  3177. * @soc: core txrx main context
  3178. *
  3179. * This function will detach dp tx into main device context
  3180. * will free dp tx resource and initialize resources
  3181. *
  3182. * Return: QDF_STATUS_SUCCESS: success
  3183. * QDF_STATUS_E_RESOURCES: Error return
  3184. */
  3185. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3186. {
  3187. uint8_t num_pool;
  3188. uint16_t num_desc;
  3189. uint16_t num_ext_desc;
  3190. uint8_t i;
  3191. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3192. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3193. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3194. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3195. dp_tx_flow_control_deinit(soc);
  3196. dp_tx_delete_static_pools(soc, num_pool);
  3197. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3198. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3199. __func__, num_pool, num_desc);
  3200. for (i = 0; i < num_pool; i++) {
  3201. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3202. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3203. "%s Tx Ext Desc Pool Free failed",
  3204. __func__);
  3205. return QDF_STATUS_E_RESOURCES;
  3206. }
  3207. }
  3208. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3209. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3210. __func__, num_pool, num_ext_desc);
  3211. status = dp_tso_detach_wifi3(soc);
  3212. if (status != QDF_STATUS_SUCCESS)
  3213. return status;
  3214. return QDF_STATUS_SUCCESS;
  3215. }
  3216. /**
  3217. * dp_tx_soc_attach() - attach soc to dp tx
  3218. * @soc: core txrx main context
  3219. *
  3220. * This function will attach dp tx into main device context
  3221. * will allocate dp tx resource and initialize resources
  3222. *
  3223. * Return: QDF_STATUS_SUCCESS: success
  3224. * QDF_STATUS_E_RESOURCES: Error return
  3225. */
  3226. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3227. {
  3228. uint8_t i;
  3229. uint8_t num_pool;
  3230. uint32_t num_desc;
  3231. uint32_t num_ext_desc;
  3232. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3233. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3234. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3235. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3236. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3237. goto fail;
  3238. dp_tx_flow_control_init(soc);
  3239. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3240. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3241. __func__, num_pool, num_desc);
  3242. /* Allocate extension tx descriptor pools */
  3243. for (i = 0; i < num_pool; i++) {
  3244. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3245. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3246. "MSDU Ext Desc Pool alloc %d failed %pK",
  3247. i, soc);
  3248. goto fail;
  3249. }
  3250. }
  3251. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3252. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3253. __func__, num_pool, num_ext_desc);
  3254. status = dp_tso_attach_wifi3((void *)soc);
  3255. if (status != QDF_STATUS_SUCCESS)
  3256. goto fail;
  3257. /* Initialize descriptors in TCL Rings */
  3258. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3259. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3260. hal_tx_init_data_ring(soc->hal_soc,
  3261. soc->tcl_data_ring[i].hal_srng);
  3262. }
  3263. }
  3264. /*
  3265. * todo - Add a runtime config option to enable this.
  3266. */
  3267. /*
  3268. * Due to multiple issues on NPR EMU, enable it selectively
  3269. * only for NPR EMU, should be removed, once NPR platforms
  3270. * are stable.
  3271. */
  3272. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3273. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3274. "%s HAL Tx init Success", __func__);
  3275. return QDF_STATUS_SUCCESS;
  3276. fail:
  3277. /* Detach will take care of freeing only allocated resources */
  3278. dp_tx_soc_detach(soc);
  3279. return QDF_STATUS_E_RESOURCES;
  3280. }
  3281. /*
  3282. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3283. * pdev: pointer to DP PDEV structure
  3284. * seg_info_head: Pointer to the head of list
  3285. *
  3286. * return: void
  3287. */
  3288. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3289. struct dp_tx_seg_info_s *seg_info_head)
  3290. {
  3291. struct dp_tx_me_buf_t *mc_uc_buf;
  3292. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3293. qdf_nbuf_t nbuf = NULL;
  3294. uint64_t phy_addr;
  3295. while (seg_info_head) {
  3296. nbuf = seg_info_head->nbuf;
  3297. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3298. seg_info_head->frags[0].vaddr;
  3299. phy_addr = seg_info_head->frags[0].paddr_hi;
  3300. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3301. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3302. phy_addr,
  3303. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  3304. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3305. qdf_nbuf_free(nbuf);
  3306. seg_info_new = seg_info_head;
  3307. seg_info_head = seg_info_head->next;
  3308. qdf_mem_free(seg_info_new);
  3309. }
  3310. }
  3311. /**
  3312. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3313. * @vdev: DP VDEV handle
  3314. * @nbuf: Multicast nbuf
  3315. * @newmac: Table of the clients to which packets have to be sent
  3316. * @new_mac_cnt: No of clients
  3317. *
  3318. * return: no of converted packets
  3319. */
  3320. uint16_t
  3321. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3322. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  3323. {
  3324. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3325. struct dp_pdev *pdev = vdev->pdev;
  3326. struct ether_header *eh;
  3327. uint8_t *data;
  3328. uint16_t len;
  3329. /* reference to frame dst addr */
  3330. uint8_t *dstmac;
  3331. /* copy of original frame src addr */
  3332. uint8_t srcmac[DP_MAC_ADDR_LEN];
  3333. /* local index into newmac */
  3334. uint8_t new_mac_idx = 0;
  3335. struct dp_tx_me_buf_t *mc_uc_buf;
  3336. qdf_nbuf_t nbuf_clone;
  3337. struct dp_tx_msdu_info_s msdu_info;
  3338. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3339. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3340. struct dp_tx_seg_info_s *seg_info_new;
  3341. struct dp_tx_frag_info_s data_frag;
  3342. qdf_dma_addr_t paddr_data;
  3343. qdf_dma_addr_t paddr_mcbuf = 0;
  3344. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  3345. QDF_STATUS status;
  3346. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  3347. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3348. eh = (struct ether_header *) nbuf;
  3349. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  3350. len = qdf_nbuf_len(nbuf);
  3351. data = qdf_nbuf_data(nbuf);
  3352. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3353. QDF_DMA_TO_DEVICE);
  3354. if (status) {
  3355. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3356. "Mapping failure Error:%d", status);
  3357. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3358. qdf_nbuf_free(nbuf);
  3359. return 1;
  3360. }
  3361. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  3362. /*preparing data fragment*/
  3363. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  3364. data_frag.paddr_lo = (uint32_t)paddr_data;
  3365. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  3366. data_frag.len = len - DP_MAC_ADDR_LEN;
  3367. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3368. dstmac = newmac[new_mac_idx];
  3369. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3370. "added mac addr (%pM)", dstmac);
  3371. /* Check for NULL Mac Address */
  3372. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  3373. continue;
  3374. /* frame to self mac. skip */
  3375. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  3376. continue;
  3377. /*
  3378. * TODO: optimize to avoid malloc in per-packet path
  3379. * For eg. seg_pool can be made part of vdev structure
  3380. */
  3381. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3382. if (!seg_info_new) {
  3383. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3384. "alloc failed");
  3385. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3386. goto fail_seg_alloc;
  3387. }
  3388. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3389. if (mc_uc_buf == NULL)
  3390. goto fail_buf_alloc;
  3391. /*
  3392. * TODO: Check if we need to clone the nbuf
  3393. * Or can we just use the reference for all cases
  3394. */
  3395. if (new_mac_idx < (new_mac_cnt - 1)) {
  3396. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3397. if (nbuf_clone == NULL) {
  3398. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3399. goto fail_clone;
  3400. }
  3401. } else {
  3402. /*
  3403. * Update the ref
  3404. * to account for frame sent without cloning
  3405. */
  3406. qdf_nbuf_ref(nbuf);
  3407. nbuf_clone = nbuf;
  3408. }
  3409. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  3410. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3411. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  3412. &paddr_mcbuf);
  3413. if (status) {
  3414. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3415. "Mapping failure Error:%d", status);
  3416. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3417. goto fail_map;
  3418. }
  3419. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3420. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3421. seg_info_new->frags[0].paddr_hi =
  3422. ((uint64_t) paddr_mcbuf >> 32);
  3423. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  3424. seg_info_new->frags[1] = data_frag;
  3425. seg_info_new->nbuf = nbuf_clone;
  3426. seg_info_new->frag_cnt = 2;
  3427. seg_info_new->total_len = len;
  3428. seg_info_new->next = NULL;
  3429. if (seg_info_head == NULL)
  3430. seg_info_head = seg_info_new;
  3431. else
  3432. seg_info_tail->next = seg_info_new;
  3433. seg_info_tail = seg_info_new;
  3434. }
  3435. if (!seg_info_head) {
  3436. goto free_return;
  3437. }
  3438. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3439. msdu_info.num_seg = new_mac_cnt;
  3440. msdu_info.frm_type = dp_tx_frm_me;
  3441. if (qdf_unlikely(vdev->mcast_enhancement_en > 0) &&
  3442. qdf_unlikely(pdev->hmmc_tid_override_en))
  3443. msdu_info.tid = pdev->hmmc_tid;
  3444. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3445. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3446. while (seg_info_head->next) {
  3447. seg_info_new = seg_info_head;
  3448. seg_info_head = seg_info_head->next;
  3449. qdf_mem_free(seg_info_new);
  3450. }
  3451. qdf_mem_free(seg_info_head);
  3452. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3453. qdf_nbuf_free(nbuf);
  3454. return new_mac_cnt;
  3455. fail_map:
  3456. qdf_nbuf_free(nbuf_clone);
  3457. fail_clone:
  3458. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3459. fail_buf_alloc:
  3460. qdf_mem_free(seg_info_new);
  3461. fail_seg_alloc:
  3462. dp_tx_me_mem_free(pdev, seg_info_head);
  3463. free_return:
  3464. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3465. qdf_nbuf_free(nbuf);
  3466. return 1;
  3467. }