hal_8074v1.c 60 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "hal_li_hw_headers.h"
  20. #include "hal_internal.h"
  21. #include "hal_api.h"
  22. #include "target_type.h"
  23. #include "wcss_version.h"
  24. #include "qdf_module.h"
  25. #include "hal_flow.h"
  26. #include "rx_flow_search_entry.h"
  27. #include "hal_rx_flow_info.h"
  28. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
  29. RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET
  30. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
  31. RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK
  32. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
  33. RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB
  34. #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \
  35. RXPCU_PPDU_END_INFO_10_PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_OFFSET
  36. #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \
  37. RXPCU_PPDU_END_INFO_10_PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MASK
  38. #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \
  39. RXPCU_PPDU_END_INFO_10_PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_LSB
  40. #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
  41. PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET
  42. #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
  43. PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET
  44. #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
  45. PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET
  46. #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
  47. PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET
  48. #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
  49. PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET
  50. #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
  51. PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET
  52. #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
  53. PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET
  54. #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
  55. PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET
  56. #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
  57. PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET
  58. #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
  59. PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET
  60. #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
  61. PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET
  62. #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
  63. RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET
  64. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  65. RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
  66. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  67. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
  68. #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  69. RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
  70. #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  71. REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
  72. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
  73. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER
  74. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSE \
  75. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
  76. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  77. RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
  78. #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  79. TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
  80. #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  81. TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
  82. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
  83. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
  84. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
  85. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
  86. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
  87. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
  88. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
  89. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
  90. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
  91. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
  92. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
  93. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
  94. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
  95. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
  96. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
  97. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
  98. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
  99. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
  100. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
  101. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
  102. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
  103. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
  104. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
  105. WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK
  106. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
  107. WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET
  108. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
  109. WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB
  110. #include "hal_8074v1_tx.h"
  111. #include "hal_8074v1_rx.h"
  112. #include <hal_generic_api.h>
  113. #include "hal_li_rx.h"
  114. #include "hal_li_tx.h"
  115. #include "hal_li_api.h"
  116. #include "hal_li_generic_api.h"
  117. /**
  118. * hal_get_window_address_8074(): Function to get hp/tp address
  119. * @hal_soc: Pointer to hal_soc
  120. * @addr: address offset of register
  121. *
  122. * Return: modified address offset of register
  123. */
  124. static inline qdf_iomem_t hal_get_window_address_8074(struct hal_soc *hal_soc,
  125. qdf_iomem_t addr)
  126. {
  127. return addr;
  128. }
  129. /**
  130. * hal_rx_get_rx_fragment_number_8074v1(): Function to retrieve
  131. * rx fragment number
  132. *
  133. * @nbuf: Network buffer
  134. * Returns: rx fragment number
  135. */
  136. static
  137. uint8_t hal_rx_get_rx_fragment_number_8074v1(uint8_t *buf)
  138. {
  139. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  140. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  141. /* Return first 4 bits as fragment number */
  142. return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
  143. DOT11_SEQ_FRAG_MASK);
  144. }
  145. /**
  146. * hal_rx_msdu_end_da_is_mcbc_get_8074v1(): API to check if
  147. * pkt is MCBC from rx_msdu_end TLV
  148. *
  149. * @ buf: pointer to the start of RX PKT TLV headers
  150. * Return: da_is_mcbc
  151. */
  152. static uint8_t
  153. hal_rx_msdu_end_da_is_mcbc_get_8074v1(uint8_t *buf)
  154. {
  155. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  156. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  157. return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
  158. }
  159. /**
  160. * hal_rx_msdu_end_sa_is_valid_get_8074v1(): API to get_8074v1 the
  161. * sa_is_valid bit from rx_msdu_end TLV
  162. *
  163. * @ buf: pointer to the start of RX PKT TLV headers
  164. * Return: sa_is_valid bit
  165. */
  166. static uint8_t
  167. hal_rx_msdu_end_sa_is_valid_get_8074v1(uint8_t *buf)
  168. {
  169. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  170. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  171. uint8_t sa_is_valid;
  172. sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
  173. return sa_is_valid;
  174. }
  175. /**
  176. * hal_rx_msdu_end_sa_idx_get_8074v1(): API to get_8074v1 the
  177. * sa_idx from rx_msdu_end TLV
  178. *
  179. * @ buf: pointer to the start of RX PKT TLV headers
  180. * Return: sa_idx (SA AST index)
  181. */
  182. static uint16_t hal_rx_msdu_end_sa_idx_get_8074v1(uint8_t *buf)
  183. {
  184. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  185. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  186. uint16_t sa_idx;
  187. sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
  188. return sa_idx;
  189. }
  190. /**
  191. * hal_rx_desc_is_first_msdu_8074v1() - Check if first msdu
  192. *
  193. * @hal_soc_hdl: hal_soc handle
  194. * @hw_desc_addr: hardware descriptor address
  195. *
  196. * Return: 0 - success/ non-zero failure
  197. */
  198. static uint32_t hal_rx_desc_is_first_msdu_8074v1(void *hw_desc_addr)
  199. {
  200. struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
  201. struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
  202. return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
  203. }
  204. /**
  205. * hal_rx_msdu_end_l3_hdr_padding_get_8074v1(): API to get_8074v1 the
  206. * l3_header padding from rx_msdu_end TLV
  207. *
  208. * @ buf: pointer to the start of RX PKT TLV headers
  209. * Return: number of l3 header padding bytes
  210. */
  211. static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v1(uint8_t *buf)
  212. {
  213. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  214. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  215. uint32_t l3_header_padding;
  216. l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
  217. return l3_header_padding;
  218. }
  219. /*
  220. * @ hal_rx_encryption_info_valid_8074v1: Returns encryption type.
  221. *
  222. * @ buf: rx_tlv_hdr of the received packet
  223. * @ Return: encryption type
  224. */
  225. static uint32_t hal_rx_encryption_info_valid_8074v1(uint8_t *buf)
  226. {
  227. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  228. struct rx_mpdu_start *mpdu_start =
  229. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  230. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  231. uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
  232. return encryption_info;
  233. }
  234. /*
  235. * @ hal_rx_print_pn_8074v1: Prints the PN of rx packet.
  236. *
  237. * @ buf: rx_tlv_hdr of the received packet
  238. * @ Return: void
  239. */
  240. static void hal_rx_print_pn_8074v1(uint8_t *buf)
  241. {
  242. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  243. struct rx_mpdu_start *mpdu_start =
  244. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  245. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  246. uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
  247. uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
  248. uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
  249. uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
  250. hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ",
  251. pn_127_96, pn_95_64, pn_63_32, pn_31_0);
  252. }
  253. /**
  254. * hal_rx_msdu_end_first_msdu_get_8074v1: API to get first msdu status
  255. * from rx_msdu_end TLV
  256. *
  257. * @ buf: pointer to the start of RX PKT TLV headers
  258. * Return: first_msdu
  259. */
  260. static uint8_t
  261. hal_rx_msdu_end_first_msdu_get_8074v1(uint8_t *buf)
  262. {
  263. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  264. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  265. uint8_t first_msdu;
  266. first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
  267. return first_msdu;
  268. }
  269. /**
  270. * hal_rx_msdu_end_da_is_valid_get_8074v1: API to check if da is valid
  271. * from rx_msdu_end TLV
  272. *
  273. * @ buf: pointer to the start of RX PKT TLV headers
  274. * Return: da_is_valid
  275. */
  276. static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v1(uint8_t *buf)
  277. {
  278. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  279. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  280. uint8_t da_is_valid;
  281. da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
  282. return da_is_valid;
  283. }
  284. /**
  285. * hal_rx_msdu_end_last_msdu_get_8074v1: API to get last msdu status
  286. * from rx_msdu_end TLV
  287. *
  288. * @ buf: pointer to the start of RX PKT TLV headers
  289. * Return: last_msdu
  290. */
  291. static uint8_t hal_rx_msdu_end_last_msdu_get_8074v1(uint8_t *buf)
  292. {
  293. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  294. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  295. uint8_t last_msdu;
  296. last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
  297. return last_msdu;
  298. }
  299. /*
  300. * hal_rx_get_mpdu_mac_ad4_valid_8074v1(): Retrieves if mpdu 4th addr is valid
  301. *
  302. * @nbuf: Network buffer
  303. * Returns: value of mpdu 4th address valid field
  304. */
  305. static bool hal_rx_get_mpdu_mac_ad4_valid_8074v1(uint8_t *buf)
  306. {
  307. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  308. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  309. bool ad4_valid = 0;
  310. ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info);
  311. return ad4_valid;
  312. }
  313. /**
  314. * hal_rx_mpdu_start_sw_peer_id_get_8074v1: Retrieve sw peer_id
  315. * @buf: network buffer
  316. *
  317. * Return: sw peer_id
  318. */
  319. static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v1(uint8_t *buf)
  320. {
  321. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  322. struct rx_mpdu_start *mpdu_start =
  323. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  324. return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
  325. &mpdu_start->rx_mpdu_info_details);
  326. }
  327. /*
  328. * hal_rx_mpdu_get_to_ds_8074v1(): API to get the tods info
  329. * from rx_mpdu_start
  330. *
  331. * @buf: pointer to the start of RX PKT TLV header
  332. * Return: uint32_t(to_ds)
  333. */
  334. static uint32_t hal_rx_mpdu_get_to_ds_8074v1(uint8_t *buf)
  335. {
  336. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  337. struct rx_mpdu_start *mpdu_start =
  338. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  339. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  340. return HAL_RX_MPDU_GET_TODS(mpdu_info);
  341. }
  342. /*
  343. * hal_rx_mpdu_get_fr_ds_8074v1(): API to get the from ds info
  344. * from rx_mpdu_start
  345. *
  346. * @buf: pointer to the start of RX PKT TLV header
  347. * Return: uint32_t(fr_ds)
  348. */
  349. static uint32_t hal_rx_mpdu_get_fr_ds_8074v1(uint8_t *buf)
  350. {
  351. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  352. struct rx_mpdu_start *mpdu_start =
  353. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  354. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  355. return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
  356. }
  357. /*
  358. * hal_rx_get_mpdu_frame_control_valid_8074v1(): Retrieves mpdu
  359. * frame control valid
  360. *
  361. * @nbuf: Network buffer
  362. * Returns: value of frame control valid field
  363. */
  364. static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v1(uint8_t *buf)
  365. {
  366. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  367. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  368. return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
  369. }
  370. /*
  371. * hal_rx_mpdu_get_addr1_8074v1(): API to check get address1 of the mpdu
  372. *
  373. * @buf: pointer to the start of RX PKT TLV headera
  374. * @mac_addr: pointer to mac address
  375. * Return: success/failure
  376. */
  377. static QDF_STATUS hal_rx_mpdu_get_addr1_8074v1(uint8_t *buf,
  378. uint8_t *mac_addr)
  379. {
  380. struct __attribute__((__packed__)) hal_addr1 {
  381. uint32_t ad1_31_0;
  382. uint16_t ad1_47_32;
  383. };
  384. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  385. struct rx_mpdu_start *mpdu_start =
  386. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  387. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  388. struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
  389. uint32_t mac_addr_ad1_valid;
  390. mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
  391. if (mac_addr_ad1_valid) {
  392. addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
  393. addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
  394. return QDF_STATUS_SUCCESS;
  395. }
  396. return QDF_STATUS_E_FAILURE;
  397. }
  398. /*
  399. * hal_rx_mpdu_get_addr2_8074v1(): API to check get address2 of the mpdu
  400. * in the packet
  401. *
  402. * @buf: pointer to the start of RX PKT TLV header
  403. * @mac_addr: pointer to mac address
  404. * Return: success/failure
  405. */
  406. static QDF_STATUS hal_rx_mpdu_get_addr2_8074v1(uint8_t *buf, uint8_t *mac_addr)
  407. {
  408. struct __attribute__((__packed__)) hal_addr2 {
  409. uint16_t ad2_15_0;
  410. uint32_t ad2_47_16;
  411. };
  412. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  413. struct rx_mpdu_start *mpdu_start =
  414. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  415. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  416. struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
  417. uint32_t mac_addr_ad2_valid;
  418. mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
  419. if (mac_addr_ad2_valid) {
  420. addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
  421. addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
  422. return QDF_STATUS_SUCCESS;
  423. }
  424. return QDF_STATUS_E_FAILURE;
  425. }
  426. /*
  427. * hal_rx_mpdu_get_addr3_8074v1(): API to get address3 of the mpdu
  428. * in the packet
  429. *
  430. * @buf: pointer to the start of RX PKT TLV header
  431. * @mac_addr: pointer to mac address
  432. * Return: success/failure
  433. */
  434. static QDF_STATUS hal_rx_mpdu_get_addr3_8074v1(uint8_t *buf, uint8_t *mac_addr)
  435. {
  436. struct __attribute__((__packed__)) hal_addr3 {
  437. uint32_t ad3_31_0;
  438. uint16_t ad3_47_32;
  439. };
  440. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  441. struct rx_mpdu_start *mpdu_start =
  442. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  443. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  444. struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
  445. uint32_t mac_addr_ad3_valid;
  446. mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
  447. if (mac_addr_ad3_valid) {
  448. addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
  449. addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
  450. return QDF_STATUS_SUCCESS;
  451. }
  452. return QDF_STATUS_E_FAILURE;
  453. }
  454. /*
  455. * hal_rx_mpdu_get_addr4_8074v1(): API to get address4 of the mpdu
  456. * in the packet
  457. *
  458. * @buf: pointer to the start of RX PKT TLV header
  459. * @mac_addr: pointer to mac address
  460. * Return: success/failure
  461. */
  462. static QDF_STATUS hal_rx_mpdu_get_addr4_8074v1(uint8_t *buf, uint8_t *mac_addr)
  463. {
  464. struct __attribute__((__packed__)) hal_addr4 {
  465. uint32_t ad4_31_0;
  466. uint16_t ad4_47_32;
  467. };
  468. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  469. struct rx_mpdu_start *mpdu_start =
  470. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  471. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  472. struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
  473. uint32_t mac_addr_ad4_valid;
  474. mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
  475. if (mac_addr_ad4_valid) {
  476. addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
  477. addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
  478. return QDF_STATUS_SUCCESS;
  479. }
  480. return QDF_STATUS_E_FAILURE;
  481. }
  482. /*
  483. * hal_rx_get_mpdu_sequence_control_valid_8074v1(): Get mpdu
  484. * sequence control valid
  485. *
  486. * @nbuf: Network buffer
  487. * Returns: value of sequence control valid field
  488. */
  489. static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v1(uint8_t *buf)
  490. {
  491. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  492. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  493. return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
  494. }
  495. /**
  496. * hal_rx_is_unicast_8074v1: check packet is unicast frame or not.
  497. *
  498. * @ buf: pointer to rx pkt TLV.
  499. *
  500. * Return: true on unicast.
  501. */
  502. static bool hal_rx_is_unicast_8074v1(uint8_t *buf)
  503. {
  504. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  505. struct rx_mpdu_start *mpdu_start =
  506. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  507. uint32_t grp_id;
  508. uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
  509. grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
  510. RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)),
  511. RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK,
  512. RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB));
  513. return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
  514. }
  515. /**
  516. * hal_rx_tid_get_8074v1: get tid based on qos control valid.
  517. *
  518. * @ buf: pointer to rx pkt TLV.
  519. *
  520. * Return: tid
  521. */
  522. static uint32_t hal_rx_tid_get_8074v1(hal_soc_handle_t hal_soc_hdl,
  523. uint8_t *buf)
  524. {
  525. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  526. struct rx_mpdu_start *mpdu_start =
  527. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  528. uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
  529. uint8_t qos_control_valid =
  530. (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
  531. RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)),
  532. RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK,
  533. RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB));
  534. if (qos_control_valid)
  535. return hal_rx_mpdu_start_tid_get_8074(buf);
  536. return HAL_RX_NON_QOS_TID;
  537. }
  538. /**
  539. * hal_rx_hw_desc_get_ppduid_get_8074v1(): retrieve ppdu id
  540. * @rx_tlv_hdr: Rx tlv header
  541. * @rxdma_dst_ring_desc: Rx HW descriptor
  542. *
  543. * Return: ppdu id
  544. */
  545. static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v1(void *rx_tlv_hdr,
  546. void *rxdma_dst_ring_desc)
  547. {
  548. struct rx_mpdu_info *rx_mpdu_info;
  549. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
  550. rx_mpdu_info =
  551. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  552. return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
  553. }
  554. /**
  555. * hal_reo_status_get_header_8074v1 - Process reo desc info
  556. * @ring_desc: REO status ring descriptor
  557. * @b - tlv type info
  558. * @h1 - Pointer to hal_reo_status_header where info to be stored
  559. *
  560. * Return - none.
  561. *
  562. */
  563. static void hal_reo_status_get_header_8074v1(hal_ring_desc_t ring_desc, int b,
  564. void *h1)
  565. {
  566. uint32_t *d = (uint32_t *)ring_desc;
  567. uint32_t val1 = 0;
  568. struct hal_reo_status_header *h =
  569. (struct hal_reo_status_header *)h1;
  570. /* Offsets of descriptor fields defined in HW headers start
  571. * from the field after TLV header
  572. */
  573. d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
  574. switch (b) {
  575. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  576. val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
  577. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  578. break;
  579. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  580. val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
  581. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  582. break;
  583. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  584. val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
  585. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  586. break;
  587. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  588. val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
  589. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  590. break;
  591. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  592. val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
  593. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  594. break;
  595. case HAL_REO_DESC_THRES_STATUS_TLV:
  596. val1 =
  597. d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
  598. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  599. break;
  600. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  601. val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
  602. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  603. break;
  604. default:
  605. qdf_nofl_err("ERROR: Unknown tlv\n");
  606. break;
  607. }
  608. h->cmd_num =
  609. HAL_GET_FIELD(
  610. UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
  611. val1);
  612. h->exec_time =
  613. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
  614. CMD_EXECUTION_TIME, val1);
  615. h->status =
  616. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
  617. REO_CMD_EXECUTION_STATUS, val1);
  618. switch (b) {
  619. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  620. val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
  621. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  622. break;
  623. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  624. val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
  625. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  626. break;
  627. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  628. val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
  629. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  630. break;
  631. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  632. val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
  633. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  634. break;
  635. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  636. val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
  637. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  638. break;
  639. case HAL_REO_DESC_THRES_STATUS_TLV:
  640. val1 =
  641. d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
  642. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  643. break;
  644. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  645. val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
  646. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  647. break;
  648. default:
  649. qdf_nofl_err("ERROR: Unknown tlv\n");
  650. break;
  651. }
  652. h->tstamp =
  653. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
  654. }
  655. /**
  656. * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1():
  657. * Retrieve qos control valid bit from the tlv.
  658. * @buf: pointer to rx pkt TLV.
  659. *
  660. * Return: qos control value.
  661. */
  662. static inline uint32_t
  663. hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(uint8_t *buf)
  664. {
  665. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  666. struct rx_mpdu_start *mpdu_start =
  667. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  668. return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
  669. &mpdu_start->rx_mpdu_info_details);
  670. }
  671. /**
  672. * hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(): API to get the
  673. * sa_sw_peer_id from rx_msdu_end TLV
  674. * @buf: pointer to the start of RX PKT TLV headers
  675. *
  676. * Return: sa_sw_peer_id index
  677. */
  678. static inline uint32_t
  679. hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(uint8_t *buf)
  680. {
  681. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  682. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  683. return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
  684. }
  685. /**
  686. * hal_tx_desc_set_mesh_en_8074v1 - Set mesh_enable flag in Tx descriptor
  687. * @desc: Handle to Tx Descriptor
  688. * @en: For raw WiFi frames, this indicates transmission to a mesh STA,
  689. * enabling the interpretation of the 'Mesh Control Present' bit
  690. * (bit 8) of QoS Control (otherwise this bit is ignored),
  691. * For native WiFi frames, this indicates that a 'Mesh Control' field
  692. * is present between the header and the LLC.
  693. *
  694. * Return: void
  695. */
  696. static inline
  697. void hal_tx_desc_set_mesh_en_8074v1(void *desc, uint8_t en)
  698. {
  699. HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
  700. HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
  701. }
  702. static
  703. void *hal_rx_msdu0_buffer_addr_lsb_8074v1(void *link_desc_va)
  704. {
  705. return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
  706. }
  707. static
  708. void *hal_rx_msdu_desc_info_ptr_get_8074v1(void *msdu0)
  709. {
  710. return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
  711. }
  712. static
  713. void *hal_ent_mpdu_desc_info_8074v1(void *ent_ring_desc)
  714. {
  715. return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
  716. }
  717. static
  718. void *hal_dst_mpdu_desc_info_8074v1(void *dst_ring_desc)
  719. {
  720. return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
  721. }
  722. static
  723. uint8_t hal_rx_get_fc_valid_8074v1(uint8_t *buf)
  724. {
  725. return HAL_RX_GET_FC_VALID(buf);
  726. }
  727. static uint8_t hal_rx_get_to_ds_flag_8074v1(uint8_t *buf)
  728. {
  729. return HAL_RX_GET_TO_DS_FLAG(buf);
  730. }
  731. static uint8_t hal_rx_get_mac_addr2_valid_8074v1(uint8_t *buf)
  732. {
  733. return HAL_RX_GET_MAC_ADDR2_VALID(buf);
  734. }
  735. static uint8_t hal_rx_get_filter_category_8074v1(uint8_t *buf)
  736. {
  737. return HAL_RX_GET_FILTER_CATEGORY(buf);
  738. }
  739. static uint32_t
  740. hal_rx_get_ppdu_id_8074v1(uint8_t *buf)
  741. {
  742. struct rx_mpdu_info *rx_mpdu_info;
  743. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf;
  744. rx_mpdu_info =
  745. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  746. return HAL_RX_GET_PPDU_ID(rx_mpdu_info);
  747. }
  748. /**
  749. * hal_reo_config_8074v1(): Set reo config parameters
  750. * @soc: hal soc handle
  751. * @reg_val: value to be set
  752. * @reo_params: reo parameters
  753. *
  754. * Return: void
  755. */
  756. static void
  757. hal_reo_config_8074v1(struct hal_soc *soc,
  758. uint32_t reg_val,
  759. struct hal_reo_params *reo_params)
  760. {
  761. HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
  762. }
  763. /**
  764. * hal_rx_msdu_desc_info_get_ptr_8074v1() - Get msdu desc info ptr
  765. * @msdu_details_ptr - Pointer to msdu_details_ptr
  766. *
  767. * Return - Pointer to rx_msdu_desc_info structure.
  768. *
  769. */
  770. static void *hal_rx_msdu_desc_info_get_ptr_8074v1(void *msdu_details_ptr)
  771. {
  772. return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
  773. }
  774. /**
  775. * hal_rx_link_desc_msdu0_ptr_8074v1 - Get pointer to rx_msdu details
  776. * @link_desc - Pointer to link desc
  777. *
  778. * Return - Pointer to rx_msdu_details structure
  779. *
  780. */
  781. static void *hal_rx_link_desc_msdu0_ptr_8074v1(void *link_desc)
  782. {
  783. return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
  784. }
  785. /**
  786. * hal_rx_msdu_flow_idx_get_8074v1: API to get flow index
  787. * from rx_msdu_end TLV
  788. * @buf: pointer to the start of RX PKT TLV headers
  789. *
  790. * Return: flow index value from MSDU END TLV
  791. */
  792. static inline uint32_t hal_rx_msdu_flow_idx_get_8074v1(uint8_t *buf)
  793. {
  794. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  795. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  796. return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
  797. }
  798. /**
  799. * hal_rx_msdu_flow_idx_invalid_8074v1: API to get flow index invalid
  800. * from rx_msdu_end TLV
  801. * @buf: pointer to the start of RX PKT TLV headers
  802. *
  803. * Return: flow index invalid value from MSDU END TLV
  804. */
  805. static bool hal_rx_msdu_flow_idx_invalid_8074v1(uint8_t *buf)
  806. {
  807. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  808. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  809. return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
  810. }
  811. /**
  812. * hal_rx_msdu_flow_idx_timeout_8074v1: API to get flow index timeout
  813. * from rx_msdu_end TLV
  814. * @buf: pointer to the start of RX PKT TLV headers
  815. *
  816. * Return: flow index timeout value from MSDU END TLV
  817. */
  818. static bool hal_rx_msdu_flow_idx_timeout_8074v1(uint8_t *buf)
  819. {
  820. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  821. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  822. return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
  823. }
  824. /**
  825. * hal_rx_msdu_fse_metadata_get_8074v1: API to get FSE metadata
  826. * from rx_msdu_end TLV
  827. * @buf: pointer to the start of RX PKT TLV headers
  828. *
  829. * Return: fse metadata value from MSDU END TLV
  830. */
  831. static uint32_t hal_rx_msdu_fse_metadata_get_8074v1(uint8_t *buf)
  832. {
  833. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  834. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  835. return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
  836. }
  837. /**
  838. * hal_rx_msdu_cce_metadata_get_8074v1: API to get CCE metadata
  839. * from rx_msdu_end TLV
  840. * @buf: pointer to the start of RX PKT TLV headers
  841. *
  842. * Return: cce_metadata
  843. */
  844. static uint16_t
  845. hal_rx_msdu_cce_metadata_get_8074v1(uint8_t *buf)
  846. {
  847. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  848. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  849. return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
  850. }
  851. /**
  852. * hal_rx_msdu_get_flow_params_8074v1: API to get flow index, flow index invalid
  853. * and flow index timeout from rx_msdu_end TLV
  854. * @buf: pointer to the start of RX PKT TLV headers
  855. * @flow_invalid: pointer to return value of flow_idx_valid
  856. * @flow_timeout: pointer to return value of flow_idx_timeout
  857. * @flow_index: pointer to return value of flow_idx
  858. *
  859. * Return: none
  860. */
  861. static inline void
  862. hal_rx_msdu_get_flow_params_8074v1(uint8_t *buf,
  863. bool *flow_invalid,
  864. bool *flow_timeout,
  865. uint32_t *flow_index)
  866. {
  867. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  868. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  869. *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
  870. *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
  871. *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
  872. }
  873. /**
  874. * hal_rx_tlv_get_tcp_chksum_8074v1() - API to get tcp checksum
  875. * @buf: rx_tlv_hdr
  876. *
  877. * Return: tcp checksum
  878. */
  879. static uint16_t
  880. hal_rx_tlv_get_tcp_chksum_8074v1(uint8_t *buf)
  881. {
  882. return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
  883. }
  884. /**
  885. * hal_rx_get_rx_sequence_8074v1(): Function to retrieve rx sequence number
  886. *
  887. * @nbuf: Network buffer
  888. * Returns: rx sequence number
  889. */
  890. static
  891. uint16_t hal_rx_get_rx_sequence_8074v1(uint8_t *buf)
  892. {
  893. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  894. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  895. return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
  896. }
  897. /**
  898. * hal_rx_mpdu_start_tlv_tag_valid_8074v1 () - API to check if RX_MPDU_START
  899. * tlv tag is valid
  900. *
  901. * @rx_tlv_hdr: start address of rx_pkt_tlvs
  902. *
  903. * Return: true if RX_MPDU_START is valied, else false.
  904. */
  905. uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v1(void *rx_tlv_hdr)
  906. {
  907. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
  908. uint32_t tlv_tag;
  909. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(
  910. &rx_desc->mpdu_start_tlv);
  911. return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
  912. }
  913. /**
  914. * hal_rx_flow_setup_fse_8074v1() - Setup a flow search entry in HW FST
  915. * @fst: Pointer to the Rx Flow Search Table
  916. * @table_offset: offset into the table where the flow is to be setup
  917. * @flow: Flow Parameters
  918. *
  919. * Return: Success/Failure
  920. */
  921. static void *
  922. hal_rx_flow_setup_fse_8074v1(uint8_t *rx_fst, uint32_t table_offset,
  923. uint8_t *rx_flow)
  924. {
  925. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  926. struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
  927. uint8_t *fse;
  928. bool fse_valid;
  929. if (table_offset >= fst->max_entries) {
  930. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  931. "HAL FSE table offset %u exceeds max entries %u",
  932. table_offset, fst->max_entries);
  933. return NULL;
  934. }
  935. fse = (uint8_t *)fst->base_vaddr +
  936. (table_offset * HAL_RX_FST_ENTRY_SIZE);
  937. fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
  938. if (fse_valid) {
  939. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  940. "HAL FSE %pK already valid", fse);
  941. return NULL;
  942. }
  943. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) =
  944. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96,
  945. qdf_htonl(flow->tuple_info.src_ip_127_96));
  946. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) =
  947. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64,
  948. qdf_htonl(flow->tuple_info.src_ip_95_64));
  949. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) =
  950. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32,
  951. qdf_htonl(flow->tuple_info.src_ip_63_32));
  952. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) =
  953. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0,
  954. qdf_htonl(flow->tuple_info.src_ip_31_0));
  955. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) =
  956. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96,
  957. qdf_htonl(flow->tuple_info.dest_ip_127_96));
  958. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) =
  959. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64,
  960. qdf_htonl(flow->tuple_info.dest_ip_95_64));
  961. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) =
  962. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32,
  963. qdf_htonl(flow->tuple_info.dest_ip_63_32));
  964. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) =
  965. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0,
  966. qdf_htonl(flow->tuple_info.dest_ip_31_0));
  967. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT);
  968. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |=
  969. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT,
  970. (flow->tuple_info.dest_port));
  971. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT);
  972. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |=
  973. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT,
  974. (flow->tuple_info.src_port));
  975. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL);
  976. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |=
  977. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL,
  978. flow->tuple_info.l4_protocol);
  979. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER);
  980. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |=
  981. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER,
  982. flow->reo_destination_handler);
  983. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
  984. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |=
  985. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1);
  986. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA);
  987. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) =
  988. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA,
  989. flow->fse_metadata);
  990. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION);
  991. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |=
  992. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11,
  993. REO_DESTINATION_INDICATION,
  994. flow->reo_destination_indication);
  995. /* Reset all the other fields in FSE */
  996. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9);
  997. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP);
  998. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11);
  999. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT);
  1000. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT);
  1001. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP);
  1002. return fse;
  1003. }
  1004. static
  1005. void hal_compute_reo_remap_ix2_ix3_8074v1(uint32_t *ring, uint32_t num_rings,
  1006. uint32_t *remap1, uint32_t *remap2)
  1007. {
  1008. switch (num_rings) {
  1009. case 1:
  1010. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1011. HAL_REO_REMAP_IX2(ring[0], 17) |
  1012. HAL_REO_REMAP_IX2(ring[0], 18) |
  1013. HAL_REO_REMAP_IX2(ring[0], 19) |
  1014. HAL_REO_REMAP_IX2(ring[0], 20) |
  1015. HAL_REO_REMAP_IX2(ring[0], 21) |
  1016. HAL_REO_REMAP_IX2(ring[0], 22) |
  1017. HAL_REO_REMAP_IX2(ring[0], 23);
  1018. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  1019. HAL_REO_REMAP_IX3(ring[0], 25) |
  1020. HAL_REO_REMAP_IX3(ring[0], 26) |
  1021. HAL_REO_REMAP_IX3(ring[0], 27) |
  1022. HAL_REO_REMAP_IX3(ring[0], 28) |
  1023. HAL_REO_REMAP_IX3(ring[0], 29) |
  1024. HAL_REO_REMAP_IX3(ring[0], 30) |
  1025. HAL_REO_REMAP_IX3(ring[0], 31);
  1026. break;
  1027. case 2:
  1028. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1029. HAL_REO_REMAP_IX2(ring[0], 17) |
  1030. HAL_REO_REMAP_IX2(ring[1], 18) |
  1031. HAL_REO_REMAP_IX2(ring[1], 19) |
  1032. HAL_REO_REMAP_IX2(ring[0], 20) |
  1033. HAL_REO_REMAP_IX2(ring[0], 21) |
  1034. HAL_REO_REMAP_IX2(ring[1], 22) |
  1035. HAL_REO_REMAP_IX2(ring[1], 23);
  1036. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  1037. HAL_REO_REMAP_IX3(ring[0], 25) |
  1038. HAL_REO_REMAP_IX3(ring[1], 26) |
  1039. HAL_REO_REMAP_IX3(ring[1], 27) |
  1040. HAL_REO_REMAP_IX3(ring[0], 28) |
  1041. HAL_REO_REMAP_IX3(ring[0], 29) |
  1042. HAL_REO_REMAP_IX3(ring[1], 30) |
  1043. HAL_REO_REMAP_IX3(ring[1], 31);
  1044. break;
  1045. case 3:
  1046. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1047. HAL_REO_REMAP_IX2(ring[1], 17) |
  1048. HAL_REO_REMAP_IX2(ring[2], 18) |
  1049. HAL_REO_REMAP_IX2(ring[0], 19) |
  1050. HAL_REO_REMAP_IX2(ring[1], 20) |
  1051. HAL_REO_REMAP_IX2(ring[2], 21) |
  1052. HAL_REO_REMAP_IX2(ring[0], 22) |
  1053. HAL_REO_REMAP_IX2(ring[1], 23);
  1054. *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
  1055. HAL_REO_REMAP_IX3(ring[0], 25) |
  1056. HAL_REO_REMAP_IX3(ring[1], 26) |
  1057. HAL_REO_REMAP_IX3(ring[2], 27) |
  1058. HAL_REO_REMAP_IX3(ring[0], 28) |
  1059. HAL_REO_REMAP_IX3(ring[1], 29) |
  1060. HAL_REO_REMAP_IX3(ring[2], 30) |
  1061. HAL_REO_REMAP_IX3(ring[0], 31);
  1062. break;
  1063. case 4:
  1064. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1065. HAL_REO_REMAP_IX2(ring[1], 17) |
  1066. HAL_REO_REMAP_IX2(ring[2], 18) |
  1067. HAL_REO_REMAP_IX2(ring[3], 19) |
  1068. HAL_REO_REMAP_IX2(ring[0], 20) |
  1069. HAL_REO_REMAP_IX2(ring[1], 21) |
  1070. HAL_REO_REMAP_IX2(ring[2], 22) |
  1071. HAL_REO_REMAP_IX2(ring[3], 23);
  1072. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  1073. HAL_REO_REMAP_IX3(ring[1], 25) |
  1074. HAL_REO_REMAP_IX3(ring[2], 26) |
  1075. HAL_REO_REMAP_IX3(ring[3], 27) |
  1076. HAL_REO_REMAP_IX3(ring[0], 28) |
  1077. HAL_REO_REMAP_IX3(ring[1], 29) |
  1078. HAL_REO_REMAP_IX3(ring[2], 30) |
  1079. HAL_REO_REMAP_IX3(ring[3], 31);
  1080. break;
  1081. }
  1082. }
  1083. static void hal_hw_txrx_ops_attach_qca8074(struct hal_soc *hal_soc)
  1084. {
  1085. /* init and setup */
  1086. hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
  1087. hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
  1088. hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
  1089. hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
  1090. hal_soc->ops->hal_get_window_address = hal_get_window_address_8074;
  1091. /* tx */
  1092. hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
  1093. hal_tx_desc_set_dscp_tid_table_id_8074;
  1094. hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074;
  1095. hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074;
  1096. hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074;
  1097. hal_soc->ops->hal_tx_desc_set_buf_addr =
  1098. hal_tx_desc_set_buf_addr_generic_li;
  1099. hal_soc->ops->hal_tx_desc_set_search_type =
  1100. hal_tx_desc_set_search_type_generic_li;
  1101. hal_soc->ops->hal_tx_desc_set_search_index =
  1102. hal_tx_desc_set_search_index_generic_li;
  1103. hal_soc->ops->hal_tx_desc_set_cache_set_num =
  1104. hal_tx_desc_set_cache_set_num_generic_li;
  1105. hal_soc->ops->hal_tx_comp_get_status =
  1106. hal_tx_comp_get_status_generic_li;
  1107. hal_soc->ops->hal_tx_comp_get_release_reason =
  1108. hal_tx_comp_get_release_reason_generic_li;
  1109. hal_soc->ops->hal_get_wbm_internal_error =
  1110. hal_get_wbm_internal_error_generic_li;
  1111. hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v1;
  1112. hal_soc->ops->hal_tx_init_cmd_credit_ring =
  1113. hal_tx_init_cmd_credit_ring_8074v1;
  1114. /* rx */
  1115. hal_soc->ops->hal_rx_msdu_start_nss_get =
  1116. hal_rx_msdu_start_nss_get_8074;
  1117. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
  1118. hal_rx_mon_hw_desc_get_mpdu_status_8074;
  1119. hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074;
  1120. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
  1121. hal_rx_proc_phyrx_other_receive_info_tlv_8074;
  1122. hal_soc->ops->hal_rx_dump_msdu_start_tlv =
  1123. hal_rx_dump_msdu_start_tlv_8074;
  1124. hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074;
  1125. hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074;
  1126. hal_soc->ops->hal_rx_mpdu_start_tid_get =
  1127. hal_rx_mpdu_start_tid_get_8074;
  1128. hal_soc->ops->hal_rx_msdu_start_reception_type_get =
  1129. hal_rx_msdu_start_reception_type_get_8074;
  1130. hal_soc->ops->hal_rx_msdu_end_da_idx_get =
  1131. hal_rx_msdu_end_da_idx_get_8074;
  1132. hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
  1133. hal_rx_msdu_desc_info_get_ptr_8074v1;
  1134. hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
  1135. hal_rx_link_desc_msdu0_ptr_8074v1;
  1136. hal_soc->ops->hal_reo_status_get_header =
  1137. hal_reo_status_get_header_8074v1;
  1138. hal_soc->ops->hal_rx_status_get_tlv_info =
  1139. hal_rx_status_get_tlv_info_generic_li;
  1140. hal_soc->ops->hal_rx_wbm_err_info_get =
  1141. hal_rx_wbm_err_info_get_generic_li;
  1142. hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
  1143. hal_rx_dump_mpdu_start_tlv_generic_li;
  1144. hal_soc->ops->hal_tx_set_pcp_tid_map =
  1145. hal_tx_set_pcp_tid_map_generic_li;
  1146. hal_soc->ops->hal_tx_update_pcp_tid_map =
  1147. hal_tx_update_pcp_tid_generic_li;
  1148. hal_soc->ops->hal_tx_set_tidmap_prty =
  1149. hal_tx_update_tidmap_prty_generic_li;
  1150. hal_soc->ops->hal_rx_get_rx_fragment_number =
  1151. hal_rx_get_rx_fragment_number_8074v1;
  1152. hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
  1153. hal_rx_msdu_end_da_is_mcbc_get_8074v1;
  1154. hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
  1155. hal_rx_msdu_end_sa_is_valid_get_8074v1;
  1156. hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
  1157. hal_rx_msdu_end_sa_idx_get_8074v1;
  1158. hal_soc->ops->hal_rx_desc_is_first_msdu =
  1159. hal_rx_desc_is_first_msdu_8074v1;
  1160. hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
  1161. hal_rx_msdu_end_l3_hdr_padding_get_8074v1;
  1162. hal_soc->ops->hal_rx_encryption_info_valid =
  1163. hal_rx_encryption_info_valid_8074v1;
  1164. hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v1;
  1165. hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
  1166. hal_rx_msdu_end_first_msdu_get_8074v1;
  1167. hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
  1168. hal_rx_msdu_end_da_is_valid_get_8074v1;
  1169. hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
  1170. hal_rx_msdu_end_last_msdu_get_8074v1;
  1171. hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
  1172. hal_rx_get_mpdu_mac_ad4_valid_8074v1;
  1173. hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
  1174. hal_rx_mpdu_start_sw_peer_id_get_8074v1;
  1175. hal_soc->ops->hal_rx_mpdu_peer_meta_data_get =
  1176. hal_rx_mpdu_peer_meta_data_get_li;
  1177. hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v1;
  1178. hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v1;
  1179. hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
  1180. hal_rx_get_mpdu_frame_control_valid_8074v1;
  1181. hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v1;
  1182. hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v1;
  1183. hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v1;
  1184. hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v1;
  1185. hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
  1186. hal_rx_get_mpdu_sequence_control_valid_8074v1;
  1187. hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v1;
  1188. hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v1;
  1189. hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
  1190. hal_rx_hw_desc_get_ppduid_get_8074v1;
  1191. hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
  1192. hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1;
  1193. hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
  1194. hal_rx_msdu_end_sa_sw_peer_id_get_8074v1;
  1195. hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
  1196. hal_rx_msdu0_buffer_addr_lsb_8074v1;
  1197. hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
  1198. hal_rx_msdu_desc_info_ptr_get_8074v1;
  1199. hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v1;
  1200. hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v1;
  1201. hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v1;
  1202. hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v1;
  1203. hal_soc->ops->hal_rx_get_mac_addr2_valid =
  1204. hal_rx_get_mac_addr2_valid_8074v1;
  1205. hal_soc->ops->hal_rx_get_filter_category =
  1206. hal_rx_get_filter_category_8074v1;
  1207. hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v1;
  1208. hal_soc->ops->hal_reo_config = hal_reo_config_8074v1;
  1209. hal_soc->ops->hal_rx_msdu_flow_idx_get =
  1210. hal_rx_msdu_flow_idx_get_8074v1;
  1211. hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
  1212. hal_rx_msdu_flow_idx_invalid_8074v1;
  1213. hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
  1214. hal_rx_msdu_flow_idx_timeout_8074v1;
  1215. hal_soc->ops->hal_rx_msdu_fse_metadata_get =
  1216. hal_rx_msdu_fse_metadata_get_8074v1;
  1217. hal_soc->ops->hal_rx_msdu_cce_match_get =
  1218. hal_rx_msdu_cce_match_get_li;
  1219. hal_soc->ops->hal_rx_msdu_cce_metadata_get =
  1220. hal_rx_msdu_cce_metadata_get_8074v1;
  1221. hal_soc->ops->hal_rx_msdu_get_flow_params =
  1222. hal_rx_msdu_get_flow_params_8074v1;
  1223. hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
  1224. hal_rx_tlv_get_tcp_chksum_8074v1;
  1225. hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v1;
  1226. /* rx - msdu fast path info fields */
  1227. hal_soc->ops->hal_rx_msdu_packet_metadata_get =
  1228. hal_rx_msdu_packet_metadata_get_generic_li;
  1229. hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
  1230. hal_rx_mpdu_start_tlv_tag_valid_8074v1;
  1231. /* rx - TLV struct offsets */
  1232. hal_soc->ops->hal_rx_msdu_end_offset_get =
  1233. hal_rx_msdu_end_offset_get_generic;
  1234. hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
  1235. hal_soc->ops->hal_rx_msdu_start_offset_get =
  1236. hal_rx_msdu_start_offset_get_generic;
  1237. hal_soc->ops->hal_rx_mpdu_start_offset_get =
  1238. hal_rx_mpdu_start_offset_get_generic;
  1239. hal_soc->ops->hal_rx_mpdu_end_offset_get =
  1240. hal_rx_mpdu_end_offset_get_generic;
  1241. #ifndef NO_RX_PKT_HDR_TLV
  1242. hal_soc->ops->hal_rx_pkt_tlv_offset_get =
  1243. hal_rx_pkt_tlv_offset_get_generic;
  1244. #endif
  1245. hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v1;
  1246. hal_soc->ops->hal_rx_flow_get_tuple_info =
  1247. hal_rx_flow_get_tuple_info_li;
  1248. hal_soc->ops->hal_rx_flow_delete_entry =
  1249. hal_rx_flow_delete_entry_li;
  1250. hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li;
  1251. hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
  1252. hal_compute_reo_remap_ix2_ix3_8074v1;
  1253. hal_soc->ops->hal_setup_link_idle_list =
  1254. hal_setup_link_idle_list_generic_li;
  1255. hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
  1256. };
  1257. struct hal_hw_srng_config hw_srng_table_8074[] = {
  1258. /* TODO: max_rings can populated by querying HW capabilities */
  1259. { /* REO_DST */
  1260. .start_ring_id = HAL_SRNG_REO2SW1,
  1261. .max_rings = 4,
  1262. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1263. .lmac_ring = FALSE,
  1264. .ring_dir = HAL_SRNG_DST_RING,
  1265. .reg_start = {
  1266. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
  1267. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1268. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
  1269. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1270. },
  1271. .reg_size = {
  1272. HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
  1273. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
  1274. HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
  1275. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
  1276. },
  1277. .max_size =
  1278. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1279. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
  1280. },
  1281. { /* REO_EXCEPTION */
  1282. /* Designating REO2TCL ring as exception ring. This ring is
  1283. * similar to other REO2SW rings though it is named as REO2TCL.
  1284. * Any of theREO2SW rings can be used as exception ring.
  1285. */
  1286. .start_ring_id = HAL_SRNG_REO2TCL,
  1287. .max_rings = 1,
  1288. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1289. .lmac_ring = FALSE,
  1290. .ring_dir = HAL_SRNG_DST_RING,
  1291. .reg_start = {
  1292. HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
  1293. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1294. HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
  1295. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1296. },
  1297. /* Single ring - provide ring size if multiple rings of this
  1298. * type are supported
  1299. */
  1300. .reg_size = {},
  1301. .max_size =
  1302. HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
  1303. HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
  1304. },
  1305. { /* REO_REINJECT */
  1306. .start_ring_id = HAL_SRNG_SW2REO,
  1307. .max_rings = 1,
  1308. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1309. .lmac_ring = FALSE,
  1310. .ring_dir = HAL_SRNG_SRC_RING,
  1311. .reg_start = {
  1312. HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
  1313. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1314. HWIO_REO_R2_SW2REO_RING_HP_ADDR(
  1315. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1316. },
  1317. /* Single ring - provide ring size if multiple rings of this
  1318. * type are supported
  1319. */
  1320. .reg_size = {},
  1321. .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
  1322. HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
  1323. },
  1324. { /* REO_CMD */
  1325. .start_ring_id = HAL_SRNG_REO_CMD,
  1326. .max_rings = 1,
  1327. .entry_size = (sizeof(struct tlv_32_hdr) +
  1328. sizeof(struct reo_get_queue_stats)) >> 2,
  1329. .lmac_ring = FALSE,
  1330. .ring_dir = HAL_SRNG_SRC_RING,
  1331. .reg_start = {
  1332. HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
  1333. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1334. HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
  1335. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1336. },
  1337. /* Single ring - provide ring size if multiple rings of this
  1338. * type are supported
  1339. */
  1340. .reg_size = {},
  1341. .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
  1342. HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
  1343. },
  1344. { /* REO_STATUS */
  1345. .start_ring_id = HAL_SRNG_REO_STATUS,
  1346. .max_rings = 1,
  1347. .entry_size = (sizeof(struct tlv_32_hdr) +
  1348. sizeof(struct reo_get_queue_stats_status)) >> 2,
  1349. .lmac_ring = FALSE,
  1350. .ring_dir = HAL_SRNG_DST_RING,
  1351. .reg_start = {
  1352. HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
  1353. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1354. HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
  1355. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1356. },
  1357. /* Single ring - provide ring size if multiple rings of this
  1358. * type are supported
  1359. */
  1360. .reg_size = {},
  1361. .max_size =
  1362. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1363. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1364. },
  1365. { /* TCL_DATA */
  1366. .start_ring_id = HAL_SRNG_SW2TCL1,
  1367. .max_rings = 3,
  1368. .entry_size = (sizeof(struct tlv_32_hdr) +
  1369. sizeof(struct tcl_data_cmd)) >> 2,
  1370. .lmac_ring = FALSE,
  1371. .ring_dir = HAL_SRNG_SRC_RING,
  1372. .reg_start = {
  1373. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
  1374. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1375. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
  1376. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1377. },
  1378. .reg_size = {
  1379. HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
  1380. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
  1381. HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
  1382. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
  1383. },
  1384. .max_size =
  1385. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1386. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
  1387. },
  1388. { /* TCL_CMD */
  1389. .start_ring_id = HAL_SRNG_SW2TCL_CMD,
  1390. .max_rings = 1,
  1391. .entry_size = (sizeof(struct tlv_32_hdr) +
  1392. sizeof(struct tcl_data_cmd)) >> 2,
  1393. .lmac_ring = FALSE,
  1394. .ring_dir = HAL_SRNG_SRC_RING,
  1395. .reg_start = {
  1396. HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(
  1397. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1398. HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(
  1399. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1400. },
  1401. /* Single ring - provide ring size if multiple rings of this
  1402. * type are supported
  1403. */
  1404. .reg_size = {},
  1405. .max_size =
  1406. HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
  1407. HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
  1408. },
  1409. { /* TCL_STATUS */
  1410. .start_ring_id = HAL_SRNG_TCL_STATUS,
  1411. .max_rings = 1,
  1412. .entry_size = (sizeof(struct tlv_32_hdr) +
  1413. sizeof(struct tcl_status_ring)) >> 2,
  1414. .lmac_ring = FALSE,
  1415. .ring_dir = HAL_SRNG_DST_RING,
  1416. .reg_start = {
  1417. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
  1418. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1419. HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
  1420. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1421. },
  1422. /* Single ring - provide ring size if multiple rings of this
  1423. * type are supported
  1424. */
  1425. .reg_size = {},
  1426. .max_size =
  1427. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1428. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
  1429. },
  1430. { /* CE_SRC */
  1431. .start_ring_id = HAL_SRNG_CE_0_SRC,
  1432. .max_rings = 12,
  1433. .entry_size = sizeof(struct ce_src_desc) >> 2,
  1434. .lmac_ring = FALSE,
  1435. .ring_dir = HAL_SRNG_SRC_RING,
  1436. .reg_start = {
  1437. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1438. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
  1439. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1440. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
  1441. },
  1442. .reg_size = {
  1443. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
  1444. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
  1445. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
  1446. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
  1447. },
  1448. .max_size =
  1449. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1450. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1451. },
  1452. { /* CE_DST */
  1453. .start_ring_id = HAL_SRNG_CE_0_DST,
  1454. .max_rings = 12,
  1455. .entry_size = 8 >> 2,
  1456. /*TODO: entry_size above should actually be
  1457. * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
  1458. * of struct ce_dst_desc in HW header files
  1459. */
  1460. .lmac_ring = FALSE,
  1461. .ring_dir = HAL_SRNG_SRC_RING,
  1462. .reg_start = {
  1463. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1464. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1465. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1466. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1467. },
  1468. .reg_size = {
  1469. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1470. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1471. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1472. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1473. },
  1474. .max_size =
  1475. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1476. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1477. },
  1478. { /* CE_DST_STATUS */
  1479. .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
  1480. .max_rings = 12,
  1481. .entry_size = sizeof(struct ce_stat_desc) >> 2,
  1482. .lmac_ring = FALSE,
  1483. .ring_dir = HAL_SRNG_DST_RING,
  1484. .reg_start = {
  1485. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
  1486. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1487. HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
  1488. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1489. },
  1490. /* TODO: check destination status ring registers */
  1491. .reg_size = {
  1492. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1493. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1494. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1495. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1496. },
  1497. .max_size =
  1498. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1499. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1500. },
  1501. { /* WBM_IDLE_LINK */
  1502. .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
  1503. .max_rings = 1,
  1504. .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
  1505. .lmac_ring = FALSE,
  1506. .ring_dir = HAL_SRNG_SRC_RING,
  1507. .reg_start = {
  1508. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1509. HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1510. },
  1511. /* Single ring - provide ring size if multiple rings of this
  1512. * type are supported
  1513. */
  1514. .reg_size = {},
  1515. .max_size =
  1516. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
  1517. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
  1518. },
  1519. { /* SW2WBM_RELEASE */
  1520. .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
  1521. .max_rings = 1,
  1522. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  1523. .lmac_ring = FALSE,
  1524. .ring_dir = HAL_SRNG_SRC_RING,
  1525. .reg_start = {
  1526. HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1527. HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1528. },
  1529. /* Single ring - provide ring size if multiple rings of this
  1530. * type are supported
  1531. */
  1532. .reg_size = {},
  1533. .max_size =
  1534. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  1535. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  1536. },
  1537. { /* WBM2SW_RELEASE */
  1538. .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
  1539. .max_rings = 4,
  1540. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  1541. .lmac_ring = FALSE,
  1542. .ring_dir = HAL_SRNG_DST_RING,
  1543. .reg_start = {
  1544. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1545. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1546. },
  1547. .reg_size = {
  1548. HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
  1549. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1550. HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
  1551. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1552. },
  1553. .max_size =
  1554. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  1555. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  1556. },
  1557. { /* RXDMA_BUF */
  1558. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
  1559. #ifdef IPA_OFFLOAD
  1560. .max_rings = 3,
  1561. #else
  1562. .max_rings = 2,
  1563. #endif
  1564. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1565. .lmac_ring = TRUE,
  1566. .ring_dir = HAL_SRNG_SRC_RING,
  1567. /* reg_start is not set because LMAC rings are not accessed
  1568. * from host
  1569. */
  1570. .reg_start = {},
  1571. .reg_size = {},
  1572. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1573. },
  1574. { /* RXDMA_DST */
  1575. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
  1576. .max_rings = 1,
  1577. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1578. .lmac_ring = TRUE,
  1579. .ring_dir = HAL_SRNG_DST_RING,
  1580. /* reg_start is not set because LMAC rings are not accessed
  1581. * from host
  1582. */
  1583. .reg_start = {},
  1584. .reg_size = {},
  1585. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1586. },
  1587. { /* RXDMA_MONITOR_BUF */
  1588. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
  1589. .max_rings = 1,
  1590. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1591. .lmac_ring = TRUE,
  1592. .ring_dir = HAL_SRNG_SRC_RING,
  1593. /* reg_start is not set because LMAC rings are not accessed
  1594. * from host
  1595. */
  1596. .reg_start = {},
  1597. .reg_size = {},
  1598. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1599. },
  1600. { /* RXDMA_MONITOR_STATUS */
  1601. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
  1602. .max_rings = 1,
  1603. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1604. .lmac_ring = TRUE,
  1605. .ring_dir = HAL_SRNG_SRC_RING,
  1606. /* reg_start is not set because LMAC rings are not accessed
  1607. * from host
  1608. */
  1609. .reg_start = {},
  1610. .reg_size = {},
  1611. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1612. },
  1613. { /* RXDMA_MONITOR_DST */
  1614. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
  1615. .max_rings = 1,
  1616. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1617. .lmac_ring = TRUE,
  1618. .ring_dir = HAL_SRNG_DST_RING,
  1619. /* reg_start is not set because LMAC rings are not accessed
  1620. * from host
  1621. */
  1622. .reg_start = {},
  1623. .reg_size = {},
  1624. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1625. },
  1626. { /* RXDMA_MONITOR_DESC */
  1627. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
  1628. .max_rings = 1,
  1629. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1630. .lmac_ring = TRUE,
  1631. .ring_dir = HAL_SRNG_SRC_RING,
  1632. /* reg_start is not set because LMAC rings are not accessed
  1633. * from host
  1634. */
  1635. .reg_start = {},
  1636. .reg_size = {},
  1637. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1638. },
  1639. { /* DIR_BUF_RX_DMA_SRC */
  1640. .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  1641. .max_rings = 1,
  1642. .entry_size = 2,
  1643. .lmac_ring = TRUE,
  1644. .ring_dir = HAL_SRNG_SRC_RING,
  1645. /* reg_start is not set because LMAC rings are not accessed
  1646. * from host
  1647. */
  1648. .reg_start = {},
  1649. .reg_size = {},
  1650. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1651. },
  1652. #ifdef WLAN_FEATURE_CIF_CFR
  1653. { /* WIFI_POS_SRC */
  1654. .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
  1655. .max_rings = 1,
  1656. .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
  1657. .lmac_ring = TRUE,
  1658. .ring_dir = HAL_SRNG_SRC_RING,
  1659. /* reg_start is not set because LMAC rings are not accessed
  1660. * from host
  1661. */
  1662. .reg_start = {},
  1663. .reg_size = {},
  1664. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1665. },
  1666. #endif
  1667. { /* REO2PPE */ 0},
  1668. { /* PPE2TCL */ 0},
  1669. { /* PPE_RELEASE */ 0},
  1670. { /* TX_MONITOR_BUF */ 0},
  1671. { /* TX_MONITOR_DST */ 0},
  1672. { /* SW2RXDMA_NEW */ 0},
  1673. };
  1674. /**
  1675. * hal_qca8074_attach() - Attach 8074 target specific hal_soc ops,
  1676. * offset and srng table
  1677. */
  1678. void hal_qca8074_attach(struct hal_soc *hal_soc)
  1679. {
  1680. hal_soc->hw_srng_table = hw_srng_table_8074;
  1681. hal_srng_hw_reg_offset_init_generic(hal_soc);
  1682. hal_hw_txrx_default_ops_attach_li(hal_soc);
  1683. hal_hw_txrx_ops_attach_qca8074(hal_soc);
  1684. }