hal_6490.c 75 KB

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  1. /*
  2. * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "qdf_types.h"
  20. #include "qdf_util.h"
  21. #include "qdf_types.h"
  22. #include "qdf_lock.h"
  23. #include "qdf_mem.h"
  24. #include "qdf_nbuf.h"
  25. #include "hal_li_hw_headers.h"
  26. #include "hal_internal.h"
  27. #include "hal_api.h"
  28. #include "target_type.h"
  29. #include "wcss_version.h"
  30. #include "qdf_module.h"
  31. #include "hal_flow.h"
  32. #include "rx_flow_search_entry.h"
  33. #include "hal_rx_flow_info.h"
  34. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
  35. RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET
  36. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
  37. RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK
  38. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
  39. RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB
  40. #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
  41. PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
  42. #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
  43. PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
  44. #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
  45. PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET
  46. #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
  47. PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET
  48. #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
  49. PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET
  50. #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
  51. PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET
  52. #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
  53. PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET
  54. #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
  55. PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET
  56. #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
  57. PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET
  58. #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
  59. PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET
  60. #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
  61. PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
  62. #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
  63. RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET
  64. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  65. RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
  66. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  67. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
  68. #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  69. RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
  70. #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  71. REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
  72. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
  73. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER
  74. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  75. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
  76. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  77. RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
  78. #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  79. TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
  80. #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  81. TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
  82. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
  83. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
  84. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
  85. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
  86. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
  87. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
  88. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
  89. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
  90. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
  91. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
  92. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
  93. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
  94. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
  95. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
  96. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
  97. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
  98. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
  99. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
  100. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
  101. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
  102. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
  103. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
  104. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
  105. WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
  106. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
  107. WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
  108. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
  109. WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
  110. #include "hal_6490_tx.h"
  111. #include "hal_6490_rx.h"
  112. #include <hal_generic_api.h>
  113. #include "hal_li_rx.h"
  114. #include "hal_li_api.h"
  115. #include "hal_li_generic_api.h"
  116. /*
  117. * hal_rx_msdu_start_nss_get_6490(): API to get the NSS
  118. * Interval from rx_msdu_start
  119. *
  120. * @buf: pointer to the start of RX PKT TLV header
  121. * Return: uint32_t(nss)
  122. */
  123. static uint32_t
  124. hal_rx_msdu_start_nss_get_6490(uint8_t *buf)
  125. {
  126. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  127. struct rx_msdu_start *msdu_start =
  128. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  129. uint8_t mimo_ss_bitmap;
  130. mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
  131. return qdf_get_hweight8(mimo_ss_bitmap);
  132. }
  133. /**
  134. * hal_rx_msdu_start_get_len_6490(): API to get the MSDU length
  135. * from rx_msdu_start TLV
  136. *
  137. * @ buf: pointer to the start of RX PKT TLV headers
  138. * Return: (uint32_t)msdu length
  139. */
  140. static uint32_t hal_rx_msdu_start_get_len_6490(uint8_t *buf)
  141. {
  142. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  143. struct rx_msdu_start *msdu_start =
  144. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  145. uint32_t msdu_len;
  146. msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
  147. return msdu_len;
  148. }
  149. /**
  150. * hal_rx_mon_hw_desc_get_mpdu_status_6490(): Retrieve MPDU status
  151. *
  152. * @ hw_desc_addr: Start address of Rx HW TLVs
  153. * @ rs: Status for monitor mode
  154. *
  155. * Return: void
  156. */
  157. static void hal_rx_mon_hw_desc_get_mpdu_status_6490(void *hw_desc_addr,
  158. struct mon_rx_status *rs)
  159. {
  160. struct rx_msdu_start *rx_msdu_start;
  161. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  162. uint32_t reg_value;
  163. const uint32_t sgi_hw_to_cdp[] = {
  164. CDP_SGI_0_8_US,
  165. CDP_SGI_0_4_US,
  166. CDP_SGI_1_6_US,
  167. CDP_SGI_3_2_US,
  168. };
  169. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  170. HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
  171. rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
  172. RX_MSDU_START_5, USER_RSSI);
  173. if (!rs->vht_flags) {
  174. rs->is_stbc = HAL_RX_GET(rx_msdu_start,
  175. RX_MSDU_START_5, STBC);
  176. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
  177. rs->sgi = sgi_hw_to_cdp[reg_value];
  178. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5,
  179. RECEPTION_TYPE);
  180. rs->beamformed =
  181. (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
  182. }
  183. /* TODO: rs->beamformed should be set for SU beamforming also */
  184. }
  185. #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
  186. static uint32_t hal_get_link_desc_size_6490(void)
  187. {
  188. return LINK_DESC_SIZE;
  189. }
  190. /*
  191. * hal_rx_get_tlv_6490(): API to get the tlv
  192. *
  193. * @rx_tlv: TLV data extracted from the rx packet
  194. * Return: uint8_t
  195. */
  196. static uint8_t hal_rx_get_tlv_6490(void *rx_tlv)
  197. {
  198. return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
  199. }
  200. /**
  201. * hal_rx_proc_phyrx_other_receive_info_tlv_6490()
  202. * - process other receive info TLV
  203. * @rx_tlv_hdr: pointer to TLV header
  204. * @ppdu_info: pointer to ppdu_info
  205. *
  206. * Return: None
  207. */
  208. static
  209. void hal_rx_proc_phyrx_other_receive_info_tlv_6490(void *rx_tlv_hdr,
  210. void *ppdu_info_handle)
  211. {
  212. uint32_t tlv_tag, tlv_len;
  213. uint32_t temp_len, other_tlv_len, other_tlv_tag;
  214. void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  215. void *other_tlv_hdr = NULL;
  216. void *other_tlv = NULL;
  217. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  218. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  219. temp_len = 0;
  220. other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
  221. other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
  222. other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
  223. temp_len += other_tlv_len;
  224. other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  225. switch (other_tlv_tag) {
  226. default:
  227. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  228. "%s unhandled TLV type: %d, TLV len:%d",
  229. __func__, other_tlv_tag, other_tlv_len);
  230. break;
  231. }
  232. }
  233. /**
  234. * hal_rx_dump_msdu_start_tlv_6490() : dump RX msdu_start TLV in structured
  235. * human readable format.
  236. * @ msdu_start: pointer the msdu_start TLV in pkt.
  237. * @ dbg_level: log level.
  238. *
  239. * Return: void
  240. */
  241. static void hal_rx_dump_msdu_start_tlv_6490(void *msdustart, uint8_t dbg_level)
  242. {
  243. struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart;
  244. __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
  245. "rx_msdu_start tlv (1/2) - "
  246. "rxpcu_mpdu_filter_in_category: %x "
  247. "sw_frame_group_id: %x "
  248. "phy_ppdu_id: %x "
  249. "msdu_length: %x "
  250. "ipsec_esp: %x "
  251. "l3_offset: %x "
  252. "ipsec_ah: %x "
  253. "l4_offset: %x "
  254. "msdu_number: %x "
  255. "decap_format: %x "
  256. "ipv4_proto: %x "
  257. "ipv6_proto: %x "
  258. "tcp_proto: %x "
  259. "udp_proto: %x "
  260. "ip_frag: %x "
  261. "tcp_only_ack: %x "
  262. "da_is_bcast_mcast: %x "
  263. "ip4_protocol_ip6_next_header: %x "
  264. "toeplitz_hash_2_or_4: %x "
  265. "flow_id_toeplitz: %x "
  266. "user_rssi: %x "
  267. "pkt_type: %x "
  268. "stbc: %x "
  269. "sgi: %x "
  270. "rate_mcs: %x "
  271. "receive_bandwidth: %x "
  272. "reception_type: %x "
  273. "ppdu_start_timestamp: %u ",
  274. msdu_start->rxpcu_mpdu_filter_in_category,
  275. msdu_start->sw_frame_group_id,
  276. msdu_start->phy_ppdu_id,
  277. msdu_start->msdu_length,
  278. msdu_start->ipsec_esp,
  279. msdu_start->l3_offset,
  280. msdu_start->ipsec_ah,
  281. msdu_start->l4_offset,
  282. msdu_start->msdu_number,
  283. msdu_start->decap_format,
  284. msdu_start->ipv4_proto,
  285. msdu_start->ipv6_proto,
  286. msdu_start->tcp_proto,
  287. msdu_start->udp_proto,
  288. msdu_start->ip_frag,
  289. msdu_start->tcp_only_ack,
  290. msdu_start->da_is_bcast_mcast,
  291. msdu_start->ip4_protocol_ip6_next_header,
  292. msdu_start->toeplitz_hash_2_or_4,
  293. msdu_start->flow_id_toeplitz,
  294. msdu_start->user_rssi,
  295. msdu_start->pkt_type,
  296. msdu_start->stbc,
  297. msdu_start->sgi,
  298. msdu_start->rate_mcs,
  299. msdu_start->receive_bandwidth,
  300. msdu_start->reception_type,
  301. msdu_start->ppdu_start_timestamp);
  302. __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
  303. "rx_msdu_start tlv (2/2) - "
  304. "sw_phy_meta_data: %x ",
  305. msdu_start->sw_phy_meta_data);
  306. }
  307. /**
  308. * hal_rx_dump_msdu_end_tlv_6490: dump RX msdu_end TLV in structured
  309. * human readable format.
  310. * @ msdu_end: pointer the msdu_end TLV in pkt.
  311. * @ dbg_level: log level.
  312. *
  313. * Return: void
  314. */
  315. static void hal_rx_dump_msdu_end_tlv_6490(void *msduend,
  316. uint8_t dbg_level)
  317. {
  318. struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend;
  319. __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
  320. "rx_msdu_end tlv (1/3) - "
  321. "rxpcu_mpdu_filter_in_category: %x "
  322. "sw_frame_group_id: %x "
  323. "phy_ppdu_id: %x "
  324. "ip_hdr_chksum: %x "
  325. "tcp_udp_chksum: %x "
  326. "key_id_octet: %x "
  327. "cce_super_rule: %x "
  328. "cce_classify_not_done_truncat: %x "
  329. "cce_classify_not_done_cce_dis: %x "
  330. "ext_wapi_pn_63_48: %x "
  331. "ext_wapi_pn_95_64: %x "
  332. "ext_wapi_pn_127_96: %x "
  333. "reported_mpdu_length: %x "
  334. "first_msdu: %x "
  335. "last_msdu: %x "
  336. "sa_idx_timeout: %x "
  337. "da_idx_timeout: %x "
  338. "msdu_limit_error: %x "
  339. "flow_idx_timeout: %x "
  340. "flow_idx_invalid: %x "
  341. "wifi_parser_error: %x "
  342. "amsdu_parser_error: %x",
  343. msdu_end->rxpcu_mpdu_filter_in_category,
  344. msdu_end->sw_frame_group_id,
  345. msdu_end->phy_ppdu_id,
  346. msdu_end->ip_hdr_chksum,
  347. msdu_end->tcp_udp_chksum,
  348. msdu_end->key_id_octet,
  349. msdu_end->cce_super_rule,
  350. msdu_end->cce_classify_not_done_truncate,
  351. msdu_end->cce_classify_not_done_cce_dis,
  352. msdu_end->ext_wapi_pn_63_48,
  353. msdu_end->ext_wapi_pn_95_64,
  354. msdu_end->ext_wapi_pn_127_96,
  355. msdu_end->reported_mpdu_length,
  356. msdu_end->first_msdu,
  357. msdu_end->last_msdu,
  358. msdu_end->sa_idx_timeout,
  359. msdu_end->da_idx_timeout,
  360. msdu_end->msdu_limit_error,
  361. msdu_end->flow_idx_timeout,
  362. msdu_end->flow_idx_invalid,
  363. msdu_end->wifi_parser_error,
  364. msdu_end->amsdu_parser_error);
  365. __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
  366. "rx_msdu_end tlv (2/3)- "
  367. "sa_is_valid: %x "
  368. "da_is_valid: %x "
  369. "da_is_mcbc: %x "
  370. "l3_header_padding: %x "
  371. "ipv6_options_crc: %x "
  372. "tcp_seq_number: %x "
  373. "tcp_ack_number: %x "
  374. "tcp_flag: %x "
  375. "lro_eligible: %x "
  376. "window_size: %x "
  377. "da_offset: %x "
  378. "sa_offset: %x "
  379. "da_offset_valid: %x "
  380. "sa_offset_valid: %x "
  381. "rule_indication_31_0: %x "
  382. "rule_indication_63_32: %x "
  383. "sa_idx: %x "
  384. "da_idx: %x "
  385. "msdu_drop: %x "
  386. "reo_destination_indication: %x "
  387. "flow_idx: %x "
  388. "fse_metadata: %x "
  389. "cce_metadata: %x "
  390. "sa_sw_peer_id: %x ",
  391. msdu_end->sa_is_valid,
  392. msdu_end->da_is_valid,
  393. msdu_end->da_is_mcbc,
  394. msdu_end->l3_header_padding,
  395. msdu_end->ipv6_options_crc,
  396. msdu_end->tcp_seq_number,
  397. msdu_end->tcp_ack_number,
  398. msdu_end->tcp_flag,
  399. msdu_end->lro_eligible,
  400. msdu_end->window_size,
  401. msdu_end->da_offset,
  402. msdu_end->sa_offset,
  403. msdu_end->da_offset_valid,
  404. msdu_end->sa_offset_valid,
  405. msdu_end->rule_indication_31_0,
  406. msdu_end->rule_indication_63_32,
  407. msdu_end->sa_idx,
  408. msdu_end->da_idx_or_sw_peer_id,
  409. msdu_end->msdu_drop,
  410. msdu_end->reo_destination_indication,
  411. msdu_end->flow_idx,
  412. msdu_end->fse_metadata,
  413. msdu_end->cce_metadata,
  414. msdu_end->sa_sw_peer_id);
  415. __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
  416. "rx_msdu_end tlv (3/3)"
  417. "aggregation_count %x "
  418. "flow_aggregation_continuation %x "
  419. "fisa_timeout %x "
  420. "cumulative_l4_checksum %x "
  421. "cumulative_ip_length %x",
  422. msdu_end->aggregation_count,
  423. msdu_end->flow_aggregation_continuation,
  424. msdu_end->fisa_timeout,
  425. msdu_end->cumulative_l4_checksum,
  426. msdu_end->cumulative_ip_length);
  427. }
  428. /*
  429. * Get tid from RX_MPDU_START
  430. */
  431. #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
  432. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
  433. RX_MPDU_INFO_7_TID_OFFSET)), \
  434. RX_MPDU_INFO_7_TID_MASK, \
  435. RX_MPDU_INFO_7_TID_LSB))
  436. static uint32_t hal_rx_mpdu_start_tid_get_6490(uint8_t *buf)
  437. {
  438. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  439. struct rx_mpdu_start *mpdu_start =
  440. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  441. uint32_t tid;
  442. tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
  443. return tid;
  444. }
  445. #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
  446. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
  447. RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
  448. RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
  449. RX_MSDU_START_5_RECEPTION_TYPE_LSB))
  450. /*
  451. * hal_rx_msdu_start_reception_type_get(): API to get the reception type
  452. * Interval from rx_msdu_start
  453. *
  454. * @buf: pointer to the start of RX PKT TLV header
  455. * Return: uint32_t(reception_type)
  456. */
  457. static
  458. uint32_t hal_rx_msdu_start_reception_type_get_6490(uint8_t *buf)
  459. {
  460. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  461. struct rx_msdu_start *msdu_start =
  462. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  463. uint32_t reception_type;
  464. reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
  465. return reception_type;
  466. }
  467. /**
  468. * hal_rx_msdu_end_da_idx_get_6490: API to get da_idx
  469. * from rx_msdu_end TLV
  470. *
  471. * @ buf: pointer to the start of RX PKT TLV headers
  472. * Return: da index
  473. */
  474. static uint16_t hal_rx_msdu_end_da_idx_get_6490(uint8_t *buf)
  475. {
  476. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  477. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  478. uint16_t da_idx;
  479. da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  480. return da_idx;
  481. }
  482. /**
  483. * hal_rx_get_rx_fragment_number_6490(): Function to retrieve rx fragment number
  484. *
  485. * @nbuf: Network buffer
  486. * Returns: rx fragment number
  487. */
  488. static
  489. uint8_t hal_rx_get_rx_fragment_number_6490(uint8_t *buf)
  490. {
  491. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  492. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  493. /* Return first 4 bits as fragment number */
  494. return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
  495. DOT11_SEQ_FRAG_MASK);
  496. }
  497. /**
  498. * hal_rx_msdu_end_da_is_mcbc_get_6490(): API to check if pkt is MCBC
  499. * from rx_msdu_end TLV
  500. *
  501. * @ buf: pointer to the start of RX PKT TLV headers
  502. * Return: da_is_mcbc
  503. */
  504. static uint8_t
  505. hal_rx_msdu_end_da_is_mcbc_get_6490(uint8_t *buf)
  506. {
  507. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  508. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  509. return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
  510. }
  511. /**
  512. * hal_rx_msdu_end_sa_is_valid_get_6490(): API to get_6490 the
  513. * sa_is_valid bit from rx_msdu_end TLV
  514. *
  515. * @ buf: pointer to the start of RX PKT TLV headers
  516. * Return: sa_is_valid bit
  517. */
  518. static uint8_t
  519. hal_rx_msdu_end_sa_is_valid_get_6490(uint8_t *buf)
  520. {
  521. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  522. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  523. uint8_t sa_is_valid;
  524. sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
  525. return sa_is_valid;
  526. }
  527. /**
  528. * hal_rx_msdu_end_sa_idx_get_6490(): API to get_6490 the
  529. * sa_idx from rx_msdu_end TLV
  530. *
  531. * @ buf: pointer to the start of RX PKT TLV headers
  532. * Return: sa_idx (SA AST index)
  533. */
  534. static
  535. uint16_t hal_rx_msdu_end_sa_idx_get_6490(uint8_t *buf)
  536. {
  537. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  538. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  539. uint16_t sa_idx;
  540. sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
  541. return sa_idx;
  542. }
  543. /**
  544. * hal_rx_desc_is_first_msdu_6490() - Check if first msdu
  545. *
  546. * @hal_soc_hdl: hal_soc handle
  547. * @hw_desc_addr: hardware descriptor address
  548. *
  549. * Return: 0 - success/ non-zero failure
  550. */
  551. static uint32_t hal_rx_desc_is_first_msdu_6490(void *hw_desc_addr)
  552. {
  553. struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
  554. struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
  555. return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU);
  556. }
  557. /**
  558. * hal_rx_msdu_end_l3_hdr_padding_get_6490(): API to get_6490 the
  559. * l3_header padding from rx_msdu_end TLV
  560. *
  561. * @ buf: pointer to the start of RX PKT TLV headers
  562. * Return: number of l3 header padding bytes
  563. */
  564. static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6490(uint8_t *buf)
  565. {
  566. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  567. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  568. uint32_t l3_header_padding;
  569. l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
  570. return l3_header_padding;
  571. }
  572. /*
  573. * @ hal_rx_encryption_info_valid_6490: Returns encryption type.
  574. *
  575. * @ buf: rx_tlv_hdr of the received packet
  576. * @ Return: encryption type
  577. */
  578. static uint32_t hal_rx_encryption_info_valid_6490(uint8_t *buf)
  579. {
  580. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  581. struct rx_mpdu_start *mpdu_start =
  582. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  583. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  584. uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
  585. return encryption_info;
  586. }
  587. /*
  588. * @ hal_rx_print_pn_6490: Prints the PN of rx packet.
  589. *
  590. * @ buf: rx_tlv_hdr of the received packet
  591. * @ Return: void
  592. */
  593. static void hal_rx_print_pn_6490(uint8_t *buf)
  594. {
  595. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  596. struct rx_mpdu_start *mpdu_start =
  597. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  598. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  599. uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
  600. uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
  601. uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
  602. uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
  603. hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ",
  604. pn_127_96, pn_95_64, pn_63_32, pn_31_0);
  605. }
  606. /**
  607. * hal_rx_msdu_end_first_msdu_get_6490: API to get first msdu status
  608. * from rx_msdu_end TLV
  609. *
  610. * @ buf: pointer to the start of RX PKT TLV headers
  611. * Return: first_msdu
  612. */
  613. static uint8_t hal_rx_msdu_end_first_msdu_get_6490(uint8_t *buf)
  614. {
  615. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  616. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  617. uint8_t first_msdu;
  618. first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
  619. return first_msdu;
  620. }
  621. /**
  622. * hal_rx_msdu_end_da_is_valid_get_6490: API to check if da is valid
  623. * from rx_msdu_end TLV
  624. *
  625. * @ buf: pointer to the start of RX PKT TLV headers
  626. * Return: da_is_valid
  627. */
  628. static uint8_t hal_rx_msdu_end_da_is_valid_get_6490(uint8_t *buf)
  629. {
  630. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  631. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  632. uint8_t da_is_valid;
  633. da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
  634. return da_is_valid;
  635. }
  636. /**
  637. * hal_rx_msdu_end_last_msdu_get_6490: API to get last msdu status
  638. * from rx_msdu_end TLV
  639. *
  640. * @ buf: pointer to the start of RX PKT TLV headers
  641. * Return: last_msdu
  642. */
  643. static uint8_t hal_rx_msdu_end_last_msdu_get_6490(uint8_t *buf)
  644. {
  645. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  646. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  647. uint8_t last_msdu;
  648. last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
  649. return last_msdu;
  650. }
  651. /*
  652. * hal_rx_get_mpdu_mac_ad4_valid_6490(): Retrieves if mpdu 4th addr is valid
  653. *
  654. * @nbuf: Network buffer
  655. * Returns: value of mpdu 4th address valid field
  656. */
  657. static bool hal_rx_get_mpdu_mac_ad4_valid_6490(uint8_t *buf)
  658. {
  659. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  660. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  661. bool ad4_valid = 0;
  662. ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info);
  663. return ad4_valid;
  664. }
  665. /**
  666. * hal_rx_mpdu_start_sw_peer_id_get_6490: Retrieve sw peer_id
  667. * @buf: network buffer
  668. *
  669. * Return: sw peer_id
  670. */
  671. static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6490(uint8_t *buf)
  672. {
  673. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  674. struct rx_mpdu_start *mpdu_start =
  675. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  676. return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
  677. &mpdu_start->rx_mpdu_info_details);
  678. }
  679. /**
  680. * hal_rx_mpdu_get_to_ds_6490(): API to get the tods info
  681. * from rx_mpdu_start
  682. *
  683. * @buf: pointer to the start of RX PKT TLV header
  684. * Return: uint32_t(to_ds)
  685. */
  686. static uint32_t hal_rx_mpdu_get_to_ds_6490(uint8_t *buf)
  687. {
  688. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  689. struct rx_mpdu_start *mpdu_start =
  690. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  691. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  692. return HAL_RX_MPDU_GET_TODS(mpdu_info);
  693. }
  694. /*
  695. * hal_rx_mpdu_get_fr_ds_6490(): API to get the from ds info
  696. * from rx_mpdu_start
  697. *
  698. * @buf: pointer to the start of RX PKT TLV header
  699. * Return: uint32_t(fr_ds)
  700. */
  701. static uint32_t hal_rx_mpdu_get_fr_ds_6490(uint8_t *buf)
  702. {
  703. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  704. struct rx_mpdu_start *mpdu_start =
  705. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  706. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  707. return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
  708. }
  709. /*
  710. * hal_rx_get_mpdu_frame_control_valid_6490(): Retrieves mpdu
  711. * frame control valid
  712. *
  713. * @nbuf: Network buffer
  714. * Returns: value of frame control valid field
  715. */
  716. static uint8_t hal_rx_get_mpdu_frame_control_valid_6490(uint8_t *buf)
  717. {
  718. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  719. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  720. return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
  721. }
  722. /*
  723. * hal_rx_mpdu_get_addr1_6490(): API to check get address1 of the mpdu
  724. *
  725. * @buf: pointer to the start of RX PKT TLV headera
  726. * @mac_addr: pointer to mac address
  727. * Return: success/failure
  728. */
  729. static QDF_STATUS hal_rx_mpdu_get_addr1_6490(uint8_t *buf, uint8_t *mac_addr)
  730. {
  731. struct __attribute__((__packed__)) hal_addr1 {
  732. uint32_t ad1_31_0;
  733. uint16_t ad1_47_32;
  734. };
  735. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  736. struct rx_mpdu_start *mpdu_start =
  737. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  738. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  739. struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
  740. uint32_t mac_addr_ad1_valid;
  741. mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
  742. if (mac_addr_ad1_valid) {
  743. addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
  744. addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
  745. return QDF_STATUS_SUCCESS;
  746. }
  747. return QDF_STATUS_E_FAILURE;
  748. }
  749. /*
  750. * hal_rx_mpdu_get_addr2_6490(): API to check get address2 of the mpdu
  751. * in the packet
  752. *
  753. * @buf: pointer to the start of RX PKT TLV header
  754. * @mac_addr: pointer to mac address
  755. * Return: success/failure
  756. */
  757. static QDF_STATUS hal_rx_mpdu_get_addr2_6490(uint8_t *buf,
  758. uint8_t *mac_addr)
  759. {
  760. struct __attribute__((__packed__)) hal_addr2 {
  761. uint16_t ad2_15_0;
  762. uint32_t ad2_47_16;
  763. };
  764. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  765. struct rx_mpdu_start *mpdu_start =
  766. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  767. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  768. struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
  769. uint32_t mac_addr_ad2_valid;
  770. mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
  771. if (mac_addr_ad2_valid) {
  772. addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
  773. addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
  774. return QDF_STATUS_SUCCESS;
  775. }
  776. return QDF_STATUS_E_FAILURE;
  777. }
  778. /*
  779. * hal_rx_mpdu_get_addr3_6490(): API to get address3 of the mpdu
  780. * in the packet
  781. *
  782. * @buf: pointer to the start of RX PKT TLV header
  783. * @mac_addr: pointer to mac address
  784. * Return: success/failure
  785. */
  786. static QDF_STATUS hal_rx_mpdu_get_addr3_6490(uint8_t *buf, uint8_t *mac_addr)
  787. {
  788. struct __attribute__((__packed__)) hal_addr3 {
  789. uint32_t ad3_31_0;
  790. uint16_t ad3_47_32;
  791. };
  792. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  793. struct rx_mpdu_start *mpdu_start =
  794. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  795. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  796. struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
  797. uint32_t mac_addr_ad3_valid;
  798. mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
  799. if (mac_addr_ad3_valid) {
  800. addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
  801. addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
  802. return QDF_STATUS_SUCCESS;
  803. }
  804. return QDF_STATUS_E_FAILURE;
  805. }
  806. /*
  807. * hal_rx_mpdu_get_addr4_6490(): API to get address4 of the mpdu
  808. * in the packet
  809. *
  810. * @buf: pointer to the start of RX PKT TLV header
  811. * @mac_addr: pointer to mac address
  812. * Return: success/failure
  813. */
  814. static QDF_STATUS hal_rx_mpdu_get_addr4_6490(uint8_t *buf, uint8_t *mac_addr)
  815. {
  816. struct __attribute__((__packed__)) hal_addr4 {
  817. uint32_t ad4_31_0;
  818. uint16_t ad4_47_32;
  819. };
  820. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  821. struct rx_mpdu_start *mpdu_start =
  822. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  823. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  824. struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
  825. uint32_t mac_addr_ad4_valid;
  826. mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
  827. if (mac_addr_ad4_valid) {
  828. addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
  829. addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
  830. return QDF_STATUS_SUCCESS;
  831. }
  832. return QDF_STATUS_E_FAILURE;
  833. }
  834. /*
  835. * hal_rx_get_mpdu_sequence_control_valid_6490(): Get mpdu
  836. * sequence control valid
  837. *
  838. * @nbuf: Network buffer
  839. * Returns: value of sequence control valid field
  840. */
  841. static uint8_t hal_rx_get_mpdu_sequence_control_valid_6490(uint8_t *buf)
  842. {
  843. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  844. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  845. return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
  846. }
  847. /**
  848. * hal_rx_is_unicast_6490: check packet is unicast frame or not.
  849. *
  850. * @ buf: pointer to rx pkt TLV.
  851. *
  852. * Return: true on unicast.
  853. */
  854. static bool hal_rx_is_unicast_6490(uint8_t *buf)
  855. {
  856. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  857. struct rx_mpdu_start *mpdu_start =
  858. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  859. uint32_t grp_id;
  860. uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
  861. grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
  862. RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)),
  863. RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK,
  864. RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB));
  865. return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
  866. }
  867. /**
  868. * hal_rx_tid_get_6490: get tid based on qos control valid.
  869. * @hal_soc_hdl: hal_soc handle
  870. * @ buf: pointer to rx pkt TLV.
  871. *
  872. * Return: tid
  873. */
  874. static uint32_t hal_rx_tid_get_6490(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  875. {
  876. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  877. struct rx_mpdu_start *mpdu_start =
  878. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  879. uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
  880. uint8_t qos_control_valid =
  881. (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
  882. RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)),
  883. RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK,
  884. RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB));
  885. if (qos_control_valid)
  886. return hal_rx_mpdu_start_tid_get_6490(buf);
  887. return HAL_RX_NON_QOS_TID;
  888. }
  889. /**
  890. * hal_rx_hw_desc_get_ppduid_get_6490(): retrieve ppdu id
  891. * @rx_tlv_hdr: start address of rx_pkt_tlvs
  892. * @rxdma_dst_ring_desc: Rx HW descriptor
  893. *
  894. * Return: ppdu id
  895. */
  896. static uint32_t hal_rx_hw_desc_get_ppduid_get_6490(void *rx_tlv_hdr,
  897. void *rxdma_dst_ring_desc)
  898. {
  899. struct rx_mpdu_info *rx_mpdu_info;
  900. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
  901. rx_mpdu_info =
  902. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  903. return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID);
  904. }
  905. /**
  906. * hal_reo_status_get_header_6490 - Process reo desc info
  907. * @ring_desc: REO status ring descriptor
  908. * @b - tlv type info
  909. * @h1 - Pointer to hal_reo_status_header where info to be stored
  910. *
  911. * Return - none.
  912. *
  913. */
  914. static void hal_reo_status_get_header_6490(hal_ring_desc_t ring_desc, int b,
  915. void *h1)
  916. {
  917. uint32_t *d = (uint32_t *)ring_desc;
  918. uint32_t val1 = 0;
  919. struct hal_reo_status_header *h =
  920. (struct hal_reo_status_header *)h1;
  921. /* Offsets of descriptor fields defined in HW headers start
  922. * from the field after TLV header
  923. */
  924. d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
  925. switch (b) {
  926. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  927. val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
  928. STATUS_HEADER_REO_STATUS_NUMBER)];
  929. break;
  930. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  931. val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
  932. STATUS_HEADER_REO_STATUS_NUMBER)];
  933. break;
  934. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  935. val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
  936. STATUS_HEADER_REO_STATUS_NUMBER)];
  937. break;
  938. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  939. val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
  940. STATUS_HEADER_REO_STATUS_NUMBER)];
  941. break;
  942. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  943. val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
  944. STATUS_HEADER_REO_STATUS_NUMBER)];
  945. break;
  946. case HAL_REO_DESC_THRES_STATUS_TLV:
  947. val1 =
  948. d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
  949. STATUS_HEADER_REO_STATUS_NUMBER)];
  950. break;
  951. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  952. val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
  953. STATUS_HEADER_REO_STATUS_NUMBER)];
  954. break;
  955. default:
  956. qdf_nofl_err("ERROR: Unknown tlv\n");
  957. break;
  958. }
  959. h->cmd_num =
  960. HAL_GET_FIELD(
  961. UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
  962. val1);
  963. h->exec_time =
  964. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
  965. CMD_EXECUTION_TIME, val1);
  966. h->status =
  967. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
  968. REO_CMD_EXECUTION_STATUS, val1);
  969. switch (b) {
  970. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  971. val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
  972. STATUS_HEADER_TIMESTAMP)];
  973. break;
  974. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  975. val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
  976. STATUS_HEADER_TIMESTAMP)];
  977. break;
  978. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  979. val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
  980. STATUS_HEADER_TIMESTAMP)];
  981. break;
  982. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  983. val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
  984. STATUS_HEADER_TIMESTAMP)];
  985. break;
  986. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  987. val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
  988. STATUS_HEADER_TIMESTAMP)];
  989. break;
  990. case HAL_REO_DESC_THRES_STATUS_TLV:
  991. val1 =
  992. d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
  993. STATUS_HEADER_TIMESTAMP)];
  994. break;
  995. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  996. val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
  997. STATUS_HEADER_TIMESTAMP)];
  998. break;
  999. default:
  1000. qdf_nofl_err("ERROR: Unknown tlv\n");
  1001. break;
  1002. }
  1003. h->tstamp =
  1004. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
  1005. }
  1006. /**
  1007. * hal_tx_desc_set_mesh_en_6490 - Set mesh_enable flag in Tx descriptor
  1008. * @desc: Handle to Tx Descriptor
  1009. * @en: For raw WiFi frames, this indicates transmission to a mesh STA,
  1010. * enabling the interpretation of the 'Mesh Control Present' bit
  1011. * (bit 8) of QoS Control (otherwise this bit is ignored),
  1012. * For native WiFi frames, this indicates that a 'Mesh Control' field
  1013. * is present between the header and the LLC.
  1014. *
  1015. * Return: void
  1016. */
  1017. static inline
  1018. void hal_tx_desc_set_mesh_en_6490(void *desc, uint8_t en)
  1019. {
  1020. HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |=
  1021. HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en);
  1022. }
  1023. static
  1024. void *hal_rx_msdu0_buffer_addr_lsb_6490(void *link_desc_va)
  1025. {
  1026. return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
  1027. }
  1028. static
  1029. void *hal_rx_msdu_desc_info_ptr_get_6490(void *msdu0)
  1030. {
  1031. return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
  1032. }
  1033. static
  1034. void *hal_ent_mpdu_desc_info_6490(void *ent_ring_desc)
  1035. {
  1036. return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
  1037. }
  1038. static
  1039. void *hal_dst_mpdu_desc_info_6490(void *dst_ring_desc)
  1040. {
  1041. return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
  1042. }
  1043. static
  1044. uint8_t hal_rx_get_fc_valid_6490(uint8_t *buf)
  1045. {
  1046. return HAL_RX_GET_FC_VALID(buf);
  1047. }
  1048. static uint8_t hal_rx_get_to_ds_flag_6490(uint8_t *buf)
  1049. {
  1050. return HAL_RX_GET_TO_DS_FLAG(buf);
  1051. }
  1052. static uint8_t hal_rx_get_mac_addr2_valid_6490(uint8_t *buf)
  1053. {
  1054. return HAL_RX_GET_MAC_ADDR2_VALID(buf);
  1055. }
  1056. static uint8_t hal_rx_get_filter_category_6490(uint8_t *buf)
  1057. {
  1058. return HAL_RX_GET_FILTER_CATEGORY(buf);
  1059. }
  1060. static uint32_t
  1061. hal_rx_get_ppdu_id_6490(uint8_t *buf)
  1062. {
  1063. return HAL_RX_GET_PPDU_ID(buf);
  1064. }
  1065. /**
  1066. * hal_reo_config_6490(): Set reo config parameters
  1067. * @soc: hal soc handle
  1068. * @reg_val: value to be set
  1069. * @reo_params: reo parameters
  1070. *
  1071. * Return: void
  1072. */
  1073. static
  1074. void hal_reo_config_6490(struct hal_soc *soc,
  1075. uint32_t reg_val,
  1076. struct hal_reo_params *reo_params)
  1077. {
  1078. HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
  1079. }
  1080. /**
  1081. * hal_rx_msdu_desc_info_get_ptr_6490() - Get msdu desc info ptr
  1082. * @msdu_details_ptr - Pointer to msdu_details_ptr
  1083. *
  1084. * Return - Pointer to rx_msdu_desc_info structure.
  1085. *
  1086. */
  1087. static void *hal_rx_msdu_desc_info_get_ptr_6490(void *msdu_details_ptr)
  1088. {
  1089. return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
  1090. }
  1091. /**
  1092. * hal_rx_link_desc_msdu0_ptr_6490 - Get pointer to rx_msdu details
  1093. * @link_desc - Pointer to link desc
  1094. *
  1095. * Return - Pointer to rx_msdu_details structure
  1096. *
  1097. */
  1098. static void *hal_rx_link_desc_msdu0_ptr_6490(void *link_desc)
  1099. {
  1100. return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
  1101. }
  1102. /**
  1103. * hal_rx_msdu_flow_idx_get_6490: API to get flow index
  1104. * from rx_msdu_end TLV
  1105. * @buf: pointer to the start of RX PKT TLV headers
  1106. *
  1107. * Return: flow index value from MSDU END TLV
  1108. */
  1109. static inline uint32_t hal_rx_msdu_flow_idx_get_6490(uint8_t *buf)
  1110. {
  1111. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1112. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1113. return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
  1114. }
  1115. /**
  1116. * hal_rx_msdu_get_reo_destination_indication_6490: API to get
  1117. * reo_destination_indication from rx_msdu_end TLV
  1118. * @buf: pointer to the start of RX PKT TLV headers
  1119. * @reo_destination_indication: pointer to return value of reo_destination_indication
  1120. *
  1121. * Return: none
  1122. */
  1123. static inline void
  1124. hal_rx_msdu_get_reo_destination_indication_6490(uint8_t *buf,
  1125. uint32_t *reo_destination_indication)
  1126. {
  1127. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1128. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1129. *reo_destination_indication = HAL_RX_MSDU_END_REO_DEST_IND_GET(msdu_end);
  1130. }
  1131. /**
  1132. * hal_rx_msdu_flow_idx_invalid_6490: API to get flow index invalid
  1133. * from rx_msdu_end TLV
  1134. * @buf: pointer to the start of RX PKT TLV headers
  1135. *
  1136. * Return: flow index invalid value from MSDU END TLV
  1137. */
  1138. static bool hal_rx_msdu_flow_idx_invalid_6490(uint8_t *buf)
  1139. {
  1140. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1141. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1142. return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
  1143. }
  1144. /**
  1145. * hal_rx_msdu_flow_idx_timeout_6490: API to get flow index timeout
  1146. * from rx_msdu_end TLV
  1147. * @buf: pointer to the start of RX PKT TLV headers
  1148. *
  1149. * Return: flow index timeout value from MSDU END TLV
  1150. */
  1151. static bool hal_rx_msdu_flow_idx_timeout_6490(uint8_t *buf)
  1152. {
  1153. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1154. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1155. return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
  1156. }
  1157. /**
  1158. * hal_rx_msdu_fse_metadata_get_6490: API to get FSE metadata
  1159. * from rx_msdu_end TLV
  1160. * @buf: pointer to the start of RX PKT TLV headers
  1161. *
  1162. * Return: fse metadata value from MSDU END TLV
  1163. */
  1164. static uint32_t hal_rx_msdu_fse_metadata_get_6490(uint8_t *buf)
  1165. {
  1166. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1167. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1168. return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
  1169. }
  1170. /**
  1171. * hal_rx_msdu_cce_metadata_get_6490: API to get CCE metadata
  1172. * from rx_msdu_end TLV
  1173. * @buf: pointer to the start of RX PKT TLV headers
  1174. *
  1175. * Return: cce_metadata
  1176. */
  1177. static uint16_t
  1178. hal_rx_msdu_cce_metadata_get_6490(uint8_t *buf)
  1179. {
  1180. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1181. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1182. return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
  1183. }
  1184. /**
  1185. * hal_rx_msdu_get_flow_params_6490: API to get flow index, flow index invalid
  1186. * and flow index timeout from rx_msdu_end TLV
  1187. * @buf: pointer to the start of RX PKT TLV headers
  1188. * @flow_invalid: pointer to return value of flow_idx_valid
  1189. * @flow_timeout: pointer to return value of flow_idx_timeout
  1190. * @flow_index: pointer to return value of flow_idx
  1191. *
  1192. * Return: none
  1193. */
  1194. static inline void
  1195. hal_rx_msdu_get_flow_params_6490(uint8_t *buf,
  1196. bool *flow_invalid,
  1197. bool *flow_timeout,
  1198. uint32_t *flow_index)
  1199. {
  1200. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1201. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1202. *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
  1203. *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
  1204. *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
  1205. }
  1206. /**
  1207. * hal_rx_tlv_get_tcp_chksum_6490() - API to get tcp checksum
  1208. * @buf: rx_tlv_hdr
  1209. *
  1210. * Return: tcp checksum
  1211. */
  1212. static uint16_t
  1213. hal_rx_tlv_get_tcp_chksum_6490(uint8_t *buf)
  1214. {
  1215. return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
  1216. }
  1217. /**
  1218. * hal_rx_get_rx_sequence_6490(): Function to retrieve rx sequence number
  1219. *
  1220. * @nbuf: Network buffer
  1221. * Returns: rx sequence number
  1222. */
  1223. static
  1224. uint16_t hal_rx_get_rx_sequence_6490(uint8_t *buf)
  1225. {
  1226. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  1227. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  1228. return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
  1229. }
  1230. /**
  1231. * hal_get_window_address_6490(): Function to get hp/tp address
  1232. * @hal_soc: Pointer to hal_soc
  1233. * @addr: address offset of register
  1234. *
  1235. * Return: modified address offset of register
  1236. */
  1237. static inline qdf_iomem_t hal_get_window_address_6490(struct hal_soc *hal_soc,
  1238. qdf_iomem_t addr)
  1239. {
  1240. return addr;
  1241. }
  1242. /**
  1243. * hal_rx_get_fisa_cumulative_l4_checksum_6490() - Retrieve cumulative
  1244. * checksum
  1245. * @buf: buffer pointer
  1246. *
  1247. * Return: cumulative checksum
  1248. */
  1249. static inline
  1250. uint16_t hal_rx_get_fisa_cumulative_l4_checksum_6490(uint8_t *buf)
  1251. {
  1252. return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf);
  1253. }
  1254. /**
  1255. * hal_rx_get_fisa_cumulative_ip_length_6490() - Retrieve cumulative
  1256. * ip length
  1257. * @buf: buffer pointer
  1258. *
  1259. * Return: cumulative length
  1260. */
  1261. static inline
  1262. uint16_t hal_rx_get_fisa_cumulative_ip_length_6490(uint8_t *buf)
  1263. {
  1264. return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf);
  1265. }
  1266. /**
  1267. * hal_rx_get_udp_proto_6490() - Retrieve udp proto value
  1268. * @buf: buffer
  1269. *
  1270. * Return: udp proto bit
  1271. */
  1272. static inline
  1273. bool hal_rx_get_udp_proto_6490(uint8_t *buf)
  1274. {
  1275. return HAL_RX_TLV_GET_UDP_PROTO(buf);
  1276. }
  1277. /**
  1278. * hal_rx_get_flow_agg_continuation_6490() - retrieve flow agg
  1279. * continuation
  1280. * @buf: buffer
  1281. *
  1282. * Return: flow agg
  1283. */
  1284. static inline
  1285. bool hal_rx_get_flow_agg_continuation_6490(uint8_t *buf)
  1286. {
  1287. return HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf);
  1288. }
  1289. /**
  1290. * hal_rx_get_flow_agg_count_6490()- Retrieve flow agg count
  1291. * @buf: buffer
  1292. *
  1293. * Return: flow agg count
  1294. */
  1295. static inline
  1296. uint8_t hal_rx_get_flow_agg_count_6490(uint8_t *buf)
  1297. {
  1298. return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf);
  1299. }
  1300. /**
  1301. * hal_rx_get_fisa_timeout_6490() - Retrieve fisa timeout
  1302. * @buf: buffer
  1303. *
  1304. * Return: fisa timeout
  1305. */
  1306. static inline
  1307. bool hal_rx_get_fisa_timeout_6490(uint8_t *buf)
  1308. {
  1309. return HAL_RX_TLV_GET_FISA_TIMEOUT(buf);
  1310. }
  1311. /**
  1312. * hal_rx_mpdu_start_tlv_tag_valid_6490 () - API to check if RX_MPDU_START
  1313. * tlv tag is valid
  1314. *
  1315. *@rx_tlv_hdr: start address of rx_pkt_tlvs
  1316. *
  1317. * Return: true if RX_MPDU_START is valied, else false.
  1318. */
  1319. static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6490(void *rx_tlv_hdr)
  1320. {
  1321. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
  1322. uint32_t tlv_tag;
  1323. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv);
  1324. return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
  1325. }
  1326. /**
  1327. * hal_reo_set_err_dst_remap_6490(): Function to set REO error destination
  1328. * ring remap register
  1329. * @hal_soc: Pointer to hal_soc
  1330. *
  1331. * Return: none.
  1332. */
  1333. static void
  1334. hal_reo_set_err_dst_remap_6490(void *hal_soc)
  1335. {
  1336. /*
  1337. * Set REO error 2k jump (error code 5) / OOR (error code 7)
  1338. * frame routed to REO2TCL ring.
  1339. */
  1340. uint32_t dst_remap_ix0 =
  1341. HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) |
  1342. HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) |
  1343. HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) |
  1344. HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) |
  1345. HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) |
  1346. HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) |
  1347. HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) |
  1348. HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7);
  1349. uint32_t dst_remap_ix1 =
  1350. HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 14) |
  1351. HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 13) |
  1352. HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 12) |
  1353. HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 11) |
  1354. HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 10) |
  1355. HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 9) |
  1356. HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8);
  1357. HAL_REG_WRITE(hal_soc,
  1358. HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
  1359. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1360. dst_remap_ix0);
  1361. hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x",
  1362. HAL_REG_READ(
  1363. hal_soc,
  1364. HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
  1365. SEQ_WCSS_UMAC_REO_REG_OFFSET)));
  1366. HAL_REG_WRITE(hal_soc,
  1367. HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(
  1368. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1369. dst_remap_ix1);
  1370. hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x",
  1371. HAL_REG_READ(
  1372. hal_soc,
  1373. HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(
  1374. SEQ_WCSS_UMAC_REO_REG_OFFSET)));
  1375. }
  1376. /**
  1377. * hal_rx_flow_setup_fse_6490() - Setup a flow search entry in HW FST
  1378. * @fst: Pointer to the Rx Flow Search Table
  1379. * @table_offset: offset into the table where the flow is to be setup
  1380. * @flow: Flow Parameters
  1381. *
  1382. * Flow table entry fields are updated in host byte order, little endian order.
  1383. *
  1384. * Return: Success/Failure
  1385. */
  1386. static void *
  1387. hal_rx_flow_setup_fse_6490(uint8_t *rx_fst, uint32_t table_offset,
  1388. uint8_t *rx_flow)
  1389. {
  1390. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  1391. struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
  1392. uint8_t *fse;
  1393. bool fse_valid;
  1394. if (table_offset >= fst->max_entries) {
  1395. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1396. "HAL FSE table offset %u exceeds max entries %u",
  1397. table_offset, fst->max_entries);
  1398. return NULL;
  1399. }
  1400. fse = (uint8_t *)fst->base_vaddr +
  1401. (table_offset * HAL_RX_FST_ENTRY_SIZE);
  1402. fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
  1403. if (fse_valid) {
  1404. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1405. "HAL FSE %pK already valid", fse);
  1406. return NULL;
  1407. }
  1408. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) =
  1409. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96,
  1410. (flow->tuple_info.src_ip_127_96));
  1411. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) =
  1412. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64,
  1413. (flow->tuple_info.src_ip_95_64));
  1414. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) =
  1415. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32,
  1416. (flow->tuple_info.src_ip_63_32));
  1417. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) =
  1418. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0,
  1419. (flow->tuple_info.src_ip_31_0));
  1420. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) =
  1421. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96,
  1422. (flow->tuple_info.dest_ip_127_96));
  1423. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) =
  1424. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64,
  1425. (flow->tuple_info.dest_ip_95_64));
  1426. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) =
  1427. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32,
  1428. (flow->tuple_info.dest_ip_63_32));
  1429. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) =
  1430. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0,
  1431. (flow->tuple_info.dest_ip_31_0));
  1432. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT);
  1433. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |=
  1434. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT,
  1435. (flow->tuple_info.dest_port));
  1436. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT);
  1437. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |=
  1438. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT,
  1439. (flow->tuple_info.src_port));
  1440. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL);
  1441. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |=
  1442. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL,
  1443. flow->tuple_info.l4_protocol);
  1444. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER);
  1445. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |=
  1446. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER,
  1447. flow->reo_destination_handler);
  1448. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
  1449. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |=
  1450. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1);
  1451. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA);
  1452. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) =
  1453. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA,
  1454. (flow->fse_metadata));
  1455. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION);
  1456. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |=
  1457. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9,
  1458. REO_DESTINATION_INDICATION,
  1459. flow->reo_destination_indication);
  1460. /* Reset all the other fields in FSE */
  1461. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9);
  1462. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP);
  1463. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT);
  1464. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT);
  1465. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP);
  1466. return fse;
  1467. }
  1468. static
  1469. void hal_compute_reo_remap_ix2_ix3_6490(uint32_t *ring, uint32_t num_rings,
  1470. uint32_t *remap1, uint32_t *remap2)
  1471. {
  1472. switch (num_rings) {
  1473. case 3:
  1474. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1475. HAL_REO_REMAP_IX2(ring[1], 17) |
  1476. HAL_REO_REMAP_IX2(ring[2], 18) |
  1477. HAL_REO_REMAP_IX2(ring[0], 19) |
  1478. HAL_REO_REMAP_IX2(ring[1], 20) |
  1479. HAL_REO_REMAP_IX2(ring[2], 21) |
  1480. HAL_REO_REMAP_IX2(ring[0], 22) |
  1481. HAL_REO_REMAP_IX2(ring[1], 23);
  1482. *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
  1483. HAL_REO_REMAP_IX3(ring[0], 25) |
  1484. HAL_REO_REMAP_IX3(ring[1], 26) |
  1485. HAL_REO_REMAP_IX3(ring[2], 27) |
  1486. HAL_REO_REMAP_IX3(ring[0], 28) |
  1487. HAL_REO_REMAP_IX3(ring[1], 29) |
  1488. HAL_REO_REMAP_IX3(ring[2], 30) |
  1489. HAL_REO_REMAP_IX3(ring[0], 31);
  1490. break;
  1491. case 4:
  1492. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  1493. HAL_REO_REMAP_IX2(ring[1], 17) |
  1494. HAL_REO_REMAP_IX2(ring[2], 18) |
  1495. HAL_REO_REMAP_IX2(ring[3], 19) |
  1496. HAL_REO_REMAP_IX2(ring[0], 20) |
  1497. HAL_REO_REMAP_IX2(ring[1], 21) |
  1498. HAL_REO_REMAP_IX2(ring[2], 22) |
  1499. HAL_REO_REMAP_IX2(ring[3], 23);
  1500. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  1501. HAL_REO_REMAP_IX3(ring[1], 25) |
  1502. HAL_REO_REMAP_IX3(ring[2], 26) |
  1503. HAL_REO_REMAP_IX3(ring[3], 27) |
  1504. HAL_REO_REMAP_IX3(ring[0], 28) |
  1505. HAL_REO_REMAP_IX3(ring[1], 29) |
  1506. HAL_REO_REMAP_IX3(ring[2], 30) |
  1507. HAL_REO_REMAP_IX3(ring[3], 31);
  1508. break;
  1509. }
  1510. }
  1511. static
  1512. void hal_compute_reo_remap_ix0_6490(uint32_t *remap0)
  1513. {
  1514. *remap0 = HAL_REO_REMAP_IX0(REO_REMAP_SW1, 0) |
  1515. HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) |
  1516. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) |
  1517. HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) |
  1518. HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) |
  1519. HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) |
  1520. HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) |
  1521. HAL_REO_REMAP_IX0(REO_REMAP_FW, 7);
  1522. }
  1523. #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
  1524. /**
  1525. * hal_get_first_wow_wakeup_packet_6490(): Function to retrieve
  1526. * rx_msdu_end_1_reserved_1a
  1527. *
  1528. * reserved_1a is used by target to tag the first packet that wakes up host from
  1529. * WoW
  1530. *
  1531. * @buf: Network buffer
  1532. *
  1533. * Returns: 1 to indicate it is first packet received that wakes up host from
  1534. * WoW. Otherwise 0
  1535. */
  1536. static uint8_t hal_get_first_wow_wakeup_packet_6490(uint8_t *buf)
  1537. {
  1538. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  1539. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1540. return HAL_RX_MSDU_END_RESERVED_1A_GET(msdu_end);
  1541. }
  1542. #endif
  1543. /**
  1544. * hal_rx_tlv_l3_type_get_6490(): Function to retrieve l3_type
  1545. *
  1546. * @buf: Network buffer
  1547. *
  1548. * Returns: l3_type
  1549. */
  1550. static uint32_t hal_rx_tlv_l3_type_get_6490(uint8_t *buf)
  1551. {
  1552. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  1553. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1554. return HAL_RX_MSDU_END_L3_TYPE_GET(msdu_end);
  1555. }
  1556. static void hal_hw_txrx_ops_attach_qca6490(struct hal_soc *hal_soc)
  1557. {
  1558. /* init and setup */
  1559. hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
  1560. hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
  1561. hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
  1562. hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
  1563. hal_soc->ops->hal_get_window_address = hal_get_window_address_6490;
  1564. hal_soc->ops->hal_reo_set_err_dst_remap =
  1565. hal_reo_set_err_dst_remap_6490;
  1566. /* tx */
  1567. hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
  1568. hal_tx_desc_set_dscp_tid_table_id_6490;
  1569. hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6490;
  1570. hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6490;
  1571. hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6490;
  1572. hal_soc->ops->hal_tx_desc_set_buf_addr =
  1573. hal_tx_desc_set_buf_addr_generic_li;
  1574. hal_soc->ops->hal_tx_desc_set_search_type =
  1575. hal_tx_desc_set_search_type_generic_li;
  1576. hal_soc->ops->hal_tx_desc_set_search_index =
  1577. hal_tx_desc_set_search_index_generic_li;
  1578. hal_soc->ops->hal_tx_desc_set_cache_set_num =
  1579. hal_tx_desc_set_cache_set_num_generic_li;
  1580. hal_soc->ops->hal_tx_comp_get_status =
  1581. hal_tx_comp_get_status_generic_li;
  1582. hal_soc->ops->hal_tx_comp_get_release_reason =
  1583. hal_tx_comp_get_release_reason_generic_li;
  1584. hal_soc->ops->hal_get_wbm_internal_error =
  1585. hal_get_wbm_internal_error_generic_li;
  1586. hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6490;
  1587. hal_soc->ops->hal_tx_init_cmd_credit_ring =
  1588. hal_tx_init_cmd_credit_ring_6490;
  1589. /* rx */
  1590. hal_soc->ops->hal_rx_msdu_start_nss_get =
  1591. hal_rx_msdu_start_nss_get_6490;
  1592. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
  1593. hal_rx_mon_hw_desc_get_mpdu_status_6490;
  1594. hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6490;
  1595. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
  1596. hal_rx_proc_phyrx_other_receive_info_tlv_6490;
  1597. hal_soc->ops->hal_rx_dump_msdu_start_tlv =
  1598. hal_rx_dump_msdu_start_tlv_6490;
  1599. hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6490;
  1600. hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6490;
  1601. hal_soc->ops->hal_rx_mpdu_start_tid_get =
  1602. hal_rx_mpdu_start_tid_get_6490;
  1603. hal_soc->ops->hal_rx_msdu_start_reception_type_get =
  1604. hal_rx_msdu_start_reception_type_get_6490;
  1605. hal_soc->ops->hal_rx_msdu_end_da_idx_get =
  1606. hal_rx_msdu_end_da_idx_get_6490;
  1607. hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
  1608. hal_rx_msdu_desc_info_get_ptr_6490;
  1609. hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
  1610. hal_rx_link_desc_msdu0_ptr_6490;
  1611. hal_soc->ops->hal_reo_status_get_header =
  1612. hal_reo_status_get_header_6490;
  1613. hal_soc->ops->hal_rx_status_get_tlv_info =
  1614. hal_rx_status_get_tlv_info_generic_li;
  1615. hal_soc->ops->hal_rx_wbm_err_info_get =
  1616. hal_rx_wbm_err_info_get_generic_li;
  1617. hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
  1618. hal_rx_dump_mpdu_start_tlv_generic_li;
  1619. hal_soc->ops->hal_tx_set_pcp_tid_map =
  1620. hal_tx_set_pcp_tid_map_generic_li;
  1621. hal_soc->ops->hal_tx_update_pcp_tid_map =
  1622. hal_tx_update_pcp_tid_generic_li;
  1623. hal_soc->ops->hal_tx_set_tidmap_prty =
  1624. hal_tx_update_tidmap_prty_generic_li;
  1625. hal_soc->ops->hal_rx_get_rx_fragment_number =
  1626. hal_rx_get_rx_fragment_number_6490;
  1627. hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
  1628. hal_rx_msdu_end_da_is_mcbc_get_6490;
  1629. hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
  1630. hal_rx_msdu_end_sa_is_valid_get_6490;
  1631. hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
  1632. hal_rx_msdu_end_sa_idx_get_6490;
  1633. hal_soc->ops->hal_rx_desc_is_first_msdu =
  1634. hal_rx_desc_is_first_msdu_6490;
  1635. hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
  1636. hal_rx_msdu_end_l3_hdr_padding_get_6490;
  1637. hal_soc->ops->hal_rx_encryption_info_valid =
  1638. hal_rx_encryption_info_valid_6490;
  1639. hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6490;
  1640. hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
  1641. hal_rx_msdu_end_first_msdu_get_6490;
  1642. hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
  1643. hal_rx_msdu_end_da_is_valid_get_6490;
  1644. hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
  1645. hal_rx_msdu_end_last_msdu_get_6490;
  1646. hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
  1647. hal_rx_get_mpdu_mac_ad4_valid_6490;
  1648. hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
  1649. hal_rx_mpdu_start_sw_peer_id_get_6490;
  1650. hal_soc->ops->hal_rx_mpdu_peer_meta_data_get =
  1651. hal_rx_mpdu_peer_meta_data_get_li;
  1652. hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6490;
  1653. hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6490;
  1654. hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
  1655. hal_rx_get_mpdu_frame_control_valid_6490;
  1656. hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6490;
  1657. hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6490;
  1658. hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6490;
  1659. hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6490;
  1660. hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
  1661. hal_rx_get_mpdu_sequence_control_valid_6490;
  1662. hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6490;
  1663. hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6490;
  1664. hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
  1665. hal_rx_hw_desc_get_ppduid_get_6490;
  1666. hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
  1667. hal_rx_msdu0_buffer_addr_lsb_6490;
  1668. hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
  1669. hal_rx_msdu_desc_info_ptr_get_6490;
  1670. hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6490;
  1671. hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6490;
  1672. hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6490;
  1673. hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6490;
  1674. hal_soc->ops->hal_rx_get_mac_addr2_valid =
  1675. hal_rx_get_mac_addr2_valid_6490;
  1676. hal_soc->ops->hal_rx_get_filter_category =
  1677. hal_rx_get_filter_category_6490;
  1678. hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6490;
  1679. hal_soc->ops->hal_reo_config = hal_reo_config_6490;
  1680. hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6490;
  1681. hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
  1682. hal_rx_msdu_flow_idx_invalid_6490;
  1683. hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
  1684. hal_rx_msdu_flow_idx_timeout_6490;
  1685. hal_soc->ops->hal_rx_msdu_fse_metadata_get =
  1686. hal_rx_msdu_fse_metadata_get_6490;
  1687. hal_soc->ops->hal_rx_msdu_cce_match_get =
  1688. hal_rx_msdu_cce_match_get_li;
  1689. hal_soc->ops->hal_rx_msdu_cce_metadata_get =
  1690. hal_rx_msdu_cce_metadata_get_6490;
  1691. hal_soc->ops->hal_rx_msdu_get_flow_params =
  1692. hal_rx_msdu_get_flow_params_6490;
  1693. hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
  1694. hal_rx_tlv_get_tcp_chksum_6490;
  1695. hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6490;
  1696. #if defined(QCA_WIFI_QCA6490) && defined(WLAN_CFR_ENABLE) && \
  1697. defined(WLAN_ENH_CFR_ENABLE)
  1698. hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6490;
  1699. hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6490;
  1700. #endif
  1701. /* rx - msdu end fast path info fields */
  1702. hal_soc->ops->hal_rx_msdu_packet_metadata_get =
  1703. hal_rx_msdu_packet_metadata_get_generic_li;
  1704. hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum =
  1705. hal_rx_get_fisa_cumulative_l4_checksum_6490;
  1706. hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length =
  1707. hal_rx_get_fisa_cumulative_ip_length_6490;
  1708. hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6490;
  1709. hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation =
  1710. hal_rx_get_flow_agg_continuation_6490;
  1711. hal_soc->ops->hal_rx_get_fisa_flow_agg_count =
  1712. hal_rx_get_flow_agg_count_6490;
  1713. hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6490;
  1714. hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
  1715. hal_rx_mpdu_start_tlv_tag_valid_6490;
  1716. /* rx - TLV struct offsets */
  1717. hal_soc->ops->hal_rx_msdu_end_offset_get =
  1718. hal_rx_msdu_end_offset_get_generic;
  1719. hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
  1720. hal_soc->ops->hal_rx_msdu_start_offset_get =
  1721. hal_rx_msdu_start_offset_get_generic;
  1722. hal_soc->ops->hal_rx_mpdu_start_offset_get =
  1723. hal_rx_mpdu_start_offset_get_generic;
  1724. hal_soc->ops->hal_rx_mpdu_end_offset_get =
  1725. hal_rx_mpdu_end_offset_get_generic;
  1726. #ifndef NO_RX_PKT_HDR_TLV
  1727. hal_soc->ops->hal_rx_pkt_tlv_offset_get =
  1728. hal_rx_pkt_tlv_offset_get_generic;
  1729. #endif
  1730. hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6490;
  1731. hal_soc->ops->hal_rx_flow_get_tuple_info =
  1732. hal_rx_flow_get_tuple_info_li;
  1733. hal_soc->ops->hal_rx_flow_delete_entry =
  1734. hal_rx_flow_delete_entry_li;
  1735. hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li;
  1736. hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
  1737. hal_compute_reo_remap_ix2_ix3_6490;
  1738. hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
  1739. hal_rx_msdu_get_reo_destination_indication_6490;
  1740. hal_soc->ops->hal_setup_link_idle_list =
  1741. hal_setup_link_idle_list_generic_li;
  1742. #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
  1743. hal_soc->ops->hal_get_first_wow_wakeup_packet =
  1744. hal_get_first_wow_wakeup_packet_6490;
  1745. #endif
  1746. hal_soc->ops->hal_compute_reo_remap_ix0 =
  1747. hal_compute_reo_remap_ix0_6490;
  1748. hal_soc->ops->hal_rx_tlv_l3_type_get =
  1749. hal_rx_tlv_l3_type_get_6490;
  1750. hal_soc->ops->hal_rx_tlv_msdu_len_get =
  1751. hal_rx_msdu_start_get_len_6490;
  1752. };
  1753. struct hal_hw_srng_config hw_srng_table_6490[] = {
  1754. /* TODO: max_rings can populated by querying HW capabilities */
  1755. { /* REO_DST */
  1756. .start_ring_id = HAL_SRNG_REO2SW1,
  1757. .max_rings = 4,
  1758. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1759. .lmac_ring = FALSE,
  1760. .ring_dir = HAL_SRNG_DST_RING,
  1761. .reg_start = {
  1762. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
  1763. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1764. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
  1765. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1766. },
  1767. .reg_size = {
  1768. HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
  1769. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
  1770. HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
  1771. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
  1772. },
  1773. .max_size =
  1774. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1775. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
  1776. },
  1777. { /* REO_EXCEPTION */
  1778. /* Designating REO2TCL ring as exception ring. This ring is
  1779. * similar to other REO2SW rings though it is named as REO2TCL.
  1780. * Any of theREO2SW rings can be used as exception ring.
  1781. */
  1782. .start_ring_id = HAL_SRNG_REO2TCL,
  1783. .max_rings = 1,
  1784. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1785. .lmac_ring = FALSE,
  1786. .ring_dir = HAL_SRNG_DST_RING,
  1787. .reg_start = {
  1788. HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
  1789. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1790. HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
  1791. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1792. },
  1793. /* Single ring - provide ring size if multiple rings of this
  1794. * type are supported
  1795. */
  1796. .reg_size = {},
  1797. .max_size =
  1798. HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
  1799. HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
  1800. },
  1801. { /* REO_REINJECT */
  1802. .start_ring_id = HAL_SRNG_SW2REO,
  1803. .max_rings = 1,
  1804. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1805. .lmac_ring = FALSE,
  1806. .ring_dir = HAL_SRNG_SRC_RING,
  1807. .reg_start = {
  1808. HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
  1809. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1810. HWIO_REO_R2_SW2REO_RING_HP_ADDR(
  1811. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1812. },
  1813. /* Single ring - provide ring size if multiple rings of this
  1814. * type are supported
  1815. */
  1816. .reg_size = {},
  1817. .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
  1818. HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
  1819. },
  1820. { /* REO_CMD */
  1821. .start_ring_id = HAL_SRNG_REO_CMD,
  1822. .max_rings = 1,
  1823. .entry_size = (sizeof(struct tlv_32_hdr) +
  1824. sizeof(struct reo_get_queue_stats)) >> 2,
  1825. .lmac_ring = FALSE,
  1826. .ring_dir = HAL_SRNG_SRC_RING,
  1827. .reg_start = {
  1828. HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
  1829. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1830. HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
  1831. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1832. },
  1833. /* Single ring - provide ring size if multiple rings of this
  1834. * type are supported
  1835. */
  1836. .reg_size = {},
  1837. .max_size =
  1838. HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
  1839. HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
  1840. },
  1841. { /* REO_STATUS */
  1842. .start_ring_id = HAL_SRNG_REO_STATUS,
  1843. .max_rings = 1,
  1844. .entry_size = (sizeof(struct tlv_32_hdr) +
  1845. sizeof(struct reo_get_queue_stats_status)) >> 2,
  1846. .lmac_ring = FALSE,
  1847. .ring_dir = HAL_SRNG_DST_RING,
  1848. .reg_start = {
  1849. HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
  1850. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1851. HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
  1852. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1853. },
  1854. /* Single ring - provide ring size if multiple rings of this
  1855. * type are supported
  1856. */
  1857. .reg_size = {},
  1858. .max_size =
  1859. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1860. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1861. },
  1862. { /* TCL_DATA */
  1863. .start_ring_id = HAL_SRNG_SW2TCL1,
  1864. .max_rings = 3,
  1865. .entry_size = (sizeof(struct tlv_32_hdr) +
  1866. sizeof(struct tcl_data_cmd)) >> 2,
  1867. .lmac_ring = FALSE,
  1868. .ring_dir = HAL_SRNG_SRC_RING,
  1869. .reg_start = {
  1870. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
  1871. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1872. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
  1873. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1874. },
  1875. .reg_size = {
  1876. HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
  1877. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
  1878. HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
  1879. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
  1880. },
  1881. .max_size =
  1882. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1883. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
  1884. },
  1885. { /* TCL_CMD */
  1886. .start_ring_id = HAL_SRNG_SW2TCL_CMD,
  1887. .max_rings = 1,
  1888. .entry_size = (sizeof(struct tlv_32_hdr) +
  1889. sizeof(struct tcl_gse_cmd)) >> 2,
  1890. .lmac_ring = FALSE,
  1891. .ring_dir = HAL_SRNG_SRC_RING,
  1892. .reg_start = {
  1893. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
  1894. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1895. HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
  1896. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1897. },
  1898. /* Single ring - provide ring size if multiple rings of this
  1899. * type are supported
  1900. */
  1901. .reg_size = {},
  1902. .max_size =
  1903. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
  1904. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
  1905. },
  1906. { /* TCL_STATUS */
  1907. .start_ring_id = HAL_SRNG_TCL_STATUS,
  1908. .max_rings = 1,
  1909. .entry_size = (sizeof(struct tlv_32_hdr) +
  1910. sizeof(struct tcl_status_ring)) >> 2,
  1911. .lmac_ring = FALSE,
  1912. .ring_dir = HAL_SRNG_DST_RING,
  1913. .reg_start = {
  1914. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
  1915. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1916. HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
  1917. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1918. },
  1919. /* Single ring - provide ring size if multiple rings of this
  1920. * type are supported
  1921. */
  1922. .reg_size = {},
  1923. .max_size =
  1924. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1925. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
  1926. },
  1927. { /* CE_SRC */
  1928. .start_ring_id = HAL_SRNG_CE_0_SRC,
  1929. .max_rings = 12,
  1930. .entry_size = sizeof(struct ce_src_desc) >> 2,
  1931. .lmac_ring = FALSE,
  1932. .ring_dir = HAL_SRNG_SRC_RING,
  1933. .reg_start = {
  1934. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1935. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
  1936. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1937. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
  1938. },
  1939. .reg_size = {
  1940. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
  1941. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
  1942. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
  1943. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
  1944. },
  1945. .max_size =
  1946. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1947. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1948. },
  1949. { /* CE_DST */
  1950. .start_ring_id = HAL_SRNG_CE_0_DST,
  1951. .max_rings = 12,
  1952. .entry_size = 8 >> 2,
  1953. /*TODO: entry_size above should actually be
  1954. * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
  1955. * of struct ce_dst_desc in HW header files
  1956. */
  1957. .lmac_ring = FALSE,
  1958. .ring_dir = HAL_SRNG_SRC_RING,
  1959. .reg_start = {
  1960. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1961. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1962. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1963. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1964. },
  1965. .reg_size = {
  1966. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1967. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1968. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1969. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1970. },
  1971. .max_size =
  1972. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1973. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1974. },
  1975. { /* CE_DST_STATUS */
  1976. .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
  1977. .max_rings = 12,
  1978. .entry_size = sizeof(struct ce_stat_desc) >> 2,
  1979. .lmac_ring = FALSE,
  1980. .ring_dir = HAL_SRNG_DST_RING,
  1981. .reg_start = {
  1982. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
  1983. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1984. HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
  1985. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1986. },
  1987. /* TODO: check destination status ring registers */
  1988. .reg_size = {
  1989. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1990. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1991. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1992. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1993. },
  1994. .max_size =
  1995. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1996. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1997. },
  1998. { /* WBM_IDLE_LINK */
  1999. .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
  2000. .max_rings = 1,
  2001. .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
  2002. .lmac_ring = FALSE,
  2003. .ring_dir = HAL_SRNG_SRC_RING,
  2004. .reg_start = {
  2005. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2006. HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2007. },
  2008. /* Single ring - provide ring size if multiple rings of this
  2009. * type are supported
  2010. */
  2011. .reg_size = {},
  2012. .max_size =
  2013. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
  2014. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
  2015. },
  2016. { /* SW2WBM_RELEASE */
  2017. .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
  2018. .max_rings = 1,
  2019. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  2020. .lmac_ring = FALSE,
  2021. .ring_dir = HAL_SRNG_SRC_RING,
  2022. .reg_start = {
  2023. HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2024. HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2025. },
  2026. /* Single ring - provide ring size if multiple rings of this
  2027. * type are supported
  2028. */
  2029. .reg_size = {},
  2030. .max_size =
  2031. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  2032. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  2033. },
  2034. { /* WBM2SW_RELEASE */
  2035. .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
  2036. #if defined(IPA_WDI3_TX_TWO_PIPES) || defined(TX_MULTI_TCL) || \
  2037. defined(CONFIG_PLD_PCIE_FW_SIM)
  2038. .max_rings = 5,
  2039. #else
  2040. .max_rings = 4,
  2041. #endif
  2042. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  2043. .lmac_ring = FALSE,
  2044. .ring_dir = HAL_SRNG_DST_RING,
  2045. .reg_start = {
  2046. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2047. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2048. },
  2049. .reg_size = {
  2050. HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
  2051. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2052. HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
  2053. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  2054. },
  2055. .max_size =
  2056. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  2057. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  2058. },
  2059. { /* RXDMA_BUF */
  2060. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
  2061. #ifdef IPA_OFFLOAD
  2062. .max_rings = 3,
  2063. #else
  2064. .max_rings = 2,
  2065. #endif
  2066. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  2067. .lmac_ring = TRUE,
  2068. .ring_dir = HAL_SRNG_SRC_RING,
  2069. /* reg_start is not set because LMAC rings are not accessed
  2070. * from host
  2071. */
  2072. .reg_start = {},
  2073. .reg_size = {},
  2074. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2075. },
  2076. { /* RXDMA_DST */
  2077. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
  2078. .max_rings = 1,
  2079. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  2080. .lmac_ring = TRUE,
  2081. .ring_dir = HAL_SRNG_DST_RING,
  2082. /* reg_start is not set because LMAC rings are not accessed
  2083. * from host
  2084. */
  2085. .reg_start = {},
  2086. .reg_size = {},
  2087. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2088. },
  2089. { /* RXDMA_MONITOR_BUF */
  2090. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
  2091. .max_rings = 1,
  2092. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  2093. .lmac_ring = TRUE,
  2094. .ring_dir = HAL_SRNG_SRC_RING,
  2095. /* reg_start is not set because LMAC rings are not accessed
  2096. * from host
  2097. */
  2098. .reg_start = {},
  2099. .reg_size = {},
  2100. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2101. },
  2102. { /* RXDMA_MONITOR_STATUS */
  2103. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
  2104. .max_rings = 1,
  2105. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  2106. .lmac_ring = TRUE,
  2107. .ring_dir = HAL_SRNG_SRC_RING,
  2108. /* reg_start is not set because LMAC rings are not accessed
  2109. * from host
  2110. */
  2111. .reg_start = {},
  2112. .reg_size = {},
  2113. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2114. },
  2115. { /* RXDMA_MONITOR_DST */
  2116. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
  2117. .max_rings = 1,
  2118. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  2119. .lmac_ring = TRUE,
  2120. .ring_dir = HAL_SRNG_DST_RING,
  2121. /* reg_start is not set because LMAC rings are not accessed
  2122. * from host
  2123. */
  2124. .reg_start = {},
  2125. .reg_size = {},
  2126. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2127. },
  2128. { /* RXDMA_MONITOR_DESC */
  2129. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
  2130. .max_rings = 1,
  2131. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  2132. .lmac_ring = TRUE,
  2133. .ring_dir = HAL_SRNG_SRC_RING,
  2134. /* reg_start is not set because LMAC rings are not accessed
  2135. * from host
  2136. */
  2137. .reg_start = {},
  2138. .reg_size = {},
  2139. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2140. },
  2141. { /* DIR_BUF_RX_DMA_SRC */
  2142. .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  2143. /*
  2144. * one ring is for spectral scan
  2145. * the other is for cfr
  2146. */
  2147. .max_rings = 2,
  2148. .entry_size = 2,
  2149. .lmac_ring = TRUE,
  2150. .ring_dir = HAL_SRNG_SRC_RING,
  2151. /* reg_start is not set because LMAC rings are not accessed
  2152. * from host
  2153. */
  2154. .reg_start = {},
  2155. .reg_size = {},
  2156. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2157. },
  2158. #ifdef WLAN_FEATURE_CIF_CFR
  2159. { /* WIFI_POS_SRC */
  2160. .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
  2161. .max_rings = 1,
  2162. .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
  2163. .lmac_ring = TRUE,
  2164. .ring_dir = HAL_SRNG_SRC_RING,
  2165. /* reg_start is not set because LMAC rings are not accessed
  2166. * from host
  2167. */
  2168. .reg_start = {},
  2169. .reg_size = {},
  2170. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2171. },
  2172. #endif
  2173. { /* REO2PPE */ 0},
  2174. { /* PPE2TCL */ 0},
  2175. { /* PPE_RELEASE */ 0},
  2176. { /* TX_MONITOR_BUF */ 0},
  2177. { /* TX_MONITOR_DST */ 0},
  2178. { /* SW2RXDMA_NEW */ 0},
  2179. };
  2180. /**
  2181. * hal_qca6490_attach() - Attach 6490 target specific hal_soc ops,
  2182. * offset and srng table
  2183. */
  2184. void hal_qca6490_attach(struct hal_soc *hal_soc)
  2185. {
  2186. hal_soc->hw_srng_table = hw_srng_table_6490;
  2187. hal_srng_hw_reg_offset_init_generic(hal_soc);
  2188. hal_hw_txrx_default_ops_attach_li(hal_soc);
  2189. hal_hw_txrx_ops_attach_qca6490(hal_soc);
  2190. }