hal_5332_rx.h 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109
  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifndef _HAL_5332_RX_H_
  18. #define _HAL_5332_RX_H_
  19. #include "qdf_util.h"
  20. #include "qdf_types.h"
  21. #include "qdf_lock.h"
  22. #include "qdf_mem.h"
  23. #include "qdf_nbuf.h"
  24. #include "tcl_data_cmd.h"
  25. #include "phyrx_rssi_legacy.h"
  26. #include "rx_msdu_start.h"
  27. #include "tlv_tag_def.h"
  28. #include "hal_hw_headers.h"
  29. #include "hal_internal.h"
  30. #include "cdp_txrx_mon_struct.h"
  31. #include "qdf_trace.h"
  32. #include "hal_rx.h"
  33. #include "hal_tx.h"
  34. #include "dp_types.h"
  35. #include "hal_api_mon.h"
  36. #include "phyrx_other_receive_info_ru_details.h"
  37. #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
  38. (uint8_t *)(link_desc_va) + \
  39. RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  40. #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
  41. (uint8_t *)(msdu0) + \
  42. RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  43. #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
  44. (uint8_t *)(ent_ring_desc) + \
  45. RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  46. #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
  47. (uint8_t *)(dst_ring_desc) + \
  48. REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  49. #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
  50. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID)
  51. #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
  52. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID)
  53. #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
  54. do { \
  55. reg_val &= \
  56. ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\
  57. HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
  58. reg_val |= \
  59. HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
  60. AGING_LIST_ENABLE, 1) | \
  61. HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
  62. AGING_FLUSH_ENABLE, 1); \
  63. HAL_REG_WRITE(soc, \
  64. HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
  65. REO_REG_REG_BASE), \
  66. reg_val); \
  67. reg_val = HAL_REG_READ(soc, \
  68. HWIO_REO_R0_MISC_CTL_ADDR( \
  69. REO_REG_REG_BASE)); \
  70. reg_val &= ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
  71. reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL, \
  72. FRAGMENT_DEST_RING, \
  73. (reo_params)->frag_dst_ring); \
  74. } while (0)
  75. #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
  76. ((struct rx_msdu_desc_info *) \
  77. _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
  78. UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
  79. #define HAL_RX_TLV_MSDU_DONE_COPY_GET(_rx_pkt_tlv) \
  80. HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done_copy
  81. #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
  82. ((struct rx_msdu_details *) \
  83. _OFFSET_TO_BYTE_PTR((link_desc),\
  84. RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET))
  85. #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
  86. #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK 0x00000006
  87. #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB 1
  88. #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_MSB 2
  89. #define HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv) \
  90. ((HAL_RX_GET((rx_tlv), \
  91. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, \
  92. RTT_CFR_STATUS) & \
  93. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK) >> \
  94. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB)
  95. #endif
  96. #endif