hal_5018.c 73 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "hal_li_hw_headers.h"
  20. #include "hal_internal.h"
  21. #include "hal_api.h"
  22. #include "target_type.h"
  23. #include "wcss_version.h"
  24. #include "qdf_module.h"
  25. #include "hal_flow.h"
  26. #include "rx_flow_search_entry.h"
  27. #include "hal_rx_flow_info.h"
  28. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
  29. RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET
  30. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
  31. RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK
  32. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
  33. RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB
  34. #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \
  35. RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET
  36. #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \
  37. RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK
  38. #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \
  39. RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB
  40. #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
  41. PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET
  42. #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
  43. PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
  44. #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
  45. PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET
  46. #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
  47. PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET
  48. #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
  49. PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET
  50. #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
  51. PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET
  52. #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
  53. PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET
  54. #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
  55. PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET
  56. #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
  57. PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET
  58. #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
  59. PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
  60. #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
  61. PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
  62. #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
  63. RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
  64. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  65. RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  66. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  67. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  68. #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  69. RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  70. #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  71. REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  72. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
  73. STATUS_HEADER_REO_STATUS_NUMBER
  74. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
  75. STATUS_HEADER_TIMESTAMP
  76. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  77. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  78. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  79. RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  80. #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  81. TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
  82. #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  83. TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
  84. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
  85. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
  86. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
  87. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
  88. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
  89. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
  90. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
  91. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
  92. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
  93. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
  94. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
  95. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
  96. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
  97. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
  98. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
  99. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
  100. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
  101. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
  102. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
  103. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
  104. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
  105. TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
  106. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
  107. WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
  108. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
  109. WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
  110. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
  111. WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
  112. #define CE_WINDOW_ADDRESS_5018 \
  113. ((WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
  114. #define UMAC_WINDOW_ADDRESS_5018 \
  115. ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
  116. #define WINDOW_CONFIGURATION_VALUE_5018 \
  117. ((CE_WINDOW_ADDRESS_5018 << 6) |\
  118. (UMAC_WINDOW_ADDRESS_5018 << 12) | \
  119. WINDOW_ENABLE_BIT)
  120. #define HOST_CE_MASK_VALUE 0xFF000000
  121. #include "hal_5018_tx.h"
  122. #include "hal_5018_rx.h"
  123. #include <hal_generic_api.h>
  124. #include "hal_li_rx.h"
  125. #include "hal_li_api.h"
  126. #include "hal_li_generic_api.h"
  127. /**
  128. * hal_rx_msdu_start_nss_get_5018(): API to get the NSS
  129. * Interval from rx_msdu_start
  130. *
  131. * @buf: pointer to the start of RX PKT TLV header
  132. * Return: uint32_t(nss)
  133. */
  134. static uint32_t hal_rx_msdu_start_nss_get_5018(uint8_t *buf)
  135. {
  136. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  137. struct rx_msdu_start *msdu_start =
  138. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  139. uint8_t mimo_ss_bitmap;
  140. mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
  141. return qdf_get_hweight8(mimo_ss_bitmap);
  142. }
  143. /**
  144. * hal_rx_msdu_start_get_len_5018(): API to get the MSDU length
  145. * from rx_msdu_start TLV
  146. *
  147. * @ buf: pointer to the start of RX PKT TLV headers
  148. * Return: (uint32_t)msdu length
  149. */
  150. static uint32_t hal_rx_msdu_start_get_len_5018(uint8_t *buf)
  151. {
  152. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  153. struct rx_msdu_start *msdu_start =
  154. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  155. uint32_t msdu_len;
  156. msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
  157. return msdu_len;
  158. }
  159. /**
  160. * hal_rx_mon_hw_desc_get_mpdu_status_5018(): Retrieve MPDU status
  161. *
  162. * @ hw_desc_addr: Start address of Rx HW TLVs
  163. * @ rs: Status for monitor mode
  164. *
  165. * Return: void
  166. */
  167. static void hal_rx_mon_hw_desc_get_mpdu_status_5018(void *hw_desc_addr,
  168. struct mon_rx_status *rs)
  169. {
  170. struct rx_msdu_start *rx_msdu_start;
  171. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  172. uint32_t reg_value;
  173. const uint32_t sgi_hw_to_cdp[] = {
  174. CDP_SGI_0_8_US,
  175. CDP_SGI_0_4_US,
  176. CDP_SGI_1_6_US,
  177. CDP_SGI_3_2_US,
  178. };
  179. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  180. HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
  181. rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
  182. RX_MSDU_START_5, USER_RSSI);
  183. rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
  184. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
  185. rs->sgi = sgi_hw_to_cdp[reg_value];
  186. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
  187. rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
  188. /* TODO: rs->beamformed should be set for SU beamforming also */
  189. }
  190. #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
  191. /**
  192. * hal_get_link_desc_size_5018(): API to get the link desc size
  193. *
  194. * Return: uint32_t
  195. */
  196. static uint32_t hal_get_link_desc_size_5018(void)
  197. {
  198. return LINK_DESC_SIZE;
  199. }
  200. /**
  201. * hal_rx_get_tlv_5018(): API to get the tlv
  202. *
  203. * @rx_tlv: TLV data extracted from the rx packet
  204. * Return: uint8_t
  205. */
  206. static uint8_t hal_rx_get_tlv_5018(void *rx_tlv)
  207. {
  208. return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
  209. }
  210. /**
  211. * hal_rx_mpdu_start_tlv_tag_valid_5018 () - API to check if RX_MPDU_START
  212. * tlv tag is valid
  213. *
  214. *@rx_tlv_hdr: start address of rx_pkt_tlvs
  215. *
  216. * Return: true if RX_MPDU_START is valied, else false.
  217. */
  218. uint8_t hal_rx_mpdu_start_tlv_tag_valid_5018(void *rx_tlv_hdr)
  219. {
  220. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
  221. uint32_t tlv_tag;
  222. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv);
  223. return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
  224. }
  225. /**
  226. * hal_rx_wbm_err_msdu_continuation_get_5018 () - API to check if WBM
  227. * msdu continuation bit is set
  228. *
  229. *@wbm_desc: wbm release ring descriptor
  230. *
  231. * Return: true if msdu continuation bit is set.
  232. */
  233. uint8_t hal_rx_wbm_err_msdu_continuation_get_5018(void *wbm_desc)
  234. {
  235. uint32_t comp_desc =
  236. *(uint32_t *)(((uint8_t *)wbm_desc) +
  237. WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET);
  238. return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >>
  239. WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB;
  240. }
  241. static
  242. void hal_compute_reo_remap_ix2_ix3_5018(uint32_t *ring, uint32_t num_rings,
  243. uint32_t *remap1, uint32_t *remap2)
  244. {
  245. switch (num_rings) {
  246. case 1:
  247. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  248. HAL_REO_REMAP_IX2(ring[0], 17) |
  249. HAL_REO_REMAP_IX2(ring[0], 18) |
  250. HAL_REO_REMAP_IX2(ring[0], 19) |
  251. HAL_REO_REMAP_IX2(ring[0], 20) |
  252. HAL_REO_REMAP_IX2(ring[0], 21) |
  253. HAL_REO_REMAP_IX2(ring[0], 22) |
  254. HAL_REO_REMAP_IX2(ring[0], 23);
  255. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  256. HAL_REO_REMAP_IX3(ring[0], 25) |
  257. HAL_REO_REMAP_IX3(ring[0], 26) |
  258. HAL_REO_REMAP_IX3(ring[0], 27) |
  259. HAL_REO_REMAP_IX3(ring[0], 28) |
  260. HAL_REO_REMAP_IX3(ring[0], 29) |
  261. HAL_REO_REMAP_IX3(ring[0], 30) |
  262. HAL_REO_REMAP_IX3(ring[0], 31);
  263. break;
  264. case 2:
  265. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  266. HAL_REO_REMAP_IX2(ring[0], 17) |
  267. HAL_REO_REMAP_IX2(ring[1], 18) |
  268. HAL_REO_REMAP_IX2(ring[1], 19) |
  269. HAL_REO_REMAP_IX2(ring[0], 20) |
  270. HAL_REO_REMAP_IX2(ring[0], 21) |
  271. HAL_REO_REMAP_IX2(ring[1], 22) |
  272. HAL_REO_REMAP_IX2(ring[1], 23);
  273. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  274. HAL_REO_REMAP_IX3(ring[0], 25) |
  275. HAL_REO_REMAP_IX3(ring[1], 26) |
  276. HAL_REO_REMAP_IX3(ring[1], 27) |
  277. HAL_REO_REMAP_IX3(ring[0], 28) |
  278. HAL_REO_REMAP_IX3(ring[0], 29) |
  279. HAL_REO_REMAP_IX3(ring[1], 30) |
  280. HAL_REO_REMAP_IX3(ring[1], 31);
  281. break;
  282. case 3:
  283. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  284. HAL_REO_REMAP_IX2(ring[1], 17) |
  285. HAL_REO_REMAP_IX2(ring[2], 18) |
  286. HAL_REO_REMAP_IX2(ring[0], 19) |
  287. HAL_REO_REMAP_IX2(ring[1], 20) |
  288. HAL_REO_REMAP_IX2(ring[2], 21) |
  289. HAL_REO_REMAP_IX2(ring[0], 22) |
  290. HAL_REO_REMAP_IX2(ring[1], 23);
  291. *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
  292. HAL_REO_REMAP_IX3(ring[0], 25) |
  293. HAL_REO_REMAP_IX3(ring[1], 26) |
  294. HAL_REO_REMAP_IX3(ring[2], 27) |
  295. HAL_REO_REMAP_IX3(ring[0], 28) |
  296. HAL_REO_REMAP_IX3(ring[1], 29) |
  297. HAL_REO_REMAP_IX3(ring[2], 30) |
  298. HAL_REO_REMAP_IX3(ring[0], 31);
  299. break;
  300. case 4:
  301. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  302. HAL_REO_REMAP_IX2(ring[1], 17) |
  303. HAL_REO_REMAP_IX2(ring[2], 18) |
  304. HAL_REO_REMAP_IX2(ring[3], 19) |
  305. HAL_REO_REMAP_IX2(ring[0], 20) |
  306. HAL_REO_REMAP_IX2(ring[1], 21) |
  307. HAL_REO_REMAP_IX2(ring[2], 22) |
  308. HAL_REO_REMAP_IX2(ring[3], 23);
  309. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  310. HAL_REO_REMAP_IX3(ring[1], 25) |
  311. HAL_REO_REMAP_IX3(ring[2], 26) |
  312. HAL_REO_REMAP_IX3(ring[3], 27) |
  313. HAL_REO_REMAP_IX3(ring[0], 28) |
  314. HAL_REO_REMAP_IX3(ring[1], 29) |
  315. HAL_REO_REMAP_IX3(ring[2], 30) |
  316. HAL_REO_REMAP_IX3(ring[3], 31);
  317. break;
  318. }
  319. }
  320. /**
  321. * hal_rx_proc_phyrx_other_receive_info_tlv_5018(): API to get tlv info
  322. *
  323. * Return: uint32_t
  324. */
  325. static inline
  326. void hal_rx_proc_phyrx_other_receive_info_tlv_5018(void *rx_tlv_hdr,
  327. void *ppdu_info_hdl)
  328. {
  329. }
  330. #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
  331. static inline
  332. void hal_rx_get_bb_info_5018(void *rx_tlv,
  333. void *ppdu_info_hdl)
  334. {
  335. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  336. ppdu_info->cfr_info.bb_captured_channel =
  337. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL);
  338. ppdu_info->cfr_info.bb_captured_timeout =
  339. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT);
  340. ppdu_info->cfr_info.bb_captured_reason =
  341. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON);
  342. }
  343. static inline
  344. void hal_rx_get_rtt_info_5018(void *rx_tlv,
  345. void *ppdu_info_hdl)
  346. {
  347. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  348. ppdu_info->cfr_info.rx_location_info_valid =
  349. HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS,
  350. RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID);
  351. ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
  352. HAL_RX_GET(rx_tlv,
  353. PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
  354. RTT_CHE_BUFFER_POINTER_LOW32);
  355. ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
  356. HAL_RX_GET(rx_tlv,
  357. PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
  358. RTT_CHE_BUFFER_POINTER_HIGH8);
  359. ppdu_info->cfr_info.chan_capture_status =
  360. HAL_RX_GET(rx_tlv,
  361. PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
  362. RESERVED_8);
  363. }
  364. #endif
  365. /**
  366. * hal_rx_dump_msdu_start_tlv_5018() : dump RX msdu_start TLV in structured
  367. * human readable format.
  368. * @ msdu_start: pointer the msdu_start TLV in pkt.
  369. * @ dbg_level: log level.
  370. *
  371. * Return: void
  372. */
  373. static void hal_rx_dump_msdu_start_tlv_5018(void *msdustart,
  374. uint8_t dbg_level)
  375. {
  376. struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart;
  377. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  378. "rx_msdu_start tlv - "
  379. "rxpcu_mpdu_filter_in_category: %d "
  380. "sw_frame_group_id: %d "
  381. "phy_ppdu_id: %d "
  382. "msdu_length: %d "
  383. "ipsec_esp: %d "
  384. "l3_offset: %d "
  385. "ipsec_ah: %d "
  386. "l4_offset: %d "
  387. "msdu_number: %d "
  388. "decap_format: %d "
  389. "ipv4_proto: %d "
  390. "ipv6_proto: %d "
  391. "tcp_proto: %d "
  392. "udp_proto: %d "
  393. "ip_frag: %d "
  394. "tcp_only_ack: %d "
  395. "da_is_bcast_mcast: %d "
  396. "ip4_protocol_ip6_next_header: %d "
  397. "toeplitz_hash_2_or_4: %d "
  398. "flow_id_toeplitz: %d "
  399. "user_rssi: %d "
  400. "pkt_type: %d "
  401. "stbc: %d "
  402. "sgi: %d "
  403. "rate_mcs: %d "
  404. "receive_bandwidth: %d "
  405. "reception_type: %d "
  406. "ppdu_start_timestamp: %d "
  407. "sw_phy_meta_data: %d ",
  408. msdu_start->rxpcu_mpdu_filter_in_category,
  409. msdu_start->sw_frame_group_id,
  410. msdu_start->phy_ppdu_id,
  411. msdu_start->msdu_length,
  412. msdu_start->ipsec_esp,
  413. msdu_start->l3_offset,
  414. msdu_start->ipsec_ah,
  415. msdu_start->l4_offset,
  416. msdu_start->msdu_number,
  417. msdu_start->decap_format,
  418. msdu_start->ipv4_proto,
  419. msdu_start->ipv6_proto,
  420. msdu_start->tcp_proto,
  421. msdu_start->udp_proto,
  422. msdu_start->ip_frag,
  423. msdu_start->tcp_only_ack,
  424. msdu_start->da_is_bcast_mcast,
  425. msdu_start->ip4_protocol_ip6_next_header,
  426. msdu_start->toeplitz_hash_2_or_4,
  427. msdu_start->flow_id_toeplitz,
  428. msdu_start->user_rssi,
  429. msdu_start->pkt_type,
  430. msdu_start->stbc,
  431. msdu_start->sgi,
  432. msdu_start->rate_mcs,
  433. msdu_start->receive_bandwidth,
  434. msdu_start->reception_type,
  435. msdu_start->ppdu_start_timestamp,
  436. msdu_start->sw_phy_meta_data);
  437. }
  438. /**
  439. * hal_rx_dump_msdu_end_tlv_5018: dump RX msdu_end TLV in structured
  440. * human readable format.
  441. * @ msdu_end: pointer the msdu_end TLV in pkt.
  442. * @ dbg_level: log level.
  443. *
  444. * Return: void
  445. */
  446. static void hal_rx_dump_msdu_end_tlv_5018(void *msduend,
  447. uint8_t dbg_level)
  448. {
  449. struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend;
  450. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  451. "rx_msdu_end tlv - "
  452. "rxpcu_mpdu_filter_in_category: %d "
  453. "sw_frame_group_id: %d "
  454. "phy_ppdu_id: %d "
  455. "ip_hdr_chksum: %d "
  456. "reported_mpdu_length: %d "
  457. "key_id_octet: %d "
  458. "cce_super_rule: %d "
  459. "cce_classify_not_done_truncat: %d "
  460. "cce_classify_not_done_cce_dis: %d "
  461. "rule_indication_31_0: %d "
  462. "rule_indication_63_32: %d "
  463. "da_offset: %d "
  464. "sa_offset: %d "
  465. "da_offset_valid: %d "
  466. "sa_offset_valid: %d "
  467. "ipv6_options_crc: %d "
  468. "tcp_seq_number: %d "
  469. "tcp_ack_number: %d "
  470. "tcp_flag: %d "
  471. "lro_eligible: %d "
  472. "window_size: %d "
  473. "tcp_udp_chksum: %d "
  474. "sa_idx_timeout: %d "
  475. "da_idx_timeout: %d "
  476. "msdu_limit_error: %d "
  477. "flow_idx_timeout: %d "
  478. "flow_idx_invalid: %d "
  479. "wifi_parser_error: %d "
  480. "amsdu_parser_error: %d "
  481. "sa_is_valid: %d "
  482. "da_is_valid: %d "
  483. "da_is_mcbc: %d "
  484. "l3_header_padding: %d "
  485. "first_msdu: %d "
  486. "last_msdu: %d "
  487. "sa_idx: %d "
  488. "msdu_drop: %d "
  489. "reo_destination_indication: %d "
  490. "flow_idx: %d "
  491. "fse_metadata: %d "
  492. "cce_metadata: %d "
  493. "sa_sw_peer_id: %d ",
  494. msdu_end->rxpcu_mpdu_filter_in_category,
  495. msdu_end->sw_frame_group_id,
  496. msdu_end->phy_ppdu_id,
  497. msdu_end->ip_hdr_chksum,
  498. msdu_end->reported_mpdu_length,
  499. msdu_end->key_id_octet,
  500. msdu_end->cce_super_rule,
  501. msdu_end->cce_classify_not_done_truncate,
  502. msdu_end->cce_classify_not_done_cce_dis,
  503. msdu_end->rule_indication_31_0,
  504. msdu_end->rule_indication_63_32,
  505. msdu_end->da_offset,
  506. msdu_end->sa_offset,
  507. msdu_end->da_offset_valid,
  508. msdu_end->sa_offset_valid,
  509. msdu_end->ipv6_options_crc,
  510. msdu_end->tcp_seq_number,
  511. msdu_end->tcp_ack_number,
  512. msdu_end->tcp_flag,
  513. msdu_end->lro_eligible,
  514. msdu_end->window_size,
  515. msdu_end->tcp_udp_chksum,
  516. msdu_end->sa_idx_timeout,
  517. msdu_end->da_idx_timeout,
  518. msdu_end->msdu_limit_error,
  519. msdu_end->flow_idx_timeout,
  520. msdu_end->flow_idx_invalid,
  521. msdu_end->wifi_parser_error,
  522. msdu_end->amsdu_parser_error,
  523. msdu_end->sa_is_valid,
  524. msdu_end->da_is_valid,
  525. msdu_end->da_is_mcbc,
  526. msdu_end->l3_header_padding,
  527. msdu_end->first_msdu,
  528. msdu_end->last_msdu,
  529. msdu_end->sa_idx,
  530. msdu_end->msdu_drop,
  531. msdu_end->reo_destination_indication,
  532. msdu_end->flow_idx,
  533. msdu_end->fse_metadata,
  534. msdu_end->cce_metadata,
  535. msdu_end->sa_sw_peer_id);
  536. }
  537. /**
  538. * hal_rx_mpdu_start_tid_get_5018(): API to get tid
  539. * from rx_msdu_start
  540. *
  541. * @buf: pointer to the start of RX PKT TLV header
  542. * Return: uint32_t(tid value)
  543. */
  544. static uint32_t hal_rx_mpdu_start_tid_get_5018(uint8_t *buf)
  545. {
  546. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  547. struct rx_mpdu_start *mpdu_start =
  548. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  549. uint32_t tid;
  550. tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
  551. return tid;
  552. }
  553. /**
  554. * hal_rx_msdu_start_reception_type_get(): API to get the reception type
  555. * Interval from rx_msdu_start
  556. *
  557. * @buf: pointer to the start of RX PKT TLV header
  558. * Return: uint32_t(reception_type)
  559. */
  560. static uint32_t hal_rx_msdu_start_reception_type_get_5018(uint8_t *buf)
  561. {
  562. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  563. struct rx_msdu_start *msdu_start =
  564. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  565. uint32_t reception_type;
  566. reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
  567. return reception_type;
  568. }
  569. /**
  570. * hal_rx_msdu_end_da_idx_get_5018: API to get da_idx
  571. * from rx_msdu_end TLV
  572. *
  573. * @ buf: pointer to the start of RX PKT TLV headers
  574. * Return: da index
  575. */
  576. static uint16_t hal_rx_msdu_end_da_idx_get_5018(uint8_t *buf)
  577. {
  578. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  579. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  580. uint16_t da_idx;
  581. da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  582. return da_idx;
  583. }
  584. /**
  585. * hal_rx_get_rx_fragment_number_5018(): Function to retrieve rx fragment number
  586. *
  587. * @nbuf: Network buffer
  588. * Returns: rx fragment number
  589. */
  590. static
  591. uint8_t hal_rx_get_rx_fragment_number_5018(uint8_t *buf)
  592. {
  593. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  594. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  595. /* Return first 4 bits as fragment number */
  596. return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
  597. DOT11_SEQ_FRAG_MASK);
  598. }
  599. /**
  600. * hal_rx_msdu_end_da_is_mcbc_get_5018(): API to check if pkt is MCBC
  601. * from rx_msdu_end TLV
  602. *
  603. * @ buf: pointer to the start of RX PKT TLV headers
  604. * Return: da_is_mcbc
  605. */
  606. static uint8_t
  607. hal_rx_msdu_end_da_is_mcbc_get_5018(uint8_t *buf)
  608. {
  609. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  610. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  611. return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
  612. }
  613. /**
  614. * hal_rx_msdu_end_sa_is_valid_get_5018(): API to get_5018 the
  615. * sa_is_valid bit from rx_msdu_end TLV
  616. *
  617. * @ buf: pointer to the start of RX PKT TLV headers
  618. * Return: sa_is_valid bit
  619. */
  620. static uint8_t
  621. hal_rx_msdu_end_sa_is_valid_get_5018(uint8_t *buf)
  622. {
  623. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  624. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  625. uint8_t sa_is_valid;
  626. sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
  627. return sa_is_valid;
  628. }
  629. /**
  630. * hal_rx_msdu_end_sa_idx_get_5018(): API to get_5018 the
  631. * sa_idx from rx_msdu_end TLV
  632. *
  633. * @ buf: pointer to the start of RX PKT TLV headers
  634. * Return: sa_idx (SA AST index)
  635. */
  636. static uint16_t hal_rx_msdu_end_sa_idx_get_5018(uint8_t *buf)
  637. {
  638. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  639. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  640. uint16_t sa_idx;
  641. sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
  642. return sa_idx;
  643. }
  644. /**
  645. * hal_rx_desc_is_first_msdu_5018() - Check if first msdu
  646. *
  647. * @hal_soc_hdl: hal_soc handle
  648. * @hw_desc_addr: hardware descriptor address
  649. *
  650. * Return: 0 - success/ non-zero failure
  651. */
  652. static uint32_t hal_rx_desc_is_first_msdu_5018(void *hw_desc_addr)
  653. {
  654. struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
  655. struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
  656. return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU);
  657. }
  658. /**
  659. * hal_rx_msdu_end_l3_hdr_padding_get_5018(): API to get_5018 the
  660. * l3_header padding from rx_msdu_end TLV
  661. *
  662. * @ buf: pointer to the start of RX PKT TLV headers
  663. * Return: number of l3 header padding bytes
  664. */
  665. static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_5018(uint8_t *buf)
  666. {
  667. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  668. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  669. uint32_t l3_header_padding;
  670. l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
  671. return l3_header_padding;
  672. }
  673. /**
  674. * @ hal_rx_encryption_info_valid_5018: Returns encryption type.
  675. *
  676. * @ buf: rx_tlv_hdr of the received packet
  677. * @ Return: encryption type
  678. */
  679. inline uint32_t hal_rx_encryption_info_valid_5018(uint8_t *buf)
  680. {
  681. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  682. struct rx_mpdu_start *mpdu_start =
  683. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  684. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  685. uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
  686. return encryption_info;
  687. }
  688. /*
  689. * @ hal_rx_print_pn_5018: Prints the PN of rx packet.
  690. *
  691. * @ buf: rx_tlv_hdr of the received packet
  692. * @ Return: void
  693. */
  694. static void hal_rx_print_pn_5018(uint8_t *buf)
  695. {
  696. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  697. struct rx_mpdu_start *mpdu_start =
  698. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  699. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  700. uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
  701. uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
  702. uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
  703. uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
  704. hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ",
  705. pn_127_96, pn_95_64, pn_63_32, pn_31_0);
  706. }
  707. /**
  708. * hal_rx_msdu_end_first_msdu_get_5018: API to get first msdu status
  709. * from rx_msdu_end TLV
  710. *
  711. * @ buf: pointer to the start of RX PKT TLV headers
  712. * Return: first_msdu
  713. */
  714. static uint8_t hal_rx_msdu_end_first_msdu_get_5018(uint8_t *buf)
  715. {
  716. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  717. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  718. uint8_t first_msdu;
  719. first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
  720. return first_msdu;
  721. }
  722. /**
  723. * hal_rx_msdu_end_da_is_valid_get_5018: API to check if da is valid
  724. * from rx_msdu_end TLV
  725. *
  726. * @ buf: pointer to the start of RX PKT TLV headers
  727. * Return: da_is_valid
  728. */
  729. static uint8_t hal_rx_msdu_end_da_is_valid_get_5018(uint8_t *buf)
  730. {
  731. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  732. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  733. uint8_t da_is_valid;
  734. da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
  735. return da_is_valid;
  736. }
  737. /**
  738. * hal_rx_msdu_end_last_msdu_get_5018: API to get last msdu status
  739. * from rx_msdu_end TLV
  740. *
  741. * @ buf: pointer to the start of RX PKT TLV headers
  742. * Return: last_msdu
  743. */
  744. static uint8_t hal_rx_msdu_end_last_msdu_get_5018(uint8_t *buf)
  745. {
  746. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  747. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  748. uint8_t last_msdu;
  749. last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
  750. return last_msdu;
  751. }
  752. /*
  753. * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid
  754. *
  755. * @nbuf: Network buffer
  756. * Returns: value of mpdu 4th address valid field
  757. */
  758. inline bool hal_rx_get_mpdu_mac_ad4_valid_5018(uint8_t *buf)
  759. {
  760. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  761. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  762. bool ad4_valid = 0;
  763. ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info);
  764. return ad4_valid;
  765. }
  766. /**
  767. * hal_rx_mpdu_start_sw_peer_id_get_5018: Retrieve sw peer_id
  768. * @buf: network buffer
  769. *
  770. * Return: sw peer_id
  771. */
  772. static uint32_t hal_rx_mpdu_start_sw_peer_id_get_5018(uint8_t *buf)
  773. {
  774. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  775. struct rx_mpdu_start *mpdu_start =
  776. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  777. return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
  778. &mpdu_start->rx_mpdu_info_details);
  779. }
  780. /*
  781. * hal_rx_mpdu_get_to_ds_5018(): API to get the tods info
  782. * from rx_mpdu_start
  783. *
  784. * @buf: pointer to the start of RX PKT TLV header
  785. * Return: uint32_t(to_ds)
  786. */
  787. static uint32_t hal_rx_mpdu_get_to_ds_5018(uint8_t *buf)
  788. {
  789. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  790. struct rx_mpdu_start *mpdu_start =
  791. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  792. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  793. return HAL_RX_MPDU_GET_TODS(mpdu_info);
  794. }
  795. /*
  796. * hal_rx_mpdu_get_fr_ds_5018(): API to get the from ds info
  797. * from rx_mpdu_start
  798. *
  799. * @buf: pointer to the start of RX PKT TLV header
  800. * Return: uint32_t(fr_ds)
  801. */
  802. static uint32_t hal_rx_mpdu_get_fr_ds_5018(uint8_t *buf)
  803. {
  804. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  805. struct rx_mpdu_start *mpdu_start =
  806. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  807. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  808. return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
  809. }
  810. /*
  811. * hal_rx_get_mpdu_frame_control_valid_5018(): Retrieves mpdu
  812. * frame control valid
  813. *
  814. * @nbuf: Network buffer
  815. * Returns: value of frame control valid field
  816. */
  817. static uint8_t hal_rx_get_mpdu_frame_control_valid_5018(uint8_t *buf)
  818. {
  819. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  820. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  821. return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
  822. }
  823. /*
  824. * hal_rx_mpdu_get_addr1_5018(): API to check get address1 of the mpdu
  825. *
  826. * @buf: pointer to the start of RX PKT TLV headera
  827. * @mac_addr: pointer to mac address
  828. * Return: success/failure
  829. */
  830. static QDF_STATUS hal_rx_mpdu_get_addr1_5018(uint8_t *buf,
  831. uint8_t *mac_addr)
  832. {
  833. struct __attribute__((__packed__)) hal_addr1 {
  834. uint32_t ad1_31_0;
  835. uint16_t ad1_47_32;
  836. };
  837. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  838. struct rx_mpdu_start *mpdu_start =
  839. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  840. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  841. struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
  842. uint32_t mac_addr_ad1_valid;
  843. mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
  844. if (mac_addr_ad1_valid) {
  845. addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
  846. addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
  847. return QDF_STATUS_SUCCESS;
  848. }
  849. return QDF_STATUS_E_FAILURE;
  850. }
  851. /*
  852. * hal_rx_mpdu_get_addr2_5018(): API to check get address2 of the mpdu
  853. * in the packet
  854. *
  855. * @buf: pointer to the start of RX PKT TLV header
  856. * @mac_addr: pointer to mac address
  857. * Return: success/failure
  858. */
  859. static QDF_STATUS hal_rx_mpdu_get_addr2_5018(uint8_t *buf, uint8_t *mac_addr)
  860. {
  861. struct __attribute__((__packed__)) hal_addr2 {
  862. uint16_t ad2_15_0;
  863. uint32_t ad2_47_16;
  864. };
  865. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  866. struct rx_mpdu_start *mpdu_start =
  867. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  868. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  869. struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
  870. uint32_t mac_addr_ad2_valid;
  871. mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
  872. if (mac_addr_ad2_valid) {
  873. addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
  874. addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
  875. return QDF_STATUS_SUCCESS;
  876. }
  877. return QDF_STATUS_E_FAILURE;
  878. }
  879. /*
  880. * hal_rx_mpdu_get_addr3_5018(): API to get address3 of the mpdu
  881. * in the packet
  882. *
  883. * @buf: pointer to the start of RX PKT TLV header
  884. * @mac_addr: pointer to mac address
  885. * Return: success/failure
  886. */
  887. static QDF_STATUS hal_rx_mpdu_get_addr3_5018(uint8_t *buf, uint8_t *mac_addr)
  888. {
  889. struct __attribute__((__packed__)) hal_addr3 {
  890. uint32_t ad3_31_0;
  891. uint16_t ad3_47_32;
  892. };
  893. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  894. struct rx_mpdu_start *mpdu_start =
  895. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  896. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  897. struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
  898. uint32_t mac_addr_ad3_valid;
  899. mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
  900. if (mac_addr_ad3_valid) {
  901. addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
  902. addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
  903. return QDF_STATUS_SUCCESS;
  904. }
  905. return QDF_STATUS_E_FAILURE;
  906. }
  907. /*
  908. * hal_rx_mpdu_get_addr4_5018(): API to get address4 of the mpdu
  909. * in the packet
  910. *
  911. * @buf: pointer to the start of RX PKT TLV header
  912. * @mac_addr: pointer to mac address
  913. * Return: success/failure
  914. */
  915. static QDF_STATUS hal_rx_mpdu_get_addr4_5018(uint8_t *buf, uint8_t *mac_addr)
  916. {
  917. struct __attribute__((__packed__)) hal_addr4 {
  918. uint32_t ad4_31_0;
  919. uint16_t ad4_47_32;
  920. };
  921. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  922. struct rx_mpdu_start *mpdu_start =
  923. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  924. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  925. struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
  926. uint32_t mac_addr_ad4_valid;
  927. mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
  928. if (mac_addr_ad4_valid) {
  929. addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
  930. addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
  931. return QDF_STATUS_SUCCESS;
  932. }
  933. return QDF_STATUS_E_FAILURE;
  934. }
  935. /*
  936. * hal_rx_get_mpdu_sequence_control_valid_5018(): Get mpdu
  937. * sequence control valid
  938. *
  939. * @nbuf: Network buffer
  940. * Returns: value of sequence control valid field
  941. */
  942. static uint8_t hal_rx_get_mpdu_sequence_control_valid_5018(uint8_t *buf)
  943. {
  944. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  945. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  946. return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
  947. }
  948. /**
  949. * hal_rx_is_unicast_5018: check packet is unicast frame or not.
  950. *
  951. * @ buf: pointer to rx pkt TLV.
  952. *
  953. * Return: true on unicast.
  954. */
  955. static bool hal_rx_is_unicast_5018(uint8_t *buf)
  956. {
  957. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  958. struct rx_mpdu_start *mpdu_start =
  959. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  960. uint32_t grp_id;
  961. uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
  962. grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
  963. RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)),
  964. RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK,
  965. RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB));
  966. return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
  967. }
  968. /**
  969. * hal_rx_tid_get_5018: get tid based on qos control valid.
  970. * @hal_soc_hdl: hal soc handle
  971. * @buf: pointer to rx pkt TLV.
  972. *
  973. * Return: tid
  974. */
  975. static uint32_t hal_rx_tid_get_5018(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  976. {
  977. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  978. struct rx_mpdu_start *mpdu_start =
  979. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  980. uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
  981. uint8_t qos_control_valid =
  982. (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
  983. RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)),
  984. RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK,
  985. RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB));
  986. if (qos_control_valid)
  987. return hal_rx_mpdu_start_tid_get_5018(buf);
  988. return HAL_RX_NON_QOS_TID;
  989. }
  990. /**
  991. * hal_rx_hw_desc_get_ppduid_get_5018(): retrieve ppdu id
  992. * @rx_tlv_hdr: rx tlv header
  993. * @rxdma_dst_ring_desc: rxdma HW descriptor
  994. *
  995. * Return: ppdu id
  996. */
  997. static uint32_t hal_rx_hw_desc_get_ppduid_get_5018(void *rx_tlv_hdr,
  998. void *rxdma_dst_ring_desc)
  999. {
  1000. struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc;
  1001. return HAL_RX_REO_ENT_PHY_PPDU_ID_GET(reo_ent);
  1002. }
  1003. /**
  1004. * hal_reo_status_get_header_5018 - Process reo desc info
  1005. * @ring_desc: REO status ring descriptor
  1006. * @b - tlv type info
  1007. * @h1 - Pointer to hal_reo_status_header where info to be stored
  1008. *
  1009. * Return - none.
  1010. *
  1011. */
  1012. static void hal_reo_status_get_header_5018(hal_ring_desc_t ring_desc, int b,
  1013. void *h1)
  1014. {
  1015. uint32_t *d = (uint32_t *)ring_desc;
  1016. uint32_t val1 = 0;
  1017. struct hal_reo_status_header *h =
  1018. (struct hal_reo_status_header *)h1;
  1019. /* Offsets of descriptor fields defined in HW headers start
  1020. * from the field after TLV header
  1021. */
  1022. d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
  1023. switch (b) {
  1024. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  1025. val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
  1026. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1027. break;
  1028. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  1029. val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
  1030. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1031. break;
  1032. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  1033. val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
  1034. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1035. break;
  1036. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  1037. val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
  1038. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1039. break;
  1040. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  1041. val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
  1042. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1043. break;
  1044. case HAL_REO_DESC_THRES_STATUS_TLV:
  1045. val1 =
  1046. d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
  1047. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1048. break;
  1049. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  1050. val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
  1051. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
  1052. break;
  1053. default:
  1054. qdf_nofl_err("ERROR: Unknown tlv\n");
  1055. break;
  1056. }
  1057. h->cmd_num =
  1058. HAL_GET_FIELD(
  1059. UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
  1060. val1);
  1061. h->exec_time =
  1062. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
  1063. CMD_EXECUTION_TIME, val1);
  1064. h->status =
  1065. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
  1066. REO_CMD_EXECUTION_STATUS, val1);
  1067. switch (b) {
  1068. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  1069. val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
  1070. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1071. break;
  1072. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  1073. val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
  1074. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1075. break;
  1076. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  1077. val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
  1078. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1079. break;
  1080. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  1081. val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
  1082. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1083. break;
  1084. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  1085. val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
  1086. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1087. break;
  1088. case HAL_REO_DESC_THRES_STATUS_TLV:
  1089. val1 =
  1090. d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
  1091. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1092. break;
  1093. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  1094. val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
  1095. UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
  1096. break;
  1097. default:
  1098. qdf_nofl_err("ERROR: Unknown tlv\n");
  1099. break;
  1100. }
  1101. h->tstamp =
  1102. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
  1103. }
  1104. /**
  1105. * hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018():
  1106. * Retrieve qos control valid bit from the tlv.
  1107. * @buf: pointer to rx pkt TLV.
  1108. *
  1109. * Return: qos control value.
  1110. */
  1111. static inline uint32_t
  1112. hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(uint8_t *buf)
  1113. {
  1114. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1115. struct rx_mpdu_start *mpdu_start =
  1116. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  1117. return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
  1118. &mpdu_start->rx_mpdu_info_details);
  1119. }
  1120. /**
  1121. * hal_rx_msdu_end_sa_sw_peer_id_get_5018(): API to get the
  1122. * sa_sw_peer_id from rx_msdu_end TLV
  1123. * @buf: pointer to the start of RX PKT TLV headers
  1124. *
  1125. * Return: sa_sw_peer_id index
  1126. */
  1127. static inline uint32_t
  1128. hal_rx_msdu_end_sa_sw_peer_id_get_5018(uint8_t *buf)
  1129. {
  1130. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1131. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1132. return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
  1133. }
  1134. /**
  1135. * hal_tx_desc_set_mesh_en_5018 - Set mesh_enable flag in Tx descriptor
  1136. * @desc: Handle to Tx Descriptor
  1137. * @en: For raw WiFi frames, this indicates transmission to a mesh STA,
  1138. * enabling the interpretation of the 'Mesh Control Present' bit
  1139. * (bit 8) of QoS Control (otherwise this bit is ignored),
  1140. * For native WiFi frames, this indicates that a 'Mesh Control' field
  1141. * is present between the header and the LLC.
  1142. *
  1143. * Return: void
  1144. */
  1145. static inline
  1146. void hal_tx_desc_set_mesh_en_5018(void *desc, uint8_t en)
  1147. {
  1148. HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |=
  1149. HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en);
  1150. }
  1151. static
  1152. void *hal_rx_msdu0_buffer_addr_lsb_5018(void *link_desc_va)
  1153. {
  1154. return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
  1155. }
  1156. static
  1157. void *hal_rx_msdu_desc_info_ptr_get_5018(void *msdu0)
  1158. {
  1159. return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
  1160. }
  1161. static
  1162. void *hal_ent_mpdu_desc_info_5018(void *ent_ring_desc)
  1163. {
  1164. return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
  1165. }
  1166. static
  1167. void *hal_dst_mpdu_desc_info_5018(void *dst_ring_desc)
  1168. {
  1169. return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
  1170. }
  1171. static
  1172. uint8_t hal_rx_get_fc_valid_5018(uint8_t *buf)
  1173. {
  1174. return HAL_RX_GET_FC_VALID(buf);
  1175. }
  1176. static uint8_t hal_rx_get_to_ds_flag_5018(uint8_t *buf)
  1177. {
  1178. return HAL_RX_GET_TO_DS_FLAG(buf);
  1179. }
  1180. static uint8_t hal_rx_get_mac_addr2_valid_5018(uint8_t *buf)
  1181. {
  1182. return HAL_RX_GET_MAC_ADDR2_VALID(buf);
  1183. }
  1184. static uint8_t hal_rx_get_filter_category_5018(uint8_t *buf)
  1185. {
  1186. return HAL_RX_GET_FILTER_CATEGORY(buf);
  1187. }
  1188. static uint32_t
  1189. hal_rx_get_ppdu_id_5018(uint8_t *buf)
  1190. {
  1191. struct rx_mpdu_info *rx_mpdu_info;
  1192. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf;
  1193. rx_mpdu_info =
  1194. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  1195. return HAL_RX_GET_PPDU_ID(rx_mpdu_info);
  1196. }
  1197. /**
  1198. * hal_reo_config_5018(): Set reo config parameters
  1199. * @soc: hal soc handle
  1200. * @reg_val: value to be set
  1201. * @reo_params: reo parameters
  1202. *
  1203. * Return: void
  1204. */
  1205. static void
  1206. hal_reo_config_5018(struct hal_soc *soc,
  1207. uint32_t reg_val,
  1208. struct hal_reo_params *reo_params)
  1209. {
  1210. HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
  1211. }
  1212. /**
  1213. * hal_rx_msdu_desc_info_get_ptr_5018() - Get msdu desc info ptr
  1214. * @msdu_details_ptr - Pointer to msdu_details_ptr
  1215. *
  1216. * Return - Pointer to rx_msdu_desc_info structure.
  1217. *
  1218. */
  1219. static void *hal_rx_msdu_desc_info_get_ptr_5018(void *msdu_details_ptr)
  1220. {
  1221. return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
  1222. }
  1223. /**
  1224. * hal_rx_link_desc_msdu0_ptr_5018 - Get pointer to rx_msdu details
  1225. * @link_desc - Pointer to link desc
  1226. *
  1227. * Return - Pointer to rx_msdu_details structure
  1228. *
  1229. */
  1230. static void *hal_rx_link_desc_msdu0_ptr_5018(void *link_desc)
  1231. {
  1232. return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
  1233. }
  1234. /**
  1235. * hal_rx_msdu_flow_idx_get_5018: API to get flow index
  1236. * from rx_msdu_end TLV
  1237. * @buf: pointer to the start of RX PKT TLV headers
  1238. *
  1239. * Return: flow index value from MSDU END TLV
  1240. */
  1241. static inline uint32_t hal_rx_msdu_flow_idx_get_5018(uint8_t *buf)
  1242. {
  1243. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1244. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1245. return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
  1246. }
  1247. /**
  1248. * hal_rx_msdu_flow_idx_invalid_5018: API to get flow index invalid
  1249. * from rx_msdu_end TLV
  1250. * @buf: pointer to the start of RX PKT TLV headers
  1251. *
  1252. * Return: flow index invalid value from MSDU END TLV
  1253. */
  1254. static bool hal_rx_msdu_flow_idx_invalid_5018(uint8_t *buf)
  1255. {
  1256. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1257. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1258. return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
  1259. }
  1260. /**
  1261. * hal_rx_msdu_flow_idx_timeout_5018: API to get flow index timeout
  1262. * from rx_msdu_end TLV
  1263. * @buf: pointer to the start of RX PKT TLV headers
  1264. *
  1265. * Return: flow index timeout value from MSDU END TLV
  1266. */
  1267. static bool hal_rx_msdu_flow_idx_timeout_5018(uint8_t *buf)
  1268. {
  1269. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1270. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1271. return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
  1272. }
  1273. /**
  1274. * hal_rx_msdu_fse_metadata_get_5018: API to get FSE metadata
  1275. * from rx_msdu_end TLV
  1276. * @buf: pointer to the start of RX PKT TLV headers
  1277. *
  1278. * Return: fse metadata value from MSDU END TLV
  1279. */
  1280. static uint32_t hal_rx_msdu_fse_metadata_get_5018(uint8_t *buf)
  1281. {
  1282. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1283. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1284. return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
  1285. }
  1286. /**
  1287. * hal_rx_msdu_cce_metadata_get_5018: API to get CCE metadata
  1288. * from rx_msdu_end TLV
  1289. * @buf: pointer to the start of RX PKT TLV headers
  1290. *
  1291. * Return: cce_metadata
  1292. */
  1293. static uint16_t
  1294. hal_rx_msdu_cce_metadata_get_5018(uint8_t *buf)
  1295. {
  1296. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1297. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1298. return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
  1299. }
  1300. /**
  1301. * hal_rx_msdu_get_flow_params_5018: API to get flow index, flow index invalid
  1302. * and flow index timeout from rx_msdu_end TLV
  1303. * @buf: pointer to the start of RX PKT TLV headers
  1304. * @flow_invalid: pointer to return value of flow_idx_valid
  1305. * @flow_timeout: pointer to return value of flow_idx_timeout
  1306. * @flow_index: pointer to return value of flow_idx
  1307. *
  1308. * Return: none
  1309. */
  1310. static inline void
  1311. hal_rx_msdu_get_flow_params_5018(uint8_t *buf,
  1312. bool *flow_invalid,
  1313. bool *flow_timeout,
  1314. uint32_t *flow_index)
  1315. {
  1316. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1317. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1318. *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
  1319. *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
  1320. *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
  1321. }
  1322. /**
  1323. * hal_rx_tlv_get_tcp_chksum_5018() - API to get tcp checksum
  1324. * @buf: rx_tlv_hdr
  1325. *
  1326. * Return: tcp checksum
  1327. */
  1328. static uint16_t
  1329. hal_rx_tlv_get_tcp_chksum_5018(uint8_t *buf)
  1330. {
  1331. return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
  1332. }
  1333. /**
  1334. * hal_rx_get_rx_sequence_5018(): Function to retrieve rx sequence number
  1335. *
  1336. * @nbuf: Network buffer
  1337. * Returns: rx sequence number
  1338. */
  1339. static
  1340. uint16_t hal_rx_get_rx_sequence_5018(uint8_t *buf)
  1341. {
  1342. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  1343. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  1344. return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
  1345. }
  1346. /**
  1347. * hal_get_window_address_5018(): Function to get hp/tp address
  1348. * @hal_soc: Pointer to hal_soc
  1349. * @addr: address offset of register
  1350. *
  1351. * Return: modified address offset of register
  1352. */
  1353. static inline qdf_iomem_t hal_get_window_address_5018(struct hal_soc *hal_soc,
  1354. qdf_iomem_t addr)
  1355. {
  1356. uint32_t offset = addr - hal_soc->dev_base_addr;
  1357. qdf_iomem_t new_offset;
  1358. /*
  1359. * Check if offset lies within CE register range(0x08400000)
  1360. * or UMAC/DP register range (0x00A00000).
  1361. * If offset lies within CE register range, map it
  1362. * into CE region.
  1363. */
  1364. if (offset & HOST_CE_MASK_VALUE) {
  1365. offset = offset - WFSS_CE_REG_BASE;
  1366. new_offset = (hal_soc->dev_base_addr_ce + offset);
  1367. return new_offset;
  1368. } else {
  1369. /*
  1370. * If offset lies within DP register range,
  1371. * return the address as such
  1372. */
  1373. return addr;
  1374. }
  1375. }
  1376. static inline void hal_write_window_register(struct hal_soc *hal_soc)
  1377. {
  1378. /* Write value into window configuration register */
  1379. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  1380. WINDOW_CONFIGURATION_VALUE_5018);
  1381. }
  1382. /**
  1383. * hal_rx_msdu_packet_metadata_get_5018(): API to get the
  1384. * msdu information from rx_msdu_end TLV
  1385. *
  1386. * @ buf: pointer to the start of RX PKT TLV headers
  1387. * @ hal_rx_msdu_metadata: pointer to the msdu info structure
  1388. */
  1389. static void
  1390. hal_rx_msdu_packet_metadata_get_5018(uint8_t *buf,
  1391. void *msdu_pkt_metadata)
  1392. {
  1393. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1394. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1395. struct hal_rx_msdu_metadata *msdu_metadata =
  1396. (struct hal_rx_msdu_metadata *)msdu_pkt_metadata;
  1397. msdu_metadata->l3_hdr_pad =
  1398. HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
  1399. msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
  1400. msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  1401. msdu_metadata->sa_sw_peer_id =
  1402. HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
  1403. }
  1404. /**
  1405. * hal_rx_flow_setup_fse_5018() - Setup a flow search entry in HW FST
  1406. * @fst: Pointer to the Rx Flow Search Table
  1407. * @table_offset: offset into the table where the flow is to be setup
  1408. * @flow: Flow Parameters
  1409. *
  1410. * Return: Success/Failure
  1411. */
  1412. static void *
  1413. hal_rx_flow_setup_fse_5018(uint8_t *rx_fst, uint32_t table_offset,
  1414. uint8_t *rx_flow)
  1415. {
  1416. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  1417. struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
  1418. uint8_t *fse;
  1419. bool fse_valid;
  1420. if (table_offset >= fst->max_entries) {
  1421. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1422. "HAL FSE table offset %u exceeds max entries %u",
  1423. table_offset, fst->max_entries);
  1424. return NULL;
  1425. }
  1426. fse = (uint8_t *)fst->base_vaddr +
  1427. (table_offset * HAL_RX_FST_ENTRY_SIZE);
  1428. fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
  1429. if (fse_valid) {
  1430. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  1431. "HAL FSE %pK already valid", fse);
  1432. return NULL;
  1433. }
  1434. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) =
  1435. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96,
  1436. qdf_htonl(flow->tuple_info.src_ip_127_96));
  1437. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) =
  1438. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64,
  1439. qdf_htonl(flow->tuple_info.src_ip_95_64));
  1440. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) =
  1441. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32,
  1442. qdf_htonl(flow->tuple_info.src_ip_63_32));
  1443. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) =
  1444. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0,
  1445. qdf_htonl(flow->tuple_info.src_ip_31_0));
  1446. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) =
  1447. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96,
  1448. qdf_htonl(flow->tuple_info.dest_ip_127_96));
  1449. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) =
  1450. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64,
  1451. qdf_htonl(flow->tuple_info.dest_ip_95_64));
  1452. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) =
  1453. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32,
  1454. qdf_htonl(flow->tuple_info.dest_ip_63_32));
  1455. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) =
  1456. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0,
  1457. qdf_htonl(flow->tuple_info.dest_ip_31_0));
  1458. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT);
  1459. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |=
  1460. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT,
  1461. (flow->tuple_info.dest_port));
  1462. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT);
  1463. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |=
  1464. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT,
  1465. (flow->tuple_info.src_port));
  1466. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL);
  1467. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |=
  1468. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL,
  1469. flow->tuple_info.l4_protocol);
  1470. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER);
  1471. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |=
  1472. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER,
  1473. flow->reo_destination_handler);
  1474. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
  1475. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |=
  1476. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1);
  1477. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA);
  1478. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) =
  1479. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA,
  1480. flow->fse_metadata);
  1481. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION);
  1482. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |=
  1483. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9,
  1484. REO_DESTINATION_INDICATION,
  1485. flow->reo_destination_indication);
  1486. /* Reset all the other fields in FSE */
  1487. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9);
  1488. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP);
  1489. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT);
  1490. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT);
  1491. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP);
  1492. return fse;
  1493. }
  1494. static void hal_hw_txrx_ops_attach_qca5018(struct hal_soc *hal_soc)
  1495. {
  1496. /* init and setup */
  1497. hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
  1498. hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
  1499. hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
  1500. hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
  1501. hal_soc->ops->hal_get_window_address = hal_get_window_address_5018;
  1502. /* tx */
  1503. hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
  1504. hal_tx_desc_set_dscp_tid_table_id_5018;
  1505. hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5018;
  1506. hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5018;
  1507. hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_5018;
  1508. hal_soc->ops->hal_tx_desc_set_buf_addr =
  1509. hal_tx_desc_set_buf_addr_generic_li;
  1510. hal_soc->ops->hal_tx_desc_set_search_type =
  1511. hal_tx_desc_set_search_type_generic_li;
  1512. hal_soc->ops->hal_tx_desc_set_search_index =
  1513. hal_tx_desc_set_search_index_generic_li;
  1514. hal_soc->ops->hal_tx_desc_set_cache_set_num =
  1515. hal_tx_desc_set_cache_set_num_generic_li;
  1516. hal_soc->ops->hal_tx_comp_get_status =
  1517. hal_tx_comp_get_status_generic_li;
  1518. hal_soc->ops->hal_tx_comp_get_release_reason =
  1519. hal_tx_comp_get_release_reason_generic_li;
  1520. hal_soc->ops->hal_get_wbm_internal_error =
  1521. hal_get_wbm_internal_error_generic_li;
  1522. hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_5018;
  1523. hal_soc->ops->hal_tx_init_cmd_credit_ring =
  1524. hal_tx_init_cmd_credit_ring_5018;
  1525. /* rx */
  1526. hal_soc->ops->hal_rx_msdu_start_nss_get =
  1527. hal_rx_msdu_start_nss_get_5018;
  1528. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
  1529. hal_rx_mon_hw_desc_get_mpdu_status_5018;
  1530. hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5018;
  1531. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
  1532. hal_rx_proc_phyrx_other_receive_info_tlv_5018;
  1533. hal_soc->ops->hal_rx_dump_msdu_start_tlv =
  1534. hal_rx_dump_msdu_start_tlv_5018;
  1535. hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5018;
  1536. hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5018;
  1537. hal_soc->ops->hal_rx_mpdu_start_tid_get =
  1538. hal_rx_mpdu_start_tid_get_5018;
  1539. hal_soc->ops->hal_rx_msdu_start_reception_type_get =
  1540. hal_rx_msdu_start_reception_type_get_5018;
  1541. hal_soc->ops->hal_rx_msdu_end_da_idx_get =
  1542. hal_rx_msdu_end_da_idx_get_5018;
  1543. hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
  1544. hal_rx_msdu_desc_info_get_ptr_5018;
  1545. hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
  1546. hal_rx_link_desc_msdu0_ptr_5018;
  1547. hal_soc->ops->hal_reo_status_get_header =
  1548. hal_reo_status_get_header_5018;
  1549. hal_soc->ops->hal_rx_status_get_tlv_info =
  1550. hal_rx_status_get_tlv_info_generic_li;
  1551. hal_soc->ops->hal_rx_wbm_err_info_get =
  1552. hal_rx_wbm_err_info_get_generic_li;
  1553. hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
  1554. hal_rx_dump_mpdu_start_tlv_generic_li;
  1555. hal_soc->ops->hal_tx_set_pcp_tid_map =
  1556. hal_tx_set_pcp_tid_map_generic_li;
  1557. hal_soc->ops->hal_tx_update_pcp_tid_map =
  1558. hal_tx_update_pcp_tid_generic_li;
  1559. hal_soc->ops->hal_tx_set_tidmap_prty =
  1560. hal_tx_update_tidmap_prty_generic_li;
  1561. hal_soc->ops->hal_rx_get_rx_fragment_number =
  1562. hal_rx_get_rx_fragment_number_5018;
  1563. hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
  1564. hal_rx_msdu_end_da_is_mcbc_get_5018;
  1565. hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
  1566. hal_rx_msdu_end_sa_is_valid_get_5018;
  1567. hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
  1568. hal_rx_msdu_end_sa_idx_get_5018;
  1569. hal_soc->ops->hal_rx_desc_is_first_msdu =
  1570. hal_rx_desc_is_first_msdu_5018;
  1571. hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
  1572. hal_rx_msdu_end_l3_hdr_padding_get_5018;
  1573. hal_soc->ops->hal_rx_encryption_info_valid =
  1574. hal_rx_encryption_info_valid_5018;
  1575. hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_5018;
  1576. hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
  1577. hal_rx_msdu_end_first_msdu_get_5018;
  1578. hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
  1579. hal_rx_msdu_end_da_is_valid_get_5018;
  1580. hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
  1581. hal_rx_msdu_end_last_msdu_get_5018;
  1582. hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
  1583. hal_rx_get_mpdu_mac_ad4_valid_5018;
  1584. hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
  1585. hal_rx_mpdu_start_sw_peer_id_get_5018;
  1586. hal_soc->ops->hal_rx_mpdu_peer_meta_data_get =
  1587. hal_rx_mpdu_peer_meta_data_get_li;
  1588. hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_5018;
  1589. hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_5018;
  1590. hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
  1591. hal_rx_get_mpdu_frame_control_valid_5018;
  1592. hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_5018;
  1593. hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_5018;
  1594. hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_5018;
  1595. hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_5018;
  1596. hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
  1597. hal_rx_get_mpdu_sequence_control_valid_5018;
  1598. hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_5018;
  1599. hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_5018;
  1600. hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
  1601. hal_rx_hw_desc_get_ppduid_get_5018;
  1602. hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
  1603. hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018;
  1604. hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
  1605. hal_rx_msdu_end_sa_sw_peer_id_get_5018;
  1606. hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
  1607. hal_rx_msdu0_buffer_addr_lsb_5018;
  1608. hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
  1609. hal_rx_msdu_desc_info_ptr_get_5018;
  1610. hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5018;
  1611. hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5018;
  1612. hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_5018;
  1613. hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_5018;
  1614. hal_soc->ops->hal_rx_get_mac_addr2_valid =
  1615. hal_rx_get_mac_addr2_valid_5018;
  1616. hal_soc->ops->hal_rx_get_filter_category =
  1617. hal_rx_get_filter_category_5018;
  1618. hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_5018;
  1619. hal_soc->ops->hal_reo_config = hal_reo_config_5018;
  1620. hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_5018;
  1621. hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
  1622. hal_rx_msdu_flow_idx_invalid_5018;
  1623. hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
  1624. hal_rx_msdu_flow_idx_timeout_5018;
  1625. hal_soc->ops->hal_rx_msdu_fse_metadata_get =
  1626. hal_rx_msdu_fse_metadata_get_5018;
  1627. hal_soc->ops->hal_rx_msdu_cce_match_get =
  1628. hal_rx_msdu_cce_match_get_li;
  1629. hal_soc->ops->hal_rx_msdu_cce_metadata_get =
  1630. hal_rx_msdu_cce_metadata_get_5018;
  1631. hal_soc->ops->hal_rx_msdu_get_flow_params =
  1632. hal_rx_msdu_get_flow_params_5018;
  1633. hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
  1634. hal_rx_tlv_get_tcp_chksum_5018;
  1635. hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_5018;
  1636. #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
  1637. hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5018;
  1638. hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5018;
  1639. #endif
  1640. /* rx - msdu fast path info fields */
  1641. hal_soc->ops->hal_rx_msdu_packet_metadata_get =
  1642. hal_rx_msdu_packet_metadata_get_5018;
  1643. hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
  1644. hal_rx_mpdu_start_tlv_tag_valid_5018;
  1645. hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
  1646. hal_rx_wbm_err_msdu_continuation_get_5018;
  1647. /* rx - TLV struct offsets */
  1648. hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
  1649. hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
  1650. hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
  1651. hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
  1652. hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
  1653. #ifndef NO_RX_PKT_HDR_TLV
  1654. hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
  1655. #endif
  1656. hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5018;
  1657. hal_soc->ops->hal_rx_flow_get_tuple_info =
  1658. hal_rx_flow_get_tuple_info_li;
  1659. hal_soc->ops->hal_rx_flow_delete_entry =
  1660. hal_rx_flow_delete_entry_li;
  1661. hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li;
  1662. hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_5018;
  1663. hal_soc->ops->hal_setup_link_idle_list =
  1664. hal_setup_link_idle_list_generic_li;
  1665. hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
  1666. hal_soc->ops->hal_rx_tlv_msdu_len_get =
  1667. hal_rx_msdu_start_get_len_5018;
  1668. };
  1669. struct hal_hw_srng_config hw_srng_table_5018[] = {
  1670. /* TODO: max_rings can populated by querying HW capabilities */
  1671. { /* REO_DST */
  1672. .start_ring_id = HAL_SRNG_REO2SW1,
  1673. .max_rings = 4,
  1674. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1675. .lmac_ring = FALSE,
  1676. .ring_dir = HAL_SRNG_DST_RING,
  1677. .reg_start = {
  1678. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
  1679. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1680. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
  1681. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1682. },
  1683. .reg_size = {
  1684. HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
  1685. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
  1686. HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
  1687. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
  1688. },
  1689. .max_size =
  1690. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1691. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
  1692. },
  1693. { /* REO_EXCEPTION */
  1694. /* Designating REO2TCL ring as exception ring. This ring is
  1695. * similar to other REO2SW rings though it is named as REO2TCL.
  1696. * Any of theREO2SW rings can be used as exception ring.
  1697. */
  1698. .start_ring_id = HAL_SRNG_REO2TCL,
  1699. .max_rings = 1,
  1700. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1701. .lmac_ring = FALSE,
  1702. .ring_dir = HAL_SRNG_DST_RING,
  1703. .reg_start = {
  1704. HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
  1705. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1706. HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
  1707. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1708. },
  1709. /* Single ring - provide ring size if multiple rings of this
  1710. * type are supported
  1711. */
  1712. .reg_size = {},
  1713. .max_size =
  1714. HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
  1715. HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
  1716. },
  1717. { /* REO_REINJECT */
  1718. .start_ring_id = HAL_SRNG_SW2REO,
  1719. .max_rings = 1,
  1720. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1721. .lmac_ring = FALSE,
  1722. .ring_dir = HAL_SRNG_SRC_RING,
  1723. .reg_start = {
  1724. HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
  1725. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1726. HWIO_REO_R2_SW2REO_RING_HP_ADDR(
  1727. SEQ_WCSS_UMAC_REO_REG_OFFSET)
  1728. },
  1729. /* Single ring - provide ring size if multiple rings of this
  1730. * type are supported
  1731. */
  1732. .reg_size = {},
  1733. .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
  1734. HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
  1735. },
  1736. { /* REO_CMD */
  1737. .start_ring_id = HAL_SRNG_REO_CMD,
  1738. .max_rings = 1,
  1739. .entry_size = (sizeof(struct tlv_32_hdr) +
  1740. sizeof(struct reo_get_queue_stats)) >> 2,
  1741. .lmac_ring = FALSE,
  1742. .ring_dir = HAL_SRNG_SRC_RING,
  1743. .reg_start = {
  1744. HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
  1745. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1746. HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
  1747. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1748. },
  1749. /* Single ring - provide ring size if multiple rings of this
  1750. * type are supported
  1751. */
  1752. .reg_size = {},
  1753. .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
  1754. HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
  1755. },
  1756. { /* REO_STATUS */
  1757. .start_ring_id = HAL_SRNG_REO_STATUS,
  1758. .max_rings = 1,
  1759. .entry_size = (sizeof(struct tlv_32_hdr) +
  1760. sizeof(struct reo_get_queue_stats_status)) >> 2,
  1761. .lmac_ring = FALSE,
  1762. .ring_dir = HAL_SRNG_DST_RING,
  1763. .reg_start = {
  1764. HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
  1765. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1766. HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
  1767. SEQ_WCSS_UMAC_REO_REG_OFFSET),
  1768. },
  1769. /* Single ring - provide ring size if multiple rings of this
  1770. * type are supported
  1771. */
  1772. .reg_size = {},
  1773. .max_size =
  1774. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1775. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1776. },
  1777. { /* TCL_DATA */
  1778. .start_ring_id = HAL_SRNG_SW2TCL1,
  1779. .max_rings = 3,
  1780. .entry_size = (sizeof(struct tlv_32_hdr) +
  1781. sizeof(struct tcl_data_cmd)) >> 2,
  1782. .lmac_ring = FALSE,
  1783. .ring_dir = HAL_SRNG_SRC_RING,
  1784. .reg_start = {
  1785. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
  1786. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1787. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
  1788. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1789. },
  1790. .reg_size = {
  1791. HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
  1792. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
  1793. HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
  1794. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
  1795. },
  1796. .max_size =
  1797. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1798. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
  1799. },
  1800. { /* TCL_CMD */
  1801. .start_ring_id = HAL_SRNG_SW2TCL_CMD,
  1802. .max_rings = 1,
  1803. .entry_size = (sizeof(struct tlv_32_hdr) +
  1804. sizeof(struct tcl_data_cmd)) >> 2,
  1805. .lmac_ring = FALSE,
  1806. .ring_dir = HAL_SRNG_SRC_RING,
  1807. .reg_start = {
  1808. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
  1809. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1810. HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
  1811. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1812. },
  1813. /* Single ring - provide ring size if multiple rings of this
  1814. * type are supported
  1815. */
  1816. .reg_size = {},
  1817. .max_size =
  1818. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
  1819. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
  1820. },
  1821. { /* TCL_STATUS */
  1822. .start_ring_id = HAL_SRNG_TCL_STATUS,
  1823. .max_rings = 1,
  1824. .entry_size = (sizeof(struct tlv_32_hdr) +
  1825. sizeof(struct tcl_status_ring)) >> 2,
  1826. .lmac_ring = FALSE,
  1827. .ring_dir = HAL_SRNG_DST_RING,
  1828. .reg_start = {
  1829. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
  1830. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1831. HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
  1832. SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
  1833. },
  1834. /* Single ring - provide ring size if multiple rings of this
  1835. * type are supported
  1836. */
  1837. .reg_size = {},
  1838. .max_size =
  1839. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1840. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
  1841. },
  1842. { /* CE_SRC */
  1843. .start_ring_id = HAL_SRNG_CE_0_SRC,
  1844. .max_rings = 12,
  1845. .entry_size = sizeof(struct ce_src_desc) >> 2,
  1846. .lmac_ring = FALSE,
  1847. .ring_dir = HAL_SRNG_SRC_RING,
  1848. .reg_start = {
  1849. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1850. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
  1851. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1852. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
  1853. },
  1854. .reg_size = {
  1855. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
  1856. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
  1857. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
  1858. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
  1859. },
  1860. .max_size =
  1861. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1862. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1863. },
  1864. { /* CE_DST */
  1865. .start_ring_id = HAL_SRNG_CE_0_DST,
  1866. .max_rings = 12,
  1867. .entry_size = 8 >> 2,
  1868. /*TODO: entry_size above should actually be
  1869. * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
  1870. * of struct ce_dst_desc in HW header files
  1871. */
  1872. .lmac_ring = FALSE,
  1873. .ring_dir = HAL_SRNG_SRC_RING,
  1874. .reg_start = {
  1875. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1876. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1877. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1878. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1879. },
  1880. .reg_size = {
  1881. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1882. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1883. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1884. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1885. },
  1886. .max_size =
  1887. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1888. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1889. },
  1890. { /* CE_DST_STATUS */
  1891. .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
  1892. .max_rings = 12,
  1893. .entry_size = sizeof(struct ce_stat_desc) >> 2,
  1894. .lmac_ring = FALSE,
  1895. .ring_dir = HAL_SRNG_DST_RING,
  1896. .reg_start = {
  1897. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
  1898. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1899. HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
  1900. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
  1901. },
  1902. /* TODO: check destination status ring registers */
  1903. .reg_size = {
  1904. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1905. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1906. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
  1907. SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
  1908. },
  1909. .max_size =
  1910. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1911. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1912. },
  1913. { /* WBM_IDLE_LINK */
  1914. .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
  1915. .max_rings = 1,
  1916. .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
  1917. .lmac_ring = FALSE,
  1918. .ring_dir = HAL_SRNG_SRC_RING,
  1919. .reg_start = {
  1920. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1921. HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1922. },
  1923. /* Single ring - provide ring size if multiple rings of this
  1924. * type are supported
  1925. */
  1926. .reg_size = {},
  1927. .max_size =
  1928. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
  1929. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
  1930. },
  1931. { /* SW2WBM_RELEASE */
  1932. .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
  1933. .max_rings = 1,
  1934. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  1935. .lmac_ring = FALSE,
  1936. .ring_dir = HAL_SRNG_SRC_RING,
  1937. .reg_start = {
  1938. HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1939. HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1940. },
  1941. /* Single ring - provide ring size if multiple rings of this
  1942. * type are supported
  1943. */
  1944. .reg_size = {},
  1945. .max_size =
  1946. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  1947. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  1948. },
  1949. { /* WBM2SW_RELEASE */
  1950. .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
  1951. .max_rings = 5,
  1952. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  1953. .lmac_ring = FALSE,
  1954. .ring_dir = HAL_SRNG_DST_RING,
  1955. .reg_start = {
  1956. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1957. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1958. },
  1959. .reg_size = {
  1960. HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
  1961. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1962. HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
  1963. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
  1964. },
  1965. .max_size =
  1966. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  1967. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  1968. },
  1969. { /* RXDMA_BUF */
  1970. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
  1971. #ifdef IPA_OFFLOAD
  1972. .max_rings = 3,
  1973. #else
  1974. .max_rings = 2,
  1975. #endif
  1976. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1977. .lmac_ring = TRUE,
  1978. .ring_dir = HAL_SRNG_SRC_RING,
  1979. /* reg_start is not set because LMAC rings are not accessed
  1980. * from host
  1981. */
  1982. .reg_start = {},
  1983. .reg_size = {},
  1984. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1985. },
  1986. { /* RXDMA_DST */
  1987. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
  1988. .max_rings = 1,
  1989. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1990. .lmac_ring = TRUE,
  1991. .ring_dir = HAL_SRNG_DST_RING,
  1992. /* reg_start is not set because LMAC rings are not accessed
  1993. * from host
  1994. */
  1995. .reg_start = {},
  1996. .reg_size = {},
  1997. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1998. },
  1999. { /* RXDMA_MONITOR_BUF */
  2000. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
  2001. .max_rings = 1,
  2002. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  2003. .lmac_ring = TRUE,
  2004. .ring_dir = HAL_SRNG_SRC_RING,
  2005. /* reg_start is not set because LMAC rings are not accessed
  2006. * from host
  2007. */
  2008. .reg_start = {},
  2009. .reg_size = {},
  2010. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2011. },
  2012. { /* RXDMA_MONITOR_STATUS */
  2013. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
  2014. .max_rings = 1,
  2015. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  2016. .lmac_ring = TRUE,
  2017. .ring_dir = HAL_SRNG_SRC_RING,
  2018. /* reg_start is not set because LMAC rings are not accessed
  2019. * from host
  2020. */
  2021. .reg_start = {},
  2022. .reg_size = {},
  2023. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2024. },
  2025. { /* RXDMA_MONITOR_DST */
  2026. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
  2027. .max_rings = 1,
  2028. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  2029. .lmac_ring = TRUE,
  2030. .ring_dir = HAL_SRNG_DST_RING,
  2031. /* reg_start is not set because LMAC rings are not accessed
  2032. * from host
  2033. */
  2034. .reg_start = {},
  2035. .reg_size = {},
  2036. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2037. },
  2038. { /* RXDMA_MONITOR_DESC */
  2039. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
  2040. .max_rings = 1,
  2041. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  2042. .lmac_ring = TRUE,
  2043. .ring_dir = HAL_SRNG_SRC_RING,
  2044. /* reg_start is not set because LMAC rings are not accessed
  2045. * from host
  2046. */
  2047. .reg_start = {},
  2048. .reg_size = {},
  2049. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2050. },
  2051. { /* DIR_BUF_RX_DMA_SRC */
  2052. .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  2053. /* one ring for spectral and one ring for cfr */
  2054. .max_rings = 2,
  2055. .entry_size = 2,
  2056. .lmac_ring = TRUE,
  2057. .ring_dir = HAL_SRNG_SRC_RING,
  2058. /* reg_start is not set because LMAC rings are not accessed
  2059. * from host
  2060. */
  2061. .reg_start = {},
  2062. .reg_size = {},
  2063. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2064. },
  2065. #ifdef WLAN_FEATURE_CIF_CFR
  2066. { /* WIFI_POS_SRC */
  2067. .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
  2068. .max_rings = 1,
  2069. .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
  2070. .lmac_ring = TRUE,
  2071. .ring_dir = HAL_SRNG_SRC_RING,
  2072. /* reg_start is not set because LMAC rings are not accessed
  2073. * from host
  2074. */
  2075. .reg_start = {},
  2076. .reg_size = {},
  2077. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  2078. },
  2079. #endif
  2080. { /* REO2PPE */ 0},
  2081. { /* PPE2TCL */ 0},
  2082. { /* PPE_RELEASE */ 0},
  2083. { /* TX_MONITOR_BUF */ 0},
  2084. { /* TX_MONITOR_DST */ 0},
  2085. { /* SW2RXDMA_NEW */ 0},
  2086. };
  2087. /**
  2088. * hal_qca5018_attach()- Attach 5018 target specific hal_soc ops,
  2089. * offset and srng table
  2090. * Return: void
  2091. */
  2092. void hal_qca5018_attach(struct hal_soc *hal_soc)
  2093. {
  2094. hal_soc->hw_srng_table = hw_srng_table_5018;
  2095. hal_srng_hw_reg_offset_init_generic(hal_soc);
  2096. hal_hw_txrx_default_ops_attach_li(hal_soc);
  2097. hal_hw_txrx_ops_attach_qca5018(hal_soc);
  2098. }