swr-mstr-ctrl.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _SWR_WCD_CTRL_H
  6. #define _SWR_WCD_CTRL_H
  7. #include <linux/module.h>
  8. #include <soc/swr-wcd.h>
  9. #define SWR_ROW_48 0
  10. #define SWR_ROW_50 1
  11. #define SWR_ROW_64 2
  12. #define SWR_MAX_COL 7 /* Cols = 16 */
  13. #define SWR_MIN_COL 0 /* Cols = 2 */
  14. #define SWR_WCD_NAME "swr-wcd"
  15. #define SWR_MSTR_PORT_LEN 8 /* Number of master ports */
  16. #define SWRM_VERSION_1_0 0x01010000
  17. #define SWRM_VERSION_1_2 0x01030000
  18. #define SWRM_VERSION_1_3 0x01040000
  19. #define SWRM_VERSION_1_5 0x01050000
  20. #define SWR_MAX_CH_PER_PORT 8
  21. #define SWR_MAX_SLAVE_DEVICES 11
  22. enum {
  23. SWR_MSTR_PAUSE,
  24. SWR_MSTR_RESUME,
  25. SWR_MSTR_UP,
  26. SWR_MSTR_DOWN,
  27. SWR_MSTR_SSR,
  28. };
  29. enum {
  30. SWR_IRQ_FREE,
  31. SWR_IRQ_REGISTER,
  32. };
  33. enum {
  34. SWR_DAC_PORT,
  35. SWR_COMP_PORT,
  36. SWR_BOOST_PORT,
  37. SWR_VISENSE_PORT,
  38. };
  39. struct usecase {
  40. u8 num_port;
  41. u8 num_ch;
  42. u32 chrate;
  43. };
  44. struct port_params {
  45. u8 si;
  46. u8 off1;
  47. u8 off2;
  48. u8 hstart;/* head start */
  49. u8 hstop; /* head stop */
  50. u8 wd_len;/* word length */
  51. u8 bp_mode; /* block pack mode */
  52. u8 bgp_ctrl;/* block group control */
  53. u8 lane_ctrl;/* lane to be used */
  54. };
  55. struct swrm_mports {
  56. struct list_head port_req_list;
  57. bool port_en;
  58. u8 ch_en;
  59. u8 req_ch;
  60. u8 ch_rate;
  61. u8 offset1;
  62. u8 offset2;
  63. u8 sinterval;
  64. u8 hstart;
  65. u8 hstop;
  66. u8 blk_grp_count;
  67. u8 blk_pack_mode;
  68. u8 word_length;
  69. u8 lane_ctrl;
  70. };
  71. struct swrm_port_type {
  72. u8 port_type;
  73. u8 ch_mask;
  74. };
  75. struct swr_ctrl_platform_data {
  76. void *handle; /* holds priv data */
  77. int (*read)(void *handle, int reg);
  78. int (*write)(void *handle, int reg, int val);
  79. int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
  80. int (*clk)(void *handle, bool enable);
  81. int (*reg_irq)(void *handle, irqreturn_t(*irq_handler)(int irq,
  82. void *data), void *swr_handle, int type);
  83. };
  84. struct swr_mstr_ctrl {
  85. struct swr_master master;
  86. struct device *dev;
  87. struct resource *supplies;
  88. struct clk *mclk;
  89. int clk_ref_count;
  90. struct completion clk_off_complete;
  91. struct completion reset;
  92. struct completion broadcast;
  93. struct mutex clklock;
  94. struct mutex iolock;
  95. struct mutex devlock;
  96. struct mutex mlock;
  97. struct mutex reslock;
  98. u32 swrm_base_reg;
  99. char __iomem *swrm_dig_base;
  100. u8 rcmd_id;
  101. u8 wcmd_id;
  102. u32 master_id;
  103. void *handle; /* SWR Master handle from client for read and writes */
  104. int (*read)(void *handle, int reg);
  105. int (*write)(void *handle, int reg, int val);
  106. int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
  107. int (*clk)(void *handle, bool enable);
  108. int (*reg_irq)(void *handle, irqreturn_t(*irq_handler)(int irq,
  109. void *data), void *swr_handle, int type);
  110. int irq;
  111. int wake_irq;
  112. int version;
  113. int mclk_freq;
  114. u32 num_dev;
  115. int slave_status;
  116. struct swrm_mports mport_cfg[SWR_MAX_MSTR_PORT_NUM];
  117. struct list_head port_req_list;
  118. unsigned long port_req_pending;
  119. int state;
  120. struct platform_device *pdev;
  121. int num_rx_chs;
  122. u8 num_cfg_devs;
  123. struct mutex force_down_lock;
  124. int force_down_state;
  125. struct notifier_block event_notifier;
  126. struct work_struct dc_presence_work;
  127. u8 num_ports;
  128. struct swrm_port_type
  129. port_mapping[SWR_MSTR_PORT_LEN][SWR_MAX_CH_PER_PORT];
  130. int swr_irq;
  131. u32 clk_stop_mode0_supp;
  132. struct work_struct wakeup_work;
  133. u32 ipc_wakeup;
  134. bool dev_up;
  135. bool ipc_wakeup_triggered;
  136. };
  137. #endif /* _SWR_WCD_CTRL_H */