dp_tx.c 110 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167
  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "enet.h"
  34. #include "dp_internal.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. /* TODO Add support in TSO */
  42. #define DP_DESC_NUM_FRAG(x) 0
  43. /* disable TQM_BYPASS */
  44. #define TQM_BYPASS_WAR 0
  45. /* invalid peer id for reinject*/
  46. #define DP_INVALID_PEER 0XFFFE
  47. /*mapping between hal encrypt type and cdp_sec_type*/
  48. #define MAX_CDP_SEC_TYPE 12
  49. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  50. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  51. HAL_TX_ENCRYPT_TYPE_WEP_128,
  52. HAL_TX_ENCRYPT_TYPE_WEP_104,
  53. HAL_TX_ENCRYPT_TYPE_WEP_40,
  54. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  56. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  57. HAL_TX_ENCRYPT_TYPE_WAPI,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  59. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  62. #ifdef QCA_TX_LIMIT_CHECK
  63. /**
  64. * dp_tx_limit_check - Check if allocated tx descriptors reached
  65. * soc max limit and pdev max limit
  66. * @vdev: DP vdev handle
  67. *
  68. * Return: true if allocated tx descriptors reached max configured value, else
  69. * false
  70. */
  71. static inline bool
  72. dp_tx_limit_check(struct dp_vdev *vdev)
  73. {
  74. struct dp_pdev *pdev = vdev->pdev;
  75. struct dp_soc *soc = pdev->soc;
  76. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  77. soc->num_tx_allowed) {
  78. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  79. "%s: queued packets are more than max tx, drop the frame",
  80. __func__);
  81. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  82. return true;
  83. }
  84. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  85. pdev->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. return false;
  93. }
  94. /**
  95. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  96. * @vdev: DP pdev handle
  97. *
  98. * Return: void
  99. */
  100. static inline void
  101. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  102. {
  103. struct dp_soc *soc = pdev->soc;
  104. qdf_atomic_inc(&pdev->num_tx_outstanding);
  105. qdf_atomic_inc(&soc->num_tx_outstanding);
  106. }
  107. /**
  108. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  109. * @vdev: DP pdev handle
  110. *
  111. * Return: void
  112. */
  113. static inline void
  114. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  115. {
  116. struct dp_soc *soc = pdev->soc;
  117. qdf_atomic_dec(&pdev->num_tx_outstanding);
  118. qdf_atomic_dec(&soc->num_tx_outstanding);
  119. }
  120. #else //QCA_TX_LIMIT_CHECK
  121. static inline bool
  122. dp_tx_limit_check(struct dp_vdev *vdev)
  123. {
  124. return false;
  125. }
  126. static inline void
  127. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  128. {
  129. }
  130. static inline void
  131. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  132. {
  133. }
  134. #endif //QCA_TX_LIMIT_CHECK
  135. #if defined(FEATURE_TSO)
  136. /**
  137. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  138. *
  139. * @soc - core txrx main context
  140. * @seg_desc - tso segment descriptor
  141. * @num_seg_desc - tso number segment descriptor
  142. */
  143. static void dp_tx_tso_unmap_segment(
  144. struct dp_soc *soc,
  145. struct qdf_tso_seg_elem_t *seg_desc,
  146. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  147. {
  148. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  149. if (qdf_unlikely(!seg_desc)) {
  150. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  151. __func__, __LINE__);
  152. qdf_assert(0);
  153. } else if (qdf_unlikely(!num_seg_desc)) {
  154. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  155. __func__, __LINE__);
  156. qdf_assert(0);
  157. } else {
  158. bool is_last_seg;
  159. /* no tso segment left to do dma unmap */
  160. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  161. return;
  162. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  163. true : false;
  164. qdf_nbuf_unmap_tso_segment(soc->osdev,
  165. seg_desc, is_last_seg);
  166. num_seg_desc->num_seg.tso_cmn_num_seg--;
  167. }
  168. }
  169. /**
  170. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  171. * back to the freelist
  172. *
  173. * @soc - soc device handle
  174. * @tx_desc - Tx software descriptor
  175. */
  176. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  177. struct dp_tx_desc_s *tx_desc)
  178. {
  179. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  180. if (qdf_unlikely(!tx_desc->tso_desc)) {
  181. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  182. "%s %d TSO desc is NULL!",
  183. __func__, __LINE__);
  184. qdf_assert(0);
  185. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  186. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  187. "%s %d TSO num desc is NULL!",
  188. __func__, __LINE__);
  189. qdf_assert(0);
  190. } else {
  191. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  192. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  193. /* Add the tso num segment into the free list */
  194. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  195. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  196. tx_desc->tso_num_desc);
  197. tx_desc->tso_num_desc = NULL;
  198. }
  199. /* Add the tso segment into the free list*/
  200. dp_tx_tso_desc_free(soc,
  201. tx_desc->pool_id, tx_desc->tso_desc);
  202. tx_desc->tso_desc = NULL;
  203. }
  204. }
  205. #else
  206. static void dp_tx_tso_unmap_segment(
  207. struct dp_soc *soc,
  208. struct qdf_tso_seg_elem_t *seg_desc,
  209. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  210. {
  211. }
  212. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  213. struct dp_tx_desc_s *tx_desc)
  214. {
  215. }
  216. #endif
  217. /**
  218. * dp_tx_desc_release() - Release Tx Descriptor
  219. * @tx_desc : Tx Descriptor
  220. * @desc_pool_id: Descriptor Pool ID
  221. *
  222. * Deallocate all resources attached to Tx descriptor and free the Tx
  223. * descriptor.
  224. *
  225. * Return:
  226. */
  227. static void
  228. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  229. {
  230. struct dp_pdev *pdev = tx_desc->pdev;
  231. struct dp_soc *soc;
  232. uint8_t comp_status = 0;
  233. qdf_assert(pdev);
  234. soc = pdev->soc;
  235. if (tx_desc->frm_type == dp_tx_frm_tso)
  236. dp_tx_tso_desc_release(soc, tx_desc);
  237. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  238. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  239. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  240. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  241. dp_tx_outstanding_dec(pdev);
  242. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  243. qdf_atomic_dec(&pdev->num_tx_exception);
  244. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  245. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  246. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  247. soc->hal_soc);
  248. else
  249. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  250. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  251. "Tx Completion Release desc %d status %d outstanding %d",
  252. tx_desc->id, comp_status,
  253. qdf_atomic_read(&pdev->num_tx_outstanding));
  254. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  255. return;
  256. }
  257. /**
  258. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  259. * @vdev: DP vdev Handle
  260. * @nbuf: skb
  261. * @msdu_info: msdu_info required to create HTT metadata
  262. *
  263. * Prepares and fills HTT metadata in the frame pre-header for special frames
  264. * that should be transmitted using varying transmit parameters.
  265. * There are 2 VDEV modes that currently needs this special metadata -
  266. * 1) Mesh Mode
  267. * 2) DSRC Mode
  268. *
  269. * Return: HTT metadata size
  270. *
  271. */
  272. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  273. struct dp_tx_msdu_info_s *msdu_info)
  274. {
  275. uint32_t *meta_data = msdu_info->meta_data;
  276. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  277. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  278. uint8_t htt_desc_size;
  279. /* Size rounded of multiple of 8 bytes */
  280. uint8_t htt_desc_size_aligned;
  281. uint8_t *hdr = NULL;
  282. /*
  283. * Metadata - HTT MSDU Extension header
  284. */
  285. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  286. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  287. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  288. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  289. meta_data[0])) {
  290. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  291. htt_desc_size_aligned)) {
  292. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  293. htt_desc_size_aligned);
  294. if (!nbuf) {
  295. /*
  296. * qdf_nbuf_realloc_headroom won't do skb_clone
  297. * as skb_realloc_headroom does. so, no free is
  298. * needed here.
  299. */
  300. DP_STATS_INC(vdev,
  301. tx_i.dropped.headroom_insufficient,
  302. 1);
  303. qdf_print(" %s[%d] skb_realloc_headroom failed",
  304. __func__, __LINE__);
  305. return 0;
  306. }
  307. }
  308. /* Fill and add HTT metaheader */
  309. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  310. if (!hdr) {
  311. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  312. "Error in filling HTT metadata");
  313. return 0;
  314. }
  315. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  316. } else if (vdev->opmode == wlan_op_mode_ocb) {
  317. /* Todo - Add support for DSRC */
  318. }
  319. return htt_desc_size_aligned;
  320. }
  321. /**
  322. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  323. * @tso_seg: TSO segment to process
  324. * @ext_desc: Pointer to MSDU extension descriptor
  325. *
  326. * Return: void
  327. */
  328. #if defined(FEATURE_TSO)
  329. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  330. void *ext_desc)
  331. {
  332. uint8_t num_frag;
  333. uint32_t tso_flags;
  334. /*
  335. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  336. * tcp_flag_mask
  337. *
  338. * Checksum enable flags are set in TCL descriptor and not in Extension
  339. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  340. */
  341. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  342. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  343. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  344. tso_seg->tso_flags.ip_len);
  345. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  346. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  347. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  348. uint32_t lo = 0;
  349. uint32_t hi = 0;
  350. qdf_dmaaddr_to_32s(
  351. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  352. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  353. tso_seg->tso_frags[num_frag].length);
  354. }
  355. return;
  356. }
  357. #else
  358. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  359. void *ext_desc)
  360. {
  361. return;
  362. }
  363. #endif
  364. #if defined(FEATURE_TSO)
  365. /**
  366. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  367. * allocated and free them
  368. *
  369. * @soc: soc handle
  370. * @free_seg: list of tso segments
  371. * @msdu_info: msdu descriptor
  372. *
  373. * Return - void
  374. */
  375. static void dp_tx_free_tso_seg_list(
  376. struct dp_soc *soc,
  377. struct qdf_tso_seg_elem_t *free_seg,
  378. struct dp_tx_msdu_info_s *msdu_info)
  379. {
  380. struct qdf_tso_seg_elem_t *next_seg;
  381. while (free_seg) {
  382. next_seg = free_seg->next;
  383. dp_tx_tso_desc_free(soc,
  384. msdu_info->tx_queue.desc_pool_id,
  385. free_seg);
  386. free_seg = next_seg;
  387. }
  388. }
  389. /**
  390. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  391. * allocated and free them
  392. *
  393. * @soc: soc handle
  394. * @free_num_seg: list of tso number segments
  395. * @msdu_info: msdu descriptor
  396. * Return - void
  397. */
  398. static void dp_tx_free_tso_num_seg_list(
  399. struct dp_soc *soc,
  400. struct qdf_tso_num_seg_elem_t *free_num_seg,
  401. struct dp_tx_msdu_info_s *msdu_info)
  402. {
  403. struct qdf_tso_num_seg_elem_t *next_num_seg;
  404. while (free_num_seg) {
  405. next_num_seg = free_num_seg->next;
  406. dp_tso_num_seg_free(soc,
  407. msdu_info->tx_queue.desc_pool_id,
  408. free_num_seg);
  409. free_num_seg = next_num_seg;
  410. }
  411. }
  412. /**
  413. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  414. * do dma unmap for each segment
  415. *
  416. * @soc: soc handle
  417. * @free_seg: list of tso segments
  418. * @num_seg_desc: tso number segment descriptor
  419. *
  420. * Return - void
  421. */
  422. static void dp_tx_unmap_tso_seg_list(
  423. struct dp_soc *soc,
  424. struct qdf_tso_seg_elem_t *free_seg,
  425. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  426. {
  427. struct qdf_tso_seg_elem_t *next_seg;
  428. if (qdf_unlikely(!num_seg_desc)) {
  429. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  430. return;
  431. }
  432. while (free_seg) {
  433. next_seg = free_seg->next;
  434. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  435. free_seg = next_seg;
  436. }
  437. }
  438. /**
  439. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  440. * free the tso segments descriptor and
  441. * tso num segments descriptor
  442. *
  443. * @soc: soc handle
  444. * @msdu_info: msdu descriptor
  445. * @tso_seg_unmap: flag to show if dma unmap is necessary
  446. *
  447. * Return - void
  448. */
  449. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  450. struct dp_tx_msdu_info_s *msdu_info,
  451. bool tso_seg_unmap)
  452. {
  453. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  454. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  455. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  456. tso_info->tso_num_seg_list;
  457. /* do dma unmap for each segment */
  458. if (tso_seg_unmap)
  459. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  460. /* free all tso number segment descriptor though looks only have 1 */
  461. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  462. /* free all tso segment descriptor */
  463. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  464. }
  465. /**
  466. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  467. * @vdev: virtual device handle
  468. * @msdu: network buffer
  469. * @msdu_info: meta data associated with the msdu
  470. *
  471. * Return: QDF_STATUS_SUCCESS success
  472. */
  473. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  474. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  475. {
  476. struct qdf_tso_seg_elem_t *tso_seg;
  477. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  478. struct dp_soc *soc = vdev->pdev->soc;
  479. struct qdf_tso_info_t *tso_info;
  480. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  481. tso_info = &msdu_info->u.tso_info;
  482. tso_info->curr_seg = NULL;
  483. tso_info->tso_seg_list = NULL;
  484. tso_info->num_segs = num_seg;
  485. msdu_info->frm_type = dp_tx_frm_tso;
  486. tso_info->tso_num_seg_list = NULL;
  487. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  488. while (num_seg) {
  489. tso_seg = dp_tx_tso_desc_alloc(
  490. soc, msdu_info->tx_queue.desc_pool_id);
  491. if (tso_seg) {
  492. tso_seg->next = tso_info->tso_seg_list;
  493. tso_info->tso_seg_list = tso_seg;
  494. num_seg--;
  495. } else {
  496. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  497. __func__);
  498. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  499. return QDF_STATUS_E_NOMEM;
  500. }
  501. }
  502. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  503. tso_num_seg = dp_tso_num_seg_alloc(soc,
  504. msdu_info->tx_queue.desc_pool_id);
  505. if (tso_num_seg) {
  506. tso_num_seg->next = tso_info->tso_num_seg_list;
  507. tso_info->tso_num_seg_list = tso_num_seg;
  508. } else {
  509. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  510. __func__);
  511. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  512. return QDF_STATUS_E_NOMEM;
  513. }
  514. msdu_info->num_seg =
  515. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  516. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  517. msdu_info->num_seg);
  518. if (!(msdu_info->num_seg)) {
  519. /*
  520. * Free allocated TSO seg desc and number seg desc,
  521. * do unmap for segments if dma map has done.
  522. */
  523. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  524. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  525. return QDF_STATUS_E_INVAL;
  526. }
  527. tso_info->curr_seg = tso_info->tso_seg_list;
  528. return QDF_STATUS_SUCCESS;
  529. }
  530. #else
  531. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  532. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  533. {
  534. return QDF_STATUS_E_NOMEM;
  535. }
  536. #endif
  537. /**
  538. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  539. * @vdev: DP Vdev handle
  540. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  541. * @desc_pool_id: Descriptor Pool ID
  542. *
  543. * Return:
  544. */
  545. static
  546. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  547. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  548. {
  549. uint8_t i;
  550. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  551. struct dp_tx_seg_info_s *seg_info;
  552. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  553. struct dp_soc *soc = vdev->pdev->soc;
  554. /* Allocate an extension descriptor */
  555. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  556. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  557. if (!msdu_ext_desc) {
  558. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  559. return NULL;
  560. }
  561. if (msdu_info->exception_fw &&
  562. qdf_unlikely(vdev->mesh_vdev)) {
  563. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  564. &msdu_info->meta_data[0],
  565. sizeof(struct htt_tx_msdu_desc_ext2_t));
  566. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  567. }
  568. switch (msdu_info->frm_type) {
  569. case dp_tx_frm_sg:
  570. case dp_tx_frm_me:
  571. case dp_tx_frm_raw:
  572. seg_info = msdu_info->u.sg_info.curr_seg;
  573. /* Update the buffer pointers in MSDU Extension Descriptor */
  574. for (i = 0; i < seg_info->frag_cnt; i++) {
  575. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  576. seg_info->frags[i].paddr_lo,
  577. seg_info->frags[i].paddr_hi,
  578. seg_info->frags[i].len);
  579. }
  580. break;
  581. case dp_tx_frm_tso:
  582. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  583. &cached_ext_desc[0]);
  584. break;
  585. default:
  586. break;
  587. }
  588. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  589. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  590. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  591. msdu_ext_desc->vaddr);
  592. return msdu_ext_desc;
  593. }
  594. /**
  595. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  596. *
  597. * @skb: skb to be traced
  598. * @msdu_id: msdu_id of the packet
  599. * @vdev_id: vdev_id of the packet
  600. *
  601. * Return: None
  602. */
  603. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  604. uint8_t vdev_id)
  605. {
  606. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  607. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  608. DPTRACE(qdf_dp_trace_ptr(skb,
  609. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  610. QDF_TRACE_DEFAULT_PDEV_ID,
  611. qdf_nbuf_data_addr(skb),
  612. sizeof(qdf_nbuf_data(skb)),
  613. msdu_id, vdev_id));
  614. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  615. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  616. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  617. msdu_id, QDF_TX));
  618. }
  619. /**
  620. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  621. * @vdev: DP vdev handle
  622. * @nbuf: skb
  623. * @desc_pool_id: Descriptor pool ID
  624. * @meta_data: Metadata to the fw
  625. * @tx_exc_metadata: Handle that holds exception path metadata
  626. * Allocate and prepare Tx descriptor with msdu information.
  627. *
  628. * Return: Pointer to Tx Descriptor on success,
  629. * NULL on failure
  630. */
  631. static
  632. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  633. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  634. struct dp_tx_msdu_info_s *msdu_info,
  635. struct cdp_tx_exception_metadata *tx_exc_metadata)
  636. {
  637. uint8_t align_pad;
  638. uint8_t is_exception = 0;
  639. uint8_t htt_hdr_size;
  640. qdf_ether_header_t *eh;
  641. struct dp_tx_desc_s *tx_desc;
  642. struct dp_pdev *pdev = vdev->pdev;
  643. struct dp_soc *soc = pdev->soc;
  644. if (dp_tx_limit_check(vdev))
  645. return NULL;
  646. /* Allocate software Tx descriptor */
  647. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  648. if (qdf_unlikely(!tx_desc)) {
  649. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  650. return NULL;
  651. }
  652. dp_tx_outstanding_inc(pdev);
  653. /* Initialize the SW tx descriptor */
  654. tx_desc->nbuf = nbuf;
  655. tx_desc->frm_type = dp_tx_frm_std;
  656. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  657. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  658. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  659. tx_desc->vdev = vdev;
  660. tx_desc->pdev = pdev;
  661. tx_desc->msdu_ext_desc = NULL;
  662. tx_desc->pkt_offset = 0;
  663. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  664. if (qdf_unlikely(vdev->multipass_en)) {
  665. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  666. goto failure;
  667. }
  668. /*
  669. * For special modes (vdev_type == ocb or mesh), data frames should be
  670. * transmitted using varying transmit parameters (tx spec) which include
  671. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  672. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  673. * These frames are sent as exception packets to firmware.
  674. *
  675. * HW requirement is that metadata should always point to a
  676. * 8-byte aligned address. So we add alignment pad to start of buffer.
  677. * HTT Metadata should be ensured to be multiple of 8-bytes,
  678. * to get 8-byte aligned start address along with align_pad added
  679. *
  680. * |-----------------------------|
  681. * | |
  682. * |-----------------------------| <-----Buffer Pointer Address given
  683. * | | ^ in HW descriptor (aligned)
  684. * | HTT Metadata | |
  685. * | | |
  686. * | | | Packet Offset given in descriptor
  687. * | | |
  688. * |-----------------------------| |
  689. * | Alignment Pad | v
  690. * |-----------------------------| <----- Actual buffer start address
  691. * | SKB Data | (Unaligned)
  692. * | |
  693. * | |
  694. * | |
  695. * | |
  696. * | |
  697. * |-----------------------------|
  698. */
  699. if (qdf_unlikely((msdu_info->exception_fw)) ||
  700. (vdev->opmode == wlan_op_mode_ocb) ||
  701. (tx_exc_metadata &&
  702. tx_exc_metadata->is_tx_sniffer)) {
  703. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  704. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  705. DP_STATS_INC(vdev,
  706. tx_i.dropped.headroom_insufficient, 1);
  707. goto failure;
  708. }
  709. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  710. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  711. "qdf_nbuf_push_head failed");
  712. goto failure;
  713. }
  714. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  715. msdu_info);
  716. if (htt_hdr_size == 0)
  717. goto failure;
  718. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  719. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  720. is_exception = 1;
  721. }
  722. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  723. qdf_nbuf_map(soc->osdev, nbuf,
  724. QDF_DMA_TO_DEVICE))) {
  725. /* Handle failure */
  726. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  727. "qdf_nbuf_map failed");
  728. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  729. goto failure;
  730. }
  731. if (qdf_unlikely(vdev->nawds_enabled)) {
  732. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  733. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  734. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  735. is_exception = 1;
  736. }
  737. }
  738. #if !TQM_BYPASS_WAR
  739. if (is_exception || tx_exc_metadata)
  740. #endif
  741. {
  742. /* Temporary WAR due to TQM VP issues */
  743. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  744. qdf_atomic_inc(&pdev->num_tx_exception);
  745. }
  746. return tx_desc;
  747. failure:
  748. dp_tx_desc_release(tx_desc, desc_pool_id);
  749. return NULL;
  750. }
  751. /**
  752. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  753. * @vdev: DP vdev handle
  754. * @nbuf: skb
  755. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  756. * @desc_pool_id : Descriptor Pool ID
  757. *
  758. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  759. * information. For frames wth fragments, allocate and prepare
  760. * an MSDU extension descriptor
  761. *
  762. * Return: Pointer to Tx Descriptor on success,
  763. * NULL on failure
  764. */
  765. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  766. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  767. uint8_t desc_pool_id)
  768. {
  769. struct dp_tx_desc_s *tx_desc;
  770. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  771. struct dp_pdev *pdev = vdev->pdev;
  772. struct dp_soc *soc = pdev->soc;
  773. if (dp_tx_limit_check(vdev))
  774. return NULL;
  775. /* Allocate software Tx descriptor */
  776. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  777. if (!tx_desc) {
  778. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  779. return NULL;
  780. }
  781. dp_tx_outstanding_inc(pdev);
  782. /* Initialize the SW tx descriptor */
  783. tx_desc->nbuf = nbuf;
  784. tx_desc->frm_type = msdu_info->frm_type;
  785. tx_desc->tx_encap_type = vdev->tx_encap_type;
  786. tx_desc->vdev = vdev;
  787. tx_desc->pdev = pdev;
  788. tx_desc->pkt_offset = 0;
  789. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  790. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  791. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  792. /* Handle scattered frames - TSO/SG/ME */
  793. /* Allocate and prepare an extension descriptor for scattered frames */
  794. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  795. if (!msdu_ext_desc) {
  796. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  797. "%s Tx Extension Descriptor Alloc Fail",
  798. __func__);
  799. goto failure;
  800. }
  801. #if TQM_BYPASS_WAR
  802. /* Temporary WAR due to TQM VP issues */
  803. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  804. qdf_atomic_inc(&pdev->num_tx_exception);
  805. #endif
  806. if (qdf_unlikely(msdu_info->exception_fw))
  807. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  808. tx_desc->msdu_ext_desc = msdu_ext_desc;
  809. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  810. return tx_desc;
  811. failure:
  812. dp_tx_desc_release(tx_desc, desc_pool_id);
  813. return NULL;
  814. }
  815. /**
  816. * dp_tx_prepare_raw() - Prepare RAW packet TX
  817. * @vdev: DP vdev handle
  818. * @nbuf: buffer pointer
  819. * @seg_info: Pointer to Segment info Descriptor to be prepared
  820. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  821. * descriptor
  822. *
  823. * Return:
  824. */
  825. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  826. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  827. {
  828. qdf_nbuf_t curr_nbuf = NULL;
  829. uint16_t total_len = 0;
  830. qdf_dma_addr_t paddr;
  831. int32_t i;
  832. int32_t mapped_buf_num = 0;
  833. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  834. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  835. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  836. /* Continue only if frames are of DATA type */
  837. if (!DP_FRAME_IS_DATA(qos_wh)) {
  838. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  839. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  840. "Pkt. recd is of not data type");
  841. goto error;
  842. }
  843. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  844. if (vdev->raw_mode_war &&
  845. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  846. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  847. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  848. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  849. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  850. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  851. QDF_DMA_TO_DEVICE)) {
  852. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  853. "%s dma map error ", __func__);
  854. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  855. mapped_buf_num = i;
  856. goto error;
  857. }
  858. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  859. seg_info->frags[i].paddr_lo = paddr;
  860. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  861. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  862. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  863. total_len += qdf_nbuf_len(curr_nbuf);
  864. }
  865. seg_info->frag_cnt = i;
  866. seg_info->total_len = total_len;
  867. seg_info->next = NULL;
  868. sg_info->curr_seg = seg_info;
  869. msdu_info->frm_type = dp_tx_frm_raw;
  870. msdu_info->num_seg = 1;
  871. return nbuf;
  872. error:
  873. i = 0;
  874. while (nbuf) {
  875. curr_nbuf = nbuf;
  876. if (i < mapped_buf_num) {
  877. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  878. i++;
  879. }
  880. nbuf = qdf_nbuf_next(nbuf);
  881. qdf_nbuf_free(curr_nbuf);
  882. }
  883. return NULL;
  884. }
  885. /**
  886. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  887. * @soc: DP soc handle
  888. * @nbuf: Buffer pointer
  889. *
  890. * unmap the chain of nbufs that belong to this RAW frame.
  891. *
  892. * Return: None
  893. */
  894. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  895. qdf_nbuf_t nbuf)
  896. {
  897. qdf_nbuf_t cur_nbuf = nbuf;
  898. do {
  899. qdf_nbuf_unmap(soc->osdev, cur_nbuf, QDF_DMA_TO_DEVICE);
  900. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  901. } while (cur_nbuf);
  902. }
  903. /**
  904. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  905. * @soc: DP Soc Handle
  906. * @vdev: DP vdev handle
  907. * @tx_desc: Tx Descriptor Handle
  908. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  909. * @fw_metadata: Metadata to send to Target Firmware along with frame
  910. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  911. * @tx_exc_metadata: Handle that holds exception path meta data
  912. *
  913. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  914. * from software Tx descriptor
  915. *
  916. * Return:
  917. */
  918. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  919. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  920. uint16_t fw_metadata, uint8_t ring_id,
  921. struct cdp_tx_exception_metadata
  922. *tx_exc_metadata)
  923. {
  924. uint8_t type;
  925. uint16_t length;
  926. void *hal_tx_desc, *hal_tx_desc_cached;
  927. qdf_dma_addr_t dma_addr;
  928. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  929. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  930. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  931. tx_exc_metadata->sec_type : vdev->sec_type);
  932. /* Return Buffer Manager ID */
  933. uint8_t bm_id = ring_id;
  934. hal_ring_handle_t hal_ring_hdl = soc->tcl_data_ring[ring_id].hal_srng;
  935. hal_tx_desc_cached = (void *) cached_desc;
  936. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  937. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  938. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  939. type = HAL_TX_BUF_TYPE_EXT_DESC;
  940. dma_addr = tx_desc->msdu_ext_desc->paddr;
  941. } else {
  942. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  943. type = HAL_TX_BUF_TYPE_BUFFER;
  944. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  945. }
  946. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  947. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  948. dma_addr, bm_id, tx_desc->id,
  949. type, soc->hal_soc);
  950. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  951. return QDF_STATUS_E_RESOURCES;
  952. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  953. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  954. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  955. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  956. vdev->pdev->lmac_id);
  957. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  958. vdev->search_type);
  959. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  960. vdev->bss_ast_hash);
  961. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  962. vdev->dscp_tid_map_id);
  963. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  964. sec_type_map[sec_type]);
  965. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  966. length, type, (uint64_t)dma_addr,
  967. tx_desc->pkt_offset, tx_desc->id);
  968. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  969. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  970. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  971. vdev->hal_desc_addr_search_flags);
  972. /* verify checksum offload configuration*/
  973. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  974. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  975. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  976. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  977. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  978. }
  979. if (tid != HTT_TX_EXT_TID_INVALID)
  980. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  981. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  982. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  983. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  984. /* Sync cached descriptor with HW */
  985. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  986. if (!hal_tx_desc) {
  987. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  988. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  989. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  990. return QDF_STATUS_E_RESOURCES;
  991. }
  992. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  993. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  994. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  995. return QDF_STATUS_SUCCESS;
  996. }
  997. /**
  998. * dp_cce_classify() - Classify the frame based on CCE rules
  999. * @vdev: DP vdev handle
  1000. * @nbuf: skb
  1001. *
  1002. * Classify frames based on CCE rules
  1003. * Return: bool( true if classified,
  1004. * else false)
  1005. */
  1006. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1007. {
  1008. qdf_ether_header_t *eh = NULL;
  1009. uint16_t ether_type;
  1010. qdf_llc_t *llcHdr;
  1011. qdf_nbuf_t nbuf_clone = NULL;
  1012. qdf_dot3_qosframe_t *qos_wh = NULL;
  1013. /* for mesh packets don't do any classification */
  1014. if (qdf_unlikely(vdev->mesh_vdev))
  1015. return false;
  1016. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1017. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1018. ether_type = eh->ether_type;
  1019. llcHdr = (qdf_llc_t *)(nbuf->data +
  1020. sizeof(qdf_ether_header_t));
  1021. } else {
  1022. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1023. /* For encrypted packets don't do any classification */
  1024. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1025. return false;
  1026. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1027. if (qdf_unlikely(
  1028. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1029. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1030. ether_type = *(uint16_t *)(nbuf->data
  1031. + QDF_IEEE80211_4ADDR_HDR_LEN
  1032. + sizeof(qdf_llc_t)
  1033. - sizeof(ether_type));
  1034. llcHdr = (qdf_llc_t *)(nbuf->data +
  1035. QDF_IEEE80211_4ADDR_HDR_LEN);
  1036. } else {
  1037. ether_type = *(uint16_t *)(nbuf->data
  1038. + QDF_IEEE80211_3ADDR_HDR_LEN
  1039. + sizeof(qdf_llc_t)
  1040. - sizeof(ether_type));
  1041. llcHdr = (qdf_llc_t *)(nbuf->data +
  1042. QDF_IEEE80211_3ADDR_HDR_LEN);
  1043. }
  1044. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1045. && (ether_type ==
  1046. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1047. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1048. return true;
  1049. }
  1050. }
  1051. return false;
  1052. }
  1053. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1054. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1055. sizeof(*llcHdr));
  1056. nbuf_clone = qdf_nbuf_clone(nbuf);
  1057. if (qdf_unlikely(nbuf_clone)) {
  1058. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1059. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1060. qdf_nbuf_pull_head(nbuf_clone,
  1061. sizeof(qdf_net_vlanhdr_t));
  1062. }
  1063. }
  1064. } else {
  1065. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1066. nbuf_clone = qdf_nbuf_clone(nbuf);
  1067. if (qdf_unlikely(nbuf_clone)) {
  1068. qdf_nbuf_pull_head(nbuf_clone,
  1069. sizeof(qdf_net_vlanhdr_t));
  1070. }
  1071. }
  1072. }
  1073. if (qdf_unlikely(nbuf_clone))
  1074. nbuf = nbuf_clone;
  1075. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1076. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1077. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1078. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1079. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1080. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1081. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1082. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1083. if (qdf_unlikely(nbuf_clone))
  1084. qdf_nbuf_free(nbuf_clone);
  1085. return true;
  1086. }
  1087. if (qdf_unlikely(nbuf_clone))
  1088. qdf_nbuf_free(nbuf_clone);
  1089. return false;
  1090. }
  1091. /**
  1092. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1093. * @vdev: DP vdev handle
  1094. * @nbuf: skb
  1095. *
  1096. * Extract the DSCP or PCP information from frame and map into TID value.
  1097. *
  1098. * Return: void
  1099. */
  1100. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1101. struct dp_tx_msdu_info_s *msdu_info)
  1102. {
  1103. uint8_t tos = 0, dscp_tid_override = 0;
  1104. uint8_t *hdr_ptr, *L3datap;
  1105. uint8_t is_mcast = 0;
  1106. qdf_ether_header_t *eh = NULL;
  1107. qdf_ethervlan_header_t *evh = NULL;
  1108. uint16_t ether_type;
  1109. qdf_llc_t *llcHdr;
  1110. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1111. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1112. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1113. eh = (qdf_ether_header_t *)nbuf->data;
  1114. hdr_ptr = eh->ether_dhost;
  1115. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1116. } else {
  1117. qdf_dot3_qosframe_t *qos_wh =
  1118. (qdf_dot3_qosframe_t *) nbuf->data;
  1119. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1120. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1121. return;
  1122. }
  1123. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1124. ether_type = eh->ether_type;
  1125. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1126. /*
  1127. * Check if packet is dot3 or eth2 type.
  1128. */
  1129. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1130. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1131. sizeof(*llcHdr));
  1132. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1133. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1134. sizeof(*llcHdr);
  1135. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1136. + sizeof(*llcHdr) +
  1137. sizeof(qdf_net_vlanhdr_t));
  1138. } else {
  1139. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1140. sizeof(*llcHdr);
  1141. }
  1142. } else {
  1143. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1144. evh = (qdf_ethervlan_header_t *) eh;
  1145. ether_type = evh->ether_type;
  1146. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1147. }
  1148. }
  1149. /*
  1150. * Find priority from IP TOS DSCP field
  1151. */
  1152. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1153. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1154. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1155. /* Only for unicast frames */
  1156. if (!is_mcast) {
  1157. /* send it on VO queue */
  1158. msdu_info->tid = DP_VO_TID;
  1159. }
  1160. } else {
  1161. /*
  1162. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1163. * from TOS byte.
  1164. */
  1165. tos = ip->ip_tos;
  1166. dscp_tid_override = 1;
  1167. }
  1168. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1169. /* TODO
  1170. * use flowlabel
  1171. *igmpmld cases to be handled in phase 2
  1172. */
  1173. unsigned long ver_pri_flowlabel;
  1174. unsigned long pri;
  1175. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1176. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1177. DP_IPV6_PRIORITY_SHIFT;
  1178. tos = pri;
  1179. dscp_tid_override = 1;
  1180. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1181. msdu_info->tid = DP_VO_TID;
  1182. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1183. /* Only for unicast frames */
  1184. if (!is_mcast) {
  1185. /* send ucast arp on VO queue */
  1186. msdu_info->tid = DP_VO_TID;
  1187. }
  1188. }
  1189. /*
  1190. * Assign all MCAST packets to BE
  1191. */
  1192. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1193. if (is_mcast) {
  1194. tos = 0;
  1195. dscp_tid_override = 1;
  1196. }
  1197. }
  1198. if (dscp_tid_override == 1) {
  1199. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1200. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1201. }
  1202. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1203. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1204. return;
  1205. }
  1206. /**
  1207. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1208. * @vdev: DP vdev handle
  1209. * @nbuf: skb
  1210. *
  1211. * Software based TID classification is required when more than 2 DSCP-TID
  1212. * mapping tables are needed.
  1213. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1214. *
  1215. * Return: void
  1216. */
  1217. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1218. struct dp_tx_msdu_info_s *msdu_info)
  1219. {
  1220. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1221. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1222. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1223. return;
  1224. /* for mesh packets don't do any classification */
  1225. if (qdf_unlikely(vdev->mesh_vdev))
  1226. return;
  1227. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1228. }
  1229. #ifdef FEATURE_WLAN_TDLS
  1230. /**
  1231. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1232. * @tx_desc: TX descriptor
  1233. *
  1234. * Return: None
  1235. */
  1236. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1237. {
  1238. if (tx_desc->vdev) {
  1239. if (tx_desc->vdev->is_tdls_frame) {
  1240. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1241. tx_desc->vdev->is_tdls_frame = false;
  1242. }
  1243. }
  1244. }
  1245. /**
  1246. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1247. * @tx_desc: TX descriptor
  1248. * @vdev: datapath vdev handle
  1249. *
  1250. * Return: None
  1251. */
  1252. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1253. struct dp_vdev *vdev)
  1254. {
  1255. struct hal_tx_completion_status ts = {0};
  1256. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1257. if (qdf_unlikely(!vdev)) {
  1258. dp_err("vdev is null!");
  1259. return;
  1260. }
  1261. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1262. if (vdev->tx_non_std_data_callback.func) {
  1263. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1264. vdev->tx_non_std_data_callback.func(
  1265. vdev->tx_non_std_data_callback.ctxt,
  1266. nbuf, ts.status);
  1267. return;
  1268. }
  1269. }
  1270. #else
  1271. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1272. {
  1273. }
  1274. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1275. struct dp_vdev *vdev)
  1276. {
  1277. }
  1278. #endif
  1279. /**
  1280. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1281. * @vdev: DP vdev handle
  1282. * @nbuf: skb
  1283. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1284. * @meta_data: Metadata to the fw
  1285. * @tx_q: Tx queue to be used for this Tx frame
  1286. * @peer_id: peer_id of the peer in case of NAWDS frames
  1287. * @tx_exc_metadata: Handle that holds exception path metadata
  1288. *
  1289. * Return: NULL on success,
  1290. * nbuf when it fails to send
  1291. */
  1292. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1293. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1294. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1295. {
  1296. struct dp_pdev *pdev = vdev->pdev;
  1297. struct dp_soc *soc = pdev->soc;
  1298. struct dp_tx_desc_s *tx_desc;
  1299. QDF_STATUS status;
  1300. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1301. hal_ring_handle_t hal_ring_hdl =
  1302. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1303. uint16_t htt_tcl_metadata = 0;
  1304. uint8_t tid = msdu_info->tid;
  1305. struct cdp_tid_tx_stats *tid_stats = NULL;
  1306. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1307. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1308. msdu_info, tx_exc_metadata);
  1309. if (!tx_desc) {
  1310. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1311. vdev, tx_q->desc_pool_id);
  1312. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1313. tid_stats = &pdev->stats.tid_stats.
  1314. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1315. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1316. return nbuf;
  1317. }
  1318. if (qdf_unlikely(soc->cce_disable)) {
  1319. if (dp_cce_classify(vdev, nbuf) == true) {
  1320. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1321. tid = DP_VO_TID;
  1322. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1323. }
  1324. }
  1325. dp_tx_update_tdls_flags(tx_desc);
  1326. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1327. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1328. "%s %d : HAL RING Access Failed -- %pK",
  1329. __func__, __LINE__, hal_ring_hdl);
  1330. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1331. tid_stats = &pdev->stats.tid_stats.
  1332. tid_tx_stats[tx_q->ring_id][tid];
  1333. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1334. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1335. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1336. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1337. goto fail_return;
  1338. }
  1339. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1340. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1341. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1342. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1343. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1344. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1345. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1346. peer_id);
  1347. } else
  1348. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1349. if (msdu_info->exception_fw) {
  1350. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1351. }
  1352. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1353. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1354. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1355. if (status != QDF_STATUS_SUCCESS) {
  1356. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1357. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1358. __func__, tx_desc, tx_q->ring_id);
  1359. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1360. tid_stats = &pdev->stats.tid_stats.
  1361. tid_tx_stats[tx_q->ring_id][tid];
  1362. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1363. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1364. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1365. goto fail_return;
  1366. }
  1367. nbuf = NULL;
  1368. fail_return:
  1369. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1370. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1371. hif_pm_runtime_put(soc->hif_handle);
  1372. } else {
  1373. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1374. }
  1375. return nbuf;
  1376. }
  1377. /**
  1378. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1379. * @vdev: DP vdev handle
  1380. * @nbuf: skb
  1381. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1382. *
  1383. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1384. *
  1385. * Return: NULL on success,
  1386. * nbuf when it fails to send
  1387. */
  1388. #if QDF_LOCK_STATS
  1389. noinline
  1390. #else
  1391. #endif
  1392. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1393. struct dp_tx_msdu_info_s *msdu_info)
  1394. {
  1395. uint8_t i;
  1396. struct dp_pdev *pdev = vdev->pdev;
  1397. struct dp_soc *soc = pdev->soc;
  1398. struct dp_tx_desc_s *tx_desc;
  1399. bool is_cce_classified = false;
  1400. QDF_STATUS status;
  1401. uint16_t htt_tcl_metadata = 0;
  1402. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1403. hal_ring_handle_t hal_ring_hdl =
  1404. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1405. struct cdp_tid_tx_stats *tid_stats = NULL;
  1406. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1407. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1408. "%s %d : HAL RING Access Failed -- %pK",
  1409. __func__, __LINE__, hal_ring_hdl);
  1410. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1411. tid_stats = &pdev->stats.tid_stats.
  1412. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1413. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1414. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1415. return nbuf;
  1416. }
  1417. if (qdf_unlikely(soc->cce_disable)) {
  1418. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1419. if (is_cce_classified) {
  1420. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1421. msdu_info->tid = DP_VO_TID;
  1422. }
  1423. }
  1424. if (msdu_info->frm_type == dp_tx_frm_me)
  1425. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1426. i = 0;
  1427. /* Print statement to track i and num_seg */
  1428. /*
  1429. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1430. * descriptors using information in msdu_info
  1431. */
  1432. while (i < msdu_info->num_seg) {
  1433. /*
  1434. * Setup Tx descriptor for an MSDU, and MSDU extension
  1435. * descriptor
  1436. */
  1437. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1438. tx_q->desc_pool_id);
  1439. if (!tx_desc) {
  1440. if (msdu_info->frm_type == dp_tx_frm_me) {
  1441. dp_tx_me_free_buf(pdev,
  1442. (void *)(msdu_info->u.sg_info
  1443. .curr_seg->frags[0].vaddr));
  1444. }
  1445. goto done;
  1446. }
  1447. if (msdu_info->frm_type == dp_tx_frm_me) {
  1448. tx_desc->me_buffer =
  1449. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1450. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1451. }
  1452. if (is_cce_classified)
  1453. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1454. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1455. if (msdu_info->exception_fw) {
  1456. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1457. }
  1458. /*
  1459. * Enqueue the Tx MSDU descriptor to HW for transmit
  1460. */
  1461. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1462. htt_tcl_metadata, tx_q->ring_id, NULL);
  1463. if (status != QDF_STATUS_SUCCESS) {
  1464. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1465. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1466. __func__, tx_desc, tx_q->ring_id);
  1467. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1468. tid_stats = &pdev->stats.tid_stats.
  1469. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1470. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1471. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1472. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1473. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1474. goto done;
  1475. }
  1476. /*
  1477. * TODO
  1478. * if tso_info structure can be modified to have curr_seg
  1479. * as first element, following 2 blocks of code (for TSO and SG)
  1480. * can be combined into 1
  1481. */
  1482. /*
  1483. * For frames with multiple segments (TSO, ME), jump to next
  1484. * segment.
  1485. */
  1486. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1487. if (msdu_info->u.tso_info.curr_seg->next) {
  1488. msdu_info->u.tso_info.curr_seg =
  1489. msdu_info->u.tso_info.curr_seg->next;
  1490. /*
  1491. * If this is a jumbo nbuf, then increment the number of
  1492. * nbuf users for each additional segment of the msdu.
  1493. * This will ensure that the skb is freed only after
  1494. * receiving tx completion for all segments of an nbuf
  1495. */
  1496. qdf_nbuf_inc_users(nbuf);
  1497. /* Check with MCL if this is needed */
  1498. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1499. }
  1500. }
  1501. /*
  1502. * For Multicast-Unicast converted packets,
  1503. * each converted frame (for a client) is represented as
  1504. * 1 segment
  1505. */
  1506. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1507. (msdu_info->frm_type == dp_tx_frm_me)) {
  1508. if (msdu_info->u.sg_info.curr_seg->next) {
  1509. msdu_info->u.sg_info.curr_seg =
  1510. msdu_info->u.sg_info.curr_seg->next;
  1511. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1512. }
  1513. }
  1514. i++;
  1515. }
  1516. nbuf = NULL;
  1517. done:
  1518. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1519. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1520. hif_pm_runtime_put(soc->hif_handle);
  1521. } else {
  1522. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1523. }
  1524. return nbuf;
  1525. }
  1526. /**
  1527. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1528. * for SG frames
  1529. * @vdev: DP vdev handle
  1530. * @nbuf: skb
  1531. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1532. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1533. *
  1534. * Return: NULL on success,
  1535. * nbuf when it fails to send
  1536. */
  1537. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1538. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1539. {
  1540. uint32_t cur_frag, nr_frags;
  1541. qdf_dma_addr_t paddr;
  1542. struct dp_tx_sg_info_s *sg_info;
  1543. sg_info = &msdu_info->u.sg_info;
  1544. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1545. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1546. QDF_DMA_TO_DEVICE)) {
  1547. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1548. "dma map error");
  1549. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1550. qdf_nbuf_free(nbuf);
  1551. return NULL;
  1552. }
  1553. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1554. seg_info->frags[0].paddr_lo = paddr;
  1555. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1556. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1557. seg_info->frags[0].vaddr = (void *) nbuf;
  1558. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1559. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1560. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1561. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1562. "frag dma map error");
  1563. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1564. qdf_nbuf_free(nbuf);
  1565. return NULL;
  1566. }
  1567. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1568. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1569. seg_info->frags[cur_frag + 1].paddr_hi =
  1570. ((uint64_t) paddr) >> 32;
  1571. seg_info->frags[cur_frag + 1].len =
  1572. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1573. }
  1574. seg_info->frag_cnt = (cur_frag + 1);
  1575. seg_info->total_len = qdf_nbuf_len(nbuf);
  1576. seg_info->next = NULL;
  1577. sg_info->curr_seg = seg_info;
  1578. msdu_info->frm_type = dp_tx_frm_sg;
  1579. msdu_info->num_seg = 1;
  1580. return nbuf;
  1581. }
  1582. /**
  1583. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1584. * @vdev: DP vdev handle
  1585. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1586. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1587. *
  1588. * Return: NULL on failure,
  1589. * nbuf when extracted successfully
  1590. */
  1591. static
  1592. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1593. struct dp_tx_msdu_info_s *msdu_info,
  1594. uint16_t ppdu_cookie)
  1595. {
  1596. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1597. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1598. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1599. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1600. (msdu_info->meta_data[5], 1);
  1601. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1602. (msdu_info->meta_data[5], 1);
  1603. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1604. (msdu_info->meta_data[6], ppdu_cookie);
  1605. msdu_info->exception_fw = 1;
  1606. msdu_info->is_tx_sniffer = 1;
  1607. }
  1608. #ifdef MESH_MODE_SUPPORT
  1609. /**
  1610. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1611. and prepare msdu_info for mesh frames.
  1612. * @vdev: DP vdev handle
  1613. * @nbuf: skb
  1614. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1615. *
  1616. * Return: NULL on failure,
  1617. * nbuf when extracted successfully
  1618. */
  1619. static
  1620. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1621. struct dp_tx_msdu_info_s *msdu_info)
  1622. {
  1623. struct meta_hdr_s *mhdr;
  1624. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1625. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1626. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1627. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1628. msdu_info->exception_fw = 0;
  1629. goto remove_meta_hdr;
  1630. }
  1631. msdu_info->exception_fw = 1;
  1632. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1633. meta_data->host_tx_desc_pool = 1;
  1634. meta_data->update_peer_cache = 1;
  1635. meta_data->learning_frame = 1;
  1636. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1637. meta_data->power = mhdr->power;
  1638. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1639. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1640. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1641. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1642. meta_data->dyn_bw = 1;
  1643. meta_data->valid_pwr = 1;
  1644. meta_data->valid_mcs_mask = 1;
  1645. meta_data->valid_nss_mask = 1;
  1646. meta_data->valid_preamble_type = 1;
  1647. meta_data->valid_retries = 1;
  1648. meta_data->valid_bw_info = 1;
  1649. }
  1650. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1651. meta_data->encrypt_type = 0;
  1652. meta_data->valid_encrypt_type = 1;
  1653. meta_data->learning_frame = 0;
  1654. }
  1655. meta_data->valid_key_flags = 1;
  1656. meta_data->key_flags = (mhdr->keyix & 0x3);
  1657. remove_meta_hdr:
  1658. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1659. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1660. "qdf_nbuf_pull_head failed");
  1661. qdf_nbuf_free(nbuf);
  1662. return NULL;
  1663. }
  1664. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1665. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1666. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1667. " tid %d to_fw %d",
  1668. __func__, msdu_info->meta_data[0],
  1669. msdu_info->meta_data[1],
  1670. msdu_info->meta_data[2],
  1671. msdu_info->meta_data[3],
  1672. msdu_info->meta_data[4],
  1673. msdu_info->meta_data[5],
  1674. msdu_info->tid, msdu_info->exception_fw);
  1675. return nbuf;
  1676. }
  1677. #else
  1678. static
  1679. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1680. struct dp_tx_msdu_info_s *msdu_info)
  1681. {
  1682. return nbuf;
  1683. }
  1684. #endif
  1685. /**
  1686. * dp_check_exc_metadata() - Checks if parameters are valid
  1687. * @tx_exc - holds all exception path parameters
  1688. *
  1689. * Returns true when all the parameters are valid else false
  1690. *
  1691. */
  1692. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1693. {
  1694. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1695. HTT_INVALID_TID);
  1696. bool invalid_encap_type =
  1697. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1698. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1699. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1700. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1701. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1702. tx_exc->ppdu_cookie == 0);
  1703. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1704. invalid_cookie) {
  1705. return false;
  1706. }
  1707. return true;
  1708. }
  1709. /**
  1710. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1711. * @vap_dev: DP vdev handle
  1712. * @nbuf: skb
  1713. * @tx_exc_metadata: Handle that holds exception path meta data
  1714. *
  1715. * Entry point for Core Tx layer (DP_TX) invoked from
  1716. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1717. *
  1718. * Return: NULL on success,
  1719. * nbuf when it fails to send
  1720. */
  1721. qdf_nbuf_t
  1722. dp_tx_send_exception(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf,
  1723. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1724. {
  1725. qdf_ether_header_t *eh = NULL;
  1726. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1727. struct dp_tx_msdu_info_s msdu_info;
  1728. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1729. if (!tx_exc_metadata)
  1730. goto fail;
  1731. msdu_info.tid = tx_exc_metadata->tid;
  1732. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1733. dp_verbose_debug("skb %pM", nbuf->data);
  1734. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1735. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1736. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1737. "Invalid parameters in exception path");
  1738. goto fail;
  1739. }
  1740. /* Basic sanity checks for unsupported packets */
  1741. /* MESH mode */
  1742. if (qdf_unlikely(vdev->mesh_vdev)) {
  1743. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1744. "Mesh mode is not supported in exception path");
  1745. goto fail;
  1746. }
  1747. /* TSO or SG */
  1748. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1749. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1750. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1751. "TSO and SG are not supported in exception path");
  1752. goto fail;
  1753. }
  1754. /* RAW */
  1755. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1756. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1757. "Raw frame is not supported in exception path");
  1758. goto fail;
  1759. }
  1760. /* Mcast enhancement*/
  1761. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1762. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1763. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1764. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1765. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1766. }
  1767. }
  1768. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1769. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1770. qdf_nbuf_len(nbuf));
  1771. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1772. tx_exc_metadata->ppdu_cookie);
  1773. }
  1774. /*
  1775. * Get HW Queue to use for this frame.
  1776. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1777. * dedicated for data and 1 for command.
  1778. * "queue_id" maps to one hardware ring.
  1779. * With each ring, we also associate a unique Tx descriptor pool
  1780. * to minimize lock contention for these resources.
  1781. */
  1782. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1783. /* Single linear frame */
  1784. /*
  1785. * If nbuf is a simple linear frame, use send_single function to
  1786. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1787. * SRNG. There is no need to setup a MSDU extension descriptor.
  1788. */
  1789. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1790. tx_exc_metadata->peer_id, tx_exc_metadata);
  1791. return nbuf;
  1792. fail:
  1793. dp_verbose_debug("pkt send failed");
  1794. return nbuf;
  1795. }
  1796. /**
  1797. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1798. * @vap_dev: DP vdev handle
  1799. * @nbuf: skb
  1800. *
  1801. * Entry point for Core Tx layer (DP_TX) invoked from
  1802. * hard_start_xmit in OSIF/HDD
  1803. *
  1804. * Return: NULL on success,
  1805. * nbuf when it fails to send
  1806. */
  1807. #ifdef MESH_MODE_SUPPORT
  1808. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1809. {
  1810. struct meta_hdr_s *mhdr;
  1811. qdf_nbuf_t nbuf_mesh = NULL;
  1812. qdf_nbuf_t nbuf_clone = NULL;
  1813. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1814. uint8_t no_enc_frame = 0;
  1815. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1816. if (!nbuf_mesh) {
  1817. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1818. "qdf_nbuf_unshare failed");
  1819. return nbuf;
  1820. }
  1821. nbuf = nbuf_mesh;
  1822. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1823. if ((vdev->sec_type != cdp_sec_type_none) &&
  1824. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1825. no_enc_frame = 1;
  1826. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1827. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1828. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1829. !no_enc_frame) {
  1830. nbuf_clone = qdf_nbuf_clone(nbuf);
  1831. if (!nbuf_clone) {
  1832. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1833. "qdf_nbuf_clone failed");
  1834. return nbuf;
  1835. }
  1836. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1837. }
  1838. if (nbuf_clone) {
  1839. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1840. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1841. } else {
  1842. qdf_nbuf_free(nbuf_clone);
  1843. }
  1844. }
  1845. if (no_enc_frame)
  1846. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1847. else
  1848. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1849. nbuf = dp_tx_send(vap_dev, nbuf);
  1850. if ((!nbuf) && no_enc_frame) {
  1851. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1852. }
  1853. return nbuf;
  1854. }
  1855. #else
  1856. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1857. {
  1858. return dp_tx_send(vap_dev, nbuf);
  1859. }
  1860. #endif
  1861. /**
  1862. * dp_tx_send() - Transmit a frame on a given VAP
  1863. * @vap_dev: DP vdev handle
  1864. * @nbuf: skb
  1865. *
  1866. * Entry point for Core Tx layer (DP_TX) invoked from
  1867. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1868. * cases
  1869. *
  1870. * Return: NULL on success,
  1871. * nbuf when it fails to send
  1872. */
  1873. qdf_nbuf_t dp_tx_send(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1874. {
  1875. qdf_ether_header_t *eh = NULL;
  1876. struct dp_tx_msdu_info_s msdu_info;
  1877. struct dp_tx_seg_info_s seg_info;
  1878. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1879. uint16_t peer_id = HTT_INVALID_PEER;
  1880. qdf_nbuf_t nbuf_mesh = NULL;
  1881. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1882. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1883. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1884. dp_verbose_debug("skb %pM", nbuf->data);
  1885. /*
  1886. * Set Default Host TID value to invalid TID
  1887. * (TID override disabled)
  1888. */
  1889. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1890. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1891. if (qdf_unlikely(vdev->mesh_vdev)) {
  1892. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1893. &msdu_info);
  1894. if (!nbuf_mesh) {
  1895. dp_verbose_debug("Extracting mesh metadata failed");
  1896. return nbuf;
  1897. }
  1898. nbuf = nbuf_mesh;
  1899. }
  1900. /*
  1901. * Get HW Queue to use for this frame.
  1902. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1903. * dedicated for data and 1 for command.
  1904. * "queue_id" maps to one hardware ring.
  1905. * With each ring, we also associate a unique Tx descriptor pool
  1906. * to minimize lock contention for these resources.
  1907. */
  1908. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1909. /*
  1910. * TCL H/W supports 2 DSCP-TID mapping tables.
  1911. * Table 1 - Default DSCP-TID mapping table
  1912. * Table 2 - 1 DSCP-TID override table
  1913. *
  1914. * If we need a different DSCP-TID mapping for this vap,
  1915. * call tid_classify to extract DSCP/ToS from frame and
  1916. * map to a TID and store in msdu_info. This is later used
  1917. * to fill in TCL Input descriptor (per-packet TID override).
  1918. */
  1919. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1920. /*
  1921. * Classify the frame and call corresponding
  1922. * "prepare" function which extracts the segment (TSO)
  1923. * and fragmentation information (for TSO , SG, ME, or Raw)
  1924. * into MSDU_INFO structure which is later used to fill
  1925. * SW and HW descriptors.
  1926. */
  1927. if (qdf_nbuf_is_tso(nbuf)) {
  1928. dp_verbose_debug("TSO frame %pK", vdev);
  1929. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1930. qdf_nbuf_len(nbuf));
  1931. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1932. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1933. qdf_nbuf_len(nbuf));
  1934. return nbuf;
  1935. }
  1936. goto send_multiple;
  1937. }
  1938. /* SG */
  1939. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1940. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1941. if (!nbuf)
  1942. return NULL;
  1943. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1944. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1945. qdf_nbuf_len(nbuf));
  1946. goto send_multiple;
  1947. }
  1948. #ifdef ATH_SUPPORT_IQUE
  1949. /* Mcast to Ucast Conversion*/
  1950. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1951. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1952. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1953. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1954. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1955. DP_STATS_INC_PKT(vdev,
  1956. tx_i.mcast_en.mcast_pkt, 1,
  1957. qdf_nbuf_len(nbuf));
  1958. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1959. QDF_STATUS_SUCCESS) {
  1960. return NULL;
  1961. }
  1962. }
  1963. }
  1964. #endif
  1965. /* RAW */
  1966. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1967. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1968. if (!nbuf)
  1969. return NULL;
  1970. dp_verbose_debug("Raw frame %pK", vdev);
  1971. goto send_multiple;
  1972. }
  1973. /* Single linear frame */
  1974. /*
  1975. * If nbuf is a simple linear frame, use send_single function to
  1976. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1977. * SRNG. There is no need to setup a MSDU extension descriptor.
  1978. */
  1979. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1980. return nbuf;
  1981. send_multiple:
  1982. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1983. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  1984. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  1985. return nbuf;
  1986. }
  1987. /**
  1988. * dp_tx_reinject_handler() - Tx Reinject Handler
  1989. * @tx_desc: software descriptor head pointer
  1990. * @status : Tx completion status from HTT descriptor
  1991. *
  1992. * This function reinjects frames back to Target.
  1993. * Todo - Host queue needs to be added
  1994. *
  1995. * Return: none
  1996. */
  1997. static
  1998. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1999. {
  2000. struct dp_vdev *vdev;
  2001. struct dp_peer *peer = NULL;
  2002. uint32_t peer_id = HTT_INVALID_PEER;
  2003. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2004. qdf_nbuf_t nbuf_copy = NULL;
  2005. struct dp_tx_msdu_info_s msdu_info;
  2006. struct dp_peer *sa_peer = NULL;
  2007. struct dp_ast_entry *ast_entry = NULL;
  2008. struct dp_soc *soc = NULL;
  2009. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2010. #ifdef WDS_VENDOR_EXTENSION
  2011. int is_mcast = 0, is_ucast = 0;
  2012. int num_peers_3addr = 0;
  2013. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2014. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2015. #endif
  2016. vdev = tx_desc->vdev;
  2017. soc = vdev->pdev->soc;
  2018. qdf_assert(vdev);
  2019. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2020. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2021. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2022. "%s Tx reinject path", __func__);
  2023. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2024. qdf_nbuf_len(tx_desc->nbuf));
  2025. qdf_spin_lock_bh(&(soc->ast_lock));
  2026. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2027. (soc,
  2028. (uint8_t *)(eh->ether_shost),
  2029. vdev->pdev->pdev_id);
  2030. if (ast_entry)
  2031. sa_peer = ast_entry->peer;
  2032. qdf_spin_unlock_bh(&(soc->ast_lock));
  2033. #ifdef WDS_VENDOR_EXTENSION
  2034. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2035. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2036. } else {
  2037. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2038. }
  2039. is_ucast = !is_mcast;
  2040. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2041. if (peer->bss_peer)
  2042. continue;
  2043. /* Detect wds peers that use 3-addr framing for mcast.
  2044. * if there are any, the bss_peer is used to send the
  2045. * the mcast frame using 3-addr format. all wds enabled
  2046. * peers that use 4-addr framing for mcast frames will
  2047. * be duplicated and sent as 4-addr frames below.
  2048. */
  2049. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2050. num_peers_3addr = 1;
  2051. break;
  2052. }
  2053. }
  2054. #endif
  2055. if (qdf_unlikely(vdev->mesh_vdev)) {
  2056. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2057. } else {
  2058. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2059. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2060. #ifdef WDS_VENDOR_EXTENSION
  2061. /*
  2062. * . if 3-addr STA, then send on BSS Peer
  2063. * . if Peer WDS enabled and accept 4-addr mcast,
  2064. * send mcast on that peer only
  2065. * . if Peer WDS enabled and accept 4-addr ucast,
  2066. * send ucast on that peer only
  2067. */
  2068. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2069. (peer->wds_enabled &&
  2070. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2071. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2072. #else
  2073. ((peer->bss_peer &&
  2074. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2075. peer->nawds_enabled)) {
  2076. #endif
  2077. peer_id = DP_INVALID_PEER;
  2078. if (peer->nawds_enabled) {
  2079. peer_id = peer->peer_ids[0];
  2080. if (sa_peer == peer) {
  2081. QDF_TRACE(
  2082. QDF_MODULE_ID_DP,
  2083. QDF_TRACE_LEVEL_DEBUG,
  2084. " %s: multicast packet",
  2085. __func__);
  2086. DP_STATS_INC(peer,
  2087. tx.nawds_mcast_drop, 1);
  2088. continue;
  2089. }
  2090. }
  2091. nbuf_copy = qdf_nbuf_copy(nbuf);
  2092. if (!nbuf_copy) {
  2093. QDF_TRACE(QDF_MODULE_ID_DP,
  2094. QDF_TRACE_LEVEL_DEBUG,
  2095. FL("nbuf copy failed"));
  2096. break;
  2097. }
  2098. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2099. nbuf_copy,
  2100. &msdu_info,
  2101. peer_id,
  2102. NULL);
  2103. if (nbuf_copy) {
  2104. QDF_TRACE(QDF_MODULE_ID_DP,
  2105. QDF_TRACE_LEVEL_DEBUG,
  2106. FL("pkt send failed"));
  2107. qdf_nbuf_free(nbuf_copy);
  2108. } else {
  2109. if (peer_id != DP_INVALID_PEER)
  2110. DP_STATS_INC_PKT(peer,
  2111. tx.nawds_mcast,
  2112. 1, qdf_nbuf_len(nbuf));
  2113. }
  2114. }
  2115. }
  2116. }
  2117. if (vdev->nawds_enabled) {
  2118. peer_id = DP_INVALID_PEER;
  2119. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2120. 1, qdf_nbuf_len(nbuf));
  2121. nbuf = dp_tx_send_msdu_single(vdev,
  2122. nbuf,
  2123. &msdu_info,
  2124. peer_id, NULL);
  2125. if (nbuf) {
  2126. QDF_TRACE(QDF_MODULE_ID_DP,
  2127. QDF_TRACE_LEVEL_DEBUG,
  2128. FL("pkt send failed"));
  2129. qdf_nbuf_free(nbuf);
  2130. }
  2131. } else
  2132. qdf_nbuf_free(nbuf);
  2133. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2134. }
  2135. /**
  2136. * dp_tx_inspect_handler() - Tx Inspect Handler
  2137. * @tx_desc: software descriptor head pointer
  2138. * @status : Tx completion status from HTT descriptor
  2139. *
  2140. * Handles Tx frames sent back to Host for inspection
  2141. * (ProxyARP)
  2142. *
  2143. * Return: none
  2144. */
  2145. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2146. {
  2147. struct dp_soc *soc;
  2148. struct dp_pdev *pdev = tx_desc->pdev;
  2149. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2150. "%s Tx inspect path",
  2151. __func__);
  2152. qdf_assert(pdev);
  2153. soc = pdev->soc;
  2154. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2155. qdf_nbuf_len(tx_desc->nbuf));
  2156. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2157. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2158. }
  2159. #ifdef FEATURE_PERPKT_INFO
  2160. /**
  2161. * dp_get_completion_indication_for_stack() - send completion to stack
  2162. * @soc : dp_soc handle
  2163. * @pdev: dp_pdev handle
  2164. * @peer: dp peer handle
  2165. * @ts: transmit completion status structure
  2166. * @netbuf: Buffer pointer for free
  2167. *
  2168. * This function is used for indication whether buffer needs to be
  2169. * sent to stack for freeing or not
  2170. */
  2171. QDF_STATUS
  2172. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2173. struct dp_pdev *pdev,
  2174. struct dp_peer *peer,
  2175. struct hal_tx_completion_status *ts,
  2176. qdf_nbuf_t netbuf,
  2177. uint64_t time_latency)
  2178. {
  2179. struct tx_capture_hdr *ppdu_hdr;
  2180. uint16_t peer_id = ts->peer_id;
  2181. uint32_t ppdu_id = ts->ppdu_id;
  2182. uint8_t first_msdu = ts->first_msdu;
  2183. uint8_t last_msdu = ts->last_msdu;
  2184. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2185. !pdev->latency_capture_enable))
  2186. return QDF_STATUS_E_NOSUPPORT;
  2187. if (!peer) {
  2188. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2189. FL("Peer Invalid"));
  2190. return QDF_STATUS_E_INVAL;
  2191. }
  2192. if (pdev->mcopy_mode) {
  2193. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2194. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2195. return QDF_STATUS_E_INVAL;
  2196. }
  2197. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2198. pdev->m_copy_id.tx_peer_id = peer_id;
  2199. }
  2200. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2201. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2202. FL("No headroom"));
  2203. return QDF_STATUS_E_NOMEM;
  2204. }
  2205. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2206. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2207. QDF_MAC_ADDR_SIZE);
  2208. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2209. QDF_MAC_ADDR_SIZE);
  2210. ppdu_hdr->ppdu_id = ppdu_id;
  2211. ppdu_hdr->peer_id = peer_id;
  2212. ppdu_hdr->first_msdu = first_msdu;
  2213. ppdu_hdr->last_msdu = last_msdu;
  2214. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2215. ppdu_hdr->tsf = ts->tsf;
  2216. ppdu_hdr->time_latency = time_latency;
  2217. }
  2218. return QDF_STATUS_SUCCESS;
  2219. }
  2220. /**
  2221. * dp_send_completion_to_stack() - send completion to stack
  2222. * @soc : dp_soc handle
  2223. * @pdev: dp_pdev handle
  2224. * @peer_id: peer_id of the peer for which completion came
  2225. * @ppdu_id: ppdu_id
  2226. * @netbuf: Buffer pointer for free
  2227. *
  2228. * This function is used to send completion to stack
  2229. * to free buffer
  2230. */
  2231. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2232. uint16_t peer_id, uint32_t ppdu_id,
  2233. qdf_nbuf_t netbuf)
  2234. {
  2235. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2236. netbuf, peer_id,
  2237. WDI_NO_VAL, pdev->pdev_id);
  2238. }
  2239. #else
  2240. static QDF_STATUS
  2241. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2242. struct dp_pdev *pdev,
  2243. struct dp_peer *peer,
  2244. struct hal_tx_completion_status *ts,
  2245. qdf_nbuf_t netbuf,
  2246. uint64_t time_latency)
  2247. {
  2248. return QDF_STATUS_E_NOSUPPORT;
  2249. }
  2250. static void
  2251. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2252. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2253. {
  2254. }
  2255. #endif
  2256. /**
  2257. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2258. * @soc: Soc handle
  2259. * @desc: software Tx descriptor to be processed
  2260. *
  2261. * Return: none
  2262. */
  2263. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2264. struct dp_tx_desc_s *desc)
  2265. {
  2266. struct dp_vdev *vdev = desc->vdev;
  2267. qdf_nbuf_t nbuf = desc->nbuf;
  2268. /* nbuf already freed in vdev detach path */
  2269. if (!nbuf)
  2270. return;
  2271. /* If it is TDLS mgmt, don't unmap or free the frame */
  2272. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2273. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2274. /* 0 : MSDU buffer, 1 : MLE */
  2275. if (desc->msdu_ext_desc) {
  2276. /* TSO free */
  2277. if (hal_tx_ext_desc_get_tso_enable(
  2278. desc->msdu_ext_desc->vaddr)) {
  2279. /* unmap eash TSO seg before free the nbuf */
  2280. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2281. desc->tso_num_desc);
  2282. qdf_nbuf_free(nbuf);
  2283. return;
  2284. }
  2285. }
  2286. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2287. if (qdf_unlikely(!vdev)) {
  2288. qdf_nbuf_free(nbuf);
  2289. return;
  2290. }
  2291. if (qdf_likely(!vdev->mesh_vdev))
  2292. qdf_nbuf_free(nbuf);
  2293. else {
  2294. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2295. qdf_nbuf_free(nbuf);
  2296. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2297. } else
  2298. vdev->osif_tx_free_ext((nbuf));
  2299. }
  2300. }
  2301. #ifdef MESH_MODE_SUPPORT
  2302. /**
  2303. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2304. * in mesh meta header
  2305. * @tx_desc: software descriptor head pointer
  2306. * @ts: pointer to tx completion stats
  2307. * Return: none
  2308. */
  2309. static
  2310. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2311. struct hal_tx_completion_status *ts)
  2312. {
  2313. struct meta_hdr_s *mhdr;
  2314. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2315. if (!tx_desc->msdu_ext_desc) {
  2316. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2317. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2318. "netbuf %pK offset %d",
  2319. netbuf, tx_desc->pkt_offset);
  2320. return;
  2321. }
  2322. }
  2323. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2324. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2325. "netbuf %pK offset %lu", netbuf,
  2326. sizeof(struct meta_hdr_s));
  2327. return;
  2328. }
  2329. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2330. mhdr->rssi = ts->ack_frame_rssi;
  2331. mhdr->channel = tx_desc->pdev->operating_channel;
  2332. }
  2333. #else
  2334. static
  2335. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2336. struct hal_tx_completion_status *ts)
  2337. {
  2338. }
  2339. #endif
  2340. /**
  2341. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2342. * to pass in correct fields
  2343. *
  2344. * @vdev: pdev handle
  2345. * @tx_desc: tx descriptor
  2346. * @tid: tid value
  2347. * @ring_id: TCL or WBM ring number for transmit path
  2348. * Return: none
  2349. */
  2350. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2351. struct dp_tx_desc_s *tx_desc,
  2352. uint8_t tid, uint8_t ring_id)
  2353. {
  2354. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2355. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2356. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2357. return;
  2358. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2359. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2360. timestamp_hw_enqueue = tx_desc->timestamp;
  2361. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2362. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2363. timestamp_hw_enqueue);
  2364. interframe_delay = (uint32_t)(timestamp_ingress -
  2365. vdev->prev_tx_enq_tstamp);
  2366. /*
  2367. * Delay in software enqueue
  2368. */
  2369. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2370. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2371. /*
  2372. * Delay between packet enqueued to HW and Tx completion
  2373. */
  2374. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2375. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2376. /*
  2377. * Update interframe delay stats calculated at hardstart receive point.
  2378. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2379. * interframe delay will not be calculate correctly for 1st frame.
  2380. * On the other side, this will help in avoiding extra per packet check
  2381. * of !vdev->prev_tx_enq_tstamp.
  2382. */
  2383. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2384. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2385. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2386. }
  2387. /**
  2388. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2389. * per wbm ring
  2390. *
  2391. * @tx_desc: software descriptor head pointer
  2392. * @ts: Tx completion status
  2393. * @peer: peer handle
  2394. * @ring_id: ring number
  2395. *
  2396. * Return: None
  2397. */
  2398. static inline void
  2399. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2400. struct hal_tx_completion_status *ts,
  2401. struct dp_peer *peer, uint8_t ring_id)
  2402. {
  2403. struct dp_pdev *pdev = peer->vdev->pdev;
  2404. struct dp_soc *soc = NULL;
  2405. uint8_t mcs, pkt_type;
  2406. uint8_t tid = ts->tid;
  2407. uint32_t length;
  2408. struct cdp_tid_tx_stats *tid_stats;
  2409. if (!pdev)
  2410. return;
  2411. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2412. tid = CDP_MAX_DATA_TIDS - 1;
  2413. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2414. soc = pdev->soc;
  2415. mcs = ts->mcs;
  2416. pkt_type = ts->pkt_type;
  2417. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2418. dp_err("Release source is not from TQM");
  2419. return;
  2420. }
  2421. length = qdf_nbuf_len(tx_desc->nbuf);
  2422. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2423. if (qdf_unlikely(pdev->delay_stats_flag))
  2424. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2425. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2426. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2427. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2428. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2429. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2430. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2431. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2432. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2433. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2434. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2435. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2436. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2437. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2438. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2439. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2440. tid_stats->comp_fail_cnt++;
  2441. return;
  2442. }
  2443. tid_stats->success_cnt++;
  2444. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2445. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2446. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2447. /*
  2448. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2449. * Return from here if HTT PPDU events are enabled.
  2450. */
  2451. if (!(soc->process_tx_status))
  2452. return;
  2453. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2454. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2455. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2456. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2457. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2458. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2459. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2460. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2461. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2462. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2463. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2464. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2465. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2466. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2467. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2468. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2469. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2470. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2471. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2472. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2473. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2474. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2475. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2476. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2477. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2478. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2479. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2480. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2481. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2482. &peer->stats, ts->peer_id,
  2483. UPDATE_PEER_STATS, pdev->pdev_id);
  2484. #endif
  2485. }
  2486. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2487. /**
  2488. * dp_tx_flow_pool_lock() - take flow pool lock
  2489. * @soc: core txrx main context
  2490. * @tx_desc: tx desc
  2491. *
  2492. * Return: None
  2493. */
  2494. static inline
  2495. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2496. struct dp_tx_desc_s *tx_desc)
  2497. {
  2498. struct dp_tx_desc_pool_s *pool;
  2499. uint8_t desc_pool_id;
  2500. desc_pool_id = tx_desc->pool_id;
  2501. pool = &soc->tx_desc[desc_pool_id];
  2502. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2503. }
  2504. /**
  2505. * dp_tx_flow_pool_unlock() - release flow pool lock
  2506. * @soc: core txrx main context
  2507. * @tx_desc: tx desc
  2508. *
  2509. * Return: None
  2510. */
  2511. static inline
  2512. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2513. struct dp_tx_desc_s *tx_desc)
  2514. {
  2515. struct dp_tx_desc_pool_s *pool;
  2516. uint8_t desc_pool_id;
  2517. desc_pool_id = tx_desc->pool_id;
  2518. pool = &soc->tx_desc[desc_pool_id];
  2519. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2520. }
  2521. #else
  2522. static inline
  2523. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2524. {
  2525. }
  2526. static inline
  2527. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2528. {
  2529. }
  2530. #endif
  2531. /**
  2532. * dp_tx_notify_completion() - Notify tx completion for this desc
  2533. * @soc: core txrx main context
  2534. * @tx_desc: tx desc
  2535. * @netbuf: buffer
  2536. *
  2537. * Return: none
  2538. */
  2539. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2540. struct dp_tx_desc_s *tx_desc,
  2541. qdf_nbuf_t netbuf)
  2542. {
  2543. void *osif_dev;
  2544. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2545. qdf_assert(tx_desc);
  2546. dp_tx_flow_pool_lock(soc, tx_desc);
  2547. if (!tx_desc->vdev ||
  2548. !tx_desc->vdev->osif_vdev) {
  2549. dp_tx_flow_pool_unlock(soc, tx_desc);
  2550. return;
  2551. }
  2552. osif_dev = tx_desc->vdev->osif_vdev;
  2553. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2554. dp_tx_flow_pool_unlock(soc, tx_desc);
  2555. if (tx_compl_cbk)
  2556. tx_compl_cbk(netbuf, osif_dev);
  2557. }
  2558. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2559. * @pdev: pdev handle
  2560. * @tid: tid value
  2561. * @txdesc_ts: timestamp from txdesc
  2562. * @ppdu_id: ppdu id
  2563. *
  2564. * Return: none
  2565. */
  2566. #ifdef FEATURE_PERPKT_INFO
  2567. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2568. struct dp_peer *peer,
  2569. uint8_t tid,
  2570. uint64_t txdesc_ts,
  2571. uint32_t ppdu_id)
  2572. {
  2573. uint64_t delta_ms;
  2574. struct cdp_tx_sojourn_stats *sojourn_stats;
  2575. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2576. return;
  2577. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2578. tid >= CDP_DATA_TID_MAX))
  2579. return;
  2580. if (qdf_unlikely(!pdev->sojourn_buf))
  2581. return;
  2582. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2583. qdf_nbuf_data(pdev->sojourn_buf);
  2584. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2585. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2586. txdesc_ts;
  2587. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2588. delta_ms);
  2589. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2590. sojourn_stats->num_msdus[tid] = 1;
  2591. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2592. peer->avg_sojourn_msdu[tid].internal;
  2593. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2594. pdev->sojourn_buf, HTT_INVALID_PEER,
  2595. WDI_NO_VAL, pdev->pdev_id);
  2596. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2597. sojourn_stats->num_msdus[tid] = 0;
  2598. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2599. }
  2600. #else
  2601. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2602. uint8_t tid,
  2603. uint64_t txdesc_ts,
  2604. uint32_t ppdu_id)
  2605. {
  2606. }
  2607. #endif
  2608. /**
  2609. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2610. * @soc: DP Soc handle
  2611. * @tx_desc: software Tx descriptor
  2612. * @ts : Tx completion status from HAL/HTT descriptor
  2613. *
  2614. * Return: none
  2615. */
  2616. static inline void
  2617. dp_tx_comp_process_desc(struct dp_soc *soc,
  2618. struct dp_tx_desc_s *desc,
  2619. struct hal_tx_completion_status *ts,
  2620. struct dp_peer *peer)
  2621. {
  2622. uint64_t time_latency = 0;
  2623. /*
  2624. * m_copy/tx_capture modes are not supported for
  2625. * scatter gather packets
  2626. */
  2627. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2628. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2629. desc->timestamp);
  2630. }
  2631. if (!(desc->msdu_ext_desc)) {
  2632. if (QDF_STATUS_SUCCESS ==
  2633. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2634. return;
  2635. }
  2636. if (QDF_STATUS_SUCCESS ==
  2637. dp_get_completion_indication_for_stack(soc,
  2638. desc->pdev,
  2639. peer, ts,
  2640. desc->nbuf,
  2641. time_latency)) {
  2642. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2643. QDF_DMA_TO_DEVICE);
  2644. dp_send_completion_to_stack(soc,
  2645. desc->pdev,
  2646. ts->peer_id,
  2647. ts->ppdu_id,
  2648. desc->nbuf);
  2649. return;
  2650. }
  2651. }
  2652. dp_tx_comp_free_buf(soc, desc);
  2653. }
  2654. /**
  2655. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2656. * @tx_desc: software descriptor head pointer
  2657. * @ts: Tx completion status
  2658. * @peer: peer handle
  2659. * @ring_id: ring number
  2660. *
  2661. * Return: none
  2662. */
  2663. static inline
  2664. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2665. struct hal_tx_completion_status *ts,
  2666. struct dp_peer *peer, uint8_t ring_id)
  2667. {
  2668. uint32_t length;
  2669. qdf_ether_header_t *eh;
  2670. struct dp_soc *soc = NULL;
  2671. struct dp_vdev *vdev = tx_desc->vdev;
  2672. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2673. if (!vdev || !nbuf) {
  2674. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2675. "invalid tx descriptor. vdev or nbuf NULL");
  2676. goto out;
  2677. }
  2678. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2679. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2680. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2681. QDF_TRACE_DEFAULT_PDEV_ID,
  2682. qdf_nbuf_data_addr(nbuf),
  2683. sizeof(qdf_nbuf_data(nbuf)),
  2684. tx_desc->id,
  2685. ts->status));
  2686. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2687. "-------------------- \n"
  2688. "Tx Completion Stats: \n"
  2689. "-------------------- \n"
  2690. "ack_frame_rssi = %d \n"
  2691. "first_msdu = %d \n"
  2692. "last_msdu = %d \n"
  2693. "msdu_part_of_amsdu = %d \n"
  2694. "rate_stats valid = %d \n"
  2695. "bw = %d \n"
  2696. "pkt_type = %d \n"
  2697. "stbc = %d \n"
  2698. "ldpc = %d \n"
  2699. "sgi = %d \n"
  2700. "mcs = %d \n"
  2701. "ofdma = %d \n"
  2702. "tones_in_ru = %d \n"
  2703. "tsf = %d \n"
  2704. "ppdu_id = %d \n"
  2705. "transmit_cnt = %d \n"
  2706. "tid = %d \n"
  2707. "peer_id = %d\n",
  2708. ts->ack_frame_rssi, ts->first_msdu,
  2709. ts->last_msdu, ts->msdu_part_of_amsdu,
  2710. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2711. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2712. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2713. ts->transmit_cnt, ts->tid, ts->peer_id);
  2714. soc = vdev->pdev->soc;
  2715. /* Update SoC level stats */
  2716. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2717. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2718. /* Update per-packet stats for mesh mode */
  2719. if (qdf_unlikely(vdev->mesh_vdev) &&
  2720. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2721. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2722. length = qdf_nbuf_len(nbuf);
  2723. /* Update peer level stats */
  2724. if (!peer) {
  2725. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2726. "peer is null or deletion in progress");
  2727. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2728. goto out;
  2729. }
  2730. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2731. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2732. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2733. if ((peer->vdev->tx_encap_type ==
  2734. htt_cmn_pkt_type_ethernet) &&
  2735. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2736. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2737. }
  2738. }
  2739. } else {
  2740. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2741. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2742. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2743. }
  2744. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2745. #ifdef QCA_SUPPORT_RDK_STATS
  2746. if (soc->wlanstats_enabled)
  2747. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2748. tx_desc->timestamp,
  2749. ts->ppdu_id);
  2750. #endif
  2751. out:
  2752. return;
  2753. }
  2754. /**
  2755. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2756. * @soc: core txrx main context
  2757. * @comp_head: software descriptor head pointer
  2758. * @ring_id: ring number
  2759. *
  2760. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2761. * and release the software descriptors after processing is complete
  2762. *
  2763. * Return: none
  2764. */
  2765. static void
  2766. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2767. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2768. {
  2769. struct dp_tx_desc_s *desc;
  2770. struct dp_tx_desc_s *next;
  2771. struct hal_tx_completion_status ts = {0};
  2772. struct dp_peer *peer;
  2773. qdf_nbuf_t netbuf;
  2774. desc = comp_head;
  2775. while (desc) {
  2776. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2777. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2778. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2779. netbuf = desc->nbuf;
  2780. /* check tx complete notification */
  2781. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2782. dp_tx_notify_completion(soc, desc, netbuf);
  2783. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2784. if (peer)
  2785. dp_peer_unref_del_find_by_id(peer);
  2786. next = desc->next;
  2787. dp_tx_desc_release(desc, desc->pool_id);
  2788. desc = next;
  2789. }
  2790. }
  2791. /**
  2792. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2793. * @tx_desc: software descriptor head pointer
  2794. * @status : Tx completion status from HTT descriptor
  2795. * @ring_id: ring number
  2796. *
  2797. * This function will process HTT Tx indication messages from Target
  2798. *
  2799. * Return: none
  2800. */
  2801. static
  2802. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2803. uint8_t ring_id)
  2804. {
  2805. uint8_t tx_status;
  2806. struct dp_pdev *pdev;
  2807. struct dp_vdev *vdev;
  2808. struct dp_soc *soc;
  2809. struct hal_tx_completion_status ts = {0};
  2810. uint32_t *htt_desc = (uint32_t *)status;
  2811. struct dp_peer *peer;
  2812. struct cdp_tid_tx_stats *tid_stats = NULL;
  2813. struct htt_soc *htt_handle;
  2814. qdf_assert(tx_desc->pdev);
  2815. pdev = tx_desc->pdev;
  2816. vdev = tx_desc->vdev;
  2817. soc = pdev->soc;
  2818. if (!vdev)
  2819. return;
  2820. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2821. htt_handle = (struct htt_soc *)soc->htt_handle;
  2822. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  2823. switch (tx_status) {
  2824. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2825. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2826. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2827. {
  2828. uint8_t tid;
  2829. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2830. ts.peer_id =
  2831. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2832. htt_desc[2]);
  2833. ts.tid =
  2834. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2835. htt_desc[2]);
  2836. } else {
  2837. ts.peer_id = HTT_INVALID_PEER;
  2838. ts.tid = HTT_INVALID_TID;
  2839. }
  2840. ts.ppdu_id =
  2841. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2842. htt_desc[1]);
  2843. ts.ack_frame_rssi =
  2844. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2845. htt_desc[1]);
  2846. ts.first_msdu = 1;
  2847. ts.last_msdu = 1;
  2848. tid = ts.tid;
  2849. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2850. tid = CDP_MAX_DATA_TIDS - 1;
  2851. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2852. if (qdf_unlikely(pdev->delay_stats_flag))
  2853. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2854. if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
  2855. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2856. tid_stats->comp_fail_cnt++;
  2857. } else {
  2858. tid_stats->success_cnt++;
  2859. }
  2860. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2861. if (qdf_likely(peer))
  2862. dp_peer_unref_del_find_by_id(peer);
  2863. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2864. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2865. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2866. break;
  2867. }
  2868. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2869. {
  2870. dp_tx_reinject_handler(tx_desc, status);
  2871. break;
  2872. }
  2873. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2874. {
  2875. dp_tx_inspect_handler(tx_desc, status);
  2876. break;
  2877. }
  2878. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2879. {
  2880. dp_tx_mec_handler(vdev, status);
  2881. break;
  2882. }
  2883. default:
  2884. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2885. "%s Invalid HTT tx_status %d\n",
  2886. __func__, tx_status);
  2887. break;
  2888. }
  2889. }
  2890. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2891. static inline
  2892. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2893. {
  2894. bool limit_hit = false;
  2895. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2896. limit_hit =
  2897. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2898. if (limit_hit)
  2899. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2900. return limit_hit;
  2901. }
  2902. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2903. {
  2904. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2905. }
  2906. #else
  2907. static inline
  2908. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2909. {
  2910. return false;
  2911. }
  2912. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2913. {
  2914. return false;
  2915. }
  2916. #endif
  2917. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2918. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  2919. uint32_t quota)
  2920. {
  2921. void *tx_comp_hal_desc;
  2922. uint8_t buffer_src;
  2923. uint8_t pool_id;
  2924. uint32_t tx_desc_id;
  2925. struct dp_tx_desc_s *tx_desc = NULL;
  2926. struct dp_tx_desc_s *head_desc = NULL;
  2927. struct dp_tx_desc_s *tail_desc = NULL;
  2928. uint32_t num_processed = 0;
  2929. uint32_t count = 0;
  2930. bool force_break = false;
  2931. DP_HIST_INIT();
  2932. more_data:
  2933. /* Re-initialize local variables to be re-used */
  2934. head_desc = NULL;
  2935. tail_desc = NULL;
  2936. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  2937. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2938. "%s %d : HAL RING Access Failed -- %pK",
  2939. __func__, __LINE__, hal_ring_hdl);
  2940. return 0;
  2941. }
  2942. /* Find head descriptor from completion ring */
  2943. while (qdf_likely(tx_comp_hal_desc =
  2944. hal_srng_dst_get_next(soc->hal_soc, hal_ring_hdl))) {
  2945. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2946. /* If this buffer was not released by TQM or FW, then it is not
  2947. * Tx completion indication, assert */
  2948. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2949. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2950. QDF_TRACE(QDF_MODULE_ID_DP,
  2951. QDF_TRACE_LEVEL_FATAL,
  2952. "Tx comp release_src != TQM | FW but from %d",
  2953. buffer_src);
  2954. hal_dump_comp_desc(tx_comp_hal_desc);
  2955. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  2956. qdf_assert_always(0);
  2957. }
  2958. /* Get descriptor id */
  2959. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2960. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2961. DP_TX_DESC_ID_POOL_OS;
  2962. /* Find Tx descriptor */
  2963. tx_desc = dp_tx_desc_find(soc, pool_id,
  2964. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2965. DP_TX_DESC_ID_PAGE_OS,
  2966. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2967. DP_TX_DESC_ID_OFFSET_OS);
  2968. /*
  2969. * If the descriptor is already freed in vdev_detach,
  2970. * continue to next descriptor
  2971. */
  2972. if (!tx_desc->vdev && !tx_desc->flags) {
  2973. QDF_TRACE(QDF_MODULE_ID_DP,
  2974. QDF_TRACE_LEVEL_INFO,
  2975. "Descriptor freed in vdev_detach %d",
  2976. tx_desc_id);
  2977. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2978. count++;
  2979. continue;
  2980. }
  2981. /*
  2982. * If the release source is FW, process the HTT status
  2983. */
  2984. if (qdf_unlikely(buffer_src ==
  2985. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2986. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2987. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2988. htt_tx_status);
  2989. dp_tx_process_htt_completion(tx_desc,
  2990. htt_tx_status, ring_id);
  2991. } else {
  2992. /* Pool id is not matching. Error */
  2993. if (tx_desc->pool_id != pool_id) {
  2994. QDF_TRACE(QDF_MODULE_ID_DP,
  2995. QDF_TRACE_LEVEL_FATAL,
  2996. "Tx Comp pool id %d not matched %d",
  2997. pool_id, tx_desc->pool_id);
  2998. qdf_assert_always(0);
  2999. }
  3000. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3001. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3002. QDF_TRACE(QDF_MODULE_ID_DP,
  3003. QDF_TRACE_LEVEL_FATAL,
  3004. "Txdesc invalid, flgs = %x,id = %d",
  3005. tx_desc->flags, tx_desc_id);
  3006. qdf_assert_always(0);
  3007. }
  3008. /* First ring descriptor on the cycle */
  3009. if (!head_desc) {
  3010. head_desc = tx_desc;
  3011. tail_desc = tx_desc;
  3012. }
  3013. tail_desc->next = tx_desc;
  3014. tx_desc->next = NULL;
  3015. tail_desc = tx_desc;
  3016. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3017. /* Collect hw completion contents */
  3018. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3019. &tx_desc->comp, 1);
  3020. }
  3021. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3022. /*
  3023. * Processed packet count is more than given quota
  3024. * stop to processing
  3025. */
  3026. if (num_processed >= quota) {
  3027. force_break = true;
  3028. break;
  3029. }
  3030. count++;
  3031. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3032. break;
  3033. }
  3034. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3035. /* Process the reaped descriptors */
  3036. if (head_desc)
  3037. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3038. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3039. if (!force_break &&
  3040. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3041. hal_ring_hdl)) {
  3042. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3043. if (!hif_exec_should_yield(soc->hif_handle,
  3044. int_ctx->dp_intr_id))
  3045. goto more_data;
  3046. }
  3047. }
  3048. DP_TX_HIST_STATS_PER_PDEV();
  3049. return num_processed;
  3050. }
  3051. #ifdef FEATURE_WLAN_TDLS
  3052. /**
  3053. * dp_tx_non_std() - Allow the control-path SW to send data frames
  3054. *
  3055. * @data_vdev - which vdev should transmit the tx data frames
  3056. * @tx_spec - what non-standard handling to apply to the tx data frames
  3057. * @msdu_list - NULL-terminated list of tx MSDUs
  3058. *
  3059. * Return: NULL on success,
  3060. * nbuf when it fails to send
  3061. */
  3062. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  3063. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3064. {
  3065. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3066. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3067. vdev->is_tdls_frame = true;
  3068. return dp_tx_send(vdev_handle, msdu_list);
  3069. }
  3070. #endif
  3071. /**
  3072. * dp_tx_vdev_attach() - attach vdev to dp tx
  3073. * @vdev: virtual device instance
  3074. *
  3075. * Return: QDF_STATUS_SUCCESS: success
  3076. * QDF_STATUS_E_RESOURCES: Error return
  3077. */
  3078. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3079. {
  3080. /*
  3081. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3082. */
  3083. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3084. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3085. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3086. vdev->vdev_id);
  3087. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3088. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3089. /*
  3090. * Set HTT Extension Valid bit to 0 by default
  3091. */
  3092. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3093. dp_tx_vdev_update_search_flags(vdev);
  3094. return QDF_STATUS_SUCCESS;
  3095. }
  3096. #ifndef FEATURE_WDS
  3097. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3098. {
  3099. return false;
  3100. }
  3101. #endif
  3102. /**
  3103. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3104. * @vdev: virtual device instance
  3105. *
  3106. * Return: void
  3107. *
  3108. */
  3109. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3110. {
  3111. struct dp_soc *soc = vdev->pdev->soc;
  3112. /*
  3113. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3114. * for TDLS link
  3115. *
  3116. * Enable AddrY (SA based search) only for non-WDS STA and
  3117. * ProxySTA VAP (in HKv1) modes.
  3118. *
  3119. * In all other VAP modes, only DA based search should be
  3120. * enabled
  3121. */
  3122. if (vdev->opmode == wlan_op_mode_sta &&
  3123. vdev->tdls_link_connected)
  3124. vdev->hal_desc_addr_search_flags =
  3125. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3126. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3127. !dp_tx_da_search_override(vdev))
  3128. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3129. else
  3130. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3131. /* Set search type only when peer map v2 messaging is enabled
  3132. * as we will have the search index (AST hash) only when v2 is
  3133. * enabled
  3134. */
  3135. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3136. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3137. else
  3138. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3139. }
  3140. static inline bool
  3141. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3142. struct dp_vdev *vdev,
  3143. struct dp_tx_desc_s *tx_desc)
  3144. {
  3145. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3146. return false;
  3147. /*
  3148. * if vdev is given, then only check whether desc
  3149. * vdev match. if vdev is NULL, then check whether
  3150. * desc pdev match.
  3151. */
  3152. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3153. }
  3154. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3155. /**
  3156. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3157. *
  3158. * @soc: Handle to DP SoC structure
  3159. * @tx_desc: pointer of one TX desc
  3160. * @desc_pool_id: TX Desc pool id
  3161. */
  3162. static inline void
  3163. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3164. uint8_t desc_pool_id)
  3165. {
  3166. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3167. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3168. tx_desc->vdev = NULL;
  3169. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3170. }
  3171. /**
  3172. * dp_tx_desc_flush() - release resources associated
  3173. * to TX Desc
  3174. *
  3175. * @dp_pdev: Handle to DP pdev structure
  3176. * @vdev: virtual device instance
  3177. * NULL: no specific Vdev is required and check all allcated TX desc
  3178. * on this pdev.
  3179. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3180. *
  3181. * @force_free:
  3182. * true: flush the TX desc.
  3183. * false: only reset the Vdev in each allocated TX desc
  3184. * that associated to current Vdev.
  3185. *
  3186. * This function will go through the TX desc pool to flush
  3187. * the outstanding TX data or reset Vdev to NULL in associated TX
  3188. * Desc.
  3189. */
  3190. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3191. struct dp_vdev *vdev,
  3192. bool force_free)
  3193. {
  3194. uint8_t i;
  3195. uint32_t j;
  3196. uint32_t num_desc, page_id, offset;
  3197. uint16_t num_desc_per_page;
  3198. struct dp_soc *soc = pdev->soc;
  3199. struct dp_tx_desc_s *tx_desc = NULL;
  3200. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3201. if (!vdev && !force_free) {
  3202. dp_err("Reset TX desc vdev, Vdev param is required!");
  3203. return;
  3204. }
  3205. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3206. tx_desc_pool = &soc->tx_desc[i];
  3207. if (!(tx_desc_pool->pool_size) ||
  3208. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3209. !(tx_desc_pool->desc_pages.cacheable_pages))
  3210. continue;
  3211. num_desc = tx_desc_pool->pool_size;
  3212. num_desc_per_page =
  3213. tx_desc_pool->desc_pages.num_element_per_page;
  3214. for (j = 0; j < num_desc; j++) {
  3215. page_id = j / num_desc_per_page;
  3216. offset = j % num_desc_per_page;
  3217. if (qdf_unlikely(!(tx_desc_pool->
  3218. desc_pages.cacheable_pages)))
  3219. break;
  3220. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3221. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3222. /*
  3223. * Free TX desc if force free is
  3224. * required, otherwise only reset vdev
  3225. * in this TX desc.
  3226. */
  3227. if (force_free) {
  3228. dp_tx_comp_free_buf(soc, tx_desc);
  3229. dp_tx_desc_release(tx_desc, i);
  3230. } else {
  3231. dp_tx_desc_reset_vdev(soc, tx_desc,
  3232. i);
  3233. }
  3234. }
  3235. }
  3236. }
  3237. }
  3238. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3239. static inline void
  3240. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3241. uint8_t desc_pool_id)
  3242. {
  3243. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3244. tx_desc->vdev = NULL;
  3245. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3246. }
  3247. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3248. struct dp_vdev *vdev,
  3249. bool force_free)
  3250. {
  3251. uint8_t i, num_pool;
  3252. uint32_t j;
  3253. uint32_t num_desc, page_id, offset;
  3254. uint16_t num_desc_per_page;
  3255. struct dp_soc *soc = pdev->soc;
  3256. struct dp_tx_desc_s *tx_desc = NULL;
  3257. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3258. if (!vdev && !force_free) {
  3259. dp_err("Reset TX desc vdev, Vdev param is required!");
  3260. return;
  3261. }
  3262. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3263. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3264. for (i = 0; i < num_pool; i++) {
  3265. tx_desc_pool = &soc->tx_desc[i];
  3266. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3267. continue;
  3268. num_desc_per_page =
  3269. tx_desc_pool->desc_pages.num_element_per_page;
  3270. for (j = 0; j < num_desc; j++) {
  3271. page_id = j / num_desc_per_page;
  3272. offset = j % num_desc_per_page;
  3273. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3274. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3275. if (force_free) {
  3276. dp_tx_comp_free_buf(soc, tx_desc);
  3277. dp_tx_desc_release(tx_desc, i);
  3278. } else {
  3279. dp_tx_desc_reset_vdev(soc, tx_desc,
  3280. i);
  3281. }
  3282. }
  3283. }
  3284. }
  3285. }
  3286. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3287. /**
  3288. * dp_tx_vdev_detach() - detach vdev from dp tx
  3289. * @vdev: virtual device instance
  3290. *
  3291. * Return: QDF_STATUS_SUCCESS: success
  3292. * QDF_STATUS_E_RESOURCES: Error return
  3293. */
  3294. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3295. {
  3296. struct dp_pdev *pdev = vdev->pdev;
  3297. /* Reset TX desc associated to this Vdev as NULL */
  3298. dp_tx_desc_flush(pdev, vdev, false);
  3299. dp_tx_vdev_multipass_deinit(vdev);
  3300. return QDF_STATUS_SUCCESS;
  3301. }
  3302. /**
  3303. * dp_tx_pdev_attach() - attach pdev to dp tx
  3304. * @pdev: physical device instance
  3305. *
  3306. * Return: QDF_STATUS_SUCCESS: success
  3307. * QDF_STATUS_E_RESOURCES: Error return
  3308. */
  3309. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3310. {
  3311. struct dp_soc *soc = pdev->soc;
  3312. /* Initialize Flow control counters */
  3313. qdf_atomic_init(&pdev->num_tx_exception);
  3314. qdf_atomic_init(&pdev->num_tx_outstanding);
  3315. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3316. /* Initialize descriptors in TCL Ring */
  3317. hal_tx_init_data_ring(soc->hal_soc,
  3318. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3319. }
  3320. return QDF_STATUS_SUCCESS;
  3321. }
  3322. /**
  3323. * dp_tx_pdev_detach() - detach pdev from dp tx
  3324. * @pdev: physical device instance
  3325. *
  3326. * Return: QDF_STATUS_SUCCESS: success
  3327. * QDF_STATUS_E_RESOURCES: Error return
  3328. */
  3329. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3330. {
  3331. /* flush TX outstanding data per pdev */
  3332. dp_tx_desc_flush(pdev, NULL, true);
  3333. dp_tx_me_exit(pdev);
  3334. return QDF_STATUS_SUCCESS;
  3335. }
  3336. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3337. /* Pools will be allocated dynamically */
  3338. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3339. int num_desc)
  3340. {
  3341. uint8_t i;
  3342. for (i = 0; i < num_pool; i++) {
  3343. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3344. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3345. }
  3346. return 0;
  3347. }
  3348. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3349. {
  3350. uint8_t i;
  3351. for (i = 0; i < num_pool; i++)
  3352. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3353. }
  3354. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3355. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3356. int num_desc)
  3357. {
  3358. uint8_t i;
  3359. /* Allocate software Tx descriptor pools */
  3360. for (i = 0; i < num_pool; i++) {
  3361. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3362. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3363. "%s Tx Desc Pool alloc %d failed %pK",
  3364. __func__, i, soc);
  3365. return ENOMEM;
  3366. }
  3367. }
  3368. return 0;
  3369. }
  3370. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3371. {
  3372. uint8_t i;
  3373. for (i = 0; i < num_pool; i++) {
  3374. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3375. if (dp_tx_desc_pool_free(soc, i)) {
  3376. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3377. "%s Tx Desc Pool Free failed", __func__);
  3378. }
  3379. }
  3380. }
  3381. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3382. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3383. /**
  3384. * dp_tso_attach_wifi3() - TSO attach handler
  3385. * @txrx_soc: Opaque Dp handle
  3386. *
  3387. * Reserve TSO descriptor buffers
  3388. *
  3389. * Return: QDF_STATUS_E_FAILURE on failure or
  3390. * QDF_STATUS_SUCCESS on success
  3391. */
  3392. static
  3393. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3394. {
  3395. return dp_tso_soc_attach(txrx_soc);
  3396. }
  3397. /**
  3398. * dp_tso_detach_wifi3() - TSO Detach handler
  3399. * @txrx_soc: Opaque Dp handle
  3400. *
  3401. * Deallocate TSO descriptor buffers
  3402. *
  3403. * Return: QDF_STATUS_E_FAILURE on failure or
  3404. * QDF_STATUS_SUCCESS on success
  3405. */
  3406. static
  3407. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3408. {
  3409. return dp_tso_soc_detach(txrx_soc);
  3410. }
  3411. #else
  3412. static
  3413. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3414. {
  3415. return QDF_STATUS_SUCCESS;
  3416. }
  3417. static
  3418. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3419. {
  3420. return QDF_STATUS_SUCCESS;
  3421. }
  3422. #endif
  3423. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3424. {
  3425. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3426. uint8_t i;
  3427. uint8_t num_pool;
  3428. uint32_t num_desc;
  3429. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3430. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3431. for (i = 0; i < num_pool; i++)
  3432. dp_tx_tso_desc_pool_free(soc, i);
  3433. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3434. __func__, num_pool, num_desc);
  3435. for (i = 0; i < num_pool; i++)
  3436. dp_tx_tso_num_seg_pool_free(soc, i);
  3437. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3438. __func__, num_pool, num_desc);
  3439. return QDF_STATUS_SUCCESS;
  3440. }
  3441. /**
  3442. * dp_tso_attach() - TSO attach handler
  3443. * @txrx_soc: Opaque Dp handle
  3444. *
  3445. * Reserve TSO descriptor buffers
  3446. *
  3447. * Return: QDF_STATUS_E_FAILURE on failure or
  3448. * QDF_STATUS_SUCCESS on success
  3449. */
  3450. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3451. {
  3452. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3453. uint8_t i;
  3454. uint8_t num_pool;
  3455. uint32_t num_desc;
  3456. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3457. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3458. for (i = 0; i < num_pool; i++) {
  3459. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3460. dp_err("TSO Desc Pool alloc %d failed %pK",
  3461. i, soc);
  3462. return QDF_STATUS_E_FAILURE;
  3463. }
  3464. }
  3465. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3466. __func__, num_pool, num_desc);
  3467. for (i = 0; i < num_pool; i++) {
  3468. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3469. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3470. i, soc);
  3471. return QDF_STATUS_E_FAILURE;
  3472. }
  3473. }
  3474. return QDF_STATUS_SUCCESS;
  3475. }
  3476. /**
  3477. * dp_tx_soc_detach() - detach soc from dp tx
  3478. * @soc: core txrx main context
  3479. *
  3480. * This function will detach dp tx into main device context
  3481. * will free dp tx resource and initialize resources
  3482. *
  3483. * Return: QDF_STATUS_SUCCESS: success
  3484. * QDF_STATUS_E_RESOURCES: Error return
  3485. */
  3486. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3487. {
  3488. uint8_t num_pool;
  3489. uint16_t num_desc;
  3490. uint16_t num_ext_desc;
  3491. uint8_t i;
  3492. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3493. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3494. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3495. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3496. dp_tx_flow_control_deinit(soc);
  3497. dp_tx_delete_static_pools(soc, num_pool);
  3498. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3499. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3500. __func__, num_pool, num_desc);
  3501. for (i = 0; i < num_pool; i++) {
  3502. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3503. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3504. "%s Tx Ext Desc Pool Free failed",
  3505. __func__);
  3506. return QDF_STATUS_E_RESOURCES;
  3507. }
  3508. }
  3509. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3510. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3511. __func__, num_pool, num_ext_desc);
  3512. status = dp_tso_detach_wifi3(soc);
  3513. if (status != QDF_STATUS_SUCCESS)
  3514. return status;
  3515. return QDF_STATUS_SUCCESS;
  3516. }
  3517. /**
  3518. * dp_tx_soc_attach() - attach soc to dp tx
  3519. * @soc: core txrx main context
  3520. *
  3521. * This function will attach dp tx into main device context
  3522. * will allocate dp tx resource and initialize resources
  3523. *
  3524. * Return: QDF_STATUS_SUCCESS: success
  3525. * QDF_STATUS_E_RESOURCES: Error return
  3526. */
  3527. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3528. {
  3529. uint8_t i;
  3530. uint8_t num_pool;
  3531. uint32_t num_desc;
  3532. uint32_t num_ext_desc;
  3533. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3534. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3535. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3536. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3537. if (num_pool > MAX_TXDESC_POOLS)
  3538. goto fail;
  3539. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3540. goto fail;
  3541. dp_tx_flow_control_init(soc);
  3542. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3543. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3544. __func__, num_pool, num_desc);
  3545. /* Allocate extension tx descriptor pools */
  3546. for (i = 0; i < num_pool; i++) {
  3547. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3548. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3549. "MSDU Ext Desc Pool alloc %d failed %pK",
  3550. i, soc);
  3551. goto fail;
  3552. }
  3553. }
  3554. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3555. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3556. __func__, num_pool, num_ext_desc);
  3557. status = dp_tso_attach_wifi3((void *)soc);
  3558. if (status != QDF_STATUS_SUCCESS)
  3559. goto fail;
  3560. /* Initialize descriptors in TCL Rings */
  3561. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3562. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3563. hal_tx_init_data_ring(soc->hal_soc,
  3564. soc->tcl_data_ring[i].hal_srng);
  3565. }
  3566. }
  3567. /*
  3568. * todo - Add a runtime config option to enable this.
  3569. */
  3570. /*
  3571. * Due to multiple issues on NPR EMU, enable it selectively
  3572. * only for NPR EMU, should be removed, once NPR platforms
  3573. * are stable.
  3574. */
  3575. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3576. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3577. "%s HAL Tx init Success", __func__);
  3578. return QDF_STATUS_SUCCESS;
  3579. fail:
  3580. /* Detach will take care of freeing only allocated resources */
  3581. dp_tx_soc_detach(soc);
  3582. return QDF_STATUS_E_RESOURCES;
  3583. }