cpastop100.h 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #ifndef _CPASTOP100_H_
  7. #define _CPASTOP100_H_
  8. #define TEST_IRQ_ENABLE 0
  9. static struct cam_camnoc_irq_sbm cam_cpas100_irq_sbm = {
  10. .sbm_enable = {
  11. .access_type = CAM_REG_TYPE_READ_WRITE,
  12. .enable = true,
  13. .offset = 0x2040, /* SBM_FAULTINEN0_LOW */
  14. .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
  15. 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
  16. 0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
  17. 0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
  18. 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
  19. 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
  20. (TEST_IRQ_ENABLE ?
  21. 0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */
  22. 0x0),
  23. },
  24. .sbm_status = {
  25. .access_type = CAM_REG_TYPE_READ,
  26. .enable = true,
  27. .offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */
  28. },
  29. .sbm_clear = {
  30. .access_type = CAM_REG_TYPE_WRITE,
  31. .enable = true,
  32. .offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */
  33. .value = TEST_IRQ_ENABLE ? 0x6 : 0x2,
  34. }
  35. };
  36. static struct cam_camnoc_irq_err
  37. cam_cpas100_irq_err[] = {
  38. {
  39. .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
  40. .enable = true,
  41. .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
  42. .err_enable = {
  43. .access_type = CAM_REG_TYPE_READ_WRITE,
  44. .enable = true,
  45. .offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
  46. .value = 1,
  47. },
  48. .err_status = {
  49. .access_type = CAM_REG_TYPE_READ,
  50. .enable = true,
  51. .offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
  52. },
  53. .err_clear = {
  54. .access_type = CAM_REG_TYPE_WRITE,
  55. .enable = true,
  56. .offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */
  57. .value = 1,
  58. },
  59. },
  60. {
  61. .irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR,
  62. .enable = true,
  63. .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
  64. .err_enable = {
  65. .access_type = CAM_REG_TYPE_READ_WRITE,
  66. .enable = true,
  67. .offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */
  68. .value = 1,
  69. },
  70. .err_status = {
  71. .access_type = CAM_REG_TYPE_READ,
  72. .enable = true,
  73. .offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */
  74. },
  75. .err_clear = {
  76. .access_type = CAM_REG_TYPE_WRITE,
  77. .enable = true,
  78. .offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */
  79. .value = 1,
  80. },
  81. },
  82. {
  83. .irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR,
  84. .enable = true,
  85. .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
  86. .err_enable = {
  87. .access_type = CAM_REG_TYPE_READ_WRITE,
  88. .enable = true,
  89. .offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */
  90. .value = 1,
  91. },
  92. .err_status = {
  93. .access_type = CAM_REG_TYPE_READ,
  94. .enable = true,
  95. .offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */
  96. },
  97. .err_clear = {
  98. .access_type = CAM_REG_TYPE_WRITE,
  99. .enable = true,
  100. .offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */
  101. .value = 1,
  102. },
  103. },
  104. {
  105. .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
  106. .enable = true,
  107. .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
  108. .err_enable = {
  109. .access_type = CAM_REG_TYPE_READ_WRITE,
  110. .enable = true,
  111. .offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */
  112. .value = 1,
  113. },
  114. .err_status = {
  115. .access_type = CAM_REG_TYPE_READ,
  116. .enable = true,
  117. .offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */
  118. },
  119. .err_clear = {
  120. .access_type = CAM_REG_TYPE_WRITE,
  121. .enable = true,
  122. .offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */
  123. .value = 1,
  124. },
  125. },
  126. {
  127. .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
  128. .enable = true,
  129. .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
  130. .err_enable = {
  131. .access_type = CAM_REG_TYPE_READ_WRITE,
  132. .enable = true,
  133. .offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */
  134. .value = 1,
  135. },
  136. .err_status = {
  137. .access_type = CAM_REG_TYPE_READ,
  138. .enable = true,
  139. .offset = 0x1190,
  140. /* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */
  141. },
  142. .err_clear = {
  143. .access_type = CAM_REG_TYPE_WRITE,
  144. .enable = true,
  145. .offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */
  146. .value = 1,
  147. },
  148. },
  149. {
  150. .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
  151. .enable = true,
  152. .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
  153. .err_enable = {
  154. .access_type = CAM_REG_TYPE_READ_WRITE,
  155. .enable = true,
  156. .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
  157. .value = 0x1,
  158. },
  159. .err_status = {
  160. .access_type = CAM_REG_TYPE_READ,
  161. .enable = true,
  162. .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
  163. },
  164. .err_clear = {
  165. .enable = false,
  166. },
  167. },
  168. {
  169. .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
  170. .enable = false,
  171. },
  172. {
  173. .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
  174. .enable = false,
  175. },
  176. {
  177. .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
  178. .enable = TEST_IRQ_ENABLE ? true : false,
  179. .sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */
  180. .err_enable = {
  181. .access_type = CAM_REG_TYPE_READ_WRITE,
  182. .enable = true,
  183. .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
  184. .value = 0x5,
  185. },
  186. .err_status = {
  187. .access_type = CAM_REG_TYPE_READ,
  188. .enable = true,
  189. .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
  190. },
  191. .err_clear = {
  192. .enable = false,
  193. },
  194. },
  195. };
  196. static struct cam_camnoc_specific
  197. cam_cpas100_camnoc_specific[] = {
  198. {
  199. .port_type = CAM_CAMNOC_CDM,
  200. .enable = true,
  201. .priority_lut_low = {
  202. .enable = true,
  203. .access_type = CAM_REG_TYPE_READ_WRITE,
  204. .masked_value = 0,
  205. .offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */
  206. .value = 0x22222222,
  207. },
  208. .priority_lut_high = {
  209. .enable = true,
  210. .access_type = CAM_REG_TYPE_READ_WRITE,
  211. .masked_value = 0,
  212. .offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */
  213. .value = 0x22222222,
  214. },
  215. .urgency = {
  216. .enable = true,
  217. .access_type = CAM_REG_TYPE_READ_WRITE,
  218. .masked_value = 1,
  219. .offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */
  220. .mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */
  221. .shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */
  222. .value = 0,
  223. },
  224. .danger_lut = {
  225. .enable = false,
  226. .access_type = CAM_REG_TYPE_READ_WRITE,
  227. .masked_value = 0,
  228. .offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */
  229. .value = 0x0,
  230. },
  231. .safe_lut = {
  232. .enable = false,
  233. .access_type = CAM_REG_TYPE_READ_WRITE,
  234. .masked_value = 0,
  235. .offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */
  236. .value = 0x0,
  237. },
  238. .ubwc_ctl = {
  239. .enable = false,
  240. },
  241. },
  242. {
  243. .port_type = CAM_CAMNOC_IFE02,
  244. .enable = true,
  245. .priority_lut_low = {
  246. .enable = true,
  247. .access_type = CAM_REG_TYPE_READ_WRITE,
  248. .masked_value = 0,
  249. .offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */
  250. .value = 0x66665433,
  251. },
  252. .priority_lut_high = {
  253. .enable = true,
  254. .access_type = CAM_REG_TYPE_READ_WRITE,
  255. .masked_value = 0,
  256. .offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */
  257. .value = 0x66666666,
  258. },
  259. .urgency = {
  260. .enable = true,
  261. .access_type = CAM_REG_TYPE_READ_WRITE,
  262. .masked_value = 1,
  263. .offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */
  264. /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */
  265. .mask = 0x70,
  266. /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */
  267. .shift = 0x4,
  268. .value = 3,
  269. },
  270. .danger_lut = {
  271. .enable = true,
  272. .access_type = CAM_REG_TYPE_READ_WRITE,
  273. .offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */
  274. .value = 0xFFFFFF00,
  275. },
  276. .safe_lut = {
  277. .enable = true,
  278. .access_type = CAM_REG_TYPE_READ_WRITE,
  279. .offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */
  280. .value = 0x3,
  281. },
  282. .ubwc_ctl = {
  283. .enable = true,
  284. .access_type = CAM_REG_TYPE_READ_WRITE,
  285. .masked_value = 0,
  286. .offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */
  287. .value = 1,
  288. },
  289. },
  290. {
  291. .port_type = CAM_CAMNOC_IFE13,
  292. .enable = true,
  293. .priority_lut_low = {
  294. .enable = true,
  295. .access_type = CAM_REG_TYPE_READ_WRITE,
  296. .masked_value = 0,
  297. .offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */
  298. .value = 0x66665433,
  299. },
  300. .priority_lut_high = {
  301. .enable = true,
  302. .access_type = CAM_REG_TYPE_READ_WRITE,
  303. .masked_value = 0,
  304. .offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */
  305. .value = 0x66666666,
  306. },
  307. .urgency = {
  308. .enable = true,
  309. .access_type = CAM_REG_TYPE_READ_WRITE,
  310. .masked_value = 1,
  311. .offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */
  312. /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */
  313. .mask = 0x70,
  314. /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */
  315. .shift = 0x4,
  316. .value = 3,
  317. },
  318. .danger_lut = {
  319. .enable = true,
  320. .access_type = CAM_REG_TYPE_READ_WRITE,
  321. .offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */
  322. .value = 0xFFFFFF00,
  323. },
  324. .safe_lut = {
  325. .enable = true,
  326. .access_type = CAM_REG_TYPE_READ_WRITE,
  327. .offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */
  328. .value = 0x3,
  329. },
  330. .ubwc_ctl = {
  331. .enable = true,
  332. .access_type = CAM_REG_TYPE_READ_WRITE,
  333. .masked_value = 0,
  334. .offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */
  335. .value = 1,
  336. },
  337. },
  338. {
  339. .port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
  340. .enable = true,
  341. .priority_lut_low = {
  342. .enable = true,
  343. .access_type = CAM_REG_TYPE_READ_WRITE,
  344. .masked_value = 0,
  345. .offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */
  346. .value = 0x33333333,
  347. },
  348. .priority_lut_high = {
  349. .enable = true,
  350. .access_type = CAM_REG_TYPE_READ_WRITE,
  351. .masked_value = 0,
  352. .offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */
  353. .value = 0x33333333,
  354. },
  355. .urgency = {
  356. .enable = true,
  357. .access_type = CAM_REG_TYPE_READ_WRITE,
  358. .masked_value = 1,
  359. .offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */
  360. /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */
  361. .mask = 0x7,
  362. /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */
  363. .shift = 0x0,
  364. .value = 3,
  365. },
  366. .danger_lut = {
  367. .enable = false,
  368. .access_type = CAM_REG_TYPE_READ_WRITE,
  369. .masked_value = 0,
  370. .offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */
  371. .value = 0x0,
  372. },
  373. .safe_lut = {
  374. .enable = false,
  375. .access_type = CAM_REG_TYPE_READ_WRITE,
  376. .masked_value = 0,
  377. .offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */
  378. .value = 0x0,
  379. },
  380. .ubwc_ctl = {
  381. .enable = true,
  382. .access_type = CAM_REG_TYPE_READ_WRITE,
  383. .masked_value = 0,
  384. .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */
  385. .value = 1,
  386. },
  387. },
  388. {
  389. .port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
  390. .enable = true,
  391. .priority_lut_low = {
  392. .enable = true,
  393. .access_type = CAM_REG_TYPE_READ_WRITE,
  394. .masked_value = 0,
  395. .offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */
  396. .value = 0x33333333,
  397. },
  398. .priority_lut_high = {
  399. .enable = true,
  400. .access_type = CAM_REG_TYPE_READ_WRITE,
  401. .masked_value = 0,
  402. .offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */
  403. .value = 0x33333333,
  404. },
  405. .urgency = {
  406. .enable = true,
  407. .access_type = CAM_REG_TYPE_READ_WRITE,
  408. .masked_value = 1,
  409. .offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */
  410. /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */
  411. .mask = 0x70,
  412. /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */
  413. .shift = 0x4,
  414. .value = 3,
  415. },
  416. .danger_lut = {
  417. .enable = false,
  418. .access_type = CAM_REG_TYPE_READ_WRITE,
  419. .masked_value = 0,
  420. .offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */
  421. .value = 0x0,
  422. },
  423. .safe_lut = {
  424. .enable = false,
  425. .access_type = CAM_REG_TYPE_READ_WRITE,
  426. .masked_value = 0,
  427. .offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */
  428. .value = 0x0,
  429. },
  430. .ubwc_ctl = {
  431. .enable = true,
  432. .access_type = CAM_REG_TYPE_READ_WRITE,
  433. .masked_value = 0,
  434. .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
  435. .value = 1,
  436. },
  437. },
  438. {
  439. .port_type = CAM_CAMNOC_JPEG,
  440. .enable = true,
  441. .priority_lut_low = {
  442. .enable = true,
  443. .access_type = CAM_REG_TYPE_READ_WRITE,
  444. .masked_value = 0,
  445. .offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */
  446. .value = 0x22222222,
  447. },
  448. .priority_lut_high = {
  449. .enable = true,
  450. .access_type = CAM_REG_TYPE_READ_WRITE,
  451. .masked_value = 0,
  452. .offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */
  453. .value = 0x22222222,
  454. },
  455. .urgency = {
  456. .enable = true,
  457. .access_type = CAM_REG_TYPE_READ_WRITE,
  458. .masked_value = 0,
  459. .offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */
  460. .value = 0x22,
  461. },
  462. .danger_lut = {
  463. .enable = false,
  464. .access_type = CAM_REG_TYPE_READ_WRITE,
  465. .masked_value = 0,
  466. .offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */
  467. .value = 0x0,
  468. },
  469. .safe_lut = {
  470. .enable = false,
  471. .access_type = CAM_REG_TYPE_READ_WRITE,
  472. .masked_value = 0,
  473. .offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */
  474. .value = 0x0,
  475. },
  476. .ubwc_ctl = {
  477. .enable = false,
  478. },
  479. },
  480. {
  481. .port_type = CAM_CAMNOC_FD,
  482. .enable = false,
  483. },
  484. {
  485. .port_type = CAM_CAMNOC_ICP,
  486. .enable = false,
  487. }
  488. };
  489. static struct cam_camnoc_err_logger_info cam170_cpas100_err_logger_offsets = {
  490. .mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
  491. .errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
  492. .errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */
  493. .errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */
  494. .errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */
  495. .errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */
  496. .errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */
  497. .errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */
  498. .errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */
  499. .errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */
  500. };
  501. static struct cam_cpas_hw_errata_wa_list cam170_cpas100_errata_wa_list = {
  502. .camnoc_flush_slave_pending_trans = {
  503. .enable = true,
  504. .data.reg_info = {
  505. .access_type = CAM_REG_TYPE_READ,
  506. .offset = 0x2100, /* SidebandManager_SenseIn0_Low */
  507. .mask = 0xE0000, /* Bits 17, 18, 19 */
  508. .value = 0, /* expected to be 0 */
  509. },
  510. },
  511. };
  512. struct cam_camnoc_info cam170_cpas100_camnoc_info = {
  513. .specific = &cam_cpas100_camnoc_specific[0],
  514. .specific_size = sizeof(cam_cpas100_camnoc_specific) /
  515. sizeof(cam_cpas100_camnoc_specific[0]),
  516. .irq_sbm = &cam_cpas100_irq_sbm,
  517. .irq_err = &cam_cpas100_irq_err[0],
  518. .irq_err_size = sizeof(cam_cpas100_irq_err) /
  519. sizeof(cam_cpas100_irq_err[0]),
  520. .err_logger = &cam170_cpas100_err_logger_offsets,
  521. .errata_wa_list = &cam170_cpas100_errata_wa_list,
  522. };
  523. static struct cam_cpas_info cam170_cpas100_cpas_info = {
  524. .hw_caps_info = {
  525. .num_caps_registers = 1,
  526. .hw_caps_offsets = {0x8},
  527. },
  528. };
  529. #endif /* _CPASTOP100_H_ */