dp_ipa.c 118 KB

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  1. /*
  2. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifdef IPA_OFFLOAD
  18. #include <wlan_ipa_ucfg_api.h>
  19. #include <wlan_ipa_core.h>
  20. #include <qdf_ipa_wdi3.h>
  21. #include <qdf_types.h>
  22. #include <qdf_lock.h>
  23. #include <hal_hw_headers.h>
  24. #include <hal_api.h>
  25. #include <hal_reo.h>
  26. #include <hif.h>
  27. #include <htt.h>
  28. #include <wdi_event.h>
  29. #include <queue.h>
  30. #include "dp_types.h"
  31. #include "dp_htt.h"
  32. #include "dp_tx.h"
  33. #include "dp_rx.h"
  34. #include "dp_ipa.h"
  35. #include "dp_internal.h"
  36. #ifdef WIFI_MONITOR_SUPPORT
  37. #include "dp_mon.h"
  38. #endif
  39. #ifdef FEATURE_WDS
  40. #include "dp_txrx_wds.h"
  41. #endif
  42. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  43. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  44. /* WAR for IPA_OFFLOAD case. In some cases, its observed that WBM tries to
  45. * release a buffer into WBM2SW RELEASE ring for IPA, and the ring is full.
  46. * This causes back pressure, resulting in a FW crash.
  47. * By leaving some entries with no buffer attached, WBM will be able to write
  48. * to the ring, and from dumps we can figure out the buffer which is causing
  49. * this issue.
  50. */
  51. #define DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES 16
  52. /**
  53. * struct dp_ipa_reo_remap_record - history for dp ipa reo remaps
  54. * @timestamp: Timestamp when remap occurs
  55. * @ix0_reg: reo destination ring IX0 value
  56. * @ix2_reg: reo destination ring IX2 value
  57. * @ix3_reg: reo destination ring IX3 value
  58. */
  59. struct dp_ipa_reo_remap_record {
  60. uint64_t timestamp;
  61. uint32_t ix0_reg;
  62. uint32_t ix2_reg;
  63. uint32_t ix3_reg;
  64. };
  65. #ifdef IPA_WDS_EASYMESH_FEATURE
  66. #define WLAN_IPA_META_DATA_MASK htonl(0x000000FF)
  67. #else
  68. #define WLAN_IPA_META_DATA_MASK htonl(0x00FF0000)
  69. #endif
  70. #define REO_REMAP_HISTORY_SIZE 32
  71. struct dp_ipa_reo_remap_record dp_ipa_reo_remap_history[REO_REMAP_HISTORY_SIZE];
  72. static qdf_atomic_t dp_ipa_reo_remap_history_index;
  73. static int dp_ipa_reo_remap_record_index_next(qdf_atomic_t *index)
  74. {
  75. int next = qdf_atomic_inc_return(index);
  76. if (next == REO_REMAP_HISTORY_SIZE)
  77. qdf_atomic_sub(REO_REMAP_HISTORY_SIZE, index);
  78. return next % REO_REMAP_HISTORY_SIZE;
  79. }
  80. /**
  81. * dp_ipa_reo_remap_history_add() - Record dp ipa reo remap values
  82. * @ix0_val: reo destination ring IX0 value
  83. * @ix2_val: reo destination ring IX2 value
  84. * @ix3_val: reo destination ring IX3 value
  85. *
  86. * Return: None
  87. */
  88. static void dp_ipa_reo_remap_history_add(uint32_t ix0_val, uint32_t ix2_val,
  89. uint32_t ix3_val)
  90. {
  91. int idx = dp_ipa_reo_remap_record_index_next(
  92. &dp_ipa_reo_remap_history_index);
  93. struct dp_ipa_reo_remap_record *record = &dp_ipa_reo_remap_history[idx];
  94. record->timestamp = qdf_get_log_timestamp();
  95. record->ix0_reg = ix0_val;
  96. record->ix2_reg = ix2_val;
  97. record->ix3_reg = ix3_val;
  98. }
  99. static QDF_STATUS __dp_ipa_handle_buf_smmu_mapping(struct dp_soc *soc,
  100. qdf_nbuf_t nbuf,
  101. uint32_t size,
  102. bool create,
  103. const char *func,
  104. uint32_t line)
  105. {
  106. qdf_mem_info_t mem_map_table = {0};
  107. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  108. qdf_ipa_wdi_hdl_t hdl;
  109. /* Need to handle the case when one soc will
  110. * have multiple pdev(radio's), Currently passing
  111. * pdev_id as 0 assuming 1 soc has only 1 radio.
  112. */
  113. hdl = wlan_ipa_get_hdl(soc->ctrl_psoc, 0);
  114. if (hdl == DP_IPA_HDL_INVALID) {
  115. dp_err("IPA handle is invalid");
  116. return QDF_STATUS_E_INVAL;
  117. }
  118. qdf_update_mem_map_table(soc->osdev, &mem_map_table,
  119. qdf_nbuf_get_frag_paddr(nbuf, 0),
  120. size);
  121. if (create) {
  122. /* Assert if PA is zero */
  123. qdf_assert_always(mem_map_table.pa);
  124. ret = qdf_nbuf_smmu_map_debug(nbuf, hdl, 1, &mem_map_table,
  125. func, line);
  126. } else {
  127. ret = qdf_nbuf_smmu_unmap_debug(nbuf, hdl, 1, &mem_map_table,
  128. func, line);
  129. }
  130. qdf_assert_always(!ret);
  131. /* Return status of mapping/unmapping is stored in
  132. * mem_map_table.result field, assert if the result
  133. * is failure
  134. */
  135. if (create)
  136. qdf_assert_always(!mem_map_table.result);
  137. else
  138. qdf_assert_always(mem_map_table.result >= mem_map_table.size);
  139. return ret;
  140. }
  141. QDF_STATUS dp_ipa_handle_rx_buf_smmu_mapping(struct dp_soc *soc,
  142. qdf_nbuf_t nbuf,
  143. uint32_t size,
  144. bool create, const char *func,
  145. uint32_t line)
  146. {
  147. struct dp_pdev *pdev;
  148. int i;
  149. for (i = 0; i < soc->pdev_count; i++) {
  150. pdev = soc->pdev_list[i];
  151. if (pdev && dp_monitor_is_configured(pdev))
  152. return QDF_STATUS_SUCCESS;
  153. }
  154. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx) ||
  155. !qdf_mem_smmu_s1_enabled(soc->osdev))
  156. return QDF_STATUS_SUCCESS;
  157. /*
  158. * Even if ipa pipes is disabled, but if it's unmap
  159. * operation and nbuf has done ipa smmu map before,
  160. * do ipa smmu unmap as well.
  161. */
  162. if (!qdf_atomic_read(&soc->ipa_pipes_enabled)) {
  163. if (!create && qdf_nbuf_is_rx_ipa_smmu_map(nbuf)) {
  164. DP_STATS_INC(soc, rx.err.ipa_unmap_no_pipe, 1);
  165. } else {
  166. return QDF_STATUS_SUCCESS;
  167. }
  168. }
  169. if (qdf_unlikely(create == qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  170. if (create) {
  171. DP_STATS_INC(soc, rx.err.ipa_smmu_map_dup, 1);
  172. } else {
  173. DP_STATS_INC(soc, rx.err.ipa_smmu_unmap_dup, 1);
  174. }
  175. return QDF_STATUS_E_INVAL;
  176. }
  177. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  178. return __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, size, create,
  179. func, line);
  180. }
  181. static QDF_STATUS __dp_ipa_tx_buf_smmu_mapping(
  182. struct dp_soc *soc,
  183. struct dp_pdev *pdev,
  184. bool create,
  185. const char *func,
  186. uint32_t line)
  187. {
  188. uint32_t index;
  189. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  190. uint32_t tx_buffer_cnt = soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  191. qdf_nbuf_t nbuf;
  192. uint32_t buf_len;
  193. if (!ipa_is_ready()) {
  194. dp_info("IPA is not READY");
  195. return 0;
  196. }
  197. for (index = 0; index < tx_buffer_cnt; index++) {
  198. nbuf = (qdf_nbuf_t)
  199. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[index];
  200. if (!nbuf)
  201. continue;
  202. buf_len = qdf_nbuf_get_data_len(nbuf);
  203. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  204. create, func, line);
  205. }
  206. return ret;
  207. }
  208. #ifndef QCA_OL_DP_SRNG_LOCK_LESS_ACCESS
  209. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  210. bool lock_required)
  211. {
  212. hal_ring_handle_t hal_ring_hdl;
  213. int ring;
  214. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  215. hal_ring_hdl = soc->reo_dest_ring[ring].hal_srng;
  216. hal_srng_lock(hal_ring_hdl);
  217. soc->ipa_reo_ctx_lock_required[ring] = lock_required;
  218. hal_srng_unlock(hal_ring_hdl);
  219. }
  220. }
  221. #else
  222. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  223. bool lock_required)
  224. {
  225. }
  226. #endif
  227. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  228. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  229. struct dp_pdev *pdev,
  230. bool create,
  231. const char *func,
  232. uint32_t line)
  233. {
  234. struct rx_desc_pool *rx_pool;
  235. uint8_t pdev_id;
  236. uint32_t num_desc, page_id, offset, i;
  237. uint16_t num_desc_per_page;
  238. union dp_rx_desc_list_elem_t *rx_desc_elem;
  239. struct dp_rx_desc *rx_desc;
  240. qdf_nbuf_t nbuf;
  241. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  242. if (!qdf_ipa_is_ready())
  243. return ret;
  244. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  245. return ret;
  246. pdev_id = pdev->pdev_id;
  247. rx_pool = &soc->rx_desc_buf[pdev_id];
  248. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  249. qdf_spin_lock_bh(&rx_pool->lock);
  250. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  251. num_desc = rx_pool->pool_size;
  252. num_desc_per_page = rx_pool->desc_pages.num_element_per_page;
  253. for (i = 0; i < num_desc; i++) {
  254. page_id = i / num_desc_per_page;
  255. offset = i % num_desc_per_page;
  256. if (qdf_unlikely(!(rx_pool->desc_pages.cacheable_pages)))
  257. break;
  258. rx_desc_elem = dp_rx_desc_find(page_id, offset, rx_pool);
  259. rx_desc = &rx_desc_elem->rx_desc;
  260. if ((!(rx_desc->in_use)) || rx_desc->unmapped)
  261. continue;
  262. nbuf = rx_desc->nbuf;
  263. if (qdf_unlikely(create ==
  264. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  265. if (create) {
  266. DP_STATS_INC(soc,
  267. rx.err.ipa_smmu_map_dup, 1);
  268. } else {
  269. DP_STATS_INC(soc,
  270. rx.err.ipa_smmu_unmap_dup, 1);
  271. }
  272. continue;
  273. }
  274. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  275. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  276. rx_pool->buf_size,
  277. create, func, line);
  278. }
  279. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  280. qdf_spin_unlock_bh(&rx_pool->lock);
  281. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  282. return ret;
  283. }
  284. #else
  285. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(
  286. struct dp_soc *soc,
  287. struct dp_pdev *pdev,
  288. bool create,
  289. const char *func,
  290. uint32_t line)
  291. {
  292. struct rx_desc_pool *rx_pool;
  293. uint8_t pdev_id;
  294. qdf_nbuf_t nbuf;
  295. int i;
  296. if (!qdf_ipa_is_ready())
  297. return QDF_STATUS_SUCCESS;
  298. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  299. return QDF_STATUS_SUCCESS;
  300. pdev_id = pdev->pdev_id;
  301. rx_pool = &soc->rx_desc_buf[pdev_id];
  302. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  303. qdf_spin_lock_bh(&rx_pool->lock);
  304. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  305. for (i = 0; i < rx_pool->pool_size; i++) {
  306. if ((!(rx_pool->array[i].rx_desc.in_use)) ||
  307. rx_pool->array[i].rx_desc.unmapped)
  308. continue;
  309. nbuf = rx_pool->array[i].rx_desc.nbuf;
  310. if (qdf_unlikely(create ==
  311. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  312. if (create) {
  313. DP_STATS_INC(soc,
  314. rx.err.ipa_smmu_map_dup, 1);
  315. } else {
  316. DP_STATS_INC(soc,
  317. rx.err.ipa_smmu_unmap_dup, 1);
  318. }
  319. continue;
  320. }
  321. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  322. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, rx_pool->buf_size,
  323. create, func, line);
  324. }
  325. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  326. qdf_spin_unlock_bh(&rx_pool->lock);
  327. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  328. return QDF_STATUS_SUCCESS;
  329. }
  330. #endif /* RX_DESC_MULTI_PAGE_ALLOC */
  331. static QDF_STATUS dp_ipa_get_shared_mem_info(qdf_device_t osdev,
  332. qdf_shared_mem_t *shared_mem,
  333. void *cpu_addr,
  334. qdf_dma_addr_t dma_addr,
  335. uint32_t size)
  336. {
  337. qdf_dma_addr_t paddr;
  338. int ret;
  339. shared_mem->vaddr = cpu_addr;
  340. qdf_mem_set_dma_size(osdev, &shared_mem->mem_info, size);
  341. *qdf_mem_get_dma_addr_ptr(osdev, &shared_mem->mem_info) = dma_addr;
  342. paddr = qdf_mem_paddr_from_dmaaddr(osdev, dma_addr);
  343. qdf_mem_set_dma_pa(osdev, &shared_mem->mem_info, paddr);
  344. ret = qdf_mem_dma_get_sgtable(osdev->dev, &shared_mem->sgtable,
  345. shared_mem->vaddr, dma_addr, size);
  346. if (ret) {
  347. dp_err("Unable to get DMA sgtable");
  348. return QDF_STATUS_E_NOMEM;
  349. }
  350. qdf_dma_get_sgtable_dma_addr(&shared_mem->sgtable);
  351. return QDF_STATUS_SUCCESS;
  352. }
  353. /**
  354. * dp_ipa_get_tx_bank_id() - API to get TCL bank id
  355. * @soc: dp_soc handle
  356. * @bank_id: out parameter for bank id
  357. *
  358. * Return: QDF_STATUS
  359. */
  360. static QDF_STATUS dp_ipa_get_tx_bank_id(struct dp_soc *soc, uint8_t *bank_id)
  361. {
  362. if (soc->arch_ops.ipa_get_bank_id) {
  363. *bank_id = soc->arch_ops.ipa_get_bank_id(soc);
  364. if (*bank_id < 0) {
  365. return QDF_STATUS_E_INVAL;
  366. } else {
  367. dp_info("bank_id %u", *bank_id);
  368. return QDF_STATUS_SUCCESS;
  369. }
  370. } else {
  371. return QDF_STATUS_E_NOSUPPORT;
  372. }
  373. }
  374. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  375. defined(CONFIG_IPA_WDI_UNIFIED_API)
  376. static void dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  377. qdf_ipa_wdi_pipe_setup_info_t *tx)
  378. {
  379. uint8_t bank_id;
  380. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  381. QDF_IPA_WDI_SETUP_INFO_RX_BANK_ID(tx, bank_id);
  382. }
  383. static void
  384. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  385. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  386. {
  387. uint8_t bank_id;
  388. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  389. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_BANK_ID(tx_smmu, bank_id);
  390. }
  391. #else
  392. static inline void
  393. dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  394. qdf_ipa_wdi_pipe_setup_info_t *tx)
  395. {
  396. }
  397. static inline void
  398. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  399. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  400. {
  401. }
  402. #endif
  403. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  404. static void
  405. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  406. qdf_ipa_wdi_pipe_setup_info_t *tx)
  407. {
  408. uint8_t pmac_id = 0;
  409. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  410. if (soc->pdev_count > 1)
  411. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  412. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  413. }
  414. static void
  415. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  416. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  417. {
  418. uint8_t pmac_id = 0;
  419. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  420. if (soc->pdev_count > 1)
  421. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  422. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  423. }
  424. static void
  425. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  426. qdf_ipa_wdi_pipe_setup_info_t *tx)
  427. {
  428. uint8_t pmac_id;
  429. pmac_id = soc->pdev_list[0]->lmac_id;
  430. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  431. }
  432. static void
  433. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  434. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  435. {
  436. uint8_t pmac_id;
  437. pmac_id = soc->pdev_list[0]->lmac_id;
  438. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  439. }
  440. #else
  441. static inline void
  442. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  443. qdf_ipa_wdi_pipe_setup_info_t *tx)
  444. {
  445. }
  446. static inline void
  447. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  448. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  449. {
  450. }
  451. static inline void
  452. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  453. qdf_ipa_wdi_pipe_setup_info_t *tx)
  454. {
  455. }
  456. static inline void
  457. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  458. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  459. {
  460. }
  461. #endif
  462. #ifdef IPA_WDI3_TX_TWO_PIPES
  463. static void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  464. {
  465. struct dp_ipa_resources *ipa_res;
  466. qdf_nbuf_t nbuf;
  467. int idx;
  468. for (idx = 0; idx < soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt; idx++) {
  469. nbuf = (qdf_nbuf_t)
  470. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx];
  471. if (!nbuf)
  472. continue;
  473. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  474. qdf_mem_dp_tx_skb_cnt_dec();
  475. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  476. qdf_nbuf_free(nbuf);
  477. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx] =
  478. (void *)NULL;
  479. }
  480. qdf_mem_free(soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  481. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  482. ipa_res = &pdev->ipa_resource;
  483. if (!ipa_res->is_db_ddr_mapped && ipa_res->tx_alt_comp_doorbell_vaddr)
  484. iounmap(ipa_res->tx_alt_comp_doorbell_vaddr);
  485. qdf_mem_free_sgtable(&ipa_res->tx_alt_ring.sgtable);
  486. qdf_mem_free_sgtable(&ipa_res->tx_alt_comp_ring.sgtable);
  487. }
  488. static int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  489. {
  490. uint32_t tx_buffer_count;
  491. uint32_t ring_base_align = 8;
  492. qdf_dma_addr_t buffer_paddr;
  493. struct hal_srng *wbm_srng = (struct hal_srng *)
  494. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  495. struct hal_srng_params srng_params;
  496. uint32_t wbm_bm_id;
  497. void *ring_entry;
  498. int num_entries;
  499. qdf_nbuf_t nbuf;
  500. int retval = QDF_STATUS_SUCCESS;
  501. int max_alloc_count = 0;
  502. /*
  503. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  504. * unsigned int uc_tx_buf_sz =
  505. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  506. */
  507. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  508. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  509. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  510. IPA_TX_ALT_RING_IDX);
  511. hal_get_srng_params(soc->hal_soc,
  512. hal_srng_to_hal_ring_handle(wbm_srng),
  513. &srng_params);
  514. num_entries = srng_params.num_entries;
  515. max_alloc_count =
  516. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  517. if (max_alloc_count <= 0) {
  518. dp_err("incorrect value for buffer count %u", max_alloc_count);
  519. return -EINVAL;
  520. }
  521. dp_info("requested %d buffers to be posted to wbm ring",
  522. max_alloc_count);
  523. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned =
  524. qdf_mem_malloc(num_entries *
  525. sizeof(*soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned));
  526. if (!soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned) {
  527. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  528. return -ENOMEM;
  529. }
  530. hal_srng_access_start_unlocked(soc->hal_soc,
  531. hal_srng_to_hal_ring_handle(wbm_srng));
  532. /*
  533. * Allocate Tx buffers as many as possible.
  534. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  535. * Populate Tx buffers into WBM2IPA ring
  536. * This initial buffer population will simulate H/W as source ring,
  537. * and update HP
  538. */
  539. for (tx_buffer_count = 0;
  540. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  541. nbuf = qdf_nbuf_alloc(soc->osdev, alloc_size, 0, 256, FALSE);
  542. if (!nbuf)
  543. break;
  544. ring_entry = hal_srng_dst_get_next_hp(
  545. soc->hal_soc,
  546. hal_srng_to_hal_ring_handle(wbm_srng));
  547. if (!ring_entry) {
  548. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  549. "%s: Failed to get WBM ring entry",
  550. __func__);
  551. qdf_nbuf_free(nbuf);
  552. break;
  553. }
  554. qdf_nbuf_map_single(soc->osdev, nbuf,
  555. QDF_DMA_BIDIRECTIONAL);
  556. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  557. qdf_mem_dp_tx_skb_cnt_inc();
  558. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  559. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  560. buffer_paddr, 0, wbm_bm_id);
  561. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[
  562. tx_buffer_count] = (void *)nbuf;
  563. }
  564. hal_srng_access_end_unlocked(soc->hal_soc,
  565. hal_srng_to_hal_ring_handle(wbm_srng));
  566. soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt = tx_buffer_count;
  567. if (tx_buffer_count) {
  568. dp_info("IPA TX buffer pool2: %d allocated", tx_buffer_count);
  569. } else {
  570. dp_err("Failed to allocate IPA TX buffer pool2");
  571. qdf_mem_free(
  572. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  573. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  574. retval = -ENOMEM;
  575. }
  576. return retval;
  577. }
  578. static QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  579. {
  580. struct dp_soc *soc = pdev->soc;
  581. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  582. ipa_res->tx_alt_ring_num_alloc_buffer =
  583. (uint32_t)soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt;
  584. dp_ipa_get_shared_mem_info(
  585. soc->osdev, &ipa_res->tx_alt_ring,
  586. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  587. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  588. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  589. dp_ipa_get_shared_mem_info(
  590. soc->osdev, &ipa_res->tx_alt_comp_ring,
  591. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  592. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  593. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  594. if (!qdf_mem_get_dma_addr(soc->osdev,
  595. &ipa_res->tx_alt_comp_ring.mem_info))
  596. return QDF_STATUS_E_FAILURE;
  597. return QDF_STATUS_SUCCESS;
  598. }
  599. static void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  600. {
  601. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  602. struct hal_srng *hal_srng;
  603. struct hal_srng_params srng_params;
  604. unsigned long addr_offset, dev_base_paddr;
  605. /* IPA TCL_DATA Alternative Ring - HAL_SRNG_SW2TCL2 */
  606. hal_srng = (struct hal_srng *)
  607. soc->tcl_data_ring[IPA_TX_ALT_RING_IDX].hal_srng;
  608. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  609. hal_srng_to_hal_ring_handle(hal_srng),
  610. &srng_params);
  611. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr =
  612. srng_params.ring_base_paddr;
  613. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr =
  614. srng_params.ring_base_vaddr;
  615. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size =
  616. (srng_params.num_entries * srng_params.entry_size) << 2;
  617. /*
  618. * For the register backed memory addresses, use the scn->mem_pa to
  619. * calculate the physical address of the shadow registers
  620. */
  621. dev_base_paddr =
  622. (unsigned long)
  623. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  624. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  625. (unsigned long)(hal_soc->dev_base_addr);
  626. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr =
  627. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  628. dp_info("IPA TCL_DATA Alt Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  629. (unsigned int)addr_offset,
  630. (unsigned int)dev_base_paddr,
  631. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr),
  632. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  633. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  634. srng_params.num_entries,
  635. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  636. /* IPA TX Alternative COMP Ring - HAL_SRNG_WBM2SW4_RELEASE */
  637. hal_srng = (struct hal_srng *)
  638. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  639. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  640. hal_srng_to_hal_ring_handle(hal_srng),
  641. &srng_params);
  642. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr =
  643. srng_params.ring_base_paddr;
  644. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr =
  645. srng_params.ring_base_vaddr;
  646. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size =
  647. (srng_params.num_entries * srng_params.entry_size) << 2;
  648. soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr =
  649. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  650. hal_srng_to_hal_ring_handle(hal_srng));
  651. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  652. (unsigned long)(hal_soc->dev_base_addr);
  653. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr =
  654. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  655. dp_info("IPA TX Alt COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  656. (unsigned int)addr_offset,
  657. (unsigned int)dev_base_paddr,
  658. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr),
  659. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  660. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  661. srng_params.num_entries,
  662. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  663. }
  664. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  665. {
  666. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  667. uint32_t rx_ready_doorbell_dmaaddr;
  668. uint32_t tx_comp_doorbell_dmaaddr;
  669. struct dp_soc *soc = pdev->soc;
  670. int ret = 0;
  671. if (ipa_res->is_db_ddr_mapped)
  672. ipa_res->tx_comp_doorbell_vaddr =
  673. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  674. else
  675. ipa_res->tx_comp_doorbell_vaddr =
  676. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  677. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  678. ret = pld_smmu_map(soc->osdev->dev,
  679. ipa_res->tx_comp_doorbell_paddr,
  680. &tx_comp_doorbell_dmaaddr,
  681. sizeof(uint32_t));
  682. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  683. qdf_assert_always(!ret);
  684. ret = pld_smmu_map(soc->osdev->dev,
  685. ipa_res->rx_ready_doorbell_paddr,
  686. &rx_ready_doorbell_dmaaddr,
  687. sizeof(uint32_t));
  688. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  689. qdf_assert_always(!ret);
  690. }
  691. /* Setup for alternative TX pipe */
  692. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  693. return;
  694. if (ipa_res->is_db_ddr_mapped)
  695. ipa_res->tx_alt_comp_doorbell_vaddr =
  696. phys_to_virt(ipa_res->tx_alt_comp_doorbell_paddr);
  697. else
  698. ipa_res->tx_alt_comp_doorbell_vaddr =
  699. ioremap(ipa_res->tx_alt_comp_doorbell_paddr, 4);
  700. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  701. ret = pld_smmu_map(soc->osdev->dev,
  702. ipa_res->tx_alt_comp_doorbell_paddr,
  703. &tx_comp_doorbell_dmaaddr,
  704. sizeof(uint32_t));
  705. ipa_res->tx_alt_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  706. qdf_assert_always(!ret);
  707. }
  708. }
  709. static void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  710. {
  711. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  712. struct dp_soc *soc = pdev->soc;
  713. int ret = 0;
  714. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  715. return;
  716. /* Unmap must be in reverse order of map */
  717. if (ipa_res->tx_alt_comp_doorbell_paddr) {
  718. ret = pld_smmu_unmap(soc->osdev->dev,
  719. ipa_res->tx_alt_comp_doorbell_paddr,
  720. sizeof(uint32_t));
  721. qdf_assert_always(!ret);
  722. }
  723. ret = pld_smmu_unmap(soc->osdev->dev,
  724. ipa_res->rx_ready_doorbell_paddr,
  725. sizeof(uint32_t));
  726. qdf_assert_always(!ret);
  727. ret = pld_smmu_unmap(soc->osdev->dev,
  728. ipa_res->tx_comp_doorbell_paddr,
  729. sizeof(uint32_t));
  730. qdf_assert_always(!ret);
  731. }
  732. static QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  733. struct dp_pdev *pdev,
  734. bool create, const char *func,
  735. uint32_t line)
  736. {
  737. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  738. struct ipa_dp_tx_rsc *rsc;
  739. uint32_t tx_buffer_cnt;
  740. uint32_t buf_len;
  741. qdf_nbuf_t nbuf;
  742. uint32_t index;
  743. if (!ipa_is_ready()) {
  744. dp_info("IPA is not READY");
  745. return QDF_STATUS_SUCCESS;
  746. }
  747. rsc = &soc->ipa_uc_tx_rsc_alt;
  748. tx_buffer_cnt = rsc->alloc_tx_buf_cnt;
  749. for (index = 0; index < tx_buffer_cnt; index++) {
  750. nbuf = (qdf_nbuf_t)rsc->tx_buf_pool_vaddr_unaligned[index];
  751. if (!nbuf)
  752. continue;
  753. buf_len = qdf_nbuf_get_data_len(nbuf);
  754. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  755. create, func, line);
  756. }
  757. return ret;
  758. }
  759. static void dp_ipa_wdi_tx_alt_pipe_params(struct dp_soc *soc,
  760. struct dp_ipa_resources *ipa_res,
  761. qdf_ipa_wdi_pipe_setup_info_t *tx)
  762. {
  763. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS1;
  764. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  765. qdf_mem_get_dma_addr(soc->osdev,
  766. &ipa_res->tx_alt_comp_ring.mem_info);
  767. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  768. qdf_mem_get_dma_size(soc->osdev,
  769. &ipa_res->tx_alt_comp_ring.mem_info);
  770. /* WBM Tail Pointer Address */
  771. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  772. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  773. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  774. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  775. qdf_mem_get_dma_addr(soc->osdev,
  776. &ipa_res->tx_alt_ring.mem_info);
  777. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  778. qdf_mem_get_dma_size(soc->osdev,
  779. &ipa_res->tx_alt_ring.mem_info);
  780. /* TCL Head Pointer Address */
  781. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  782. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  783. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  784. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  785. ipa_res->tx_alt_ring_num_alloc_buffer;
  786. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  787. dp_ipa_setup_tx_params_bank_id(soc, tx);
  788. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  789. dp_ipa_setup_tx_alt_params_pmac_id(soc, tx);
  790. }
  791. static void
  792. dp_ipa_wdi_tx_alt_pipe_smmu_params(struct dp_soc *soc,
  793. struct dp_ipa_resources *ipa_res,
  794. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  795. {
  796. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) = IPA_CLIENT_WLAN2_CONS1;
  797. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  798. &ipa_res->tx_alt_comp_ring.sgtable,
  799. sizeof(sgtable_t));
  800. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  801. qdf_mem_get_dma_size(soc->osdev,
  802. &ipa_res->tx_alt_comp_ring.mem_info);
  803. /* WBM Tail Pointer Address */
  804. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  805. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  806. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  807. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  808. &ipa_res->tx_alt_ring.sgtable,
  809. sizeof(sgtable_t));
  810. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  811. qdf_mem_get_dma_size(soc->osdev,
  812. &ipa_res->tx_alt_ring.mem_info);
  813. /* TCL Head Pointer Address */
  814. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  815. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  816. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  817. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  818. ipa_res->tx_alt_ring_num_alloc_buffer;
  819. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  820. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  821. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  822. dp_ipa_setup_tx_alt_smmu_params_pmac_id(soc, tx_smmu);
  823. }
  824. static void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc,
  825. struct dp_ipa_resources *res,
  826. qdf_ipa_wdi_conn_in_params_t *in)
  827. {
  828. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu = NULL;
  829. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  830. qdf_ipa_ep_cfg_t *tx_cfg;
  831. QDF_IPA_WDI_CONN_IN_PARAMS_IS_TX1_USED(in) = true;
  832. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  833. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE_SMMU(in);
  834. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  835. dp_ipa_wdi_tx_alt_pipe_smmu_params(soc, res, tx_smmu);
  836. } else {
  837. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE(in);
  838. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx);
  839. dp_ipa_wdi_tx_alt_pipe_params(soc, res, tx);
  840. }
  841. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  842. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  843. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  844. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  845. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  846. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  847. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  848. }
  849. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  850. qdf_ipa_wdi_conn_out_params_t *out)
  851. {
  852. res->tx_comp_doorbell_paddr =
  853. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  854. res->rx_ready_doorbell_paddr =
  855. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  856. res->tx_alt_comp_doorbell_paddr =
  857. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_ALT_DB_PA(out);
  858. }
  859. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  860. uint8_t session_id)
  861. {
  862. bool is_2g_iface = session_id & IPA_SESSION_ID_SHIFT;
  863. session_id = session_id >> IPA_SESSION_ID_SHIFT;
  864. dp_debug("session_id %u is_2g_iface %d", session_id, is_2g_iface);
  865. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  866. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_TX1_USED(in) = is_2g_iface;
  867. }
  868. static void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  869. struct dp_ipa_resources *res)
  870. {
  871. struct hal_srng *wbm_srng;
  872. /* Init first TX comp ring */
  873. wbm_srng = (struct hal_srng *)
  874. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  875. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  876. res->tx_comp_doorbell_vaddr);
  877. /* Init the alternate TX comp ring */
  878. if (!res->tx_alt_comp_doorbell_paddr)
  879. return;
  880. wbm_srng = (struct hal_srng *)
  881. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  882. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  883. res->tx_alt_comp_doorbell_vaddr);
  884. }
  885. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  886. struct dp_ipa_resources *ipa_res)
  887. {
  888. struct hal_srng *wbm_srng;
  889. wbm_srng = (struct hal_srng *)
  890. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  891. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  892. ipa_res->tx_comp_doorbell_paddr);
  893. dp_info("paddr %pK vaddr %pK",
  894. (void *)ipa_res->tx_comp_doorbell_paddr,
  895. (void *)ipa_res->tx_comp_doorbell_vaddr);
  896. /* Setup for alternative TX comp ring */
  897. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  898. return;
  899. wbm_srng = (struct hal_srng *)
  900. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  901. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  902. ipa_res->tx_alt_comp_doorbell_paddr);
  903. dp_info("paddr %pK vaddr %pK",
  904. (void *)ipa_res->tx_alt_comp_doorbell_paddr,
  905. (void *)ipa_res->tx_alt_comp_doorbell_vaddr);
  906. }
  907. #ifdef IPA_SET_RESET_TX_DB_PA
  908. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  909. struct dp_ipa_resources *ipa_res)
  910. {
  911. hal_ring_handle_t wbm_srng;
  912. qdf_dma_addr_t hp_addr;
  913. wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  914. if (!wbm_srng)
  915. return QDF_STATUS_E_FAILURE;
  916. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  917. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  918. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  919. /* Reset alternative TX comp ring */
  920. wbm_srng = soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  921. if (!wbm_srng)
  922. return QDF_STATUS_E_FAILURE;
  923. hp_addr = soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr;
  924. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  925. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  926. return QDF_STATUS_SUCCESS;
  927. }
  928. #endif /* IPA_SET_RESET_TX_DB_PA */
  929. #else /* !IPA_WDI3_TX_TWO_PIPES */
  930. static inline
  931. void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  932. {
  933. }
  934. static inline void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  935. {
  936. }
  937. static inline int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  938. {
  939. return 0;
  940. }
  941. static inline QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  942. {
  943. return QDF_STATUS_SUCCESS;
  944. }
  945. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  946. {
  947. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  948. uint32_t rx_ready_doorbell_dmaaddr;
  949. uint32_t tx_comp_doorbell_dmaaddr;
  950. struct dp_soc *soc = pdev->soc;
  951. int ret = 0;
  952. if (ipa_res->is_db_ddr_mapped)
  953. ipa_res->tx_comp_doorbell_vaddr =
  954. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  955. else
  956. ipa_res->tx_comp_doorbell_vaddr =
  957. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  958. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  959. ret = pld_smmu_map(soc->osdev->dev,
  960. ipa_res->tx_comp_doorbell_paddr,
  961. &tx_comp_doorbell_dmaaddr,
  962. sizeof(uint32_t));
  963. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  964. qdf_assert_always(!ret);
  965. ret = pld_smmu_map(soc->osdev->dev,
  966. ipa_res->rx_ready_doorbell_paddr,
  967. &rx_ready_doorbell_dmaaddr,
  968. sizeof(uint32_t));
  969. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  970. qdf_assert_always(!ret);
  971. }
  972. }
  973. static inline void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  974. {
  975. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  976. struct dp_soc *soc = pdev->soc;
  977. int ret = 0;
  978. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  979. return;
  980. ret = pld_smmu_unmap(soc->osdev->dev,
  981. ipa_res->rx_ready_doorbell_paddr,
  982. sizeof(uint32_t));
  983. qdf_assert_always(!ret);
  984. ret = pld_smmu_unmap(soc->osdev->dev,
  985. ipa_res->tx_comp_doorbell_paddr,
  986. sizeof(uint32_t));
  987. qdf_assert_always(!ret);
  988. }
  989. static inline QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  990. struct dp_pdev *pdev,
  991. bool create,
  992. const char *func,
  993. uint32_t line)
  994. {
  995. return QDF_STATUS_SUCCESS;
  996. }
  997. static inline
  998. void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc, struct dp_ipa_resources *res,
  999. qdf_ipa_wdi_conn_in_params_t *in)
  1000. {
  1001. }
  1002. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  1003. qdf_ipa_wdi_conn_out_params_t *out)
  1004. {
  1005. res->tx_comp_doorbell_paddr =
  1006. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  1007. res->rx_ready_doorbell_paddr =
  1008. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  1009. }
  1010. #ifdef IPA_WDS_EASYMESH_FEATURE
  1011. /**
  1012. * dp_ipa_setup_iface_session_id() - Pass vdev id to IPA
  1013. * @in: ipa in params
  1014. * @session_id: vdev id
  1015. *
  1016. * Pass Vdev id to IPA, IPA metadata order is changed and vdev id
  1017. * is stored at higher nibble so, no shift is required.
  1018. *
  1019. * Return: none
  1020. */
  1021. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1022. uint8_t session_id)
  1023. {
  1024. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id);
  1025. }
  1026. #else
  1027. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1028. uint8_t session_id)
  1029. {
  1030. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  1031. }
  1032. #endif
  1033. static inline void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  1034. struct dp_ipa_resources *res)
  1035. {
  1036. struct hal_srng *wbm_srng = (struct hal_srng *)
  1037. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1038. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  1039. res->tx_comp_doorbell_vaddr);
  1040. }
  1041. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  1042. struct dp_ipa_resources *ipa_res)
  1043. {
  1044. struct hal_srng *wbm_srng = (struct hal_srng *)
  1045. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1046. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  1047. ipa_res->tx_comp_doorbell_paddr);
  1048. dp_info("paddr %pK vaddr %pK",
  1049. (void *)ipa_res->tx_comp_doorbell_paddr,
  1050. (void *)ipa_res->tx_comp_doorbell_vaddr);
  1051. }
  1052. #ifdef IPA_SET_RESET_TX_DB_PA
  1053. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  1054. struct dp_ipa_resources *ipa_res)
  1055. {
  1056. hal_ring_handle_t wbm_srng =
  1057. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1058. qdf_dma_addr_t hp_addr;
  1059. if (!wbm_srng)
  1060. return QDF_STATUS_E_FAILURE;
  1061. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  1062. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  1063. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  1064. return QDF_STATUS_SUCCESS;
  1065. }
  1066. #endif /* IPA_SET_RESET_TX_DB_PA */
  1067. #endif /* IPA_WDI3_TX_TWO_PIPES */
  1068. /**
  1069. * dp_tx_ipa_uc_detach() - Free autonomy TX resources
  1070. * @soc: data path instance
  1071. * @pdev: core txrx pdev context
  1072. *
  1073. * Free allocated TX buffers with WBM SRNG
  1074. *
  1075. * Return: none
  1076. */
  1077. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1078. {
  1079. int idx;
  1080. qdf_nbuf_t nbuf;
  1081. struct dp_ipa_resources *ipa_res;
  1082. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  1083. nbuf = (qdf_nbuf_t)
  1084. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx];
  1085. if (!nbuf)
  1086. continue;
  1087. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  1088. qdf_mem_dp_tx_skb_cnt_dec();
  1089. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  1090. qdf_nbuf_free(nbuf);
  1091. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
  1092. (void *)NULL;
  1093. }
  1094. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1095. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1096. ipa_res = &pdev->ipa_resource;
  1097. qdf_mem_free_sgtable(&ipa_res->tx_ring.sgtable);
  1098. qdf_mem_free_sgtable(&ipa_res->tx_comp_ring.sgtable);
  1099. }
  1100. /**
  1101. * dp_rx_ipa_uc_detach() - free autonomy RX resources
  1102. * @soc: data path instance
  1103. * @pdev: core txrx pdev context
  1104. *
  1105. * This function will detach DP RX into main device context
  1106. * will free DP Rx resources.
  1107. *
  1108. * Return: none
  1109. */
  1110. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1111. {
  1112. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1113. qdf_mem_free_sgtable(&ipa_res->rx_rdy_ring.sgtable);
  1114. qdf_mem_free_sgtable(&ipa_res->rx_refill_ring.sgtable);
  1115. }
  1116. /**
  1117. * dp_rx_alt_ipa_uc_detach() - free autonomy RX resources
  1118. * @soc: data path instance
  1119. * @pdev: core txrx pdev context
  1120. *
  1121. * This function will detach DP RX into main device context
  1122. * will free DP Rx resources.
  1123. *
  1124. * Return: none
  1125. */
  1126. #ifdef IPA_WDI3_VLAN_SUPPORT
  1127. static void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1128. {
  1129. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1130. if (!wlan_ipa_is_vlan_enabled())
  1131. return;
  1132. qdf_mem_free_sgtable(&ipa_res->rx_alt_rdy_ring.sgtable);
  1133. qdf_mem_free_sgtable(&ipa_res->rx_alt_refill_ring.sgtable);
  1134. }
  1135. #else
  1136. static inline
  1137. void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1138. { }
  1139. #endif
  1140. int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1141. {
  1142. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1143. return QDF_STATUS_SUCCESS;
  1144. /* TX resource detach */
  1145. dp_tx_ipa_uc_detach(soc, pdev);
  1146. /* Cleanup 2nd TX pipe resources */
  1147. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1148. /* RX resource detach */
  1149. dp_rx_ipa_uc_detach(soc, pdev);
  1150. /* Cleanup 2nd RX pipe resources */
  1151. dp_rx_alt_ipa_uc_detach(soc, pdev);
  1152. return QDF_STATUS_SUCCESS; /* success */
  1153. }
  1154. /**
  1155. * dp_tx_ipa_uc_attach() - Allocate autonomy TX resources
  1156. * @soc: data path instance
  1157. * @pdev: Physical device handle
  1158. *
  1159. * Allocate TX buffer from non-cacheable memory
  1160. * Attach allocated TX buffers with WBM SRNG
  1161. *
  1162. * Return: int
  1163. */
  1164. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1165. {
  1166. uint32_t tx_buffer_count;
  1167. uint32_t ring_base_align = 8;
  1168. qdf_dma_addr_t buffer_paddr;
  1169. struct hal_srng *wbm_srng = (struct hal_srng *)
  1170. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1171. struct hal_srng_params srng_params;
  1172. void *ring_entry;
  1173. int num_entries;
  1174. qdf_nbuf_t nbuf;
  1175. int retval = QDF_STATUS_SUCCESS;
  1176. int max_alloc_count = 0;
  1177. uint32_t wbm_bm_id;
  1178. /*
  1179. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  1180. * unsigned int uc_tx_buf_sz =
  1181. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  1182. */
  1183. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  1184. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  1185. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  1186. IPA_TCL_DATA_RING_IDX);
  1187. hal_get_srng_params(soc->hal_soc, hal_srng_to_hal_ring_handle(wbm_srng),
  1188. &srng_params);
  1189. num_entries = srng_params.num_entries;
  1190. max_alloc_count =
  1191. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  1192. if (max_alloc_count <= 0) {
  1193. dp_err("incorrect value for buffer count %u", max_alloc_count);
  1194. return -EINVAL;
  1195. }
  1196. dp_info("requested %d buffers to be posted to wbm ring",
  1197. max_alloc_count);
  1198. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned =
  1199. qdf_mem_malloc(num_entries *
  1200. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned));
  1201. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned) {
  1202. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  1203. return -ENOMEM;
  1204. }
  1205. hal_srng_access_start_unlocked(soc->hal_soc,
  1206. hal_srng_to_hal_ring_handle(wbm_srng));
  1207. /*
  1208. * Allocate Tx buffers as many as possible.
  1209. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  1210. * Populate Tx buffers into WBM2IPA ring
  1211. * This initial buffer population will simulate H/W as source ring,
  1212. * and update HP
  1213. */
  1214. for (tx_buffer_count = 0;
  1215. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  1216. nbuf = qdf_nbuf_alloc(soc->osdev, alloc_size, 0, 256, FALSE);
  1217. if (!nbuf)
  1218. break;
  1219. ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
  1220. hal_srng_to_hal_ring_handle(wbm_srng));
  1221. if (!ring_entry) {
  1222. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1223. "%s: Failed to get WBM ring entry",
  1224. __func__);
  1225. qdf_nbuf_free(nbuf);
  1226. break;
  1227. }
  1228. qdf_nbuf_map_single(soc->osdev, nbuf,
  1229. QDF_DMA_BIDIRECTIONAL);
  1230. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1231. qdf_mem_dp_tx_skb_cnt_inc();
  1232. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  1233. /*
  1234. * TODO - KIWI code can directly call the be handler
  1235. * instead of hal soc ops.
  1236. */
  1237. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  1238. buffer_paddr, 0, wbm_bm_id);
  1239. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
  1240. = (void *)nbuf;
  1241. }
  1242. hal_srng_access_end_unlocked(soc->hal_soc,
  1243. hal_srng_to_hal_ring_handle(wbm_srng));
  1244. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  1245. if (tx_buffer_count) {
  1246. dp_info("IPA WDI TX buffer: %d allocated", tx_buffer_count);
  1247. } else {
  1248. dp_err("No IPA WDI TX buffer allocated!");
  1249. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1250. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1251. retval = -ENOMEM;
  1252. }
  1253. return retval;
  1254. }
  1255. /**
  1256. * dp_rx_ipa_uc_attach() - Allocate autonomy RX resources
  1257. * @soc: data path instance
  1258. * @pdev: core txrx pdev context
  1259. *
  1260. * This function will attach a DP RX instance into the main
  1261. * device (SOC) context.
  1262. *
  1263. * Return: QDF_STATUS_SUCCESS: success
  1264. * QDF_STATUS_E_RESOURCES: Error return
  1265. */
  1266. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1267. {
  1268. return QDF_STATUS_SUCCESS;
  1269. }
  1270. int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1271. {
  1272. int error;
  1273. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1274. return QDF_STATUS_SUCCESS;
  1275. /* TX resource attach */
  1276. error = dp_tx_ipa_uc_attach(soc, pdev);
  1277. if (error) {
  1278. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1279. "%s: DP IPA UC TX attach fail code %d",
  1280. __func__, error);
  1281. return error;
  1282. }
  1283. /* Setup 2nd TX pipe */
  1284. error = dp_ipa_tx_alt_pool_attach(soc);
  1285. if (error) {
  1286. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1287. "%s: DP IPA TX pool2 attach fail code %d",
  1288. __func__, error);
  1289. dp_tx_ipa_uc_detach(soc, pdev);
  1290. return error;
  1291. }
  1292. /* RX resource attach */
  1293. error = dp_rx_ipa_uc_attach(soc, pdev);
  1294. if (error) {
  1295. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1296. "%s: DP IPA UC RX attach fail code %d",
  1297. __func__, error);
  1298. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1299. dp_tx_ipa_uc_detach(soc, pdev);
  1300. return error;
  1301. }
  1302. return QDF_STATUS_SUCCESS; /* success */
  1303. }
  1304. #ifdef IPA_WDI3_VLAN_SUPPORT
  1305. /**
  1306. * dp_ipa_rx_alt_ring_resource_setup() - setup IPA 2nd RX ring resources
  1307. * @soc: data path SoC handle
  1308. * @pdev: data path pdev handle
  1309. *
  1310. * Return: none
  1311. */
  1312. static
  1313. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1314. {
  1315. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1316. struct hal_srng *hal_srng;
  1317. struct hal_srng_params srng_params;
  1318. unsigned long addr_offset, dev_base_paddr;
  1319. qdf_dma_addr_t hp_addr;
  1320. if (!wlan_ipa_is_vlan_enabled())
  1321. return;
  1322. dev_base_paddr =
  1323. (unsigned long)
  1324. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1325. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW3 */
  1326. hal_srng = (struct hal_srng *)
  1327. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1328. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1329. hal_srng_to_hal_ring_handle(hal_srng),
  1330. &srng_params);
  1331. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr =
  1332. srng_params.ring_base_paddr;
  1333. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr =
  1334. srng_params.ring_base_vaddr;
  1335. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size =
  1336. (srng_params.num_entries * srng_params.entry_size) << 2;
  1337. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1338. (unsigned long)(hal_soc->dev_base_addr);
  1339. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr =
  1340. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1341. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1342. (unsigned int)addr_offset,
  1343. (unsigned int)dev_base_paddr,
  1344. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr),
  1345. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1346. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1347. srng_params.num_entries,
  1348. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1349. hal_srng = (struct hal_srng *)
  1350. pdev->rx_refill_buf_ring3.hal_srng;
  1351. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1352. hal_srng_to_hal_ring_handle(hal_srng),
  1353. &srng_params);
  1354. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr =
  1355. srng_params.ring_base_paddr;
  1356. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr =
  1357. srng_params.ring_base_vaddr;
  1358. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size =
  1359. (srng_params.num_entries * srng_params.entry_size) << 2;
  1360. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1361. hal_srng_to_hal_ring_handle(hal_srng));
  1362. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr =
  1363. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1364. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1365. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr),
  1366. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1367. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1368. srng_params.num_entries,
  1369. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1370. }
  1371. #else
  1372. static inline
  1373. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1374. { }
  1375. #endif
  1376. int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1377. struct dp_pdev *pdev)
  1378. {
  1379. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1380. struct hal_srng *hal_srng;
  1381. struct hal_srng_params srng_params;
  1382. qdf_dma_addr_t hp_addr;
  1383. unsigned long addr_offset, dev_base_paddr;
  1384. uint32_t ix0;
  1385. uint8_t ix0_map[8];
  1386. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1387. return QDF_STATUS_SUCCESS;
  1388. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL3 */
  1389. hal_srng = (struct hal_srng *)
  1390. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1391. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1392. hal_srng_to_hal_ring_handle(hal_srng),
  1393. &srng_params);
  1394. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1395. srng_params.ring_base_paddr;
  1396. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1397. srng_params.ring_base_vaddr;
  1398. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1399. (srng_params.num_entries * srng_params.entry_size) << 2;
  1400. /*
  1401. * For the register backed memory addresses, use the scn->mem_pa to
  1402. * calculate the physical address of the shadow registers
  1403. */
  1404. dev_base_paddr =
  1405. (unsigned long)
  1406. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1407. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  1408. (unsigned long)(hal_soc->dev_base_addr);
  1409. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr =
  1410. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1411. dp_info("IPA TCL_DATA Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1412. (unsigned int)addr_offset,
  1413. (unsigned int)dev_base_paddr,
  1414. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr),
  1415. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1416. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1417. srng_params.num_entries,
  1418. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1419. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW2_RELEASE */
  1420. hal_srng = (struct hal_srng *)
  1421. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1422. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1423. hal_srng_to_hal_ring_handle(hal_srng),
  1424. &srng_params);
  1425. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1426. srng_params.ring_base_paddr;
  1427. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1428. srng_params.ring_base_vaddr;
  1429. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1430. (srng_params.num_entries * srng_params.entry_size) << 2;
  1431. soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr =
  1432. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1433. hal_srng_to_hal_ring_handle(hal_srng));
  1434. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1435. (unsigned long)(hal_soc->dev_base_addr);
  1436. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr =
  1437. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1438. dp_info("IPA TX COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  1439. (unsigned int)addr_offset,
  1440. (unsigned int)dev_base_paddr,
  1441. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr),
  1442. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1443. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1444. srng_params.num_entries,
  1445. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1446. dp_ipa_tx_alt_ring_resource_setup(soc);
  1447. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1448. hal_srng = (struct hal_srng *)
  1449. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1450. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1451. hal_srng_to_hal_ring_handle(hal_srng),
  1452. &srng_params);
  1453. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1454. srng_params.ring_base_paddr;
  1455. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1456. srng_params.ring_base_vaddr;
  1457. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1458. (srng_params.num_entries * srng_params.entry_size) << 2;
  1459. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1460. (unsigned long)(hal_soc->dev_base_addr);
  1461. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr =
  1462. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1463. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1464. (unsigned int)addr_offset,
  1465. (unsigned int)dev_base_paddr,
  1466. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr),
  1467. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1468. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1469. srng_params.num_entries,
  1470. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1471. hal_srng = (struct hal_srng *)
  1472. pdev->rx_refill_buf_ring2.hal_srng;
  1473. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1474. hal_srng_to_hal_ring_handle(hal_srng),
  1475. &srng_params);
  1476. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1477. srng_params.ring_base_paddr;
  1478. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1479. srng_params.ring_base_vaddr;
  1480. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1481. (srng_params.num_entries * srng_params.entry_size) << 2;
  1482. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1483. hal_srng_to_hal_ring_handle(hal_srng));
  1484. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr =
  1485. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1486. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1487. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr),
  1488. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1489. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1490. srng_params.num_entries,
  1491. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1492. /*
  1493. * Set DEST_RING_MAPPING_4 to SW2 as default value for
  1494. * DESTINATION_RING_CTRL_IX_0.
  1495. */
  1496. ix0_map[0] = REO_REMAP_SW1;
  1497. ix0_map[1] = REO_REMAP_SW1;
  1498. ix0_map[2] = REO_REMAP_SW2;
  1499. ix0_map[3] = REO_REMAP_SW3;
  1500. ix0_map[4] = REO_REMAP_SW2;
  1501. ix0_map[5] = REO_REMAP_RELEASE;
  1502. ix0_map[6] = REO_REMAP_FW;
  1503. ix0_map[7] = REO_REMAP_FW;
  1504. dp_ipa_opt_dp_ixo_remap(ix0_map);
  1505. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1506. ix0_map);
  1507. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL, NULL, NULL);
  1508. dp_ipa_rx_alt_ring_resource_setup(soc, pdev);
  1509. return 0;
  1510. }
  1511. #ifdef IPA_WDI3_VLAN_SUPPORT
  1512. /**
  1513. * dp_ipa_rx_alt_ring_get_resource() - get IPA 2nd RX ring resources
  1514. * @pdev: data path pdev handle
  1515. *
  1516. * Return: Success if resourece is found
  1517. */
  1518. static QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1519. {
  1520. struct dp_soc *soc = pdev->soc;
  1521. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1522. if (!wlan_ipa_is_vlan_enabled())
  1523. return QDF_STATUS_SUCCESS;
  1524. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_alt_rdy_ring,
  1525. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1526. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1527. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1528. dp_ipa_get_shared_mem_info(
  1529. soc->osdev, &ipa_res->rx_alt_refill_ring,
  1530. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1531. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1532. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1533. if (!qdf_mem_get_dma_addr(soc->osdev,
  1534. &ipa_res->rx_alt_rdy_ring.mem_info) ||
  1535. !qdf_mem_get_dma_addr(soc->osdev,
  1536. &ipa_res->rx_alt_refill_ring.mem_info))
  1537. return QDF_STATUS_E_FAILURE;
  1538. return QDF_STATUS_SUCCESS;
  1539. }
  1540. #else
  1541. static inline QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1542. {
  1543. return QDF_STATUS_SUCCESS;
  1544. }
  1545. #endif
  1546. QDF_STATUS dp_ipa_get_resource(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1547. {
  1548. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1549. struct dp_pdev *pdev =
  1550. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1551. struct dp_ipa_resources *ipa_res;
  1552. if (!pdev) {
  1553. dp_err("Invalid instance");
  1554. return QDF_STATUS_E_FAILURE;
  1555. }
  1556. ipa_res = &pdev->ipa_resource;
  1557. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1558. return QDF_STATUS_SUCCESS;
  1559. ipa_res->tx_num_alloc_buffer =
  1560. (uint32_t)soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  1561. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_ring,
  1562. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1563. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1564. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1565. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_comp_ring,
  1566. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1567. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1568. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1569. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_rdy_ring,
  1570. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1571. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1572. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1573. dp_ipa_get_shared_mem_info(
  1574. soc->osdev, &ipa_res->rx_refill_ring,
  1575. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1576. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1577. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1578. if (!qdf_mem_get_dma_addr(soc->osdev, &ipa_res->tx_ring.mem_info) ||
  1579. !qdf_mem_get_dma_addr(soc->osdev,
  1580. &ipa_res->tx_comp_ring.mem_info) ||
  1581. !qdf_mem_get_dma_addr(soc->osdev, &ipa_res->rx_rdy_ring.mem_info) ||
  1582. !qdf_mem_get_dma_addr(soc->osdev,
  1583. &ipa_res->rx_refill_ring.mem_info))
  1584. return QDF_STATUS_E_FAILURE;
  1585. if (dp_ipa_tx_alt_ring_get_resource(pdev))
  1586. return QDF_STATUS_E_FAILURE;
  1587. if (dp_ipa_rx_alt_ring_get_resource(pdev))
  1588. return QDF_STATUS_E_FAILURE;
  1589. return QDF_STATUS_SUCCESS;
  1590. }
  1591. #ifdef IPA_SET_RESET_TX_DB_PA
  1592. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res)
  1593. #else
  1594. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res) \
  1595. dp_ipa_set_tx_doorbell_paddr(soc, ipa_res)
  1596. #endif
  1597. #ifdef IPA_WDI3_VLAN_SUPPORT
  1598. /**
  1599. * dp_ipa_map_rx_alt_ring_doorbell_paddr() - Map 2nd rx ring doorbell paddr
  1600. * @pdev: data path pdev handle
  1601. *
  1602. * Return: none
  1603. */
  1604. static void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1605. {
  1606. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1607. uint32_t rx_ready_doorbell_dmaaddr;
  1608. struct dp_soc *soc = pdev->soc;
  1609. struct hal_srng *reo_srng = (struct hal_srng *)
  1610. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1611. int ret = 0;
  1612. if (!wlan_ipa_is_vlan_enabled())
  1613. return;
  1614. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1615. ret = pld_smmu_map(soc->osdev->dev,
  1616. ipa_res->rx_alt_ready_doorbell_paddr,
  1617. &rx_ready_doorbell_dmaaddr,
  1618. sizeof(uint32_t));
  1619. ipa_res->rx_alt_ready_doorbell_paddr =
  1620. rx_ready_doorbell_dmaaddr;
  1621. qdf_assert_always(!ret);
  1622. }
  1623. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1624. ipa_res->rx_alt_ready_doorbell_paddr);
  1625. }
  1626. /**
  1627. * dp_ipa_unmap_rx_alt_ring_doorbell_paddr() - Unmap 2nd rx ring doorbell paddr
  1628. * @pdev: data path pdev handle
  1629. *
  1630. * Return: none
  1631. */
  1632. static void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1633. {
  1634. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1635. struct dp_soc *soc = pdev->soc;
  1636. int ret = 0;
  1637. if (!wlan_ipa_is_vlan_enabled())
  1638. return;
  1639. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  1640. return;
  1641. ret = pld_smmu_unmap(soc->osdev->dev,
  1642. ipa_res->rx_alt_ready_doorbell_paddr,
  1643. sizeof(uint32_t));
  1644. qdf_assert_always(!ret);
  1645. }
  1646. #else
  1647. static inline void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1648. { }
  1649. static inline void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1650. { }
  1651. #endif
  1652. QDF_STATUS dp_ipa_set_doorbell_paddr(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1653. {
  1654. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1655. struct dp_pdev *pdev =
  1656. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1657. struct dp_ipa_resources *ipa_res;
  1658. struct hal_srng *reo_srng = (struct hal_srng *)
  1659. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1660. if (!pdev) {
  1661. dp_err("Invalid instance");
  1662. return QDF_STATUS_E_FAILURE;
  1663. }
  1664. ipa_res = &pdev->ipa_resource;
  1665. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1666. return QDF_STATUS_SUCCESS;
  1667. dp_ipa_map_ring_doorbell_paddr(pdev);
  1668. dp_ipa_map_rx_alt_ring_doorbell_paddr(pdev);
  1669. DP_IPA_SET_TX_DB_PADDR(soc, ipa_res);
  1670. /*
  1671. * For RX, REO module on Napier/Hastings does reordering on incoming
  1672. * Ethernet packets and writes one or more descriptors to REO2IPA Rx
  1673. * ring.It then updates the ring’s Write/Head ptr and rings a doorbell
  1674. * to IPA.
  1675. * Set the doorbell addr for the REO ring.
  1676. */
  1677. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1678. ipa_res->rx_ready_doorbell_paddr);
  1679. return QDF_STATUS_SUCCESS;
  1680. }
  1681. QDF_STATUS dp_ipa_iounmap_doorbell_vaddr(struct cdp_soc_t *soc_hdl,
  1682. uint8_t pdev_id)
  1683. {
  1684. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1685. struct dp_pdev *pdev =
  1686. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1687. struct dp_ipa_resources *ipa_res;
  1688. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1689. return QDF_STATUS_SUCCESS;
  1690. if (!pdev) {
  1691. dp_err("Invalid instance");
  1692. return QDF_STATUS_E_FAILURE;
  1693. }
  1694. ipa_res = &pdev->ipa_resource;
  1695. if (!ipa_res->is_db_ddr_mapped)
  1696. iounmap(ipa_res->tx_comp_doorbell_vaddr);
  1697. return QDF_STATUS_SUCCESS;
  1698. }
  1699. QDF_STATUS dp_ipa_op_response(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1700. uint8_t *op_msg)
  1701. {
  1702. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1703. struct dp_pdev *pdev =
  1704. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1705. if (!pdev) {
  1706. dp_err("Invalid instance");
  1707. return QDF_STATUS_E_FAILURE;
  1708. }
  1709. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1710. return QDF_STATUS_SUCCESS;
  1711. if (pdev->ipa_uc_op_cb) {
  1712. pdev->ipa_uc_op_cb(op_msg, pdev->usr_ctxt);
  1713. } else {
  1714. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1715. "%s: IPA callback function is not registered", __func__);
  1716. qdf_mem_free(op_msg);
  1717. return QDF_STATUS_E_FAILURE;
  1718. }
  1719. return QDF_STATUS_SUCCESS;
  1720. }
  1721. QDF_STATUS dp_ipa_register_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1722. ipa_uc_op_cb_type op_cb,
  1723. void *usr_ctxt)
  1724. {
  1725. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1726. struct dp_pdev *pdev =
  1727. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1728. if (!pdev) {
  1729. dp_err("Invalid instance");
  1730. return QDF_STATUS_E_FAILURE;
  1731. }
  1732. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1733. return QDF_STATUS_SUCCESS;
  1734. pdev->ipa_uc_op_cb = op_cb;
  1735. pdev->usr_ctxt = usr_ctxt;
  1736. return QDF_STATUS_SUCCESS;
  1737. }
  1738. void dp_ipa_deregister_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1739. {
  1740. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1741. struct dp_pdev *pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1742. if (!pdev) {
  1743. dp_err("Invalid instance");
  1744. return;
  1745. }
  1746. dp_debug("Deregister OP handler callback");
  1747. pdev->ipa_uc_op_cb = NULL;
  1748. pdev->usr_ctxt = NULL;
  1749. }
  1750. QDF_STATUS dp_ipa_get_stat(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1751. {
  1752. /* TBD */
  1753. return QDF_STATUS_SUCCESS;
  1754. }
  1755. qdf_nbuf_t dp_tx_send_ipa_data_frame(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1756. qdf_nbuf_t skb)
  1757. {
  1758. qdf_nbuf_t ret;
  1759. /* Terminate the (single-element) list of tx frames */
  1760. qdf_nbuf_set_next(skb, NULL);
  1761. ret = dp_tx_send(soc_hdl, vdev_id, skb);
  1762. if (ret) {
  1763. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1764. "%s: Failed to tx", __func__);
  1765. return ret;
  1766. }
  1767. return NULL;
  1768. }
  1769. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  1770. /**
  1771. * dp_ipa_is_target_ready() - check if target is ready or not
  1772. * @soc: datapath soc handle
  1773. *
  1774. * Return: true if target is ready
  1775. */
  1776. static inline
  1777. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1778. {
  1779. if (hif_get_target_status(soc->hif_handle) == TARGET_STATUS_RESET)
  1780. return false;
  1781. else
  1782. return true;
  1783. }
  1784. #else
  1785. static inline
  1786. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1787. {
  1788. return true;
  1789. }
  1790. #endif
  1791. QDF_STATUS dp_ipa_enable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1792. {
  1793. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1794. struct dp_pdev *pdev =
  1795. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1796. uint32_t ix0;
  1797. uint32_t ix2;
  1798. uint8_t ix_map[8];
  1799. if (!pdev) {
  1800. dp_err("Invalid instance");
  1801. return QDF_STATUS_E_FAILURE;
  1802. }
  1803. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1804. return QDF_STATUS_SUCCESS;
  1805. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1806. return QDF_STATUS_E_AGAIN;
  1807. if (!dp_ipa_is_target_ready(soc))
  1808. return QDF_STATUS_E_AGAIN;
  1809. /* Call HAL API to remap REO rings to REO2IPA ring */
  1810. ix_map[0] = REO_REMAP_SW1;
  1811. ix_map[1] = REO_REMAP_SW4;
  1812. ix_map[2] = REO_REMAP_SW1;
  1813. if (wlan_ipa_is_vlan_enabled())
  1814. ix_map[3] = REO_REMAP_SW3;
  1815. else
  1816. ix_map[3] = REO_REMAP_SW4;
  1817. ix_map[4] = REO_REMAP_SW4;
  1818. ix_map[5] = REO_REMAP_RELEASE;
  1819. ix_map[6] = REO_REMAP_FW;
  1820. ix_map[7] = REO_REMAP_FW;
  1821. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1822. ix_map);
  1823. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1824. ix_map[0] = REO_REMAP_SW4;
  1825. ix_map[1] = REO_REMAP_SW4;
  1826. ix_map[2] = REO_REMAP_SW4;
  1827. ix_map[3] = REO_REMAP_SW4;
  1828. ix_map[4] = REO_REMAP_SW4;
  1829. ix_map[5] = REO_REMAP_SW4;
  1830. ix_map[6] = REO_REMAP_SW4;
  1831. ix_map[7] = REO_REMAP_SW4;
  1832. ix2 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX2,
  1833. ix_map);
  1834. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1835. &ix2, &ix2);
  1836. dp_ipa_reo_remap_history_add(ix0, ix2, ix2);
  1837. } else {
  1838. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1839. NULL, NULL);
  1840. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1841. }
  1842. return QDF_STATUS_SUCCESS;
  1843. }
  1844. QDF_STATUS dp_ipa_disable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1845. {
  1846. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1847. struct dp_pdev *pdev =
  1848. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1849. uint8_t ix0_map[8];
  1850. uint32_t ix0;
  1851. uint32_t ix1;
  1852. uint32_t ix2;
  1853. uint32_t ix3;
  1854. if (!pdev) {
  1855. dp_err("Invalid instance");
  1856. return QDF_STATUS_E_FAILURE;
  1857. }
  1858. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1859. return QDF_STATUS_SUCCESS;
  1860. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1861. return QDF_STATUS_E_AGAIN;
  1862. if (!dp_ipa_is_target_ready(soc))
  1863. return QDF_STATUS_E_AGAIN;
  1864. ix0_map[0] = REO_REMAP_SW1;
  1865. ix0_map[1] = REO_REMAP_SW1;
  1866. ix0_map[2] = REO_REMAP_SW2;
  1867. ix0_map[3] = REO_REMAP_SW3;
  1868. ix0_map[4] = REO_REMAP_SW2;
  1869. ix0_map[5] = REO_REMAP_RELEASE;
  1870. ix0_map[6] = REO_REMAP_FW;
  1871. ix0_map[7] = REO_REMAP_FW;
  1872. /* Call HAL API to remap REO rings to REO2IPA ring */
  1873. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1874. ix0_map);
  1875. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1876. dp_reo_remap_config(soc, &ix1, &ix2, &ix3);
  1877. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1878. &ix2, &ix3);
  1879. dp_ipa_reo_remap_history_add(ix0, ix2, ix3);
  1880. } else {
  1881. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1882. NULL, NULL);
  1883. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1884. }
  1885. return QDF_STATUS_SUCCESS;
  1886. }
  1887. /* This should be configurable per H/W configuration enable status */
  1888. #define L3_HEADER_PADDING 2
  1889. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  1890. defined(CONFIG_IPA_WDI_UNIFIED_API)
  1891. #if !defined(QCA_LL_TX_FLOW_CONTROL_V2) && !defined(QCA_IPA_LL_TX_FLOW_CONTROL)
  1892. static inline void dp_setup_mcc_sys_pipes(
  1893. qdf_ipa_sys_connect_params_t *sys_in,
  1894. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  1895. {
  1896. int i = 0;
  1897. /* Setup MCC sys pipe */
  1898. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) =
  1899. DP_IPA_MAX_IFACE;
  1900. for (i = 0; i < DP_IPA_MAX_IFACE; i++)
  1901. memcpy(&QDF_IPA_WDI_CONN_IN_PARAMS_SYS_IN(pipe_in)[i],
  1902. &sys_in[i], sizeof(qdf_ipa_sys_connect_params_t));
  1903. }
  1904. #else
  1905. static inline void dp_setup_mcc_sys_pipes(
  1906. qdf_ipa_sys_connect_params_t *sys_in,
  1907. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  1908. {
  1909. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) = 0;
  1910. }
  1911. #endif
  1912. static void dp_ipa_wdi_tx_params(struct dp_soc *soc,
  1913. struct dp_ipa_resources *ipa_res,
  1914. qdf_ipa_wdi_pipe_setup_info_t *tx,
  1915. bool over_gsi)
  1916. {
  1917. if (over_gsi)
  1918. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS;
  1919. else
  1920. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  1921. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  1922. qdf_mem_get_dma_addr(soc->osdev,
  1923. &ipa_res->tx_comp_ring.mem_info);
  1924. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  1925. qdf_mem_get_dma_size(soc->osdev,
  1926. &ipa_res->tx_comp_ring.mem_info);
  1927. /* WBM Tail Pointer Address */
  1928. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  1929. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  1930. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  1931. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  1932. qdf_mem_get_dma_addr(soc->osdev,
  1933. &ipa_res->tx_ring.mem_info);
  1934. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  1935. qdf_mem_get_dma_size(soc->osdev,
  1936. &ipa_res->tx_ring.mem_info);
  1937. /* TCL Head Pointer Address */
  1938. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  1939. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  1940. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  1941. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  1942. ipa_res->tx_num_alloc_buffer;
  1943. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  1944. dp_ipa_setup_tx_params_bank_id(soc, tx);
  1945. /* Set Pmac ID, extract pmac_id from pdev_id 0 for TX ring */
  1946. dp_ipa_setup_tx_params_pmac_id(soc, tx);
  1947. }
  1948. static void dp_ipa_wdi_rx_params(struct dp_soc *soc,
  1949. struct dp_ipa_resources *ipa_res,
  1950. qdf_ipa_wdi_pipe_setup_info_t *rx,
  1951. bool over_gsi)
  1952. {
  1953. if (over_gsi)
  1954. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  1955. IPA_CLIENT_WLAN2_PROD;
  1956. else
  1957. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  1958. IPA_CLIENT_WLAN1_PROD;
  1959. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  1960. qdf_mem_get_dma_addr(soc->osdev,
  1961. &ipa_res->rx_rdy_ring.mem_info);
  1962. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  1963. qdf_mem_get_dma_size(soc->osdev,
  1964. &ipa_res->rx_rdy_ring.mem_info);
  1965. /* REO Tail Pointer Address */
  1966. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  1967. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  1968. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  1969. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  1970. qdf_mem_get_dma_addr(soc->osdev,
  1971. &ipa_res->rx_refill_ring.mem_info);
  1972. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  1973. qdf_mem_get_dma_size(soc->osdev,
  1974. &ipa_res->rx_refill_ring.mem_info);
  1975. /* FW Head Pointer Address */
  1976. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  1977. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  1978. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  1979. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  1980. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  1981. }
  1982. static void
  1983. dp_ipa_wdi_tx_smmu_params(struct dp_soc *soc,
  1984. struct dp_ipa_resources *ipa_res,
  1985. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu,
  1986. bool over_gsi,
  1987. qdf_ipa_wdi_hdl_t hdl)
  1988. {
  1989. if (over_gsi) {
  1990. if (hdl == DP_IPA_HDL_FIRST)
  1991. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  1992. IPA_CLIENT_WLAN2_CONS;
  1993. else if (hdl == DP_IPA_HDL_SECOND)
  1994. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  1995. IPA_CLIENT_WLAN4_CONS;
  1996. } else {
  1997. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  1998. IPA_CLIENT_WLAN1_CONS;
  1999. }
  2000. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  2001. &ipa_res->tx_comp_ring.sgtable,
  2002. sizeof(sgtable_t));
  2003. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  2004. qdf_mem_get_dma_size(soc->osdev,
  2005. &ipa_res->tx_comp_ring.mem_info);
  2006. /* WBM Tail Pointer Address */
  2007. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  2008. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2009. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  2010. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  2011. &ipa_res->tx_ring.sgtable,
  2012. sizeof(sgtable_t));
  2013. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  2014. qdf_mem_get_dma_size(soc->osdev,
  2015. &ipa_res->tx_ring.mem_info);
  2016. /* TCL Head Pointer Address */
  2017. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  2018. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2019. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  2020. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  2021. ipa_res->tx_num_alloc_buffer;
  2022. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  2023. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  2024. /* Set Pmac ID, extract pmac_id from first pdev for TX ring */
  2025. dp_ipa_setup_tx_smmu_params_pmac_id(soc, tx_smmu);
  2026. }
  2027. static void
  2028. dp_ipa_wdi_rx_smmu_params(struct dp_soc *soc,
  2029. struct dp_ipa_resources *ipa_res,
  2030. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2031. bool over_gsi,
  2032. qdf_ipa_wdi_hdl_t hdl)
  2033. {
  2034. if (over_gsi) {
  2035. if (hdl == DP_IPA_HDL_FIRST)
  2036. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2037. IPA_CLIENT_WLAN2_PROD;
  2038. else if (hdl == DP_IPA_HDL_SECOND)
  2039. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2040. IPA_CLIENT_WLAN3_PROD;
  2041. } else {
  2042. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2043. IPA_CLIENT_WLAN1_PROD;
  2044. }
  2045. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2046. &ipa_res->rx_rdy_ring.sgtable,
  2047. sizeof(sgtable_t));
  2048. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2049. qdf_mem_get_dma_size(soc->osdev,
  2050. &ipa_res->rx_rdy_ring.mem_info);
  2051. /* REO Tail Pointer Address */
  2052. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2053. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2054. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  2055. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2056. &ipa_res->rx_refill_ring.sgtable,
  2057. sizeof(sgtable_t));
  2058. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2059. qdf_mem_get_dma_size(soc->osdev,
  2060. &ipa_res->rx_refill_ring.mem_info);
  2061. /* FW Head Pointer Address */
  2062. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2063. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2064. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2065. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2066. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2067. }
  2068. #ifdef IPA_WDI3_VLAN_SUPPORT
  2069. /**
  2070. * dp_ipa_wdi_rx_alt_pipe_smmu_params() - Setup 2nd rx pipe smmu params
  2071. * @soc: data path soc handle
  2072. * @ipa_res: ipa resource pointer
  2073. * @rx_smmu: smmu pipe info handle
  2074. * @over_gsi: flag for IPA offload over gsi
  2075. * @hdl: ipa registered handle
  2076. *
  2077. * Return: none
  2078. */
  2079. static void
  2080. dp_ipa_wdi_rx_alt_pipe_smmu_params(struct dp_soc *soc,
  2081. struct dp_ipa_resources *ipa_res,
  2082. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2083. bool over_gsi,
  2084. qdf_ipa_wdi_hdl_t hdl)
  2085. {
  2086. if (!wlan_ipa_is_vlan_enabled())
  2087. return;
  2088. if (over_gsi) {
  2089. if (hdl == DP_IPA_HDL_FIRST)
  2090. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2091. IPA_CLIENT_WLAN2_PROD1;
  2092. else if (hdl == DP_IPA_HDL_SECOND)
  2093. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2094. IPA_CLIENT_WLAN3_PROD1;
  2095. } else {
  2096. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2097. IPA_CLIENT_WLAN1_PROD;
  2098. }
  2099. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2100. &ipa_res->rx_alt_rdy_ring.sgtable,
  2101. sizeof(sgtable_t));
  2102. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2103. qdf_mem_get_dma_size(soc->osdev,
  2104. &ipa_res->rx_alt_rdy_ring.mem_info);
  2105. /* REO Tail Pointer Address */
  2106. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2107. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2108. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  2109. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2110. &ipa_res->rx_alt_refill_ring.sgtable,
  2111. sizeof(sgtable_t));
  2112. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2113. qdf_mem_get_dma_size(soc->osdev,
  2114. &ipa_res->rx_alt_refill_ring.mem_info);
  2115. /* FW Head Pointer Address */
  2116. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2117. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2118. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2119. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2120. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2121. }
  2122. /**
  2123. * dp_ipa_wdi_rx_alt_pipe_params() - Setup 2nd rx pipe params
  2124. * @soc: data path soc handle
  2125. * @ipa_res: ipa resource pointer
  2126. * @rx: pipe info handle
  2127. * @over_gsi: flag for IPA offload over gsi
  2128. * @hdl: ipa registered handle
  2129. *
  2130. * Return: none
  2131. */
  2132. static void dp_ipa_wdi_rx_alt_pipe_params(struct dp_soc *soc,
  2133. struct dp_ipa_resources *ipa_res,
  2134. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2135. bool over_gsi,
  2136. qdf_ipa_wdi_hdl_t hdl)
  2137. {
  2138. if (!wlan_ipa_is_vlan_enabled())
  2139. return;
  2140. if (over_gsi) {
  2141. if (hdl == DP_IPA_HDL_FIRST)
  2142. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2143. IPA_CLIENT_WLAN2_PROD1;
  2144. else if (hdl == DP_IPA_HDL_SECOND)
  2145. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2146. IPA_CLIENT_WLAN3_PROD1;
  2147. } else {
  2148. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2149. IPA_CLIENT_WLAN1_PROD;
  2150. }
  2151. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2152. qdf_mem_get_dma_addr(soc->osdev,
  2153. &ipa_res->rx_alt_rdy_ring.mem_info);
  2154. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2155. qdf_mem_get_dma_size(soc->osdev,
  2156. &ipa_res->rx_alt_rdy_ring.mem_info);
  2157. /* REO Tail Pointer Address */
  2158. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2159. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2160. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2161. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2162. qdf_mem_get_dma_addr(soc->osdev,
  2163. &ipa_res->rx_alt_refill_ring.mem_info);
  2164. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2165. qdf_mem_get_dma_size(soc->osdev,
  2166. &ipa_res->rx_alt_refill_ring.mem_info);
  2167. /* FW Head Pointer Address */
  2168. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2169. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2170. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2171. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2172. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2173. }
  2174. /**
  2175. * dp_ipa_setup_rx_alt_pipe() - Setup 2nd rx pipe for IPA offload
  2176. * @soc: data path soc handle
  2177. * @res: ipa resource pointer
  2178. * @in: pipe in handle
  2179. * @over_gsi: flag for IPA offload over gsi
  2180. * @hdl: ipa registered handle
  2181. *
  2182. * Return: none
  2183. */
  2184. static void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2185. struct dp_ipa_resources *res,
  2186. qdf_ipa_wdi_conn_in_params_t *in,
  2187. bool over_gsi,
  2188. qdf_ipa_wdi_hdl_t hdl)
  2189. {
  2190. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2191. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2192. qdf_ipa_ep_cfg_t *rx_cfg;
  2193. if (!wlan_ipa_is_vlan_enabled())
  2194. return;
  2195. QDF_IPA_WDI_CONN_IN_PARAMS_IS_RX1_USED(in) = true;
  2196. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  2197. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT_SMMU(in);
  2198. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2199. dp_ipa_wdi_rx_alt_pipe_smmu_params(soc, res, rx_smmu,
  2200. over_gsi, hdl);
  2201. } else {
  2202. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT(in);
  2203. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx);
  2204. dp_ipa_wdi_rx_alt_pipe_params(soc, res, rx, over_gsi, hdl);
  2205. }
  2206. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2207. /* Update with wds len(96) + 4 if wds support is enabled */
  2208. if (ucfg_ipa_is_wds_enabled())
  2209. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST_VLAN;
  2210. else
  2211. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2212. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2213. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2214. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2215. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2216. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2217. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2218. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2219. }
  2220. /**
  2221. * dp_ipa_set_rx_alt_pipe_db() - Setup 2nd rx pipe doorbell
  2222. * @res: ipa resource pointer
  2223. * @out: pipe out handle
  2224. *
  2225. * Return: none
  2226. */
  2227. static void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2228. qdf_ipa_wdi_conn_out_params_t *out)
  2229. {
  2230. if (!wlan_ipa_is_vlan_enabled())
  2231. return;
  2232. res->rx_alt_ready_doorbell_paddr =
  2233. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_ALT_UC_DB_PA(out);
  2234. dp_debug("Setting DB 0x%x for RX alt pipe",
  2235. res->rx_alt_ready_doorbell_paddr);
  2236. }
  2237. #else
  2238. static inline
  2239. void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2240. struct dp_ipa_resources *res,
  2241. qdf_ipa_wdi_conn_in_params_t *in,
  2242. bool over_gsi,
  2243. qdf_ipa_wdi_hdl_t hdl)
  2244. { }
  2245. static inline
  2246. void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2247. qdf_ipa_wdi_conn_out_params_t *out)
  2248. { }
  2249. #endif
  2250. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2251. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2252. void *ipa_wdi_meter_notifier_cb,
  2253. uint32_t ipa_desc_size, void *ipa_priv,
  2254. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2255. uint32_t *rx_pipe_handle, bool is_smmu_enabled,
  2256. qdf_ipa_sys_connect_params_t *sys_in, bool over_gsi,
  2257. qdf_ipa_wdi_hdl_t hdl, qdf_ipa_wdi_hdl_t id,
  2258. void *ipa_ast_notify_cb)
  2259. {
  2260. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2261. struct dp_pdev *pdev =
  2262. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2263. struct dp_ipa_resources *ipa_res;
  2264. qdf_ipa_ep_cfg_t *tx_cfg;
  2265. qdf_ipa_ep_cfg_t *rx_cfg;
  2266. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  2267. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2268. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu;
  2269. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2270. qdf_ipa_wdi_conn_in_params_t *pipe_in = NULL;
  2271. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2272. int ret;
  2273. if (!pdev) {
  2274. dp_err("Invalid instance");
  2275. return QDF_STATUS_E_FAILURE;
  2276. }
  2277. ipa_res = &pdev->ipa_resource;
  2278. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2279. return QDF_STATUS_SUCCESS;
  2280. pipe_in = qdf_mem_malloc(sizeof(*pipe_in));
  2281. if (!pipe_in)
  2282. return QDF_STATUS_E_NOMEM;
  2283. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2284. if (is_smmu_enabled)
  2285. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = true;
  2286. else
  2287. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = false;
  2288. dp_setup_mcc_sys_pipes(sys_in, pipe_in);
  2289. /* TX PIPE */
  2290. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2291. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_SMMU(pipe_in);
  2292. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  2293. } else {
  2294. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(pipe_in);
  2295. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(tx);
  2296. }
  2297. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  2298. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2299. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  2300. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  2301. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  2302. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  2303. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  2304. /*
  2305. * Transfer Ring: WBM Ring
  2306. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2307. * Event Ring: TCL ring
  2308. * Event Ring Doorbell PA: TCL Head Pointer Address
  2309. */
  2310. if (is_smmu_enabled)
  2311. dp_ipa_wdi_tx_smmu_params(soc, ipa_res, tx_smmu, over_gsi, id);
  2312. else
  2313. dp_ipa_wdi_tx_params(soc, ipa_res, tx, over_gsi);
  2314. dp_ipa_setup_tx_alt_pipe(soc, ipa_res, pipe_in);
  2315. /* RX PIPE */
  2316. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2317. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_SMMU(pipe_in);
  2318. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2319. } else {
  2320. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(pipe_in);
  2321. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(rx);
  2322. }
  2323. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2324. if (ucfg_ipa_is_wds_enabled())
  2325. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST;
  2326. else
  2327. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2328. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2329. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2330. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2331. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2332. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2333. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2334. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2335. /*
  2336. * Transfer Ring: REO Ring
  2337. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2338. * Event Ring: FW ring
  2339. * Event Ring Doorbell PA: FW Head Pointer Address
  2340. */
  2341. if (is_smmu_enabled)
  2342. dp_ipa_wdi_rx_smmu_params(soc, ipa_res, rx_smmu, over_gsi, id);
  2343. else
  2344. dp_ipa_wdi_rx_params(soc, ipa_res, rx, over_gsi);
  2345. /* setup 2nd rx pipe */
  2346. dp_ipa_setup_rx_alt_pipe(soc, ipa_res, pipe_in, over_gsi, id);
  2347. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(pipe_in) = ipa_w2i_cb;
  2348. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(pipe_in) = ipa_priv;
  2349. QDF_IPA_WDI_CONN_IN_PARAMS_HANDLE(pipe_in) = hdl;
  2350. dp_ipa_ast_notify_cb(pipe_in, ipa_ast_notify_cb);
  2351. /* Connect WDI IPA PIPEs */
  2352. ret = qdf_ipa_wdi_conn_pipes(pipe_in, &pipe_out);
  2353. if (ret) {
  2354. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2355. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2356. __func__, ret);
  2357. qdf_mem_free(pipe_in);
  2358. return QDF_STATUS_E_FAILURE;
  2359. }
  2360. /* IPA uC Doorbell registers */
  2361. dp_info("Tx DB PA=0x%x, Rx DB PA=0x%x",
  2362. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2363. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2364. dp_ipa_set_pipe_db(ipa_res, &pipe_out);
  2365. dp_ipa_set_rx_alt_pipe_db(ipa_res, &pipe_out);
  2366. ipa_res->is_db_ddr_mapped =
  2367. QDF_IPA_WDI_CONN_OUT_PARAMS_IS_DB_DDR_MAPPED(&pipe_out);
  2368. soc->ipa_first_tx_db_access = true;
  2369. qdf_mem_free(pipe_in);
  2370. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2371. soc->ipa_rx_buf_map_lock_initialized = true;
  2372. return QDF_STATUS_SUCCESS;
  2373. }
  2374. #ifdef IPA_WDI3_VLAN_SUPPORT
  2375. /**
  2376. * dp_ipa_set_rx1_used() - Set rx1 used flag for 2nd rx offload ring
  2377. * @in: pipe in handle
  2378. *
  2379. * Return: none
  2380. */
  2381. static inline
  2382. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2383. {
  2384. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_RX1_USED(in) = true;
  2385. }
  2386. /**
  2387. * dp_ipa_set_v4_vlan_hdr() - Set v4 vlan hdr
  2388. * @in: pipe in handle
  2389. * @hdr: pointer to hdr
  2390. *
  2391. * Return: none
  2392. */
  2393. static inline
  2394. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2395. qdf_ipa_wdi_hdr_info_t *hdr)
  2396. {
  2397. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v4_VLAN]),
  2398. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2399. }
  2400. /**
  2401. * dp_ipa_set_v6_vlan_hdr() - Set v6 vlan hdr
  2402. * @in: pipe in handle
  2403. * @hdr: pointer to hdr
  2404. *
  2405. * Return: none
  2406. */
  2407. static inline
  2408. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2409. qdf_ipa_wdi_hdr_info_t *hdr)
  2410. {
  2411. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v6_VLAN]),
  2412. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2413. }
  2414. #else
  2415. static inline
  2416. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2417. { }
  2418. static inline
  2419. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2420. qdf_ipa_wdi_hdr_info_t *hdr)
  2421. { }
  2422. static inline
  2423. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2424. qdf_ipa_wdi_hdr_info_t *hdr)
  2425. { }
  2426. #endif
  2427. #ifdef IPA_WDS_EASYMESH_FEATURE
  2428. /**
  2429. * dp_ipa_set_wdi_hdr_type() - Set wdi hdr type for IPA
  2430. * @hdr_info: Header info
  2431. *
  2432. * Return: None
  2433. */
  2434. static inline void
  2435. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2436. {
  2437. if (ucfg_ipa_is_wds_enabled())
  2438. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2439. IPA_HDR_L2_ETHERNET_II_AST;
  2440. else
  2441. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2442. IPA_HDR_L2_ETHERNET_II;
  2443. }
  2444. #else
  2445. static inline void
  2446. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2447. {
  2448. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2449. }
  2450. #endif
  2451. #ifdef IPA_WDI3_VLAN_SUPPORT
  2452. /**
  2453. * dp_ipa_set_wdi_vlan_hdr_type() - Set wdi vlan hdr type for IPA
  2454. * @hdr_info: Header info
  2455. *
  2456. * Return: None
  2457. */
  2458. static inline void
  2459. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2460. {
  2461. if (ucfg_ipa_is_wds_enabled())
  2462. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2463. IPA_HDR_L2_802_1Q_AST;
  2464. else
  2465. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2466. IPA_HDR_L2_802_1Q;
  2467. }
  2468. #else
  2469. static inline void
  2470. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2471. { }
  2472. #endif
  2473. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2474. qdf_ipa_client_type_t prod_client,
  2475. qdf_ipa_client_type_t cons_client,
  2476. uint8_t session_id, bool is_ipv6_enabled,
  2477. qdf_ipa_wdi_hdl_t hdl)
  2478. {
  2479. qdf_ipa_wdi_reg_intf_in_params_t in;
  2480. qdf_ipa_wdi_hdr_info_t hdr_info;
  2481. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2482. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2483. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr;
  2484. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr_v6;
  2485. int ret = -EINVAL;
  2486. qdf_mem_zero(&in, sizeof(qdf_ipa_wdi_reg_intf_in_params_t));
  2487. /* Need to reset the values to 0 as all the fields are not
  2488. * updated in the Header, Unused fields will be set to 0.
  2489. */
  2490. qdf_mem_zero(&uc_tx_vlan_hdr, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2491. qdf_mem_zero(&uc_tx_vlan_hdr_v6, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2492. dp_debug("Add Partial hdr: %s, "QDF_MAC_ADDR_FMT, ifname,
  2493. QDF_MAC_ADDR_REF(mac_addr));
  2494. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2495. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2496. /* IPV4 header */
  2497. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2498. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2499. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2500. dp_ipa_set_wdi_hdr_type(&hdr_info);
  2501. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2502. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2503. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2504. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2505. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2506. QDF_IPA_WDI_REG_INTF_IN_PARAMS_ALT_DST_PIPE(&in) = cons_client;
  2507. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2508. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = WLAN_IPA_META_DATA_MASK;
  2509. QDF_IPA_WDI_REG_INTF_IN_PARAMS_HANDLE(&in) = hdl;
  2510. dp_ipa_setup_iface_session_id(&in, session_id);
  2511. dp_debug("registering for session_id: %u", session_id);
  2512. /* IPV6 header */
  2513. if (is_ipv6_enabled) {
  2514. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2515. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2516. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2517. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2518. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2519. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2520. }
  2521. if (wlan_ipa_is_vlan_enabled()) {
  2522. /* Add vlan specific headers if vlan supporti is enabled */
  2523. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2524. dp_ipa_set_rx1_used(&in);
  2525. qdf_ether_addr_copy(uc_tx_vlan_hdr.eth.h_source, mac_addr);
  2526. /* IPV4 Vlan header */
  2527. uc_tx_vlan_hdr.eth.h_vlan_proto = qdf_htons(ETH_P_8021Q);
  2528. uc_tx_vlan_hdr.eth.h_vlan_encapsulated_proto = qdf_htons(ETH_P_IP);
  2529. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2530. (uint8_t *)&uc_tx_vlan_hdr;
  2531. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) =
  2532. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2533. dp_ipa_set_wdi_vlan_hdr_type(&hdr_info);
  2534. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2535. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2536. dp_ipa_set_v4_vlan_hdr(&in, &hdr_info);
  2537. /* IPV6 Vlan header */
  2538. if (is_ipv6_enabled) {
  2539. qdf_mem_copy(&uc_tx_vlan_hdr_v6, &uc_tx_vlan_hdr,
  2540. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN);
  2541. uc_tx_vlan_hdr_v6.eth.h_vlan_proto =
  2542. qdf_htons(ETH_P_8021Q);
  2543. uc_tx_vlan_hdr_v6.eth.h_vlan_encapsulated_proto =
  2544. qdf_htons(ETH_P_IPV6);
  2545. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2546. (uint8_t *)&uc_tx_vlan_hdr_v6;
  2547. dp_ipa_set_v6_vlan_hdr(&in, &hdr_info);
  2548. }
  2549. }
  2550. ret = qdf_ipa_wdi_reg_intf(&in);
  2551. if (ret) {
  2552. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2553. "%s: ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2554. __func__, ret);
  2555. return QDF_STATUS_E_FAILURE;
  2556. }
  2557. return QDF_STATUS_SUCCESS;
  2558. }
  2559. #else /* !CONFIG_IPA_WDI_UNIFIED_API */
  2560. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2561. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2562. void *ipa_wdi_meter_notifier_cb,
  2563. uint32_t ipa_desc_size, void *ipa_priv,
  2564. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2565. uint32_t *rx_pipe_handle)
  2566. {
  2567. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2568. struct dp_pdev *pdev =
  2569. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2570. struct dp_ipa_resources *ipa_res;
  2571. qdf_ipa_wdi_pipe_setup_info_t *tx;
  2572. qdf_ipa_wdi_pipe_setup_info_t *rx;
  2573. qdf_ipa_wdi_conn_in_params_t pipe_in;
  2574. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2575. struct tcl_data_cmd *tcl_desc_ptr;
  2576. uint8_t *desc_addr;
  2577. uint32_t desc_size;
  2578. int ret;
  2579. if (!pdev) {
  2580. dp_err("Invalid instance");
  2581. return QDF_STATUS_E_FAILURE;
  2582. }
  2583. ipa_res = &pdev->ipa_resource;
  2584. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2585. return QDF_STATUS_SUCCESS;
  2586. qdf_mem_zero(&tx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2587. qdf_mem_zero(&rx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2588. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  2589. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2590. /* TX PIPE */
  2591. /*
  2592. * Transfer Ring: WBM Ring
  2593. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2594. * Event Ring: TCL ring
  2595. * Event Ring Doorbell PA: TCL Head Pointer Address
  2596. */
  2597. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  2598. QDF_IPA_WDI_SETUP_INFO_NAT_EN(tx) = IPA_BYPASS_NAT;
  2599. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(tx) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2600. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(tx) = 0;
  2601. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(tx) = 0;
  2602. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(tx) = 0;
  2603. QDF_IPA_WDI_SETUP_INFO_MODE(tx) = IPA_BASIC;
  2604. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(tx) = true;
  2605. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2606. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2607. ipa_res->tx_comp_ring_base_paddr;
  2608. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2609. ipa_res->tx_comp_ring_size;
  2610. /* WBM Tail Pointer Address */
  2611. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2612. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2613. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2614. ipa_res->tx_ring_base_paddr;
  2615. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) = ipa_res->tx_ring_size;
  2616. /* TCL Head Pointer Address */
  2617. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2618. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2619. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2620. ipa_res->tx_num_alloc_buffer;
  2621. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2622. /* Preprogram TCL descriptor */
  2623. desc_addr =
  2624. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  2625. desc_size = sizeof(struct tcl_data_cmd);
  2626. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  2627. tcl_desc_ptr = (struct tcl_data_cmd *)
  2628. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  2629. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  2630. HAL_RX_BUF_RBM_SW2_BM;
  2631. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  2632. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  2633. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  2634. /* RX PIPE */
  2635. /*
  2636. * Transfer Ring: REO Ring
  2637. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2638. * Event Ring: FW ring
  2639. * Event Ring Doorbell PA: FW Head Pointer Address
  2640. */
  2641. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  2642. QDF_IPA_WDI_SETUP_INFO_NAT_EN(rx) = IPA_BYPASS_NAT;
  2643. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(rx) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2644. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(rx) = 0;
  2645. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(rx) = 0;
  2646. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(rx) = 0;
  2647. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_METADATA_VALID(rx) = 0;
  2648. QDF_IPA_WDI_SETUP_INFO_HDR_METADATA_REG_VALID(rx) = 1;
  2649. QDF_IPA_WDI_SETUP_INFO_MODE(rx) = IPA_BASIC;
  2650. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(rx) = true;
  2651. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) = IPA_CLIENT_WLAN1_PROD;
  2652. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2653. ipa_res->rx_rdy_ring_base_paddr;
  2654. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2655. ipa_res->rx_rdy_ring_size;
  2656. /* REO Tail Pointer Address */
  2657. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2658. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2659. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2660. ipa_res->rx_refill_ring_base_paddr;
  2661. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2662. ipa_res->rx_refill_ring_size;
  2663. /* FW Head Pointer Address */
  2664. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2665. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2666. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) = soc->rx_pkt_tlv_size +
  2667. L3_HEADER_PADDING;
  2668. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  2669. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  2670. /* Connect WDI IPA PIPE */
  2671. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  2672. if (ret) {
  2673. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2674. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2675. __func__, ret);
  2676. return QDF_STATUS_E_FAILURE;
  2677. }
  2678. /* IPA uC Doorbell registers */
  2679. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2680. "%s: Tx DB PA=0x%x, Rx DB PA=0x%x",
  2681. __func__,
  2682. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2683. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2684. ipa_res->tx_comp_doorbell_paddr =
  2685. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  2686. ipa_res->tx_comp_doorbell_vaddr =
  2687. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_VA(&pipe_out);
  2688. ipa_res->rx_ready_doorbell_paddr =
  2689. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  2690. soc->ipa_first_tx_db_access = true;
  2691. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2692. soc->ipa_rx_buf_map_lock_initialized = true;
  2693. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2694. "%s: Tx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2695. __func__,
  2696. "transfer_ring_base_pa",
  2697. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx),
  2698. "transfer_ring_size",
  2699. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx),
  2700. "transfer_ring_doorbell_pa",
  2701. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx),
  2702. "event_ring_base_pa",
  2703. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx),
  2704. "event_ring_size",
  2705. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx),
  2706. "event_ring_doorbell_pa",
  2707. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx),
  2708. "num_pkt_buffers",
  2709. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx),
  2710. "tx_comp_doorbell_paddr",
  2711. (void *)ipa_res->tx_comp_doorbell_paddr);
  2712. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2713. "%s: Rx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2714. __func__,
  2715. "transfer_ring_base_pa",
  2716. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx),
  2717. "transfer_ring_size",
  2718. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx),
  2719. "transfer_ring_doorbell_pa",
  2720. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx),
  2721. "event_ring_base_pa",
  2722. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx),
  2723. "event_ring_size",
  2724. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx),
  2725. "event_ring_doorbell_pa",
  2726. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx),
  2727. "num_pkt_buffers",
  2728. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(rx),
  2729. "tx_comp_doorbell_paddr",
  2730. (void *)ipa_res->rx_ready_doorbell_paddr);
  2731. return QDF_STATUS_SUCCESS;
  2732. }
  2733. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2734. qdf_ipa_client_type_t prod_client,
  2735. qdf_ipa_client_type_t cons_client,
  2736. uint8_t session_id, bool is_ipv6_enabled,
  2737. qdf_ipa_wdi_hdl_t hdl)
  2738. {
  2739. qdf_ipa_wdi_reg_intf_in_params_t in;
  2740. qdf_ipa_wdi_hdr_info_t hdr_info;
  2741. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2742. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2743. int ret = -EINVAL;
  2744. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2745. "%s: Add Partial hdr: %s, "QDF_MAC_ADDR_FMT,
  2746. __func__, ifname, QDF_MAC_ADDR_REF(mac_addr));
  2747. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2748. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2749. /* IPV4 header */
  2750. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2751. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2752. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2753. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2754. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2755. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2756. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2757. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2758. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2759. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2760. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  2761. htonl(session_id << 16);
  2762. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  2763. /* IPV6 header */
  2764. if (is_ipv6_enabled) {
  2765. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2766. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2767. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2768. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2769. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2770. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2771. }
  2772. ret = qdf_ipa_wdi_reg_intf(&in);
  2773. if (ret) {
  2774. dp_err("ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2775. ret);
  2776. return QDF_STATUS_E_FAILURE;
  2777. }
  2778. return QDF_STATUS_SUCCESS;
  2779. }
  2780. #endif /* CONFIG_IPA_WDI_UNIFIED_API */
  2781. QDF_STATUS dp_ipa_cleanup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2782. uint32_t tx_pipe_handle, uint32_t rx_pipe_handle,
  2783. qdf_ipa_wdi_hdl_t hdl)
  2784. {
  2785. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2786. QDF_STATUS status = QDF_STATUS_SUCCESS;
  2787. struct dp_pdev *pdev;
  2788. int ret;
  2789. ret = qdf_ipa_wdi_disconn_pipes(hdl);
  2790. if (ret) {
  2791. dp_err("ipa_wdi_disconn_pipes: IPA pipe cleanup failed: ret=%d",
  2792. ret);
  2793. status = QDF_STATUS_E_FAILURE;
  2794. }
  2795. if (soc->ipa_rx_buf_map_lock_initialized) {
  2796. qdf_spinlock_destroy(&soc->ipa_rx_buf_map_lock);
  2797. soc->ipa_rx_buf_map_lock_initialized = false;
  2798. }
  2799. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2800. if (qdf_unlikely(!pdev)) {
  2801. dp_err_rl("Invalid pdev for pdev_id %d", pdev_id);
  2802. status = QDF_STATUS_E_FAILURE;
  2803. goto exit;
  2804. }
  2805. dp_ipa_unmap_ring_doorbell_paddr(pdev);
  2806. dp_ipa_unmap_rx_alt_ring_doorbell_paddr(pdev);
  2807. exit:
  2808. return status;
  2809. }
  2810. QDF_STATUS dp_ipa_cleanup_iface(char *ifname, bool is_ipv6_enabled,
  2811. qdf_ipa_wdi_hdl_t hdl)
  2812. {
  2813. int ret;
  2814. ret = qdf_ipa_wdi_dereg_intf(ifname, hdl);
  2815. if (ret) {
  2816. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2817. "%s: ipa_wdi_dereg_intf: IPA pipe deregistration failed: ret=%d",
  2818. __func__, ret);
  2819. return QDF_STATUS_E_FAILURE;
  2820. }
  2821. return QDF_STATUS_SUCCESS;
  2822. }
  2823. #ifdef IPA_SET_RESET_TX_DB_PA
  2824. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res) \
  2825. dp_ipa_set_tx_doorbell_paddr((soc), (ipa_res))
  2826. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res) \
  2827. dp_ipa_reset_tx_doorbell_pa((soc), (ipa_res))
  2828. #else
  2829. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res)
  2830. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res)
  2831. #endif
  2832. QDF_STATUS dp_ipa_enable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2833. qdf_ipa_wdi_hdl_t hdl)
  2834. {
  2835. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2836. struct dp_pdev *pdev =
  2837. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2838. struct dp_ipa_resources *ipa_res;
  2839. QDF_STATUS result;
  2840. if (!pdev) {
  2841. dp_err("Invalid instance");
  2842. return QDF_STATUS_E_FAILURE;
  2843. }
  2844. ipa_res = &pdev->ipa_resource;
  2845. qdf_atomic_set(&soc->ipa_pipes_enabled, 1);
  2846. DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res);
  2847. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, true,
  2848. __func__, __LINE__);
  2849. result = qdf_ipa_wdi_enable_pipes(hdl);
  2850. if (result) {
  2851. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2852. "%s: Enable WDI PIPE fail, code %d",
  2853. __func__, result);
  2854. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  2855. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  2856. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false,
  2857. __func__, __LINE__);
  2858. return QDF_STATUS_E_FAILURE;
  2859. }
  2860. if (soc->ipa_first_tx_db_access) {
  2861. dp_ipa_tx_comp_ring_init_hp(soc, ipa_res);
  2862. soc->ipa_first_tx_db_access = false;
  2863. }
  2864. return QDF_STATUS_SUCCESS;
  2865. }
  2866. QDF_STATUS dp_ipa_disable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2867. qdf_ipa_wdi_hdl_t hdl)
  2868. {
  2869. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2870. struct dp_pdev *pdev =
  2871. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2872. QDF_STATUS result;
  2873. struct dp_ipa_resources *ipa_res;
  2874. if (!pdev) {
  2875. dp_err("Invalid instance");
  2876. return QDF_STATUS_E_FAILURE;
  2877. }
  2878. ipa_res = &pdev->ipa_resource;
  2879. qdf_sleep(TX_COMP_DRAIN_WAIT_TIMEOUT_MS);
  2880. /*
  2881. * Reset the tx completion doorbell address before invoking IPA disable
  2882. * pipes API to ensure that there is no access to IPA tx doorbell
  2883. * address post disable pipes.
  2884. */
  2885. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  2886. result = qdf_ipa_wdi_disable_pipes(hdl);
  2887. if (result) {
  2888. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2889. "%s: Disable WDI PIPE fail, code %d",
  2890. __func__, result);
  2891. qdf_assert_always(0);
  2892. return QDF_STATUS_E_FAILURE;
  2893. }
  2894. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  2895. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false,
  2896. __func__, __LINE__);
  2897. return result ? QDF_STATUS_E_FAILURE : QDF_STATUS_SUCCESS;
  2898. }
  2899. QDF_STATUS dp_ipa_set_perf_level(int client, uint32_t max_supported_bw_mbps,
  2900. qdf_ipa_wdi_hdl_t hdl)
  2901. {
  2902. qdf_ipa_wdi_perf_profile_t profile;
  2903. QDF_STATUS result;
  2904. profile.client = client;
  2905. profile.max_supported_bw_mbps = max_supported_bw_mbps;
  2906. result = qdf_ipa_wdi_set_perf_profile(hdl, &profile);
  2907. if (result) {
  2908. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2909. "%s: ipa_wdi_set_perf_profile fail, code %d",
  2910. __func__, result);
  2911. return QDF_STATUS_E_FAILURE;
  2912. }
  2913. return QDF_STATUS_SUCCESS;
  2914. }
  2915. /**
  2916. * dp_ipa_intrabss_send() - send IPA RX intra-bss frames
  2917. * @pdev: pdev
  2918. * @vdev: vdev
  2919. * @nbuf: skb
  2920. *
  2921. * Return: nbuf if TX fails and NULL if TX succeeds
  2922. */
  2923. static qdf_nbuf_t dp_ipa_intrabss_send(struct dp_pdev *pdev,
  2924. struct dp_vdev *vdev,
  2925. qdf_nbuf_t nbuf)
  2926. {
  2927. struct dp_peer *vdev_peer;
  2928. uint16_t len;
  2929. vdev_peer = dp_vdev_bss_peer_ref_n_get(pdev->soc, vdev, DP_MOD_ID_IPA);
  2930. if (qdf_unlikely(!vdev_peer))
  2931. return nbuf;
  2932. if (qdf_unlikely(!vdev_peer->txrx_peer)) {
  2933. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  2934. return nbuf;
  2935. }
  2936. qdf_mem_zero(nbuf->cb, sizeof(nbuf->cb));
  2937. len = qdf_nbuf_len(nbuf);
  2938. if (dp_tx_send((struct cdp_soc_t *)pdev->soc, vdev->vdev_id, nbuf)) {
  2939. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  2940. rx.intra_bss.fail, 1, len,
  2941. 0);
  2942. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  2943. return nbuf;
  2944. }
  2945. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  2946. rx.intra_bss.pkts, 1, len, 0);
  2947. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  2948. return NULL;
  2949. }
  2950. #ifdef IPA_OPT_WIFI_DP
  2951. /**
  2952. * dp_ipa_rx_super_rule_setup()- pass cce super rule params to fw from ipa
  2953. *
  2954. * @soc_hdl: cdp soc
  2955. * @flt_params: filter tuple
  2956. *
  2957. * Return: QDF_STATUS
  2958. */
  2959. QDF_STATUS dp_ipa_rx_super_rule_setup(struct cdp_soc_t *soc_hdl,
  2960. void *flt_params)
  2961. {
  2962. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2963. return htt_h2t_rx_cce_super_rule_setup(soc->htt_handle, flt_params);
  2964. }
  2965. /**
  2966. * dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb()- send cce super rule filter
  2967. * add/remove result to ipa
  2968. *
  2969. * @flt0_rslt : result for filter0 add/remove
  2970. * @flt1_rslt : result for filter1 add/remove
  2971. *
  2972. * Return: void
  2973. */
  2974. void dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(int flt0_rslt, int flt1_rslt)
  2975. {
  2976. wlan_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(flt0_rslt, flt1_rslt);
  2977. }
  2978. int dp_ipa_pcie_link_up(struct cdp_soc_t *soc_hdl)
  2979. {
  2980. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2981. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  2982. int response = 0;
  2983. response = hif_prevent_l1((hal_soc->hif_handle));
  2984. return response;
  2985. }
  2986. void dp_ipa_pcie_link_down(struct cdp_soc_t *soc_hdl)
  2987. {
  2988. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2989. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  2990. hif_allow_l1(hal_soc->hif_handle);
  2991. }
  2992. /**
  2993. * dp_ipa_wdi_opt_dpath_notify_flt_rlsd()- send cce super rule release
  2994. * notification to ipa
  2995. *
  2996. * @flt0_rslt : result for filter0 release
  2997. * @flt1_rslt : result for filter1 release
  2998. *
  2999. *Return: void
  3000. */
  3001. void dp_ipa_wdi_opt_dpath_notify_flt_rlsd(int flt0_rslt, int flt1_rslt)
  3002. {
  3003. wlan_ipa_wdi_opt_dpath_notify_flt_rlsd(flt0_rslt, flt1_rslt);
  3004. }
  3005. /**
  3006. * dp_ipa_wdi_opt_dpath_notify_flt_rsvd()- send cce super rule reserve
  3007. * notification to ipa
  3008. *
  3009. *@is_success : result of filter reservatiom
  3010. *
  3011. *Return: void
  3012. */
  3013. void dp_ipa_wdi_opt_dpath_notify_flt_rsvd(bool is_success)
  3014. {
  3015. wlan_ipa_wdi_opt_dpath_notify_flt_rsvd(is_success);
  3016. }
  3017. #endif
  3018. #ifdef IPA_WDS_EASYMESH_FEATURE
  3019. /**
  3020. * dp_ipa_peer_check() - Check for peer for given mac
  3021. * @soc: dp soc object
  3022. * @peer_mac_addr: peer mac address
  3023. * @vdev_id: vdev id
  3024. *
  3025. * Return: true if peer is found, else false
  3026. */
  3027. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3028. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3029. {
  3030. struct dp_ast_entry *ast_entry = NULL;
  3031. struct dp_peer *peer = NULL;
  3032. qdf_spin_lock_bh(&soc->ast_lock);
  3033. ast_entry = dp_peer_ast_hash_find_soc(soc, peer_mac_addr);
  3034. if ((!ast_entry) ||
  3035. (ast_entry->delete_in_progress && !ast_entry->callback)) {
  3036. qdf_spin_unlock_bh(&soc->ast_lock);
  3037. return false;
  3038. }
  3039. peer = dp_peer_get_ref_by_id(soc, ast_entry->peer_id,
  3040. DP_MOD_ID_IPA);
  3041. if (!peer) {
  3042. qdf_spin_unlock_bh(&soc->ast_lock);
  3043. return false;
  3044. } else {
  3045. if (peer->vdev->vdev_id == vdev_id) {
  3046. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3047. qdf_spin_unlock_bh(&soc->ast_lock);
  3048. return true;
  3049. }
  3050. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3051. qdf_spin_unlock_bh(&soc->ast_lock);
  3052. return false;
  3053. }
  3054. }
  3055. #else
  3056. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3057. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3058. {
  3059. struct cdp_peer_info peer_info = {0};
  3060. struct dp_peer *peer = NULL;
  3061. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac_addr, false,
  3062. CDP_WILD_PEER_TYPE);
  3063. peer = dp_peer_hash_find_wrapper(soc, &peer_info, DP_MOD_ID_IPA);
  3064. if (peer) {
  3065. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3066. return true;
  3067. } else {
  3068. return false;
  3069. }
  3070. }
  3071. #endif
  3072. bool dp_ipa_rx_intrabss_fwd(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3073. qdf_nbuf_t nbuf, bool *fwd_success)
  3074. {
  3075. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3076. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3077. DP_MOD_ID_IPA);
  3078. struct dp_pdev *pdev;
  3079. qdf_nbuf_t nbuf_copy;
  3080. uint8_t da_is_bcmc;
  3081. struct ethhdr *eh;
  3082. bool status = false;
  3083. *fwd_success = false; /* set default as failure */
  3084. /*
  3085. * WDI 3.0 skb->cb[] info from IPA driver
  3086. * skb->cb[0] = vdev_id
  3087. * skb->cb[1].bit#1 = da_is_bcmc
  3088. */
  3089. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3090. if (qdf_unlikely(!vdev))
  3091. return false;
  3092. pdev = vdev->pdev;
  3093. if (qdf_unlikely(!pdev))
  3094. goto out;
  3095. /* no fwd for station mode and just pass up to stack */
  3096. if (vdev->opmode == wlan_op_mode_sta)
  3097. goto out;
  3098. if (da_is_bcmc) {
  3099. nbuf_copy = qdf_nbuf_copy(nbuf);
  3100. if (!nbuf_copy)
  3101. goto out;
  3102. if (dp_ipa_intrabss_send(pdev, vdev, nbuf_copy))
  3103. qdf_nbuf_free(nbuf_copy);
  3104. else
  3105. *fwd_success = true;
  3106. /* return false to pass original pkt up to stack */
  3107. goto out;
  3108. }
  3109. eh = (struct ethhdr *)qdf_nbuf_data(nbuf);
  3110. if (!qdf_mem_cmp(eh->h_dest, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  3111. goto out;
  3112. if (!dp_ipa_peer_check(soc, eh->h_dest, vdev->vdev_id))
  3113. goto out;
  3114. if (!dp_ipa_peer_check(soc, eh->h_source, vdev->vdev_id))
  3115. goto out;
  3116. /*
  3117. * In intra-bss forwarding scenario, skb is allocated by IPA driver.
  3118. * Need to add skb to internal tracking table to avoid nbuf memory
  3119. * leak check for unallocated skb.
  3120. */
  3121. qdf_net_buf_debug_acquire_skb(nbuf, __FILE__, __LINE__);
  3122. if (dp_ipa_intrabss_send(pdev, vdev, nbuf))
  3123. qdf_nbuf_free(nbuf);
  3124. else
  3125. *fwd_success = true;
  3126. status = true;
  3127. out:
  3128. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3129. return status;
  3130. }
  3131. #ifdef MDM_PLATFORM
  3132. bool dp_ipa_is_mdm_platform(void)
  3133. {
  3134. return true;
  3135. }
  3136. #else
  3137. bool dp_ipa_is_mdm_platform(void)
  3138. {
  3139. return false;
  3140. }
  3141. #endif
  3142. /**
  3143. * dp_ipa_frag_nbuf_linearize() - linearize nbuf for IPA
  3144. * @soc: soc
  3145. * @nbuf: source skb
  3146. *
  3147. * Return: new nbuf if success and otherwise NULL
  3148. */
  3149. static qdf_nbuf_t dp_ipa_frag_nbuf_linearize(struct dp_soc *soc,
  3150. qdf_nbuf_t nbuf)
  3151. {
  3152. uint8_t *src_nbuf_data;
  3153. uint8_t *dst_nbuf_data;
  3154. qdf_nbuf_t dst_nbuf;
  3155. qdf_nbuf_t temp_nbuf = nbuf;
  3156. uint32_t nbuf_len = qdf_nbuf_len(nbuf);
  3157. bool is_nbuf_head = true;
  3158. uint32_t copy_len = 0;
  3159. dst_nbuf = qdf_nbuf_alloc(soc->osdev, RX_DATA_BUFFER_SIZE,
  3160. RX_BUFFER_RESERVATION,
  3161. RX_DATA_BUFFER_ALIGNMENT, FALSE);
  3162. if (!dst_nbuf) {
  3163. dp_err_rl("nbuf allocate fail");
  3164. return NULL;
  3165. }
  3166. if ((nbuf_len + L3_HEADER_PADDING) > RX_DATA_BUFFER_SIZE) {
  3167. qdf_nbuf_free(dst_nbuf);
  3168. dp_err_rl("nbuf is jumbo data");
  3169. return NULL;
  3170. }
  3171. /* prepeare to copy all data into new skb */
  3172. dst_nbuf_data = qdf_nbuf_data(dst_nbuf);
  3173. while (temp_nbuf) {
  3174. src_nbuf_data = qdf_nbuf_data(temp_nbuf);
  3175. /* first head nbuf */
  3176. if (is_nbuf_head) {
  3177. qdf_mem_copy(dst_nbuf_data, src_nbuf_data,
  3178. soc->rx_pkt_tlv_size);
  3179. /* leave extra 2 bytes L3_HEADER_PADDING */
  3180. dst_nbuf_data += (soc->rx_pkt_tlv_size +
  3181. L3_HEADER_PADDING);
  3182. src_nbuf_data += soc->rx_pkt_tlv_size;
  3183. copy_len = qdf_nbuf_headlen(temp_nbuf) -
  3184. soc->rx_pkt_tlv_size;
  3185. temp_nbuf = qdf_nbuf_get_ext_list(temp_nbuf);
  3186. is_nbuf_head = false;
  3187. } else {
  3188. copy_len = qdf_nbuf_len(temp_nbuf);
  3189. temp_nbuf = qdf_nbuf_queue_next(temp_nbuf);
  3190. }
  3191. qdf_mem_copy(dst_nbuf_data, src_nbuf_data, copy_len);
  3192. dst_nbuf_data += copy_len;
  3193. }
  3194. qdf_nbuf_set_len(dst_nbuf, nbuf_len);
  3195. /* copy is done, free original nbuf */
  3196. qdf_nbuf_free(nbuf);
  3197. return dst_nbuf;
  3198. }
  3199. qdf_nbuf_t dp_ipa_handle_rx_reo_reinject(struct dp_soc *soc, qdf_nbuf_t nbuf)
  3200. {
  3201. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  3202. return nbuf;
  3203. /* WLAN IPA is run-time disabled */
  3204. if (!qdf_atomic_read(&soc->ipa_pipes_enabled))
  3205. return nbuf;
  3206. if (!qdf_nbuf_is_frag(nbuf))
  3207. return nbuf;
  3208. /* linearize skb for IPA */
  3209. return dp_ipa_frag_nbuf_linearize(soc, nbuf);
  3210. }
  3211. QDF_STATUS dp_ipa_tx_buf_smmu_mapping(
  3212. struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3213. const char *func, uint32_t line)
  3214. {
  3215. QDF_STATUS ret;
  3216. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3217. struct dp_pdev *pdev =
  3218. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3219. if (!pdev) {
  3220. dp_err("%s invalid instance", __func__);
  3221. return QDF_STATUS_E_FAILURE;
  3222. }
  3223. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3224. dp_debug("SMMU S1 disabled");
  3225. return QDF_STATUS_SUCCESS;
  3226. }
  3227. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, true, func, line);
  3228. if (ret)
  3229. return ret;
  3230. ret = dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, true, func, line);
  3231. if (ret)
  3232. __dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line);
  3233. return ret;
  3234. }
  3235. QDF_STATUS dp_ipa_tx_buf_smmu_unmapping(
  3236. struct cdp_soc_t *soc_hdl, uint8_t pdev_id, const char *func,
  3237. uint32_t line)
  3238. {
  3239. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3240. struct dp_pdev *pdev =
  3241. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3242. if (!pdev) {
  3243. dp_err("%s invalid instance", __func__);
  3244. return QDF_STATUS_E_FAILURE;
  3245. }
  3246. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3247. dp_debug("SMMU S1 disabled");
  3248. return QDF_STATUS_SUCCESS;
  3249. }
  3250. if (__dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line) ||
  3251. dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, false, func, line))
  3252. return QDF_STATUS_E_FAILURE;
  3253. return QDF_STATUS_SUCCESS;
  3254. }
  3255. #ifdef IPA_WDS_EASYMESH_FEATURE
  3256. QDF_STATUS dp_ipa_ast_create(struct cdp_soc_t *soc_hdl,
  3257. qdf_ipa_ast_info_type_t *data)
  3258. {
  3259. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3260. uint8_t *rx_tlv_hdr;
  3261. struct dp_peer *peer;
  3262. struct hal_rx_msdu_metadata msdu_metadata;
  3263. qdf_ipa_ast_info_type_t *ast_info;
  3264. if (!data) {
  3265. dp_err("Data is NULL !!!");
  3266. return QDF_STATUS_E_FAILURE;
  3267. }
  3268. ast_info = data;
  3269. rx_tlv_hdr = qdf_nbuf_data(ast_info->skb);
  3270. peer = dp_peer_get_ref_by_id(soc, ast_info->ta_peer_id,
  3271. DP_MOD_ID_IPA);
  3272. if (!peer) {
  3273. dp_err("Peer is NULL !!!!");
  3274. return QDF_STATUS_E_FAILURE;
  3275. }
  3276. hal_rx_msdu_metadata_get(soc->hal_soc, rx_tlv_hdr, &msdu_metadata);
  3277. dp_rx_ipa_wds_srcport_learn(soc, peer, ast_info->skb, msdu_metadata,
  3278. ast_info->mac_addr_ad4_valid,
  3279. ast_info->first_msdu_in_mpdu_flag);
  3280. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3281. return QDF_STATUS_SUCCESS;
  3282. }
  3283. #endif
  3284. #ifdef QCA_ENHANCED_STATS_SUPPORT
  3285. QDF_STATUS dp_ipa_update_peer_rx_stats(struct cdp_soc_t *soc,
  3286. uint8_t vdev_id, uint8_t *peer_mac,
  3287. qdf_nbuf_t nbuf)
  3288. {
  3289. struct dp_peer *peer = dp_peer_find_hash_find((struct dp_soc *)soc,
  3290. peer_mac, 0, vdev_id,
  3291. DP_MOD_ID_IPA);
  3292. struct dp_txrx_peer *txrx_peer;
  3293. uint8_t da_is_bcmc;
  3294. qdf_ether_header_t *eh;
  3295. if (!peer)
  3296. return QDF_STATUS_E_FAILURE;
  3297. txrx_peer = dp_get_txrx_peer(peer);
  3298. if (!txrx_peer) {
  3299. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3300. return QDF_STATUS_E_FAILURE;
  3301. }
  3302. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3303. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3304. if (da_is_bcmc) {
  3305. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.multicast, 1,
  3306. qdf_nbuf_len(nbuf), 0);
  3307. if (QDF_IS_ADDR_BROADCAST(eh->ether_dhost))
  3308. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.bcast,
  3309. 1, qdf_nbuf_len(nbuf), 0);
  3310. }
  3311. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3312. return QDF_STATUS_SUCCESS;
  3313. }
  3314. void
  3315. dp_peer_aggregate_tid_stats(struct dp_peer *peer)
  3316. {
  3317. uint8_t i = 0;
  3318. struct dp_rx_tid *rx_tid = NULL;
  3319. struct cdp_pkt_info rx_total = {0};
  3320. struct dp_txrx_peer *txrx_peer = NULL;
  3321. if (!peer->rx_tid)
  3322. return;
  3323. txrx_peer = dp_get_txrx_peer(peer);
  3324. if (!txrx_peer)
  3325. return;
  3326. for (i = 0; i < DP_MAX_TIDS; i++) {
  3327. rx_tid = &peer->rx_tid[i];
  3328. rx_total.num += rx_tid->rx_msdu_cnt.num;
  3329. rx_total.bytes += rx_tid->rx_msdu_cnt.bytes;
  3330. }
  3331. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.num,
  3332. rx_total.num, 0);
  3333. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.bytes,
  3334. rx_total.bytes, 0);
  3335. }
  3336. /**
  3337. * dp_ipa_update_vdev_stats(): update vdev stats
  3338. * @soc: soc handle
  3339. * @srcobj: DP_PEER object
  3340. * @arg: point to vdev stats structure
  3341. *
  3342. * Return: void
  3343. */
  3344. static inline
  3345. void dp_ipa_update_vdev_stats(struct dp_soc *soc, struct dp_peer *srcobj,
  3346. void *arg)
  3347. {
  3348. dp_peer_aggregate_tid_stats(srcobj);
  3349. dp_update_vdev_stats(soc, srcobj, arg);
  3350. }
  3351. /**
  3352. * dp_ipa_aggregate_vdev_stats - Aggregate vdev_stats
  3353. * @vdev: Data path vdev
  3354. * @vdev_stats: buffer to hold vdev stats
  3355. *
  3356. * Return: void
  3357. */
  3358. static inline
  3359. void dp_ipa_aggregate_vdev_stats(struct dp_vdev *vdev,
  3360. struct cdp_vdev_stats *vdev_stats)
  3361. {
  3362. struct dp_soc *soc = NULL;
  3363. if (!vdev || !vdev->pdev)
  3364. return;
  3365. soc = vdev->pdev->soc;
  3366. dp_update_vdev_ingress_stats(vdev);
  3367. qdf_mem_copy(vdev_stats, &vdev->stats, sizeof(vdev->stats));
  3368. dp_vdev_iterate_peer(vdev, dp_ipa_update_vdev_stats, vdev_stats,
  3369. DP_MOD_ID_GENERIC_STATS);
  3370. dp_update_vdev_rate_stats(vdev_stats, &vdev->stats);
  3371. vdev_stats->tx.ucast.num = vdev_stats->tx.tx_ucast_total.num;
  3372. vdev_stats->tx.ucast.bytes = vdev_stats->tx.tx_ucast_total.bytes;
  3373. vdev_stats->tx.tx_success.num = vdev_stats->tx.tx_ucast_success.num;
  3374. vdev_stats->tx.tx_success.bytes = vdev_stats->tx.tx_ucast_success.bytes;
  3375. if (vdev_stats->rx.rx_total.num >= vdev_stats->rx.multicast.num)
  3376. vdev_stats->rx.unicast.num = vdev_stats->rx.rx_total.num -
  3377. vdev_stats->rx.multicast.num;
  3378. if (vdev_stats->rx.rx_total.bytes >= vdev_stats->rx.multicast.bytes)
  3379. vdev_stats->rx.unicast.bytes = vdev_stats->rx.rx_total.bytes -
  3380. vdev_stats->rx.multicast.bytes;
  3381. vdev_stats->rx.to_stack.num = vdev_stats->rx.rx_total.num;
  3382. vdev_stats->rx.to_stack.bytes = vdev_stats->rx.rx_total.bytes;
  3383. }
  3384. /**
  3385. * dp_ipa_aggregate_pdev_stats - Aggregate pdev stats
  3386. * @pdev: Data path pdev
  3387. *
  3388. * Return: void
  3389. */
  3390. static inline
  3391. void dp_ipa_aggregate_pdev_stats(struct dp_pdev *pdev)
  3392. {
  3393. struct dp_vdev *vdev = NULL;
  3394. struct dp_soc *soc;
  3395. struct cdp_vdev_stats *vdev_stats =
  3396. qdf_mem_malloc_atomic(sizeof(struct cdp_vdev_stats));
  3397. if (!vdev_stats) {
  3398. dp_err("%pK: DP alloc failure - unable to get alloc vdev stats",
  3399. pdev->soc);
  3400. return;
  3401. }
  3402. soc = pdev->soc;
  3403. qdf_mem_zero(&pdev->stats.tx, sizeof(pdev->stats.tx));
  3404. qdf_mem_zero(&pdev->stats.rx, sizeof(pdev->stats.rx));
  3405. qdf_mem_zero(&pdev->stats.tx_i, sizeof(pdev->stats.tx_i));
  3406. qdf_mem_zero(&pdev->stats.rx_i, sizeof(pdev->stats.rx_i));
  3407. qdf_spin_lock_bh(&pdev->vdev_list_lock);
  3408. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3409. dp_ipa_aggregate_vdev_stats(vdev, vdev_stats);
  3410. dp_update_pdev_stats(pdev, vdev_stats);
  3411. dp_update_pdev_ingress_stats(pdev, vdev);
  3412. }
  3413. qdf_spin_unlock_bh(&pdev->vdev_list_lock);
  3414. qdf_mem_free(vdev_stats);
  3415. }
  3416. /**
  3417. * dp_ipa_get_peer_stats - Get peer stats
  3418. * @peer: Data path peer
  3419. * @peer_stats: buffer to hold peer stats
  3420. *
  3421. * Return: void
  3422. */
  3423. static
  3424. void dp_ipa_get_peer_stats(struct dp_peer *peer,
  3425. struct cdp_peer_stats *peer_stats)
  3426. {
  3427. dp_peer_aggregate_tid_stats(peer);
  3428. dp_get_peer_stats(peer, peer_stats);
  3429. peer_stats->tx.tx_success.num =
  3430. peer_stats->tx.tx_ucast_success.num;
  3431. peer_stats->tx.tx_success.bytes =
  3432. peer_stats->tx.tx_ucast_success.bytes;
  3433. peer_stats->tx.ucast.num =
  3434. peer_stats->tx.tx_ucast_total.num;
  3435. peer_stats->tx.ucast.bytes =
  3436. peer_stats->tx.tx_ucast_total.bytes;
  3437. if (peer_stats->rx.rx_total.num >= peer_stats->rx.multicast.num)
  3438. peer_stats->rx.unicast.num = peer_stats->rx.rx_total.num -
  3439. peer_stats->rx.multicast.num;
  3440. if (peer_stats->rx.rx_total.bytes >= peer_stats->rx.multicast.bytes)
  3441. peer_stats->rx.unicast.bytes = peer_stats->rx.rx_total.bytes -
  3442. peer_stats->rx.multicast.bytes;
  3443. }
  3444. QDF_STATUS
  3445. dp_ipa_txrx_get_pdev_stats(struct cdp_soc_t *soc, uint8_t pdev_id,
  3446. struct cdp_pdev_stats *pdev_stats)
  3447. {
  3448. struct dp_pdev *pdev =
  3449. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)soc,
  3450. pdev_id);
  3451. if (!pdev)
  3452. return QDF_STATUS_E_FAILURE;
  3453. dp_ipa_aggregate_pdev_stats(pdev);
  3454. qdf_mem_copy(pdev_stats, &pdev->stats, sizeof(struct cdp_pdev_stats));
  3455. return QDF_STATUS_SUCCESS;
  3456. }
  3457. int dp_ipa_txrx_get_vdev_stats(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3458. void *buf, bool is_aggregate)
  3459. {
  3460. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3461. struct cdp_vdev_stats *vdev_stats;
  3462. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3463. DP_MOD_ID_IPA);
  3464. if (!vdev)
  3465. return 1;
  3466. vdev_stats = (struct cdp_vdev_stats *)buf;
  3467. dp_ipa_aggregate_vdev_stats(vdev, buf);
  3468. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3469. return 0;
  3470. }
  3471. QDF_STATUS dp_ipa_txrx_get_peer_stats(struct cdp_soc_t *soc, uint8_t vdev_id,
  3472. uint8_t *peer_mac,
  3473. struct cdp_peer_stats *peer_stats)
  3474. {
  3475. struct dp_peer *peer = NULL;
  3476. struct cdp_peer_info peer_info = { 0 };
  3477. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac, false,
  3478. CDP_WILD_PEER_TYPE);
  3479. peer = dp_peer_hash_find_wrapper((struct dp_soc *)soc, &peer_info,
  3480. DP_MOD_ID_IPA);
  3481. qdf_mem_zero(peer_stats, sizeof(struct cdp_peer_stats));
  3482. if (!peer)
  3483. return QDF_STATUS_E_FAILURE;
  3484. dp_ipa_get_peer_stats(peer, peer_stats);
  3485. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3486. return QDF_STATUS_SUCCESS;
  3487. }
  3488. #endif
  3489. /**
  3490. * dp_ipa_get_wdi_version() - Get WDI version
  3491. * @soc_hdl: data path soc handle
  3492. * @wdi_ver: Out parameter for wdi version
  3493. *
  3494. * Get WDI version based on soc arch
  3495. *
  3496. * Return: None
  3497. */
  3498. void dp_ipa_get_wdi_version(struct cdp_soc_t *soc_hdl, uint8_t *wdi_ver)
  3499. {
  3500. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3501. if (soc->arch_ops.ipa_get_wdi_ver)
  3502. soc->arch_ops.ipa_get_wdi_ver(wdi_ver);
  3503. else
  3504. *wdi_ver = IPA_WDI_3;
  3505. }
  3506. #endif