rx_desc.h 16 KB

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  1. /*
  2. * Copyright (c) 2011-2015 The Linux Foundation. All rights reserved.
  3. *
  4. * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
  5. *
  6. *
  7. * Permission to use, copy, modify, and/or distribute this software for
  8. * any purpose with or without fee is hereby granted, provided that the
  9. * above copyright notice and this permission notice appear in all
  10. * copies.
  11. *
  12. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  13. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  14. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  15. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  16. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  17. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  18. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  19. * PERFORMANCE OF THIS SOFTWARE.
  20. */
  21. /*
  22. * This file was originally distributed by Qualcomm Atheros, Inc.
  23. * under proprietary terms before Copyright ownership was assigned
  24. * to the Linux Foundation.
  25. */
  26. #ifndef _RX_DESC_H_
  27. #define _RX_DESC_H_
  28. /*
  29. * REMIND: Copy one of rx_desc related structures here for export,
  30. * hopes they are always the same between Peregrine and Rome in future
  31. */
  32. struct rx_attention {
  33. volatile
  34. uint32_t first_mpdu:1, /* [0] */
  35. last_mpdu:1, /* [1] */
  36. mcast_bcast:1, /* [2] */
  37. peer_idx_invalid:1, /* [3] */
  38. peer_idx_timeout:1, /* [4] */
  39. power_mgmt:1, /* [5] */
  40. non_qos:1, /* [6] */
  41. null_data:1, /* [7] */
  42. mgmt_type:1, /* [8] */
  43. ctrl_type:1, /* [9] */
  44. more_data:1, /* [10] */
  45. eosp:1, /* [11] */
  46. u_apsd_trigger:1, /* [12] */
  47. fragment:1, /* [13] */
  48. order:1, /* [14] */
  49. classification:1, /* [15] */
  50. overflow_err:1, /* [16] */
  51. msdu_length_err:1, /* [17] */
  52. tcp_udp_chksum_fail:1, /* [18] */
  53. ip_chksum_fail:1, /* [19] */
  54. sa_idx_invalid:1, /* [20] */
  55. da_idx_invalid:1, /* [21] */
  56. sa_idx_timeout:1, /* [22] */
  57. da_idx_timeout:1, /* [23] */
  58. encrypt_required:1, /* [24] */
  59. directed:1, /* [25] */
  60. buffer_fragment:1, /* [26] */
  61. mpdu_length_err:1, /* [27] */
  62. tkip_mic_err:1, /* [28] */
  63. decrypt_err:1, /* [29] */
  64. fcs_err:1, /* [30] */
  65. msdu_done:1; /* [31] */
  66. };
  67. struct rx_frag_info {
  68. volatile
  69. uint32_t ring0_more_count:8, /* [7:0] */
  70. ring1_more_count:8, /* [15:8] */
  71. ring2_more_count:8, /* [23:16] */
  72. ring3_more_count:8; /* [31:24] */
  73. volatile
  74. uint32_t ring4_more_count:8, /* [7:0] */
  75. ring5_more_count:8, /* [15:8] */
  76. ring6_more_count:8, /* [23:16] */
  77. ring7_more_count:8; /* [31:24] */
  78. };
  79. struct rx_msdu_start {
  80. volatile
  81. uint32_t msdu_length:14, /* [13:0] */
  82. #if defined(HELIUMPLUS)
  83. l3_offset:7, /* [20:14] */
  84. ipsec_ah:1, /* [21] */
  85. reserved_0a:2, /* [23:22] */
  86. l4_offset:7, /* [30:24] */
  87. ipsec_esp:1; /* [31] */
  88. #else
  89. ip_offset:6, /* [19:14] */
  90. ring_mask:4, /* [23:20] */
  91. tcp_udp_offset:7, /* [30:24] */
  92. reserved_0c:1; /* [31] */
  93. #endif /* defined(HELIUMPLUS) */
  94. #if defined(HELIUMPLUS)
  95. volatile uint32_t flow_id_toeplitz:32; /* [31:0] */
  96. #else
  97. volatile uint32_t flow_id_crc:32; /* [31:0] */
  98. #endif /* defined(HELIUMPLUS) */
  99. volatile
  100. uint32_t msdu_number:8, /* [7:0] */
  101. decap_format:2, /* [9:8] */
  102. ipv4_proto:1, /* [10] */
  103. ipv6_proto:1, /* [11] */
  104. tcp_proto:1, /* [12] */
  105. udp_proto:1, /* [13] */
  106. ip_frag:1, /* [14] */
  107. tcp_only_ack:1, /* [15] */
  108. sa_idx:11, /* [26:16] */
  109. reserved_2b:5; /* [31:27] */
  110. #if defined(HELIUMPLUS_PADDR64)
  111. volatile
  112. uint32_t da_idx:11, /* [10:0] */
  113. da_is_bcast_mcast:1, /* [11] */
  114. reserved_3a:4, /* [15:12] */
  115. ip4_protocol_ip6_next_header:8, /* [23:16] */
  116. ring_mask:8; /* [31:24] */
  117. volatile uint32_t toeplitz_hash_2_or_4:32; /* [31:0] */
  118. #endif /* defined(HELIUMPLUS_PADDR64) */
  119. };
  120. struct rx_msdu_end {
  121. volatile
  122. uint32_t ip_hdr_chksum:16, /* [15:0] */
  123. tcp_udp_chksum:16; /* [31:16] */
  124. volatile
  125. uint32_t key_id_octet:8, /* [7:0] */
  126. #if defined(HELIUMPLUS)
  127. classification_rule:6, /* [13:8] */
  128. classify_not_done_truncate:1, /* [14] */
  129. classify_not_done_cce_dis:1, /* [15] */
  130. #else
  131. classification_filter:8, /* [15:8] */
  132. #endif /* defined(HELIUMPLUS) */
  133. ext_wapi_pn_63_48:16; /* [31:16] */
  134. volatile uint32_t ext_wapi_pn_95_64:32; /* [31:0] */
  135. volatile uint32_t ext_wapi_pn_127_96:32; /* [31:0] */
  136. volatile
  137. uint32_t reported_mpdu_length:14, /* [13:0] */
  138. first_msdu:1, /* [14] */
  139. last_msdu:1, /* [15] */
  140. #if defined(HELIUMPLUS)
  141. sa_idx_timeout:1, /* [16] */
  142. da_idx_timeout:1, /* [17] */
  143. msdu_limit_error:1, /* [18] */
  144. classify_ring_mask:8, /* [26:19] */
  145. #endif /* defined(HELIUMPLUS) */
  146. reserved_3a:3, /* [29:27] */
  147. pre_delim_err:1, /* [30] */
  148. reserved_3b:1; /* [31] */
  149. #if defined(HELIUMPLUS_PADDR64)
  150. volatile uint32_t ipv6_options_crc:32;
  151. volatile uint32_t tcp_seq_number:32;
  152. volatile uint32_t tcp_ack_number:32;
  153. volatile
  154. uint32_t tcp_flag:9, /* [8:0] */
  155. lro_eligible:1, /* [9] */
  156. l3_header_padding:3, /* [12:10] */
  157. reserved_8a:3, /* [15:13] */
  158. window_size:16; /* [31:16] */
  159. volatile
  160. uint32_t da_offset:6, /* [5:0] */
  161. sa_offset:6, /* [11:6] */
  162. da_offset_valid:1, /* [12] */
  163. sa_offset_valid:1, /* [13] */
  164. type_offset:7, /* [20:14] */
  165. reserved_9a:11; /* [31:21] */
  166. volatile uint32_t rule_indication_31_0:32;
  167. volatile uint32_t rule_indication_63_32:32;
  168. volatile uint32_t rule_indication_95_64:32;
  169. volatile uint32_t rule_indication_127_96:32;
  170. #endif /* defined(HELIUMPLUS_PADDR64) */
  171. };
  172. struct rx_mpdu_end {
  173. volatile
  174. uint32_t reserved_0:13, /* [12:0] */
  175. overflow_err:1, /* [13] */
  176. last_mpdu:1, /* [14] */
  177. post_delim_err:1, /* [15] */
  178. post_delim_cnt:12, /* [27:16] */
  179. mpdu_length_err:1, /* [28] */
  180. tkip_mic_err:1, /* [29] */
  181. decrypt_err:1, /* [30] */
  182. fcs_err:1; /* [31] */
  183. };
  184. #if defined(HELIUMPLUS)
  185. struct rx_mpdu_start {
  186. volatile
  187. uint32_t peer_idx:11, /* [10:0] */
  188. fr_ds:1, /* [11] */
  189. to_ds:1, /* [12] */
  190. encrypted:1, /* [13] */
  191. retry:1, /* [14] */
  192. reserved:1, /* [15] */
  193. seq_num:12, /* [27:16] */
  194. encrypt_type:4; /* [31:28] */
  195. volatile uint32_t pn_31_0:32; /* [31:0] */
  196. volatile
  197. uint32_t pn_47_32:16, /* [15:0] */
  198. toeplitz_hash:2, /* [17:16] */
  199. reserved_2:10, /* [27:18] */
  200. tid:4; /* [31:28] */
  201. };
  202. struct rx_ppdu_start {
  203. volatile
  204. uint32_t rssi_pri_chain0:8, /* [7:0] */
  205. rssi_sec20_chain0:8, /* [15:8] */
  206. rssi_sec40_chain0:8, /* [23:16] */
  207. rssi_sec80_chain0:8; /* [31:24] */
  208. volatile
  209. uint32_t rssi_pri_chain1:8, /* [7:0] */
  210. rssi_sec20_chain1:8, /* [15:8] */
  211. rssi_sec40_chain1:8, /* [23:16] */
  212. rssi_sec80_chain1:8; /* [31:24] */
  213. volatile
  214. uint32_t rssi_pri_chain2:8, /* [7:0] */
  215. rssi_sec20_chain2:8, /* [15:8] */
  216. rssi_sec40_chain2:8, /* [23:16] */
  217. rssi_sec80_chain2:8; /* [31:24] */
  218. volatile
  219. uint32_t rssi_pri_chain3:8, /* [7:0] */
  220. rssi_sec20_chain3:8, /* [15:8] */
  221. rssi_sec40_chain3:8, /* [23:16] */
  222. rssi_sec80_chain3:8; /* [31:24] */
  223. volatile
  224. uint32_t rssi_comb:8, /* [7:0] */
  225. bandwidth:3, /* [10:8] */
  226. reserved_4a:5, /* [15:11] */
  227. rssi_comb_ht:8, /* [23:16] */
  228. reserved_4b:8; /* [31:24] */
  229. volatile
  230. uint32_t l_sig_rate:4, /*[3:0] */
  231. l_sig_rate_select:1, /* [4] */
  232. l_sig_length:12, /* [16:5] */
  233. l_sig_parity:1, /* [17] */
  234. l_sig_tail:6, /* [23:18] */
  235. preamble_type:8; /* [31:24] */
  236. volatile
  237. uint32_t ht_sig_vht_sig_ah_sig_a_1:24, /* [23:0] */
  238. captured_implicit_sounding:1, /* [24] */
  239. reserved_6:7; /* [31:25] */
  240. volatile
  241. uint32_t ht_sig_vht_sig_ah_sig_a_2:24, /* [23:0] */
  242. reserved_7:8; /* [31:24] */
  243. volatile uint32_t vht_sig_b:32; /* [31:0] */
  244. volatile
  245. uint32_t service:16, /* [15:0] */
  246. reserved_9:16; /* [31:16] */
  247. };
  248. struct rx_location_info {
  249. volatile
  250. uint32_t rtt_fac_legacy:14, /* [13:0] */
  251. rtt_fac_legacy_status:1, /* [14] */
  252. rtt_fac_vht:14, /* [28:15] */
  253. rtt_fac_vht_status:1, /* [29] */
  254. rtt_cfr_status:1, /* [30] */
  255. rtt_cir_status:1; /* [31] */
  256. volatile
  257. uint32_t rtt_fac_sifs:10, /* [9:0] */
  258. rtt_fac_sifs_status:2, /* [11:10] */
  259. rtt_channel_dump_size:11, /* [22:12] */
  260. rtt_mac_phy_phase:2, /* [24:23] */
  261. rtt_hw_ifft_mode:1, /* [25] */
  262. rtt_btcf_status:1, /* [26] */
  263. rtt_preamble_type:2, /* [28:27] */
  264. rtt_pkt_bw:2, /* [30:29] */
  265. rtt_gi_type:1; /* [31] */
  266. volatile
  267. uint32_t rtt_mcs_rate:4, /* [3:0] */
  268. rtt_strongest_chain:2, /* [5:4] */
  269. rtt_phase_jump:7, /* [12:6] */
  270. rtt_rx_chain_mask:4, /* [16:13] */
  271. rtt_tx_data_start_x_phase:1, /* [17] */
  272. reserved_2:13, /* [30:18] */
  273. rx_location_info_valid:1; /* [31] */
  274. };
  275. struct rx_pkt_end {
  276. volatile
  277. uint32_t rx_success:1, /* [0] */
  278. reserved_0a:2, /* [2:1] */
  279. error_tx_interrupt_rx:1, /* [3] */
  280. error_ofdm_power_drop:1, /* [4] */
  281. error_ofdm_restart:1, /* [5] */
  282. error_cck_power_drop:1, /* [6] */
  283. error_cck_restart:1, /* [7] */
  284. reserved_0b:24; /* [31:8] */
  285. volatile uint32_t phy_timestamp_1_lower_32:32; /* [31:0] */
  286. volatile uint32_t phy_timestamp_1_upper_32:32; /* [31:0] */
  287. volatile uint32_t phy_timestamp_2_lower_32:32; /* [31:0] */
  288. volatile uint32_t phy_timestamp_2_upper_32:32; /* [31:0] */
  289. struct rx_location_info rx_location_info;
  290. };
  291. struct rx_phy_ppdu_end {
  292. volatile
  293. uint32_t reserved_0a:2, /* [1:0] */
  294. error_radar:1, /* [2] */
  295. error_rx_abort:1, /* [3] */
  296. error_rx_nap:1, /* [4] */
  297. error_ofdm_timing:1, /* [5] */
  298. error_ofdm_signal_parity:1, /* [6] */
  299. error_ofdm_rate_illegal:1, /* [7] */
  300. error_ofdm_length_illegal:1, /* [8] */
  301. error_ppdu_ofdm_restart:1, /* [9] */
  302. error_ofdm_service:1, /* [10] */
  303. error_ppdu_ofdm_power_drop:1, /* [11] */
  304. error_cck_blocker:1, /* [12] */
  305. error_cck_timing:1, /* [13] */
  306. error_cck_header_crc:1, /* [14] */
  307. error_cck_rate_illegal:1, /* [15] */
  308. error_cck_length_illegal:1, /* [16] */
  309. error_ppdu_cck_restart:1, /* [17] */
  310. error_cck_service:1, /* [18] */
  311. error_ppdu_cck_power_drop:1, /* [19] */
  312. error_ht_crc_err:1, /* [20] */
  313. error_ht_length_illegal:1, /* [21] */
  314. error_ht_rate_illegal:1, /* [22] */
  315. error_ht_zlf:1, /* [23] */
  316. error_false_radar_ext:1, /* [24] */
  317. error_green_field:1, /* [25] */
  318. error_spectral_scan:1, /* [26] */
  319. error_rx_bw_gt_dyn_bw:1, /* [27] */
  320. error_leg_ht_mismatch:1, /* [28] */
  321. error_vht_crc_error:1, /* [29] */
  322. error_vht_siga_unsupported:1, /* [30] */
  323. error_vht_lsig_len_invalid:1; /* [31] */
  324. volatile
  325. uint32_t error_vht_ndp_or_zlf:1, /* [0] */
  326. error_vht_nsym_lt_zero:1, /* [1] */
  327. error_vht_rx_extra_symbol_mismatch:1, /* [2] */
  328. error_vht_rx_skip_group_id0:1, /* [3] */
  329. error_vht_rx_skip_group_id1to62:1, /* [4] */
  330. error_vht_rx_skip_group_id63:1, /* [5] */
  331. error_ofdm_ldpc_decoder_disabled:1, /* [6] */
  332. error_defer_nap:1, /* [7] */
  333. error_fdomain_timeout:1, /* [8] */
  334. error_lsig_rel_check:1, /* [9] */
  335. error_bt_collision:1, /* [10] */
  336. error_unsupported_mu_feedback:1, /* [11] */
  337. error_ppdu_tx_interrupt_rx:1, /* [12] */
  338. error_rx_unsupported_cbf:1, /* [13] */
  339. reserved_1:18; /* [31:14] */
  340. };
  341. struct rx_timing_offset {
  342. volatile
  343. uint32_t timing_offset:12, /* [11:0] */
  344. reserved:20; /* [31:12] */
  345. };
  346. struct rx_ppdu_end {
  347. volatile uint32_t evm_p0:32;
  348. volatile uint32_t evm_p1:32;
  349. volatile uint32_t evm_p2:32;
  350. volatile uint32_t evm_p3:32;
  351. volatile uint32_t evm_p4:32;
  352. volatile uint32_t evm_p5:32;
  353. volatile uint32_t evm_p6:32;
  354. volatile uint32_t evm_p7:32;
  355. volatile uint32_t evm_p8:32;
  356. volatile uint32_t evm_p9:32;
  357. volatile uint32_t evm_p10:32;
  358. volatile uint32_t evm_p11:32;
  359. volatile uint32_t evm_p12:32;
  360. volatile uint32_t evm_p13:32;
  361. volatile uint32_t evm_p14:32;
  362. volatile uint32_t evm_p15:32;
  363. volatile uint32_t reserved_16:32;
  364. volatile uint32_t reserved_17:32;
  365. volatile uint32_t wb_timestamp_lower_32:32;
  366. volatile uint32_t wb_timestamp_upper_32:32;
  367. struct rx_pkt_end rx_pkt_end;
  368. struct rx_phy_ppdu_end rx_phy_ppdu_end;
  369. struct rx_timing_offset rx_timing_offset;
  370. volatile
  371. uint32_t rx_antenna:24, /* [23:0] */
  372. tx_ht_vht_ack:1, /* [24] */
  373. rx_pkt_end_valid:1, /* [25] */
  374. rx_phy_ppdu_end_valid:1, /* [26] */
  375. rx_timing_offset_valid:1, /* [27] */
  376. bb_captured_channel:1, /* [28] */
  377. unsupported_mu_nc:1, /* [29] */
  378. otp_txbf_disable:1, /* [30] */
  379. reserved_31:1; /* [31] */
  380. volatile
  381. uint32_t coex_bt_tx_from_start_of_rx:1, /* [0] */
  382. coex_bt_tx_after_start_of_rx:1, /* [1] */
  383. coex_wan_tx_from_start_of_rx:1, /* [2] */
  384. coex_wan_tx_after_start_of_rx:1, /* [3] */
  385. coex_wlan_tx_from_start_of_rx:1, /* [4] */
  386. coex_wlan_tx_after_start_of_rx:1, /* [5] */
  387. mpdu_delimiter_errors_seen:1, /* [6] */
  388. ftm:1, /* [7] */
  389. ftm_dialog_token:8, /* [15:8] */
  390. ftm_follow_up_dialog_token:8, /* [23:16] */
  391. reserved_32:8; /* [31:24] */
  392. volatile
  393. uint32_t before_mpdu_cnt_passing_fcs:8, /* [7:0] */
  394. before_mpdu_cnt_failing_fcs:8, /* [15:8] */
  395. after_mpdu_cnt_passing_fcs:8, /* [23:16] */
  396. after_mpdu_cnt_failing_fcs:8; /* [31:24] */
  397. volatile uint32_t phy_timestamp_tx_lower_32:32; /* [31:0] */
  398. volatile uint32_t phy_timestamp_tx_upper_32:32; /* [31:0] */
  399. volatile
  400. uint32_t bb_length:16, /* [15:0] */
  401. bb_data:1, /* [16] */
  402. peer_idx_valid:1, /* [17] */
  403. peer_idx:11, /* [28:18] */
  404. reserved_26:2, /* [30:29] */
  405. ppdu_done:1; /* [31] */
  406. };
  407. #else
  408. struct rx_ppdu_start {
  409. volatile
  410. uint32_t rssi_chain0_pri20:8, /* [7:0] */
  411. rssi_chain0_sec20:8, /* [15:8] */
  412. rssi_chain0_sec40:8, /* [23:16] */
  413. rssi_chain0_sec80:8; /* [31:24] */
  414. volatile
  415. uint32_t rssi_chain1_pri20:8, /* [7:0] */
  416. rssi_chain1_sec20:8, /* [15:8] */
  417. rssi_chain1_sec40:8, /* [23:16] */
  418. rssi_chain1_sec80:8; /* [31:24] */
  419. volatile
  420. uint32_t rssi_chain2_pri20:8, /* [7:0] */
  421. rssi_chain2_sec20:8, /* [15:8] */
  422. rssi_chain2_sec40:8, /* [23:16] */
  423. rssi_chain2_sec80:8; /* [31:24] */
  424. volatile
  425. uint32_t rssi_chain3_pri20:8, /* [7:0] */
  426. rssi_chain3_sec20:8, /* [15:8] */
  427. rssi_chain3_sec40:8, /* [23:16] */
  428. rssi_chain3_sec80:8; /* [31:24] */
  429. volatile
  430. uint32_t rssi_comb:8, /* [7:0] */
  431. reserved_4a:16, /* [23:8] */
  432. is_greenfield:1, /* [24] */
  433. reserved_4b:7; /* [31:25] */
  434. volatile
  435. uint32_t l_sig_rate:4, /* [3:0] */
  436. l_sig_rate_select:1, /* [4] */
  437. l_sig_length:12, /* [16:5] */
  438. l_sig_parity:1, /* [17] */
  439. l_sig_tail:6, /* [23:18] */
  440. preamble_type:8; /* [31:24] */
  441. volatile
  442. uint32_t ht_sig_vht_sig_a_1:24, /* [23:0] */
  443. reserved_6:8; /* [31:24] */
  444. volatile
  445. uint32_t ht_sig_vht_sig_a_2:24, /* [23:0] */
  446. txbf_h_info:1, /* [24] */
  447. reserved_7:7; /* [31:25] */
  448. volatile
  449. uint32_t vht_sig_b:29, /* [28:0] */
  450. reserved_8:3; /* [31:29] */
  451. volatile
  452. uint32_t service:16, /* [15:0] */
  453. reserved_9:16; /* [31:16] */
  454. };
  455. struct rx_mpdu_start {
  456. volatile
  457. uint32_t peer_idx:11, /* [10:0] */
  458. fr_ds:1, /* [11] */
  459. to_ds:1, /* [12] */
  460. encrypted:1, /* [13] */
  461. retry:1, /* [14] */
  462. txbf_h_info:1, /* [15] */
  463. seq_num:12, /* [27:16] */
  464. encrypt_type:4; /* [31:28] */
  465. volatile uint32_t pn_31_0:32; /* [31:0] */
  466. volatile
  467. uint32_t pn_47_32:16, /* [15:0] */
  468. directed:1, /* [16] */
  469. reserved_2:11, /* [27:17] */
  470. tid:4; /* [31:28] */
  471. };
  472. struct rx_ppdu_end {
  473. volatile uint32_t evm_p0:32; /* [31:0] */
  474. volatile uint32_t evm_p1:32; /* [31:0] */
  475. volatile uint32_t evm_p2:32; /* [31:0] */
  476. volatile uint32_t evm_p3:32; /* [31:0] */
  477. volatile uint32_t evm_p4:32; /* [31:0] */
  478. volatile uint32_t evm_p5:32; /* [31:0] */
  479. volatile uint32_t evm_p6:32; /* [31:0] */
  480. volatile uint32_t evm_p7:32; /* [31:0] */
  481. volatile uint32_t evm_p8:32; /* [31:0] */
  482. volatile uint32_t evm_p9:32; /* [31:0] */
  483. volatile uint32_t evm_p10:32; /* [31:0] */
  484. volatile uint32_t evm_p11:32; /* [31:0] */
  485. volatile uint32_t evm_p12:32; /* [31:0] */
  486. volatile uint32_t evm_p13:32; /* [31:0] */
  487. volatile uint32_t evm_p14:32; /* [31:0] */
  488. volatile uint32_t evm_p15:32; /* [31:0] */
  489. volatile uint32_t tsf_timestamp:32; /* [31:0] */
  490. volatile uint32_t wb_timestamp:32; /* [31:0] */
  491. volatile
  492. uint32_t locationing_timestamp:8, /* [7:0] */
  493. phy_err_code:8, /* [15:8] */
  494. phy_err:1, /* [16] */
  495. rx_location:1, /* [17] */
  496. txbf_h_info:1, /* [18] */
  497. reserved_18:13; /* [31:19] */
  498. volatile
  499. uint32_t rx_antenna:24, /* [23:0] */
  500. tx_ht_vht_ack:1, /* [24] */
  501. bb_captured_channel:1, /* [25] */
  502. reserved_19:6; /* [31:26] */
  503. volatile
  504. uint32_t rtt_correction_value:24, /* [23:0] */
  505. reserved_20:7, /* [30:24] */
  506. rtt_normal_mode:1; /* [31] */
  507. volatile
  508. uint32_t bb_length:16, /* [15:0] */
  509. reserved_21:15, /* [30:16] */
  510. ppdu_done:1; /* [31] */
  511. };
  512. #endif /* defined(HELIUMPLUS) */
  513. #endif /*_RX_DESC_H_*/