cvp_hfi.c 117 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <asm/memory.h>
  6. #include <linux/coresight-stm.h>
  7. #include <linux/delay.h>
  8. #include <linux/devfreq.h>
  9. #include <linux/hash.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/iommu.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/of.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/slab.h>
  18. #include <linux/workqueue.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/soc/qcom/llcc-qcom.h>
  21. #include <linux/qcom_scm.h>
  22. #include <linux/soc/qcom/smem.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/reset.h>
  25. #include "hfi_packetization.h"
  26. #include "msm_cvp_debug.h"
  27. #include "cvp_core_hfi.h"
  28. #include "cvp_hfi_helper.h"
  29. #include "cvp_hfi_io.h"
  30. #include "msm_cvp_dsp.h"
  31. #define FIRMWARE_SIZE 0X00A00000
  32. #define REG_ADDR_OFFSET_BITMASK 0x000FFFFF
  33. #define QDSS_IOVA_START 0x80001000
  34. #define MIN_PAYLOAD_SIZE 3
  35. const struct msm_cvp_hfi_defs cvp_hfi_defs[] = {
  36. {
  37. .size = HFI_DFS_CONFIG_CMD_SIZE,
  38. .type = HFI_CMD_SESSION_CVP_DFS_CONFIG,
  39. .buf_offset = 0,
  40. .buf_num = 0,
  41. .resp = HAL_SESSION_DFS_CONFIG_CMD_DONE,
  42. },
  43. {
  44. .size = HFI_DFS_FRAME_CMD_SIZE,
  45. .type = HFI_CMD_SESSION_CVP_DFS_FRAME,
  46. .buf_offset = HFI_DFS_FRAME_BUFFERS_OFFSET,
  47. .buf_num = HFI_DFS_BUF_NUM,
  48. .resp = HAL_NO_RESP,
  49. },
  50. {
  51. .size = 0xFFFFFFFF,
  52. .type = HFI_CMD_SESSION_CVP_SGM_OF_CONFIG,
  53. .buf_offset = 0,
  54. .buf_num = 0,
  55. .resp = HAL_SESSION_SGM_OF_CONFIG_CMD_DONE,
  56. },
  57. {
  58. .size = 0xFFFFFFFF,
  59. .type = HFI_CMD_SESSION_CVP_SGM_OF_FRAME,
  60. .buf_offset = 0,
  61. .buf_num = 0,
  62. .resp = HAL_NO_RESP,
  63. },
  64. {
  65. .size = 0xFFFFFFFF,
  66. .type = HFI_CMD_SESSION_CVP_WARP_NCC_CONFIG,
  67. .buf_offset = 0,
  68. .buf_num = 0,
  69. .resp = HAL_SESSION_WARP_NCC_CONFIG_CMD_DONE,
  70. },
  71. {
  72. .size = 0xFFFFFFFF,
  73. .type = HFI_CMD_SESSION_CVP_WARP_NCC_FRAME,
  74. .buf_offset = 0,
  75. .buf_num = 0,
  76. .resp = HAL_NO_RESP,
  77. },
  78. {
  79. .size = 0xFFFFFFFF,
  80. .type = HFI_CMD_SESSION_CVP_WARP_CONFIG,
  81. .buf_offset = 0,
  82. .buf_num = 0,
  83. .resp = HAL_SESSION_WARP_CONFIG_CMD_DONE,
  84. },
  85. {
  86. .size = 0xFFFFFFFF,
  87. .type = HFI_CMD_SESSION_CVP_WARP_DS_PARAMS,
  88. .buf_offset = 0,
  89. .buf_num = 0,
  90. .resp = HAL_SESSION_WARP_DS_PARAMS_CMD_DONE,
  91. },
  92. {
  93. .size = 0xFFFFFFFF,
  94. .type = HFI_CMD_SESSION_CVP_WARP_FRAME,
  95. .buf_offset = 0,
  96. .buf_num = 0,
  97. .resp = HAL_NO_RESP,
  98. },
  99. {
  100. .size = HFI_DMM_CONFIG_CMD_SIZE,
  101. .type = HFI_CMD_SESSION_CVP_DMM_CONFIG,
  102. .buf_offset = 0,
  103. .buf_num = 0,
  104. .resp = HAL_SESSION_DMM_CONFIG_CMD_DONE,
  105. },
  106. {
  107. .size = 0xFFFFFFFF,
  108. .type = HFI_CMD_SESSION_CVP_DMM_PARAMS,
  109. .buf_offset = 0,
  110. .buf_num = 0,
  111. .resp = HAL_SESSION_DMM_PARAMS_CMD_DONE,
  112. },
  113. {
  114. .size = HFI_DMM_FRAME_CMD_SIZE,
  115. .type = HFI_CMD_SESSION_CVP_DMM_FRAME,
  116. .buf_offset = HFI_DMM_FRAME_BUFFERS_OFFSET,
  117. .buf_num = HFI_DMM_BUF_NUM,
  118. .resp = HAL_NO_RESP,
  119. },
  120. {
  121. .size = HFI_PERSIST_CMD_SIZE,
  122. .type = HFI_CMD_SESSION_CVP_SET_PERSIST_BUFFERS,
  123. .buf_offset = HFI_PERSIST_BUFFERS_OFFSET,
  124. .buf_num = HFI_PERSIST_BUF_NUM,
  125. .resp = HAL_SESSION_PERSIST_SET_DONE,
  126. },
  127. {
  128. .size = 0xffffffff,
  129. .type = HFI_CMD_SESSION_CVP_RELEASE_PERSIST_BUFFERS,
  130. .buf_offset = 0,
  131. .buf_num = 0,
  132. .resp = HAL_SESSION_PERSIST_REL_DONE,
  133. },
  134. {
  135. .size = HFI_DS_CMD_SIZE,
  136. .type = HFI_CMD_SESSION_CVP_DS,
  137. .buf_offset = HFI_DS_BUFFERS_OFFSET,
  138. .buf_num = HFI_DS_BUF_NUM,
  139. .resp = HAL_NO_RESP,
  140. },
  141. {
  142. .size = HFI_OF_CONFIG_CMD_SIZE,
  143. .type = HFI_CMD_SESSION_CVP_CV_TME_CONFIG,
  144. .buf_offset = 0,
  145. .buf_num = 0,
  146. .resp = HAL_SESSION_TME_CONFIG_CMD_DONE,
  147. },
  148. {
  149. .size = HFI_OF_FRAME_CMD_SIZE,
  150. .type = HFI_CMD_SESSION_CVP_CV_TME_FRAME,
  151. .buf_offset = HFI_OF_BUFFERS_OFFSET,
  152. .buf_num = HFI_OF_BUF_NUM,
  153. .resp = HAL_NO_RESP,
  154. },
  155. {
  156. .size = HFI_ODT_CONFIG_CMD_SIZE,
  157. .type = HFI_CMD_SESSION_CVP_CV_ODT_CONFIG,
  158. .buf_offset = 0,
  159. .buf_num = 0,
  160. .resp = HAL_SESSION_ODT_CONFIG_CMD_DONE,
  161. },
  162. {
  163. .size = HFI_ODT_FRAME_CMD_SIZE,
  164. .type = HFI_CMD_SESSION_CVP_CV_ODT_FRAME,
  165. .buf_offset = HFI_ODT_BUFFERS_OFFSET,
  166. .buf_num = HFI_ODT_BUF_NUM,
  167. .resp = HAL_NO_RESP,
  168. },
  169. {
  170. .size = HFI_OD_CONFIG_CMD_SIZE,
  171. .type = HFI_CMD_SESSION_CVP_CV_OD_CONFIG,
  172. .buf_offset = 0,
  173. .buf_num = 0,
  174. .resp = HAL_SESSION_OD_CONFIG_CMD_DONE,
  175. },
  176. {
  177. .size = HFI_OD_FRAME_CMD_SIZE,
  178. .type = HFI_CMD_SESSION_CVP_CV_OD_FRAME,
  179. .buf_offset = HFI_OD_BUFFERS_OFFSET,
  180. .buf_num = HFI_OD_BUF_NUM,
  181. .resp = HAL_NO_RESP,
  182. },
  183. {
  184. .size = HFI_NCC_CONFIG_CMD_SIZE,
  185. .type = HFI_CMD_SESSION_CVP_NCC_CONFIG,
  186. .buf_offset = 0,
  187. .buf_num = 0,
  188. .resp = HAL_SESSION_NCC_CONFIG_CMD_DONE,
  189. },
  190. {
  191. .size = HFI_NCC_FRAME_CMD_SIZE,
  192. .type = HFI_CMD_SESSION_CVP_NCC_FRAME,
  193. .buf_offset = HFI_NCC_BUFFERS_OFFSET,
  194. .buf_num = HFI_NCC_BUF_NUM,
  195. .resp = HAL_NO_RESP,
  196. },
  197. {
  198. .size = HFI_ICA_CONFIG_CMD_SIZE,
  199. .type = HFI_CMD_SESSION_CVP_ICA_CONFIG,
  200. .buf_offset = 0,
  201. .buf_num = 0,
  202. .resp = HAL_SESSION_ICA_CONFIG_CMD_DONE,
  203. },
  204. {
  205. .size = HFI_ICA_FRAME_CMD_SIZE,
  206. .type = HFI_CMD_SESSION_CVP_ICA_FRAME,
  207. .buf_offset = HFI_ICA_BUFFERS_OFFSET,
  208. .buf_num = HFI_ICA_BUF_NUM,
  209. .resp = HAL_NO_RESP,
  210. },
  211. {
  212. .size = HFI_HCD_CONFIG_CMD_SIZE,
  213. .type = HFI_CMD_SESSION_CVP_HCD_CONFIG,
  214. .buf_offset = 0,
  215. .buf_num = 0,
  216. .resp = HAL_SESSION_HCD_CONFIG_CMD_DONE,
  217. },
  218. {
  219. .size = HFI_HCD_FRAME_CMD_SIZE,
  220. .type = HFI_CMD_SESSION_CVP_HCD_FRAME,
  221. .buf_offset = HFI_HCD_BUFFERS_OFFSET,
  222. .buf_num = HFI_HCD_BUF_NUM,
  223. .resp = HAL_NO_RESP,
  224. },
  225. {
  226. .size = HFI_DCM_CONFIG_CMD_SIZE,
  227. .type = HFI_CMD_SESSION_CVP_DC_CONFIG,
  228. .buf_offset = 0,
  229. .buf_num = 0,
  230. .resp = HAL_SESSION_DC_CONFIG_CMD_DONE,
  231. },
  232. {
  233. .size = HFI_DCM_FRAME_CMD_SIZE,
  234. .type = HFI_CMD_SESSION_CVP_DC_FRAME,
  235. .buf_offset = HFI_DCM_BUFFERS_OFFSET,
  236. .buf_num = HFI_DCM_BUF_NUM,
  237. .resp = HAL_NO_RESP,
  238. },
  239. {
  240. .size = HFI_DCM_CONFIG_CMD_SIZE,
  241. .type = HFI_CMD_SESSION_CVP_DCM_CONFIG,
  242. .buf_offset = 0,
  243. .buf_num = 0,
  244. .resp = HAL_SESSION_DCM_CONFIG_CMD_DONE,
  245. },
  246. {
  247. .size = HFI_DCM_FRAME_CMD_SIZE,
  248. .type = HFI_CMD_SESSION_CVP_DCM_FRAME,
  249. .buf_offset = HFI_DCM_BUFFERS_OFFSET,
  250. .buf_num = HFI_DCM_BUF_NUM,
  251. .resp = HAL_NO_RESP,
  252. },
  253. {
  254. .size = HFI_PYS_HCD_CONFIG_CMD_SIZE,
  255. .type = HFI_CMD_SESSION_CVP_PYS_HCD_CONFIG,
  256. .buf_offset = 0,
  257. .buf_num = 0,
  258. .resp = HAL_SESSION_PYS_HCD_CONFIG_CMD_DONE,
  259. },
  260. {
  261. .size = HFI_PYS_HCD_FRAME_CMD_SIZE,
  262. .type = HFI_CMD_SESSION_CVP_PYS_HCD_FRAME,
  263. .buf_offset = HFI_PYS_HCD_BUFFERS_OFFSET,
  264. .buf_num = HFI_PYS_HCD_BUF_NUM,
  265. .resp = HAL_NO_RESP,
  266. },
  267. {
  268. .size = 0xFFFFFFFF,
  269. .type = HFI_CMD_SESSION_CVP_SET_MODEL_BUFFERS,
  270. .buf_offset = 0,
  271. .buf_num = 0,
  272. .resp = HAL_SESSION_MODEL_BUF_CMD_DONE,
  273. },
  274. {
  275. .size = 0xFFFFFFFF,
  276. .type = HFI_CMD_SESSION_CVP_FD_CONFIG,
  277. .buf_offset = 0,
  278. .buf_num = 0,
  279. .resp = HAL_SESSION_FD_CONFIG_CMD_DONE,
  280. },
  281. {
  282. .size = 0xFFFFFFFF,
  283. .type = HFI_CMD_SESSION_CVP_FD_FRAME,
  284. .buf_offset = 0,
  285. .buf_num = 0,
  286. .resp = HAL_NO_RESP,
  287. },
  288. };
  289. struct cvp_tzbsp_memprot {
  290. u32 cp_start;
  291. u32 cp_size;
  292. u32 cp_nonpixel_start;
  293. u32 cp_nonpixel_size;
  294. };
  295. #define TZBSP_PIL_SET_STATE 0xA
  296. #define TZBSP_CVP_PAS_ID 26
  297. /* Poll interval in uS */
  298. #define POLL_INTERVAL_US 50
  299. enum tzbsp_subsys_state {
  300. TZ_SUBSYS_STATE_SUSPEND = 0,
  301. TZ_SUBSYS_STATE_RESUME = 1,
  302. TZ_SUBSYS_STATE_RESTORE_THRESHOLD = 2,
  303. };
  304. const struct msm_cvp_gov_data CVP_DEFAULT_BUS_VOTE = {
  305. .data = NULL,
  306. .data_count = 0,
  307. };
  308. const int cvp_max_packets = 32;
  309. static void iris_hfi_pm_handler(struct work_struct *work);
  310. static DECLARE_DELAYED_WORK(iris_hfi_pm_work, iris_hfi_pm_handler);
  311. static inline int __resume(struct iris_hfi_device *device);
  312. static inline int __suspend(struct iris_hfi_device *device);
  313. static int __disable_regulators(struct iris_hfi_device *device);
  314. static int __enable_regulators(struct iris_hfi_device *device);
  315. static inline int __prepare_enable_clks(struct iris_hfi_device *device);
  316. static inline void __disable_unprepare_clks(struct iris_hfi_device *device);
  317. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet);
  318. static int __initialize_packetization(struct iris_hfi_device *device);
  319. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  320. u32 session_id);
  321. static bool __is_session_valid(struct iris_hfi_device *device,
  322. struct cvp_hal_session *session, const char *func);
  323. static int __set_clocks(struct iris_hfi_device *device, u32 freq);
  324. static int __iface_cmdq_write(struct iris_hfi_device *device,
  325. void *pkt);
  326. static int __load_fw(struct iris_hfi_device *device);
  327. static void __unload_fw(struct iris_hfi_device *device);
  328. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state);
  329. static int __enable_subcaches(struct iris_hfi_device *device);
  330. static int __set_subcaches(struct iris_hfi_device *device);
  331. static int __release_subcaches(struct iris_hfi_device *device);
  332. static int __disable_subcaches(struct iris_hfi_device *device);
  333. static int __power_collapse(struct iris_hfi_device *device, bool force);
  334. static int iris_hfi_noc_error_info(void *dev);
  335. static void interrupt_init_iris2(struct iris_hfi_device *device);
  336. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device);
  337. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device);
  338. static int reset_ahb2axi_bridge(struct iris_hfi_device *device);
  339. static void power_off_iris2(struct iris_hfi_device *device);
  340. static int __set_ubwc_config(struct iris_hfi_device *device);
  341. static void __noc_error_info_iris2(struct iris_hfi_device *device);
  342. static int __enable_hw_power_collapse(struct iris_hfi_device *device);
  343. static struct iris_hfi_vpu_ops iris2_ops = {
  344. .interrupt_init = interrupt_init_iris2,
  345. .setup_dsp_uc_memmap = setup_dsp_uc_memmap_vpu5,
  346. .clock_config_on_enable = clock_config_on_enable_vpu5,
  347. .reset_ahb2axi_bridge = reset_ahb2axi_bridge,
  348. .power_off = power_off_iris2,
  349. .noc_error_info = __noc_error_info_iris2,
  350. };
  351. /**
  352. * Utility function to enforce some of our assumptions. Spam calls to this
  353. * in hotspots in code to double check some of the assumptions that we hold.
  354. */
  355. static inline void __strict_check(struct iris_hfi_device *device)
  356. {
  357. msm_cvp_res_handle_fatal_hw_error(device->res,
  358. !mutex_is_locked(&device->lock));
  359. }
  360. static inline void __set_state(struct iris_hfi_device *device,
  361. enum iris_hfi_state state)
  362. {
  363. device->state = state;
  364. }
  365. static inline bool __core_in_valid_state(struct iris_hfi_device *device)
  366. {
  367. return device->state != IRIS_STATE_DEINIT;
  368. }
  369. static inline bool is_sys_cache_present(struct iris_hfi_device *device)
  370. {
  371. return device->res->sys_cache_present;
  372. }
  373. #define ROW_SIZE 32
  374. int get_pkt_index(struct cvp_hal_session_cmd_pkt *hdr)
  375. {
  376. int i, pkt_num = ARRAY_SIZE(cvp_hfi_defs);
  377. for (i = 0; i < pkt_num; i++)
  378. if (cvp_hfi_defs[i].type == hdr->packet_type)
  379. return i;
  380. return -EINVAL;
  381. }
  382. int get_hfi_version(void)
  383. {
  384. struct msm_cvp_core *core;
  385. struct iris_hfi_device *hfi;
  386. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  387. hfi = (struct iris_hfi_device *)core->device->hfi_device_data;
  388. return hfi->version;
  389. }
  390. unsigned int get_msg_size(struct cvp_hfi_msg_session_hdr *hdr)
  391. {
  392. struct msm_cvp_core *core;
  393. struct iris_hfi_device *device;
  394. u32 minor_ver;
  395. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  396. if (core)
  397. device = core->device->hfi_device_data;
  398. else
  399. return 0;
  400. if (!device) {
  401. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  402. return 0;
  403. }
  404. minor_ver = (device->version & HFI_VERSION_MINOR_MASK) >>
  405. HFI_VERSION_MINOR_SHIFT;
  406. if (minor_ver < 2)
  407. return sizeof(struct cvp_hfi_msg_session_hdr);
  408. if (hdr->packet_type == HFI_MSG_SESSION_CVP_FD)
  409. return sizeof(struct cvp_hfi_msg_session_hdr_ext);
  410. else
  411. return sizeof(struct cvp_hfi_msg_session_hdr);
  412. }
  413. unsigned int get_msg_session_id(void *msg)
  414. {
  415. struct cvp_hfi_msg_session_hdr *hdr =
  416. (struct cvp_hfi_msg_session_hdr *)msg;
  417. return hdr->session_id;
  418. }
  419. unsigned int get_msg_errorcode(void *msg)
  420. {
  421. struct cvp_hfi_msg_session_hdr *hdr =
  422. (struct cvp_hfi_msg_session_hdr *)msg;
  423. return hdr->error_type;
  424. }
  425. int get_msg_opconfigs(void *msg, unsigned int *session_id,
  426. unsigned int *error_type, unsigned int *config_id)
  427. {
  428. struct cvp_hfi_msg_session_op_cfg_packet *cfg =
  429. (struct cvp_hfi_msg_session_op_cfg_packet *)msg;
  430. *session_id = cfg->session_id;
  431. *error_type = cfg->error_type;
  432. *config_id = cfg->op_conf_id;
  433. return 0;
  434. }
  435. int get_signal_from_pkt_type(unsigned int type)
  436. {
  437. int i, pkt_num = ARRAY_SIZE(cvp_hfi_defs);
  438. for (i = 0; i < pkt_num; i++)
  439. if (cvp_hfi_defs[i].type == type)
  440. return cvp_hfi_defs[i].resp;
  441. return -EINVAL;
  442. }
  443. static void __dump_packet(u8 *packet, enum cvp_msg_prio log_level)
  444. {
  445. u32 c = 0, packet_size = *(u32 *)packet;
  446. /*
  447. * row must contain enough for 0xdeadbaad * 8 to be converted into
  448. * "de ad ba ab " * 8 + '\0'
  449. */
  450. char row[3 * ROW_SIZE];
  451. for (c = 0; c * ROW_SIZE < packet_size; ++c) {
  452. int bytes_to_read = ((c + 1) * ROW_SIZE > packet_size) ?
  453. packet_size % ROW_SIZE : ROW_SIZE;
  454. hex_dump_to_buffer(packet + c * ROW_SIZE, bytes_to_read,
  455. ROW_SIZE, 4, row, sizeof(row), false);
  456. dprintk(log_level, "%s\n", row);
  457. }
  458. }
  459. static int __dsp_suspend(struct iris_hfi_device *device, bool force, u32 flags)
  460. {
  461. int rc;
  462. struct cvp_hal_session *temp;
  463. if (msm_cvp_dsp_disable)
  464. return 0;
  465. list_for_each_entry(temp, &device->sess_head, list) {
  466. /* if forceful suspend, don't check session pause info */
  467. if (force)
  468. continue;
  469. /* don't suspend if cvp session is not paused */
  470. if (!(temp->flags & SESSION_PAUSE)) {
  471. dprintk(CVP_DSP,
  472. "%s: cvp session %x not paused\n",
  473. __func__, hash32_ptr(temp));
  474. return -EBUSY;
  475. }
  476. }
  477. dprintk(CVP_DSP, "%s: suspend dsp\n", __func__);
  478. rc = cvp_dsp_suspend(flags);
  479. if (rc) {
  480. dprintk(CVP_ERR, "%s: dsp suspend failed with error %d\n",
  481. __func__, rc);
  482. return -EINVAL;
  483. }
  484. dprintk(CVP_DSP, "%s: dsp suspended\n", __func__);
  485. return 0;
  486. }
  487. static int __dsp_resume(struct iris_hfi_device *device, u32 flags)
  488. {
  489. int rc;
  490. if (msm_cvp_dsp_disable)
  491. return 0;
  492. dprintk(CVP_DSP, "%s: resume dsp\n", __func__);
  493. rc = cvp_dsp_resume(flags);
  494. if (rc) {
  495. dprintk(CVP_ERR,
  496. "%s: dsp resume failed with error %d\n",
  497. __func__, rc);
  498. return rc;
  499. }
  500. dprintk(CVP_DSP, "%s: dsp resumed\n", __func__);
  501. return rc;
  502. }
  503. static int __dsp_shutdown(struct iris_hfi_device *device, u32 flags)
  504. {
  505. int rc;
  506. if (msm_cvp_dsp_disable)
  507. return 0;
  508. dprintk(CVP_DSP, "%s: shutdown dsp\n", __func__);
  509. rc = cvp_dsp_shutdown(flags);
  510. if (rc) {
  511. dprintk(CVP_ERR,
  512. "%s: dsp shutdown failed with error %d\n",
  513. __func__, rc);
  514. WARN_ON(1);
  515. }
  516. dprintk(CVP_DSP, "%s: dsp shutdown successful\n", __func__);
  517. return rc;
  518. }
  519. static int __acquire_regulator(struct regulator_info *rinfo,
  520. struct iris_hfi_device *device)
  521. {
  522. int rc = 0;
  523. if (rinfo->has_hw_power_collapse) {
  524. rc = regulator_set_mode(rinfo->regulator,
  525. REGULATOR_MODE_NORMAL);
  526. if (rc) {
  527. /*
  528. * This is somewhat fatal, but nothing we can do
  529. * about it. We can't disable the regulator w/o
  530. * getting it back under s/w control
  531. */
  532. dprintk(CVP_WARN,
  533. "Failed to acquire regulator control: %s\n",
  534. rinfo->name);
  535. } else {
  536. dprintk(CVP_PWR,
  537. "Acquire regulator control from HW: %s\n",
  538. rinfo->name);
  539. }
  540. }
  541. if (!regulator_is_enabled(rinfo->regulator)) {
  542. dprintk(CVP_WARN, "Regulator is not enabled %s\n",
  543. rinfo->name);
  544. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  545. }
  546. return rc;
  547. }
  548. static int __hand_off_regulator(struct regulator_info *rinfo)
  549. {
  550. int rc = 0;
  551. if (rinfo->has_hw_power_collapse) {
  552. rc = regulator_set_mode(rinfo->regulator,
  553. REGULATOR_MODE_FAST);
  554. if (rc) {
  555. dprintk(CVP_WARN,
  556. "Failed to hand off regulator control: %s\n",
  557. rinfo->name);
  558. } else {
  559. dprintk(CVP_PWR,
  560. "Hand off regulator control to HW: %s\n",
  561. rinfo->name);
  562. }
  563. }
  564. return rc;
  565. }
  566. static int __hand_off_regulators(struct iris_hfi_device *device)
  567. {
  568. struct regulator_info *rinfo;
  569. int rc = 0, c = 0;
  570. iris_hfi_for_each_regulator(device, rinfo) {
  571. rc = __hand_off_regulator(rinfo);
  572. /*
  573. * If one regulator hand off failed, driver should take
  574. * the control for other regulators back.
  575. */
  576. if (rc)
  577. goto err_reg_handoff_failed;
  578. c++;
  579. }
  580. return rc;
  581. err_reg_handoff_failed:
  582. iris_hfi_for_each_regulator_reverse_continue(device, rinfo, c)
  583. __acquire_regulator(rinfo, device);
  584. return rc;
  585. }
  586. static int __write_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  587. bool *rx_req_is_set)
  588. {
  589. struct cvp_hfi_queue_header *queue;
  590. u32 packet_size_in_words, new_write_idx;
  591. u32 empty_space, read_idx, write_idx;
  592. u32 *write_ptr;
  593. if (!qinfo || !packet) {
  594. dprintk(CVP_ERR, "Invalid Params\n");
  595. return -EINVAL;
  596. } else if (!qinfo->q_array.align_virtual_addr) {
  597. dprintk(CVP_WARN, "Queues have already been freed\n");
  598. return -EINVAL;
  599. }
  600. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  601. if (!queue) {
  602. dprintk(CVP_ERR, "queue not present\n");
  603. return -ENOENT;
  604. }
  605. if (msm_cvp_debug & CVP_PKT) {
  606. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  607. __dump_packet(packet, CVP_PKT);
  608. }
  609. packet_size_in_words = (*(u32 *)packet) >> 2;
  610. if (!packet_size_in_words || packet_size_in_words >
  611. qinfo->q_array.mem_size>>2) {
  612. dprintk(CVP_ERR, "Invalid packet size\n");
  613. return -ENODATA;
  614. }
  615. spin_lock(&qinfo->hfi_lock);
  616. read_idx = queue->qhdr_read_idx;
  617. write_idx = queue->qhdr_write_idx;
  618. empty_space = (write_idx >= read_idx) ?
  619. ((qinfo->q_array.mem_size>>2) - (write_idx - read_idx)) :
  620. (read_idx - write_idx);
  621. if (empty_space <= packet_size_in_words) {
  622. queue->qhdr_tx_req = 1;
  623. spin_unlock(&qinfo->hfi_lock);
  624. dprintk(CVP_ERR, "Insufficient size (%d) to write (%d)\n",
  625. empty_space, packet_size_in_words);
  626. return -ENOTEMPTY;
  627. }
  628. queue->qhdr_tx_req = 0;
  629. new_write_idx = write_idx + packet_size_in_words;
  630. write_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  631. (write_idx << 2));
  632. if (write_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  633. write_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  634. qinfo->q_array.mem_size)) {
  635. spin_unlock(&qinfo->hfi_lock);
  636. dprintk(CVP_ERR, "Invalid write index\n");
  637. return -ENODATA;
  638. }
  639. if (new_write_idx < (qinfo->q_array.mem_size >> 2)) {
  640. memcpy(write_ptr, packet, packet_size_in_words << 2);
  641. } else {
  642. new_write_idx -= qinfo->q_array.mem_size >> 2;
  643. memcpy(write_ptr, packet, (packet_size_in_words -
  644. new_write_idx) << 2);
  645. memcpy((void *)qinfo->q_array.align_virtual_addr,
  646. packet + ((packet_size_in_words - new_write_idx) << 2),
  647. new_write_idx << 2);
  648. }
  649. /*
  650. * Memory barrier to make sure packet is written before updating the
  651. * write index
  652. */
  653. mb();
  654. queue->qhdr_write_idx = new_write_idx;
  655. if (rx_req_is_set)
  656. *rx_req_is_set = queue->qhdr_rx_req == 1;
  657. /*
  658. * Memory barrier to make sure write index is updated before an
  659. * interrupt is raised.
  660. */
  661. mb();
  662. spin_unlock(&qinfo->hfi_lock);
  663. return 0;
  664. }
  665. static int __read_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  666. u32 *pb_tx_req_is_set)
  667. {
  668. struct cvp_hfi_queue_header *queue;
  669. u32 packet_size_in_words, new_read_idx;
  670. u32 *read_ptr;
  671. u32 receive_request = 0;
  672. u32 read_idx, write_idx;
  673. int rc = 0;
  674. if (!qinfo || !packet || !pb_tx_req_is_set) {
  675. dprintk(CVP_ERR, "Invalid Params\n");
  676. return -EINVAL;
  677. } else if (!qinfo->q_array.align_virtual_addr) {
  678. dprintk(CVP_WARN, "Queues have already been freed\n");
  679. return -EINVAL;
  680. }
  681. /*
  682. * Memory barrier to make sure data is valid before
  683. *reading it
  684. */
  685. mb();
  686. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  687. if (!queue) {
  688. dprintk(CVP_ERR, "Queue memory is not allocated\n");
  689. return -ENOMEM;
  690. }
  691. /*
  692. * Do not set receive request for debug queue, if set,
  693. * Iris generates interrupt for debug messages even
  694. * when there is no response message available.
  695. * In general debug queue will not become full as it
  696. * is being emptied out for every interrupt from Iris.
  697. * Iris will anyway generates interrupt if it is full.
  698. */
  699. spin_lock(&qinfo->hfi_lock);
  700. if (queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_MSG_Q)
  701. receive_request = 1;
  702. read_idx = queue->qhdr_read_idx;
  703. write_idx = queue->qhdr_write_idx;
  704. if (read_idx == write_idx) {
  705. queue->qhdr_rx_req = receive_request;
  706. /*
  707. * mb() to ensure qhdr is updated in main memory
  708. * so that iris reads the updated header values
  709. */
  710. mb();
  711. *pb_tx_req_is_set = 0;
  712. if (write_idx != queue->qhdr_write_idx) {
  713. queue->qhdr_rx_req = 0;
  714. } else {
  715. spin_unlock(&qinfo->hfi_lock);
  716. dprintk(CVP_HFI,
  717. "%s queue is empty, rx_req = %u, tx_req = %u, read_idx = %u\n",
  718. receive_request ? "message" : "debug",
  719. queue->qhdr_rx_req, queue->qhdr_tx_req,
  720. queue->qhdr_read_idx);
  721. return -ENODATA;
  722. }
  723. }
  724. read_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  725. (read_idx << 2));
  726. if (read_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  727. read_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  728. qinfo->q_array.mem_size - sizeof(*read_ptr))) {
  729. spin_unlock(&qinfo->hfi_lock);
  730. dprintk(CVP_ERR, "Invalid read index\n");
  731. return -ENODATA;
  732. }
  733. packet_size_in_words = (*read_ptr) >> 2;
  734. if (!packet_size_in_words) {
  735. spin_unlock(&qinfo->hfi_lock);
  736. dprintk(CVP_ERR, "Zero packet size\n");
  737. return -ENODATA;
  738. }
  739. new_read_idx = read_idx + packet_size_in_words;
  740. if (((packet_size_in_words << 2) <= CVP_IFACEQ_VAR_HUGE_PKT_SIZE)
  741. && read_idx <= (qinfo->q_array.mem_size >> 2)) {
  742. if (new_read_idx < (qinfo->q_array.mem_size >> 2)) {
  743. memcpy(packet, read_ptr,
  744. packet_size_in_words << 2);
  745. } else {
  746. new_read_idx -= (qinfo->q_array.mem_size >> 2);
  747. memcpy(packet, read_ptr,
  748. (packet_size_in_words - new_read_idx) << 2);
  749. memcpy(packet + ((packet_size_in_words -
  750. new_read_idx) << 2),
  751. (u8 *)qinfo->q_array.align_virtual_addr,
  752. new_read_idx << 2);
  753. }
  754. } else {
  755. dprintk(CVP_WARN,
  756. "BAD packet received, read_idx: %#x, pkt_size: %d\n",
  757. read_idx, packet_size_in_words << 2);
  758. dprintk(CVP_WARN, "Dropping this packet\n");
  759. new_read_idx = write_idx;
  760. rc = -ENODATA;
  761. }
  762. if (new_read_idx != queue->qhdr_write_idx)
  763. queue->qhdr_rx_req = 0;
  764. else
  765. queue->qhdr_rx_req = receive_request;
  766. queue->qhdr_read_idx = new_read_idx;
  767. /*
  768. * mb() to ensure qhdr is updated in main memory
  769. * so that iris reads the updated header values
  770. */
  771. mb();
  772. *pb_tx_req_is_set = (queue->qhdr_tx_req == 1) ? 1 : 0;
  773. spin_unlock(&qinfo->hfi_lock);
  774. if ((msm_cvp_debug & CVP_PKT) &&
  775. !(queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q)) {
  776. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  777. __dump_packet(packet, CVP_PKT);
  778. }
  779. return rc;
  780. }
  781. static int __smem_alloc(struct iris_hfi_device *dev, struct cvp_mem_addr *mem,
  782. u32 size, u32 align, u32 flags)
  783. {
  784. struct msm_cvp_smem *alloc = &mem->mem_data;
  785. int rc = 0;
  786. if (!dev || !mem || !size) {
  787. dprintk(CVP_ERR, "Invalid Params\n");
  788. return -EINVAL;
  789. }
  790. dprintk(CVP_INFO, "start to alloc size: %d, flags: %d\n", size, flags);
  791. alloc->flags = flags;
  792. rc = msm_cvp_smem_alloc(size, align, 1, (void *)dev->res, alloc);
  793. if (rc) {
  794. dprintk(CVP_ERR, "Alloc failed\n");
  795. rc = -ENOMEM;
  796. goto fail_smem_alloc;
  797. }
  798. dprintk(CVP_MEM, "%s: ptr = %pK, size = %d\n", __func__,
  799. alloc->kvaddr, size);
  800. mem->mem_size = alloc->size;
  801. mem->align_virtual_addr = alloc->kvaddr;
  802. mem->align_device_addr = alloc->device_addr;
  803. return rc;
  804. fail_smem_alloc:
  805. return rc;
  806. }
  807. static void __smem_free(struct iris_hfi_device *dev, struct msm_cvp_smem *mem)
  808. {
  809. if (!dev || !mem) {
  810. dprintk(CVP_ERR, "invalid param %pK %pK\n", dev, mem);
  811. return;
  812. }
  813. msm_cvp_smem_free(mem);
  814. }
  815. static void __write_register(struct iris_hfi_device *device,
  816. u32 reg, u32 value)
  817. {
  818. u32 hwiosymaddr = reg;
  819. u8 *base_addr;
  820. if (!device) {
  821. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  822. return;
  823. }
  824. __strict_check(device);
  825. if (!device->power_enabled) {
  826. dprintk(CVP_WARN,
  827. "HFI Write register failed : Power is OFF\n");
  828. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  829. return;
  830. }
  831. base_addr = device->cvp_hal_data->register_base;
  832. dprintk(CVP_REG, "Base addr: %pK, written to: %#x, Value: %#x...\n",
  833. base_addr, hwiosymaddr, value);
  834. base_addr += hwiosymaddr;
  835. writel_relaxed(value, base_addr);
  836. /*
  837. * Memory barrier to make sure value is written into the register.
  838. */
  839. wmb();
  840. }
  841. static int __read_register(struct iris_hfi_device *device, u32 reg)
  842. {
  843. int rc = 0;
  844. u8 *base_addr;
  845. if (!device) {
  846. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  847. return -EINVAL;
  848. }
  849. __strict_check(device);
  850. if (!device->power_enabled) {
  851. dprintk(CVP_WARN,
  852. "HFI Read register failed : Power is OFF\n");
  853. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  854. return -EINVAL;
  855. }
  856. base_addr = device->cvp_hal_data->register_base;
  857. rc = readl_relaxed(base_addr + reg);
  858. /*
  859. * Memory barrier to make sure value is read correctly from the
  860. * register.
  861. */
  862. rmb();
  863. dprintk(CVP_REG, "Base addr: %pK, read from: %#x, value: %#x...\n",
  864. base_addr, reg, rc);
  865. return rc;
  866. }
  867. static void __set_registers(struct iris_hfi_device *device)
  868. {
  869. struct reg_set *reg_set;
  870. int i;
  871. if (!device->res) {
  872. dprintk(CVP_ERR,
  873. "device resources null, cannot set registers\n");
  874. return;
  875. }
  876. reg_set = &device->res->reg_set;
  877. for (i = 0; i < reg_set->count; i++) {
  878. __write_register(device, reg_set->reg_tbl[i].reg,
  879. reg_set->reg_tbl[i].value);
  880. dprintk(CVP_REG, "write_reg offset=%x, val=%x\n",
  881. reg_set->reg_tbl[i].reg,
  882. reg_set->reg_tbl[i].value);
  883. }
  884. }
  885. /*
  886. * The existence of this function is a hack for 8996 (or certain Iris versions)
  887. * to overcome a hardware bug. Whenever the GDSCs momentarily power collapse
  888. * (after calling __hand_off_regulators()), the values of the threshold
  889. * registers (typically programmed by TZ) are incorrectly reset. As a result
  890. * reprogram these registers at certain agreed upon points.
  891. */
  892. static void __set_threshold_registers(struct iris_hfi_device *device)
  893. {
  894. u32 version = __read_register(device, CVP_WRAPPER_HW_VERSION);
  895. version &= ~GENMASK(15, 0);
  896. if (version != (0x3 << 28 | 0x43 << 16))
  897. return;
  898. if (__tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESTORE_THRESHOLD))
  899. dprintk(CVP_ERR, "Failed to restore threshold values\n");
  900. }
  901. static int __unvote_buses(struct iris_hfi_device *device)
  902. {
  903. int rc = 0;
  904. struct bus_info *bus = NULL;
  905. kfree(device->bus_vote.data);
  906. device->bus_vote.data = NULL;
  907. device->bus_vote.data_count = 0;
  908. iris_hfi_for_each_bus(device, bus) {
  909. rc = icc_set_bw(bus->client, 0, 0);
  910. if (rc) {
  911. dprintk(CVP_ERR,
  912. "%s: Failed unvoting bus\n", __func__);
  913. goto err_unknown_device;
  914. }
  915. }
  916. err_unknown_device:
  917. return rc;
  918. }
  919. static int __vote_buses(struct iris_hfi_device *device,
  920. struct cvp_bus_vote_data *data, int num_data)
  921. {
  922. int rc = 0;
  923. struct bus_info *bus = NULL;
  924. struct cvp_bus_vote_data *new_data = NULL;
  925. if (!num_data) {
  926. dprintk(CVP_PWR, "No vote data available\n");
  927. goto no_data_count;
  928. } else if (!data) {
  929. dprintk(CVP_ERR, "Invalid voting data\n");
  930. return -EINVAL;
  931. }
  932. new_data = kmemdup(data, num_data * sizeof(*new_data), GFP_KERNEL);
  933. if (!new_data) {
  934. dprintk(CVP_ERR, "Can't alloc memory to cache bus votes\n");
  935. rc = -ENOMEM;
  936. goto err_no_mem;
  937. }
  938. no_data_count:
  939. kfree(device->bus_vote.data);
  940. device->bus_vote.data = new_data;
  941. device->bus_vote.data_count = num_data;
  942. iris_hfi_for_each_bus(device, bus) {
  943. if (bus) {
  944. rc = icc_set_bw(bus->client, bus->range[1], 0);
  945. if (rc)
  946. dprintk(CVP_ERR,
  947. "Failed voting bus %s to ab %u\n",
  948. bus->name, bus->range[1]*1000);
  949. }
  950. }
  951. err_no_mem:
  952. return rc;
  953. }
  954. static int iris_hfi_vote_buses(void *dev, struct cvp_bus_vote_data *d, int n)
  955. {
  956. int rc = 0;
  957. struct iris_hfi_device *device = dev;
  958. if (!device)
  959. return -EINVAL;
  960. mutex_lock(&device->lock);
  961. rc = __vote_buses(device, d, n);
  962. mutex_unlock(&device->lock);
  963. return rc;
  964. }
  965. static int __core_set_resource(struct iris_hfi_device *device,
  966. struct cvp_resource_hdr *resource_hdr, void *resource_value)
  967. {
  968. struct cvp_hfi_cmd_sys_set_resource_packet *pkt;
  969. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  970. int rc = 0;
  971. if (!device || !resource_hdr || !resource_value) {
  972. dprintk(CVP_ERR, "set_res: Invalid Params\n");
  973. return -EINVAL;
  974. }
  975. pkt = (struct cvp_hfi_cmd_sys_set_resource_packet *) packet;
  976. rc = call_hfi_pkt_op(device, sys_set_resource,
  977. pkt, resource_hdr, resource_value);
  978. if (rc) {
  979. dprintk(CVP_ERR, "set_res: failed to create packet\n");
  980. goto err_create_pkt;
  981. }
  982. rc = __iface_cmdq_write(device, pkt);
  983. if (rc)
  984. rc = -ENOTEMPTY;
  985. err_create_pkt:
  986. return rc;
  987. }
  988. static int __core_release_resource(struct iris_hfi_device *device,
  989. struct cvp_resource_hdr *resource_hdr)
  990. {
  991. struct cvp_hfi_cmd_sys_release_resource_packet *pkt;
  992. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  993. int rc = 0;
  994. if (!device || !resource_hdr) {
  995. dprintk(CVP_ERR, "release_res: Invalid Params\n");
  996. return -EINVAL;
  997. }
  998. pkt = (struct cvp_hfi_cmd_sys_release_resource_packet *) packet;
  999. rc = call_hfi_pkt_op(device, sys_release_resource,
  1000. pkt, resource_hdr);
  1001. if (rc) {
  1002. dprintk(CVP_ERR, "release_res: failed to create packet\n");
  1003. goto err_create_pkt;
  1004. }
  1005. rc = __iface_cmdq_write(device, pkt);
  1006. if (rc)
  1007. rc = -ENOTEMPTY;
  1008. err_create_pkt:
  1009. return rc;
  1010. }
  1011. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state)
  1012. {
  1013. int rc = 0;
  1014. rc = qcom_scm_set_remote_state(state, TZBSP_CVP_PAS_ID);
  1015. dprintk(CVP_CORE, "Set state %d, resp %d\n", state, rc);
  1016. if (rc) {
  1017. dprintk(CVP_ERR, "Failed qcom_scm_set_remote_state %d\n", rc);
  1018. return rc;
  1019. }
  1020. return 0;
  1021. }
  1022. static inline int __boot_firmware(struct iris_hfi_device *device)
  1023. {
  1024. int rc = 0, loop = 10;
  1025. u32 ctrl_init_val = 0, ctrl_status = 0, count = 0, max_tries = 1000;
  1026. u32 reg_gdsc;
  1027. /*
  1028. * Hand off control of regulators to h/w _after_ enabling clocks.
  1029. * Note that the GDSC will turn off when switching from normal
  1030. * (s/w triggered) to fast (HW triggered) unless the h/w vote is
  1031. * present. Since Iris isn't up yet, the GDSC will be off briefly.
  1032. */
  1033. if (__enable_hw_power_collapse(device))
  1034. dprintk(CVP_ERR, "Failed to enabled inter-frame PC\n");
  1035. while (loop) {
  1036. reg_gdsc = __read_register(device, CVP_CC_MVS1_GDSCR);
  1037. if (reg_gdsc & 0x80000000) {
  1038. usleep_range(100, 200);
  1039. loop--;
  1040. } else {
  1041. break;
  1042. }
  1043. }
  1044. if (!loop)
  1045. dprintk(CVP_ERR, "fail to power off CORE during resume\n");
  1046. ctrl_init_val = BIT(0);
  1047. __write_register(device, CVP_CTRL_INIT, ctrl_init_val);
  1048. while (!ctrl_status && count < max_tries) {
  1049. ctrl_status = __read_register(device, CVP_CTRL_STATUS);
  1050. if ((ctrl_status & CVP_CTRL_ERROR_STATUS__M) == 0x4) {
  1051. dprintk(CVP_ERR, "invalid setting for UC_REGION\n");
  1052. rc = -ENODATA;
  1053. break;
  1054. }
  1055. /* Reduce to 1/100th and x100 of max_tries */
  1056. usleep_range(500, 1000);
  1057. count++;
  1058. }
  1059. if (!(ctrl_status & CVP_CTRL_INIT_STATUS__M)) {
  1060. dprintk(CVP_ERR, "Failed to boot FW status: %x\n",
  1061. ctrl_status);
  1062. rc = -ENODEV;
  1063. }
  1064. /* Enable interrupt before sending commands to tensilica */
  1065. __write_register(device, CVP_CPU_CS_H2XSOFTINTEN, 0x1);
  1066. __write_register(device, CVP_CPU_CS_X2RPMh, 0x0);
  1067. return rc;
  1068. }
  1069. static int iris_hfi_resume(void *dev)
  1070. {
  1071. int rc = 0;
  1072. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1073. if (!device) {
  1074. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1075. return -EINVAL;
  1076. }
  1077. dprintk(CVP_CORE, "Resuming Iris\n");
  1078. mutex_lock(&device->lock);
  1079. rc = __resume(device);
  1080. mutex_unlock(&device->lock);
  1081. return rc;
  1082. }
  1083. static int iris_hfi_suspend(void *dev)
  1084. {
  1085. int rc = 0;
  1086. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1087. if (!device) {
  1088. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1089. return -EINVAL;
  1090. } else if (!device->res->sw_power_collapsible) {
  1091. return -ENOTSUPP;
  1092. }
  1093. dprintk(CVP_CORE, "Suspending Iris\n");
  1094. mutex_lock(&device->lock);
  1095. rc = __power_collapse(device, true);
  1096. if (rc) {
  1097. dprintk(CVP_WARN, "%s: Iris is busy\n", __func__);
  1098. rc = -EBUSY;
  1099. }
  1100. mutex_unlock(&device->lock);
  1101. /* Cancel pending delayed works if any */
  1102. if (!rc)
  1103. cancel_delayed_work(&iris_hfi_pm_work);
  1104. return rc;
  1105. }
  1106. static void cvp_dump_csr(struct iris_hfi_device *dev)
  1107. {
  1108. u32 reg;
  1109. if (!dev)
  1110. return;
  1111. if (!dev->power_enabled || dev->reg_dumped)
  1112. return;
  1113. reg = __read_register(dev, CVP_WRAPPER_CPU_STATUS);
  1114. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_STATUS: %x\n", reg);
  1115. reg = __read_register(dev, CVP_CPU_CS_SCIACMDARG0);
  1116. dprintk(CVP_ERR, "CVP_CPU_CS_SCIACMDARG0: %x\n", reg);
  1117. reg = __read_register(dev, CVP_WRAPPER_CPU_CLOCK_CONFIG);
  1118. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_CLOCK_CONFIG: %x\n", reg);
  1119. reg = __read_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  1120. dprintk(CVP_ERR, "CVP_WRAPPER_CORE_CLOCK_CONFIG: %x\n", reg);
  1121. reg = __read_register(dev, CVP_WRAPPER_INTR_STATUS);
  1122. dprintk(CVP_ERR, "CVP_WRAPPER_INTR_STATUS: %x\n", reg);
  1123. reg = __read_register(dev, CVP_CPU_CS_H2ASOFTINT);
  1124. dprintk(CVP_ERR, "CVP_CPU_CS_H2ASOFTINT: %x\n", reg);
  1125. reg = __read_register(dev, CVP_CPU_CS_A2HSOFTINT);
  1126. dprintk(CVP_ERR, "CVP_CPU_CS_A2HSOFTINT: %x\n", reg);
  1127. reg = __read_register(dev, CVP_CC_MVS1C_GDSCR);
  1128. dprintk(CVP_ERR, "CVP_CC_MVS1C_GDSCR: %x\n", reg);
  1129. reg = __read_register(dev, CVP_CC_MVS1C_CBCR);
  1130. dprintk(CVP_ERR, "CVP_CC_MVS1C_CBCR: %x\n", reg);
  1131. dev->reg_dumped = true;
  1132. }
  1133. static int iris_hfi_flush_debug_queue(void *dev)
  1134. {
  1135. int rc = 0;
  1136. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1137. if (!device) {
  1138. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1139. return -EINVAL;
  1140. }
  1141. cvp_dump_csr(device);
  1142. mutex_lock(&device->lock);
  1143. if (!device->power_enabled) {
  1144. dprintk(CVP_WARN, "%s: iris power off\n", __func__);
  1145. rc = -EINVAL;
  1146. goto exit;
  1147. }
  1148. __flush_debug_queue(device, NULL);
  1149. exit:
  1150. mutex_unlock(&device->lock);
  1151. return rc;
  1152. }
  1153. static int __set_clocks(struct iris_hfi_device *device, u32 freq)
  1154. {
  1155. struct clock_info *cl;
  1156. int rc = 0;
  1157. int factorsrc2clk = 3; // ratio factor for clock source : clk
  1158. dprintk(CVP_PWR, "%s: entering with freq : %ld\n", __func__, freq);
  1159. iris_hfi_for_each_clock(device, cl) {
  1160. if (cl->has_scaling) {/* has_scaling */
  1161. device->clk_freq = freq;
  1162. if (msm_cvp_clock_voting)
  1163. freq = msm_cvp_clock_voting;
  1164. freq = freq * factorsrc2clk;
  1165. dprintk(CVP_PWR, "%s: clock source rate set to: %ld\n", __func__, freq);
  1166. rc = clk_set_rate(cl->clk, freq);
  1167. if (rc) {
  1168. dprintk(CVP_ERR,
  1169. "Failed to set clock rate %u %s: %d %s\n",
  1170. freq, cl->name, rc, __func__);
  1171. return rc;
  1172. }
  1173. dprintk(CVP_PWR, "Scaling clock %s to %u\n",
  1174. cl->name, freq);
  1175. }
  1176. }
  1177. return 0;
  1178. }
  1179. static int iris_hfi_scale_clocks(void *dev, u32 freq)
  1180. {
  1181. int rc = 0;
  1182. struct iris_hfi_device *device = dev;
  1183. if (!device) {
  1184. dprintk(CVP_ERR, "Invalid args: %pK\n", device);
  1185. return -EINVAL;
  1186. }
  1187. mutex_lock(&device->lock);
  1188. if (__resume(device)) {
  1189. dprintk(CVP_ERR, "Resume from power collapse failed\n");
  1190. rc = -ENODEV;
  1191. goto exit;
  1192. }
  1193. rc = __set_clocks(device, freq);
  1194. exit:
  1195. mutex_unlock(&device->lock);
  1196. return rc;
  1197. }
  1198. static int __scale_clocks(struct iris_hfi_device *device)
  1199. {
  1200. int rc = 0;
  1201. struct allowed_clock_rates_table *allowed_clks_tbl = NULL;
  1202. u32 rate = 0;
  1203. allowed_clks_tbl = device->res->allowed_clks_tbl;
  1204. rate = device->clk_freq ? device->clk_freq :
  1205. allowed_clks_tbl[0].clock_rate;
  1206. dprintk(CVP_PWR, "%s: scale clock rate %d\n", __func__, rate);
  1207. rc = __set_clocks(device, rate);
  1208. return rc;
  1209. }
  1210. /* Writes into cmdq without raising an interrupt */
  1211. static int __iface_cmdq_write_relaxed(struct iris_hfi_device *device,
  1212. void *pkt, bool *requires_interrupt)
  1213. {
  1214. struct cvp_iface_q_info *q_info;
  1215. struct cvp_hal_cmd_pkt_hdr *cmd_packet;
  1216. int result = -E2BIG;
  1217. if (!device || !pkt) {
  1218. dprintk(CVP_ERR, "Invalid Params\n");
  1219. return -EINVAL;
  1220. }
  1221. __strict_check(device);
  1222. if (!__core_in_valid_state(device)) {
  1223. dprintk(CVP_ERR, "%s - fw not in init state\n", __func__);
  1224. result = -EINVAL;
  1225. goto err_q_null;
  1226. }
  1227. cmd_packet = (struct cvp_hal_cmd_pkt_hdr *)pkt;
  1228. device->last_packet_type = cmd_packet->packet_type;
  1229. q_info = &device->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1230. if (!q_info) {
  1231. dprintk(CVP_ERR, "cannot write to shared Q's\n");
  1232. goto err_q_null;
  1233. }
  1234. if (!q_info->q_array.align_virtual_addr) {
  1235. dprintk(CVP_ERR, "cannot write to shared CMD Q's\n");
  1236. result = -ENODATA;
  1237. goto err_q_null;
  1238. }
  1239. if (__resume(device)) {
  1240. dprintk(CVP_ERR, "%s: Power on failed\n", __func__);
  1241. goto err_q_write;
  1242. }
  1243. if (!__write_queue(q_info, (u8 *)pkt, requires_interrupt)) {
  1244. if (device->res->sw_power_collapsible) {
  1245. cancel_delayed_work(&iris_hfi_pm_work);
  1246. if (!queue_delayed_work(device->iris_pm_workq,
  1247. &iris_hfi_pm_work,
  1248. msecs_to_jiffies(
  1249. device->res->msm_cvp_pwr_collapse_delay))) {
  1250. dprintk(CVP_PWR,
  1251. "PM work already scheduled\n");
  1252. }
  1253. }
  1254. result = 0;
  1255. } else {
  1256. dprintk(CVP_ERR, "__iface_cmdq_write: queue full\n");
  1257. }
  1258. err_q_write:
  1259. err_q_null:
  1260. return result;
  1261. }
  1262. static int __iface_cmdq_write(struct iris_hfi_device *device, void *pkt)
  1263. {
  1264. bool needs_interrupt = false;
  1265. int rc = __iface_cmdq_write_relaxed(device, pkt, &needs_interrupt);
  1266. if (!rc && needs_interrupt) {
  1267. /* Consumer of cmdq prefers that we raise an interrupt */
  1268. rc = 0;
  1269. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1270. }
  1271. return rc;
  1272. }
  1273. static int __iface_msgq_read(struct iris_hfi_device *device, void *pkt)
  1274. {
  1275. u32 tx_req_is_set = 0;
  1276. int rc = 0;
  1277. struct cvp_iface_q_info *q_info;
  1278. if (!pkt) {
  1279. dprintk(CVP_ERR, "Invalid Params\n");
  1280. return -EINVAL;
  1281. }
  1282. __strict_check(device);
  1283. if (!__core_in_valid_state(device)) {
  1284. dprintk(CVP_WARN, "%s - fw not in init state\n", __func__);
  1285. rc = -EINVAL;
  1286. goto read_error_null;
  1287. }
  1288. q_info = &device->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1289. if (q_info->q_array.align_virtual_addr == NULL) {
  1290. dprintk(CVP_ERR, "cannot read from shared MSG Q's\n");
  1291. rc = -ENODATA;
  1292. goto read_error_null;
  1293. }
  1294. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1295. if (tx_req_is_set)
  1296. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1297. rc = 0;
  1298. } else
  1299. rc = -ENODATA;
  1300. read_error_null:
  1301. return rc;
  1302. }
  1303. static int __iface_dbgq_read(struct iris_hfi_device *device, void *pkt)
  1304. {
  1305. u32 tx_req_is_set = 0;
  1306. int rc = 0;
  1307. struct cvp_iface_q_info *q_info;
  1308. if (!pkt) {
  1309. dprintk(CVP_ERR, "Invalid Params\n");
  1310. return -EINVAL;
  1311. }
  1312. __strict_check(device);
  1313. q_info = &device->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1314. if (q_info->q_array.align_virtual_addr == NULL) {
  1315. dprintk(CVP_ERR, "cannot read from shared DBG Q's\n");
  1316. rc = -ENODATA;
  1317. goto dbg_error_null;
  1318. }
  1319. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1320. if (tx_req_is_set)
  1321. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1322. rc = 0;
  1323. } else
  1324. rc = -ENODATA;
  1325. dbg_error_null:
  1326. return rc;
  1327. }
  1328. static void __set_queue_hdr_defaults(struct cvp_hfi_queue_header *q_hdr)
  1329. {
  1330. q_hdr->qhdr_status = 0x1;
  1331. q_hdr->qhdr_type = CVP_IFACEQ_DFLT_QHDR;
  1332. q_hdr->qhdr_q_size = CVP_IFACEQ_QUEUE_SIZE / 4;
  1333. q_hdr->qhdr_pkt_size = 0;
  1334. q_hdr->qhdr_rx_wm = 0x1;
  1335. q_hdr->qhdr_tx_wm = 0x1;
  1336. q_hdr->qhdr_rx_req = 0x1;
  1337. q_hdr->qhdr_tx_req = 0x0;
  1338. q_hdr->qhdr_rx_irq_status = 0x0;
  1339. q_hdr->qhdr_tx_irq_status = 0x0;
  1340. q_hdr->qhdr_read_idx = 0x0;
  1341. q_hdr->qhdr_write_idx = 0x0;
  1342. }
  1343. static void __interface_dsp_queues_release(struct iris_hfi_device *device)
  1344. {
  1345. int i;
  1346. struct msm_cvp_smem *mem_data = &device->dsp_iface_q_table.mem_data;
  1347. struct context_bank_info *cb = mem_data->mapping_info.cb_info;
  1348. if (!device->dsp_iface_q_table.align_virtual_addr) {
  1349. dprintk(CVP_ERR, "%s: already released\n", __func__);
  1350. return;
  1351. }
  1352. dma_unmap_single_attrs(cb->dev, mem_data->device_addr,
  1353. mem_data->size, DMA_BIDIRECTIONAL, 0);
  1354. dma_free_coherent(device->res->mem_cdsp.dev, mem_data->size,
  1355. mem_data->kvaddr, mem_data->dma_handle);
  1356. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1357. device->dsp_iface_queues[i].q_hdr = NULL;
  1358. device->dsp_iface_queues[i].q_array.align_virtual_addr = NULL;
  1359. device->dsp_iface_queues[i].q_array.align_device_addr = 0;
  1360. }
  1361. device->dsp_iface_q_table.align_virtual_addr = NULL;
  1362. device->dsp_iface_q_table.align_device_addr = 0;
  1363. }
  1364. static int __interface_dsp_queues_init(struct iris_hfi_device *dev)
  1365. {
  1366. int rc = 0;
  1367. u32 i;
  1368. struct cvp_iface_q_info *iface_q;
  1369. int offset = 0;
  1370. phys_addr_t fw_bias = 0;
  1371. size_t q_size;
  1372. struct msm_cvp_smem *mem_data;
  1373. void *kvaddr;
  1374. dma_addr_t dma_handle;
  1375. dma_addr_t iova;
  1376. struct context_bank_info *cb;
  1377. q_size = ALIGN(QUEUE_SIZE, SZ_1M);
  1378. mem_data = &dev->dsp_iface_q_table.mem_data;
  1379. /* Allocate dsp queues from CDSP device memory */
  1380. kvaddr = dma_alloc_coherent(dev->res->mem_cdsp.dev, q_size,
  1381. &dma_handle, GFP_KERNEL);
  1382. if (IS_ERR_OR_NULL(kvaddr)) {
  1383. dprintk(CVP_ERR, "%s: failed dma allocation\n", __func__);
  1384. goto fail_dma_alloc;
  1385. }
  1386. cb = msm_cvp_smem_get_context_bank(dev->res, 0);
  1387. if (!cb) {
  1388. dprintk(CVP_ERR,
  1389. "%s: failed to get context bank\n", __func__);
  1390. goto fail_dma_map;
  1391. }
  1392. iova = dma_map_single_attrs(cb->dev, phys_to_virt(dma_handle),
  1393. q_size, DMA_BIDIRECTIONAL, 0);
  1394. if (dma_mapping_error(cb->dev, iova)) {
  1395. dprintk(CVP_ERR, "%s: failed dma mapping\n", __func__);
  1396. goto fail_dma_map;
  1397. }
  1398. dprintk(CVP_DSP,
  1399. "%s: kvaddr %pK dma_handle %#llx iova %#llx size %zd\n",
  1400. __func__, kvaddr, dma_handle, iova, q_size);
  1401. memset(mem_data, 0, sizeof(struct msm_cvp_smem));
  1402. mem_data->kvaddr = kvaddr;
  1403. mem_data->device_addr = iova;
  1404. mem_data->dma_handle = dma_handle;
  1405. mem_data->size = q_size;
  1406. mem_data->mapping_info.cb_info = cb;
  1407. if (!is_iommu_present(dev->res))
  1408. fw_bias = dev->cvp_hal_data->firmware_base;
  1409. dev->dsp_iface_q_table.align_virtual_addr = kvaddr;
  1410. dev->dsp_iface_q_table.align_device_addr = iova - fw_bias;
  1411. dev->dsp_iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1412. offset = dev->dsp_iface_q_table.mem_size;
  1413. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1414. iface_q = &dev->dsp_iface_queues[i];
  1415. iface_q->q_array.align_device_addr = iova + offset - fw_bias;
  1416. iface_q->q_array.align_virtual_addr = kvaddr + offset;
  1417. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1418. offset += iface_q->q_array.mem_size;
  1419. spin_lock_init(&iface_q->hfi_lock);
  1420. }
  1421. cvp_dsp_init_hfi_queue_hdr(dev);
  1422. return rc;
  1423. fail_dma_map:
  1424. dma_free_coherent(dev->res->mem_cdsp.dev, q_size, kvaddr, dma_handle);
  1425. fail_dma_alloc:
  1426. return -ENOMEM;
  1427. }
  1428. static void __interface_queues_release(struct iris_hfi_device *device)
  1429. {
  1430. int i;
  1431. struct cvp_hfi_mem_map_table *qdss;
  1432. struct cvp_hfi_mem_map *mem_map;
  1433. int num_entries = device->res->qdss_addr_set.count;
  1434. unsigned long mem_map_table_base_addr;
  1435. struct context_bank_info *cb;
  1436. if (device->qdss.align_virtual_addr) {
  1437. qdss = (struct cvp_hfi_mem_map_table *)
  1438. device->qdss.align_virtual_addr;
  1439. qdss->mem_map_num_entries = num_entries;
  1440. mem_map_table_base_addr =
  1441. device->qdss.align_device_addr +
  1442. sizeof(struct cvp_hfi_mem_map_table);
  1443. qdss->mem_map_table_base_addr =
  1444. (u32)mem_map_table_base_addr;
  1445. if ((unsigned long)qdss->mem_map_table_base_addr !=
  1446. mem_map_table_base_addr) {
  1447. dprintk(CVP_ERR,
  1448. "Invalid mem_map_table_base_addr %#lx",
  1449. mem_map_table_base_addr);
  1450. }
  1451. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1452. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1453. for (i = 0; cb && i < num_entries; i++) {
  1454. iommu_unmap(cb->domain,
  1455. mem_map[i].virtual_addr,
  1456. mem_map[i].size);
  1457. }
  1458. __smem_free(device, &device->qdss.mem_data);
  1459. }
  1460. __smem_free(device, &device->iface_q_table.mem_data);
  1461. __smem_free(device, &device->sfr.mem_data);
  1462. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1463. device->iface_queues[i].q_hdr = NULL;
  1464. device->iface_queues[i].q_array.align_virtual_addr = NULL;
  1465. device->iface_queues[i].q_array.align_device_addr = 0;
  1466. }
  1467. device->iface_q_table.align_virtual_addr = NULL;
  1468. device->iface_q_table.align_device_addr = 0;
  1469. device->qdss.align_virtual_addr = NULL;
  1470. device->qdss.align_device_addr = 0;
  1471. device->sfr.align_virtual_addr = NULL;
  1472. device->sfr.align_device_addr = 0;
  1473. device->mem_addr.align_virtual_addr = NULL;
  1474. device->mem_addr.align_device_addr = 0;
  1475. __interface_dsp_queues_release(device);
  1476. }
  1477. static int __get_qdss_iommu_virtual_addr(struct iris_hfi_device *dev,
  1478. struct cvp_hfi_mem_map *mem_map,
  1479. struct iommu_domain *domain)
  1480. {
  1481. int i;
  1482. int rc = 0;
  1483. dma_addr_t iova = QDSS_IOVA_START;
  1484. int num_entries = dev->res->qdss_addr_set.count;
  1485. struct addr_range *qdss_addr_tbl = dev->res->qdss_addr_set.addr_tbl;
  1486. if (!num_entries)
  1487. return -ENODATA;
  1488. for (i = 0; i < num_entries; i++) {
  1489. if (domain) {
  1490. rc = iommu_map(domain, iova,
  1491. qdss_addr_tbl[i].start,
  1492. qdss_addr_tbl[i].size,
  1493. IOMMU_READ | IOMMU_WRITE);
  1494. if (rc) {
  1495. dprintk(CVP_ERR,
  1496. "IOMMU QDSS mapping failed for addr %#x\n",
  1497. qdss_addr_tbl[i].start);
  1498. rc = -ENOMEM;
  1499. break;
  1500. }
  1501. } else {
  1502. iova = qdss_addr_tbl[i].start;
  1503. }
  1504. mem_map[i].virtual_addr = (u32)iova;
  1505. mem_map[i].physical_addr = qdss_addr_tbl[i].start;
  1506. mem_map[i].size = qdss_addr_tbl[i].size;
  1507. mem_map[i].attr = 0x0;
  1508. iova += mem_map[i].size;
  1509. }
  1510. if (i < num_entries) {
  1511. dprintk(CVP_ERR,
  1512. "QDSS mapping failed, Freeing other entries %d\n", i);
  1513. for (--i; domain && i >= 0; i--) {
  1514. iommu_unmap(domain,
  1515. mem_map[i].virtual_addr,
  1516. mem_map[i].size);
  1517. }
  1518. }
  1519. return rc;
  1520. }
  1521. static void __setup_ucregion_memory_map(struct iris_hfi_device *device)
  1522. {
  1523. __write_register(device, CVP_UC_REGION_ADDR,
  1524. (u32)device->iface_q_table.align_device_addr);
  1525. __write_register(device, CVP_UC_REGION_SIZE, SHARED_QSIZE);
  1526. __write_register(device, CVP_QTBL_ADDR,
  1527. (u32)device->iface_q_table.align_device_addr);
  1528. __write_register(device, CVP_QTBL_INFO, 0x01);
  1529. if (device->sfr.align_device_addr)
  1530. __write_register(device, CVP_SFR_ADDR,
  1531. (u32)device->sfr.align_device_addr);
  1532. if (device->qdss.align_device_addr)
  1533. __write_register(device, CVP_MMAP_ADDR,
  1534. (u32)device->qdss.align_device_addr);
  1535. call_iris_op(device, setup_dsp_uc_memmap, device);
  1536. }
  1537. static int __interface_queues_init(struct iris_hfi_device *dev)
  1538. {
  1539. struct cvp_hfi_queue_table_header *q_tbl_hdr;
  1540. struct cvp_hfi_queue_header *q_hdr;
  1541. u32 i;
  1542. int rc = 0;
  1543. struct cvp_hfi_mem_map_table *qdss;
  1544. struct cvp_hfi_mem_map *mem_map;
  1545. struct cvp_iface_q_info *iface_q;
  1546. struct cvp_hfi_sfr_struct *vsfr;
  1547. struct cvp_mem_addr *mem_addr;
  1548. int offset = 0;
  1549. int num_entries = dev->res->qdss_addr_set.count;
  1550. phys_addr_t fw_bias = 0;
  1551. size_t q_size;
  1552. unsigned long mem_map_table_base_addr;
  1553. struct context_bank_info *cb;
  1554. q_size = SHARED_QSIZE - ALIGNED_SFR_SIZE - ALIGNED_QDSS_SIZE;
  1555. mem_addr = &dev->mem_addr;
  1556. if (!is_iommu_present(dev->res))
  1557. fw_bias = dev->cvp_hal_data->firmware_base;
  1558. rc = __smem_alloc(dev, mem_addr, q_size, 1, SMEM_UNCACHED);
  1559. if (rc) {
  1560. dprintk(CVP_ERR, "iface_q_table_alloc_fail\n");
  1561. goto fail_alloc_queue;
  1562. }
  1563. dev->iface_q_table.align_virtual_addr = mem_addr->align_virtual_addr;
  1564. dev->iface_q_table.align_device_addr = mem_addr->align_device_addr -
  1565. fw_bias;
  1566. dev->iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1567. dev->iface_q_table.mem_data = mem_addr->mem_data;
  1568. offset += dev->iface_q_table.mem_size;
  1569. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1570. iface_q = &dev->iface_queues[i];
  1571. iface_q->q_array.align_device_addr = mem_addr->align_device_addr
  1572. + offset - fw_bias;
  1573. iface_q->q_array.align_virtual_addr =
  1574. mem_addr->align_virtual_addr + offset;
  1575. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1576. offset += iface_q->q_array.mem_size;
  1577. iface_q->q_hdr = CVP_IFACEQ_GET_QHDR_START_ADDR(
  1578. dev->iface_q_table.align_virtual_addr, i);
  1579. __set_queue_hdr_defaults(iface_q->q_hdr);
  1580. spin_lock_init(&iface_q->hfi_lock);
  1581. }
  1582. if ((msm_cvp_fw_debug_mode & HFI_DEBUG_MODE_QDSS) && num_entries) {
  1583. rc = __smem_alloc(dev, mem_addr, ALIGNED_QDSS_SIZE, 1,
  1584. SMEM_UNCACHED);
  1585. if (rc) {
  1586. dprintk(CVP_WARN,
  1587. "qdss_alloc_fail: QDSS messages logging will not work\n");
  1588. dev->qdss.align_device_addr = 0;
  1589. } else {
  1590. dev->qdss.align_device_addr =
  1591. mem_addr->align_device_addr - fw_bias;
  1592. dev->qdss.align_virtual_addr =
  1593. mem_addr->align_virtual_addr;
  1594. dev->qdss.mem_size = ALIGNED_QDSS_SIZE;
  1595. dev->qdss.mem_data = mem_addr->mem_data;
  1596. }
  1597. }
  1598. rc = __smem_alloc(dev, mem_addr, ALIGNED_SFR_SIZE, 1, SMEM_UNCACHED);
  1599. if (rc) {
  1600. dprintk(CVP_WARN, "sfr_alloc_fail: SFR not will work\n");
  1601. dev->sfr.align_device_addr = 0;
  1602. } else {
  1603. dev->sfr.align_device_addr = mem_addr->align_device_addr -
  1604. fw_bias;
  1605. dev->sfr.align_virtual_addr = mem_addr->align_virtual_addr;
  1606. dev->sfr.mem_size = ALIGNED_SFR_SIZE;
  1607. dev->sfr.mem_data = mem_addr->mem_data;
  1608. }
  1609. q_tbl_hdr = (struct cvp_hfi_queue_table_header *)
  1610. dev->iface_q_table.align_virtual_addr;
  1611. q_tbl_hdr->qtbl_version = 0;
  1612. q_tbl_hdr->device_addr = (void *)dev;
  1613. strlcpy(q_tbl_hdr->name, "msm_cvp", sizeof(q_tbl_hdr->name));
  1614. q_tbl_hdr->qtbl_size = CVP_IFACEQ_TABLE_SIZE;
  1615. q_tbl_hdr->qtbl_qhdr0_offset =
  1616. sizeof(struct cvp_hfi_queue_table_header);
  1617. q_tbl_hdr->qtbl_qhdr_size = sizeof(struct cvp_hfi_queue_header);
  1618. q_tbl_hdr->qtbl_num_q = CVP_IFACEQ_NUMQ;
  1619. q_tbl_hdr->qtbl_num_active_q = CVP_IFACEQ_NUMQ;
  1620. iface_q = &dev->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1621. q_hdr = iface_q->q_hdr;
  1622. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1623. q_hdr->qhdr_type |= HFI_Q_ID_HOST_TO_CTRL_CMD_Q;
  1624. iface_q = &dev->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1625. q_hdr = iface_q->q_hdr;
  1626. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1627. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_MSG_Q;
  1628. iface_q = &dev->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1629. q_hdr = iface_q->q_hdr;
  1630. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1631. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q;
  1632. /*
  1633. * Set receive request to zero on debug queue as there is no
  1634. * need of interrupt from cvp hardware for debug messages
  1635. */
  1636. q_hdr->qhdr_rx_req = 0;
  1637. if (dev->qdss.align_virtual_addr) {
  1638. qdss =
  1639. (struct cvp_hfi_mem_map_table *)dev->qdss.align_virtual_addr;
  1640. qdss->mem_map_num_entries = num_entries;
  1641. mem_map_table_base_addr = dev->qdss.align_device_addr +
  1642. sizeof(struct cvp_hfi_mem_map_table);
  1643. qdss->mem_map_table_base_addr = mem_map_table_base_addr;
  1644. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1645. cb = msm_cvp_smem_get_context_bank(dev->res, 0);
  1646. if (!cb) {
  1647. dprintk(CVP_ERR,
  1648. "%s: failed to get context bank\n", __func__);
  1649. return -EINVAL;
  1650. }
  1651. rc = __get_qdss_iommu_virtual_addr(dev, mem_map, cb->domain);
  1652. if (rc) {
  1653. dprintk(CVP_ERR,
  1654. "IOMMU mapping failed, Freeing qdss memdata\n");
  1655. __smem_free(dev, &dev->qdss.mem_data);
  1656. dev->qdss.align_virtual_addr = NULL;
  1657. dev->qdss.align_device_addr = 0;
  1658. }
  1659. }
  1660. vsfr = (struct cvp_hfi_sfr_struct *) dev->sfr.align_virtual_addr;
  1661. if (vsfr)
  1662. vsfr->bufSize = ALIGNED_SFR_SIZE;
  1663. rc = __interface_dsp_queues_init(dev);
  1664. if (rc) {
  1665. dprintk(CVP_ERR, "dsp_queues_init failed\n");
  1666. goto fail_alloc_queue;
  1667. }
  1668. __setup_ucregion_memory_map(dev);
  1669. return 0;
  1670. fail_alloc_queue:
  1671. return -ENOMEM;
  1672. }
  1673. static int __sys_set_debug(struct iris_hfi_device *device, u32 debug)
  1674. {
  1675. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1676. int rc = 0;
  1677. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1678. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1679. rc = call_hfi_pkt_op(device, sys_debug_config, pkt, debug);
  1680. if (rc) {
  1681. dprintk(CVP_WARN,
  1682. "Debug mode setting to FW failed\n");
  1683. return -ENOTEMPTY;
  1684. }
  1685. if (__iface_cmdq_write(device, pkt))
  1686. return -ENOTEMPTY;
  1687. return 0;
  1688. }
  1689. static int __sys_set_idle_indicator(struct iris_hfi_device *device,
  1690. bool enable)
  1691. {
  1692. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1693. int rc = 0;
  1694. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1695. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1696. rc = call_hfi_pkt_op(device, sys_set_idle_indicator, pkt, enable);
  1697. if (__iface_cmdq_write(device, pkt))
  1698. return -ENOTEMPTY;
  1699. return 0;
  1700. }
  1701. static int __sys_set_coverage(struct iris_hfi_device *device, u32 mode)
  1702. {
  1703. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1704. int rc = 0;
  1705. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1706. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1707. rc = call_hfi_pkt_op(device, sys_coverage_config,
  1708. pkt, mode);
  1709. if (rc) {
  1710. dprintk(CVP_WARN,
  1711. "Coverage mode setting to FW failed\n");
  1712. return -ENOTEMPTY;
  1713. }
  1714. if (__iface_cmdq_write(device, pkt)) {
  1715. dprintk(CVP_WARN, "Failed to send coverage pkt to f/w\n");
  1716. return -ENOTEMPTY;
  1717. }
  1718. return 0;
  1719. }
  1720. static int __sys_set_power_control(struct iris_hfi_device *device,
  1721. bool enable)
  1722. {
  1723. struct regulator_info *rinfo;
  1724. bool supported = false;
  1725. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1726. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1727. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1728. iris_hfi_for_each_regulator(device, rinfo) {
  1729. if (rinfo->has_hw_power_collapse) {
  1730. supported = true;
  1731. break;
  1732. }
  1733. }
  1734. if (!supported)
  1735. return 0;
  1736. call_hfi_pkt_op(device, sys_power_control, pkt, enable);
  1737. if (__iface_cmdq_write(device, pkt))
  1738. return -ENOTEMPTY;
  1739. return 0;
  1740. }
  1741. static int iris_hfi_core_init(void *device)
  1742. {
  1743. int rc = 0;
  1744. u32 ipcc_iova;
  1745. struct cvp_hfi_cmd_sys_init_packet pkt;
  1746. struct cvp_hfi_cmd_sys_get_property_packet version_pkt;
  1747. struct iris_hfi_device *dev;
  1748. if (!device) {
  1749. dprintk(CVP_ERR, "Invalid device\n");
  1750. return -ENODEV;
  1751. }
  1752. dev = device;
  1753. dprintk(CVP_CORE, "Core initializing\n");
  1754. mutex_lock(&dev->lock);
  1755. dev->bus_vote.data =
  1756. kzalloc(sizeof(struct cvp_bus_vote_data), GFP_KERNEL);
  1757. if (!dev->bus_vote.data) {
  1758. dprintk(CVP_ERR, "Bus vote data memory is not allocated\n");
  1759. rc = -ENOMEM;
  1760. goto err_no_mem;
  1761. }
  1762. dev->bus_vote.data_count = 1;
  1763. dev->bus_vote.data->power_mode = CVP_POWER_TURBO;
  1764. rc = __load_fw(dev);
  1765. if (rc) {
  1766. dprintk(CVP_ERR, "Failed to load Iris FW\n");
  1767. goto err_load_fw;
  1768. }
  1769. __set_state(dev, IRIS_STATE_INIT);
  1770. dev->reg_dumped = false;
  1771. dprintk(CVP_CORE, "Dev_Virt: %pa, Reg_Virt: %pK\n",
  1772. &dev->cvp_hal_data->firmware_base,
  1773. dev->cvp_hal_data->register_base);
  1774. rc = __interface_queues_init(dev);
  1775. if (rc) {
  1776. dprintk(CVP_ERR, "failed to init queues\n");
  1777. rc = -ENOMEM;
  1778. goto err_core_init;
  1779. }
  1780. rc = msm_cvp_map_ipcc_regs(&ipcc_iova);
  1781. if (!rc) {
  1782. dprintk(CVP_CORE, "IPCC iova 0x%x\n", ipcc_iova);
  1783. __write_register(dev, CVP_MMAP_ADDR, ipcc_iova);
  1784. }
  1785. rc = __boot_firmware(dev);
  1786. if (rc) {
  1787. dprintk(CVP_ERR, "Failed to start core\n");
  1788. rc = -ENODEV;
  1789. goto err_core_init;
  1790. }
  1791. dev->version = __read_register(dev, CVP_VERSION_INFO);
  1792. rc = call_hfi_pkt_op(dev, sys_init, &pkt, 0);
  1793. if (rc) {
  1794. dprintk(CVP_ERR, "Failed to create sys init pkt\n");
  1795. goto err_core_init;
  1796. }
  1797. if (__iface_cmdq_write(dev, &pkt)) {
  1798. rc = -ENOTEMPTY;
  1799. goto err_core_init;
  1800. }
  1801. rc = call_hfi_pkt_op(dev, sys_image_version, &version_pkt);
  1802. if (rc || __iface_cmdq_write(dev, &version_pkt))
  1803. dprintk(CVP_WARN, "Failed to send image version pkt to f/w\n");
  1804. __sys_set_debug(device, msm_cvp_fw_debug);
  1805. __enable_subcaches(device);
  1806. __set_subcaches(device);
  1807. __set_ubwc_config(device);
  1808. __sys_set_idle_indicator(device, true);
  1809. if (dev->res->pm_qos_latency_us)
  1810. cpu_latency_qos_add_request(&dev->qos,
  1811. dev->res->pm_qos_latency_us);
  1812. mutex_unlock(&dev->lock);
  1813. cvp_dsp_send_hfi_queue();
  1814. dprintk(CVP_CORE, "Core inited successfully\n");
  1815. return 0;
  1816. err_core_init:
  1817. __set_state(dev, IRIS_STATE_DEINIT);
  1818. __unload_fw(dev);
  1819. err_load_fw:
  1820. err_no_mem:
  1821. dprintk(CVP_ERR, "Core init failed\n");
  1822. mutex_unlock(&dev->lock);
  1823. return rc;
  1824. }
  1825. static int iris_hfi_core_release(void *dev)
  1826. {
  1827. int rc = 0;
  1828. struct iris_hfi_device *device = dev;
  1829. struct cvp_hal_session *session, *next;
  1830. if (!device) {
  1831. dprintk(CVP_ERR, "invalid device\n");
  1832. return -ENODEV;
  1833. }
  1834. mutex_lock(&device->lock);
  1835. dprintk(CVP_WARN, "Core releasing\n");
  1836. if (device->res->pm_qos_latency_us &&
  1837. cpu_latency_qos_request_active(&device->qos))
  1838. cpu_latency_qos_remove_request(&device->qos);
  1839. __resume(device);
  1840. __set_state(device, IRIS_STATE_DEINIT);
  1841. __dsp_shutdown(device, 0);
  1842. __unload_fw(device);
  1843. /* unlink all sessions from device */
  1844. list_for_each_entry_safe(session, next, &device->sess_head, list) {
  1845. list_del(&session->list);
  1846. session->device = NULL;
  1847. }
  1848. dprintk(CVP_CORE, "Core released successfully\n");
  1849. mutex_unlock(&device->lock);
  1850. return rc;
  1851. }
  1852. static void __core_clear_interrupt(struct iris_hfi_device *device)
  1853. {
  1854. u32 intr_status = 0, mask = 0;
  1855. if (!device) {
  1856. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  1857. return;
  1858. }
  1859. intr_status = __read_register(device, CVP_WRAPPER_INTR_STATUS);
  1860. mask = (CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK | CVP_FATAL_INTR_BMSK);
  1861. if (intr_status & mask) {
  1862. device->intr_status |= intr_status;
  1863. device->reg_count++;
  1864. dprintk(CVP_CORE,
  1865. "INTERRUPT for device: %pK: times: %d status: %d\n",
  1866. device, device->reg_count, intr_status);
  1867. } else {
  1868. device->spur_count++;
  1869. }
  1870. __write_register(device, CVP_CPU_CS_A2HSOFTINTCLR, 1);
  1871. }
  1872. static int iris_hfi_core_trigger_ssr(void *device,
  1873. enum hal_ssr_trigger_type type)
  1874. {
  1875. struct cvp_hfi_cmd_sys_test_ssr_packet pkt;
  1876. int rc = 0;
  1877. struct iris_hfi_device *dev;
  1878. if (!device) {
  1879. dprintk(CVP_ERR, "invalid device\n");
  1880. return -ENODEV;
  1881. }
  1882. dev = device;
  1883. if (mutex_trylock(&dev->lock)) {
  1884. rc = call_hfi_pkt_op(dev, ssr_cmd, type, &pkt);
  1885. if (rc) {
  1886. dprintk(CVP_ERR, "%s: failed to create packet\n",
  1887. __func__);
  1888. goto err_create_pkt;
  1889. }
  1890. if (__iface_cmdq_write(dev, &pkt))
  1891. rc = -ENOTEMPTY;
  1892. } else {
  1893. return -EAGAIN;
  1894. }
  1895. err_create_pkt:
  1896. mutex_unlock(&dev->lock);
  1897. return rc;
  1898. }
  1899. static void __set_default_sys_properties(struct iris_hfi_device *device)
  1900. {
  1901. if (__sys_set_debug(device, msm_cvp_fw_debug))
  1902. dprintk(CVP_WARN, "Setting fw_debug msg ON failed\n");
  1903. if (__sys_set_power_control(device, msm_cvp_fw_low_power_mode))
  1904. dprintk(CVP_WARN, "Setting h/w power collapse ON failed\n");
  1905. }
  1906. static void __session_clean(struct cvp_hal_session *session)
  1907. {
  1908. struct cvp_hal_session *temp, *next;
  1909. struct iris_hfi_device *device;
  1910. if (!session || !session->device) {
  1911. dprintk(CVP_WARN, "%s: invalid params\n", __func__);
  1912. return;
  1913. }
  1914. device = session->device;
  1915. dprintk(CVP_SESS, "deleted the session: %pK\n", session);
  1916. /*
  1917. * session might have been removed from the device list in
  1918. * core_release, so check and remove if it is in the list
  1919. */
  1920. list_for_each_entry_safe(temp, next, &device->sess_head, list) {
  1921. if (session == temp) {
  1922. list_del(&session->list);
  1923. break;
  1924. }
  1925. }
  1926. /* Poison the session handle with zeros */
  1927. *session = (struct cvp_hal_session){ {0} };
  1928. kfree(session);
  1929. }
  1930. static int iris_hfi_session_clean(void *session)
  1931. {
  1932. struct cvp_hal_session *sess_close;
  1933. struct iris_hfi_device *device;
  1934. if (!session) {
  1935. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  1936. return -EINVAL;
  1937. }
  1938. sess_close = session;
  1939. device = sess_close->device;
  1940. if (!device) {
  1941. dprintk(CVP_ERR, "Invalid device handle %s\n", __func__);
  1942. return -EINVAL;
  1943. }
  1944. mutex_lock(&device->lock);
  1945. __session_clean(sess_close);
  1946. mutex_unlock(&device->lock);
  1947. return 0;
  1948. }
  1949. static int iris_hfi_session_init(void *device, void *session_id,
  1950. void **new_session)
  1951. {
  1952. struct cvp_hfi_cmd_sys_session_init_packet pkt;
  1953. struct iris_hfi_device *dev;
  1954. struct cvp_hal_session *s;
  1955. if (!device || !new_session) {
  1956. dprintk(CVP_ERR, "%s - invalid input\n", __func__);
  1957. return -EINVAL;
  1958. }
  1959. dev = device;
  1960. mutex_lock(&dev->lock);
  1961. s = kzalloc(sizeof(*s), GFP_KERNEL);
  1962. if (!s) {
  1963. dprintk(CVP_ERR, "new session fail: Out of memory\n");
  1964. goto err_session_init_fail;
  1965. }
  1966. s->session_id = session_id;
  1967. s->device = dev;
  1968. dprintk(CVP_SESS,
  1969. "%s: inst %pK, session %pK\n", __func__, session_id, s);
  1970. list_add_tail(&s->list, &dev->sess_head);
  1971. __set_default_sys_properties(device);
  1972. if (call_hfi_pkt_op(dev, session_init, &pkt, s)) {
  1973. dprintk(CVP_ERR, "session_init: failed to create packet\n");
  1974. goto err_session_init_fail;
  1975. }
  1976. *new_session = s;
  1977. if (__iface_cmdq_write(dev, &pkt))
  1978. goto err_session_init_fail;
  1979. mutex_unlock(&dev->lock);
  1980. return 0;
  1981. err_session_init_fail:
  1982. if (s)
  1983. __session_clean(s);
  1984. *new_session = NULL;
  1985. mutex_unlock(&dev->lock);
  1986. return -EINVAL;
  1987. }
  1988. static int __send_session_cmd(struct cvp_hal_session *session, int pkt_type)
  1989. {
  1990. struct cvp_hal_session_cmd_pkt pkt;
  1991. int rc = 0;
  1992. struct iris_hfi_device *device = session->device;
  1993. if (!__is_session_valid(device, session, __func__))
  1994. return -ECONNRESET;
  1995. rc = call_hfi_pkt_op(device, session_cmd,
  1996. &pkt, pkt_type, session);
  1997. if (rc == -EPERM)
  1998. return 0;
  1999. if (rc) {
  2000. dprintk(CVP_ERR, "send session cmd: create pkt failed\n");
  2001. goto err_create_pkt;
  2002. }
  2003. if (__iface_cmdq_write(session->device, &pkt))
  2004. rc = -ENOTEMPTY;
  2005. err_create_pkt:
  2006. return rc;
  2007. }
  2008. static int iris_hfi_session_end(void *session)
  2009. {
  2010. struct cvp_hal_session *sess;
  2011. struct iris_hfi_device *device;
  2012. int rc = 0;
  2013. if (!session) {
  2014. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2015. return -EINVAL;
  2016. }
  2017. sess = session;
  2018. device = sess->device;
  2019. if (!device) {
  2020. dprintk(CVP_ERR, "Invalid session %s\n", __func__);
  2021. return -EINVAL;
  2022. }
  2023. mutex_lock(&device->lock);
  2024. if (msm_cvp_fw_coverage) {
  2025. if (__sys_set_coverage(sess->device, msm_cvp_fw_coverage))
  2026. dprintk(CVP_WARN, "Fw_coverage msg ON failed\n");
  2027. }
  2028. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_END);
  2029. mutex_unlock(&device->lock);
  2030. return rc;
  2031. }
  2032. static int iris_hfi_session_abort(void *sess)
  2033. {
  2034. struct cvp_hal_session *session = sess;
  2035. struct iris_hfi_device *device;
  2036. int rc = 0;
  2037. if (!session || !session->device) {
  2038. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2039. return -EINVAL;
  2040. }
  2041. device = session->device;
  2042. mutex_lock(&device->lock);
  2043. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_ABORT);
  2044. mutex_unlock(&device->lock);
  2045. return rc;
  2046. }
  2047. static int iris_hfi_session_set_buffers(void *sess, u32 iova, u32 size)
  2048. {
  2049. struct cvp_hfi_cmd_session_set_buffers_packet pkt;
  2050. int rc = 0;
  2051. struct cvp_hal_session *session = sess;
  2052. struct iris_hfi_device *device;
  2053. if (!session || !session->device || !iova || !size) {
  2054. dprintk(CVP_ERR, "Invalid Params\n");
  2055. return -EINVAL;
  2056. }
  2057. device = session->device;
  2058. mutex_lock(&device->lock);
  2059. if (!__is_session_valid(device, session, __func__)) {
  2060. rc = -ECONNRESET;
  2061. goto err_create_pkt;
  2062. }
  2063. rc = call_hfi_pkt_op(device, session_set_buffers,
  2064. &pkt, session, iova, size);
  2065. if (rc) {
  2066. dprintk(CVP_ERR, "set buffers: failed to create packet\n");
  2067. goto err_create_pkt;
  2068. }
  2069. if (__iface_cmdq_write(session->device, &pkt))
  2070. rc = -ENOTEMPTY;
  2071. err_create_pkt:
  2072. mutex_unlock(&device->lock);
  2073. return rc;
  2074. }
  2075. static int iris_hfi_session_release_buffers(void *sess)
  2076. {
  2077. struct cvp_session_release_buffers_packet pkt;
  2078. int rc = 0;
  2079. struct cvp_hal_session *session = sess;
  2080. struct iris_hfi_device *device;
  2081. if (!session || !session->device) {
  2082. dprintk(CVP_ERR, "Invalid Params\n");
  2083. return -EINVAL;
  2084. }
  2085. device = session->device;
  2086. mutex_lock(&device->lock);
  2087. if (!__is_session_valid(device, session, __func__)) {
  2088. rc = -ECONNRESET;
  2089. goto err_create_pkt;
  2090. }
  2091. rc = call_hfi_pkt_op(device, session_release_buffers, &pkt, session);
  2092. if (rc) {
  2093. dprintk(CVP_ERR, "release buffers: failed to create packet\n");
  2094. goto err_create_pkt;
  2095. }
  2096. if (__iface_cmdq_write(session->device, &pkt))
  2097. rc = -ENOTEMPTY;
  2098. err_create_pkt:
  2099. mutex_unlock(&device->lock);
  2100. return rc;
  2101. }
  2102. static int iris_hfi_session_send(void *sess,
  2103. struct eva_kmd_hfi_packet *in_pkt)
  2104. {
  2105. int rc = 0;
  2106. struct eva_kmd_hfi_packet pkt;
  2107. struct cvp_hal_session *session = sess;
  2108. struct iris_hfi_device *device;
  2109. if (!session || !session->device) {
  2110. dprintk(CVP_ERR, "invalid session");
  2111. return -ENODEV;
  2112. }
  2113. device = session->device;
  2114. mutex_lock(&device->lock);
  2115. if (!__is_session_valid(device, session, __func__)) {
  2116. rc = -ECONNRESET;
  2117. goto err_send_pkt;
  2118. }
  2119. rc = call_hfi_pkt_op(device, session_send,
  2120. &pkt, session, in_pkt);
  2121. if (rc) {
  2122. dprintk(CVP_ERR,
  2123. "failed to create pkt\n");
  2124. goto err_send_pkt;
  2125. }
  2126. if (__iface_cmdq_write(session->device, &pkt))
  2127. rc = -ENOTEMPTY;
  2128. err_send_pkt:
  2129. mutex_unlock(&device->lock);
  2130. return rc;
  2131. return rc;
  2132. }
  2133. static int iris_hfi_session_flush(void *sess)
  2134. {
  2135. struct cvp_hal_session *session = sess;
  2136. struct iris_hfi_device *device;
  2137. int rc = 0;
  2138. if (!session || !session->device) {
  2139. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2140. return -EINVAL;
  2141. }
  2142. device = session->device;
  2143. mutex_lock(&device->lock);
  2144. rc = __send_session_cmd(session, HFI_CMD_SESSION_CVP_FLUSH);
  2145. mutex_unlock(&device->lock);
  2146. return rc;
  2147. }
  2148. static int __check_core_registered(struct iris_hfi_device *device,
  2149. phys_addr_t fw_addr, u8 *reg_addr, u32 reg_size,
  2150. phys_addr_t irq)
  2151. {
  2152. struct cvp_hal_data *cvp_hal_data;
  2153. if (!device) {
  2154. dprintk(CVP_INFO, "no device Registered\n");
  2155. return -EINVAL;
  2156. }
  2157. cvp_hal_data = device->cvp_hal_data;
  2158. if (!cvp_hal_data)
  2159. return -EINVAL;
  2160. if (cvp_hal_data->irq == irq &&
  2161. (CONTAINS(cvp_hal_data->firmware_base,
  2162. FIRMWARE_SIZE, fw_addr) ||
  2163. CONTAINS(fw_addr, FIRMWARE_SIZE,
  2164. cvp_hal_data->firmware_base) ||
  2165. CONTAINS(cvp_hal_data->register_base,
  2166. reg_size, reg_addr) ||
  2167. CONTAINS(reg_addr, reg_size,
  2168. cvp_hal_data->register_base) ||
  2169. OVERLAPS(cvp_hal_data->register_base,
  2170. reg_size, reg_addr, reg_size) ||
  2171. OVERLAPS(reg_addr, reg_size,
  2172. cvp_hal_data->register_base,
  2173. reg_size) ||
  2174. OVERLAPS(cvp_hal_data->firmware_base,
  2175. FIRMWARE_SIZE, fw_addr,
  2176. FIRMWARE_SIZE) ||
  2177. OVERLAPS(fw_addr, FIRMWARE_SIZE,
  2178. cvp_hal_data->firmware_base,
  2179. FIRMWARE_SIZE))) {
  2180. return 0;
  2181. }
  2182. dprintk(CVP_INFO, "Device not registered\n");
  2183. return -EINVAL;
  2184. }
  2185. static void __process_fatal_error(
  2186. struct iris_hfi_device *device)
  2187. {
  2188. struct msm_cvp_cb_cmd_done cmd_done = {0};
  2189. cmd_done.device_id = device->device_id;
  2190. device->callback(HAL_SYS_ERROR, &cmd_done);
  2191. }
  2192. static int __prepare_pc(struct iris_hfi_device *device)
  2193. {
  2194. int rc = 0;
  2195. struct cvp_hfi_cmd_sys_pc_prep_packet pkt;
  2196. rc = call_hfi_pkt_op(device, sys_pc_prep, &pkt);
  2197. if (rc) {
  2198. dprintk(CVP_ERR, "Failed to create sys pc prep pkt\n");
  2199. goto err_pc_prep;
  2200. }
  2201. if (__iface_cmdq_write(device, &pkt))
  2202. rc = -ENOTEMPTY;
  2203. if (rc)
  2204. dprintk(CVP_ERR, "Failed to prepare iris for power off");
  2205. err_pc_prep:
  2206. return rc;
  2207. }
  2208. static void iris_hfi_pm_handler(struct work_struct *work)
  2209. {
  2210. int rc = 0;
  2211. struct msm_cvp_core *core;
  2212. struct iris_hfi_device *device;
  2213. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  2214. if (core)
  2215. device = core->device->hfi_device_data;
  2216. else
  2217. return;
  2218. if (!device) {
  2219. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  2220. return;
  2221. }
  2222. dprintk(CVP_PWR,
  2223. "Entering %s\n", __func__);
  2224. /*
  2225. * It is ok to check this variable outside the lock since
  2226. * it is being updated in this context only
  2227. */
  2228. if (device->skip_pc_count >= CVP_MAX_PC_SKIP_COUNT) {
  2229. dprintk(CVP_WARN, "Failed to PC for %d times\n",
  2230. device->skip_pc_count);
  2231. device->skip_pc_count = 0;
  2232. __process_fatal_error(device);
  2233. return;
  2234. }
  2235. mutex_lock(&device->lock);
  2236. if (gfa_cv.state == DSP_SUSPEND)
  2237. rc = __power_collapse(device, true);
  2238. else
  2239. rc = __power_collapse(device, false);
  2240. mutex_unlock(&device->lock);
  2241. switch (rc) {
  2242. case 0:
  2243. device->skip_pc_count = 0;
  2244. /* Cancel pending delayed works if any */
  2245. cancel_delayed_work(&iris_hfi_pm_work);
  2246. dprintk(CVP_PWR, "%s: power collapse successful!\n",
  2247. __func__);
  2248. break;
  2249. case -EBUSY:
  2250. device->skip_pc_count = 0;
  2251. dprintk(CVP_PWR, "%s: retry PC as cvp is busy\n", __func__);
  2252. queue_delayed_work(device->iris_pm_workq,
  2253. &iris_hfi_pm_work, msecs_to_jiffies(
  2254. device->res->msm_cvp_pwr_collapse_delay));
  2255. break;
  2256. case -EAGAIN:
  2257. device->skip_pc_count++;
  2258. dprintk(CVP_WARN, "%s: retry power collapse (count %d)\n",
  2259. __func__, device->skip_pc_count);
  2260. queue_delayed_work(device->iris_pm_workq,
  2261. &iris_hfi_pm_work, msecs_to_jiffies(
  2262. device->res->msm_cvp_pwr_collapse_delay));
  2263. break;
  2264. default:
  2265. dprintk(CVP_ERR, "%s: power collapse failed\n", __func__);
  2266. break;
  2267. }
  2268. }
  2269. static int __power_collapse(struct iris_hfi_device *device, bool force)
  2270. {
  2271. int rc = 0;
  2272. u32 wfi_status = 0, idle_status = 0, pc_ready = 0;
  2273. u32 flags = 0;
  2274. int count = 0;
  2275. const int max_tries = 150;
  2276. if (!device) {
  2277. dprintk(CVP_ERR, "%s: invalid params\n", __func__);
  2278. return -EINVAL;
  2279. }
  2280. if (!device->power_enabled) {
  2281. dprintk(CVP_PWR, "%s: Power already disabled\n",
  2282. __func__);
  2283. goto exit;
  2284. }
  2285. rc = __core_in_valid_state(device);
  2286. if (!rc) {
  2287. dprintk(CVP_WARN,
  2288. "Core is in bad state, Skipping power collapse\n");
  2289. return -EINVAL;
  2290. }
  2291. rc = __dsp_suspend(device, force, flags);
  2292. if (rc == -EBUSY)
  2293. goto exit;
  2294. else if (rc)
  2295. goto skip_power_off;
  2296. pc_ready = __read_register(device, CVP_CTRL_STATUS) &
  2297. CVP_CTRL_STATUS_PC_READY;
  2298. if (!pc_ready) {
  2299. wfi_status = __read_register(device,
  2300. CVP_WRAPPER_CPU_STATUS);
  2301. idle_status = __read_register(device,
  2302. CVP_CTRL_STATUS);
  2303. if (!(wfi_status & BIT(0))) {
  2304. dprintk(CVP_WARN,
  2305. "Skipping PC as wfi_status (%#x) bit not set\n",
  2306. wfi_status);
  2307. goto skip_power_off;
  2308. }
  2309. if (!(idle_status & BIT(30))) {
  2310. dprintk(CVP_WARN,
  2311. "Skipping PC as idle_status (%#x) bit not set\n",
  2312. idle_status);
  2313. goto skip_power_off;
  2314. }
  2315. rc = __prepare_pc(device);
  2316. if (rc) {
  2317. dprintk(CVP_WARN, "Failed PC %d\n", rc);
  2318. goto skip_power_off;
  2319. }
  2320. while (count < max_tries) {
  2321. wfi_status = __read_register(device,
  2322. CVP_WRAPPER_CPU_STATUS);
  2323. pc_ready = __read_register(device,
  2324. CVP_CTRL_STATUS);
  2325. if ((wfi_status & BIT(0)) && (pc_ready &
  2326. CVP_CTRL_STATUS_PC_READY))
  2327. break;
  2328. usleep_range(150, 250);
  2329. count++;
  2330. }
  2331. if (count == max_tries) {
  2332. dprintk(CVP_ERR,
  2333. "Skip PC. Core is not in right state (%#x, %#x)\n",
  2334. wfi_status, pc_ready);
  2335. goto skip_power_off;
  2336. }
  2337. }
  2338. __flush_debug_queue(device, device->raw_packet);
  2339. rc = __suspend(device);
  2340. if (rc)
  2341. dprintk(CVP_ERR, "Failed __suspend\n");
  2342. exit:
  2343. return rc;
  2344. skip_power_off:
  2345. dprintk(CVP_PWR, "Skip PC(%#x, %#x, %#x)\n",
  2346. wfi_status, idle_status, pc_ready);
  2347. __flush_debug_queue(device, device->raw_packet);
  2348. return -EAGAIN;
  2349. }
  2350. static void __process_sys_error(struct iris_hfi_device *device)
  2351. {
  2352. struct cvp_hfi_sfr_struct *vsfr = NULL;
  2353. vsfr = (struct cvp_hfi_sfr_struct *)device->sfr.align_virtual_addr;
  2354. if (vsfr) {
  2355. void *p = memchr(vsfr->rg_data, '\0', vsfr->bufSize);
  2356. /*
  2357. * SFR isn't guaranteed to be NULL terminated
  2358. * since SYS_ERROR indicates that Iris is in the
  2359. * process of crashing.
  2360. */
  2361. if (p == NULL)
  2362. vsfr->rg_data[vsfr->bufSize - 1] = '\0';
  2363. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2364. vsfr->rg_data);
  2365. }
  2366. }
  2367. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet)
  2368. {
  2369. bool local_packet = false;
  2370. enum cvp_msg_prio log_level = CVP_FW;
  2371. if (!device) {
  2372. dprintk(CVP_ERR, "%s: Invalid params\n", __func__);
  2373. return;
  2374. }
  2375. if (!packet) {
  2376. packet = kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  2377. if (!packet) {
  2378. dprintk(CVP_ERR, "In %s() Fail to allocate mem\n",
  2379. __func__);
  2380. return;
  2381. }
  2382. local_packet = true;
  2383. /*
  2384. * Local packek is used when something FATAL occurred.
  2385. * It is good to print these logs by default.
  2386. */
  2387. log_level = CVP_ERR;
  2388. }
  2389. #define SKIP_INVALID_PKT(pkt_size, payload_size, pkt_hdr_size) ({ \
  2390. if (pkt_size < pkt_hdr_size || \
  2391. payload_size < MIN_PAYLOAD_SIZE || \
  2392. payload_size > \
  2393. (pkt_size - pkt_hdr_size + sizeof(u8))) { \
  2394. dprintk(CVP_ERR, \
  2395. "%s: invalid msg size - %d\n", \
  2396. __func__, pkt->msg_size); \
  2397. continue; \
  2398. } \
  2399. })
  2400. while (!__iface_dbgq_read(device, packet)) {
  2401. struct cvp_hfi_packet_header *pkt =
  2402. (struct cvp_hfi_packet_header *) packet;
  2403. if (pkt->size < sizeof(struct cvp_hfi_packet_header)) {
  2404. dprintk(CVP_ERR, "Invalid pkt size - %s\n",
  2405. __func__);
  2406. continue;
  2407. }
  2408. if (pkt->packet_type == HFI_MSG_SYS_DEBUG) {
  2409. struct cvp_hfi_msg_sys_debug_packet *pkt =
  2410. (struct cvp_hfi_msg_sys_debug_packet *) packet;
  2411. SKIP_INVALID_PKT(pkt->size,
  2412. pkt->msg_size, sizeof(*pkt));
  2413. /*
  2414. * All fw messages starts with new line character. This
  2415. * causes dprintk to print this message in two lines
  2416. * in the kernel log. Ignoring the first character
  2417. * from the message fixes this to print it in a single
  2418. * line.
  2419. */
  2420. pkt->rg_msg_data[pkt->msg_size-1] = '\0';
  2421. dprintk(log_level, "%s", &pkt->rg_msg_data[1]);
  2422. }
  2423. }
  2424. #undef SKIP_INVALID_PKT
  2425. if (local_packet)
  2426. kfree(packet);
  2427. }
  2428. static bool __is_session_valid(struct iris_hfi_device *device,
  2429. struct cvp_hal_session *session, const char *func)
  2430. {
  2431. struct cvp_hal_session *temp = NULL;
  2432. if (!device || !session)
  2433. goto invalid;
  2434. list_for_each_entry(temp, &device->sess_head, list)
  2435. if (session == temp)
  2436. return true;
  2437. invalid:
  2438. dprintk(CVP_WARN, "%s: device %pK, invalid session %pK\n",
  2439. func, device, session);
  2440. return false;
  2441. }
  2442. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  2443. u32 session_id)
  2444. {
  2445. struct cvp_hal_session *temp = NULL;
  2446. list_for_each_entry(temp, &device->sess_head, list) {
  2447. if (session_id == hash32_ptr(temp))
  2448. return temp;
  2449. }
  2450. return NULL;
  2451. }
  2452. #define _INVALID_MSG_ "Unrecognized MSG (%#x) session (%pK), discarding\n"
  2453. #define _INVALID_STATE_ "Ignore responses from %d to %d invalid state\n"
  2454. #define _DEVFREQ_FAIL_ "Failed to add devfreq device bus %s governor %s: %d\n"
  2455. static void process_system_msg(struct msm_cvp_cb_info *info,
  2456. struct iris_hfi_device *device,
  2457. void *raw_packet)
  2458. {
  2459. struct cvp_hal_sys_init_done sys_init_done = {0};
  2460. switch (info->response_type) {
  2461. case HAL_SYS_ERROR:
  2462. __process_sys_error(device);
  2463. break;
  2464. case HAL_SYS_RELEASE_RESOURCE_DONE:
  2465. dprintk(CVP_CORE, "Received SYS_RELEASE_RESOURCE\n");
  2466. break;
  2467. case HAL_SYS_INIT_DONE:
  2468. dprintk(CVP_CORE, "Received SYS_INIT_DONE\n");
  2469. sys_init_done.capabilities =
  2470. device->sys_init_capabilities;
  2471. cvp_hfi_process_sys_init_done_prop_read(
  2472. (struct cvp_hfi_msg_sys_init_done_packet *)
  2473. raw_packet, &sys_init_done);
  2474. info->response.cmd.data.sys_init_done = sys_init_done;
  2475. break;
  2476. default:
  2477. break;
  2478. }
  2479. }
  2480. static void **get_session_id(struct msm_cvp_cb_info *info)
  2481. {
  2482. void **session_id = NULL;
  2483. /* For session-related packets, validate session */
  2484. switch (info->response_type) {
  2485. case HAL_SESSION_INIT_DONE:
  2486. case HAL_SESSION_END_DONE:
  2487. case HAL_SESSION_ABORT_DONE:
  2488. case HAL_SESSION_STOP_DONE:
  2489. case HAL_SESSION_FLUSH_DONE:
  2490. case HAL_SESSION_SET_BUFFER_DONE:
  2491. case HAL_SESSION_SUSPEND_DONE:
  2492. case HAL_SESSION_RESUME_DONE:
  2493. case HAL_SESSION_SET_PROP_DONE:
  2494. case HAL_SESSION_GET_PROP_DONE:
  2495. case HAL_SESSION_RELEASE_BUFFER_DONE:
  2496. case HAL_SESSION_REGISTER_BUFFER_DONE:
  2497. case HAL_SESSION_UNREGISTER_BUFFER_DONE:
  2498. case HAL_SESSION_DFS_CONFIG_CMD_DONE:
  2499. case HAL_SESSION_DMM_CONFIG_CMD_DONE:
  2500. case HAL_SESSION_WARP_CONFIG_CMD_DONE:
  2501. case HAL_SESSION_WARP_NCC_CONFIG_CMD_DONE:
  2502. case HAL_SESSION_SGM_OF_CONFIG_CMD_DONE:
  2503. case HAL_SESSION_TME_CONFIG_CMD_DONE:
  2504. case HAL_SESSION_ODT_CONFIG_CMD_DONE:
  2505. case HAL_SESSION_OD_CONFIG_CMD_DONE:
  2506. case HAL_SESSION_NCC_CONFIG_CMD_DONE:
  2507. case HAL_SESSION_ICA_CONFIG_CMD_DONE:
  2508. case HAL_SESSION_HCD_CONFIG_CMD_DONE:
  2509. case HAL_SESSION_DCM_CONFIG_CMD_DONE:
  2510. case HAL_SESSION_DC_CONFIG_CMD_DONE:
  2511. case HAL_SESSION_PYS_HCD_CONFIG_CMD_DONE:
  2512. case HAL_SESSION_DMM_PARAMS_CMD_DONE:
  2513. case HAL_SESSION_WARP_DS_PARAMS_CMD_DONE:
  2514. case HAL_SESSION_PERSIST_SET_DONE:
  2515. case HAL_SESSION_PERSIST_REL_DONE:
  2516. case HAL_SESSION_FD_CONFIG_CMD_DONE:
  2517. case HAL_SESSION_MODEL_BUF_CMD_DONE:
  2518. case HAL_SESSION_PROPERTY_INFO:
  2519. case HAL_SESSION_EVENT_CHANGE:
  2520. session_id = &info->response.cmd.session_id;
  2521. break;
  2522. case HAL_SESSION_ERROR:
  2523. session_id = &info->response.data.session_id;
  2524. break;
  2525. case HAL_RESPONSE_UNUSED:
  2526. default:
  2527. session_id = NULL;
  2528. break;
  2529. }
  2530. return session_id;
  2531. }
  2532. static void print_msg_hdr(void *hdr)
  2533. {
  2534. struct cvp_hfi_msg_session_hdr *new_hdr =
  2535. (struct cvp_hfi_msg_session_hdr *)hdr;
  2536. dprintk(CVP_HFI, "HFI MSG received: %x %x %x %x %x %x %x\n",
  2537. new_hdr->size, new_hdr->packet_type,
  2538. new_hdr->session_id,
  2539. new_hdr->client_data.transaction_id,
  2540. new_hdr->client_data.data1,
  2541. new_hdr->client_data.data2,
  2542. new_hdr->error_type);
  2543. }
  2544. static int __response_handler(struct iris_hfi_device *device)
  2545. {
  2546. struct msm_cvp_cb_info *packets;
  2547. int packet_count = 0;
  2548. u8 *raw_packet = NULL;
  2549. bool requeue_pm_work = true;
  2550. if (!device || device->state != IRIS_STATE_INIT)
  2551. return 0;
  2552. packets = device->response_pkt;
  2553. raw_packet = device->raw_packet;
  2554. if (!raw_packet || !packets) {
  2555. dprintk(CVP_ERR,
  2556. "%s: Invalid args : Res packet = %p, Raw packet = %p\n",
  2557. __func__, packets, raw_packet);
  2558. return 0;
  2559. }
  2560. if (device->intr_status & CVP_FATAL_INTR_BMSK) {
  2561. struct cvp_hfi_sfr_struct *vsfr = (struct cvp_hfi_sfr_struct *)
  2562. device->sfr.align_virtual_addr;
  2563. struct msm_cvp_cb_info info = {
  2564. .response_type = HAL_SYS_WATCHDOG_TIMEOUT,
  2565. .response.cmd = {
  2566. .device_id = device->device_id,
  2567. }
  2568. };
  2569. if (vsfr)
  2570. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2571. vsfr->rg_data);
  2572. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CPU_NOC_BMSK)
  2573. dprintk(CVP_ERR, "Received Xtensa NOC error\n");
  2574. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CORE_NOC_BMSK)
  2575. dprintk(CVP_ERR, "Received CVP core NOC error\n");
  2576. if (device->intr_status & CVP_WRAPPER_INTR_MASK_A2HWD_BMSK)
  2577. dprintk(CVP_ERR, "Received CVP watchdog timeout\n");
  2578. packets[packet_count++] = info;
  2579. goto exit;
  2580. }
  2581. /* Bleed the msg queue dry of packets */
  2582. while (!__iface_msgq_read(device, raw_packet)) {
  2583. void **session_id = NULL;
  2584. struct msm_cvp_cb_info *info = &packets[packet_count++];
  2585. struct cvp_hfi_msg_session_hdr *hdr =
  2586. (struct cvp_hfi_msg_session_hdr *)raw_packet;
  2587. int rc = 0;
  2588. print_msg_hdr(hdr);
  2589. rc = cvp_hfi_process_msg_packet(device->device_id,
  2590. raw_packet, info);
  2591. if (rc) {
  2592. dprintk(CVP_WARN,
  2593. "Corrupt/unknown packet found, discarding\n");
  2594. --packet_count;
  2595. continue;
  2596. } else if (info->response_type == HAL_NO_RESP) {
  2597. --packet_count;
  2598. continue;
  2599. }
  2600. /* Process the packet types that we're interested in */
  2601. process_system_msg(info, device, raw_packet);
  2602. session_id = get_session_id(info);
  2603. /*
  2604. * hfi_process_msg_packet provides a session_id that's a hashed
  2605. * value of struct cvp_hal_session, we need to coerce the hashed
  2606. * value back to pointer that we can use. Ideally, hfi_process\
  2607. * _msg_packet should take care of this, but it doesn't have
  2608. * required information for it
  2609. */
  2610. if (session_id) {
  2611. struct cvp_hal_session *session = NULL;
  2612. if (upper_32_bits((uintptr_t)*session_id) != 0) {
  2613. dprintk(CVP_ERR,
  2614. "Upper 32-bits != 0 for sess_id=%pK\n",
  2615. *session_id);
  2616. }
  2617. session = __get_session(device,
  2618. (u32)(uintptr_t)*session_id);
  2619. if (!session) {
  2620. dprintk(CVP_ERR, _INVALID_MSG_,
  2621. info->response_type,
  2622. *session_id);
  2623. --packet_count;
  2624. continue;
  2625. }
  2626. *session_id = session->session_id;
  2627. }
  2628. if (packet_count >= cvp_max_packets) {
  2629. dprintk(CVP_WARN,
  2630. "Too many packets in message queue!\n");
  2631. break;
  2632. }
  2633. /* do not read packets after sys error packet */
  2634. if (info->response_type == HAL_SYS_ERROR)
  2635. break;
  2636. }
  2637. if (requeue_pm_work && device->res->sw_power_collapsible) {
  2638. cancel_delayed_work(&iris_hfi_pm_work);
  2639. if (!queue_delayed_work(device->iris_pm_workq,
  2640. &iris_hfi_pm_work,
  2641. msecs_to_jiffies(
  2642. device->res->msm_cvp_pwr_collapse_delay))) {
  2643. dprintk(CVP_ERR, "PM work already scheduled\n");
  2644. }
  2645. }
  2646. exit:
  2647. __flush_debug_queue(device, raw_packet);
  2648. return packet_count;
  2649. }
  2650. static void iris_hfi_core_work_handler(struct work_struct *work)
  2651. {
  2652. struct msm_cvp_core *core;
  2653. struct iris_hfi_device *device;
  2654. int num_responses = 0, i = 0;
  2655. u32 intr_status;
  2656. static bool warning_on = true;
  2657. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  2658. if (core)
  2659. device = core->device->hfi_device_data;
  2660. else
  2661. return;
  2662. mutex_lock(&device->lock);
  2663. if (!__core_in_valid_state(device)) {
  2664. if (warning_on) {
  2665. dprintk(CVP_WARN, "%s Core not in init state\n",
  2666. __func__);
  2667. warning_on = false;
  2668. }
  2669. goto err_no_work;
  2670. }
  2671. warning_on = true;
  2672. if (!device->callback) {
  2673. dprintk(CVP_ERR, "No interrupt callback function: %pK\n",
  2674. device);
  2675. goto err_no_work;
  2676. }
  2677. if (__resume(device)) {
  2678. dprintk(CVP_ERR, "%s: Power enable failed\n", __func__);
  2679. goto err_no_work;
  2680. }
  2681. __core_clear_interrupt(device);
  2682. num_responses = __response_handler(device);
  2683. dprintk(CVP_HFI, "%s:: cvp_driver_debug num_responses = %d ",
  2684. __func__, num_responses);
  2685. err_no_work:
  2686. /* Keep the interrupt status before releasing device lock */
  2687. intr_status = device->intr_status;
  2688. mutex_unlock(&device->lock);
  2689. /*
  2690. * Issue the callbacks outside of the locked contex to preserve
  2691. * re-entrancy.
  2692. */
  2693. for (i = 0; !IS_ERR_OR_NULL(device->response_pkt) &&
  2694. i < num_responses; ++i) {
  2695. struct msm_cvp_cb_info *r = &device->response_pkt[i];
  2696. void *rsp = (void *)&r->response;
  2697. if (!__core_in_valid_state(device)) {
  2698. dprintk(CVP_ERR,
  2699. _INVALID_STATE_, (i + 1), num_responses);
  2700. break;
  2701. }
  2702. dprintk(CVP_HFI, "Processing response %d of %d, type %d\n",
  2703. (i + 1), num_responses, r->response_type);
  2704. device->callback(r->response_type, rsp);
  2705. }
  2706. /* We need re-enable the irq which was disabled in ISR handler */
  2707. if (!(intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  2708. enable_irq(device->cvp_hal_data->irq);
  2709. /*
  2710. * XXX: Don't add any code beyond here. Reacquiring locks after release
  2711. * it above doesn't guarantee the atomicity that we're aiming for.
  2712. */
  2713. }
  2714. static DECLARE_WORK(iris_hfi_work, iris_hfi_core_work_handler);
  2715. static irqreturn_t iris_hfi_isr(int irq, void *dev)
  2716. {
  2717. struct iris_hfi_device *device = dev;
  2718. disable_irq_nosync(irq);
  2719. queue_work(device->cvp_workq, &iris_hfi_work);
  2720. return IRQ_HANDLED;
  2721. }
  2722. static int __init_regs_and_interrupts(struct iris_hfi_device *device,
  2723. struct msm_cvp_platform_resources *res)
  2724. {
  2725. struct cvp_hal_data *hal = NULL;
  2726. int rc = 0;
  2727. rc = __check_core_registered(device, res->firmware_base,
  2728. (u8 *)(uintptr_t)res->register_base,
  2729. res->register_size, res->irq);
  2730. if (!rc) {
  2731. dprintk(CVP_ERR, "Core present/Already added\n");
  2732. rc = -EEXIST;
  2733. goto err_core_init;
  2734. }
  2735. hal = kzalloc(sizeof(*hal), GFP_KERNEL);
  2736. if (!hal) {
  2737. dprintk(CVP_ERR, "Failed to alloc\n");
  2738. rc = -ENOMEM;
  2739. goto err_core_init;
  2740. }
  2741. hal->irq = res->irq;
  2742. hal->firmware_base = res->firmware_base;
  2743. hal->register_base = devm_ioremap(&res->pdev->dev,
  2744. res->register_base, res->register_size);
  2745. hal->register_size = res->register_size;
  2746. if (!hal->register_base) {
  2747. dprintk(CVP_ERR,
  2748. "could not map reg addr %pa of size %d\n",
  2749. &res->register_base, res->register_size);
  2750. goto error_irq_fail;
  2751. }
  2752. if (res->gcc_reg_base) {
  2753. hal->gcc_reg_base = devm_ioremap(&res->pdev->dev,
  2754. res->gcc_reg_base, res->gcc_reg_size);
  2755. hal->gcc_reg_size = res->gcc_reg_size;
  2756. if (!hal->gcc_reg_base)
  2757. dprintk(CVP_ERR,
  2758. "could not map gcc reg addr %pa of size %d\n",
  2759. &res->gcc_reg_base, res->gcc_reg_size);
  2760. }
  2761. device->cvp_hal_data = hal;
  2762. rc = request_irq(res->irq, iris_hfi_isr, IRQF_TRIGGER_HIGH,
  2763. "msm_cvp", device);
  2764. if (unlikely(rc)) {
  2765. dprintk(CVP_ERR, "() :request_irq failed\n");
  2766. goto error_irq_fail;
  2767. }
  2768. disable_irq_nosync(res->irq);
  2769. dprintk(CVP_INFO,
  2770. "firmware_base = %pa, register_base = %pa, register_size = %d\n",
  2771. &res->firmware_base, &res->register_base,
  2772. res->register_size);
  2773. return rc;
  2774. error_irq_fail:
  2775. kfree(hal);
  2776. err_core_init:
  2777. return rc;
  2778. }
  2779. static inline void __deinit_clocks(struct iris_hfi_device *device)
  2780. {
  2781. struct clock_info *cl;
  2782. device->clk_freq = 0;
  2783. iris_hfi_for_each_clock_reverse(device, cl) {
  2784. if (cl->clk) {
  2785. clk_put(cl->clk);
  2786. cl->clk = NULL;
  2787. }
  2788. }
  2789. }
  2790. static inline int __init_clocks(struct iris_hfi_device *device)
  2791. {
  2792. int rc = 0;
  2793. struct clock_info *cl = NULL;
  2794. if (!device) {
  2795. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  2796. return -EINVAL;
  2797. }
  2798. iris_hfi_for_each_clock(device, cl) {
  2799. dprintk(CVP_PWR, "%s: scalable? %d, count %d\n",
  2800. cl->name, cl->has_scaling, cl->count);
  2801. }
  2802. iris_hfi_for_each_clock(device, cl) {
  2803. if (!cl->clk) {
  2804. cl->clk = clk_get(&device->res->pdev->dev, cl->name);
  2805. if (IS_ERR_OR_NULL(cl->clk)) {
  2806. dprintk(CVP_ERR,
  2807. "Failed to get clock: %s\n", cl->name);
  2808. rc = PTR_ERR(cl->clk) ?: -EINVAL;
  2809. cl->clk = NULL;
  2810. goto err_clk_get;
  2811. }
  2812. }
  2813. }
  2814. device->clk_freq = 0;
  2815. return 0;
  2816. err_clk_get:
  2817. __deinit_clocks(device);
  2818. return rc;
  2819. }
  2820. static int __handle_reset_clk(struct msm_cvp_platform_resources *res,
  2821. int reset_index, enum reset_state state,
  2822. enum power_state pwr_state)
  2823. {
  2824. int rc = 0;
  2825. struct reset_control *rst;
  2826. struct reset_info rst_info;
  2827. struct reset_set *rst_set = &res->reset_set;
  2828. if (!rst_set->reset_tbl)
  2829. return 0;
  2830. rst_info = rst_set->reset_tbl[reset_index];
  2831. rst = rst_info.rst;
  2832. dprintk(CVP_PWR, "reset_clk: name %s reset_state %d rst %pK ps=%d\n",
  2833. rst_set->reset_tbl[reset_index].name, state, rst, pwr_state);
  2834. switch (state) {
  2835. case INIT:
  2836. if (rst)
  2837. goto skip_reset_init;
  2838. rst = devm_reset_control_get(&res->pdev->dev,
  2839. rst_set->reset_tbl[reset_index].name);
  2840. if (IS_ERR(rst))
  2841. rc = PTR_ERR(rst);
  2842. rst_set->reset_tbl[reset_index].rst = rst;
  2843. break;
  2844. case ASSERT:
  2845. if (!rst) {
  2846. rc = PTR_ERR(rst);
  2847. goto failed_to_reset;
  2848. }
  2849. if (pwr_state != rst_info.required_state)
  2850. break;
  2851. rc = reset_control_assert(rst);
  2852. break;
  2853. case DEASSERT:
  2854. if (!rst) {
  2855. rc = PTR_ERR(rst);
  2856. goto failed_to_reset;
  2857. }
  2858. if (pwr_state != rst_info.required_state)
  2859. break;
  2860. rc = reset_control_deassert(rst);
  2861. break;
  2862. default:
  2863. dprintk(CVP_ERR, "Invalid reset request\n");
  2864. if (rc)
  2865. goto failed_to_reset;
  2866. }
  2867. return 0;
  2868. skip_reset_init:
  2869. failed_to_reset:
  2870. return rc;
  2871. }
  2872. static inline void __disable_unprepare_clks(struct iris_hfi_device *device)
  2873. {
  2874. struct clock_info *cl;
  2875. if (!device) {
  2876. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  2877. return;
  2878. }
  2879. iris_hfi_for_each_clock_reverse(device, cl) {
  2880. dprintk(CVP_PWR, "Clock: %s disable and unprepare\n",
  2881. cl->name);
  2882. clk_disable_unprepare(cl->clk);
  2883. }
  2884. }
  2885. static int reset_ahb2axi_bridge(struct iris_hfi_device *device)
  2886. {
  2887. int rc, i;
  2888. enum power_state s;
  2889. if (!device) {
  2890. dprintk(CVP_ERR, "NULL device\n");
  2891. rc = -EINVAL;
  2892. goto failed_to_reset;
  2893. }
  2894. if (device->power_enabled)
  2895. s = CVP_POWER_ON;
  2896. else
  2897. s = CVP_POWER_OFF;
  2898. for (i = 0; i < device->res->reset_set.count; i++) {
  2899. rc = __handle_reset_clk(device->res, i, ASSERT, s);
  2900. if (rc) {
  2901. dprintk(CVP_ERR,
  2902. "failed to assert reset clocks\n");
  2903. goto failed_to_reset;
  2904. }
  2905. /* wait for deassert */
  2906. usleep_range(1000, 1050);
  2907. rc = __handle_reset_clk(device->res, i, DEASSERT, s);
  2908. if (rc) {
  2909. dprintk(CVP_ERR,
  2910. "failed to deassert reset clocks\n");
  2911. goto failed_to_reset;
  2912. }
  2913. }
  2914. return 0;
  2915. failed_to_reset:
  2916. return rc;
  2917. }
  2918. static inline int __prepare_enable_clks(struct iris_hfi_device *device)
  2919. {
  2920. struct clock_info *cl = NULL, *cl_fail = NULL;
  2921. int rc = 0, c = 0;
  2922. if (!device) {
  2923. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  2924. return -EINVAL;
  2925. }
  2926. iris_hfi_for_each_clock(device, cl) {
  2927. /*
  2928. * For the clocks we control, set the rate prior to preparing
  2929. * them. Since we don't really have a load at this point, scale
  2930. * it to the lowest frequency possible
  2931. */
  2932. if (cl->has_scaling)
  2933. clk_set_rate(cl->clk, clk_round_rate(cl->clk, 0));
  2934. rc = clk_prepare_enable(cl->clk);
  2935. if (rc) {
  2936. dprintk(CVP_ERR, "Failed to enable clocks\n");
  2937. cl_fail = cl;
  2938. goto fail_clk_enable;
  2939. }
  2940. c++;
  2941. dprintk(CVP_PWR, "Clock: %s prepared and enabled\n", cl->name);
  2942. }
  2943. return rc;
  2944. fail_clk_enable:
  2945. iris_hfi_for_each_clock_reverse_continue(device, cl, c) {
  2946. dprintk(CVP_ERR, "Clock: %s disable and unprepare\n",
  2947. cl->name);
  2948. clk_disable_unprepare(cl->clk);
  2949. }
  2950. return rc;
  2951. }
  2952. static void __deinit_bus(struct iris_hfi_device *device)
  2953. {
  2954. struct bus_info *bus = NULL;
  2955. if (!device)
  2956. return;
  2957. kfree(device->bus_vote.data);
  2958. device->bus_vote = CVP_DEFAULT_BUS_VOTE;
  2959. iris_hfi_for_each_bus_reverse(device, bus) {
  2960. dev_set_drvdata(bus->dev, NULL);
  2961. icc_put(bus->client);
  2962. bus->client = NULL;
  2963. }
  2964. }
  2965. static int __init_bus(struct iris_hfi_device *device)
  2966. {
  2967. struct bus_info *bus = NULL;
  2968. int rc = 0;
  2969. if (!device)
  2970. return -EINVAL;
  2971. iris_hfi_for_each_bus(device, bus) {
  2972. /*
  2973. * This is stupid, but there's no other easy way to ahold
  2974. * of struct bus_info in iris_hfi_devfreq_*()
  2975. */
  2976. WARN(dev_get_drvdata(bus->dev), "%s's drvdata already set\n",
  2977. dev_name(bus->dev));
  2978. dev_set_drvdata(bus->dev, device);
  2979. bus->client = icc_get(&device->res->pdev->dev,
  2980. bus->master, bus->slave);
  2981. if (IS_ERR_OR_NULL(bus->client)) {
  2982. rc = PTR_ERR(bus->client) ?: -EBADHANDLE;
  2983. dprintk(CVP_ERR, "Failed to register bus %s: %d\n",
  2984. bus->name, rc);
  2985. bus->client = NULL;
  2986. goto err_add_dev;
  2987. }
  2988. }
  2989. return 0;
  2990. err_add_dev:
  2991. __deinit_bus(device);
  2992. return rc;
  2993. }
  2994. static void __deinit_regulators(struct iris_hfi_device *device)
  2995. {
  2996. struct regulator_info *rinfo = NULL;
  2997. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  2998. if (rinfo->regulator) {
  2999. regulator_put(rinfo->regulator);
  3000. rinfo->regulator = NULL;
  3001. }
  3002. }
  3003. }
  3004. static int __init_regulators(struct iris_hfi_device *device)
  3005. {
  3006. int rc = 0;
  3007. struct regulator_info *rinfo = NULL;
  3008. iris_hfi_for_each_regulator(device, rinfo) {
  3009. rinfo->regulator = regulator_get(&device->res->pdev->dev,
  3010. rinfo->name);
  3011. if (IS_ERR_OR_NULL(rinfo->regulator)) {
  3012. rc = PTR_ERR(rinfo->regulator) ?: -EBADHANDLE;
  3013. dprintk(CVP_ERR, "Failed to get regulator: %s\n",
  3014. rinfo->name);
  3015. rinfo->regulator = NULL;
  3016. goto err_reg_get;
  3017. }
  3018. }
  3019. return 0;
  3020. err_reg_get:
  3021. __deinit_regulators(device);
  3022. return rc;
  3023. }
  3024. static void __deinit_subcaches(struct iris_hfi_device *device)
  3025. {
  3026. struct subcache_info *sinfo = NULL;
  3027. if (!device) {
  3028. dprintk(CVP_ERR, "deinit_subcaches: invalid device %pK\n",
  3029. device);
  3030. goto exit;
  3031. }
  3032. if (!is_sys_cache_present(device))
  3033. goto exit;
  3034. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3035. if (sinfo->subcache) {
  3036. dprintk(CVP_CORE, "deinit_subcaches: %s\n",
  3037. sinfo->name);
  3038. llcc_slice_putd(sinfo->subcache);
  3039. sinfo->subcache = NULL;
  3040. }
  3041. }
  3042. exit:
  3043. return;
  3044. }
  3045. static int __init_subcaches(struct iris_hfi_device *device)
  3046. {
  3047. int rc = 0;
  3048. struct subcache_info *sinfo = NULL;
  3049. if (!device) {
  3050. dprintk(CVP_ERR, "init_subcaches: invalid device %pK\n",
  3051. device);
  3052. return -EINVAL;
  3053. }
  3054. if (!is_sys_cache_present(device))
  3055. return 0;
  3056. iris_hfi_for_each_subcache(device, sinfo) {
  3057. if (!strcmp("cvp", sinfo->name)) {
  3058. sinfo->subcache = llcc_slice_getd(LLCC_CVP);
  3059. } else if (!strcmp("cvpfw", sinfo->name)) {
  3060. sinfo->subcache = llcc_slice_getd(LLCC_CVPFW);
  3061. } else {
  3062. dprintk(CVP_ERR, "Invalid subcache name %s\n",
  3063. sinfo->name);
  3064. }
  3065. if (IS_ERR_OR_NULL(sinfo->subcache)) {
  3066. rc = PTR_ERR(sinfo->subcache) ?
  3067. PTR_ERR(sinfo->subcache) : -EBADHANDLE;
  3068. dprintk(CVP_ERR,
  3069. "init_subcaches: invalid subcache: %s rc %d\n",
  3070. sinfo->name, rc);
  3071. sinfo->subcache = NULL;
  3072. goto err_subcache_get;
  3073. }
  3074. dprintk(CVP_CORE, "init_subcaches: %s\n",
  3075. sinfo->name);
  3076. }
  3077. return 0;
  3078. err_subcache_get:
  3079. __deinit_subcaches(device);
  3080. return rc;
  3081. }
  3082. static int __init_resources(struct iris_hfi_device *device,
  3083. struct msm_cvp_platform_resources *res)
  3084. {
  3085. int i, rc = 0;
  3086. rc = __init_regulators(device);
  3087. if (rc) {
  3088. dprintk(CVP_ERR, "Failed to get all regulators\n");
  3089. return -ENODEV;
  3090. }
  3091. rc = __init_clocks(device);
  3092. if (rc) {
  3093. dprintk(CVP_ERR, "Failed to init clocks\n");
  3094. rc = -ENODEV;
  3095. goto err_init_clocks;
  3096. }
  3097. for (i = 0; i < device->res->reset_set.count; i++) {
  3098. rc = __handle_reset_clk(res, i, INIT, 0);
  3099. if (rc) {
  3100. dprintk(CVP_ERR, "Failed to init reset clocks\n");
  3101. rc = -ENODEV;
  3102. goto err_init_reset_clk;
  3103. }
  3104. }
  3105. rc = __init_bus(device);
  3106. if (rc) {
  3107. dprintk(CVP_ERR, "Failed to init bus: %d\n", rc);
  3108. goto err_init_bus;
  3109. }
  3110. rc = __init_subcaches(device);
  3111. if (rc)
  3112. dprintk(CVP_WARN, "Failed to init subcaches: %d\n", rc);
  3113. device->sys_init_capabilities =
  3114. kzalloc(sizeof(struct msm_cvp_capability)
  3115. * CVP_MAX_SESSIONS, GFP_KERNEL);
  3116. return rc;
  3117. err_init_reset_clk:
  3118. err_init_bus:
  3119. __deinit_clocks(device);
  3120. err_init_clocks:
  3121. __deinit_regulators(device);
  3122. return rc;
  3123. }
  3124. static void __deinit_resources(struct iris_hfi_device *device)
  3125. {
  3126. __deinit_subcaches(device);
  3127. __deinit_bus(device);
  3128. __deinit_clocks(device);
  3129. __deinit_regulators(device);
  3130. kfree(device->sys_init_capabilities);
  3131. device->sys_init_capabilities = NULL;
  3132. }
  3133. static int __disable_regulator(struct regulator_info *rinfo,
  3134. struct iris_hfi_device *device)
  3135. {
  3136. int rc = 0;
  3137. dprintk(CVP_PWR, "Disabling regulator %s\n", rinfo->name);
  3138. /*
  3139. * This call is needed. Driver needs to acquire the control back
  3140. * from HW in order to disable the regualtor. Else the behavior
  3141. * is unknown.
  3142. */
  3143. rc = __acquire_regulator(rinfo, device);
  3144. if (rc) {
  3145. /*
  3146. * This is somewhat fatal, but nothing we can do
  3147. * about it. We can't disable the regulator w/o
  3148. * getting it back under s/w control
  3149. */
  3150. dprintk(CVP_WARN,
  3151. "Failed to acquire control on %s\n",
  3152. rinfo->name);
  3153. goto disable_regulator_failed;
  3154. }
  3155. rc = regulator_disable(rinfo->regulator);
  3156. if (rc) {
  3157. dprintk(CVP_WARN,
  3158. "Failed to disable %s: %d\n",
  3159. rinfo->name, rc);
  3160. goto disable_regulator_failed;
  3161. }
  3162. return 0;
  3163. disable_regulator_failed:
  3164. /* Bring attention to this issue */
  3165. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3166. return rc;
  3167. }
  3168. static int __enable_hw_power_collapse(struct iris_hfi_device *device)
  3169. {
  3170. int rc = 0;
  3171. if (!msm_cvp_fw_low_power_mode) {
  3172. dprintk(CVP_PWR, "Not enabling hardware power collapse\n");
  3173. return 0;
  3174. }
  3175. rc = __hand_off_regulators(device);
  3176. if (rc)
  3177. dprintk(CVP_WARN,
  3178. "%s : Failed to enable HW power collapse %d\n",
  3179. __func__, rc);
  3180. return rc;
  3181. }
  3182. static int __enable_regulators(struct iris_hfi_device *device)
  3183. {
  3184. int rc = 0, c = 0;
  3185. struct regulator_info *rinfo;
  3186. dprintk(CVP_PWR, "Enabling regulators\n");
  3187. iris_hfi_for_each_regulator(device, rinfo) {
  3188. rc = regulator_enable(rinfo->regulator);
  3189. if (rc) {
  3190. dprintk(CVP_ERR, "Failed to enable %s: %d\n",
  3191. rinfo->name, rc);
  3192. goto err_reg_enable_failed;
  3193. }
  3194. dprintk(CVP_PWR, "Enabled regulator %s\n", rinfo->name);
  3195. c++;
  3196. }
  3197. return 0;
  3198. err_reg_enable_failed:
  3199. iris_hfi_for_each_regulator_reverse_continue(device, rinfo, c)
  3200. __disable_regulator(rinfo, device);
  3201. return rc;
  3202. }
  3203. static int __disable_regulators(struct iris_hfi_device *device)
  3204. {
  3205. struct regulator_info *rinfo;
  3206. dprintk(CVP_PWR, "Disabling regulators\n");
  3207. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  3208. __disable_regulator(rinfo, device);
  3209. if (rinfo->has_hw_power_collapse)
  3210. regulator_set_mode(rinfo->regulator,
  3211. REGULATOR_MODE_NORMAL);
  3212. }
  3213. return 0;
  3214. }
  3215. static int __enable_subcaches(struct iris_hfi_device *device)
  3216. {
  3217. int rc = 0;
  3218. u32 c = 0;
  3219. struct subcache_info *sinfo;
  3220. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3221. return 0;
  3222. /* Activate subcaches */
  3223. iris_hfi_for_each_subcache(device, sinfo) {
  3224. rc = llcc_slice_activate(sinfo->subcache);
  3225. if (rc) {
  3226. dprintk(CVP_WARN, "Failed to activate %s: %d\n",
  3227. sinfo->name, rc);
  3228. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3229. goto err_activate_fail;
  3230. }
  3231. sinfo->isactive = true;
  3232. dprintk(CVP_CORE, "Activated subcache %s\n", sinfo->name);
  3233. c++;
  3234. }
  3235. dprintk(CVP_CORE, "Activated %d Subcaches to CVP\n", c);
  3236. return 0;
  3237. err_activate_fail:
  3238. __release_subcaches(device);
  3239. __disable_subcaches(device);
  3240. return 0;
  3241. }
  3242. static int __set_subcaches(struct iris_hfi_device *device)
  3243. {
  3244. int rc = 0;
  3245. u32 c = 0;
  3246. struct subcache_info *sinfo;
  3247. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3248. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3249. struct cvp_hfi_resource_subcache_type *sc_res;
  3250. struct cvp_resource_hdr rhdr;
  3251. if (device->res->sys_cache_res_set || msm_cvp_syscache_disable) {
  3252. dprintk(CVP_CORE, "Subcaches already set or disabled\n");
  3253. return 0;
  3254. }
  3255. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3256. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3257. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3258. iris_hfi_for_each_subcache(device, sinfo) {
  3259. if (sinfo->isactive) {
  3260. sc_res[c].size = sinfo->subcache->slice_size;
  3261. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3262. c++;
  3263. }
  3264. }
  3265. /* Set resource to CVP for activated subcaches */
  3266. if (c) {
  3267. dprintk(CVP_CORE, "Setting %d Subcaches\n", c);
  3268. rhdr.resource_handle = sc_res_info; /* cookie */
  3269. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3270. sc_res_info->num_entries = c;
  3271. rc = __core_set_resource(device, &rhdr, (void *)sc_res_info);
  3272. if (rc) {
  3273. dprintk(CVP_WARN, "Failed to set subcaches %d\n", rc);
  3274. goto err_fail_set_subacaches;
  3275. }
  3276. iris_hfi_for_each_subcache(device, sinfo) {
  3277. if (sinfo->isactive)
  3278. sinfo->isset = true;
  3279. }
  3280. dprintk(CVP_CORE, "Set Subcaches done to CVP\n");
  3281. device->res->sys_cache_res_set = true;
  3282. }
  3283. return 0;
  3284. err_fail_set_subacaches:
  3285. __disable_subcaches(device);
  3286. return 0;
  3287. }
  3288. static int __release_subcaches(struct iris_hfi_device *device)
  3289. {
  3290. struct subcache_info *sinfo;
  3291. int rc = 0;
  3292. u32 c = 0;
  3293. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3294. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3295. struct cvp_hfi_resource_subcache_type *sc_res;
  3296. struct cvp_resource_hdr rhdr;
  3297. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3298. return 0;
  3299. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3300. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3301. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3302. /* Release resource command to Iris */
  3303. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3304. if (sinfo->isset) {
  3305. /* Update the entry */
  3306. sc_res[c].size = sinfo->subcache->slice_size;
  3307. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3308. c++;
  3309. sinfo->isset = false;
  3310. }
  3311. }
  3312. if (c > 0) {
  3313. dprintk(CVP_CORE, "Releasing %d subcaches\n", c);
  3314. rhdr.resource_handle = sc_res_info; /* cookie */
  3315. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3316. rc = __core_release_resource(device, &rhdr);
  3317. if (rc)
  3318. dprintk(CVP_WARN,
  3319. "Failed to release %d subcaches\n", c);
  3320. }
  3321. device->res->sys_cache_res_set = false;
  3322. return 0;
  3323. }
  3324. static int __disable_subcaches(struct iris_hfi_device *device)
  3325. {
  3326. struct subcache_info *sinfo;
  3327. int rc = 0;
  3328. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3329. return 0;
  3330. /* De-activate subcaches */
  3331. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3332. if (sinfo->isactive) {
  3333. dprintk(CVP_CORE, "De-activate subcache %s\n",
  3334. sinfo->name);
  3335. rc = llcc_slice_deactivate(sinfo->subcache);
  3336. if (rc) {
  3337. dprintk(CVP_WARN,
  3338. "Failed to de-activate %s: %d\n",
  3339. sinfo->name, rc);
  3340. }
  3341. sinfo->isactive = false;
  3342. }
  3343. }
  3344. return 0;
  3345. }
  3346. static void interrupt_init_iris2(struct iris_hfi_device *device)
  3347. {
  3348. u32 mask_val = 0;
  3349. /* All interrupts should be disabled initially 0x1F6 : Reset value */
  3350. mask_val = __read_register(device, CVP_WRAPPER_INTR_MASK);
  3351. /* Write 0 to unmask CPU and WD interrupts */
  3352. mask_val &= ~(CVP_FATAL_INTR_BMSK | CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK);
  3353. __write_register(device, CVP_WRAPPER_INTR_MASK, mask_val);
  3354. dprintk(CVP_REG, "Init irq: reg: %x, mask value %x\n",
  3355. CVP_WRAPPER_INTR_MASK, mask_val);
  3356. }
  3357. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device)
  3358. {
  3359. /* initialize DSP QTBL & UCREGION with CPU queues */
  3360. __write_register(device, HFI_DSP_QTBL_ADDR,
  3361. (u32)device->dsp_iface_q_table.align_device_addr);
  3362. __write_register(device, HFI_DSP_UC_REGION_ADDR,
  3363. (u32)device->dsp_iface_q_table.align_device_addr);
  3364. __write_register(device, HFI_DSP_UC_REGION_SIZE,
  3365. device->dsp_iface_q_table.mem_data.size);
  3366. }
  3367. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device)
  3368. {
  3369. __write_register(device, CVP_WRAPPER_CPU_CLOCK_CONFIG, 0);
  3370. }
  3371. static int __set_ubwc_config(struct iris_hfi_device *device)
  3372. {
  3373. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  3374. int rc = 0;
  3375. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  3376. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  3377. if (!device->res->ubwc_config)
  3378. return 0;
  3379. rc = call_hfi_pkt_op(device, sys_ubwc_config, pkt,
  3380. device->res->ubwc_config);
  3381. if (rc) {
  3382. dprintk(CVP_WARN,
  3383. "ubwc config setting to FW failed\n");
  3384. rc = -ENOTEMPTY;
  3385. goto fail_to_set_ubwc_config;
  3386. }
  3387. if (__iface_cmdq_write(device, pkt)) {
  3388. rc = -ENOTEMPTY;
  3389. goto fail_to_set_ubwc_config;
  3390. }
  3391. fail_to_set_ubwc_config:
  3392. return rc;
  3393. }
  3394. static int __iris_power_on(struct iris_hfi_device *device)
  3395. {
  3396. int rc = 0;
  3397. if (device->power_enabled)
  3398. return 0;
  3399. /* Vote for all hardware resources */
  3400. rc = __vote_buses(device, device->bus_vote.data,
  3401. device->bus_vote.data_count);
  3402. if (rc) {
  3403. dprintk(CVP_ERR, "Failed to vote buses, err: %d\n", rc);
  3404. goto fail_vote_buses;
  3405. }
  3406. rc = __enable_regulators(device);
  3407. if (rc) {
  3408. dprintk(CVP_ERR, "Failed to enable GDSC, err = %d\n", rc);
  3409. goto fail_enable_gdsc;
  3410. }
  3411. rc = call_iris_op(device, reset_ahb2axi_bridge, device);
  3412. if (rc) {
  3413. dprintk(CVP_ERR, "Failed to reset ahb2axi: %d\n", rc);
  3414. goto fail_enable_clks;
  3415. }
  3416. rc = __prepare_enable_clks(device);
  3417. if (rc) {
  3418. dprintk(CVP_ERR, "Failed to enable clocks: %d\n", rc);
  3419. goto fail_enable_clks;
  3420. }
  3421. rc = __scale_clocks(device);
  3422. if (rc) {
  3423. dprintk(CVP_WARN,
  3424. "Failed to scale clocks, perf may regress\n");
  3425. rc = 0;
  3426. }
  3427. /*Do not access registers before this point!*/
  3428. device->power_enabled = true;
  3429. dprintk(CVP_PWR, "Done with scaling\n");
  3430. /*
  3431. * Re-program all of the registers that get reset as a result of
  3432. * regulator_disable() and _enable()
  3433. */
  3434. __set_registers(device);
  3435. dprintk(CVP_CORE, "Done with register set\n");
  3436. call_iris_op(device, interrupt_init, device);
  3437. dprintk(CVP_CORE, "Done with interrupt enabling\n");
  3438. device->intr_status = 0;
  3439. enable_irq(device->cvp_hal_data->irq);
  3440. return rc;
  3441. fail_enable_clks:
  3442. __disable_regulators(device);
  3443. fail_enable_gdsc:
  3444. __unvote_buses(device);
  3445. fail_vote_buses:
  3446. device->power_enabled = false;
  3447. return rc;
  3448. }
  3449. void power_off_common(struct iris_hfi_device *device)
  3450. {
  3451. if (!device->power_enabled)
  3452. return;
  3453. if (!(device->intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  3454. disable_irq_nosync(device->cvp_hal_data->irq);
  3455. device->intr_status = 0;
  3456. __disable_unprepare_clks(device);
  3457. if (__disable_regulators(device))
  3458. dprintk(CVP_WARN, "Failed to disable regulators\n");
  3459. if (__unvote_buses(device))
  3460. dprintk(CVP_WARN, "Failed to unvote for buses\n");
  3461. device->power_enabled = false;
  3462. }
  3463. static inline int __suspend(struct iris_hfi_device *device)
  3464. {
  3465. int rc = 0;
  3466. if (!device) {
  3467. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  3468. return -EINVAL;
  3469. } else if (!device->power_enabled) {
  3470. dprintk(CVP_PWR, "Power already disabled\n");
  3471. return 0;
  3472. }
  3473. dprintk(CVP_PWR, "Entering suspend\n");
  3474. if (device->res->pm_qos_latency_us &&
  3475. cpu_latency_qos_request_active(&device->qos))
  3476. cpu_latency_qos_remove_request(&device->qos);
  3477. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  3478. if (rc) {
  3479. dprintk(CVP_WARN, "Failed to suspend cvp core %d\n", rc);
  3480. goto err_tzbsp_suspend;
  3481. }
  3482. __disable_subcaches(device);
  3483. call_iris_op(device, power_off, device);
  3484. dprintk(CVP_PWR, "Iris power off\n");
  3485. return rc;
  3486. err_tzbsp_suspend:
  3487. return rc;
  3488. }
  3489. static void power_off_iris2(struct iris_hfi_device *device)
  3490. {
  3491. u32 lpi_status, reg_status = 0, count = 0, max_count = 1000;
  3492. u32 pc_ready, wfi_status, sbm_ln0_low;
  3493. u32 main_sbm_ln0_low, main_sbm_ln1_high;
  3494. if (!device->power_enabled || !device->res->sw_power_collapsible)
  3495. return;
  3496. if (!(device->intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  3497. disable_irq_nosync(device->cvp_hal_data->irq);
  3498. device->intr_status = 0;
  3499. /* HPG 6.1.2 Step 1 */
  3500. __write_register(device, CVP_CPU_CS_X2RPMh, 0x3);
  3501. /* HPG 6.1.2 Step 2, noc to low power */
  3502. __write_register(device, CVP_AON_WRAPPER_MVP_NOC_LPI_CONTROL, 0x1);
  3503. while (!reg_status && count < max_count) {
  3504. lpi_status =
  3505. __read_register(device,
  3506. CVP_AON_WRAPPER_MVP_NOC_LPI_STATUS);
  3507. reg_status = lpi_status & BIT(0);
  3508. /* Wait for noc lpi status to be set */
  3509. usleep_range(50, 100);
  3510. count++;
  3511. }
  3512. dprintk(CVP_PWR,
  3513. "Noc: lpi_status %x noc_status %x (count %d)\n",
  3514. lpi_status, reg_status, count);
  3515. if (count == max_count) {
  3516. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  3517. pc_ready = __read_register(device, CVP_CTRL_STATUS);
  3518. sbm_ln0_low =
  3519. __read_register(device, CVP_NOC_SBM_SENSELN0_LOW);
  3520. main_sbm_ln0_low = __read_register(device,
  3521. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_LOW);
  3522. main_sbm_ln1_high = __read_register(device,
  3523. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN1_HIGH);
  3524. dprintk(CVP_WARN,
  3525. "NOC not in qaccept status %x %x %x %x %x %x %x\n",
  3526. reg_status, lpi_status, wfi_status, pc_ready,
  3527. sbm_ln0_low, main_sbm_ln0_low, main_sbm_ln1_high);
  3528. }
  3529. /* HPG 6.1.2 Step 3, debug bridge to low power BYPASSED */
  3530. /* HPG 6.1.2 Step 4, debug bridge to lpi release */
  3531. __write_register(device,
  3532. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x0);
  3533. lpi_status = 0x1;
  3534. count = 0;
  3535. while (lpi_status && count < max_count) {
  3536. lpi_status = __read_register(device,
  3537. CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);
  3538. usleep_range(50, 100);
  3539. count++;
  3540. }
  3541. dprintk(CVP_PWR,
  3542. "DBLP Release: lpi_status %d(count %d)\n",
  3543. lpi_status, count);
  3544. if (count == max_count) {
  3545. dprintk(CVP_WARN,
  3546. "DBLP Release: lpi_status %x\n", lpi_status);
  3547. }
  3548. /* HPG 6.1.2 Step 6 */
  3549. __disable_unprepare_clks(device);
  3550. /*
  3551. * HPG 6.1.2 Step 7 & 8
  3552. * per new HPG update, core clock reset will be unnecessary
  3553. */
  3554. if (__unvote_buses(device))
  3555. dprintk(CVP_WARN, "Failed to unvote for buses\n");
  3556. /* HPG 6.1.2 Step 5 */
  3557. if (__disable_regulators(device))
  3558. dprintk(CVP_WARN, "Failed to disable regulators\n");
  3559. /*Do not access registers after this point!*/
  3560. device->power_enabled = false;
  3561. }
  3562. static inline int __resume(struct iris_hfi_device *device)
  3563. {
  3564. int rc = 0;
  3565. u32 flags = 0, reg_gdsc, reg_cbcr;
  3566. if (!device) {
  3567. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  3568. return -EINVAL;
  3569. } else if (device->power_enabled) {
  3570. goto exit;
  3571. } else if (!__core_in_valid_state(device)) {
  3572. dprintk(CVP_PWR, "iris_hfi_device in deinit state.");
  3573. return -EINVAL;
  3574. }
  3575. dprintk(CVP_PWR, "Resuming from power collapse\n");
  3576. rc = __iris_power_on(device);
  3577. if (rc) {
  3578. dprintk(CVP_ERR, "Failed to power on cvp\n");
  3579. goto err_iris_power_on;
  3580. }
  3581. reg_gdsc = __read_register(device, CVP_CC_MVS1C_GDSCR);
  3582. reg_cbcr = __read_register(device, CVP_CC_MVS1C_CBCR);
  3583. if (!(reg_gdsc & 0x80000000) || (reg_cbcr & 0x80000000))
  3584. dprintk(CVP_ERR, "CVP power on failed gdsc %x cbcr %x\n",
  3585. reg_gdsc, reg_cbcr);
  3586. /* Reboot the firmware */
  3587. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESUME);
  3588. if (rc) {
  3589. dprintk(CVP_ERR, "Failed to resume cvp core %d\n", rc);
  3590. goto err_set_cvp_state;
  3591. }
  3592. __setup_ucregion_memory_map(device);
  3593. /* Wait for boot completion */
  3594. rc = __boot_firmware(device);
  3595. if (rc) {
  3596. dprintk(CVP_ERR, "Failed to reset cvp core\n");
  3597. goto err_reset_core;
  3598. }
  3599. /*
  3600. * Work around for H/W bug, need to reprogram these registers once
  3601. * firmware is out reset
  3602. */
  3603. __set_threshold_registers(device);
  3604. if (device->res->pm_qos_latency_us)
  3605. cpu_latency_qos_add_request(&device->qos,
  3606. device->res->pm_qos_latency_us);
  3607. __sys_set_debug(device, msm_cvp_fw_debug);
  3608. __enable_subcaches(device);
  3609. __set_subcaches(device);
  3610. __dsp_resume(device, flags);
  3611. dprintk(CVP_PWR, "Resumed from power collapse\n");
  3612. exit:
  3613. /* Don't reset skip_pc_count for SYS_PC_PREP cmd */
  3614. if (device->last_packet_type != HFI_CMD_SYS_PC_PREP)
  3615. device->skip_pc_count = 0;
  3616. return rc;
  3617. err_reset_core:
  3618. __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  3619. err_set_cvp_state:
  3620. call_iris_op(device, power_off, device);
  3621. err_iris_power_on:
  3622. dprintk(CVP_ERR, "Failed to resume from power collapse\n");
  3623. return rc;
  3624. }
  3625. static int __load_fw(struct iris_hfi_device *device)
  3626. {
  3627. int rc = 0;
  3628. /* Initialize resources */
  3629. rc = __init_resources(device, device->res);
  3630. if (rc) {
  3631. dprintk(CVP_ERR, "Failed to init resources: %d\n", rc);
  3632. goto fail_init_res;
  3633. }
  3634. rc = __initialize_packetization(device);
  3635. if (rc) {
  3636. dprintk(CVP_ERR, "Failed to initialize packetization\n");
  3637. goto fail_init_pkt;
  3638. }
  3639. rc = __iris_power_on(device);
  3640. if (rc) {
  3641. dprintk(CVP_ERR, "Failed to power on iris in in load_fw\n");
  3642. goto fail_iris_power_on;
  3643. }
  3644. if ((!device->res->use_non_secure_pil && !device->res->firmware_base)
  3645. || device->res->use_non_secure_pil) {
  3646. rc = load_cvp_fw_impl(device);
  3647. if (rc)
  3648. goto fail_load_fw;
  3649. }
  3650. return rc;
  3651. fail_load_fw:
  3652. call_iris_op(device, power_off, device);
  3653. fail_iris_power_on:
  3654. fail_init_pkt:
  3655. __deinit_resources(device);
  3656. fail_init_res:
  3657. return rc;
  3658. }
  3659. static void __unload_fw(struct iris_hfi_device *device)
  3660. {
  3661. if (!device->resources.fw.cookie)
  3662. return;
  3663. cancel_delayed_work(&iris_hfi_pm_work);
  3664. if (device->state != IRIS_STATE_DEINIT)
  3665. flush_workqueue(device->iris_pm_workq);
  3666. unload_cvp_fw_impl(device);
  3667. __interface_queues_release(device);
  3668. call_iris_op(device, power_off, device);
  3669. __deinit_resources(device);
  3670. dprintk(CVP_WARN, "Firmware unloaded\n");
  3671. }
  3672. static int iris_hfi_get_fw_info(void *dev, struct cvp_hal_fw_info *fw_info)
  3673. {
  3674. int i = 0;
  3675. struct iris_hfi_device *device = dev;
  3676. if (!device || !fw_info) {
  3677. dprintk(CVP_ERR,
  3678. "%s Invalid parameter: device = %pK fw_info = %pK\n",
  3679. __func__, device, fw_info);
  3680. return -EINVAL;
  3681. }
  3682. mutex_lock(&device->lock);
  3683. while (cvp_driver->fw_version[i++] != 'V' && i < CVP_VERSION_LENGTH)
  3684. ;
  3685. if (i == CVP_VERSION_LENGTH - 1) {
  3686. dprintk(CVP_WARN, "Iris version string is not proper\n");
  3687. fw_info->version[0] = '\0';
  3688. goto fail_version_string;
  3689. }
  3690. memcpy(&fw_info->version[0], &cvp_driver->fw_version[0],
  3691. CVP_VERSION_LENGTH);
  3692. fw_info->version[CVP_VERSION_LENGTH - 1] = '\0';
  3693. fail_version_string:
  3694. dprintk(CVP_CORE, "F/W version retrieved : %s\n", fw_info->version);
  3695. fw_info->base_addr = device->cvp_hal_data->firmware_base;
  3696. fw_info->register_base = device->res->register_base;
  3697. fw_info->register_size = device->cvp_hal_data->register_size;
  3698. fw_info->irq = device->cvp_hal_data->irq;
  3699. mutex_unlock(&device->lock);
  3700. return 0;
  3701. }
  3702. static int iris_hfi_get_core_capabilities(void *dev)
  3703. {
  3704. dprintk(CVP_CORE, "%s not supported yet!\n", __func__);
  3705. return 0;
  3706. }
  3707. static u32 cvp_arp_test_regs[16];
  3708. static u32 cvp_dma_test_regs[512];
  3709. static const char * const mid_names[16] = {
  3710. "CVP_FW",
  3711. "ARP_DATA",
  3712. "CVP_OD_NON_PIXEL",
  3713. "CVP_OD_ORIG_PIXEL",
  3714. "CVP_OD_WR_PIXEL",
  3715. "CVP_MPU_ORIG_PIXEL",
  3716. "CVP_MPU_REF_PIXEL",
  3717. "CVP_MPU_NON_PIXEL",
  3718. "CVP_MPU_DFS",
  3719. "CVP_FDU_NON_PIXEL",
  3720. "CVP_FDU_PIXEL",
  3721. "CVP_ICA_PIXEL",
  3722. "Invalid",
  3723. "Invalid",
  3724. "Invalid",
  3725. "Invalid"
  3726. };
  3727. static void __print_reg_details(u32 val)
  3728. {
  3729. u32 mid, sid;
  3730. mid = (val >> 5) & 0xF;
  3731. sid = (val >> 2) & 0x7;
  3732. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
  3733. dprintk(CVP_ERR, "Sub-client:%s, SID: %d\n", mid_names[mid], sid);
  3734. }
  3735. static void __noc_error_info_iris2(struct iris_hfi_device *device)
  3736. {
  3737. u32 val = 0, regi, i;
  3738. val = __read_register(device, CVP_NOC_ERR_SWID_LOW_OFFS);
  3739. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_SWID_LOW: %#x\n", val);
  3740. val = __read_register(device, CVP_NOC_ERR_SWID_HIGH_OFFS);
  3741. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_SWID_HIGH: %#x\n", val);
  3742. val = __read_register(device, CVP_NOC_ERR_MAINCTL_LOW_OFFS);
  3743. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_MAINCTL_LOW: %#x\n", val);
  3744. val = __read_register(device, CVP_NOC_ERR_ERRVLD_LOW_OFFS);
  3745. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRVLD_LOW: %#x\n", val);
  3746. val = __read_register(device, CVP_NOC_ERR_ERRCLR_LOW_OFFS);
  3747. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRCLR_LOW: %#x\n", val);
  3748. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_LOW_OFFS);
  3749. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG0_LOW: %#x\n", val);
  3750. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_HIGH_OFFS);
  3751. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG0_HIGH: %#x\n", val);
  3752. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_LOW_OFFS);
  3753. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG1_LOW: %#x\n", val);
  3754. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_HIGH_OFFS);
  3755. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG1_HIGH: %#x\n", val);
  3756. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_LOW_OFFS);
  3757. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG2_LOW: %#x\n", val);
  3758. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_HIGH_OFFS);
  3759. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG2_HIGH: %#x\n", val);
  3760. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_LOW_OFFS);
  3761. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
  3762. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_HIGH_OFFS);
  3763. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG3_HIGH: %#x\n", val);
  3764. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_LOW_OFFS);
  3765. dprintk(CVP_ERR, "CVP_NOC__CORE_ERL_MAIN_SWID_LOW: %#x\n", val);
  3766. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_HIGH_OFFS);
  3767. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_SWID_HIGH: %#x\n", val);
  3768. val = __read_register(device, CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS);
  3769. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_MAINCTL_LOW: %#x\n", val);
  3770. val = __read_register(device, CVP_NOC_CORE_ERR_ERRVLD_LOW_OFFS);
  3771. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRVLD_LOW: %#x\n", val);
  3772. val = __read_register(device, CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS);
  3773. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRCLR_LOW: %#x\n", val);
  3774. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_LOW_OFFS);
  3775. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_LOW: %#x\n", val);
  3776. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_HIGH_OFFS);
  3777. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_HIGH: %#x\n", val);
  3778. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_LOW_OFFS);
  3779. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_LOW: %#x\n", val);
  3780. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_HIGH_OFFS);
  3781. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_HIGH: %#x\n", val);
  3782. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_LOW_OFFS);
  3783. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_LOW: %#x\n", val);
  3784. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_HIGH_OFFS);
  3785. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_HIGH: %#x\n", val);
  3786. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_LOW_OFFS);
  3787. __print_reg_details(val);
  3788. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_HIGH_OFFS);
  3789. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_HIGH: %#x\n", val);
  3790. #define CVP_SS_CLK_HALT 0x8
  3791. #define CVP_SS_CLK_EN 0xC
  3792. #define CVP_SS_ARP_TEST_BUS_CONTROL 0x700
  3793. #define CVP_SS_ARP_TEST_BUS_REGISTER 0x704
  3794. #define CVP_DMA_TEST_BUS_CONTROL 0x66A0
  3795. #define CVP_DMA_TEST_BUS_REGISTER 0x66A4
  3796. #define CVP_VPU_WRAPPER_CORE_CONFIG 0xB0088
  3797. __write_register(device, CVP_SS_CLK_HALT, 0);
  3798. __write_register(device, CVP_SS_CLK_EN, 0x3f);
  3799. __write_register(device, CVP_VPU_WRAPPER_CORE_CONFIG, 0);
  3800. for (i = 0; i < 15; i++) {
  3801. regi = 0xC0000000 + i;
  3802. __write_register(device, CVP_SS_ARP_TEST_BUS_CONTROL, regi);
  3803. val = __read_register(device, CVP_SS_ARP_TEST_BUS_REGISTER);
  3804. cvp_arp_test_regs[i] = val;
  3805. dprintk(CVP_ERR, "ARP_CTL:%x - %x\n", regi, val);
  3806. }
  3807. for (i = 0; i < 512; i++) {
  3808. regi = 0x40000000 + i;
  3809. __write_register(device, CVP_DMA_TEST_BUS_CONTROL, regi);
  3810. val = __read_register(device, CVP_DMA_TEST_BUS_REGISTER);
  3811. cvp_dma_test_regs[i] = val;
  3812. dprintk(CVP_ERR, "DMA_CTL:%x - %x\n", regi, val);
  3813. }
  3814. }
  3815. static int iris_hfi_noc_error_info(void *dev)
  3816. {
  3817. struct iris_hfi_device *device;
  3818. if (!dev) {
  3819. dprintk(CVP_ERR, "%s: null device\n", __func__);
  3820. return -EINVAL;
  3821. }
  3822. device = dev;
  3823. mutex_lock(&device->lock);
  3824. dprintk(CVP_ERR, "%s: non error information\n", __func__);
  3825. call_iris_op(device, noc_error_info, device);
  3826. mutex_unlock(&device->lock);
  3827. return 0;
  3828. }
  3829. static int __initialize_packetization(struct iris_hfi_device *device)
  3830. {
  3831. int rc = 0;
  3832. if (!device || !device->res) {
  3833. dprintk(CVP_ERR, "%s - invalid param\n", __func__);
  3834. return -EINVAL;
  3835. }
  3836. device->packetization_type = HFI_PACKETIZATION_4XX;
  3837. device->pkt_ops = cvp_hfi_get_pkt_ops_handle(
  3838. device->packetization_type);
  3839. if (!device->pkt_ops) {
  3840. rc = -EINVAL;
  3841. dprintk(CVP_ERR, "Failed to get pkt_ops handle\n");
  3842. }
  3843. return rc;
  3844. }
  3845. void __init_cvp_ops(struct iris_hfi_device *device)
  3846. {
  3847. device->vpu_ops = &iris2_ops;
  3848. }
  3849. static struct iris_hfi_device *__add_device(u32 device_id,
  3850. struct msm_cvp_platform_resources *res,
  3851. hfi_cmd_response_callback callback)
  3852. {
  3853. struct iris_hfi_device *hdevice = NULL;
  3854. int rc = 0;
  3855. if (!res || !callback) {
  3856. dprintk(CVP_ERR, "Invalid Parameters\n");
  3857. return NULL;
  3858. }
  3859. dprintk(CVP_INFO, "%s: device_id: %d\n", __func__, device_id);
  3860. hdevice = kzalloc(sizeof(*hdevice), GFP_KERNEL);
  3861. if (!hdevice) {
  3862. dprintk(CVP_ERR, "failed to allocate new device\n");
  3863. goto exit;
  3864. }
  3865. hdevice->response_pkt = kmalloc_array(cvp_max_packets,
  3866. sizeof(*hdevice->response_pkt), GFP_KERNEL);
  3867. if (!hdevice->response_pkt) {
  3868. dprintk(CVP_ERR, "failed to allocate response_pkt\n");
  3869. goto err_cleanup;
  3870. }
  3871. hdevice->raw_packet =
  3872. kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  3873. if (!hdevice->raw_packet) {
  3874. dprintk(CVP_ERR, "failed to allocate raw packet\n");
  3875. goto err_cleanup;
  3876. }
  3877. rc = __init_regs_and_interrupts(hdevice, res);
  3878. if (rc)
  3879. goto err_cleanup;
  3880. hdevice->res = res;
  3881. hdevice->device_id = device_id;
  3882. hdevice->callback = callback;
  3883. __init_cvp_ops(hdevice);
  3884. hdevice->cvp_workq = create_singlethread_workqueue(
  3885. "msm_cvp_workerq_iris");
  3886. if (!hdevice->cvp_workq) {
  3887. dprintk(CVP_ERR, ": create cvp workq failed\n");
  3888. goto err_cleanup;
  3889. }
  3890. hdevice->iris_pm_workq = create_singlethread_workqueue(
  3891. "pm_workerq_iris");
  3892. if (!hdevice->iris_pm_workq) {
  3893. dprintk(CVP_ERR, ": create pm workq failed\n");
  3894. goto err_cleanup;
  3895. }
  3896. mutex_init(&hdevice->lock);
  3897. INIT_LIST_HEAD(&hdevice->sess_head);
  3898. return hdevice;
  3899. err_cleanup:
  3900. if (hdevice->iris_pm_workq)
  3901. destroy_workqueue(hdevice->iris_pm_workq);
  3902. if (hdevice->cvp_workq)
  3903. destroy_workqueue(hdevice->cvp_workq);
  3904. kfree(hdevice->response_pkt);
  3905. kfree(hdevice->raw_packet);
  3906. kfree(hdevice);
  3907. exit:
  3908. return NULL;
  3909. }
  3910. static struct iris_hfi_device *__get_device(u32 device_id,
  3911. struct msm_cvp_platform_resources *res,
  3912. hfi_cmd_response_callback callback)
  3913. {
  3914. if (!res || !callback) {
  3915. dprintk(CVP_ERR, "Invalid params: %pK %pK\n", res, callback);
  3916. return NULL;
  3917. }
  3918. return __add_device(device_id, res, callback);
  3919. }
  3920. void cvp_iris_hfi_delete_device(void *device)
  3921. {
  3922. struct msm_cvp_core *core;
  3923. struct iris_hfi_device *dev = NULL;
  3924. if (!device)
  3925. return;
  3926. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  3927. if (core)
  3928. dev = core->device->hfi_device_data;
  3929. if (!dev)
  3930. return;
  3931. mutex_destroy(&dev->lock);
  3932. destroy_workqueue(dev->cvp_workq);
  3933. destroy_workqueue(dev->iris_pm_workq);
  3934. free_irq(dev->cvp_hal_data->irq, dev);
  3935. iounmap(dev->cvp_hal_data->register_base);
  3936. iounmap(dev->cvp_hal_data->gcc_reg_base);
  3937. kfree(dev->cvp_hal_data);
  3938. kfree(dev->response_pkt);
  3939. kfree(dev->raw_packet);
  3940. kfree(dev);
  3941. }
  3942. static int iris_hfi_validate_session(void *sess, const char *func)
  3943. {
  3944. struct cvp_hal_session *session = sess;
  3945. int rc = 0;
  3946. struct iris_hfi_device *device;
  3947. if (!session || !session->device) {
  3948. dprintk(CVP_ERR, " %s Invalid Params %pK\n", __func__, session);
  3949. return -EINVAL;
  3950. }
  3951. device = session->device;
  3952. mutex_lock(&device->lock);
  3953. if (!__is_session_valid(device, session, func))
  3954. rc = -ECONNRESET;
  3955. mutex_unlock(&device->lock);
  3956. return rc;
  3957. }
  3958. static void iris_init_hfi_callbacks(struct cvp_hfi_device *hdev)
  3959. {
  3960. hdev->core_init = iris_hfi_core_init;
  3961. hdev->core_release = iris_hfi_core_release;
  3962. hdev->core_trigger_ssr = iris_hfi_core_trigger_ssr;
  3963. hdev->session_init = iris_hfi_session_init;
  3964. hdev->session_end = iris_hfi_session_end;
  3965. hdev->session_abort = iris_hfi_session_abort;
  3966. hdev->session_clean = iris_hfi_session_clean;
  3967. hdev->session_set_buffers = iris_hfi_session_set_buffers;
  3968. hdev->session_release_buffers = iris_hfi_session_release_buffers;
  3969. hdev->session_send = iris_hfi_session_send;
  3970. hdev->session_flush = iris_hfi_session_flush;
  3971. hdev->scale_clocks = iris_hfi_scale_clocks;
  3972. hdev->vote_bus = iris_hfi_vote_buses;
  3973. hdev->get_fw_info = iris_hfi_get_fw_info;
  3974. hdev->get_core_capabilities = iris_hfi_get_core_capabilities;
  3975. hdev->suspend = iris_hfi_suspend;
  3976. hdev->resume = iris_hfi_resume;
  3977. hdev->flush_debug_queue = iris_hfi_flush_debug_queue;
  3978. hdev->noc_error_info = iris_hfi_noc_error_info;
  3979. hdev->validate_session = iris_hfi_validate_session;
  3980. }
  3981. int cvp_iris_hfi_initialize(struct cvp_hfi_device *hdev, u32 device_id,
  3982. struct msm_cvp_platform_resources *res,
  3983. hfi_cmd_response_callback callback)
  3984. {
  3985. int rc = 0;
  3986. if (!hdev || !res || !callback) {
  3987. dprintk(CVP_ERR, "Invalid params: %pK %pK %pK\n",
  3988. hdev, res, callback);
  3989. rc = -EINVAL;
  3990. goto err_iris_hfi_init;
  3991. }
  3992. hdev->hfi_device_data = __get_device(device_id, res, callback);
  3993. if (IS_ERR_OR_NULL(hdev->hfi_device_data)) {
  3994. rc = PTR_ERR(hdev->hfi_device_data) ?: -EINVAL;
  3995. goto err_iris_hfi_init;
  3996. }
  3997. iris_init_hfi_callbacks(hdev);
  3998. err_iris_hfi_init:
  3999. return rc;
  4000. }