wcd938x.c 104 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #include "wcd938x.h"
  25. #define WCD938X_DRV_NAME "wcd938x_codec"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD938X_VARIANT_ENTRY_SIZE 32
  28. #define WCD938X_VERSION_1_0 1
  29. #define WCD938X_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_AUX 1
  31. #define ADC_MODE_VAL_HIFI 0x01
  32. #define ADC_MODE_VAL_LO_HIF 0x02
  33. #define ADC_MODE_VAL_NORMAL 0x03
  34. #define ADC_MODE_VAL_LP 0x05
  35. #define ADC_MODE_VAL_ULP1 0x09
  36. #define ADC_MODE_VAL_ULP2 0x0B
  37. enum {
  38. CODEC_TX = 0,
  39. CODEC_RX,
  40. };
  41. enum {
  42. WCD_ADC1 = 0,
  43. WCD_ADC2,
  44. WCD_ADC3,
  45. WCD_ADC4,
  46. ALLOW_BUCK_DISABLE,
  47. HPH_COMP_DELAY,
  48. HPH_PA_DELAY,
  49. AMIC2_BCS_ENABLE,
  50. };
  51. enum {
  52. ADC_MODE_INVALID = 0,
  53. ADC_MODE_HIFI,
  54. ADC_MODE_LO_HIF,
  55. ADC_MODE_NORMAL,
  56. ADC_MODE_LP,
  57. ADC_MODE_ULP1,
  58. ADC_MODE_ULP2,
  59. };
  60. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  61. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  62. static int wcd938x_handle_post_irq(void *data);
  63. static int wcd938x_reset(struct device *dev);
  64. static int wcd938x_reset_low(struct device *dev);
  65. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  66. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  67. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  68. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  69. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  70. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  71. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  86. };
  87. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  88. .name = "wcd938x",
  89. .irqs = wcd938x_irqs,
  90. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  91. .num_regs = 3,
  92. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  93. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  94. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  95. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  96. .use_ack = 1,
  97. .runtime_pm = false,
  98. .handle_post_irq = wcd938x_handle_post_irq,
  99. .irq_drv_data = NULL,
  100. };
  101. static int wcd938x_handle_post_irq(void *data)
  102. {
  103. struct wcd938x_priv *wcd938x = data;
  104. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  105. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  106. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  107. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  108. wcd938x->tx_swr_dev->slave_irq_pending =
  109. ((sts1 || sts2 || sts3) ? true : false);
  110. return IRQ_HANDLED;
  111. }
  112. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  113. {
  114. int ret = 0;
  115. int bank = 0;
  116. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  117. if (ret)
  118. return -EINVAL;
  119. return ((bank & 0x40) ? 1: 0);
  120. }
  121. static int wcd938x_swr_slv_set_host_clk_div2(struct swr_device *dev,
  122. u8 devnum, int bank)
  123. {
  124. u8 val = (bank ? 1 : 0);
  125. return (swr_write(dev, devnum,
  126. (SWR_SCP_HOST_CLK_DIV2_CTL_BANK + (0x10 * bank)), &val));
  127. }
  128. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  129. int mode, int bank)
  130. {
  131. u8 mask = (bank ? 0xF0 : 0x0F);
  132. u8 val = 0;
  133. if ((mode == ADC_MODE_ULP1) || (mode == ADC_MODE_ULP2))
  134. val = (bank ? 0x60 : 0x06);
  135. else
  136. val = 0x00;
  137. snd_soc_component_update_bits(component,
  138. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  139. mask, val);
  140. return 0;
  141. }
  142. static int wcd938x_init_reg(struct snd_soc_component *component)
  143. {
  144. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  145. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  146. /* 1 msec delay as per HW requirement */
  147. usleep_range(1000, 1010);
  148. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  149. /* 1 msec delay as per HW requirement */
  150. usleep_range(1000, 1010);
  151. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  152. 0x10, 0x00);
  153. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  154. 0xF0, 0x80);
  155. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  156. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  157. /* 10 msec delay as per HW requirement */
  158. usleep_range(10000, 10010);
  159. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  160. snd_soc_component_update_bits(component,
  161. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  162. 0xF0, 0x00);
  163. snd_soc_component_update_bits(component,
  164. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  165. 0x1F, 0x15);
  166. snd_soc_component_update_bits(component,
  167. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  168. 0x1F, 0x15);
  169. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  170. 0xC0, 0x80);
  171. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  172. 0x02, 0x02);
  173. snd_soc_component_update_bits(component,
  174. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  175. 0xFF, 0x14);
  176. snd_soc_component_update_bits(component,
  177. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  178. 0x1F, 0x08);
  179. snd_soc_component_update_bits(component,
  180. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  181. snd_soc_component_update_bits(component,
  182. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  183. snd_soc_component_update_bits(component,
  184. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  185. snd_soc_component_update_bits(component,
  186. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  187. snd_soc_component_update_bits(component,
  188. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  189. snd_soc_component_update_bits(component,
  190. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  191. snd_soc_component_update_bits(component,
  192. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  193. snd_soc_component_update_bits(component,
  194. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  195. snd_soc_component_update_bits(component,
  196. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  197. snd_soc_component_update_bits(component,
  198. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  199. return 0;
  200. }
  201. static int wcd938x_set_port_params(struct snd_soc_component *component,
  202. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  203. u8 *ch_mask, u32 *ch_rate,
  204. u8 *port_type, u8 path)
  205. {
  206. int i, j;
  207. u8 num_ports = 0;
  208. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  209. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  210. switch (path) {
  211. case CODEC_RX:
  212. map = &wcd938x->rx_port_mapping;
  213. num_ports = wcd938x->num_rx_ports;
  214. break;
  215. case CODEC_TX:
  216. map = &wcd938x->tx_port_mapping;
  217. num_ports = wcd938x->num_tx_ports;
  218. break;
  219. default:
  220. dev_err(component->dev, "%s Invalid path selected %u\n",
  221. __func__, path);
  222. return -EINVAL;
  223. }
  224. for (i = 0; i <= num_ports; i++) {
  225. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  226. if ((*map)[i][j].slave_port_type == slv_prt_type)
  227. goto found;
  228. }
  229. }
  230. found:
  231. if (i > num_ports || j == MAX_CH_PER_PORT) {
  232. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  233. __func__, slv_prt_type);
  234. return -EINVAL;
  235. }
  236. *port_id = i;
  237. *num_ch = (*map)[i][j].num_ch;
  238. *ch_mask = (*map)[i][j].ch_mask;
  239. *ch_rate = (*map)[i][j].ch_rate;
  240. *port_type = (*map)[i][j].master_port_type;
  241. return 0;
  242. }
  243. static int wcd938x_parse_port_mapping(struct device *dev,
  244. char *prop, u8 path)
  245. {
  246. u32 *dt_array, map_size, map_length;
  247. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  248. u32 slave_port_type, master_port_type;
  249. u32 i, ch_iter = 0;
  250. int ret = 0;
  251. u8 *num_ports = NULL;
  252. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  253. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  254. switch (path) {
  255. case CODEC_RX:
  256. map = &wcd938x->rx_port_mapping;
  257. num_ports = &wcd938x->num_rx_ports;
  258. break;
  259. case CODEC_TX:
  260. map = &wcd938x->tx_port_mapping;
  261. num_ports = &wcd938x->num_tx_ports;
  262. break;
  263. default:
  264. dev_err(dev, "%s Invalid path selected %u\n",
  265. __func__, path);
  266. return -EINVAL;
  267. }
  268. if (!of_find_property(dev->of_node, prop,
  269. &map_size)) {
  270. dev_err(dev, "missing port mapping prop %s\n", prop);
  271. ret = -EINVAL;
  272. goto err_port_map;
  273. }
  274. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  275. dt_array = kzalloc(map_size, GFP_KERNEL);
  276. if (!dt_array) {
  277. ret = -ENOMEM;
  278. goto err_alloc;
  279. }
  280. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  281. NUM_SWRS_DT_PARAMS * map_length);
  282. if (ret) {
  283. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  284. __func__, prop);
  285. goto err_pdata_fail;
  286. }
  287. for (i = 0; i < map_length; i++) {
  288. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  289. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  290. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  291. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  292. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  293. if (port_num != old_port_num)
  294. ch_iter = 0;
  295. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  296. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  297. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  298. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  299. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  300. old_port_num = port_num;
  301. }
  302. *num_ports = port_num;
  303. kfree(dt_array);
  304. return 0;
  305. err_pdata_fail:
  306. kfree(dt_array);
  307. err_alloc:
  308. err_port_map:
  309. return ret;
  310. }
  311. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  312. u8 slv_port_type, u8 enable)
  313. {
  314. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  315. u8 port_id, num_ch, ch_mask, port_type;
  316. u32 ch_rate;
  317. u8 num_port = 1;
  318. int ret = 0;
  319. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  320. &num_ch, &ch_mask, &ch_rate,
  321. &port_type, CODEC_TX);
  322. if (ret)
  323. return ret;
  324. if (enable)
  325. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  326. num_port, &ch_mask, &ch_rate,
  327. &num_ch, &port_type);
  328. else
  329. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  330. num_port, &ch_mask, &port_type);
  331. return ret;
  332. }
  333. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  334. u8 slv_port_type, u8 enable)
  335. {
  336. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  337. u8 port_id, num_ch, ch_mask, port_type;
  338. u32 ch_rate;
  339. u8 num_port = 1;
  340. int ret = 0;
  341. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  342. &num_ch, &ch_mask, &ch_rate,
  343. &port_type, CODEC_RX);
  344. if (ret)
  345. return ret;
  346. if (enable)
  347. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  348. num_port, &ch_mask, &ch_rate,
  349. &num_ch, &port_type);
  350. else
  351. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  352. num_port, &ch_mask, &port_type);
  353. return ret;
  354. }
  355. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  356. {
  357. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  358. if (wcd938x->rx_clk_cnt == 0) {
  359. snd_soc_component_update_bits(component,
  360. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  361. snd_soc_component_update_bits(component,
  362. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  363. snd_soc_component_update_bits(component,
  364. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  365. snd_soc_component_update_bits(component,
  366. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  367. snd_soc_component_update_bits(component,
  368. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  369. snd_soc_component_update_bits(component,
  370. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  371. snd_soc_component_update_bits(component,
  372. WCD938X_AUX_AUXPA, 0x10, 0x10);
  373. }
  374. wcd938x->rx_clk_cnt++;
  375. return 0;
  376. }
  377. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  378. {
  379. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  380. wcd938x->rx_clk_cnt--;
  381. if (wcd938x->rx_clk_cnt == 0) {
  382. snd_soc_component_update_bits(component,
  383. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  384. snd_soc_component_update_bits(component,
  385. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  386. snd_soc_component_update_bits(component,
  387. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  388. snd_soc_component_update_bits(component,
  389. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  390. snd_soc_component_update_bits(component,
  391. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  392. }
  393. return 0;
  394. }
  395. /*
  396. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  397. * @component: handle to snd_soc_component *
  398. *
  399. * return wcd938x_mbhc handle or error code in case of failure
  400. */
  401. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  402. {
  403. struct wcd938x_priv *wcd938x;
  404. if (!component) {
  405. pr_err("%s: Invalid params, NULL component\n", __func__);
  406. return NULL;
  407. }
  408. wcd938x = snd_soc_component_get_drvdata(component);
  409. if (!wcd938x) {
  410. pr_err("%s: wcd938x is NULL\n", __func__);
  411. return NULL;
  412. }
  413. return wcd938x->mbhc;
  414. }
  415. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  416. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  417. struct snd_kcontrol *kcontrol,
  418. int event)
  419. {
  420. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  421. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  422. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  423. w->name, event);
  424. switch (event) {
  425. case SND_SOC_DAPM_PRE_PMU:
  426. wcd938x_rx_clk_enable(component);
  427. snd_soc_component_update_bits(component,
  428. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  429. snd_soc_component_update_bits(component,
  430. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  431. snd_soc_component_update_bits(component,
  432. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  433. break;
  434. case SND_SOC_DAPM_POST_PMU:
  435. snd_soc_component_update_bits(component,
  436. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  437. if (wcd938x->comp1_enable) {
  438. snd_soc_component_update_bits(component,
  439. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  440. /* 5msec compander delay as per HW requirement */
  441. if (!wcd938x->comp2_enable ||
  442. (snd_soc_component_read32(component,
  443. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  444. usleep_range(5000, 5010);
  445. snd_soc_component_update_bits(component,
  446. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  447. } else {
  448. snd_soc_component_update_bits(component,
  449. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  450. 0x02, 0x00);
  451. snd_soc_component_update_bits(component,
  452. WCD938X_HPH_L_EN, 0x20, 0x20);
  453. }
  454. break;
  455. case SND_SOC_DAPM_POST_PMD:
  456. snd_soc_component_update_bits(component,
  457. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  458. 0x0F, 0x01);
  459. break;
  460. }
  461. return 0;
  462. }
  463. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  464. struct snd_kcontrol *kcontrol,
  465. int event)
  466. {
  467. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  468. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  469. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  470. w->name, event);
  471. switch (event) {
  472. case SND_SOC_DAPM_PRE_PMU:
  473. wcd938x_rx_clk_enable(component);
  474. snd_soc_component_update_bits(component,
  475. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  476. snd_soc_component_update_bits(component,
  477. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  478. snd_soc_component_update_bits(component,
  479. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  480. break;
  481. case SND_SOC_DAPM_POST_PMU:
  482. snd_soc_component_update_bits(component,
  483. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  484. if (wcd938x->comp2_enable) {
  485. snd_soc_component_update_bits(component,
  486. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  487. /* 5msec compander delay as per HW requirement */
  488. if (!wcd938x->comp1_enable ||
  489. (snd_soc_component_read32(component,
  490. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  491. usleep_range(5000, 5010);
  492. snd_soc_component_update_bits(component,
  493. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  494. } else {
  495. snd_soc_component_update_bits(component,
  496. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  497. 0x01, 0x00);
  498. snd_soc_component_update_bits(component,
  499. WCD938X_HPH_R_EN, 0x20, 0x20);
  500. }
  501. break;
  502. case SND_SOC_DAPM_POST_PMD:
  503. snd_soc_component_update_bits(component,
  504. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  505. 0x0F, 0x01);
  506. break;
  507. }
  508. return 0;
  509. }
  510. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  511. struct snd_kcontrol *kcontrol,
  512. int event)
  513. {
  514. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  515. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  516. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  517. w->name, event);
  518. switch (event) {
  519. case SND_SOC_DAPM_PRE_PMU:
  520. wcd938x_rx_clk_enable(component);
  521. wcd938x->ear_rx_path =
  522. snd_soc_component_read32(
  523. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  524. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  525. snd_soc_component_update_bits(component,
  526. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  527. snd_soc_component_update_bits(component,
  528. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  529. snd_soc_component_update_bits(component,
  530. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  531. snd_soc_component_update_bits(component,
  532. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  533. } else {
  534. snd_soc_component_update_bits(component,
  535. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  536. snd_soc_component_update_bits(component,
  537. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  538. snd_soc_component_update_bits(component,
  539. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  540. }
  541. /* 5 msec delay as per HW requirement */
  542. usleep_range(5000, 5010);
  543. if (wcd938x->flyback_cur_det_disable == 0)
  544. snd_soc_component_update_bits(component,
  545. WCD938X_FLYBACK_EN,
  546. 0x04, 0x00);
  547. wcd938x->flyback_cur_det_disable++;
  548. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  549. WCD_CLSH_EVENT_PRE_DAC,
  550. WCD_CLSH_STATE_EAR,
  551. wcd938x->hph_mode);
  552. break;
  553. case SND_SOC_DAPM_POST_PMD:
  554. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  555. snd_soc_component_update_bits(component,
  556. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  557. }
  558. snd_soc_component_update_bits(component,
  559. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  560. snd_soc_component_update_bits(component,
  561. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  562. break;
  563. };
  564. return 0;
  565. }
  566. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  567. struct snd_kcontrol *kcontrol,
  568. int event)
  569. {
  570. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  571. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  572. int ret = 0;
  573. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  574. w->name, event);
  575. switch (event) {
  576. case SND_SOC_DAPM_PRE_PMU:
  577. wcd938x_rx_clk_enable(component);
  578. snd_soc_component_update_bits(component,
  579. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  580. snd_soc_component_update_bits(component,
  581. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  582. snd_soc_component_update_bits(component,
  583. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  584. if (wcd938x->flyback_cur_det_disable == 0)
  585. snd_soc_component_update_bits(component,
  586. WCD938X_FLYBACK_EN,
  587. 0x04, 0x00);
  588. wcd938x->flyback_cur_det_disable++;
  589. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  590. WCD_CLSH_EVENT_PRE_DAC,
  591. WCD_CLSH_STATE_AUX,
  592. wcd938x->hph_mode);
  593. break;
  594. case SND_SOC_DAPM_POST_PMD:
  595. snd_soc_component_update_bits(component,
  596. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  597. break;
  598. };
  599. return ret;
  600. }
  601. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  602. struct snd_kcontrol *kcontrol,
  603. int event)
  604. {
  605. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  606. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  607. int ret = 0;
  608. int hph_mode = wcd938x->hph_mode;
  609. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  610. w->name, event);
  611. switch (event) {
  612. case SND_SOC_DAPM_PRE_PMU:
  613. if (wcd938x->ldoh)
  614. snd_soc_component_update_bits(component,
  615. WCD938X_LDOH_MODE,
  616. 0x80, 0x80);
  617. if (wcd938x->update_wcd_event)
  618. wcd938x->update_wcd_event(wcd938x->handle,
  619. WCD_BOLERO_EVT_RX_MUTE,
  620. (WCD_RX2 << 0x10 | 0x1));
  621. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  622. wcd938x->rx_swr_dev->dev_num,
  623. true);
  624. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  625. WCD_CLSH_EVENT_PRE_DAC,
  626. WCD_CLSH_STATE_HPHR,
  627. hph_mode);
  628. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  629. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  630. 0x10, 0x10);
  631. wcd_clsh_set_hph_mode(component, hph_mode);
  632. /* 100 usec delay as per HW requirement */
  633. usleep_range(100, 110);
  634. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  635. snd_soc_component_update_bits(component,
  636. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  637. break;
  638. case SND_SOC_DAPM_POST_PMU:
  639. /*
  640. * 7ms sleep is required if compander is enabled as per
  641. * HW requirement. If compander is disabled, then
  642. * 20ms delay is required.
  643. */
  644. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  645. if (!wcd938x->comp2_enable)
  646. usleep_range(20000, 20100);
  647. else
  648. usleep_range(7000, 7100);
  649. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  650. }
  651. snd_soc_component_update_bits(component,
  652. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  653. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  654. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  655. snd_soc_component_update_bits(component,
  656. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  657. if (wcd938x->update_wcd_event)
  658. wcd938x->update_wcd_event(wcd938x->handle,
  659. WCD_BOLERO_EVT_RX_MUTE,
  660. (WCD_RX2 << 0x10));
  661. wcd_enable_irq(&wcd938x->irq_info,
  662. WCD938X_IRQ_HPHR_PDM_WD_INT);
  663. break;
  664. case SND_SOC_DAPM_PRE_PMD:
  665. if (wcd938x->update_wcd_event)
  666. wcd938x->update_wcd_event(wcd938x->handle,
  667. WCD_BOLERO_EVT_RX_MUTE,
  668. (WCD_RX2 << 0x10 | 0x1));
  669. wcd_disable_irq(&wcd938x->irq_info,
  670. WCD938X_IRQ_HPHR_PDM_WD_INT);
  671. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  672. wcd938x->update_wcd_event(wcd938x->handle,
  673. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  674. (WCD_RX2 << 0x10));
  675. /*
  676. * 7ms sleep is required if compander is enabled as per
  677. * HW requirement. If compander is disabled, then
  678. * 20ms delay is required.
  679. */
  680. if (!wcd938x->comp2_enable)
  681. usleep_range(20000, 20100);
  682. else
  683. usleep_range(7000, 7100);
  684. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  685. 0x40, 0x00);
  686. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  687. WCD_EVENT_PRE_HPHR_PA_OFF,
  688. &wcd938x->mbhc->wcd_mbhc);
  689. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  690. break;
  691. case SND_SOC_DAPM_POST_PMD:
  692. /*
  693. * 7ms sleep is required if compander is enabled as per
  694. * HW requirement. If compander is disabled, then
  695. * 20ms delay is required.
  696. */
  697. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  698. if (!wcd938x->comp2_enable)
  699. usleep_range(20000, 20100);
  700. else
  701. usleep_range(7000, 7100);
  702. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  703. }
  704. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  705. WCD_EVENT_POST_HPHR_PA_OFF,
  706. &wcd938x->mbhc->wcd_mbhc);
  707. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  708. 0x10, 0x00);
  709. snd_soc_component_update_bits(component,
  710. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  711. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  712. WCD_CLSH_EVENT_POST_PA,
  713. WCD_CLSH_STATE_HPHR,
  714. hph_mode);
  715. if (wcd938x->ldoh)
  716. snd_soc_component_update_bits(component,
  717. WCD938X_LDOH_MODE,
  718. 0x80, 0x00);
  719. break;
  720. };
  721. return ret;
  722. }
  723. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  724. struct snd_kcontrol *kcontrol,
  725. int event)
  726. {
  727. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  728. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  729. int ret = 0;
  730. int hph_mode = wcd938x->hph_mode;
  731. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  732. w->name, event);
  733. switch (event) {
  734. case SND_SOC_DAPM_PRE_PMU:
  735. if (wcd938x->ldoh)
  736. snd_soc_component_update_bits(component,
  737. WCD938X_LDOH_MODE,
  738. 0x80, 0x80);
  739. if (wcd938x->update_wcd_event)
  740. wcd938x->update_wcd_event(wcd938x->handle,
  741. WCD_BOLERO_EVT_RX_MUTE,
  742. (WCD_RX1 << 0x10 | 0x01));
  743. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  744. wcd938x->rx_swr_dev->dev_num,
  745. true);
  746. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  747. WCD_CLSH_EVENT_PRE_DAC,
  748. WCD_CLSH_STATE_HPHL,
  749. hph_mode);
  750. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  751. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  752. 0x20, 0x20);
  753. wcd_clsh_set_hph_mode(component, hph_mode);
  754. /* 100 usec delay as per HW requirement */
  755. usleep_range(100, 110);
  756. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  757. snd_soc_component_update_bits(component,
  758. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  759. break;
  760. case SND_SOC_DAPM_POST_PMU:
  761. /*
  762. * 7ms sleep is required if compander is enabled as per
  763. * HW requirement. If compander is disabled, then
  764. * 20ms delay is required.
  765. */
  766. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  767. if (!wcd938x->comp1_enable)
  768. usleep_range(20000, 20100);
  769. else
  770. usleep_range(7000, 7100);
  771. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  772. }
  773. snd_soc_component_update_bits(component,
  774. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  775. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  776. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  777. snd_soc_component_update_bits(component,
  778. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  779. if (wcd938x->update_wcd_event)
  780. wcd938x->update_wcd_event(wcd938x->handle,
  781. WCD_BOLERO_EVT_RX_MUTE,
  782. (WCD_RX1 << 0x10));
  783. wcd_enable_irq(&wcd938x->irq_info,
  784. WCD938X_IRQ_HPHL_PDM_WD_INT);
  785. break;
  786. case SND_SOC_DAPM_PRE_PMD:
  787. if (wcd938x->update_wcd_event)
  788. wcd938x->update_wcd_event(wcd938x->handle,
  789. WCD_BOLERO_EVT_RX_MUTE,
  790. (WCD_RX1 << 0x10 | 0x1));
  791. wcd_disable_irq(&wcd938x->irq_info,
  792. WCD938X_IRQ_HPHL_PDM_WD_INT);
  793. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  794. wcd938x->update_wcd_event(wcd938x->handle,
  795. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  796. (WCD_RX1 << 0x10));
  797. /*
  798. * 7ms sleep is required if compander is enabled as per
  799. * HW requirement. If compander is disabled, then
  800. * 20ms delay is required.
  801. */
  802. if (!wcd938x->comp1_enable)
  803. usleep_range(20000, 20100);
  804. else
  805. usleep_range(7000, 7100);
  806. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  807. 0x80, 0x00);
  808. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  809. WCD_EVENT_PRE_HPHL_PA_OFF,
  810. &wcd938x->mbhc->wcd_mbhc);
  811. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  812. break;
  813. case SND_SOC_DAPM_POST_PMD:
  814. /*
  815. * 7ms sleep is required if compander is enabled as per
  816. * HW requirement. If compander is disabled, then
  817. * 20ms delay is required.
  818. */
  819. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  820. if (!wcd938x->comp1_enable)
  821. usleep_range(21000, 21100);
  822. else
  823. usleep_range(7000, 7100);
  824. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  825. }
  826. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  827. WCD_EVENT_POST_HPHL_PA_OFF,
  828. &wcd938x->mbhc->wcd_mbhc);
  829. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  830. 0x20, 0x00);
  831. snd_soc_component_update_bits(component,
  832. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  833. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  834. WCD_CLSH_EVENT_POST_PA,
  835. WCD_CLSH_STATE_HPHL,
  836. hph_mode);
  837. if (wcd938x->ldoh)
  838. snd_soc_component_update_bits(component,
  839. WCD938X_LDOH_MODE,
  840. 0x80, 0x00);
  841. break;
  842. };
  843. return ret;
  844. }
  845. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  846. struct snd_kcontrol *kcontrol,
  847. int event)
  848. {
  849. struct snd_soc_component *component =
  850. snd_soc_dapm_to_component(w->dapm);
  851. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  852. int hph_mode = wcd938x->hph_mode;
  853. int ret = 0;
  854. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  855. w->name, event);
  856. switch (event) {
  857. case SND_SOC_DAPM_PRE_PMU:
  858. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  859. wcd938x->rx_swr_dev->dev_num,
  860. true);
  861. snd_soc_component_update_bits(component,
  862. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  863. break;
  864. case SND_SOC_DAPM_POST_PMU:
  865. /* 1 msec delay as per HW requirement */
  866. usleep_range(1000, 1010);
  867. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  868. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  869. snd_soc_component_update_bits(component,
  870. WCD938X_ANA_RX_SUPPLIES,
  871. 0x02, 0x02);
  872. if (wcd938x->update_wcd_event)
  873. wcd938x->update_wcd_event(wcd938x->handle,
  874. WCD_BOLERO_EVT_RX_MUTE,
  875. (WCD_RX3 << 0x10));
  876. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  877. break;
  878. case SND_SOC_DAPM_PRE_PMD:
  879. wcd_disable_irq(&wcd938x->irq_info,
  880. WCD938X_IRQ_AUX_PDM_WD_INT);
  881. if (wcd938x->update_wcd_event)
  882. wcd938x->update_wcd_event(wcd938x->handle,
  883. WCD_BOLERO_EVT_RX_MUTE,
  884. (WCD_RX3 << 0x10 | 0x1));
  885. break;
  886. case SND_SOC_DAPM_POST_PMD:
  887. /* 1 msec delay as per HW requirement */
  888. usleep_range(1000, 1010);
  889. snd_soc_component_update_bits(component,
  890. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  891. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  892. WCD_CLSH_EVENT_POST_PA,
  893. WCD_CLSH_STATE_AUX,
  894. hph_mode);
  895. wcd938x->flyback_cur_det_disable--;
  896. if (wcd938x->flyback_cur_det_disable == 0)
  897. snd_soc_component_update_bits(component,
  898. WCD938X_FLYBACK_EN,
  899. 0x04, 0x04);
  900. break;
  901. };
  902. return ret;
  903. }
  904. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  905. struct snd_kcontrol *kcontrol,
  906. int event)
  907. {
  908. struct snd_soc_component *component =
  909. snd_soc_dapm_to_component(w->dapm);
  910. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  911. int hph_mode = wcd938x->hph_mode;
  912. int ret = 0;
  913. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  914. w->name, event);
  915. switch (event) {
  916. case SND_SOC_DAPM_PRE_PMU:
  917. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  918. wcd938x->rx_swr_dev->dev_num,
  919. true);
  920. /*
  921. * Enable watchdog interrupt for HPHL or AUX
  922. * depending on mux value
  923. */
  924. wcd938x->ear_rx_path =
  925. snd_soc_component_read32(
  926. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  927. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  928. snd_soc_component_update_bits(component,
  929. WCD938X_DIGITAL_PDM_WD_CTL2,
  930. 0x05, 0x05);
  931. else
  932. snd_soc_component_update_bits(component,
  933. WCD938X_DIGITAL_PDM_WD_CTL0,
  934. 0x17, 0x13);
  935. if (!wcd938x->comp1_enable)
  936. snd_soc_component_update_bits(component,
  937. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  938. break;
  939. case SND_SOC_DAPM_POST_PMU:
  940. /* 6 msec delay as per HW requirement */
  941. usleep_range(6000, 6010);
  942. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  943. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  944. snd_soc_component_update_bits(component,
  945. WCD938X_ANA_RX_SUPPLIES,
  946. 0x02, 0x02);
  947. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  948. if (wcd938x->update_wcd_event)
  949. wcd938x->update_wcd_event(wcd938x->handle,
  950. WCD_BOLERO_EVT_RX_MUTE,
  951. (WCD_RX3 << 0x10));
  952. wcd_enable_irq(&wcd938x->irq_info,
  953. WCD938X_IRQ_AUX_PDM_WD_INT);
  954. } else {
  955. if (wcd938x->update_wcd_event)
  956. wcd938x->update_wcd_event(wcd938x->handle,
  957. WCD_BOLERO_EVT_RX_MUTE,
  958. (WCD_RX1 << 0x10));
  959. wcd_enable_irq(&wcd938x->irq_info,
  960. WCD938X_IRQ_HPHL_PDM_WD_INT);
  961. }
  962. break;
  963. case SND_SOC_DAPM_PRE_PMD:
  964. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  965. wcd_disable_irq(&wcd938x->irq_info,
  966. WCD938X_IRQ_AUX_PDM_WD_INT);
  967. else
  968. wcd_disable_irq(&wcd938x->irq_info,
  969. WCD938X_IRQ_HPHL_PDM_WD_INT);
  970. if (wcd938x->update_wcd_event)
  971. wcd938x->update_wcd_event(wcd938x->handle,
  972. WCD_BOLERO_EVT_RX_MUTE,
  973. (WCD_RX1 << 0x10 | 0x1));
  974. break;
  975. case SND_SOC_DAPM_POST_PMD:
  976. if (!wcd938x->comp1_enable)
  977. snd_soc_component_update_bits(component,
  978. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  979. /* 7 msec delay as per HW requirement */
  980. usleep_range(7000, 7010);
  981. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  982. snd_soc_component_update_bits(component,
  983. WCD938X_DIGITAL_PDM_WD_CTL2,
  984. 0x05, 0x00);
  985. else
  986. snd_soc_component_update_bits(component,
  987. WCD938X_DIGITAL_PDM_WD_CTL0,
  988. 0x17, 0x00);
  989. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  990. WCD_CLSH_EVENT_POST_PA,
  991. WCD_CLSH_STATE_EAR,
  992. hph_mode);
  993. wcd938x->flyback_cur_det_disable--;
  994. if (wcd938x->flyback_cur_det_disable == 0)
  995. snd_soc_component_update_bits(component,
  996. WCD938X_FLYBACK_EN,
  997. 0x04, 0x04);
  998. break;
  999. };
  1000. return ret;
  1001. }
  1002. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1003. struct snd_kcontrol *kcontrol,
  1004. int event)
  1005. {
  1006. struct snd_soc_component *component =
  1007. snd_soc_dapm_to_component(w->dapm);
  1008. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1009. int mode = wcd938x->hph_mode;
  1010. int ret = 0;
  1011. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1012. w->name, event);
  1013. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1014. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1015. wcd938x_rx_connect_port(component, CLSH,
  1016. SND_SOC_DAPM_EVENT_ON(event));
  1017. }
  1018. if (SND_SOC_DAPM_EVENT_OFF(event))
  1019. ret = swr_slvdev_datapath_control(
  1020. wcd938x->rx_swr_dev,
  1021. wcd938x->rx_swr_dev->dev_num,
  1022. false);
  1023. return ret;
  1024. }
  1025. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1026. struct snd_kcontrol *kcontrol,
  1027. int event)
  1028. {
  1029. struct snd_soc_component *component =
  1030. snd_soc_dapm_to_component(w->dapm);
  1031. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1032. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1033. w->name, event);
  1034. switch (event) {
  1035. case SND_SOC_DAPM_PRE_PMU:
  1036. wcd938x_rx_connect_port(component, HPH_L, true);
  1037. if (wcd938x->comp1_enable)
  1038. wcd938x_rx_connect_port(component, COMP_L, true);
  1039. break;
  1040. case SND_SOC_DAPM_POST_PMD:
  1041. wcd938x_rx_connect_port(component, HPH_L, false);
  1042. if (wcd938x->comp1_enable)
  1043. wcd938x_rx_connect_port(component, COMP_L, false);
  1044. wcd938x_rx_clk_disable(component);
  1045. snd_soc_component_update_bits(component,
  1046. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1047. 0x01, 0x00);
  1048. break;
  1049. };
  1050. return 0;
  1051. }
  1052. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1053. struct snd_kcontrol *kcontrol, int event)
  1054. {
  1055. struct snd_soc_component *component =
  1056. snd_soc_dapm_to_component(w->dapm);
  1057. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1058. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1059. w->name, event);
  1060. switch (event) {
  1061. case SND_SOC_DAPM_PRE_PMU:
  1062. wcd938x_rx_connect_port(component, HPH_R, true);
  1063. if (wcd938x->comp2_enable)
  1064. wcd938x_rx_connect_port(component, COMP_R, true);
  1065. break;
  1066. case SND_SOC_DAPM_POST_PMD:
  1067. wcd938x_rx_connect_port(component, HPH_R, false);
  1068. if (wcd938x->comp2_enable)
  1069. wcd938x_rx_connect_port(component, COMP_R, false);
  1070. wcd938x_rx_clk_disable(component);
  1071. snd_soc_component_update_bits(component,
  1072. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1073. 0x02, 0x00);
  1074. break;
  1075. };
  1076. return 0;
  1077. }
  1078. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1079. struct snd_kcontrol *kcontrol,
  1080. int event)
  1081. {
  1082. struct snd_soc_component *component =
  1083. snd_soc_dapm_to_component(w->dapm);
  1084. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1085. w->name, event);
  1086. switch (event) {
  1087. case SND_SOC_DAPM_PRE_PMU:
  1088. wcd938x_rx_connect_port(component, LO, true);
  1089. break;
  1090. case SND_SOC_DAPM_POST_PMD:
  1091. wcd938x_rx_connect_port(component, LO, false);
  1092. /* 6 msec delay as per HW requirement */
  1093. usleep_range(6000, 6010);
  1094. wcd938x_rx_clk_disable(component);
  1095. snd_soc_component_update_bits(component,
  1096. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1097. break;
  1098. }
  1099. return 0;
  1100. }
  1101. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1102. struct snd_kcontrol *kcontrol,
  1103. int event)
  1104. {
  1105. struct snd_soc_component *component =
  1106. snd_soc_dapm_to_component(w->dapm);
  1107. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1108. u16 dmic_clk_reg, dmic_clk_en_reg;
  1109. s32 *dmic_clk_cnt;
  1110. u8 dmic_ctl_shift = 0;
  1111. u8 dmic_clk_shift = 0;
  1112. u8 dmic_clk_mask = 0;
  1113. u16 dmic2_left_en = 0;
  1114. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1115. w->name, event);
  1116. switch (w->shift) {
  1117. case 0:
  1118. case 1:
  1119. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1120. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1121. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1122. dmic_clk_mask = 0x0F;
  1123. dmic_clk_shift = 0x00;
  1124. dmic_ctl_shift = 0x00;
  1125. break;
  1126. case 2:
  1127. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1128. case 3:
  1129. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1130. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1131. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1132. dmic_clk_mask = 0xF0;
  1133. dmic_clk_shift = 0x04;
  1134. dmic_ctl_shift = 0x01;
  1135. break;
  1136. case 4:
  1137. case 5:
  1138. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1139. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1140. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1141. dmic_clk_mask = 0x0F;
  1142. dmic_clk_shift = 0x00;
  1143. dmic_ctl_shift = 0x02;
  1144. break;
  1145. case 6:
  1146. case 7:
  1147. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1148. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1149. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1150. dmic_clk_mask = 0xF0;
  1151. dmic_clk_shift = 0x04;
  1152. dmic_ctl_shift = 0x03;
  1153. break;
  1154. default:
  1155. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1156. __func__);
  1157. return -EINVAL;
  1158. };
  1159. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1160. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1161. switch (event) {
  1162. case SND_SOC_DAPM_PRE_PMU:
  1163. snd_soc_component_update_bits(component,
  1164. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1165. (0x01 << dmic_ctl_shift), 0x00);
  1166. /* 250us sleep as per HW requirement */
  1167. usleep_range(250, 260);
  1168. if (dmic2_left_en)
  1169. snd_soc_component_update_bits(component,
  1170. dmic2_left_en, 0x80, 0x80);
  1171. /* Setting DMIC clock rate to 2.4MHz */
  1172. snd_soc_component_update_bits(component,
  1173. dmic_clk_reg, dmic_clk_mask,
  1174. (0x03 << dmic_clk_shift));
  1175. snd_soc_component_update_bits(component,
  1176. dmic_clk_en_reg, 0x08, 0x08);
  1177. /* enable clock scaling */
  1178. snd_soc_component_update_bits(component,
  1179. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1180. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1181. break;
  1182. case SND_SOC_DAPM_POST_PMD:
  1183. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1184. snd_soc_component_update_bits(component,
  1185. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1186. (0x01 << dmic_ctl_shift),
  1187. (0x01 << dmic_ctl_shift));
  1188. if (dmic2_left_en)
  1189. snd_soc_component_update_bits(component,
  1190. dmic2_left_en, 0x80, 0x00);
  1191. snd_soc_component_update_bits(component,
  1192. dmic_clk_en_reg, 0x08, 0x00);
  1193. break;
  1194. };
  1195. return 0;
  1196. }
  1197. /*
  1198. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1199. * @micb_mv: micbias in mv
  1200. *
  1201. * return register value converted
  1202. */
  1203. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1204. {
  1205. /* min micbias voltage is 1V and maximum is 2.85V */
  1206. if (micb_mv < 1000 || micb_mv > 2850) {
  1207. pr_err("%s: unsupported micbias voltage\n", __func__);
  1208. return -EINVAL;
  1209. }
  1210. return (micb_mv - 1000) / 50;
  1211. }
  1212. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1213. /*
  1214. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1215. * @component: handle to snd_soc_component *
  1216. * @req_volt: micbias voltage to be set
  1217. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1218. *
  1219. * return 0 if adjustment is success or error code in case of failure
  1220. */
  1221. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1222. int req_volt, int micb_num)
  1223. {
  1224. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1225. int cur_vout_ctl, req_vout_ctl;
  1226. int micb_reg, micb_val, micb_en;
  1227. int ret = 0;
  1228. switch (micb_num) {
  1229. case MIC_BIAS_1:
  1230. micb_reg = WCD938X_ANA_MICB1;
  1231. break;
  1232. case MIC_BIAS_2:
  1233. micb_reg = WCD938X_ANA_MICB2;
  1234. break;
  1235. case MIC_BIAS_3:
  1236. micb_reg = WCD938X_ANA_MICB3;
  1237. break;
  1238. case MIC_BIAS_4:
  1239. micb_reg = WCD938X_ANA_MICB4;
  1240. break;
  1241. default:
  1242. return -EINVAL;
  1243. }
  1244. mutex_lock(&wcd938x->micb_lock);
  1245. /*
  1246. * If requested micbias voltage is same as current micbias
  1247. * voltage, then just return. Otherwise, adjust voltage as
  1248. * per requested value. If micbias is already enabled, then
  1249. * to avoid slow micbias ramp-up or down enable pull-up
  1250. * momentarily, change the micbias value and then re-enable
  1251. * micbias.
  1252. */
  1253. micb_val = snd_soc_component_read32(component, micb_reg);
  1254. micb_en = (micb_val & 0xC0) >> 6;
  1255. cur_vout_ctl = micb_val & 0x3F;
  1256. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1257. if (req_vout_ctl < 0) {
  1258. ret = -EINVAL;
  1259. goto exit;
  1260. }
  1261. if (cur_vout_ctl == req_vout_ctl) {
  1262. ret = 0;
  1263. goto exit;
  1264. }
  1265. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1266. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1267. req_volt, micb_en);
  1268. if (micb_en == 0x1)
  1269. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1270. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1271. if (micb_en == 0x1) {
  1272. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1273. /*
  1274. * Add 2ms delay as per HW requirement after enabling
  1275. * micbias
  1276. */
  1277. usleep_range(2000, 2100);
  1278. }
  1279. exit:
  1280. mutex_unlock(&wcd938x->micb_lock);
  1281. return ret;
  1282. }
  1283. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1284. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1285. struct snd_kcontrol *kcontrol,
  1286. int event)
  1287. {
  1288. struct snd_soc_component *component =
  1289. snd_soc_dapm_to_component(w->dapm);
  1290. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1291. int ret = 0;
  1292. int bank = 0;
  1293. int mode = 0;
  1294. bank = wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1295. wcd938x->tx_swr_dev->dev_num);
  1296. wcd938x_swr_slv_set_host_clk_div2(wcd938x->tx_swr_dev,
  1297. wcd938x->tx_swr_dev->dev_num, bank);
  1298. switch (event) {
  1299. case SND_SOC_DAPM_PRE_PMU:
  1300. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1301. wcd938x->tx_swr_dev->dev_num,
  1302. true);
  1303. if (test_bit(WCD_ADC1, &wcd938x->status_mask))
  1304. mode |= wcd938x->tx_mode[WCD_ADC1];
  1305. if (test_bit(WCD_ADC2, &wcd938x->status_mask))
  1306. mode |= wcd938x->tx_mode[WCD_ADC2];
  1307. if (test_bit(WCD_ADC3, &wcd938x->status_mask))
  1308. mode |= wcd938x->tx_mode[WCD_ADC3];
  1309. if (test_bit(WCD_ADC4, &wcd938x->status_mask))
  1310. mode |= wcd938x->tx_mode[WCD_ADC4];
  1311. wcd938x_set_swr_clk_rate(component, mode, bank);
  1312. break;
  1313. case SND_SOC_DAPM_POST_PMD:
  1314. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1315. wcd938x->tx_swr_dev->dev_num,
  1316. false);
  1317. wcd938x_set_swr_clk_rate(component, ADC_MODE_INVALID, bank);
  1318. break;
  1319. };
  1320. return ret;
  1321. }
  1322. static int wcd938x_get_adc_mode(int val)
  1323. {
  1324. int ret = 0;
  1325. switch (val) {
  1326. case ADC_MODE_INVALID:
  1327. ret = ADC_MODE_VAL_NORMAL;
  1328. break;
  1329. case ADC_MODE_HIFI:
  1330. ret = ADC_MODE_VAL_HIFI;
  1331. break;
  1332. case ADC_MODE_LO_HIF:
  1333. ret = ADC_MODE_VAL_LO_HIF;
  1334. break;
  1335. case ADC_MODE_NORMAL:
  1336. ret = ADC_MODE_VAL_NORMAL;
  1337. break;
  1338. case ADC_MODE_LP:
  1339. ret = ADC_MODE_VAL_LP;
  1340. break;
  1341. case ADC_MODE_ULP1:
  1342. ret = ADC_MODE_VAL_ULP1;
  1343. break;
  1344. case ADC_MODE_ULP2:
  1345. ret = ADC_MODE_VAL_ULP2;
  1346. break;
  1347. default:
  1348. ret = -EINVAL;
  1349. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1350. break;
  1351. }
  1352. return ret;
  1353. }
  1354. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1355. struct snd_kcontrol *kcontrol,
  1356. int event){
  1357. struct snd_soc_component *component =
  1358. snd_soc_dapm_to_component(w->dapm);
  1359. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1360. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1361. w->name, event);
  1362. switch (event) {
  1363. case SND_SOC_DAPM_PRE_PMU:
  1364. snd_soc_component_update_bits(component,
  1365. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1366. snd_soc_component_update_bits(component,
  1367. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1368. set_bit(w->shift, &wcd938x->status_mask);
  1369. /* Enable BCS for Headset mic */
  1370. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1371. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1372. wcd938x_tx_connect_port(component, MBHC, true);
  1373. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1374. }
  1375. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1376. break;
  1377. case SND_SOC_DAPM_POST_PMD:
  1378. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1379. if (w->shift == 1 &&
  1380. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1381. wcd938x_tx_connect_port(component, MBHC, false);
  1382. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1383. }
  1384. snd_soc_component_update_bits(component,
  1385. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1386. clear_bit(w->shift, &wcd938x->status_mask);
  1387. break;
  1388. };
  1389. return 0;
  1390. }
  1391. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1392. int channel, int mode)
  1393. {
  1394. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1395. int ret = 0;
  1396. switch (channel) {
  1397. case 0:
  1398. reg = WCD938X_ANA_TX_CH2;
  1399. mask = 0x40;
  1400. break;
  1401. case 1:
  1402. reg = WCD938X_ANA_TX_CH2;
  1403. mask = 0x20;
  1404. break;
  1405. case 2:
  1406. reg = WCD938X_ANA_TX_CH4;
  1407. mask = 0x40;
  1408. break;
  1409. case 3:
  1410. reg = WCD938X_ANA_TX_CH4;
  1411. mask = 0x20;
  1412. break;
  1413. default:
  1414. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1415. ret = -EINVAL;
  1416. break;
  1417. }
  1418. if (!mode)
  1419. val = 0x00;
  1420. else
  1421. val = mask;
  1422. if (!ret)
  1423. snd_soc_component_update_bits(component, reg, mask, val);
  1424. return ret;
  1425. }
  1426. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1427. struct snd_kcontrol *kcontrol, int event)
  1428. {
  1429. struct snd_soc_component *component =
  1430. snd_soc_dapm_to_component(w->dapm);
  1431. int mode;
  1432. int ret = 0;
  1433. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1434. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1435. w->name, event);
  1436. switch (event) {
  1437. case SND_SOC_DAPM_PRE_PMU:
  1438. snd_soc_component_update_bits(component,
  1439. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1440. snd_soc_component_update_bits(component,
  1441. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1442. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1443. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1444. if (mode < 0) {
  1445. dev_info(component->dev,
  1446. "%s: invalid mode, setting to normal mode\n",
  1447. __func__);
  1448. mode = ADC_MODE_VAL_NORMAL;
  1449. }
  1450. switch (w->shift) {
  1451. case 0:
  1452. snd_soc_component_update_bits(component,
  1453. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1454. mode);
  1455. snd_soc_component_update_bits(component,
  1456. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1457. break;
  1458. case 1:
  1459. snd_soc_component_update_bits(component,
  1460. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1461. mode << 4);
  1462. snd_soc_component_update_bits(component,
  1463. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1464. break;
  1465. case 2:
  1466. snd_soc_component_update_bits(component,
  1467. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1468. mode);
  1469. snd_soc_component_update_bits(component,
  1470. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1471. break;
  1472. case 3:
  1473. snd_soc_component_update_bits(component,
  1474. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1475. mode << 4);
  1476. snd_soc_component_update_bits(component,
  1477. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1478. break;
  1479. default:
  1480. break;
  1481. }
  1482. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1483. break;
  1484. case SND_SOC_DAPM_POST_PMD:
  1485. switch (w->shift) {
  1486. case 0:
  1487. snd_soc_component_update_bits(component,
  1488. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1489. break;
  1490. case 1:
  1491. snd_soc_component_update_bits(component,
  1492. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1493. break;
  1494. case 2:
  1495. snd_soc_component_update_bits(component,
  1496. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1497. break;
  1498. case 3:
  1499. snd_soc_component_update_bits(component,
  1500. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1501. break;
  1502. default:
  1503. break;
  1504. }
  1505. snd_soc_component_update_bits(component,
  1506. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1507. break;
  1508. };
  1509. return ret;
  1510. }
  1511. int wcd938x_micbias_control(struct snd_soc_component *component,
  1512. int micb_num, int req, bool is_dapm)
  1513. {
  1514. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1515. int micb_index = micb_num - 1;
  1516. u16 micb_reg;
  1517. int pre_off_event = 0, post_off_event = 0;
  1518. int post_on_event = 0, post_dapm_off = 0;
  1519. int post_dapm_on = 0;
  1520. int ret = 0;
  1521. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1522. dev_err(component->dev,
  1523. "%s: Invalid micbias index, micb_ind:%d\n",
  1524. __func__, micb_index);
  1525. return -EINVAL;
  1526. }
  1527. if (NULL == wcd938x) {
  1528. dev_err(component->dev,
  1529. "%s: wcd938x private data is NULL\n", __func__);
  1530. return -EINVAL;
  1531. }
  1532. switch (micb_num) {
  1533. case MIC_BIAS_1:
  1534. micb_reg = WCD938X_ANA_MICB1;
  1535. break;
  1536. case MIC_BIAS_2:
  1537. micb_reg = WCD938X_ANA_MICB2;
  1538. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1539. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1540. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1541. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1542. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1543. break;
  1544. case MIC_BIAS_3:
  1545. micb_reg = WCD938X_ANA_MICB3;
  1546. break;
  1547. case MIC_BIAS_4:
  1548. micb_reg = WCD938X_ANA_MICB4;
  1549. break;
  1550. default:
  1551. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1552. __func__, micb_num);
  1553. return -EINVAL;
  1554. };
  1555. mutex_lock(&wcd938x->micb_lock);
  1556. switch (req) {
  1557. case MICB_PULLUP_ENABLE:
  1558. if (!wcd938x->dev_up) {
  1559. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1560. __func__, req);
  1561. ret = -ENODEV;
  1562. goto done;
  1563. }
  1564. wcd938x->pullup_ref[micb_index]++;
  1565. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1566. (wcd938x->micb_ref[micb_index] == 0))
  1567. snd_soc_component_update_bits(component, micb_reg,
  1568. 0xC0, 0x80);
  1569. break;
  1570. case MICB_PULLUP_DISABLE:
  1571. if (wcd938x->pullup_ref[micb_index] > 0)
  1572. wcd938x->pullup_ref[micb_index]--;
  1573. if (!wcd938x->dev_up) {
  1574. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1575. __func__, req);
  1576. ret = -ENODEV;
  1577. goto done;
  1578. }
  1579. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1580. (wcd938x->micb_ref[micb_index] == 0))
  1581. snd_soc_component_update_bits(component, micb_reg,
  1582. 0xC0, 0x00);
  1583. break;
  1584. case MICB_ENABLE:
  1585. if (!wcd938x->dev_up) {
  1586. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1587. __func__, req);
  1588. ret = -ENODEV;
  1589. goto done;
  1590. }
  1591. wcd938x->micb_ref[micb_index]++;
  1592. if (wcd938x->micb_ref[micb_index] == 1) {
  1593. snd_soc_component_update_bits(component,
  1594. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1595. snd_soc_component_update_bits(component,
  1596. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1597. snd_soc_component_update_bits(component,
  1598. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1599. snd_soc_component_update_bits(component,
  1600. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1601. snd_soc_component_update_bits(component,
  1602. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1603. snd_soc_component_update_bits(component,
  1604. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1605. snd_soc_component_update_bits(component,
  1606. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1607. snd_soc_component_update_bits(component,
  1608. micb_reg, 0xC0, 0x40);
  1609. if (post_on_event)
  1610. blocking_notifier_call_chain(
  1611. &wcd938x->mbhc->notifier,
  1612. post_on_event,
  1613. &wcd938x->mbhc->wcd_mbhc);
  1614. }
  1615. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1616. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1617. post_dapm_on,
  1618. &wcd938x->mbhc->wcd_mbhc);
  1619. break;
  1620. case MICB_DISABLE:
  1621. if (wcd938x->micb_ref[micb_index] > 0)
  1622. wcd938x->micb_ref[micb_index]--;
  1623. if (!wcd938x->dev_up) {
  1624. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1625. __func__, req);
  1626. ret = -ENODEV;
  1627. goto done;
  1628. }
  1629. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1630. (wcd938x->pullup_ref[micb_index] > 0))
  1631. snd_soc_component_update_bits(component, micb_reg,
  1632. 0xC0, 0x80);
  1633. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1634. (wcd938x->pullup_ref[micb_index] == 0)) {
  1635. if (pre_off_event && wcd938x->mbhc)
  1636. blocking_notifier_call_chain(
  1637. &wcd938x->mbhc->notifier,
  1638. pre_off_event,
  1639. &wcd938x->mbhc->wcd_mbhc);
  1640. snd_soc_component_update_bits(component, micb_reg,
  1641. 0xC0, 0x00);
  1642. if (post_off_event && wcd938x->mbhc)
  1643. blocking_notifier_call_chain(
  1644. &wcd938x->mbhc->notifier,
  1645. post_off_event,
  1646. &wcd938x->mbhc->wcd_mbhc);
  1647. }
  1648. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1649. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1650. post_dapm_off,
  1651. &wcd938x->mbhc->wcd_mbhc);
  1652. break;
  1653. };
  1654. dev_dbg(component->dev,
  1655. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1656. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1657. wcd938x->pullup_ref[micb_index]);
  1658. done:
  1659. mutex_unlock(&wcd938x->micb_lock);
  1660. return ret;
  1661. }
  1662. EXPORT_SYMBOL(wcd938x_micbias_control);
  1663. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1664. {
  1665. int ret = 0;
  1666. uint8_t devnum = 0;
  1667. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1668. if (ret) {
  1669. dev_err(&swr_dev->dev,
  1670. "%s get devnum %d for dev addr %lx failed\n",
  1671. __func__, devnum, swr_dev->addr);
  1672. swr_remove_device(swr_dev);
  1673. return ret;
  1674. }
  1675. swr_dev->dev_num = devnum;
  1676. return 0;
  1677. }
  1678. static int wcd938x_event_notify(struct notifier_block *block,
  1679. unsigned long val,
  1680. void *data)
  1681. {
  1682. u16 event = (val & 0xffff);
  1683. int ret = 0;
  1684. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1685. struct snd_soc_component *component = wcd938x->component;
  1686. struct wcd_mbhc *mbhc;
  1687. switch (event) {
  1688. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1689. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1690. snd_soc_component_update_bits(component,
  1691. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1692. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1693. }
  1694. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1695. snd_soc_component_update_bits(component,
  1696. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1697. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1698. }
  1699. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1700. snd_soc_component_update_bits(component,
  1701. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1702. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1703. }
  1704. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1705. snd_soc_component_update_bits(component,
  1706. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1707. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1708. }
  1709. break;
  1710. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1711. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1712. 0xC0, 0x00);
  1713. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1714. 0x80, 0x00);
  1715. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1716. 0x80, 0x00);
  1717. break;
  1718. case BOLERO_WCD_EVT_SSR_DOWN:
  1719. wcd938x->dev_up = false;
  1720. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1721. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1722. wcd938x_reset_low(wcd938x->dev);
  1723. break;
  1724. case BOLERO_WCD_EVT_SSR_UP:
  1725. wcd938x_reset(wcd938x->dev);
  1726. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1727. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1728. wcd938x_init_reg(component);
  1729. regcache_mark_dirty(wcd938x->regmap);
  1730. regcache_sync(wcd938x->regmap);
  1731. /* Initialize MBHC module */
  1732. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1733. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1734. if (ret) {
  1735. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1736. __func__);
  1737. } else {
  1738. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1739. }
  1740. wcd938x->dev_up = true;
  1741. break;
  1742. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1743. snd_soc_component_update_bits(component,
  1744. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1745. ((val >> 0x10) << 0x01));
  1746. break;
  1747. default:
  1748. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1749. break;
  1750. }
  1751. return 0;
  1752. }
  1753. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1754. int event)
  1755. {
  1756. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1757. int micb_num;
  1758. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1759. __func__, w->name, event);
  1760. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1761. micb_num = MIC_BIAS_1;
  1762. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1763. micb_num = MIC_BIAS_2;
  1764. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1765. micb_num = MIC_BIAS_3;
  1766. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1767. micb_num = MIC_BIAS_4;
  1768. else
  1769. return -EINVAL;
  1770. switch (event) {
  1771. case SND_SOC_DAPM_PRE_PMU:
  1772. wcd938x_micbias_control(component, micb_num,
  1773. MICB_ENABLE, true);
  1774. break;
  1775. case SND_SOC_DAPM_POST_PMU:
  1776. /* 1 msec delay as per HW requirement */
  1777. usleep_range(1000, 1100);
  1778. break;
  1779. case SND_SOC_DAPM_POST_PMD:
  1780. wcd938x_micbias_control(component, micb_num,
  1781. MICB_DISABLE, true);
  1782. break;
  1783. };
  1784. return 0;
  1785. }
  1786. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1787. struct snd_kcontrol *kcontrol,
  1788. int event)
  1789. {
  1790. return __wcd938x_codec_enable_micbias(w, event);
  1791. }
  1792. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1793. int event)
  1794. {
  1795. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1796. int micb_num;
  1797. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1798. __func__, w->name, event);
  1799. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1800. micb_num = MIC_BIAS_1;
  1801. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1802. micb_num = MIC_BIAS_2;
  1803. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1804. micb_num = MIC_BIAS_3;
  1805. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1806. micb_num = MIC_BIAS_4;
  1807. else
  1808. return -EINVAL;
  1809. switch (event) {
  1810. case SND_SOC_DAPM_PRE_PMU:
  1811. wcd938x_micbias_control(component, micb_num,
  1812. MICB_PULLUP_ENABLE, true);
  1813. break;
  1814. case SND_SOC_DAPM_POST_PMU:
  1815. /* 1 msec delay as per HW requirement */
  1816. usleep_range(1000, 1100);
  1817. break;
  1818. case SND_SOC_DAPM_POST_PMD:
  1819. wcd938x_micbias_control(component, micb_num,
  1820. MICB_PULLUP_DISABLE, true);
  1821. break;
  1822. };
  1823. return 0;
  1824. }
  1825. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1826. struct snd_kcontrol *kcontrol,
  1827. int event)
  1828. {
  1829. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1830. }
  1831. static inline int wcd938x_tx_path_get(const char *wname,
  1832. unsigned int *path_num)
  1833. {
  1834. int ret = 0;
  1835. char *widget_name = NULL;
  1836. char *w_name = NULL;
  1837. char *path_num_char = NULL;
  1838. char *path_name = NULL;
  1839. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  1840. if (!widget_name)
  1841. return -EINVAL;
  1842. w_name = widget_name;
  1843. path_name = strsep(&widget_name, " ");
  1844. if (!path_name) {
  1845. pr_err("%s: Invalid widget name = %s\n",
  1846. __func__, widget_name);
  1847. ret = -EINVAL;
  1848. goto err;
  1849. }
  1850. path_num_char = strpbrk(path_name, "0123");
  1851. if (!path_num_char) {
  1852. pr_err("%s: tx path index not found\n",
  1853. __func__);
  1854. ret = -EINVAL;
  1855. goto err;
  1856. }
  1857. ret = kstrtouint(path_num_char, 10, path_num);
  1858. if (ret < 0)
  1859. pr_err("%s: Invalid tx path = %s\n",
  1860. __func__, w_name);
  1861. err:
  1862. kfree(w_name);
  1863. return ret;
  1864. }
  1865. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  1866. struct snd_ctl_elem_value *ucontrol)
  1867. {
  1868. struct snd_soc_component *component =
  1869. snd_soc_kcontrol_component(kcontrol);
  1870. struct wcd938x_priv *wcd938x = NULL;
  1871. int ret = 0;
  1872. unsigned int path = 0;
  1873. if (!component)
  1874. return -EINVAL;
  1875. wcd938x = snd_soc_component_get_drvdata(component);
  1876. if (!wcd938x)
  1877. return -EINVAL;
  1878. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1879. if (ret < 0)
  1880. return ret;
  1881. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  1882. return 0;
  1883. }
  1884. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  1885. struct snd_ctl_elem_value *ucontrol)
  1886. {
  1887. struct snd_soc_component *component =
  1888. snd_soc_kcontrol_component(kcontrol);
  1889. struct wcd938x_priv *wcd938x = NULL;
  1890. u32 mode_val;
  1891. unsigned int path = 0;
  1892. int ret = 0;
  1893. if (!component)
  1894. return -EINVAL;
  1895. wcd938x = snd_soc_component_get_drvdata(component);
  1896. if (!wcd938x)
  1897. return -EINVAL;
  1898. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  1899. if (ret)
  1900. return ret;
  1901. mode_val = ucontrol->value.enumerated.item[0];
  1902. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1903. wcd938x->tx_mode[path] = mode_val;
  1904. return 0;
  1905. }
  1906. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1907. struct snd_ctl_elem_value *ucontrol)
  1908. {
  1909. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1910. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1911. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1912. return 0;
  1913. }
  1914. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1915. struct snd_ctl_elem_value *ucontrol)
  1916. {
  1917. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1918. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1919. u32 mode_val;
  1920. mode_val = ucontrol->value.enumerated.item[0];
  1921. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1922. if (wcd938x->variant == WCD9380) {
  1923. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  1924. dev_info(component->dev,
  1925. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  1926. __func__);
  1927. mode_val = CLS_H_ULP;
  1928. }
  1929. }
  1930. if (mode_val == CLS_H_NORMAL) {
  1931. dev_info(component->dev,
  1932. "%s:Invalid HPH Mode, default to class_AB\n",
  1933. __func__);
  1934. mode_val = CLS_H_ULP;
  1935. }
  1936. wcd938x->hph_mode = mode_val;
  1937. return 0;
  1938. }
  1939. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1940. struct snd_ctl_elem_value *ucontrol)
  1941. {
  1942. u8 ear_pa_gain = 0;
  1943. struct snd_soc_component *component =
  1944. snd_soc_kcontrol_component(kcontrol);
  1945. ear_pa_gain = snd_soc_component_read32(component,
  1946. WCD938X_ANA_EAR_COMPANDER_CTL);
  1947. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1948. ucontrol->value.integer.value[0] = ear_pa_gain;
  1949. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1950. ear_pa_gain);
  1951. return 0;
  1952. }
  1953. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1954. struct snd_ctl_elem_value *ucontrol)
  1955. {
  1956. u8 ear_pa_gain = 0;
  1957. struct snd_soc_component *component =
  1958. snd_soc_kcontrol_component(kcontrol);
  1959. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1960. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1961. __func__, ucontrol->value.integer.value[0]);
  1962. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1963. if (!wcd938x->comp1_enable) {
  1964. snd_soc_component_update_bits(component,
  1965. WCD938X_ANA_EAR_COMPANDER_CTL,
  1966. 0x7C, ear_pa_gain);
  1967. }
  1968. return 0;
  1969. }
  1970. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1971. struct snd_ctl_elem_value *ucontrol)
  1972. {
  1973. struct snd_soc_component *component =
  1974. snd_soc_kcontrol_component(kcontrol);
  1975. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1976. bool hphr;
  1977. struct soc_multi_mixer_control *mc;
  1978. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1979. hphr = mc->shift;
  1980. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1981. wcd938x->comp1_enable;
  1982. return 0;
  1983. }
  1984. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1985. struct snd_ctl_elem_value *ucontrol)
  1986. {
  1987. struct snd_soc_component *component =
  1988. snd_soc_kcontrol_component(kcontrol);
  1989. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1990. int value = ucontrol->value.integer.value[0];
  1991. bool hphr;
  1992. struct soc_multi_mixer_control *mc;
  1993. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1994. hphr = mc->shift;
  1995. if (hphr)
  1996. wcd938x->comp2_enable = value;
  1997. else
  1998. wcd938x->comp1_enable = value;
  1999. return 0;
  2000. }
  2001. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2002. struct snd_ctl_elem_value *ucontrol)
  2003. {
  2004. struct snd_soc_component *component =
  2005. snd_soc_kcontrol_component(kcontrol);
  2006. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2007. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2008. return 0;
  2009. }
  2010. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2011. struct snd_ctl_elem_value *ucontrol)
  2012. {
  2013. struct snd_soc_component *component =
  2014. snd_soc_kcontrol_component(kcontrol);
  2015. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2016. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2017. return 0;
  2018. }
  2019. static const char * const tx_mode_mux_text_wcd9380[] = {
  2020. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2021. };
  2022. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2023. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2024. tx_mode_mux_text_wcd9380);
  2025. static const char * const tx_mode_mux_text[] = {
  2026. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2027. "ADC_ULP1", "ADC_ULP2",
  2028. };
  2029. static const struct soc_enum tx_mode_mux_enum =
  2030. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2031. tx_mode_mux_text);
  2032. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2033. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2034. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2035. "CLS_AB_LOHIFI",
  2036. };
  2037. static const char * const wcd938x_ear_pa_gain_text[] = {
  2038. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2039. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2040. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2041. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2042. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2043. };
  2044. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2045. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2046. rx_hph_mode_mux_text_wcd9380);
  2047. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2048. wcd938x_ear_pa_gain_text);
  2049. static const char * const rx_hph_mode_mux_text[] = {
  2050. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2051. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2052. };
  2053. static const struct soc_enum rx_hph_mode_mux_enum =
  2054. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2055. rx_hph_mode_mux_text);
  2056. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2057. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2058. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2059. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2060. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2061. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2062. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2063. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2064. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2065. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2066. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2067. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2068. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2069. };
  2070. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2071. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2072. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2073. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2074. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2075. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2076. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2077. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2078. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2079. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2080. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2081. };
  2082. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2083. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2084. wcd938x_get_compander, wcd938x_set_compander),
  2085. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2086. wcd938x_get_compander, wcd938x_set_compander),
  2087. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2088. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2089. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2090. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2091. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2092. analog_gain),
  2093. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2094. analog_gain),
  2095. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2096. analog_gain),
  2097. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2098. analog_gain),
  2099. };
  2100. static const struct snd_kcontrol_new adc1_switch[] = {
  2101. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2102. };
  2103. static const struct snd_kcontrol_new adc2_switch[] = {
  2104. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2105. };
  2106. static const struct snd_kcontrol_new adc3_switch[] = {
  2107. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2108. };
  2109. static const struct snd_kcontrol_new adc4_switch[] = {
  2110. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2111. };
  2112. static const struct snd_kcontrol_new dmic1_switch[] = {
  2113. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2114. };
  2115. static const struct snd_kcontrol_new dmic2_switch[] = {
  2116. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2117. };
  2118. static const struct snd_kcontrol_new dmic3_switch[] = {
  2119. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2120. };
  2121. static const struct snd_kcontrol_new dmic4_switch[] = {
  2122. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2123. };
  2124. static const struct snd_kcontrol_new dmic5_switch[] = {
  2125. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2126. };
  2127. static const struct snd_kcontrol_new dmic6_switch[] = {
  2128. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2129. };
  2130. static const struct snd_kcontrol_new dmic7_switch[] = {
  2131. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2132. };
  2133. static const struct snd_kcontrol_new dmic8_switch[] = {
  2134. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2135. };
  2136. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2137. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2138. };
  2139. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2140. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2141. };
  2142. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2143. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2144. };
  2145. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2146. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2147. };
  2148. static const char * const adc2_mux_text[] = {
  2149. "INP2", "INP3"
  2150. };
  2151. static const struct soc_enum adc2_enum =
  2152. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2153. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2154. static const struct snd_kcontrol_new tx_adc2_mux =
  2155. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2156. static const char * const adc3_mux_text[] = {
  2157. "INP4", "INP6"
  2158. };
  2159. static const struct soc_enum adc3_enum =
  2160. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2161. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2162. static const struct snd_kcontrol_new tx_adc3_mux =
  2163. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2164. static const char * const adc4_mux_text[] = {
  2165. "INP5", "INP7"
  2166. };
  2167. static const struct soc_enum adc4_enum =
  2168. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2169. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2170. static const struct snd_kcontrol_new tx_adc4_mux =
  2171. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2172. static const char * const rdac3_mux_text[] = {
  2173. "RX1", "RX3"
  2174. };
  2175. static const char * const hdr12_mux_text[] = {
  2176. "NO_HDR12", "HDR12"
  2177. };
  2178. static const struct soc_enum hdr12_enum =
  2179. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2180. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2181. static const struct snd_kcontrol_new tx_hdr12_mux =
  2182. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2183. static const char * const hdr34_mux_text[] = {
  2184. "NO_HDR34", "HDR34"
  2185. };
  2186. static const struct soc_enum hdr34_enum =
  2187. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2188. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2189. static const struct snd_kcontrol_new tx_hdr34_mux =
  2190. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2191. static const struct soc_enum rdac3_enum =
  2192. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2193. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2194. static const struct snd_kcontrol_new rx_rdac3_mux =
  2195. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2196. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2197. /*input widgets*/
  2198. SND_SOC_DAPM_INPUT("AMIC1"),
  2199. SND_SOC_DAPM_INPUT("AMIC2"),
  2200. SND_SOC_DAPM_INPUT("AMIC3"),
  2201. SND_SOC_DAPM_INPUT("AMIC4"),
  2202. SND_SOC_DAPM_INPUT("AMIC5"),
  2203. SND_SOC_DAPM_INPUT("AMIC6"),
  2204. SND_SOC_DAPM_INPUT("AMIC7"),
  2205. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2206. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2207. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2208. /*tx widgets*/
  2209. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2210. wcd938x_codec_enable_adc,
  2211. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2212. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2213. wcd938x_codec_enable_adc,
  2214. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2215. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2216. wcd938x_codec_enable_adc,
  2217. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2218. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2219. wcd938x_codec_enable_adc,
  2220. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2221. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2222. wcd938x_codec_enable_dmic,
  2223. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2224. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2225. wcd938x_codec_enable_dmic,
  2226. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2227. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2228. wcd938x_codec_enable_dmic,
  2229. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2230. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2231. wcd938x_codec_enable_dmic,
  2232. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2233. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2234. wcd938x_codec_enable_dmic,
  2235. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2236. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2237. wcd938x_codec_enable_dmic,
  2238. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2239. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2240. wcd938x_codec_enable_dmic,
  2241. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2242. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2243. wcd938x_codec_enable_dmic,
  2244. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2245. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2246. NULL, 0, wcd938x_enable_req,
  2247. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2248. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2249. NULL, 0, wcd938x_enable_req,
  2250. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2251. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2252. NULL, 0, wcd938x_enable_req,
  2253. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2254. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2255. NULL, 0, wcd938x_enable_req,
  2256. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2257. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2258. &tx_adc2_mux),
  2259. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2260. &tx_adc3_mux),
  2261. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2262. &tx_adc4_mux),
  2263. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2264. &tx_hdr12_mux),
  2265. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2266. &tx_hdr34_mux),
  2267. /*tx mixers*/
  2268. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2269. adc1_switch, ARRAY_SIZE(adc1_switch),
  2270. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2271. SND_SOC_DAPM_POST_PMD),
  2272. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2273. adc2_switch, ARRAY_SIZE(adc2_switch),
  2274. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2275. SND_SOC_DAPM_POST_PMD),
  2276. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2277. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2278. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2279. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2280. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2281. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2282. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2283. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2284. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2285. SND_SOC_DAPM_POST_PMD),
  2286. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2287. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2288. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2289. SND_SOC_DAPM_POST_PMD),
  2290. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2291. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2292. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2293. SND_SOC_DAPM_POST_PMD),
  2294. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2295. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2296. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2297. SND_SOC_DAPM_POST_PMD),
  2298. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2299. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2300. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2301. SND_SOC_DAPM_POST_PMD),
  2302. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2303. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2304. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2305. SND_SOC_DAPM_POST_PMD),
  2306. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2307. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2308. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2309. SND_SOC_DAPM_POST_PMD),
  2310. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2311. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2312. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2313. SND_SOC_DAPM_POST_PMD),
  2314. /* micbias widgets*/
  2315. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2316. wcd938x_codec_enable_micbias,
  2317. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2318. SND_SOC_DAPM_POST_PMD),
  2319. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2320. wcd938x_codec_enable_micbias,
  2321. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2322. SND_SOC_DAPM_POST_PMD),
  2323. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2324. wcd938x_codec_enable_micbias,
  2325. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2326. SND_SOC_DAPM_POST_PMD),
  2327. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2328. wcd938x_codec_enable_micbias,
  2329. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2330. SND_SOC_DAPM_POST_PMD),
  2331. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2332. wcd938x_enable_clsh,
  2333. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2334. /*rx widgets*/
  2335. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2336. wcd938x_codec_enable_ear_pa,
  2337. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2338. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2339. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2340. wcd938x_codec_enable_aux_pa,
  2341. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2342. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2343. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2344. wcd938x_codec_enable_hphl_pa,
  2345. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2346. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2347. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2348. wcd938x_codec_enable_hphr_pa,
  2349. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2350. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2351. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2352. wcd938x_codec_hphl_dac_event,
  2353. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2354. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2355. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2356. wcd938x_codec_hphr_dac_event,
  2357. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2358. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2359. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2360. wcd938x_codec_ear_dac_event,
  2361. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2362. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2363. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2364. wcd938x_codec_aux_dac_event,
  2365. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2366. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2367. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2368. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2369. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2370. SND_SOC_DAPM_POST_PMD),
  2371. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2372. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2373. SND_SOC_DAPM_POST_PMD),
  2374. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2375. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2376. SND_SOC_DAPM_POST_PMD),
  2377. /* rx mixer widgets*/
  2378. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2379. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2380. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2381. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2382. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2383. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2384. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2385. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2386. /*output widgets tx*/
  2387. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2388. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2389. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2390. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  2391. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2392. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2393. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2394. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2395. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2396. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2397. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  2398. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  2399. /*output widgets rx*/
  2400. SND_SOC_DAPM_OUTPUT("EAR"),
  2401. SND_SOC_DAPM_OUTPUT("AUX"),
  2402. SND_SOC_DAPM_OUTPUT("HPHL"),
  2403. SND_SOC_DAPM_OUTPUT("HPHR"),
  2404. /* micbias pull up widgets*/
  2405. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2406. wcd938x_codec_enable_micbias_pullup,
  2407. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2408. SND_SOC_DAPM_POST_PMD),
  2409. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2410. wcd938x_codec_enable_micbias_pullup,
  2411. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2412. SND_SOC_DAPM_POST_PMD),
  2413. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2414. wcd938x_codec_enable_micbias_pullup,
  2415. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2416. SND_SOC_DAPM_POST_PMD),
  2417. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2418. wcd938x_codec_enable_micbias_pullup,
  2419. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2420. SND_SOC_DAPM_POST_PMD),
  2421. };
  2422. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2423. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  2424. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2425. {"ADC1 REQ", NULL, "ADC1"},
  2426. {"ADC1", NULL, "AMIC1"},
  2427. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  2428. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2429. {"ADC2 REQ", NULL, "ADC2"},
  2430. {"ADC2", NULL, "HDR12 MUX"},
  2431. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2432. {"HDR12 MUX", "HDR12", "AMIC1"},
  2433. {"ADC2 MUX", "INP3", "AMIC3"},
  2434. {"ADC2 MUX", "INP2", "AMIC2"},
  2435. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2436. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2437. {"ADC3 REQ", NULL, "ADC3"},
  2438. {"ADC3", NULL, "HDR34 MUX"},
  2439. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2440. {"HDR34 MUX", "HDR34", "AMIC5"},
  2441. {"ADC3 MUX", "INP4", "AMIC4"},
  2442. {"ADC3 MUX", "INP6", "AMIC6"},
  2443. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  2444. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2445. {"ADC4 REQ", NULL, "ADC4"},
  2446. {"ADC4", NULL, "ADC4 MUX"},
  2447. {"ADC4 MUX", "INP5", "AMIC5"},
  2448. {"ADC4 MUX", "INP7", "AMIC7"},
  2449. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2450. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2451. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2452. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2453. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2454. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2455. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2456. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2457. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2458. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2459. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2460. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2461. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  2462. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2463. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  2464. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2465. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2466. {"RX1", NULL, "IN1_HPHL"},
  2467. {"RDAC1", NULL, "RX1"},
  2468. {"HPHL_RDAC", "Switch", "RDAC1"},
  2469. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2470. {"HPHL", NULL, "HPHL PGA"},
  2471. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2472. {"RX2", NULL, "IN2_HPHR"},
  2473. {"RDAC2", NULL, "RX2"},
  2474. {"HPHR_RDAC", "Switch", "RDAC2"},
  2475. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2476. {"HPHR", NULL, "HPHR PGA"},
  2477. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2478. {"RX3", NULL, "IN3_AUX"},
  2479. {"RDAC4", NULL, "RX3"},
  2480. {"AUX_RDAC", "Switch", "RDAC4"},
  2481. {"AUX PGA", NULL, "AUX_RDAC"},
  2482. {"AUX", NULL, "AUX PGA"},
  2483. {"RDAC3_MUX", "RX3", "RX3"},
  2484. {"RDAC3_MUX", "RX1", "RX1"},
  2485. {"RDAC3", NULL, "RDAC3_MUX"},
  2486. {"EAR_RDAC", "Switch", "RDAC3"},
  2487. {"EAR PGA", NULL, "EAR_RDAC"},
  2488. {"EAR", NULL, "EAR PGA"},
  2489. };
  2490. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2491. void *file_private_data,
  2492. struct file *file,
  2493. char __user *buf, size_t count,
  2494. loff_t pos)
  2495. {
  2496. struct wcd938x_priv *priv;
  2497. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2498. int len = 0;
  2499. priv = (struct wcd938x_priv *) entry->private_data;
  2500. if (!priv) {
  2501. pr_err("%s: wcd938x priv is null\n", __func__);
  2502. return -EINVAL;
  2503. }
  2504. switch (priv->version) {
  2505. case WCD938X_VERSION_1_0:
  2506. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2507. break;
  2508. default:
  2509. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2510. }
  2511. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2512. }
  2513. static struct snd_info_entry_ops wcd938x_info_ops = {
  2514. .read = wcd938x_version_read,
  2515. };
  2516. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2517. void *file_private_data,
  2518. struct file *file,
  2519. char __user *buf, size_t count,
  2520. loff_t pos)
  2521. {
  2522. struct wcd938x_priv *priv;
  2523. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2524. int len = 0;
  2525. priv = (struct wcd938x_priv *) entry->private_data;
  2526. if (!priv) {
  2527. pr_err("%s: wcd938x priv is null\n", __func__);
  2528. return -EINVAL;
  2529. }
  2530. switch (priv->variant) {
  2531. case WCD9380:
  2532. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2533. break;
  2534. case WCD9385:
  2535. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2536. break;
  2537. default:
  2538. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2539. }
  2540. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2541. }
  2542. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2543. .read = wcd938x_variant_read,
  2544. };
  2545. /*
  2546. * wcd938x_get_codec_variant
  2547. * @component: component instance
  2548. *
  2549. * Return: codec variant or -EINVAL in error.
  2550. */
  2551. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  2552. {
  2553. struct wcd938x_priv *priv = NULL;
  2554. if (!component)
  2555. return -EINVAL;
  2556. priv = snd_soc_component_get_drvdata(component);
  2557. if (!priv) {
  2558. dev_err(component->dev,
  2559. "%s:wcd938x not probed\n", __func__);
  2560. return 0;
  2561. }
  2562. return priv->variant;
  2563. }
  2564. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  2565. /*
  2566. * wcd938x_info_create_codec_entry - creates wcd938x module
  2567. * @codec_root: The parent directory
  2568. * @component: component instance
  2569. *
  2570. * Creates wcd938x module, variant and version entry under the given
  2571. * parent directory.
  2572. *
  2573. * Return: 0 on success or negative error code on failure.
  2574. */
  2575. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2576. struct snd_soc_component *component)
  2577. {
  2578. struct snd_info_entry *version_entry;
  2579. struct snd_info_entry *variant_entry;
  2580. struct wcd938x_priv *priv;
  2581. struct snd_soc_card *card;
  2582. if (!codec_root || !component)
  2583. return -EINVAL;
  2584. priv = snd_soc_component_get_drvdata(component);
  2585. if (priv->entry) {
  2586. dev_dbg(priv->dev,
  2587. "%s:wcd938x module already created\n", __func__);
  2588. return 0;
  2589. }
  2590. card = component->card;
  2591. priv->entry = snd_info_create_subdir(codec_root->module,
  2592. "wcd938x", codec_root);
  2593. if (!priv->entry) {
  2594. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2595. __func__);
  2596. return -ENOMEM;
  2597. }
  2598. version_entry = snd_info_create_card_entry(card->snd_card,
  2599. "version",
  2600. priv->entry);
  2601. if (!version_entry) {
  2602. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2603. __func__);
  2604. return -ENOMEM;
  2605. }
  2606. version_entry->private_data = priv;
  2607. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2608. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2609. version_entry->c.ops = &wcd938x_info_ops;
  2610. if (snd_info_register(version_entry) < 0) {
  2611. snd_info_free_entry(version_entry);
  2612. return -ENOMEM;
  2613. }
  2614. priv->version_entry = version_entry;
  2615. variant_entry = snd_info_create_card_entry(card->snd_card,
  2616. "variant",
  2617. priv->entry);
  2618. if (!variant_entry) {
  2619. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  2620. __func__);
  2621. return -ENOMEM;
  2622. }
  2623. variant_entry->private_data = priv;
  2624. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  2625. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2626. variant_entry->c.ops = &wcd938x_variant_ops;
  2627. if (snd_info_register(variant_entry) < 0) {
  2628. snd_info_free_entry(variant_entry);
  2629. return -ENOMEM;
  2630. }
  2631. priv->variant_entry = variant_entry;
  2632. return 0;
  2633. }
  2634. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2635. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  2636. struct wcd938x_pdata *pdata)
  2637. {
  2638. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  2639. int rc = 0;
  2640. if (!pdata) {
  2641. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  2642. return -ENODEV;
  2643. }
  2644. /* set micbias voltage */
  2645. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2646. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2647. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2648. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  2649. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  2650. vout_ctl_4 < 0) {
  2651. rc = -EINVAL;
  2652. goto done;
  2653. }
  2654. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  2655. vout_ctl_1);
  2656. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  2657. vout_ctl_2);
  2658. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  2659. vout_ctl_3);
  2660. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  2661. vout_ctl_4);
  2662. done:
  2663. return rc;
  2664. }
  2665. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2666. {
  2667. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2668. struct snd_soc_dapm_context *dapm =
  2669. snd_soc_component_get_dapm(component);
  2670. int variant;
  2671. int ret = -EINVAL;
  2672. dev_info(component->dev, "%s()\n", __func__);
  2673. wcd938x = snd_soc_component_get_drvdata(component);
  2674. if (!wcd938x)
  2675. return -EINVAL;
  2676. wcd938x->component = component;
  2677. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2678. variant = (snd_soc_component_read32(component,
  2679. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2680. wcd938x->variant = variant;
  2681. wcd938x->fw_data = devm_kzalloc(component->dev,
  2682. sizeof(*(wcd938x->fw_data)),
  2683. GFP_KERNEL);
  2684. if (!wcd938x->fw_data) {
  2685. dev_err(component->dev, "Failed to allocate fw_data\n");
  2686. ret = -ENOMEM;
  2687. goto err;
  2688. }
  2689. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  2690. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  2691. WCD9XXX_CODEC_HWDEP_NODE, component);
  2692. if (ret < 0) {
  2693. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2694. goto err_hwdep;
  2695. }
  2696. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  2697. if (ret) {
  2698. pr_err("%s: mbhc initialization failed\n", __func__);
  2699. goto err_hwdep;
  2700. }
  2701. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2702. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2703. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2704. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2705. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  2706. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  2707. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  2708. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2709. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2710. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2711. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2712. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2713. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2714. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  2715. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  2716. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2717. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2718. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2719. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  2720. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2721. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2722. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2723. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2724. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2725. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2726. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2727. snd_soc_dapm_sync(dapm);
  2728. wcd_cls_h_init(&wcd938x->clsh_info);
  2729. wcd938x_init_reg(component);
  2730. if (wcd938x->variant == WCD9380) {
  2731. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  2732. ARRAY_SIZE(wcd9380_snd_controls));
  2733. if (ret < 0) {
  2734. dev_err(component->dev,
  2735. "%s: Failed to add snd ctrls for variant: %d\n",
  2736. __func__, wcd938x->variant);
  2737. goto err_hwdep;
  2738. }
  2739. }
  2740. if (wcd938x->variant == WCD9385) {
  2741. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  2742. ARRAY_SIZE(wcd9385_snd_controls));
  2743. if (ret < 0) {
  2744. dev_err(component->dev,
  2745. "%s: Failed to add snd ctrls for variant: %d\n",
  2746. __func__, wcd938x->variant);
  2747. goto err_hwdep;
  2748. }
  2749. }
  2750. wcd938x->version = WCD938X_VERSION_1_0;
  2751. /* Register event notifier */
  2752. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  2753. if (wcd938x->register_notifier) {
  2754. ret = wcd938x->register_notifier(wcd938x->handle,
  2755. &wcd938x->nblock,
  2756. true);
  2757. if (ret) {
  2758. dev_err(component->dev,
  2759. "%s: Failed to register notifier %d\n",
  2760. __func__, ret);
  2761. return ret;
  2762. }
  2763. }
  2764. wcd938x->dev_up = true;
  2765. return ret;
  2766. err_hwdep:
  2767. wcd938x->fw_data = NULL;
  2768. err:
  2769. return ret;
  2770. }
  2771. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  2772. {
  2773. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2774. if (!wcd938x) {
  2775. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  2776. __func__);
  2777. return;
  2778. }
  2779. if (wcd938x->register_notifier)
  2780. wcd938x->register_notifier(wcd938x->handle,
  2781. &wcd938x->nblock,
  2782. false);
  2783. }
  2784. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2785. .name = WCD938X_DRV_NAME,
  2786. .probe = wcd938x_soc_codec_probe,
  2787. .remove = wcd938x_soc_codec_remove,
  2788. .controls = wcd938x_snd_controls,
  2789. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2790. .dapm_widgets = wcd938x_dapm_widgets,
  2791. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2792. .dapm_routes = wcd938x_audio_map,
  2793. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2794. };
  2795. static int wcd938x_reset(struct device *dev)
  2796. {
  2797. struct wcd938x_priv *wcd938x = NULL;
  2798. int rc = 0;
  2799. int value = 0;
  2800. if (!dev)
  2801. return -ENODEV;
  2802. wcd938x = dev_get_drvdata(dev);
  2803. if (!wcd938x)
  2804. return -EINVAL;
  2805. if (!wcd938x->rst_np) {
  2806. dev_err(dev, "%s: reset gpio device node not specified\n",
  2807. __func__);
  2808. return -EINVAL;
  2809. }
  2810. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2811. if (value > 0)
  2812. return 0;
  2813. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2814. if (rc) {
  2815. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2816. __func__);
  2817. return rc;
  2818. }
  2819. /* 20us sleep required after pulling the reset gpio to LOW */
  2820. usleep_range(20, 30);
  2821. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2822. if (rc) {
  2823. dev_err(dev, "%s: wcd active state request fail!\n",
  2824. __func__);
  2825. return rc;
  2826. }
  2827. /* 20us sleep required after pulling the reset gpio to HIGH */
  2828. usleep_range(20, 30);
  2829. return rc;
  2830. }
  2831. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2832. u32 *val)
  2833. {
  2834. int rc = 0;
  2835. rc = of_property_read_u32(dev->of_node, name, val);
  2836. if (rc)
  2837. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2838. __func__, name, dev->of_node->full_name);
  2839. return rc;
  2840. }
  2841. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2842. struct wcd938x_micbias_setting *mb)
  2843. {
  2844. u32 prop_val = 0;
  2845. int rc = 0;
  2846. /* MB1 */
  2847. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2848. NULL)) {
  2849. rc = wcd938x_read_of_property_u32(dev,
  2850. "qcom,cdc-micbias1-mv",
  2851. &prop_val);
  2852. if (!rc)
  2853. mb->micb1_mv = prop_val;
  2854. } else {
  2855. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2856. __func__);
  2857. }
  2858. /* MB2 */
  2859. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2860. NULL)) {
  2861. rc = wcd938x_read_of_property_u32(dev,
  2862. "qcom,cdc-micbias2-mv",
  2863. &prop_val);
  2864. if (!rc)
  2865. mb->micb2_mv = prop_val;
  2866. } else {
  2867. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2868. __func__);
  2869. }
  2870. /* MB3 */
  2871. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2872. NULL)) {
  2873. rc = wcd938x_read_of_property_u32(dev,
  2874. "qcom,cdc-micbias3-mv",
  2875. &prop_val);
  2876. if (!rc)
  2877. mb->micb3_mv = prop_val;
  2878. } else {
  2879. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2880. __func__);
  2881. }
  2882. /* MB4 */
  2883. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  2884. NULL)) {
  2885. rc = wcd938x_read_of_property_u32(dev,
  2886. "qcom,cdc-micbias4-mv",
  2887. &prop_val);
  2888. if (!rc)
  2889. mb->micb4_mv = prop_val;
  2890. } else {
  2891. dev_info(dev, "%s: Micbias4 DT property not found\n",
  2892. __func__);
  2893. }
  2894. }
  2895. static int wcd938x_reset_low(struct device *dev)
  2896. {
  2897. struct wcd938x_priv *wcd938x = NULL;
  2898. int rc = 0;
  2899. if (!dev)
  2900. return -ENODEV;
  2901. wcd938x = dev_get_drvdata(dev);
  2902. if (!wcd938x)
  2903. return -EINVAL;
  2904. if (!wcd938x->rst_np) {
  2905. dev_err(dev, "%s: reset gpio device node not specified\n",
  2906. __func__);
  2907. return -EINVAL;
  2908. }
  2909. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2910. if (rc) {
  2911. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2912. __func__);
  2913. return rc;
  2914. }
  2915. /* 20us sleep required after pulling the reset gpio to LOW */
  2916. usleep_range(20, 30);
  2917. return rc;
  2918. }
  2919. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2920. {
  2921. struct wcd938x_pdata *pdata = NULL;
  2922. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2923. GFP_KERNEL);
  2924. if (!pdata)
  2925. return NULL;
  2926. pdata->rst_np = of_parse_phandle(dev->of_node,
  2927. "qcom,wcd-rst-gpio-node", 0);
  2928. if (!pdata->rst_np) {
  2929. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2930. __func__, "qcom,wcd-rst-gpio-node",
  2931. dev->of_node->full_name);
  2932. return NULL;
  2933. }
  2934. /* Parse power supplies */
  2935. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2936. &pdata->num_supplies);
  2937. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2938. dev_err(dev, "%s: no power supplies defined for codec\n",
  2939. __func__);
  2940. return NULL;
  2941. }
  2942. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2943. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2944. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2945. return pdata;
  2946. }
  2947. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  2948. {
  2949. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2950. __func__, irq);
  2951. return IRQ_HANDLED;
  2952. }
  2953. static int wcd938x_bind(struct device *dev)
  2954. {
  2955. int ret = 0, i = 0;
  2956. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2957. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2958. /*
  2959. * Add 5msec delay to provide sufficient time for
  2960. * soundwire auto enumeration of slave devices as
  2961. * as per HW requirement.
  2962. */
  2963. usleep_range(5000, 5010);
  2964. ret = component_bind_all(dev, wcd938x);
  2965. if (ret) {
  2966. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2967. __func__, ret);
  2968. return ret;
  2969. }
  2970. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2971. if (!wcd938x->rx_swr_dev) {
  2972. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2973. __func__);
  2974. ret = -ENODEV;
  2975. goto err;
  2976. }
  2977. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2978. if (!wcd938x->tx_swr_dev) {
  2979. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2980. __func__);
  2981. ret = -ENODEV;
  2982. goto err;
  2983. }
  2984. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2985. &wcd938x_regmap_config);
  2986. if (!wcd938x->regmap) {
  2987. dev_err(dev, "%s: Regmap init failed\n",
  2988. __func__);
  2989. goto err;
  2990. }
  2991. /* Set all interupts as edge triggered */
  2992. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2993. regmap_write(wcd938x->regmap,
  2994. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2995. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2996. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2997. wcd938x->irq_info.codec_name = "WCD938X";
  2998. wcd938x->irq_info.regmap = wcd938x->regmap;
  2999. wcd938x->irq_info.dev = dev;
  3000. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3001. if (ret) {
  3002. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3003. __func__, ret);
  3004. goto err;
  3005. }
  3006. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3007. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3008. if (ret < 0) {
  3009. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3010. goto err_irq;
  3011. }
  3012. /* Request for watchdog interrupt */
  3013. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3014. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3015. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3016. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3017. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3018. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3019. /* Disable watchdog interrupt for HPH and AUX */
  3020. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3021. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3022. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3023. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3024. NULL, 0);
  3025. if (ret) {
  3026. dev_err(dev, "%s: Codec registration failed\n",
  3027. __func__);
  3028. goto err_irq;
  3029. }
  3030. return ret;
  3031. err_irq:
  3032. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3033. err:
  3034. component_unbind_all(dev, wcd938x);
  3035. return ret;
  3036. }
  3037. static void wcd938x_unbind(struct device *dev)
  3038. {
  3039. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3040. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3041. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3042. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3043. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3044. snd_soc_unregister_component(dev);
  3045. component_unbind_all(dev, wcd938x);
  3046. }
  3047. static const struct of_device_id wcd938x_dt_match[] = {
  3048. { .compatible = "qcom,wcd938x-codec" },
  3049. {}
  3050. };
  3051. static const struct component_master_ops wcd938x_comp_ops = {
  3052. .bind = wcd938x_bind,
  3053. .unbind = wcd938x_unbind,
  3054. };
  3055. static int wcd938x_compare_of(struct device *dev, void *data)
  3056. {
  3057. return dev->of_node == data;
  3058. }
  3059. static void wcd938x_release_of(struct device *dev, void *data)
  3060. {
  3061. of_node_put(data);
  3062. }
  3063. static int wcd938x_add_slave_components(struct device *dev,
  3064. struct component_match **matchptr)
  3065. {
  3066. struct device_node *np, *rx_node, *tx_node;
  3067. np = dev->of_node;
  3068. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3069. if (!rx_node) {
  3070. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3071. return -ENODEV;
  3072. }
  3073. of_node_get(rx_node);
  3074. component_match_add_release(dev, matchptr,
  3075. wcd938x_release_of,
  3076. wcd938x_compare_of,
  3077. rx_node);
  3078. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3079. if (!tx_node) {
  3080. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3081. return -ENODEV;
  3082. }
  3083. of_node_get(tx_node);
  3084. component_match_add_release(dev, matchptr,
  3085. wcd938x_release_of,
  3086. wcd938x_compare_of,
  3087. tx_node);
  3088. return 0;
  3089. }
  3090. static int wcd938x_wakeup(void *handle, bool enable)
  3091. {
  3092. struct wcd938x_priv *priv;
  3093. if (!handle) {
  3094. pr_err("%s: NULL handle\n", __func__);
  3095. return -EINVAL;
  3096. }
  3097. priv = (struct wcd938x_priv *)handle;
  3098. if (!priv->tx_swr_dev) {
  3099. pr_err("%s: tx swr dev is NULL\n", __func__);
  3100. return -EINVAL;
  3101. }
  3102. if (enable)
  3103. return swr_device_wakeup_vote(priv->tx_swr_dev);
  3104. else
  3105. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  3106. }
  3107. static int wcd938x_probe(struct platform_device *pdev)
  3108. {
  3109. struct component_match *match = NULL;
  3110. struct wcd938x_priv *wcd938x = NULL;
  3111. struct wcd938x_pdata *pdata = NULL;
  3112. struct wcd_ctrl_platform_data *plat_data = NULL;
  3113. struct device *dev = &pdev->dev;
  3114. int ret;
  3115. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3116. GFP_KERNEL);
  3117. if (!wcd938x)
  3118. return -ENOMEM;
  3119. dev_set_drvdata(dev, wcd938x);
  3120. wcd938x->dev = dev;
  3121. pdata = wcd938x_populate_dt_data(dev);
  3122. if (!pdata) {
  3123. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3124. return -EINVAL;
  3125. }
  3126. dev->platform_data = pdata;
  3127. wcd938x->rst_np = pdata->rst_np;
  3128. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3129. pdata->regulator, pdata->num_supplies);
  3130. if (!wcd938x->supplies) {
  3131. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3132. __func__);
  3133. return ret;
  3134. }
  3135. plat_data = dev_get_platdata(dev->parent);
  3136. if (!plat_data) {
  3137. dev_err(dev, "%s: platform data from parent is NULL\n",
  3138. __func__);
  3139. return -EINVAL;
  3140. }
  3141. wcd938x->handle = (void *)plat_data->handle;
  3142. if (!wcd938x->handle) {
  3143. dev_err(dev, "%s: handle is NULL\n", __func__);
  3144. return -EINVAL;
  3145. }
  3146. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3147. if (!wcd938x->update_wcd_event) {
  3148. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3149. __func__);
  3150. return -EINVAL;
  3151. }
  3152. wcd938x->register_notifier = plat_data->register_notifier;
  3153. if (!wcd938x->register_notifier) {
  3154. dev_err(dev, "%s: register_notifier api is null!\n",
  3155. __func__);
  3156. return -EINVAL;
  3157. }
  3158. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3159. pdata->regulator,
  3160. pdata->num_supplies);
  3161. if (ret) {
  3162. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3163. __func__);
  3164. return ret;
  3165. }
  3166. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3167. CODEC_RX);
  3168. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3169. CODEC_TX);
  3170. if (ret) {
  3171. dev_err(dev, "Failed to read port mapping\n");
  3172. goto err;
  3173. }
  3174. mutex_init(&wcd938x->micb_lock);
  3175. ret = wcd938x_add_slave_components(dev, &match);
  3176. if (ret)
  3177. goto err_lock_init;
  3178. wcd938x_reset(dev);
  3179. wcd938x->wakeup = wcd938x_wakeup;
  3180. return component_master_add_with_match(dev,
  3181. &wcd938x_comp_ops, match);
  3182. err_lock_init:
  3183. mutex_destroy(&wcd938x->micb_lock);
  3184. err:
  3185. return ret;
  3186. }
  3187. static int wcd938x_remove(struct platform_device *pdev)
  3188. {
  3189. struct wcd938x_priv *wcd938x = NULL;
  3190. wcd938x = platform_get_drvdata(pdev);
  3191. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3192. mutex_destroy(&wcd938x->micb_lock);
  3193. dev_set_drvdata(&pdev->dev, NULL);
  3194. return 0;
  3195. }
  3196. #ifdef CONFIG_PM_SLEEP
  3197. static int wcd938x_suspend(struct device *dev)
  3198. {
  3199. return 0;
  3200. }
  3201. static int wcd938x_resume(struct device *dev)
  3202. {
  3203. return 0;
  3204. }
  3205. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3206. SET_SYSTEM_SLEEP_PM_OPS(
  3207. wcd938x_suspend,
  3208. wcd938x_resume
  3209. )
  3210. };
  3211. #endif
  3212. static struct platform_driver wcd938x_codec_driver = {
  3213. .probe = wcd938x_probe,
  3214. .remove = wcd938x_remove,
  3215. .driver = {
  3216. .name = "wcd938x_codec",
  3217. .owner = THIS_MODULE,
  3218. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3219. #ifdef CONFIG_PM_SLEEP
  3220. .pm = &wcd938x_dev_pm_ops,
  3221. #endif
  3222. .suppress_bind_attrs = true,
  3223. },
  3224. };
  3225. module_platform_driver(wcd938x_codec_driver);
  3226. MODULE_DESCRIPTION("WCD938X Codec driver");
  3227. MODULE_LICENSE("GPL v2");