qcs405.c 266 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561556255635564556555665567556855695570557155725573557455755576557755785579558055815582558355845585558655875588558955905591559255935594559555965597559855995600560156025603560456055606560756085609561056115612561356145615561656175618561956205621562256235624562556265627562856295630563156325633563456355636563756385639564056415642564356445645564656475648564956505651565256535654565556565657565856595660566156625663566456655666566756685669567056715672567356745675567656775678567956805681568256835684568556865687568856895690569156925693569456955696569756985699570057015702570357045705570657075708570957105711571257135714571557165717571857195720572157225723572457255726572757285729573057315732573357345735573657375738573957405741574257435744574557465747574857495750575157525753575457555756575757585759576057615762576357645765576657675768576957705771577257735774577557765777577857795780578157825783578457855786578757885789579057915792579357945795579657975798579958005801580258035804580558065807580858095810581158125813581458155816581758185819582058215822582358245825582658275828582958305831583258335834583558365837583858395840584158425843584458455846584758485849585058515852585358545855585658575858585958605861586258635864586558665867586858695870587158725873587458755876587758785879588058815882588358845885588658875888588958905891589258935894589558965897589858995900590159025903590459055906590759085909591059115912591359145915591659175918591959205921592259235924592559265927592859295930593159325933593459355936593759385939594059415942594359445945594659475948594959505951595259535954595559565957595859595960596159625963596459655966596759685969597059715972597359745975597659775978597959805981598259835984598559865987598859895990599159925993599459955996599759985999600060016002600360046005600660076008600960106011601260136014601560166017601860196020602160226023602460256026602760286029603060316032603360346035603660376038603960406041604260436044604560466047604860496050605160526053605460556056605760586059606060616062606360646065606660676068606960706071607260736074607560766077607860796080608160826083608460856086608760886089609060916092609360946095609660976098609961006101610261036104610561066107610861096110611161126113611461156116611761186119612061216122612361246125612661276128612961306131613261336134613561366137613861396140614161426143614461456146614761486149615061516152615361546155615661576158615961606161616261636164616561666167616861696170617161726173617461756176617761786179618061816182618361846185618661876188618961906191619261936194619561966197619861996200620162026203620462056206620762086209621062116212621362146215621662176218621962206221622262236224622562266227622862296230623162326233623462356236623762386239624062416242624362446245624662476248624962506251625262536254625562566257625862596260626162626263626462656266626762686269627062716272627362746275627662776278627962806281628262836284628562866287628862896290629162926293629462956296629762986299630063016302630363046305630663076308630963106311631263136314631563166317631863196320632163226323632463256326632763286329633063316332633363346335633663376338633963406341634263436344634563466347634863496350635163526353635463556356635763586359636063616362636363646365636663676368636963706371637263736374637563766377637863796380638163826383638463856386638763886389639063916392639363946395639663976398639964006401640264036404640564066407640864096410641164126413641464156416641764186419642064216422642364246425642664276428642964306431643264336434643564366437643864396440644164426443644464456446644764486449645064516452645364546455645664576458645964606461646264636464646564666467646864696470647164726473647464756476647764786479648064816482648364846485648664876488648964906491649264936494649564966497649864996500650165026503650465056506650765086509651065116512651365146515651665176518651965206521652265236524652565266527652865296530653165326533653465356536653765386539654065416542654365446545654665476548654965506551655265536554655565566557655865596560656165626563656465656566656765686569657065716572657365746575657665776578657965806581658265836584658565866587658865896590659165926593659465956596659765986599660066016602660366046605660666076608660966106611661266136614661566166617661866196620662166226623662466256626662766286629663066316632663366346635663666376638663966406641664266436644664566466647664866496650665166526653665466556656665766586659666066616662666366646665666666676668666966706671667266736674667566766677667866796680668166826683668466856686668766886689669066916692669366946695669666976698669967006701670267036704670567066707670867096710671167126713671467156716671767186719672067216722672367246725672667276728672967306731673267336734673567366737673867396740674167426743674467456746674767486749675067516752675367546755675667576758675967606761676267636764676567666767676867696770677167726773677467756776677767786779678067816782678367846785678667876788678967906791679267936794679567966797679867996800680168026803680468056806680768086809681068116812681368146815681668176818681968206821682268236824682568266827682868296830683168326833683468356836683768386839684068416842684368446845684668476848684968506851685268536854685568566857685868596860686168626863686468656866686768686869687068716872687368746875687668776878687968806881688268836884688568866887688868896890689168926893689468956896689768986899690069016902690369046905690669076908690969106911691269136914691569166917691869196920692169226923692469256926692769286929693069316932693369346935693669376938693969406941694269436944694569466947694869496950695169526953695469556956695769586959696069616962696369646965696669676968696969706971697269736974697569766977697869796980698169826983698469856986698769886989699069916992699369946995699669976998699970007001700270037004700570067007700870097010701170127013701470157016701770187019702070217022702370247025702670277028702970307031703270337034703570367037703870397040704170427043704470457046704770487049705070517052705370547055705670577058705970607061706270637064706570667067706870697070707170727073707470757076707770787079708070817082708370847085708670877088708970907091709270937094709570967097709870997100710171027103710471057106710771087109711071117112711371147115711671177118711971207121712271237124712571267127712871297130713171327133713471357136713771387139714071417142714371447145714671477148714971507151715271537154715571567157715871597160716171627163716471657166716771687169717071717172717371747175717671777178717971807181718271837184718571867187718871897190719171927193719471957196719771987199720072017202720372047205720672077208720972107211721272137214721572167217721872197220722172227223722472257226722772287229723072317232723372347235723672377238723972407241724272437244724572467247724872497250725172527253725472557256725772587259726072617262726372647265726672677268726972707271727272737274727572767277727872797280728172827283728472857286728772887289729072917292729372947295729672977298729973007301730273037304730573067307730873097310731173127313731473157316731773187319732073217322732373247325732673277328732973307331733273337334733573367337733873397340734173427343734473457346734773487349735073517352735373547355735673577358735973607361736273637364736573667367736873697370737173727373737473757376737773787379738073817382738373847385738673877388738973907391739273937394739573967397739873997400740174027403740474057406740774087409741074117412741374147415741674177418741974207421742274237424742574267427742874297430743174327433743474357436743774387439744074417442744374447445744674477448744974507451745274537454745574567457745874597460746174627463746474657466746774687469747074717472747374747475747674777478747974807481748274837484748574867487748874897490749174927493749474957496749774987499750075017502750375047505750675077508750975107511751275137514751575167517751875197520752175227523752475257526752775287529753075317532753375347535753675377538753975407541754275437544754575467547754875497550755175527553755475557556755775587559756075617562756375647565756675677568756975707571757275737574757575767577757875797580758175827583758475857586758775887589759075917592759375947595759675977598759976007601760276037604760576067607760876097610761176127613761476157616761776187619762076217622762376247625762676277628762976307631763276337634763576367637763876397640764176427643764476457646764776487649765076517652765376547655765676577658765976607661766276637664766576667667766876697670767176727673767476757676767776787679768076817682768376847685768676877688768976907691769276937694769576967697769876997700770177027703770477057706770777087709771077117712771377147715771677177718771977207721772277237724772577267727772877297730773177327733773477357736773777387739774077417742774377447745774677477748774977507751775277537754775577567757775877597760776177627763776477657766776777687769777077717772777377747775777677777778777977807781778277837784778577867787778877897790779177927793779477957796779777987799780078017802780378047805780678077808780978107811781278137814781578167817781878197820782178227823782478257826782778287829783078317832783378347835783678377838783978407841784278437844784578467847784878497850785178527853785478557856785778587859786078617862786378647865786678677868786978707871787278737874787578767877787878797880788178827883788478857886788778887889789078917892789378947895789678977898789979007901790279037904790579067907790879097910791179127913791479157916791779187919792079217922792379247925792679277928792979307931793279337934793579367937793879397940794179427943794479457946794779487949795079517952795379547955795679577958795979607961796279637964796579667967796879697970797179727973797479757976797779787979798079817982798379847985798679877988798979907991799279937994799579967997799879998000800180028003800480058006800780088009801080118012801380148015801680178018801980208021802280238024802580268027802880298030803180328033803480358036803780388039804080418042804380448045804680478048804980508051805280538054805580568057805880598060806180628063806480658066806780688069807080718072807380748075807680778078807980808081808280838084808580868087808880898090809180928093809480958096809780988099810081018102810381048105810681078108810981108111811281138114811581168117811881198120812181228123812481258126812781288129813081318132813381348135813681378138813981408141814281438144814581468147814881498150815181528153815481558156815781588159816081618162816381648165816681678168816981708171817281738174817581768177817881798180818181828183818481858186818781888189819081918192819381948195819681978198819982008201820282038204820582068207820882098210821182128213821482158216821782188219822082218222822382248225822682278228822982308231823282338234823582368237823882398240824182428243824482458246824782488249825082518252825382548255825682578258825982608261826282638264826582668267826882698270827182728273827482758276827782788279828082818282828382848285828682878288828982908291829282938294829582968297829882998300830183028303830483058306830783088309831083118312831383148315831683178318831983208321832283238324832583268327832883298330833183328333833483358336833783388339834083418342834383448345834683478348834983508351835283538354835583568357835883598360836183628363836483658366836783688369837083718372837383748375837683778378837983808381838283838384838583868387838883898390839183928393839483958396839783988399840084018402840384048405840684078408840984108411841284138414841584168417841884198420842184228423842484258426842784288429843084318432843384348435843684378438843984408441844284438444844584468447844884498450845184528453845484558456845784588459846084618462846384648465846684678468846984708471847284738474847584768477847884798480848184828483848484858486848784888489849084918492849384948495849684978498849985008501850285038504850585068507850885098510851185128513851485158516851785188519852085218522852385248525852685278528852985308531853285338534853585368537853885398540854185428543854485458546854785488549855085518552855385548555855685578558855985608561856285638564856585668567856885698570857185728573857485758576857785788579858085818582858385848585858685878588858985908591859285938594859585968597859885998600860186028603860486058606860786088609861086118612861386148615861686178618861986208621862286238624862586268627862886298630863186328633863486358636863786388639864086418642864386448645864686478648864986508651865286538654865586568657865886598660866186628663866486658666866786688669867086718672867386748675867686778678867986808681868286838684868586868687868886898690869186928693869486958696869786988699870087018702870387048705870687078708870987108711871287138714871587168717871887198720872187228723872487258726872787288729873087318732873387348735873687378738873987408741874287438744874587468747874887498750875187528753875487558756875787588759876087618762876387648765876687678768876987708771877287738774877587768777877887798780878187828783878487858786878787888789879087918792879387948795879687978798879988008801880288038804880588068807880888098810881188128813881488158816881788188819882088218822882388248825882688278828882988308831883288338834883588368837883888398840884188428843884488458846884788488849885088518852885388548855885688578858885988608861886288638864886588668867886888698870887188728873887488758876887788788879888088818882888388848885888688878888888988908891889288938894889588968897889888998900890189028903890489058906890789088909891089118912891389148915891689178918891989208921892289238924892589268927892889298930893189328933893489358936893789388939894089418942894389448945894689478948894989508951895289538954895589568957895889598960896189628963896489658966896789688969897089718972897389748975897689778978897989808981898289838984898589868987898889898990899189928993899489958996899789988999900090019002900390049005900690079008900990109011901290139014901590169017901890199020902190229023902490259026902790289029903090319032903390349035903690379038903990409041904290439044904590469047904890499050905190529053905490559056905790589059906090619062906390649065906690679068906990709071907290739074907590769077907890799080908190829083908490859086908790889089909090919092909390949095909690979098909991009101910291039104910591069107910891099110911191129113911491159116911791189119912091219122912391249125912691279128912991309131913291339134913591369137913891399140914191429143914491459146914791489149915091519152915391549155915691579158915991609161916291639164916591669167916891699170917191729173917491759176917791789179918091819182918391849185918691879188918991909191919291939194919591969197919891999200920192029203920492059206920792089209921092119212921392149215921692179218921992209221922292239224922592269227922892299230923192329233923492359236923792389239924092419242924392449245924692479248924992509251925292539254925592569257925892599260926192629263926492659266926792689269927092719272927392749275927692779278927992809281928292839284928592869287928892899290929192929293929492959296929792989299930093019302930393049305930693079308930993109311931293139314931593169317931893199320932193229323932493259326932793289329933093319332933393349335933693379338933993409341934293439344934593469347934893499350935193529353935493559356935793589359936093619362936393649365936693679368936993709371937293739374937593769377937893799380938193829383938493859386938793889389939093919392939393949395939693979398939994009401940294039404940594069407940894099410941194129413941494159416941794189419942094219422942394249425942694279428942994309431943294339434943594369437943894399440944194429443944494459446944794489449945094519452945394549455945694579458945994609461946294639464946594669467946894699470947194729473947494759476947794789479948094819482948394849485948694879488948994909491949294939494949594969497949894999500950195029503950495059506950795089509951095119512951395149515951695179518951995209521952295239524952595269527952895299530953195329533953495359536953795389539954095419542954395449545954695479548954995509551955295539554955595569557955895599560956195629563956495659566956795689569957095719572957395749575957695779578957995809581958295839584958595869587958895899590959195929593959495959596959795989599960096019602960396049605960696079608
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/clk.h>
  5. #include <linux/delay.h>
  6. #include <linux/gpio.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/i2c.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <sound/core.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/info.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <dsp/q6afe-v2.h>
  25. #include <dsp/q6core.h>
  26. #include <dsp/msm_mdf.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include <asoc/msm-cdc-pinctrl.h>
  30. #include "codecs/wcd9335.h"
  31. #include "codecs/wsa881x.h"
  32. #include "codecs/csra66x0/csra66x0.h"
  33. #include <dt-bindings/sound/audio-codec-port-types.h>
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include "codecs/bolero/wsa-macro.h"
  36. #define DRV_NAME "qcs405-asoc-snd"
  37. #define __CHIPSET__ "QCS405 "
  38. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  39. #define DEV_NAME_STR_LEN 32
  40. #define SAMPLING_RATE_8KHZ 8000
  41. #define SAMPLING_RATE_11P025KHZ 11025
  42. #define SAMPLING_RATE_16KHZ 16000
  43. #define SAMPLING_RATE_22P05KHZ 22050
  44. #define SAMPLING_RATE_32KHZ 32000
  45. #define SAMPLING_RATE_44P1KHZ 44100
  46. #define SAMPLING_RATE_48KHZ 48000
  47. #define SAMPLING_RATE_88P2KHZ 88200
  48. #define SAMPLING_RATE_96KHZ 96000
  49. #define SAMPLING_RATE_176P4KHZ 176400
  50. #define SAMPLING_RATE_192KHZ 192000
  51. #define SAMPLING_RATE_352P8KHZ 352800
  52. #define SAMPLING_RATE_384KHZ 384000
  53. #define SPDIF_TX_CORE_CLK_163_P84_MHZ 163840000
  54. #define TLMM_EAST_SPARE 0x07BA0000
  55. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  56. #define WSA8810_NAME_1 "wsa881x.20170211"
  57. #define WSA8810_NAME_2 "wsa881x.20170212"
  58. #define WCN_CDC_SLIM_RX_CH_MAX 2
  59. #define WCN_CDC_SLIM_TX_CH_MAX 4
  60. #define TDM_CHANNEL_MAX 8
  61. #define BT_SLIM_TX SLIM_TX_9
  62. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  63. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  64. enum {
  65. SLIM_RX_0 = 0,
  66. SLIM_RX_1,
  67. SLIM_RX_2,
  68. SLIM_RX_3,
  69. SLIM_RX_4,
  70. SLIM_RX_5,
  71. SLIM_RX_6,
  72. SLIM_RX_7,
  73. SLIM_RX_MAX,
  74. };
  75. enum {
  76. SLIM_TX_0 = 0,
  77. SLIM_TX_1,
  78. SLIM_TX_2,
  79. SLIM_TX_3,
  80. SLIM_TX_4,
  81. SLIM_TX_5,
  82. SLIM_TX_6,
  83. SLIM_TX_7,
  84. SLIM_TX_8,
  85. SLIM_TX_9,
  86. SLIM_TX_MAX,
  87. };
  88. enum {
  89. PRIM_MI2S = 0,
  90. SEC_MI2S,
  91. TERT_MI2S,
  92. QUAT_MI2S,
  93. QUIN_MI2S,
  94. SEN_MI2S,
  95. MI2S_MAX,
  96. };
  97. enum {
  98. PRIM_META_MI2S = 0,
  99. SEC_META_MI2S,
  100. META_MI2S_MAX,
  101. };
  102. enum {
  103. PRIM_AUX_PCM = 0,
  104. SEC_AUX_PCM,
  105. TERT_AUX_PCM,
  106. QUAT_AUX_PCM,
  107. QUIN_AUX_PCM,
  108. SEN_AUX_PCM,
  109. AUX_PCM_MAX,
  110. };
  111. enum {
  112. WSA_CDC_DMA_RX_0 = 0,
  113. WSA_CDC_DMA_RX_1,
  114. CDC_DMA_RX_MAX,
  115. };
  116. enum {
  117. WSA_CDC_DMA_TX_0 = 0,
  118. WSA_CDC_DMA_TX_1,
  119. WSA_CDC_DMA_TX_2,
  120. VA_CDC_DMA_TX_0,
  121. VA_CDC_DMA_TX_1,
  122. CDC_DMA_TX_MAX,
  123. };
  124. enum {
  125. PRIM_SPDIF_RX = 0,
  126. SEC_SPDIF_RX,
  127. SPDIF_RX_MAX,
  128. };
  129. enum {
  130. PRIM_SPDIF_TX = 0,
  131. SEC_SPDIF_TX,
  132. SPDIF_TX_MAX,
  133. };
  134. struct mi2s_conf {
  135. struct mutex lock;
  136. u32 ref_cnt;
  137. u32 msm_is_mi2s_master;
  138. };
  139. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  140. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  141. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  142. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  143. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  144. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT,
  145. Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT
  146. };
  147. struct meta_mi2s_conf {
  148. u32 num_member_ports;
  149. u32 member_port[MAX_NUM_I2S_META_PORT_MEMBER_PORTS];
  150. bool clk_enable[MAX_NUM_I2S_META_PORT_MEMBER_PORTS];
  151. };
  152. struct dev_config {
  153. u32 sample_rate;
  154. u32 bit_format;
  155. u32 channels;
  156. };
  157. struct msm_wsa881x_dev_info {
  158. struct device_node *of_node;
  159. u32 index;
  160. };
  161. struct msm_csra66x0_dev_info {
  162. struct device_node *of_node;
  163. u32 index;
  164. };
  165. struct msm_asoc_mach_data {
  166. struct snd_info_entry *codec_root;
  167. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  168. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  169. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  170. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  171. struct device_node *lineout_booster_gpio_p; /* used by pinctrl API */
  172. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  173. int dmic_01_gpio_cnt;
  174. int dmic_23_gpio_cnt;
  175. int dmic_45_gpio_cnt;
  176. int dmic_67_gpio_cnt;
  177. struct regulator *tdm_micb_supply;
  178. u32 tdm_micb_voltage;
  179. u32 tdm_micb_current;
  180. bool codec_is_csra;
  181. };
  182. struct msm_asoc_wcd93xx_codec {
  183. void* (*get_afe_config_fn)(struct snd_soc_component *component,
  184. enum afe_config_type config_type);
  185. };
  186. static const char *const pin_states[] = {"sleep", "i2s-active",
  187. "tdm-active"};
  188. enum {
  189. TDM_0 = 0,
  190. TDM_1,
  191. TDM_2,
  192. TDM_3,
  193. TDM_4,
  194. TDM_5,
  195. TDM_6,
  196. TDM_7,
  197. TDM_PORT_MAX,
  198. };
  199. enum {
  200. TDM_PRI = 0,
  201. TDM_SEC,
  202. TDM_TERT,
  203. TDM_QUAT,
  204. TDM_QUIN,
  205. TDM_INTERFACE_MAX,
  206. };
  207. struct tdm_port {
  208. u32 mode;
  209. u32 channel;
  210. };
  211. /* TDM default config */
  212. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  213. { /* PRI TDM */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  222. },
  223. { /* SEC TDM */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  232. },
  233. { /* TERT TDM */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  242. },
  243. { /* QUAT TDM */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  252. },
  253. { /* QUIN TDM */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  262. }
  263. };
  264. /* TDM default config */
  265. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  266. { /* PRI TDM */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  275. },
  276. { /* SEC TDM */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  285. },
  286. { /* TERT TDM */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  295. },
  296. { /* QUAT TDM */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  305. },
  306. { /* QUIN TDM */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  315. }
  316. };
  317. /* Default configuration of slimbus channels */
  318. static struct dev_config slim_rx_cfg[] = {
  319. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  327. };
  328. static struct dev_config slim_tx_cfg[] = {
  329. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  330. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  331. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  332. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  333. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  334. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  335. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  336. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  337. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  338. [SLIM_TX_9] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  339. };
  340. /* Default configuration of Codec DMA Interface Tx */
  341. static struct dev_config cdc_dma_rx_cfg[] = {
  342. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  343. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  344. };
  345. /* Default configuration of Codec DMA Interface Rx */
  346. static struct dev_config cdc_dma_tx_cfg[] = {
  347. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  349. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  350. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  351. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  352. };
  353. static struct dev_config usb_rx_cfg = {
  354. .sample_rate = SAMPLING_RATE_48KHZ,
  355. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  356. .channels = 2,
  357. };
  358. static struct dev_config usb_tx_cfg = {
  359. .sample_rate = SAMPLING_RATE_48KHZ,
  360. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  361. .channels = 1,
  362. };
  363. static struct dev_config proxy_rx_cfg = {
  364. .sample_rate = SAMPLING_RATE_48KHZ,
  365. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  366. .channels = 2,
  367. };
  368. /* Default configuration of MI2S channels */
  369. static struct dev_config mi2s_rx_cfg[] = {
  370. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  371. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  372. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  373. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  374. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  375. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  376. };
  377. static struct dev_config meta_mi2s_rx_cfg[] = {
  378. [PRIM_META_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  379. [SEC_META_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  380. };
  381. /* Default configuration of SPDIF channels */
  382. static struct dev_config spdif_rx_cfg[] = {
  383. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  384. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  385. };
  386. static struct dev_config spdif_tx_cfg[] = {
  387. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  388. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  389. };
  390. static struct dev_config mi2s_tx_cfg[] = {
  391. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  392. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  393. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. };
  398. static struct dev_config aux_pcm_rx_cfg[] = {
  399. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  400. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  401. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  402. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  403. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  404. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  405. };
  406. static struct dev_config aux_pcm_tx_cfg[] = {
  407. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  408. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  409. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  410. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  411. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  412. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  413. };
  414. static struct dev_config afe_lb_tx_cfg = {
  415. .sample_rate = SAMPLING_RATE_48KHZ,
  416. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  417. .channels = 2,
  418. };
  419. static int msm_vi_feed_tx_ch = 2;
  420. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  421. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  422. "Five", "Six", "Seven",
  423. "Eight"};
  424. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  425. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  426. "S32_LE"};
  427. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  428. "KHZ_32", "KHZ_44P1", "KHZ_48",
  429. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  430. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  431. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  432. "KHZ_44P1", "KHZ_48",
  433. "KHZ_88P2", "KHZ_96"};
  434. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  435. "Five", "Six", "Seven",
  436. "Eight"};
  437. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  438. "Six", "Seven", "Eight"};
  439. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  440. "KHZ_16", "KHZ_22P05",
  441. "KHZ_32", "KHZ_44P1", "KHZ_48",
  442. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  443. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  444. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  445. "Five", "Six", "Seven", "Eight"};
  446. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  447. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  448. "KHZ_48", "KHZ_176P4",
  449. "KHZ_352P8"};
  450. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  451. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  452. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  453. "KHZ_48", "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  454. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  455. static const char *const mi2s_ch_text[] = {
  456. "One", "Two", "Three", "Four", "Five", "Six", "Seven",
  457. "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
  458. "Fourteen", "Fifteen", "Sixteen"
  459. };
  460. static const char *const meta_mi2s_ch_text[] = {
  461. "One", "Two", "Three", "Four", "Five", "Six", "Seven",
  462. "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
  463. "Fourteen", "Fifteen", "Sixteen", "Seventeen", "Eighteen",
  464. "Nineteen", "Twenty", "TwentyOne", "TwentyTwo", "TwentyThree",
  465. "TwentyFour", "TwentyFive", "TwentySix", "TwentySeven",
  466. "TwentyEight", "TwentyNine", "Thirty", "ThirtyOne", "ThirtyTwo"
  467. };
  468. static const char *const qos_text[] = {"Disable", "Enable"};
  469. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  470. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  471. "Five", "Six", "Seven", "Eight", "Nine", "Ten", "Eleven",
  472. "Twelve", "Thirteen", "Fourteen", "Fifteen", "Sixteen"};
  473. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  474. "KHZ_16", "KHZ_22P05",
  475. "KHZ_32", "KHZ_44P1", "KHZ_48",
  476. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  477. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  478. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  479. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  480. "KHZ_192"};
  481. static const char *spdif_ch_text[] = {"One", "Two"};
  482. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  483. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_sink, bt_sample_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(prim_meta_mi2s_rx_sample_rate, mi2s_rate_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(sec_meta_mi2s_rx_sample_rate, mi2s_rate_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(prim_meta_mi2s_rx_chs, meta_mi2s_ch_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(sec_meta_mi2s_rx_chs, meta_mi2s_ch_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(prim_meta_mi2s_rx_format, bit_format_text);
  559. static SOC_ENUM_SINGLE_EXT_DECL(sec_meta_mi2s_rx_format, bit_format_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  562. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  563. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  564. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  565. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  566. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  567. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  568. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  569. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  570. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  571. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  572. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  573. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  574. cdc_dma_sample_rate_text);
  575. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  576. cdc_dma_sample_rate_text);
  577. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  578. cdc_dma_sample_rate_text);
  579. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  580. cdc_dma_sample_rate_text);
  581. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  582. cdc_dma_sample_rate_text);
  583. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  584. cdc_dma_sample_rate_text);
  585. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  586. cdc_dma_sample_rate_text);
  587. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  588. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  589. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  590. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  591. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  592. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  593. static SOC_ENUM_SINGLE_EXT_DECL(afe_lb_tx_chs, cdc_dma_tx_ch_text);
  594. static SOC_ENUM_SINGLE_EXT_DECL(afe_lb_tx_format, bit_format_text);
  595. static SOC_ENUM_SINGLE_EXT_DECL(afe_lb_tx_sample_rate,
  596. cdc_dma_sample_rate_text);
  597. static struct platform_device *spdev;
  598. static bool is_initial_boot;
  599. static bool codec_reg_done;
  600. static struct snd_soc_aux_dev *msm_aux_dev;
  601. static struct snd_soc_codec_conf *msm_codec_conf;
  602. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  603. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  604. int enable, bool dapm);
  605. static int msm_wsa881x_init(struct snd_soc_component *component);
  606. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  607. struct snd_ctl_elem_value *ucontrol);
  608. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  609. {"MIC BIAS1", NULL, "MCLK TX"},
  610. {"MIC BIAS2", NULL, "MCLK TX"},
  611. {"MIC BIAS3", NULL, "MCLK TX"},
  612. {"MIC BIAS4", NULL, "MCLK TX"},
  613. };
  614. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  615. {
  616. AFE_API_VERSION_I2S_CONFIG,
  617. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  618. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  619. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  620. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  621. 0,
  622. },
  623. {
  624. AFE_API_VERSION_I2S_CONFIG,
  625. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  626. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  627. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  628. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  629. 0,
  630. },
  631. {
  632. AFE_API_VERSION_I2S_CONFIG,
  633. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  634. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  635. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  636. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  637. 0,
  638. },
  639. {
  640. AFE_API_VERSION_I2S_CONFIG,
  641. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  642. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  643. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  644. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  645. 0,
  646. },
  647. {
  648. AFE_API_VERSION_I2S_CONFIG,
  649. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  650. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  651. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  652. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  653. 0,
  654. },
  655. {
  656. AFE_API_VERSION_I2S_CONFIG,
  657. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  658. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  659. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  660. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  661. 0,
  662. }
  663. };
  664. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  665. static struct meta_mi2s_conf meta_mi2s_intf_conf[META_MI2S_MAX];
  666. static int msm_island_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  667. {
  668. *port_id = 0xFFFF;
  669. switch (be_id) {
  670. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  671. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  672. break;
  673. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  674. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  675. break;
  676. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  677. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  678. break;
  679. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  680. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  681. break;
  682. default:
  683. return -EINVAL;
  684. }
  685. return 0;
  686. }
  687. static int qcs405_send_island_vad_config(int32_t be_id)
  688. {
  689. int rc = 0;
  690. int port_id = 0xFFFF;
  691. rc = msm_island_vad_get_portid_from_beid(be_id, &port_id);
  692. if (rc) {
  693. pr_debug("%s: Invalid island interface\n", __func__);
  694. } else {
  695. /*
  696. * send island mode config
  697. * This should be the first configuration
  698. */
  699. rc = afe_send_port_island_mode(port_id);
  700. if (rc) {
  701. pr_err("%s: afe send island mode failed %d\n",
  702. __func__, rc);
  703. return rc;
  704. }
  705. rc = afe_send_port_vad_cfg_params(port_id);
  706. if (rc) {
  707. pr_err("%s: afe send vad config failed %d\n",
  708. __func__, rc);
  709. return rc;
  710. }
  711. }
  712. return 0;
  713. }
  714. static int slim_get_sample_rate_val(int sample_rate)
  715. {
  716. int sample_rate_val = 0;
  717. switch (sample_rate) {
  718. case SAMPLING_RATE_8KHZ:
  719. sample_rate_val = 0;
  720. break;
  721. case SAMPLING_RATE_16KHZ:
  722. sample_rate_val = 1;
  723. break;
  724. case SAMPLING_RATE_32KHZ:
  725. sample_rate_val = 2;
  726. break;
  727. case SAMPLING_RATE_44P1KHZ:
  728. sample_rate_val = 3;
  729. break;
  730. case SAMPLING_RATE_48KHZ:
  731. sample_rate_val = 4;
  732. break;
  733. case SAMPLING_RATE_88P2KHZ:
  734. sample_rate_val = 5;
  735. break;
  736. case SAMPLING_RATE_96KHZ:
  737. sample_rate_val = 6;
  738. break;
  739. case SAMPLING_RATE_176P4KHZ:
  740. sample_rate_val = 7;
  741. break;
  742. case SAMPLING_RATE_192KHZ:
  743. sample_rate_val = 8;
  744. break;
  745. case SAMPLING_RATE_352P8KHZ:
  746. sample_rate_val = 9;
  747. break;
  748. case SAMPLING_RATE_384KHZ:
  749. sample_rate_val = 10;
  750. break;
  751. default:
  752. sample_rate_val = 4;
  753. break;
  754. }
  755. return sample_rate_val;
  756. }
  757. static int slim_get_sample_rate(int value)
  758. {
  759. int sample_rate = 0;
  760. switch (value) {
  761. case 0:
  762. sample_rate = SAMPLING_RATE_8KHZ;
  763. break;
  764. case 1:
  765. sample_rate = SAMPLING_RATE_16KHZ;
  766. break;
  767. case 2:
  768. sample_rate = SAMPLING_RATE_32KHZ;
  769. break;
  770. case 3:
  771. sample_rate = SAMPLING_RATE_44P1KHZ;
  772. break;
  773. case 4:
  774. sample_rate = SAMPLING_RATE_48KHZ;
  775. break;
  776. case 5:
  777. sample_rate = SAMPLING_RATE_88P2KHZ;
  778. break;
  779. case 6:
  780. sample_rate = SAMPLING_RATE_96KHZ;
  781. break;
  782. case 7:
  783. sample_rate = SAMPLING_RATE_176P4KHZ;
  784. break;
  785. case 8:
  786. sample_rate = SAMPLING_RATE_192KHZ;
  787. break;
  788. case 9:
  789. sample_rate = SAMPLING_RATE_352P8KHZ;
  790. break;
  791. case 10:
  792. sample_rate = SAMPLING_RATE_384KHZ;
  793. break;
  794. default:
  795. sample_rate = SAMPLING_RATE_48KHZ;
  796. break;
  797. }
  798. return sample_rate;
  799. }
  800. static int slim_get_bit_format_val(int bit_format)
  801. {
  802. int val = 0;
  803. switch (bit_format) {
  804. case SNDRV_PCM_FORMAT_S32_LE:
  805. val = 3;
  806. break;
  807. case SNDRV_PCM_FORMAT_S24_3LE:
  808. val = 2;
  809. break;
  810. case SNDRV_PCM_FORMAT_S24_LE:
  811. val = 1;
  812. break;
  813. case SNDRV_PCM_FORMAT_S16_LE:
  814. default:
  815. val = 0;
  816. break;
  817. }
  818. return val;
  819. }
  820. static int slim_get_bit_format(int val)
  821. {
  822. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  823. switch (val) {
  824. case 0:
  825. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  826. break;
  827. case 1:
  828. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  829. break;
  830. case 2:
  831. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  832. break;
  833. case 3:
  834. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  835. break;
  836. default:
  837. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  838. break;
  839. }
  840. return bit_fmt;
  841. }
  842. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  843. {
  844. int port_id = 0;
  845. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  846. port_id = SLIM_RX_0;
  847. } else if (strnstr(kcontrol->id.name,
  848. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  849. port_id = SLIM_RX_2;
  850. } else if (strnstr(kcontrol->id.name,
  851. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  852. port_id = SLIM_RX_5;
  853. } else if (strnstr(kcontrol->id.name,
  854. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  855. port_id = SLIM_RX_6;
  856. } else if (strnstr(kcontrol->id.name,
  857. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  858. port_id = SLIM_TX_0;
  859. } else if (strnstr(kcontrol->id.name,
  860. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  861. port_id = SLIM_TX_1;
  862. } else {
  863. pr_err("%s: unsupported channel: %s",
  864. __func__, kcontrol->id.name);
  865. return -EINVAL;
  866. }
  867. return port_id;
  868. }
  869. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  870. struct snd_ctl_elem_value *ucontrol)
  871. {
  872. int ch_num = slim_get_port_idx(kcontrol);
  873. if (ch_num < 0)
  874. return ch_num;
  875. ucontrol->value.enumerated.item[0] =
  876. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  877. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  878. ch_num, slim_rx_cfg[ch_num].sample_rate,
  879. ucontrol->value.enumerated.item[0]);
  880. return 0;
  881. }
  882. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  883. struct snd_ctl_elem_value *ucontrol)
  884. {
  885. int ch_num = slim_get_port_idx(kcontrol);
  886. if (ch_num < 0)
  887. return ch_num;
  888. slim_rx_cfg[ch_num].sample_rate =
  889. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  890. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  891. ch_num, slim_rx_cfg[ch_num].sample_rate,
  892. ucontrol->value.enumerated.item[0]);
  893. return 0;
  894. }
  895. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  896. struct snd_ctl_elem_value *ucontrol)
  897. {
  898. int ch_num = slim_get_port_idx(kcontrol);
  899. if (ch_num < 0)
  900. return ch_num;
  901. ucontrol->value.enumerated.item[0] =
  902. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  903. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  904. ch_num, slim_tx_cfg[ch_num].sample_rate,
  905. ucontrol->value.enumerated.item[0]);
  906. return 0;
  907. }
  908. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  909. struct snd_ctl_elem_value *ucontrol)
  910. {
  911. int sample_rate = 0;
  912. int ch_num = slim_get_port_idx(kcontrol);
  913. if (ch_num < 0)
  914. return ch_num;
  915. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  916. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  917. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  918. __func__, sample_rate);
  919. return -EINVAL;
  920. }
  921. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  922. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  923. ch_num, slim_tx_cfg[ch_num].sample_rate,
  924. ucontrol->value.enumerated.item[0]);
  925. return 0;
  926. }
  927. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  928. struct snd_ctl_elem_value *ucontrol)
  929. {
  930. int ch_num = slim_get_port_idx(kcontrol);
  931. if (ch_num < 0)
  932. return ch_num;
  933. ucontrol->value.enumerated.item[0] =
  934. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  935. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  936. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  937. ucontrol->value.enumerated.item[0]);
  938. return 0;
  939. }
  940. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  941. struct snd_ctl_elem_value *ucontrol)
  942. {
  943. int ch_num = slim_get_port_idx(kcontrol);
  944. if (ch_num < 0)
  945. return ch_num;
  946. slim_rx_cfg[ch_num].bit_format =
  947. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  948. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  949. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  950. ucontrol->value.enumerated.item[0]);
  951. return 0;
  952. }
  953. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  954. struct snd_ctl_elem_value *ucontrol)
  955. {
  956. int ch_num = slim_get_port_idx(kcontrol);
  957. if (ch_num < 0)
  958. return ch_num;
  959. ucontrol->value.enumerated.item[0] =
  960. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  961. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  962. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  963. ucontrol->value.enumerated.item[0]);
  964. return 0;
  965. }
  966. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  967. struct snd_ctl_elem_value *ucontrol)
  968. {
  969. int ch_num = slim_get_port_idx(kcontrol);
  970. if (ch_num < 0)
  971. return ch_num;
  972. slim_tx_cfg[ch_num].bit_format =
  973. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  974. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  975. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  976. ucontrol->value.enumerated.item[0]);
  977. return 0;
  978. }
  979. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  980. struct snd_ctl_elem_value *ucontrol)
  981. {
  982. int ch_num = slim_get_port_idx(kcontrol);
  983. if (ch_num < 0)
  984. return ch_num;
  985. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  986. ch_num, slim_rx_cfg[ch_num].channels);
  987. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  988. return 0;
  989. }
  990. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  991. struct snd_ctl_elem_value *ucontrol)
  992. {
  993. int ch_num = slim_get_port_idx(kcontrol);
  994. if (ch_num < 0)
  995. return ch_num;
  996. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  997. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  998. ch_num, slim_rx_cfg[ch_num].channels);
  999. return 1;
  1000. }
  1001. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  1002. struct snd_ctl_elem_value *ucontrol)
  1003. {
  1004. int ch_num = slim_get_port_idx(kcontrol);
  1005. if (ch_num < 0)
  1006. return ch_num;
  1007. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  1008. ch_num, slim_tx_cfg[ch_num].channels);
  1009. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  1010. return 0;
  1011. }
  1012. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  1013. struct snd_ctl_elem_value *ucontrol)
  1014. {
  1015. int ch_num = slim_get_port_idx(kcontrol);
  1016. if (ch_num < 0)
  1017. return ch_num;
  1018. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  1019. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  1020. ch_num, slim_tx_cfg[ch_num].channels);
  1021. return 1;
  1022. }
  1023. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  1024. struct snd_ctl_elem_value *ucontrol)
  1025. {
  1026. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  1027. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  1028. ucontrol->value.integer.value[0]);
  1029. return 0;
  1030. }
  1031. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1032. struct snd_ctl_elem_value *ucontrol)
  1033. {
  1034. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1035. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1036. return 1;
  1037. }
  1038. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  1039. struct snd_ctl_elem_value *ucontrol)
  1040. {
  1041. /*
  1042. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  1043. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  1044. * value.
  1045. */
  1046. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  1047. case SAMPLING_RATE_96KHZ:
  1048. ucontrol->value.integer.value[0] = 5;
  1049. break;
  1050. case SAMPLING_RATE_88P2KHZ:
  1051. ucontrol->value.integer.value[0] = 4;
  1052. break;
  1053. case SAMPLING_RATE_48KHZ:
  1054. ucontrol->value.integer.value[0] = 3;
  1055. break;
  1056. case SAMPLING_RATE_44P1KHZ:
  1057. ucontrol->value.integer.value[0] = 2;
  1058. break;
  1059. case SAMPLING_RATE_16KHZ:
  1060. ucontrol->value.integer.value[0] = 1;
  1061. break;
  1062. case SAMPLING_RATE_8KHZ:
  1063. default:
  1064. ucontrol->value.integer.value[0] = 0;
  1065. break;
  1066. }
  1067. pr_debug("%s: sample rate = %d", __func__,
  1068. slim_rx_cfg[SLIM_RX_7].sample_rate);
  1069. return 0;
  1070. }
  1071. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  1072. struct snd_ctl_elem_value *ucontrol)
  1073. {
  1074. switch (ucontrol->value.integer.value[0]) {
  1075. case 1:
  1076. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  1077. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  1078. break;
  1079. case 2:
  1080. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  1081. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  1082. break;
  1083. case 3:
  1084. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1085. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1086. break;
  1087. case 4:
  1088. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1089. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1090. break;
  1091. case 5:
  1092. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1093. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1094. break;
  1095. case 0:
  1096. default:
  1097. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1098. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1099. break;
  1100. }
  1101. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1102. __func__,
  1103. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1104. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1105. ucontrol->value.enumerated.item[0]);
  1106. return 0;
  1107. }
  1108. static int msm_bt_sample_rate_sink_get(struct snd_kcontrol *kcontrol,
  1109. struct snd_ctl_elem_value *ucontrol)
  1110. {
  1111. switch (slim_tx_cfg[BT_SLIM_TX].sample_rate) {
  1112. case SAMPLING_RATE_96KHZ:
  1113. ucontrol->value.integer.value[0] = 5;
  1114. break;
  1115. case SAMPLING_RATE_88P2KHZ:
  1116. ucontrol->value.integer.value[0] = 4;
  1117. break;
  1118. case SAMPLING_RATE_48KHZ:
  1119. ucontrol->value.integer.value[0] = 3;
  1120. break;
  1121. case SAMPLING_RATE_44P1KHZ:
  1122. ucontrol->value.integer.value[0] = 2;
  1123. break;
  1124. case SAMPLING_RATE_16KHZ:
  1125. ucontrol->value.integer.value[0] = 1;
  1126. break;
  1127. case SAMPLING_RATE_8KHZ:
  1128. default:
  1129. ucontrol->value.integer.value[0] = 0;
  1130. break;
  1131. }
  1132. pr_debug("%s: sample rate = %d", __func__,
  1133. slim_tx_cfg[BT_SLIM_TX].sample_rate);
  1134. return 0;
  1135. }
  1136. static int msm_bt_sample_rate_sink_put(struct snd_kcontrol *kcontrol,
  1137. struct snd_ctl_elem_value *ucontrol)
  1138. {
  1139. switch (ucontrol->value.integer.value[0]) {
  1140. case 1:
  1141. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_16KHZ;
  1142. break;
  1143. case 2:
  1144. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_44P1KHZ;
  1145. break;
  1146. case 3:
  1147. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_48KHZ;
  1148. break;
  1149. case 4:
  1150. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_88P2KHZ;
  1151. break;
  1152. case 5:
  1153. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_96KHZ;
  1154. break;
  1155. case 0:
  1156. default:
  1157. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_8KHZ;
  1158. break;
  1159. }
  1160. pr_debug("%s: sample rate = %d, value = %d\n",
  1161. __func__,
  1162. slim_tx_cfg[BT_SLIM_TX].sample_rate,
  1163. ucontrol->value.enumerated.item[0]);
  1164. return 0;
  1165. }
  1166. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1167. {
  1168. int idx = 0;
  1169. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1170. sizeof("WSA_CDC_DMA_RX_0")))
  1171. idx = WSA_CDC_DMA_RX_0;
  1172. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1173. sizeof("WSA_CDC_DMA_RX_0")))
  1174. idx = WSA_CDC_DMA_RX_1;
  1175. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1176. sizeof("WSA_CDC_DMA_TX_0")))
  1177. idx = WSA_CDC_DMA_TX_0;
  1178. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1179. sizeof("WSA_CDC_DMA_TX_1")))
  1180. idx = WSA_CDC_DMA_TX_1;
  1181. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1182. sizeof("WSA_CDC_DMA_TX_2")))
  1183. idx = WSA_CDC_DMA_TX_2;
  1184. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1185. sizeof("VA_CDC_DMA_TX_0")))
  1186. idx = VA_CDC_DMA_TX_0;
  1187. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1188. sizeof("VA_CDC_DMA_TX_1")))
  1189. idx = VA_CDC_DMA_TX_1;
  1190. else {
  1191. pr_err("%s: unsupported port: %s\n",
  1192. __func__, kcontrol->id.name);
  1193. return -EINVAL;
  1194. }
  1195. return idx;
  1196. }
  1197. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1198. struct snd_ctl_elem_value *ucontrol)
  1199. {
  1200. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1201. if (ch_num < 0)
  1202. return ch_num;
  1203. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1204. cdc_dma_rx_cfg[ch_num].channels - 1);
  1205. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1206. return 0;
  1207. }
  1208. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1209. struct snd_ctl_elem_value *ucontrol)
  1210. {
  1211. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1212. if (ch_num < 0)
  1213. return ch_num;
  1214. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1215. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1216. cdc_dma_rx_cfg[ch_num].channels);
  1217. return 1;
  1218. }
  1219. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1220. struct snd_ctl_elem_value *ucontrol)
  1221. {
  1222. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1223. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1224. case SNDRV_PCM_FORMAT_S32_LE:
  1225. ucontrol->value.integer.value[0] = 3;
  1226. break;
  1227. case SNDRV_PCM_FORMAT_S24_3LE:
  1228. ucontrol->value.integer.value[0] = 2;
  1229. break;
  1230. case SNDRV_PCM_FORMAT_S24_LE:
  1231. ucontrol->value.integer.value[0] = 1;
  1232. break;
  1233. case SNDRV_PCM_FORMAT_S16_LE:
  1234. default:
  1235. ucontrol->value.integer.value[0] = 0;
  1236. break;
  1237. }
  1238. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1239. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1240. ucontrol->value.integer.value[0]);
  1241. return 0;
  1242. }
  1243. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1244. struct snd_ctl_elem_value *ucontrol)
  1245. {
  1246. int rc = 0;
  1247. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1248. switch (ucontrol->value.integer.value[0]) {
  1249. case 3:
  1250. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1251. break;
  1252. case 2:
  1253. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1254. break;
  1255. case 1:
  1256. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1257. break;
  1258. case 0:
  1259. default:
  1260. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1261. break;
  1262. }
  1263. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1264. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1265. ucontrol->value.integer.value[0]);
  1266. return rc;
  1267. }
  1268. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1269. {
  1270. int sample_rate_val = 0;
  1271. switch (sample_rate) {
  1272. case SAMPLING_RATE_8KHZ:
  1273. sample_rate_val = 0;
  1274. break;
  1275. case SAMPLING_RATE_11P025KHZ:
  1276. sample_rate_val = 1;
  1277. break;
  1278. case SAMPLING_RATE_16KHZ:
  1279. sample_rate_val = 2;
  1280. break;
  1281. case SAMPLING_RATE_22P05KHZ:
  1282. sample_rate_val = 3;
  1283. break;
  1284. case SAMPLING_RATE_32KHZ:
  1285. sample_rate_val = 4;
  1286. break;
  1287. case SAMPLING_RATE_44P1KHZ:
  1288. sample_rate_val = 5;
  1289. break;
  1290. case SAMPLING_RATE_48KHZ:
  1291. sample_rate_val = 6;
  1292. break;
  1293. case SAMPLING_RATE_88P2KHZ:
  1294. sample_rate_val = 7;
  1295. break;
  1296. case SAMPLING_RATE_96KHZ:
  1297. sample_rate_val = 8;
  1298. break;
  1299. case SAMPLING_RATE_176P4KHZ:
  1300. sample_rate_val = 9;
  1301. break;
  1302. case SAMPLING_RATE_192KHZ:
  1303. sample_rate_val = 10;
  1304. break;
  1305. case SAMPLING_RATE_352P8KHZ:
  1306. sample_rate_val = 11;
  1307. break;
  1308. case SAMPLING_RATE_384KHZ:
  1309. sample_rate_val = 12;
  1310. break;
  1311. default:
  1312. sample_rate_val = 6;
  1313. break;
  1314. }
  1315. return sample_rate_val;
  1316. }
  1317. static int cdc_dma_get_sample_rate(int value)
  1318. {
  1319. int sample_rate = 0;
  1320. switch (value) {
  1321. case 0:
  1322. sample_rate = SAMPLING_RATE_8KHZ;
  1323. break;
  1324. case 1:
  1325. sample_rate = SAMPLING_RATE_11P025KHZ;
  1326. break;
  1327. case 2:
  1328. sample_rate = SAMPLING_RATE_16KHZ;
  1329. break;
  1330. case 3:
  1331. sample_rate = SAMPLING_RATE_22P05KHZ;
  1332. break;
  1333. case 4:
  1334. sample_rate = SAMPLING_RATE_32KHZ;
  1335. break;
  1336. case 5:
  1337. sample_rate = SAMPLING_RATE_44P1KHZ;
  1338. break;
  1339. case 6:
  1340. sample_rate = SAMPLING_RATE_48KHZ;
  1341. break;
  1342. case 7:
  1343. sample_rate = SAMPLING_RATE_88P2KHZ;
  1344. break;
  1345. case 8:
  1346. sample_rate = SAMPLING_RATE_96KHZ;
  1347. break;
  1348. case 9:
  1349. sample_rate = SAMPLING_RATE_176P4KHZ;
  1350. break;
  1351. case 10:
  1352. sample_rate = SAMPLING_RATE_192KHZ;
  1353. break;
  1354. case 11:
  1355. sample_rate = SAMPLING_RATE_352P8KHZ;
  1356. break;
  1357. case 12:
  1358. sample_rate = SAMPLING_RATE_384KHZ;
  1359. break;
  1360. default:
  1361. sample_rate = SAMPLING_RATE_48KHZ;
  1362. break;
  1363. }
  1364. return sample_rate;
  1365. }
  1366. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1367. struct snd_ctl_elem_value *ucontrol)
  1368. {
  1369. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1370. if (ch_num < 0)
  1371. return ch_num;
  1372. ucontrol->value.enumerated.item[0] =
  1373. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1374. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1375. cdc_dma_rx_cfg[ch_num].sample_rate);
  1376. return 0;
  1377. }
  1378. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1379. struct snd_ctl_elem_value *ucontrol)
  1380. {
  1381. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1382. if (ch_num < 0)
  1383. return ch_num;
  1384. cdc_dma_rx_cfg[ch_num].sample_rate =
  1385. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1386. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1387. __func__, ucontrol->value.enumerated.item[0],
  1388. cdc_dma_rx_cfg[ch_num].sample_rate);
  1389. return 0;
  1390. }
  1391. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1392. struct snd_ctl_elem_value *ucontrol)
  1393. {
  1394. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1395. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1396. cdc_dma_tx_cfg[ch_num].channels);
  1397. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1398. return 0;
  1399. }
  1400. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1401. struct snd_ctl_elem_value *ucontrol)
  1402. {
  1403. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1404. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1405. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1406. cdc_dma_tx_cfg[ch_num].channels);
  1407. return 1;
  1408. }
  1409. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1410. struct snd_ctl_elem_value *ucontrol)
  1411. {
  1412. int sample_rate_val;
  1413. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1414. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1415. case SAMPLING_RATE_384KHZ:
  1416. sample_rate_val = 12;
  1417. break;
  1418. case SAMPLING_RATE_352P8KHZ:
  1419. sample_rate_val = 11;
  1420. break;
  1421. case SAMPLING_RATE_192KHZ:
  1422. sample_rate_val = 10;
  1423. break;
  1424. case SAMPLING_RATE_176P4KHZ:
  1425. sample_rate_val = 9;
  1426. break;
  1427. case SAMPLING_RATE_96KHZ:
  1428. sample_rate_val = 8;
  1429. break;
  1430. case SAMPLING_RATE_88P2KHZ:
  1431. sample_rate_val = 7;
  1432. break;
  1433. case SAMPLING_RATE_48KHZ:
  1434. sample_rate_val = 6;
  1435. break;
  1436. case SAMPLING_RATE_44P1KHZ:
  1437. sample_rate_val = 5;
  1438. break;
  1439. case SAMPLING_RATE_32KHZ:
  1440. sample_rate_val = 4;
  1441. break;
  1442. case SAMPLING_RATE_22P05KHZ:
  1443. sample_rate_val = 3;
  1444. break;
  1445. case SAMPLING_RATE_16KHZ:
  1446. sample_rate_val = 2;
  1447. break;
  1448. case SAMPLING_RATE_11P025KHZ:
  1449. sample_rate_val = 1;
  1450. break;
  1451. case SAMPLING_RATE_8KHZ:
  1452. sample_rate_val = 0;
  1453. break;
  1454. default:
  1455. sample_rate_val = 6;
  1456. break;
  1457. }
  1458. ucontrol->value.integer.value[0] = sample_rate_val;
  1459. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1460. cdc_dma_tx_cfg[ch_num].sample_rate);
  1461. return 0;
  1462. }
  1463. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1464. struct snd_ctl_elem_value *ucontrol)
  1465. {
  1466. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1467. switch (ucontrol->value.integer.value[0]) {
  1468. case 12:
  1469. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1470. break;
  1471. case 11:
  1472. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1473. break;
  1474. case 10:
  1475. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1476. break;
  1477. case 9:
  1478. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1479. break;
  1480. case 8:
  1481. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1482. break;
  1483. case 7:
  1484. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1485. break;
  1486. case 6:
  1487. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1488. break;
  1489. case 5:
  1490. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1491. break;
  1492. case 4:
  1493. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1494. break;
  1495. case 3:
  1496. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1497. break;
  1498. case 2:
  1499. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1500. break;
  1501. case 1:
  1502. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1503. break;
  1504. case 0:
  1505. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1506. break;
  1507. default:
  1508. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1509. break;
  1510. }
  1511. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1512. __func__, ucontrol->value.integer.value[0],
  1513. cdc_dma_tx_cfg[ch_num].sample_rate);
  1514. return 0;
  1515. }
  1516. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1517. struct snd_ctl_elem_value *ucontrol)
  1518. {
  1519. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1520. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1521. case SNDRV_PCM_FORMAT_S32_LE:
  1522. ucontrol->value.integer.value[0] = 3;
  1523. break;
  1524. case SNDRV_PCM_FORMAT_S24_3LE:
  1525. ucontrol->value.integer.value[0] = 2;
  1526. break;
  1527. case SNDRV_PCM_FORMAT_S24_LE:
  1528. ucontrol->value.integer.value[0] = 1;
  1529. break;
  1530. case SNDRV_PCM_FORMAT_S16_LE:
  1531. default:
  1532. ucontrol->value.integer.value[0] = 0;
  1533. break;
  1534. }
  1535. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1536. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1537. ucontrol->value.integer.value[0]);
  1538. return 0;
  1539. }
  1540. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1541. struct snd_ctl_elem_value *ucontrol)
  1542. {
  1543. int rc = 0;
  1544. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1545. switch (ucontrol->value.integer.value[0]) {
  1546. case 3:
  1547. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1548. break;
  1549. case 2:
  1550. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1551. break;
  1552. case 1:
  1553. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1554. break;
  1555. case 0:
  1556. default:
  1557. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1558. break;
  1559. }
  1560. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1561. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1562. ucontrol->value.integer.value[0]);
  1563. return rc;
  1564. }
  1565. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1566. struct snd_ctl_elem_value *ucontrol)
  1567. {
  1568. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1569. usb_rx_cfg.channels);
  1570. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1571. return 0;
  1572. }
  1573. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1574. struct snd_ctl_elem_value *ucontrol)
  1575. {
  1576. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1577. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1578. return 1;
  1579. }
  1580. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1581. struct snd_ctl_elem_value *ucontrol)
  1582. {
  1583. int sample_rate_val;
  1584. switch (usb_rx_cfg.sample_rate) {
  1585. case SAMPLING_RATE_384KHZ:
  1586. sample_rate_val = 12;
  1587. break;
  1588. case SAMPLING_RATE_352P8KHZ:
  1589. sample_rate_val = 11;
  1590. break;
  1591. case SAMPLING_RATE_192KHZ:
  1592. sample_rate_val = 10;
  1593. break;
  1594. case SAMPLING_RATE_176P4KHZ:
  1595. sample_rate_val = 9;
  1596. break;
  1597. case SAMPLING_RATE_96KHZ:
  1598. sample_rate_val = 8;
  1599. break;
  1600. case SAMPLING_RATE_88P2KHZ:
  1601. sample_rate_val = 7;
  1602. break;
  1603. case SAMPLING_RATE_48KHZ:
  1604. sample_rate_val = 6;
  1605. break;
  1606. case SAMPLING_RATE_44P1KHZ:
  1607. sample_rate_val = 5;
  1608. break;
  1609. case SAMPLING_RATE_32KHZ:
  1610. sample_rate_val = 4;
  1611. break;
  1612. case SAMPLING_RATE_22P05KHZ:
  1613. sample_rate_val = 3;
  1614. break;
  1615. case SAMPLING_RATE_16KHZ:
  1616. sample_rate_val = 2;
  1617. break;
  1618. case SAMPLING_RATE_11P025KHZ:
  1619. sample_rate_val = 1;
  1620. break;
  1621. case SAMPLING_RATE_8KHZ:
  1622. default:
  1623. sample_rate_val = 0;
  1624. break;
  1625. }
  1626. ucontrol->value.integer.value[0] = sample_rate_val;
  1627. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1628. usb_rx_cfg.sample_rate);
  1629. return 0;
  1630. }
  1631. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1632. struct snd_ctl_elem_value *ucontrol)
  1633. {
  1634. switch (ucontrol->value.integer.value[0]) {
  1635. case 12:
  1636. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1637. break;
  1638. case 11:
  1639. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1640. break;
  1641. case 10:
  1642. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1643. break;
  1644. case 9:
  1645. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1646. break;
  1647. case 8:
  1648. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1649. break;
  1650. case 7:
  1651. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1652. break;
  1653. case 6:
  1654. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1655. break;
  1656. case 5:
  1657. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1658. break;
  1659. case 4:
  1660. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1661. break;
  1662. case 3:
  1663. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1664. break;
  1665. case 2:
  1666. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1667. break;
  1668. case 1:
  1669. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1670. break;
  1671. case 0:
  1672. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1673. break;
  1674. default:
  1675. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1676. break;
  1677. }
  1678. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1679. __func__, ucontrol->value.integer.value[0],
  1680. usb_rx_cfg.sample_rate);
  1681. return 0;
  1682. }
  1683. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1684. struct snd_ctl_elem_value *ucontrol)
  1685. {
  1686. switch (usb_rx_cfg.bit_format) {
  1687. case SNDRV_PCM_FORMAT_S32_LE:
  1688. ucontrol->value.integer.value[0] = 3;
  1689. break;
  1690. case SNDRV_PCM_FORMAT_S24_3LE:
  1691. ucontrol->value.integer.value[0] = 2;
  1692. break;
  1693. case SNDRV_PCM_FORMAT_S24_LE:
  1694. ucontrol->value.integer.value[0] = 1;
  1695. break;
  1696. case SNDRV_PCM_FORMAT_S16_LE:
  1697. default:
  1698. ucontrol->value.integer.value[0] = 0;
  1699. break;
  1700. }
  1701. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1702. __func__, usb_rx_cfg.bit_format,
  1703. ucontrol->value.integer.value[0]);
  1704. return 0;
  1705. }
  1706. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1707. struct snd_ctl_elem_value *ucontrol)
  1708. {
  1709. int rc = 0;
  1710. switch (ucontrol->value.integer.value[0]) {
  1711. case 3:
  1712. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1713. break;
  1714. case 2:
  1715. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1716. break;
  1717. case 1:
  1718. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1719. break;
  1720. case 0:
  1721. default:
  1722. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1723. break;
  1724. }
  1725. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1726. __func__, usb_rx_cfg.bit_format,
  1727. ucontrol->value.integer.value[0]);
  1728. return rc;
  1729. }
  1730. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1731. struct snd_ctl_elem_value *ucontrol)
  1732. {
  1733. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1734. usb_tx_cfg.channels);
  1735. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1736. return 0;
  1737. }
  1738. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1739. struct snd_ctl_elem_value *ucontrol)
  1740. {
  1741. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1742. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1743. return 1;
  1744. }
  1745. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1746. struct snd_ctl_elem_value *ucontrol)
  1747. {
  1748. int sample_rate_val;
  1749. switch (usb_tx_cfg.sample_rate) {
  1750. case SAMPLING_RATE_384KHZ:
  1751. sample_rate_val = 12;
  1752. break;
  1753. case SAMPLING_RATE_352P8KHZ:
  1754. sample_rate_val = 11;
  1755. break;
  1756. case SAMPLING_RATE_192KHZ:
  1757. sample_rate_val = 10;
  1758. break;
  1759. case SAMPLING_RATE_176P4KHZ:
  1760. sample_rate_val = 9;
  1761. break;
  1762. case SAMPLING_RATE_96KHZ:
  1763. sample_rate_val = 8;
  1764. break;
  1765. case SAMPLING_RATE_88P2KHZ:
  1766. sample_rate_val = 7;
  1767. break;
  1768. case SAMPLING_RATE_48KHZ:
  1769. sample_rate_val = 6;
  1770. break;
  1771. case SAMPLING_RATE_44P1KHZ:
  1772. sample_rate_val = 5;
  1773. break;
  1774. case SAMPLING_RATE_32KHZ:
  1775. sample_rate_val = 4;
  1776. break;
  1777. case SAMPLING_RATE_22P05KHZ:
  1778. sample_rate_val = 3;
  1779. break;
  1780. case SAMPLING_RATE_16KHZ:
  1781. sample_rate_val = 2;
  1782. break;
  1783. case SAMPLING_RATE_11P025KHZ:
  1784. sample_rate_val = 1;
  1785. break;
  1786. case SAMPLING_RATE_8KHZ:
  1787. sample_rate_val = 0;
  1788. break;
  1789. default:
  1790. sample_rate_val = 6;
  1791. break;
  1792. }
  1793. ucontrol->value.integer.value[0] = sample_rate_val;
  1794. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1795. usb_tx_cfg.sample_rate);
  1796. return 0;
  1797. }
  1798. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1799. struct snd_ctl_elem_value *ucontrol)
  1800. {
  1801. switch (ucontrol->value.integer.value[0]) {
  1802. case 12:
  1803. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1804. break;
  1805. case 11:
  1806. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1807. break;
  1808. case 10:
  1809. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1810. break;
  1811. case 9:
  1812. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1813. break;
  1814. case 8:
  1815. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1816. break;
  1817. case 7:
  1818. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1819. break;
  1820. case 6:
  1821. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1822. break;
  1823. case 5:
  1824. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1825. break;
  1826. case 4:
  1827. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1828. break;
  1829. case 3:
  1830. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1831. break;
  1832. case 2:
  1833. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1834. break;
  1835. case 1:
  1836. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1837. break;
  1838. case 0:
  1839. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1840. break;
  1841. default:
  1842. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1843. break;
  1844. }
  1845. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1846. __func__, ucontrol->value.integer.value[0],
  1847. usb_tx_cfg.sample_rate);
  1848. return 0;
  1849. }
  1850. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1851. struct snd_ctl_elem_value *ucontrol)
  1852. {
  1853. switch (usb_tx_cfg.bit_format) {
  1854. case SNDRV_PCM_FORMAT_S32_LE:
  1855. ucontrol->value.integer.value[0] = 3;
  1856. break;
  1857. case SNDRV_PCM_FORMAT_S24_3LE:
  1858. ucontrol->value.integer.value[0] = 2;
  1859. break;
  1860. case SNDRV_PCM_FORMAT_S24_LE:
  1861. ucontrol->value.integer.value[0] = 1;
  1862. break;
  1863. case SNDRV_PCM_FORMAT_S16_LE:
  1864. default:
  1865. ucontrol->value.integer.value[0] = 0;
  1866. break;
  1867. }
  1868. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1869. __func__, usb_tx_cfg.bit_format,
  1870. ucontrol->value.integer.value[0]);
  1871. return 0;
  1872. }
  1873. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1874. struct snd_ctl_elem_value *ucontrol)
  1875. {
  1876. int rc = 0;
  1877. switch (ucontrol->value.integer.value[0]) {
  1878. case 3:
  1879. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1880. break;
  1881. case 2:
  1882. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1883. break;
  1884. case 1:
  1885. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1886. break;
  1887. case 0:
  1888. default:
  1889. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1890. break;
  1891. }
  1892. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1893. __func__, usb_tx_cfg.bit_format,
  1894. ucontrol->value.integer.value[0]);
  1895. return rc;
  1896. }
  1897. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1898. struct snd_ctl_elem_value *ucontrol)
  1899. {
  1900. pr_debug("%s: proxy_rx channels = %d\n",
  1901. __func__, proxy_rx_cfg.channels);
  1902. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1903. return 0;
  1904. }
  1905. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1906. struct snd_ctl_elem_value *ucontrol)
  1907. {
  1908. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1909. pr_debug("%s: proxy_rx channels = %d\n",
  1910. __func__, proxy_rx_cfg.channels);
  1911. return 1;
  1912. }
  1913. static int tdm_get_sample_rate(int value)
  1914. {
  1915. int sample_rate = 0;
  1916. switch (value) {
  1917. case 0:
  1918. sample_rate = SAMPLING_RATE_8KHZ;
  1919. break;
  1920. case 1:
  1921. sample_rate = SAMPLING_RATE_16KHZ;
  1922. break;
  1923. case 2:
  1924. sample_rate = SAMPLING_RATE_32KHZ;
  1925. break;
  1926. case 3:
  1927. sample_rate = SAMPLING_RATE_48KHZ;
  1928. break;
  1929. case 4:
  1930. sample_rate = SAMPLING_RATE_176P4KHZ;
  1931. break;
  1932. case 5:
  1933. sample_rate = SAMPLING_RATE_352P8KHZ;
  1934. break;
  1935. default:
  1936. sample_rate = SAMPLING_RATE_48KHZ;
  1937. break;
  1938. }
  1939. return sample_rate;
  1940. }
  1941. static int aux_pcm_get_sample_rate(int value)
  1942. {
  1943. int sample_rate;
  1944. switch (value) {
  1945. case 1:
  1946. sample_rate = SAMPLING_RATE_16KHZ;
  1947. break;
  1948. case 0:
  1949. default:
  1950. sample_rate = SAMPLING_RATE_8KHZ;
  1951. break;
  1952. }
  1953. return sample_rate;
  1954. }
  1955. static int tdm_get_sample_rate_val(int sample_rate)
  1956. {
  1957. int sample_rate_val = 0;
  1958. switch (sample_rate) {
  1959. case SAMPLING_RATE_8KHZ:
  1960. sample_rate_val = 0;
  1961. break;
  1962. case SAMPLING_RATE_16KHZ:
  1963. sample_rate_val = 1;
  1964. break;
  1965. case SAMPLING_RATE_32KHZ:
  1966. sample_rate_val = 2;
  1967. break;
  1968. case SAMPLING_RATE_48KHZ:
  1969. sample_rate_val = 3;
  1970. break;
  1971. case SAMPLING_RATE_176P4KHZ:
  1972. sample_rate_val = 4;
  1973. break;
  1974. case SAMPLING_RATE_352P8KHZ:
  1975. sample_rate_val = 5;
  1976. break;
  1977. default:
  1978. sample_rate_val = 3;
  1979. break;
  1980. }
  1981. return sample_rate_val;
  1982. }
  1983. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1984. {
  1985. int sample_rate_val;
  1986. switch (sample_rate) {
  1987. case SAMPLING_RATE_16KHZ:
  1988. sample_rate_val = 1;
  1989. break;
  1990. case SAMPLING_RATE_8KHZ:
  1991. default:
  1992. sample_rate_val = 0;
  1993. break;
  1994. }
  1995. return sample_rate_val;
  1996. }
  1997. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1998. struct tdm_port *port)
  1999. {
  2000. if (port) {
  2001. if (strnstr(kcontrol->id.name, "PRI",
  2002. sizeof(kcontrol->id.name))) {
  2003. port->mode = TDM_PRI;
  2004. } else if (strnstr(kcontrol->id.name, "SEC",
  2005. sizeof(kcontrol->id.name))) {
  2006. port->mode = TDM_SEC;
  2007. } else if (strnstr(kcontrol->id.name, "TERT",
  2008. sizeof(kcontrol->id.name))) {
  2009. port->mode = TDM_TERT;
  2010. } else if (strnstr(kcontrol->id.name, "QUAT",
  2011. sizeof(kcontrol->id.name))) {
  2012. port->mode = TDM_QUAT;
  2013. } else if (strnstr(kcontrol->id.name, "QUIN",
  2014. sizeof(kcontrol->id.name))) {
  2015. port->mode = TDM_QUIN;
  2016. } else {
  2017. pr_err("%s: unsupported mode in: %s",
  2018. __func__, kcontrol->id.name);
  2019. return -EINVAL;
  2020. }
  2021. if (strnstr(kcontrol->id.name, "RX_0",
  2022. sizeof(kcontrol->id.name)) ||
  2023. strnstr(kcontrol->id.name, "TX_0",
  2024. sizeof(kcontrol->id.name))) {
  2025. port->channel = TDM_0;
  2026. } else if (strnstr(kcontrol->id.name, "RX_1",
  2027. sizeof(kcontrol->id.name)) ||
  2028. strnstr(kcontrol->id.name, "TX_1",
  2029. sizeof(kcontrol->id.name))) {
  2030. port->channel = TDM_1;
  2031. } else if (strnstr(kcontrol->id.name, "RX_2",
  2032. sizeof(kcontrol->id.name)) ||
  2033. strnstr(kcontrol->id.name, "TX_2",
  2034. sizeof(kcontrol->id.name))) {
  2035. port->channel = TDM_2;
  2036. } else if (strnstr(kcontrol->id.name, "RX_3",
  2037. sizeof(kcontrol->id.name)) ||
  2038. strnstr(kcontrol->id.name, "TX_3",
  2039. sizeof(kcontrol->id.name))) {
  2040. port->channel = TDM_3;
  2041. } else if (strnstr(kcontrol->id.name, "RX_4",
  2042. sizeof(kcontrol->id.name)) ||
  2043. strnstr(kcontrol->id.name, "TX_4",
  2044. sizeof(kcontrol->id.name))) {
  2045. port->channel = TDM_4;
  2046. } else if (strnstr(kcontrol->id.name, "RX_5",
  2047. sizeof(kcontrol->id.name)) ||
  2048. strnstr(kcontrol->id.name, "TX_5",
  2049. sizeof(kcontrol->id.name))) {
  2050. port->channel = TDM_5;
  2051. } else if (strnstr(kcontrol->id.name, "RX_6",
  2052. sizeof(kcontrol->id.name)) ||
  2053. strnstr(kcontrol->id.name, "TX_6",
  2054. sizeof(kcontrol->id.name))) {
  2055. port->channel = TDM_6;
  2056. } else if (strnstr(kcontrol->id.name, "RX_7",
  2057. sizeof(kcontrol->id.name)) ||
  2058. strnstr(kcontrol->id.name, "TX_7",
  2059. sizeof(kcontrol->id.name))) {
  2060. port->channel = TDM_7;
  2061. } else {
  2062. pr_err("%s: unsupported channel in: %s",
  2063. __func__, kcontrol->id.name);
  2064. return -EINVAL;
  2065. }
  2066. } else
  2067. return -EINVAL;
  2068. return 0;
  2069. }
  2070. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2071. struct snd_ctl_elem_value *ucontrol)
  2072. {
  2073. struct tdm_port port;
  2074. int ret = tdm_get_port_idx(kcontrol, &port);
  2075. if (ret) {
  2076. pr_err("%s: unsupported control: %s",
  2077. __func__, kcontrol->id.name);
  2078. } else {
  2079. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2080. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  2081. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2082. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2083. ucontrol->value.enumerated.item[0]);
  2084. }
  2085. return ret;
  2086. }
  2087. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2088. struct snd_ctl_elem_value *ucontrol)
  2089. {
  2090. struct tdm_port port;
  2091. int ret = tdm_get_port_idx(kcontrol, &port);
  2092. if (ret) {
  2093. pr_err("%s: unsupported control: %s",
  2094. __func__, kcontrol->id.name);
  2095. } else {
  2096. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  2097. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2098. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2099. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2100. ucontrol->value.enumerated.item[0]);
  2101. }
  2102. return ret;
  2103. }
  2104. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2105. struct snd_ctl_elem_value *ucontrol)
  2106. {
  2107. struct tdm_port port;
  2108. int ret = tdm_get_port_idx(kcontrol, &port);
  2109. if (ret) {
  2110. pr_err("%s: unsupported control: %s",
  2111. __func__, kcontrol->id.name);
  2112. } else {
  2113. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2114. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  2115. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2116. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2117. ucontrol->value.enumerated.item[0]);
  2118. }
  2119. return ret;
  2120. }
  2121. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2122. struct snd_ctl_elem_value *ucontrol)
  2123. {
  2124. struct tdm_port port;
  2125. int ret = tdm_get_port_idx(kcontrol, &port);
  2126. if (ret) {
  2127. pr_err("%s: unsupported control: %s",
  2128. __func__, kcontrol->id.name);
  2129. } else {
  2130. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  2131. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2132. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2133. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2134. ucontrol->value.enumerated.item[0]);
  2135. }
  2136. return ret;
  2137. }
  2138. static int tdm_get_format(int value)
  2139. {
  2140. int format = 0;
  2141. switch (value) {
  2142. case 0:
  2143. format = SNDRV_PCM_FORMAT_S16_LE;
  2144. break;
  2145. case 1:
  2146. format = SNDRV_PCM_FORMAT_S24_LE;
  2147. break;
  2148. case 2:
  2149. format = SNDRV_PCM_FORMAT_S32_LE;
  2150. break;
  2151. default:
  2152. format = SNDRV_PCM_FORMAT_S16_LE;
  2153. break;
  2154. }
  2155. return format;
  2156. }
  2157. static int tdm_get_format_val(int format)
  2158. {
  2159. int value = 0;
  2160. switch (format) {
  2161. case SNDRV_PCM_FORMAT_S16_LE:
  2162. value = 0;
  2163. break;
  2164. case SNDRV_PCM_FORMAT_S24_LE:
  2165. value = 1;
  2166. break;
  2167. case SNDRV_PCM_FORMAT_S32_LE:
  2168. value = 2;
  2169. break;
  2170. default:
  2171. value = 0;
  2172. break;
  2173. }
  2174. return value;
  2175. }
  2176. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2177. struct snd_ctl_elem_value *ucontrol)
  2178. {
  2179. struct tdm_port port;
  2180. int ret = tdm_get_port_idx(kcontrol, &port);
  2181. if (ret) {
  2182. pr_err("%s: unsupported control: %s",
  2183. __func__, kcontrol->id.name);
  2184. } else {
  2185. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2186. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2187. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2188. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2189. ucontrol->value.enumerated.item[0]);
  2190. }
  2191. return ret;
  2192. }
  2193. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2194. struct snd_ctl_elem_value *ucontrol)
  2195. {
  2196. struct tdm_port port;
  2197. int ret = tdm_get_port_idx(kcontrol, &port);
  2198. if (ret) {
  2199. pr_err("%s: unsupported control: %s",
  2200. __func__, kcontrol->id.name);
  2201. } else {
  2202. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2203. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2204. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2205. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2206. ucontrol->value.enumerated.item[0]);
  2207. }
  2208. return ret;
  2209. }
  2210. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2211. struct snd_ctl_elem_value *ucontrol)
  2212. {
  2213. struct tdm_port port;
  2214. int ret = tdm_get_port_idx(kcontrol, &port);
  2215. if (ret) {
  2216. pr_err("%s: unsupported control: %s",
  2217. __func__, kcontrol->id.name);
  2218. } else {
  2219. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2220. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2221. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2222. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2223. ucontrol->value.enumerated.item[0]);
  2224. }
  2225. return ret;
  2226. }
  2227. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2228. struct snd_ctl_elem_value *ucontrol)
  2229. {
  2230. struct tdm_port port;
  2231. int ret = tdm_get_port_idx(kcontrol, &port);
  2232. if (ret) {
  2233. pr_err("%s: unsupported control: %s",
  2234. __func__, kcontrol->id.name);
  2235. } else {
  2236. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2237. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2238. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2239. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2240. ucontrol->value.enumerated.item[0]);
  2241. }
  2242. return ret;
  2243. }
  2244. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2245. struct snd_ctl_elem_value *ucontrol)
  2246. {
  2247. struct tdm_port port;
  2248. int ret = tdm_get_port_idx(kcontrol, &port);
  2249. if (ret) {
  2250. pr_err("%s: unsupported control: %s",
  2251. __func__, kcontrol->id.name);
  2252. } else {
  2253. ucontrol->value.enumerated.item[0] =
  2254. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2255. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2256. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2257. ucontrol->value.enumerated.item[0]);
  2258. }
  2259. return ret;
  2260. }
  2261. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2262. struct snd_ctl_elem_value *ucontrol)
  2263. {
  2264. struct tdm_port port;
  2265. int ret = tdm_get_port_idx(kcontrol, &port);
  2266. if (ret) {
  2267. pr_err("%s: unsupported control: %s",
  2268. __func__, kcontrol->id.name);
  2269. } else {
  2270. tdm_rx_cfg[port.mode][port.channel].channels =
  2271. ucontrol->value.enumerated.item[0] + 1;
  2272. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2273. tdm_rx_cfg[port.mode][port.channel].channels,
  2274. ucontrol->value.enumerated.item[0] + 1);
  2275. }
  2276. return ret;
  2277. }
  2278. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2279. struct snd_ctl_elem_value *ucontrol)
  2280. {
  2281. struct tdm_port port;
  2282. int ret = tdm_get_port_idx(kcontrol, &port);
  2283. if (ret) {
  2284. pr_err("%s: unsupported control: %s",
  2285. __func__, kcontrol->id.name);
  2286. } else {
  2287. ucontrol->value.enumerated.item[0] =
  2288. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2289. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2290. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2291. ucontrol->value.enumerated.item[0]);
  2292. }
  2293. return ret;
  2294. }
  2295. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2296. struct snd_ctl_elem_value *ucontrol)
  2297. {
  2298. struct tdm_port port;
  2299. int ret = tdm_get_port_idx(kcontrol, &port);
  2300. if (ret) {
  2301. pr_err("%s: unsupported control: %s",
  2302. __func__, kcontrol->id.name);
  2303. } else {
  2304. tdm_tx_cfg[port.mode][port.channel].channels =
  2305. ucontrol->value.enumerated.item[0] + 1;
  2306. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2307. tdm_tx_cfg[port.mode][port.channel].channels,
  2308. ucontrol->value.enumerated.item[0] + 1);
  2309. }
  2310. return ret;
  2311. }
  2312. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2313. {
  2314. int idx;
  2315. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2316. sizeof("PRIM_AUX_PCM")))
  2317. idx = PRIM_AUX_PCM;
  2318. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2319. sizeof("SEC_AUX_PCM")))
  2320. idx = SEC_AUX_PCM;
  2321. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2322. sizeof("TERT_AUX_PCM")))
  2323. idx = TERT_AUX_PCM;
  2324. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2325. sizeof("QUAT_AUX_PCM")))
  2326. idx = QUAT_AUX_PCM;
  2327. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2328. sizeof("QUIN_AUX_PCM")))
  2329. idx = QUIN_AUX_PCM;
  2330. else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  2331. sizeof("SENN_AUX_PCM")))
  2332. idx = SEN_AUX_PCM;
  2333. else {
  2334. pr_err("%s: unsupported port: %s",
  2335. __func__, kcontrol->id.name);
  2336. idx = -EINVAL;
  2337. }
  2338. return idx;
  2339. }
  2340. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2341. struct snd_ctl_elem_value *ucontrol)
  2342. {
  2343. int idx = aux_pcm_get_port_idx(kcontrol);
  2344. if (idx < 0)
  2345. return idx;
  2346. aux_pcm_rx_cfg[idx].sample_rate =
  2347. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2348. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2349. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2350. ucontrol->value.enumerated.item[0]);
  2351. return 0;
  2352. }
  2353. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2354. struct snd_ctl_elem_value *ucontrol)
  2355. {
  2356. int idx = aux_pcm_get_port_idx(kcontrol);
  2357. if (idx < 0)
  2358. return idx;
  2359. ucontrol->value.enumerated.item[0] =
  2360. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2361. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2362. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2363. ucontrol->value.enumerated.item[0]);
  2364. return 0;
  2365. }
  2366. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2367. struct snd_ctl_elem_value *ucontrol)
  2368. {
  2369. int idx = aux_pcm_get_port_idx(kcontrol);
  2370. if (idx < 0)
  2371. return idx;
  2372. aux_pcm_tx_cfg[idx].sample_rate =
  2373. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2374. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2375. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2376. ucontrol->value.enumerated.item[0]);
  2377. return 0;
  2378. }
  2379. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2380. struct snd_ctl_elem_value *ucontrol)
  2381. {
  2382. int idx = aux_pcm_get_port_idx(kcontrol);
  2383. if (idx < 0)
  2384. return idx;
  2385. ucontrol->value.enumerated.item[0] =
  2386. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2387. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2388. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2389. ucontrol->value.enumerated.item[0]);
  2390. return 0;
  2391. }
  2392. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2393. {
  2394. int idx;
  2395. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2396. sizeof("PRIM_MI2S_RX")))
  2397. idx = PRIM_MI2S;
  2398. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2399. sizeof("SEC_MI2S_RX")))
  2400. idx = SEC_MI2S;
  2401. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2402. sizeof("TERT_MI2S_RX")))
  2403. idx = TERT_MI2S;
  2404. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2405. sizeof("QUAT_MI2S_RX")))
  2406. idx = QUAT_MI2S;
  2407. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2408. sizeof("QUIN_MI2S_RX")))
  2409. idx = QUIN_MI2S;
  2410. else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2411. sizeof("SEN_MI2S_RX")))
  2412. idx = SEN_MI2S;
  2413. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2414. sizeof("PRIM_MI2S_TX")))
  2415. idx = PRIM_MI2S;
  2416. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2417. sizeof("SEC_MI2S_TX")))
  2418. idx = SEC_MI2S;
  2419. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2420. sizeof("TERT_MI2S_TX")))
  2421. idx = TERT_MI2S;
  2422. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2423. sizeof("QUAT_MI2S_TX")))
  2424. idx = QUAT_MI2S;
  2425. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2426. sizeof("QUIN_MI2S_TX")))
  2427. idx = QUIN_MI2S;
  2428. else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2429. sizeof("SEN_MI2S_TX")))
  2430. idx = SEN_MI2S;
  2431. else {
  2432. pr_err("%s: unsupported channel: %s",
  2433. __func__, kcontrol->id.name);
  2434. idx = -EINVAL;
  2435. }
  2436. return idx;
  2437. }
  2438. static int mi2s_get_sample_rate_val(int sample_rate)
  2439. {
  2440. int sample_rate_val;
  2441. switch (sample_rate) {
  2442. case SAMPLING_RATE_8KHZ:
  2443. sample_rate_val = 0;
  2444. break;
  2445. case SAMPLING_RATE_11P025KHZ:
  2446. sample_rate_val = 1;
  2447. break;
  2448. case SAMPLING_RATE_16KHZ:
  2449. sample_rate_val = 2;
  2450. break;
  2451. case SAMPLING_RATE_22P05KHZ:
  2452. sample_rate_val = 3;
  2453. break;
  2454. case SAMPLING_RATE_32KHZ:
  2455. sample_rate_val = 4;
  2456. break;
  2457. case SAMPLING_RATE_44P1KHZ:
  2458. sample_rate_val = 5;
  2459. break;
  2460. case SAMPLING_RATE_48KHZ:
  2461. sample_rate_val = 6;
  2462. break;
  2463. case SAMPLING_RATE_88P2KHZ:
  2464. sample_rate_val = 7;
  2465. break;
  2466. case SAMPLING_RATE_96KHZ:
  2467. sample_rate_val = 8;
  2468. break;
  2469. case SAMPLING_RATE_176P4KHZ:
  2470. sample_rate_val = 9;
  2471. break;
  2472. case SAMPLING_RATE_192KHZ:
  2473. sample_rate_val = 10;
  2474. break;
  2475. case SAMPLING_RATE_352P8KHZ:
  2476. sample_rate_val = 11;
  2477. break;
  2478. case SAMPLING_RATE_384KHZ:
  2479. sample_rate_val = 12;
  2480. break;
  2481. default:
  2482. sample_rate_val = 6;
  2483. break;
  2484. }
  2485. return sample_rate_val;
  2486. }
  2487. static int mi2s_get_sample_rate(int value)
  2488. {
  2489. int sample_rate;
  2490. switch (value) {
  2491. case 0:
  2492. sample_rate = SAMPLING_RATE_8KHZ;
  2493. break;
  2494. case 1:
  2495. sample_rate = SAMPLING_RATE_11P025KHZ;
  2496. break;
  2497. case 2:
  2498. sample_rate = SAMPLING_RATE_16KHZ;
  2499. break;
  2500. case 3:
  2501. sample_rate = SAMPLING_RATE_22P05KHZ;
  2502. break;
  2503. case 4:
  2504. sample_rate = SAMPLING_RATE_32KHZ;
  2505. break;
  2506. case 5:
  2507. sample_rate = SAMPLING_RATE_44P1KHZ;
  2508. break;
  2509. case 6:
  2510. sample_rate = SAMPLING_RATE_48KHZ;
  2511. break;
  2512. case 7:
  2513. sample_rate = SAMPLING_RATE_88P2KHZ;
  2514. break;
  2515. case 8:
  2516. sample_rate = SAMPLING_RATE_96KHZ;
  2517. break;
  2518. case 9:
  2519. sample_rate = SAMPLING_RATE_176P4KHZ;
  2520. break;
  2521. case 10:
  2522. sample_rate = SAMPLING_RATE_192KHZ;
  2523. break;
  2524. case 11:
  2525. sample_rate = SAMPLING_RATE_352P8KHZ;
  2526. break;
  2527. case 12:
  2528. sample_rate = SAMPLING_RATE_384KHZ;
  2529. break;
  2530. default:
  2531. sample_rate = SAMPLING_RATE_48KHZ;
  2532. break;
  2533. }
  2534. return sample_rate;
  2535. }
  2536. static int mi2s_auxpcm_get_format(int value)
  2537. {
  2538. int format;
  2539. switch (value) {
  2540. case 0:
  2541. format = SNDRV_PCM_FORMAT_S16_LE;
  2542. break;
  2543. case 1:
  2544. format = SNDRV_PCM_FORMAT_S24_LE;
  2545. break;
  2546. case 2:
  2547. format = SNDRV_PCM_FORMAT_S24_3LE;
  2548. break;
  2549. case 3:
  2550. format = SNDRV_PCM_FORMAT_S32_LE;
  2551. break;
  2552. default:
  2553. format = SNDRV_PCM_FORMAT_S16_LE;
  2554. break;
  2555. }
  2556. return format;
  2557. }
  2558. static int mi2s_auxpcm_get_format_value(int format)
  2559. {
  2560. int value;
  2561. switch (format) {
  2562. case SNDRV_PCM_FORMAT_S16_LE:
  2563. value = 0;
  2564. break;
  2565. case SNDRV_PCM_FORMAT_S24_LE:
  2566. value = 1;
  2567. break;
  2568. case SNDRV_PCM_FORMAT_S24_3LE:
  2569. value = 2;
  2570. break;
  2571. case SNDRV_PCM_FORMAT_S32_LE:
  2572. value = 3;
  2573. break;
  2574. default:
  2575. value = 0;
  2576. break;
  2577. }
  2578. return value;
  2579. }
  2580. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2581. struct snd_ctl_elem_value *ucontrol)
  2582. {
  2583. int idx = mi2s_get_port_idx(kcontrol);
  2584. if (idx < 0)
  2585. return idx;
  2586. mi2s_rx_cfg[idx].sample_rate =
  2587. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2588. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2589. idx, mi2s_rx_cfg[idx].sample_rate,
  2590. ucontrol->value.enumerated.item[0]);
  2591. return 0;
  2592. }
  2593. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2594. struct snd_ctl_elem_value *ucontrol)
  2595. {
  2596. int idx = mi2s_get_port_idx(kcontrol);
  2597. if (idx < 0)
  2598. return idx;
  2599. ucontrol->value.enumerated.item[0] =
  2600. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2601. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2602. idx, mi2s_rx_cfg[idx].sample_rate,
  2603. ucontrol->value.enumerated.item[0]);
  2604. return 0;
  2605. }
  2606. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2607. struct snd_ctl_elem_value *ucontrol)
  2608. {
  2609. int idx = mi2s_get_port_idx(kcontrol);
  2610. if (idx < 0)
  2611. return idx;
  2612. mi2s_tx_cfg[idx].sample_rate =
  2613. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2614. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2615. idx, mi2s_tx_cfg[idx].sample_rate,
  2616. ucontrol->value.enumerated.item[0]);
  2617. return 0;
  2618. }
  2619. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2620. struct snd_ctl_elem_value *ucontrol)
  2621. {
  2622. int idx = mi2s_get_port_idx(kcontrol);
  2623. if (idx < 0)
  2624. return idx;
  2625. ucontrol->value.enumerated.item[0] =
  2626. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2627. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2628. idx, mi2s_tx_cfg[idx].sample_rate,
  2629. ucontrol->value.enumerated.item[0]);
  2630. return 0;
  2631. }
  2632. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2633. struct snd_ctl_elem_value *ucontrol)
  2634. {
  2635. int idx = mi2s_get_port_idx(kcontrol);
  2636. if (idx < 0)
  2637. return idx;
  2638. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2639. idx, mi2s_rx_cfg[idx].channels);
  2640. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2641. return 0;
  2642. }
  2643. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2644. struct snd_ctl_elem_value *ucontrol)
  2645. {
  2646. int idx = mi2s_get_port_idx(kcontrol);
  2647. if (idx < 0)
  2648. return idx;
  2649. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2650. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2651. idx, mi2s_rx_cfg[idx].channels);
  2652. return 1;
  2653. }
  2654. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2655. struct snd_ctl_elem_value *ucontrol)
  2656. {
  2657. int idx = mi2s_get_port_idx(kcontrol);
  2658. if (idx < 0)
  2659. return idx;
  2660. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2661. idx, mi2s_tx_cfg[idx].channels);
  2662. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2663. return 0;
  2664. }
  2665. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2666. struct snd_ctl_elem_value *ucontrol)
  2667. {
  2668. int idx = mi2s_get_port_idx(kcontrol);
  2669. if (idx < 0)
  2670. return idx;
  2671. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2672. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2673. idx, mi2s_tx_cfg[idx].channels);
  2674. return 1;
  2675. }
  2676. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2677. struct snd_ctl_elem_value *ucontrol)
  2678. {
  2679. int idx = mi2s_get_port_idx(kcontrol);
  2680. if (idx < 0)
  2681. return idx;
  2682. ucontrol->value.enumerated.item[0] =
  2683. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2684. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2685. idx, mi2s_rx_cfg[idx].bit_format,
  2686. ucontrol->value.enumerated.item[0]);
  2687. return 0;
  2688. }
  2689. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2690. struct snd_ctl_elem_value *ucontrol)
  2691. {
  2692. struct msm_asoc_mach_data *pdata = NULL;
  2693. struct snd_soc_component *component = NULL;
  2694. struct snd_soc_card *card = NULL;
  2695. int idx = mi2s_get_port_idx(kcontrol);
  2696. component = snd_soc_kcontrol_component(kcontrol);
  2697. card = kcontrol->private_data;
  2698. pdata = snd_soc_card_get_drvdata(card);
  2699. if (idx < 0)
  2700. return idx;
  2701. /* check for PRIM_MI2S and CSRAx config to allow 24bit BE config only */
  2702. if ((PRIM_MI2S == idx) && (true==pdata->codec_is_csra))
  2703. {
  2704. mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2705. pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
  2706. __func__, idx, mi2s_rx_cfg[idx].bit_format,
  2707. ucontrol->value.enumerated.item[0]);
  2708. } else {
  2709. mi2s_rx_cfg[idx].bit_format =
  2710. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2711. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2712. idx, mi2s_rx_cfg[idx].bit_format,
  2713. ucontrol->value.enumerated.item[0]);
  2714. }
  2715. return 0;
  2716. }
  2717. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2718. struct snd_ctl_elem_value *ucontrol)
  2719. {
  2720. int idx = mi2s_get_port_idx(kcontrol);
  2721. if (idx < 0)
  2722. return idx;
  2723. ucontrol->value.enumerated.item[0] =
  2724. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2725. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2726. idx, mi2s_tx_cfg[idx].bit_format,
  2727. ucontrol->value.enumerated.item[0]);
  2728. return 0;
  2729. }
  2730. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2731. struct snd_ctl_elem_value *ucontrol)
  2732. {
  2733. int idx = mi2s_get_port_idx(kcontrol);
  2734. if (idx < 0)
  2735. return idx;
  2736. mi2s_tx_cfg[idx].bit_format =
  2737. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2738. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2739. idx, mi2s_tx_cfg[idx].bit_format,
  2740. ucontrol->value.enumerated.item[0]);
  2741. return 0;
  2742. }
  2743. static int msm_meta_mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2744. {
  2745. int idx = 0;
  2746. if (strnstr(kcontrol->id.name, "PRIM_META_MI2S_RX",
  2747. sizeof("PRIM_META_MI2S_RX"))) {
  2748. idx = PRIM_META_MI2S;
  2749. } else if (strnstr(kcontrol->id.name, "SEC_META_MI2S_RX",
  2750. sizeof("SEC_META_MI2S_RX"))) {
  2751. idx = SEC_META_MI2S;
  2752. } else {
  2753. pr_err("%s: unsupported port: %s",
  2754. __func__, kcontrol->id.name);
  2755. idx = -EINVAL;
  2756. }
  2757. return idx;
  2758. }
  2759. static int msm_meta_mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2760. struct snd_ctl_elem_value *ucontrol)
  2761. {
  2762. int idx = msm_meta_mi2s_get_port_idx(kcontrol);
  2763. if (idx < 0)
  2764. return idx;
  2765. ucontrol->value.enumerated.item[0] =
  2766. mi2s_get_sample_rate_val(meta_mi2s_rx_cfg[idx].sample_rate);
  2767. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2768. idx, meta_mi2s_rx_cfg[idx].sample_rate,
  2769. ucontrol->value.enumerated.item[0]);
  2770. return 0;
  2771. }
  2772. static int msm_meta_mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2773. struct snd_ctl_elem_value *ucontrol)
  2774. {
  2775. int idx = msm_meta_mi2s_get_port_idx(kcontrol);
  2776. if (idx < 0)
  2777. return idx;
  2778. meta_mi2s_rx_cfg[idx].sample_rate =
  2779. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2780. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2781. idx, meta_mi2s_rx_cfg[idx].sample_rate,
  2782. ucontrol->value.enumerated.item[0]);
  2783. return 0;
  2784. }
  2785. static int msm_meta_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2786. struct snd_ctl_elem_value *ucontrol)
  2787. {
  2788. int idx = msm_meta_mi2s_get_port_idx(kcontrol);
  2789. if (idx < 0)
  2790. return idx;
  2791. ucontrol->value.enumerated.item[0] = meta_mi2s_rx_cfg[idx].channels - 1;
  2792. pr_debug("%s: meta_mi2s_[%d]_rx_ch = %d\n", __func__,
  2793. idx, meta_mi2s_rx_cfg[idx].channels);
  2794. return 0;
  2795. }
  2796. static int msm_meta_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2797. struct snd_ctl_elem_value *ucontrol)
  2798. {
  2799. int idx = msm_meta_mi2s_get_port_idx(kcontrol);
  2800. if (idx < 0)
  2801. return idx;
  2802. meta_mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2803. pr_debug("%s: meta_mi2s_[%d]_rx_ch = %d\n", __func__,
  2804. idx, meta_mi2s_rx_cfg[idx].channels);
  2805. return 1;
  2806. }
  2807. static int msm_meta_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2808. struct snd_ctl_elem_value *ucontrol)
  2809. {
  2810. int idx = msm_meta_mi2s_get_port_idx(kcontrol);
  2811. if (idx < 0)
  2812. return idx;
  2813. ucontrol->value.enumerated.item[0] =
  2814. mi2s_auxpcm_get_format_value(meta_mi2s_rx_cfg[idx].bit_format);
  2815. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2816. idx, meta_mi2s_rx_cfg[idx].bit_format,
  2817. ucontrol->value.enumerated.item[0]);
  2818. return 0;
  2819. }
  2820. static int msm_meta_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2821. struct snd_ctl_elem_value *ucontrol)
  2822. {
  2823. struct msm_asoc_mach_data *pdata = NULL;
  2824. struct snd_soc_card *card = NULL;
  2825. int idx = msm_meta_mi2s_get_port_idx(kcontrol);
  2826. card = kcontrol->private_data;
  2827. pdata = snd_soc_card_get_drvdata(card);
  2828. if (idx < 0)
  2829. return idx;
  2830. /* check for PRIM_META_MI2S and CSRAx to allow 24bit BE config only */
  2831. if ((idx == PRIM_META_MI2S) && pdata->codec_is_csra) {
  2832. meta_mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2833. pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
  2834. __func__, idx, meta_mi2s_rx_cfg[idx].bit_format,
  2835. ucontrol->value.enumerated.item[0]);
  2836. } else {
  2837. meta_mi2s_rx_cfg[idx].bit_format =
  2838. mi2s_auxpcm_get_format(
  2839. ucontrol->value.enumerated.item[0]);
  2840. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2841. idx, meta_mi2s_rx_cfg[idx].bit_format,
  2842. ucontrol->value.enumerated.item[0]);
  2843. }
  2844. return 0;
  2845. }
  2846. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2847. struct snd_ctl_elem_value *ucontrol)
  2848. {
  2849. int idx = aux_pcm_get_port_idx(kcontrol);
  2850. if (idx < 0)
  2851. return idx;
  2852. ucontrol->value.enumerated.item[0] =
  2853. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2854. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2855. idx, aux_pcm_rx_cfg[idx].bit_format,
  2856. ucontrol->value.enumerated.item[0]);
  2857. return 0;
  2858. }
  2859. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2860. struct snd_ctl_elem_value *ucontrol)
  2861. {
  2862. int idx = aux_pcm_get_port_idx(kcontrol);
  2863. if (idx < 0)
  2864. return idx;
  2865. aux_pcm_rx_cfg[idx].bit_format =
  2866. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2867. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2868. idx, aux_pcm_rx_cfg[idx].bit_format,
  2869. ucontrol->value.enumerated.item[0]);
  2870. return 0;
  2871. }
  2872. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2873. struct snd_ctl_elem_value *ucontrol)
  2874. {
  2875. int idx = aux_pcm_get_port_idx(kcontrol);
  2876. if (idx < 0)
  2877. return idx;
  2878. ucontrol->value.enumerated.item[0] =
  2879. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2880. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2881. idx, aux_pcm_tx_cfg[idx].bit_format,
  2882. ucontrol->value.enumerated.item[0]);
  2883. return 0;
  2884. }
  2885. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2886. struct snd_ctl_elem_value *ucontrol)
  2887. {
  2888. int idx = aux_pcm_get_port_idx(kcontrol);
  2889. if (idx < 0)
  2890. return idx;
  2891. aux_pcm_tx_cfg[idx].bit_format =
  2892. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2893. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2894. idx, aux_pcm_tx_cfg[idx].bit_format,
  2895. ucontrol->value.enumerated.item[0]);
  2896. return 0;
  2897. }
  2898. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2899. {
  2900. int idx;
  2901. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2902. sizeof("PRIM_SPDIF_RX")))
  2903. idx = PRIM_SPDIF_RX;
  2904. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2905. sizeof("SEC_SPDIF_RX")))
  2906. idx = SEC_SPDIF_RX;
  2907. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2908. sizeof("PRIM_SPDIF_TX")))
  2909. idx = PRIM_SPDIF_TX;
  2910. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2911. sizeof("SEC_SPDIF_TX")))
  2912. idx = SEC_SPDIF_TX;
  2913. else {
  2914. pr_err("%s: unsupported channel: %s",
  2915. __func__, kcontrol->id.name);
  2916. idx = -EINVAL;
  2917. }
  2918. return idx;
  2919. }
  2920. static int spdif_get_sample_rate_val(int sample_rate)
  2921. {
  2922. int sample_rate_val;
  2923. switch (sample_rate) {
  2924. case SAMPLING_RATE_32KHZ:
  2925. sample_rate_val = 0;
  2926. break;
  2927. case SAMPLING_RATE_44P1KHZ:
  2928. sample_rate_val = 1;
  2929. break;
  2930. case SAMPLING_RATE_48KHZ:
  2931. sample_rate_val = 2;
  2932. break;
  2933. case SAMPLING_RATE_88P2KHZ:
  2934. sample_rate_val = 3;
  2935. break;
  2936. case SAMPLING_RATE_96KHZ:
  2937. sample_rate_val = 4;
  2938. break;
  2939. case SAMPLING_RATE_176P4KHZ:
  2940. sample_rate_val = 5;
  2941. break;
  2942. case SAMPLING_RATE_192KHZ:
  2943. sample_rate_val = 6;
  2944. break;
  2945. default:
  2946. sample_rate_val = 2;
  2947. break;
  2948. }
  2949. return sample_rate_val;
  2950. }
  2951. static int spdif_get_sample_rate(int value)
  2952. {
  2953. int sample_rate;
  2954. switch (value) {
  2955. case 0:
  2956. sample_rate = SAMPLING_RATE_32KHZ;
  2957. break;
  2958. case 1:
  2959. sample_rate = SAMPLING_RATE_44P1KHZ;
  2960. break;
  2961. case 2:
  2962. sample_rate = SAMPLING_RATE_48KHZ;
  2963. break;
  2964. case 3:
  2965. sample_rate = SAMPLING_RATE_88P2KHZ;
  2966. break;
  2967. case 4:
  2968. sample_rate = SAMPLING_RATE_96KHZ;
  2969. break;
  2970. case 5:
  2971. sample_rate = SAMPLING_RATE_176P4KHZ;
  2972. break;
  2973. case 6:
  2974. sample_rate = SAMPLING_RATE_192KHZ;
  2975. break;
  2976. default:
  2977. sample_rate = SAMPLING_RATE_48KHZ;
  2978. break;
  2979. }
  2980. return sample_rate;
  2981. }
  2982. static int spdif_get_format(int value)
  2983. {
  2984. int format;
  2985. switch (value) {
  2986. case 0:
  2987. format = SNDRV_PCM_FORMAT_S16_LE;
  2988. break;
  2989. case 1:
  2990. format = SNDRV_PCM_FORMAT_S24_LE;
  2991. break;
  2992. default:
  2993. format = SNDRV_PCM_FORMAT_S16_LE;
  2994. break;
  2995. }
  2996. return format;
  2997. }
  2998. static int spdif_get_format_value(int format)
  2999. {
  3000. int value;
  3001. switch (format) {
  3002. case SNDRV_PCM_FORMAT_S16_LE:
  3003. value = 0;
  3004. break;
  3005. case SNDRV_PCM_FORMAT_S24_LE:
  3006. value = 1;
  3007. break;
  3008. default:
  3009. value = 0;
  3010. break;
  3011. }
  3012. return value;
  3013. }
  3014. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  3015. struct snd_ctl_elem_value *ucontrol)
  3016. {
  3017. int idx = spdif_get_port_idx(kcontrol);
  3018. if (idx < 0)
  3019. return idx;
  3020. spdif_rx_cfg[idx].sample_rate =
  3021. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  3022. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  3023. idx, spdif_rx_cfg[idx].sample_rate,
  3024. ucontrol->value.enumerated.item[0]);
  3025. return 0;
  3026. }
  3027. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  3028. struct snd_ctl_elem_value *ucontrol)
  3029. {
  3030. int idx = spdif_get_port_idx(kcontrol);
  3031. if (idx < 0)
  3032. return idx;
  3033. ucontrol->value.enumerated.item[0] =
  3034. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  3035. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  3036. idx, spdif_rx_cfg[idx].sample_rate,
  3037. ucontrol->value.enumerated.item[0]);
  3038. return 0;
  3039. }
  3040. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  3041. struct snd_ctl_elem_value *ucontrol)
  3042. {
  3043. int idx = spdif_get_port_idx(kcontrol);
  3044. if (idx < 0)
  3045. return idx;
  3046. spdif_tx_cfg[idx].sample_rate =
  3047. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  3048. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  3049. idx, spdif_tx_cfg[idx].sample_rate,
  3050. ucontrol->value.enumerated.item[0]);
  3051. return 0;
  3052. }
  3053. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  3054. struct snd_ctl_elem_value *ucontrol)
  3055. {
  3056. int idx = spdif_get_port_idx(kcontrol);
  3057. if (idx < 0)
  3058. return idx;
  3059. ucontrol->value.enumerated.item[0] =
  3060. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  3061. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  3062. idx, spdif_tx_cfg[idx].sample_rate,
  3063. ucontrol->value.enumerated.item[0]);
  3064. return 0;
  3065. }
  3066. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  3067. struct snd_ctl_elem_value *ucontrol)
  3068. {
  3069. int idx = spdif_get_port_idx(kcontrol);
  3070. if (idx < 0)
  3071. return idx;
  3072. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  3073. idx, spdif_rx_cfg[idx].channels);
  3074. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  3075. return 0;
  3076. }
  3077. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  3078. struct snd_ctl_elem_value *ucontrol)
  3079. {
  3080. int idx = spdif_get_port_idx(kcontrol);
  3081. if (idx < 0)
  3082. return idx;
  3083. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  3084. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  3085. idx, spdif_rx_cfg[idx].channels);
  3086. return 1;
  3087. }
  3088. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  3089. struct snd_ctl_elem_value *ucontrol)
  3090. {
  3091. int idx = spdif_get_port_idx(kcontrol);
  3092. if (idx < 0)
  3093. return idx;
  3094. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  3095. idx, spdif_tx_cfg[idx].channels);
  3096. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  3097. return 0;
  3098. }
  3099. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  3100. struct snd_ctl_elem_value *ucontrol)
  3101. {
  3102. int idx = spdif_get_port_idx(kcontrol);
  3103. if (idx < 0)
  3104. return idx;
  3105. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  3106. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  3107. idx, spdif_tx_cfg[idx].channels);
  3108. return 1;
  3109. }
  3110. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  3111. struct snd_ctl_elem_value *ucontrol)
  3112. {
  3113. int idx = spdif_get_port_idx(kcontrol);
  3114. if (idx < 0)
  3115. return idx;
  3116. ucontrol->value.enumerated.item[0] =
  3117. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  3118. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  3119. idx, spdif_rx_cfg[idx].bit_format,
  3120. ucontrol->value.enumerated.item[0]);
  3121. return 0;
  3122. }
  3123. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  3124. struct snd_ctl_elem_value *ucontrol)
  3125. {
  3126. int idx = spdif_get_port_idx(kcontrol);
  3127. if (idx < 0)
  3128. return idx;
  3129. spdif_rx_cfg[idx].bit_format =
  3130. spdif_get_format(ucontrol->value.enumerated.item[0]);
  3131. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  3132. idx, spdif_rx_cfg[idx].bit_format,
  3133. ucontrol->value.enumerated.item[0]);
  3134. return 0;
  3135. }
  3136. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  3137. struct snd_ctl_elem_value *ucontrol)
  3138. {
  3139. int idx = spdif_get_port_idx(kcontrol);
  3140. if (idx < 0)
  3141. return idx;
  3142. ucontrol->value.enumerated.item[0] =
  3143. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  3144. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  3145. idx, spdif_tx_cfg[idx].bit_format,
  3146. ucontrol->value.enumerated.item[0]);
  3147. return 0;
  3148. }
  3149. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  3150. struct snd_ctl_elem_value *ucontrol)
  3151. {
  3152. int idx = spdif_get_port_idx(kcontrol);
  3153. if (idx < 0)
  3154. return idx;
  3155. spdif_tx_cfg[idx].bit_format =
  3156. spdif_get_format(ucontrol->value.enumerated.item[0]);
  3157. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  3158. idx, spdif_tx_cfg[idx].bit_format,
  3159. ucontrol->value.enumerated.item[0]);
  3160. return 0;
  3161. }
  3162. static int afe_lb_tx_ch_get(struct snd_kcontrol *kcontrol,
  3163. struct snd_ctl_elem_value *ucontrol)
  3164. {
  3165. pr_debug("%s: afe_lb_tx_ch = %d\n", __func__,
  3166. afe_lb_tx_cfg.channels);
  3167. ucontrol->value.integer.value[0] = afe_lb_tx_cfg.channels - 1;
  3168. return 0;
  3169. }
  3170. static int afe_lb_tx_ch_put(struct snd_kcontrol *kcontrol,
  3171. struct snd_ctl_elem_value *ucontrol)
  3172. {
  3173. afe_lb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  3174. pr_debug("%s: afe_lb_tx_ch = %d\n", __func__, afe_lb_tx_cfg.channels);
  3175. return 0;
  3176. }
  3177. static int afe_lb_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  3178. struct snd_ctl_elem_value *ucontrol)
  3179. {
  3180. int sample_rate_val;
  3181. switch (afe_lb_tx_cfg.sample_rate) {
  3182. case SAMPLING_RATE_384KHZ:
  3183. sample_rate_val = 12;
  3184. break;
  3185. case SAMPLING_RATE_352P8KHZ:
  3186. sample_rate_val = 11;
  3187. break;
  3188. case SAMPLING_RATE_192KHZ:
  3189. sample_rate_val = 10;
  3190. break;
  3191. case SAMPLING_RATE_176P4KHZ:
  3192. sample_rate_val = 9;
  3193. break;
  3194. case SAMPLING_RATE_96KHZ:
  3195. sample_rate_val = 8;
  3196. break;
  3197. case SAMPLING_RATE_88P2KHZ:
  3198. sample_rate_val = 7;
  3199. break;
  3200. case SAMPLING_RATE_48KHZ:
  3201. sample_rate_val = 6;
  3202. break;
  3203. case SAMPLING_RATE_44P1KHZ:
  3204. sample_rate_val = 5;
  3205. break;
  3206. case SAMPLING_RATE_32KHZ:
  3207. sample_rate_val = 4;
  3208. break;
  3209. case SAMPLING_RATE_22P05KHZ:
  3210. sample_rate_val = 3;
  3211. break;
  3212. case SAMPLING_RATE_16KHZ:
  3213. sample_rate_val = 2;
  3214. break;
  3215. case SAMPLING_RATE_11P025KHZ:
  3216. sample_rate_val = 1;
  3217. break;
  3218. case SAMPLING_RATE_8KHZ:
  3219. sample_rate_val = 0;
  3220. break;
  3221. default:
  3222. sample_rate_val = 6;
  3223. break;
  3224. }
  3225. ucontrol->value.integer.value[0] = sample_rate_val;
  3226. pr_debug("%s: afe_lb_tx_sample_rate = %d\n", __func__,
  3227. afe_lb_tx_cfg.sample_rate);
  3228. return 0;
  3229. }
  3230. static int afe_lb_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  3231. struct snd_ctl_elem_value *ucontrol)
  3232. {
  3233. switch (ucontrol->value.integer.value[0]) {
  3234. case 12:
  3235. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  3236. break;
  3237. case 11:
  3238. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  3239. break;
  3240. case 10:
  3241. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  3242. break;
  3243. case 9:
  3244. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  3245. break;
  3246. case 8:
  3247. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  3248. break;
  3249. case 7:
  3250. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  3251. break;
  3252. case 6:
  3253. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  3254. break;
  3255. case 5:
  3256. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  3257. break;
  3258. case 4:
  3259. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  3260. break;
  3261. case 3:
  3262. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  3263. break;
  3264. case 2:
  3265. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  3266. break;
  3267. case 1:
  3268. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  3269. break;
  3270. case 0:
  3271. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  3272. break;
  3273. default:
  3274. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  3275. break;
  3276. }
  3277. pr_debug("%s: control value = %ld, afe_lb_tx_sample_rate = %d\n",
  3278. __func__, ucontrol->value.integer.value[0],
  3279. afe_lb_tx_cfg.sample_rate);
  3280. return 0;
  3281. }
  3282. static int afe_lb_tx_format_get(struct snd_kcontrol *kcontrol,
  3283. struct snd_ctl_elem_value *ucontrol)
  3284. {
  3285. switch (afe_lb_tx_cfg.bit_format) {
  3286. case SNDRV_PCM_FORMAT_S32_LE:
  3287. ucontrol->value.integer.value[0] = 3;
  3288. break;
  3289. case SNDRV_PCM_FORMAT_S24_3LE:
  3290. ucontrol->value.integer.value[0] = 2;
  3291. break;
  3292. case SNDRV_PCM_FORMAT_S24_LE:
  3293. ucontrol->value.integer.value[0] = 1;
  3294. break;
  3295. case SNDRV_PCM_FORMAT_S16_LE:
  3296. default:
  3297. ucontrol->value.integer.value[0] = 0;
  3298. break;
  3299. }
  3300. pr_debug("%s: afe_lb_tx_format = %d, ucontrol value = %ld\n",
  3301. __func__, afe_lb_tx_cfg.bit_format,
  3302. ucontrol->value.integer.value[0]);
  3303. return 0;
  3304. }
  3305. static int afe_lb_tx_format_put(struct snd_kcontrol *kcontrol,
  3306. struct snd_ctl_elem_value *ucontrol)
  3307. {
  3308. switch (ucontrol->value.integer.value[0]) {
  3309. case 3:
  3310. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  3311. break;
  3312. case 2:
  3313. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  3314. break;
  3315. case 1:
  3316. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  3317. break;
  3318. case 0:
  3319. default:
  3320. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  3321. break;
  3322. }
  3323. pr_debug("%s: afe_lb_tx_format = %d, ucontrol value = %ld\n",
  3324. __func__, afe_lb_tx_cfg.bit_format,
  3325. ucontrol->value.integer.value[0]);
  3326. return 0;
  3327. }
  3328. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  3329. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  3330. slim_rx_ch_get, slim_rx_ch_put),
  3331. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  3332. slim_rx_ch_get, slim_rx_ch_put),
  3333. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  3334. slim_tx_ch_get, slim_tx_ch_put),
  3335. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  3336. slim_tx_ch_get, slim_tx_ch_put),
  3337. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  3338. slim_rx_ch_get, slim_rx_ch_put),
  3339. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  3340. slim_rx_ch_get, slim_rx_ch_put),
  3341. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  3342. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3343. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  3344. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3345. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  3346. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3347. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  3348. slim_tx_bit_format_get, slim_tx_bit_format_put),
  3349. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  3350. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3351. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  3352. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3353. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  3354. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  3355. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  3356. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3357. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  3358. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3359. };
  3360. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  3361. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  3362. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3363. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  3364. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3365. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  3366. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3367. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  3368. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3369. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3370. va_cdc_dma_tx_0_sample_rate,
  3371. cdc_dma_tx_sample_rate_get,
  3372. cdc_dma_tx_sample_rate_put),
  3373. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3374. va_cdc_dma_tx_1_sample_rate,
  3375. cdc_dma_tx_sample_rate_get,
  3376. cdc_dma_tx_sample_rate_put),
  3377. };
  3378. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  3379. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3380. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3381. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  3382. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3383. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  3384. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3385. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  3386. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3387. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  3388. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3389. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  3390. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3391. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  3392. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3393. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  3394. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3395. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  3396. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3397. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  3398. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3399. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  3400. wsa_cdc_dma_rx_0_sample_rate,
  3401. cdc_dma_rx_sample_rate_get,
  3402. cdc_dma_rx_sample_rate_put),
  3403. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  3404. wsa_cdc_dma_rx_1_sample_rate,
  3405. cdc_dma_rx_sample_rate_get,
  3406. cdc_dma_rx_sample_rate_put),
  3407. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  3408. wsa_cdc_dma_tx_0_sample_rate,
  3409. cdc_dma_tx_sample_rate_get,
  3410. cdc_dma_tx_sample_rate_put),
  3411. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  3412. wsa_cdc_dma_tx_1_sample_rate,
  3413. cdc_dma_tx_sample_rate_get,
  3414. cdc_dma_tx_sample_rate_put),
  3415. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  3416. wsa_cdc_dma_tx_2_sample_rate,
  3417. cdc_dma_tx_sample_rate_get,
  3418. cdc_dma_tx_sample_rate_put),
  3419. };
  3420. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3421. SOC_ENUM_EXT("BT_TX SampleRate", bt_sample_rate_sink,
  3422. msm_bt_sample_rate_sink_get,
  3423. msm_bt_sample_rate_sink_put),
  3424. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3425. msm_bt_sample_rate_get,
  3426. msm_bt_sample_rate_put),
  3427. SOC_ENUM_EXT("BT_RX SampleRate", bt_sample_rate,
  3428. msm_bt_sample_rate_get,
  3429. msm_bt_sample_rate_put),
  3430. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3431. proxy_rx_ch_get, proxy_rx_ch_put),
  3432. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3433. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3434. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3435. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3436. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3437. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3438. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3439. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3440. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3441. usb_audio_rx_sample_rate_get,
  3442. usb_audio_rx_sample_rate_put),
  3443. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3444. usb_audio_tx_sample_rate_get,
  3445. usb_audio_tx_sample_rate_put),
  3446. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3447. tdm_rx_sample_rate_get,
  3448. tdm_rx_sample_rate_put),
  3449. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3450. tdm_tx_sample_rate_get,
  3451. tdm_tx_sample_rate_put),
  3452. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3453. tdm_rx_format_get,
  3454. tdm_rx_format_put),
  3455. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3456. tdm_tx_format_get,
  3457. tdm_tx_format_put),
  3458. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3459. tdm_rx_ch_get,
  3460. tdm_rx_ch_put),
  3461. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3462. tdm_tx_ch_get,
  3463. tdm_tx_ch_put),
  3464. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3465. tdm_rx_sample_rate_get,
  3466. tdm_rx_sample_rate_put),
  3467. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3468. tdm_tx_sample_rate_get,
  3469. tdm_tx_sample_rate_put),
  3470. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3471. tdm_rx_format_get,
  3472. tdm_rx_format_put),
  3473. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3474. tdm_tx_format_get,
  3475. tdm_tx_format_put),
  3476. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3477. tdm_rx_ch_get,
  3478. tdm_rx_ch_put),
  3479. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3480. tdm_tx_ch_get,
  3481. tdm_tx_ch_put),
  3482. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3483. tdm_rx_sample_rate_get,
  3484. tdm_rx_sample_rate_put),
  3485. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3486. tdm_tx_sample_rate_get,
  3487. tdm_tx_sample_rate_put),
  3488. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3489. tdm_rx_format_get,
  3490. tdm_rx_format_put),
  3491. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3492. tdm_tx_format_get,
  3493. tdm_tx_format_put),
  3494. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3495. tdm_rx_ch_get,
  3496. tdm_rx_ch_put),
  3497. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3498. tdm_tx_ch_get,
  3499. tdm_tx_ch_put),
  3500. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3501. tdm_rx_sample_rate_get,
  3502. tdm_rx_sample_rate_put),
  3503. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3504. tdm_tx_sample_rate_get,
  3505. tdm_tx_sample_rate_put),
  3506. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3507. tdm_rx_format_get,
  3508. tdm_rx_format_put),
  3509. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3510. tdm_tx_format_get,
  3511. tdm_tx_format_put),
  3512. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3513. tdm_rx_ch_get,
  3514. tdm_rx_ch_put),
  3515. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3516. tdm_tx_ch_get,
  3517. tdm_tx_ch_put),
  3518. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3519. tdm_rx_sample_rate_get,
  3520. tdm_rx_sample_rate_put),
  3521. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3522. tdm_tx_sample_rate_get,
  3523. tdm_tx_sample_rate_put),
  3524. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3525. tdm_rx_format_get,
  3526. tdm_rx_format_put),
  3527. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3528. tdm_tx_format_get,
  3529. tdm_tx_format_put),
  3530. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3531. tdm_rx_ch_get,
  3532. tdm_rx_ch_put),
  3533. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3534. tdm_tx_ch_get,
  3535. tdm_tx_ch_put),
  3536. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3537. aux_pcm_rx_sample_rate_get,
  3538. aux_pcm_rx_sample_rate_put),
  3539. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3540. aux_pcm_rx_sample_rate_get,
  3541. aux_pcm_rx_sample_rate_put),
  3542. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3543. aux_pcm_rx_sample_rate_get,
  3544. aux_pcm_rx_sample_rate_put),
  3545. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3546. aux_pcm_rx_sample_rate_get,
  3547. aux_pcm_rx_sample_rate_put),
  3548. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3549. aux_pcm_rx_sample_rate_get,
  3550. aux_pcm_rx_sample_rate_put),
  3551. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3552. aux_pcm_tx_sample_rate_get,
  3553. aux_pcm_tx_sample_rate_put),
  3554. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3555. aux_pcm_tx_sample_rate_get,
  3556. aux_pcm_tx_sample_rate_put),
  3557. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3558. aux_pcm_tx_sample_rate_get,
  3559. aux_pcm_tx_sample_rate_put),
  3560. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3561. aux_pcm_tx_sample_rate_get,
  3562. aux_pcm_tx_sample_rate_put),
  3563. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3564. aux_pcm_tx_sample_rate_get,
  3565. aux_pcm_tx_sample_rate_put),
  3566. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3567. aux_pcm_tx_sample_rate_get,
  3568. aux_pcm_tx_sample_rate_put),
  3569. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3570. mi2s_rx_sample_rate_get,
  3571. mi2s_rx_sample_rate_put),
  3572. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3573. mi2s_rx_sample_rate_get,
  3574. mi2s_rx_sample_rate_put),
  3575. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3576. mi2s_rx_sample_rate_get,
  3577. mi2s_rx_sample_rate_put),
  3578. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3579. mi2s_rx_sample_rate_get,
  3580. mi2s_rx_sample_rate_put),
  3581. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3582. mi2s_rx_sample_rate_get,
  3583. mi2s_rx_sample_rate_put),
  3584. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3585. mi2s_rx_sample_rate_get,
  3586. mi2s_rx_sample_rate_put),
  3587. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3588. mi2s_tx_sample_rate_get,
  3589. mi2s_tx_sample_rate_put),
  3590. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3591. mi2s_tx_sample_rate_get,
  3592. mi2s_tx_sample_rate_put),
  3593. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3594. mi2s_tx_sample_rate_get,
  3595. mi2s_tx_sample_rate_put),
  3596. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3597. mi2s_tx_sample_rate_get,
  3598. mi2s_tx_sample_rate_put),
  3599. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3600. mi2s_tx_sample_rate_get,
  3601. mi2s_tx_sample_rate_put),
  3602. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3603. mi2s_tx_sample_rate_get,
  3604. mi2s_tx_sample_rate_put),
  3605. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3606. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3607. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3608. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3609. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3610. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3611. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3612. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3613. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3614. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3615. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3616. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3617. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3618. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3619. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3620. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3621. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3622. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3623. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3624. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3625. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3626. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3627. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3628. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3629. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3630. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3631. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3632. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3633. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3634. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3635. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3636. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3637. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3638. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3639. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3640. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3641. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3642. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3643. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3644. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3645. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3646. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3647. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3648. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3649. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3650. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3651. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3652. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3653. SOC_ENUM_EXT("PRIM_META_MI2S_RX SampleRate",
  3654. prim_meta_mi2s_rx_sample_rate,
  3655. msm_meta_mi2s_rx_sample_rate_get,
  3656. msm_meta_mi2s_rx_sample_rate_put),
  3657. SOC_ENUM_EXT("SEC_META_MI2S_RX SampleRate",
  3658. sec_meta_mi2s_rx_sample_rate,
  3659. msm_meta_mi2s_rx_sample_rate_get,
  3660. msm_meta_mi2s_rx_sample_rate_put),
  3661. SOC_ENUM_EXT("PRIM_META_MI2S_RX Channels", prim_meta_mi2s_rx_chs,
  3662. msm_meta_mi2s_rx_ch_get,
  3663. msm_meta_mi2s_rx_ch_put),
  3664. SOC_ENUM_EXT("SEC_META_MI2S_RX Channels", sec_meta_mi2s_rx_chs,
  3665. msm_meta_mi2s_rx_ch_get,
  3666. msm_meta_mi2s_rx_ch_put),
  3667. SOC_ENUM_EXT("PRIM_META_MI2S_RX Format", mi2s_rx_format,
  3668. msm_meta_mi2s_rx_format_get,
  3669. msm_meta_mi2s_rx_format_put),
  3670. SOC_ENUM_EXT("SEC_META_MI2S_RX Format", mi2s_rx_format,
  3671. msm_meta_mi2s_rx_format_get,
  3672. msm_meta_mi2s_rx_format_put),
  3673. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3674. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3675. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3676. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3677. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3678. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3679. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3680. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3681. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3682. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3683. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3684. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3685. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3686. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3687. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3688. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3689. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3690. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3691. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3692. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3693. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3694. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3695. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3696. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3697. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3698. msm_snd_vad_cfg_put),
  3699. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3700. msm_spdif_rx_sample_rate_get,
  3701. msm_spdif_rx_sample_rate_put),
  3702. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3703. msm_spdif_tx_sample_rate_get,
  3704. msm_spdif_tx_sample_rate_put),
  3705. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3706. msm_spdif_rx_sample_rate_get,
  3707. msm_spdif_rx_sample_rate_put),
  3708. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3709. msm_spdif_tx_sample_rate_get,
  3710. msm_spdif_tx_sample_rate_put),
  3711. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3712. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3713. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3714. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3715. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3716. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3717. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3718. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3719. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3720. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3721. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3722. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3723. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3724. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3725. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3726. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3727. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_lb_tx_chs,
  3728. afe_lb_tx_ch_get, afe_lb_tx_ch_put),
  3729. SOC_ENUM_EXT("AFE_LOOPBACK_TX Format", afe_lb_tx_format,
  3730. afe_lb_tx_format_get, afe_lb_tx_format_put),
  3731. SOC_ENUM_EXT("AFE_LOOPBACK_TX SampleRate", afe_lb_tx_sample_rate,
  3732. afe_lb_tx_sample_rate_get,
  3733. afe_lb_tx_sample_rate_put),
  3734. };
  3735. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  3736. int enable, bool dapm)
  3737. {
  3738. int ret = 0;
  3739. if (!strcmp(component.name, "tasha_codec")) {
  3740. ret = tasha_cdc_mclk_enable(component, enable, dapm);
  3741. } else {
  3742. dev_err(component->dev, "%s: unknown codec to enable ext clk\n",
  3743. __func__);
  3744. ret = -EINVAL;
  3745. }
  3746. return ret;
  3747. }
  3748. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_component *component,
  3749. int enable, bool dapm)
  3750. {
  3751. int ret = 0;
  3752. if (!strcmp(component.name, "tasha_codec")) {
  3753. ret = tasha_cdc_mclk_tx_enable(component, enable, dapm);
  3754. } else {
  3755. dev_err(component->dev, "%s: unknown codec to enable TX ext clk\n",
  3756. __func__);
  3757. ret = -EINVAL;
  3758. }
  3759. return ret;
  3760. }
  3761. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3762. struct snd_kcontrol *kcontrol, int event)
  3763. {
  3764. struct snd_soc_component *component =
  3765. snd_soc_dapm_to_component(w->dapm);
  3766. pr_debug("%s: event = %d\n", __func__, event);
  3767. switch (event) {
  3768. case SND_SOC_DAPM_PRE_PMU:
  3769. return msm_snd_enable_codec_ext_tx_clk(component, 1, true);
  3770. case SND_SOC_DAPM_POST_PMD:
  3771. return msm_snd_enable_codec_ext_tx_clk(component, 0, true);
  3772. }
  3773. return 0;
  3774. }
  3775. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3776. struct snd_kcontrol *kcontrol, int event)
  3777. {
  3778. struct snd_soc_component *component =
  3779. snd_soc_dapm_to_component(w->dapm);
  3780. pr_debug("%s: event = %d\n", __func__, event);
  3781. switch (event) {
  3782. case SND_SOC_DAPM_PRE_PMU:
  3783. return msm_snd_enable_codec_ext_clk(component, 1, true);
  3784. case SND_SOC_DAPM_POST_PMD:
  3785. return msm_snd_enable_codec_ext_clk(component, 0, true);
  3786. }
  3787. return 0;
  3788. }
  3789. static int msm_lineout_booster_ctrl_event(struct snd_soc_dapm_widget *w,
  3790. struct snd_kcontrol *k, int event)
  3791. {
  3792. struct snd_soc_component *component =
  3793. snd_soc_dapm_to_component(w->dapm);
  3794. struct snd_soc_card *card = component->card;
  3795. struct msm_asoc_mach_data *pdata =
  3796. snd_soc_card_get_drvdata(card);
  3797. pr_debug("%s: event = %d\n", __func__, event);
  3798. switch (event) {
  3799. case SND_SOC_DAPM_POST_PMU:
  3800. msm_cdc_pinctrl_select_active_state(
  3801. pdata->lineout_booster_gpio_p);
  3802. break;
  3803. case SND_SOC_DAPM_PRE_PMD:
  3804. msm_cdc_pinctrl_select_sleep_state(
  3805. pdata->lineout_booster_gpio_p);
  3806. break;
  3807. }
  3808. return 0;
  3809. }
  3810. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3811. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3812. msm_mclk_event,
  3813. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3814. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3815. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3816. SND_SOC_DAPM_SPK("lineout booster", msm_lineout_booster_ctrl_event),
  3817. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3818. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3819. };
  3820. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3821. struct snd_kcontrol *kcontrol, int event)
  3822. {
  3823. struct msm_asoc_mach_data *pdata = NULL;
  3824. struct snd_soc_component *component =
  3825. snd_soc_dapm_to_component(w->dapm);
  3826. int ret = 0;
  3827. uint32_t dmic_idx;
  3828. int *dmic_gpio_cnt;
  3829. struct device_node *dmic_gpio;
  3830. char *wname;
  3831. wname = strpbrk(w->name, "01234567");
  3832. if (!wname) {
  3833. dev_err(component->dev, "%s: widget not found\n", __func__);
  3834. return -EINVAL;
  3835. }
  3836. ret = kstrtouint(wname, 10, &dmic_idx);
  3837. if (ret < 0) {
  3838. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  3839. __func__);
  3840. return -EINVAL;
  3841. }
  3842. pdata = snd_soc_card_get_drvdata(component->card);
  3843. switch (dmic_idx) {
  3844. case 0:
  3845. case 1:
  3846. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3847. dmic_gpio = pdata->dmic_01_gpio_p;
  3848. break;
  3849. case 2:
  3850. case 3:
  3851. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3852. dmic_gpio = pdata->dmic_23_gpio_p;
  3853. break;
  3854. case 4:
  3855. case 5:
  3856. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3857. dmic_gpio = pdata->dmic_45_gpio_p;
  3858. break;
  3859. case 6:
  3860. case 7:
  3861. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3862. dmic_gpio = pdata->dmic_67_gpio_p;
  3863. break;
  3864. default:
  3865. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  3866. __func__);
  3867. return -EINVAL;
  3868. }
  3869. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3870. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3871. switch (event) {
  3872. case SND_SOC_DAPM_PRE_PMU:
  3873. (*dmic_gpio_cnt)++;
  3874. if (*dmic_gpio_cnt == 1) {
  3875. ret = msm_cdc_pinctrl_select_active_state(
  3876. dmic_gpio);
  3877. if (ret < 0) {
  3878. dev_err(component->dev, "%s: gpio set cannot be activated %sd\n",
  3879. __func__, "dmic_gpio");
  3880. return ret;
  3881. }
  3882. }
  3883. break;
  3884. case SND_SOC_DAPM_POST_PMD:
  3885. (*dmic_gpio_cnt)--;
  3886. if (*dmic_gpio_cnt == 0) {
  3887. ret = msm_cdc_pinctrl_select_sleep_state(
  3888. dmic_gpio);
  3889. if (ret < 0) {
  3890. dev_err(component->dev, "%s: gpio set cannot be de-activated %sd\n",
  3891. __func__, "dmic_gpio");
  3892. return ret;
  3893. }
  3894. }
  3895. break;
  3896. default:
  3897. dev_err(component->dev, "%s: invalid DAPM event %d\n",
  3898. __func__, event);
  3899. return -EINVAL;
  3900. }
  3901. return 0;
  3902. }
  3903. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3904. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3905. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3906. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3907. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3908. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3909. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3910. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3911. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3912. };
  3913. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3914. };
  3915. static inline int param_is_mask(int p)
  3916. {
  3917. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3918. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3919. }
  3920. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3921. int n)
  3922. {
  3923. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3924. }
  3925. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3926. unsigned int bit)
  3927. {
  3928. if (bit >= SNDRV_MASK_MAX)
  3929. return;
  3930. if (param_is_mask(n)) {
  3931. struct snd_mask *m = param_to_mask(p, n);
  3932. m->bits[0] = 0;
  3933. m->bits[1] = 0;
  3934. m->bits[bit >> 5] |= (1 << (bit & 31));
  3935. }
  3936. }
  3937. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3938. {
  3939. int ch_id = 0;
  3940. switch (be_id) {
  3941. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3942. ch_id = SLIM_RX_0;
  3943. break;
  3944. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3945. ch_id = SLIM_RX_1;
  3946. break;
  3947. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3948. ch_id = SLIM_RX_2;
  3949. break;
  3950. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3951. ch_id = SLIM_RX_3;
  3952. break;
  3953. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3954. ch_id = SLIM_RX_4;
  3955. break;
  3956. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3957. ch_id = SLIM_RX_6;
  3958. break;
  3959. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3960. ch_id = SLIM_TX_0;
  3961. break;
  3962. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3963. ch_id = SLIM_TX_3;
  3964. break;
  3965. default:
  3966. ch_id = SLIM_RX_0;
  3967. break;
  3968. }
  3969. return ch_id;
  3970. }
  3971. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3972. {
  3973. int idx = 0;
  3974. switch (be_id) {
  3975. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3976. idx = WSA_CDC_DMA_RX_0;
  3977. break;
  3978. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3979. idx = WSA_CDC_DMA_TX_0;
  3980. break;
  3981. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3982. idx = WSA_CDC_DMA_RX_1;
  3983. break;
  3984. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3985. idx = WSA_CDC_DMA_TX_1;
  3986. break;
  3987. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3988. idx = WSA_CDC_DMA_TX_2;
  3989. break;
  3990. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3991. idx = VA_CDC_DMA_TX_0;
  3992. break;
  3993. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3994. idx = VA_CDC_DMA_TX_1;
  3995. break;
  3996. default:
  3997. idx = VA_CDC_DMA_TX_0;
  3998. break;
  3999. }
  4000. return idx;
  4001. }
  4002. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4003. struct snd_pcm_hw_params *params)
  4004. {
  4005. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4006. struct snd_interval *rate = hw_param_interval(params,
  4007. SNDRV_PCM_HW_PARAM_RATE);
  4008. struct snd_interval *channels = hw_param_interval(params,
  4009. SNDRV_PCM_HW_PARAM_CHANNELS);
  4010. int rc = 0;
  4011. int idx;
  4012. void *config = NULL;
  4013. struct snd_soc_component *component = NULL;
  4014. pr_debug("%s: format = %d, rate = %d\n",
  4015. __func__, params_format(params), params_rate(params));
  4016. switch (dai_link->id) {
  4017. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  4018. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  4019. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  4020. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  4021. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  4022. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  4023. idx = msm_slim_get_ch_from_beid(dai_link->id);
  4024. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4025. slim_rx_cfg[idx].bit_format);
  4026. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  4027. channels->min = channels->max = slim_rx_cfg[idx].channels;
  4028. break;
  4029. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  4030. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  4031. idx = msm_slim_get_ch_from_beid(dai_link->id);
  4032. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4033. slim_tx_cfg[idx].bit_format);
  4034. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  4035. channels->min = channels->max = slim_tx_cfg[idx].channels;
  4036. break;
  4037. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  4038. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4039. slim_tx_cfg[1].bit_format);
  4040. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  4041. channels->min = channels->max = slim_tx_cfg[1].channels;
  4042. break;
  4043. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  4044. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4045. SNDRV_PCM_FORMAT_S32_LE);
  4046. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  4047. channels->min = channels->max = msm_vi_feed_tx_ch;
  4048. break;
  4049. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  4050. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4051. slim_rx_cfg[5].bit_format);
  4052. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  4053. channels->min = channels->max = slim_rx_cfg[5].channels;
  4054. break;
  4055. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  4056. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4057. if (!component) {
  4058. pr_err("%s: component is NULL\n", __func__);
  4059. return -EINVAL;
  4060. }
  4061. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  4062. channels->min = channels->max = 1;
  4063. config = msm_codec_fn.get_afe_config_fn(component,
  4064. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  4065. if (config) {
  4066. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  4067. config, SLIMBUS_5_TX);
  4068. if (rc)
  4069. pr_err("%s: Failed to set slimbus slave port config %d\n",
  4070. __func__, rc);
  4071. }
  4072. break;
  4073. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  4074. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4075. slim_rx_cfg[SLIM_RX_7].bit_format);
  4076. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  4077. channels->min = channels->max =
  4078. slim_rx_cfg[SLIM_RX_7].channels;
  4079. break;
  4080. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  4081. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  4082. channels->min = channels->max =
  4083. slim_tx_cfg[SLIM_TX_7].channels;
  4084. break;
  4085. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  4086. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  4087. channels->min = channels->max =
  4088. slim_tx_cfg[SLIM_TX_8].channels;
  4089. break;
  4090. case MSM_BACKEND_DAI_SLIMBUS_9_TX:
  4091. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4092. slim_tx_cfg[SLIM_TX_9].bit_format);
  4093. rate->min = rate->max = slim_tx_cfg[SLIM_TX_9].sample_rate;
  4094. channels->min = channels->max =
  4095. slim_tx_cfg[SLIM_TX_9].channels;
  4096. break;
  4097. case MSM_BACKEND_DAI_USB_RX:
  4098. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4099. usb_rx_cfg.bit_format);
  4100. rate->min = rate->max = usb_rx_cfg.sample_rate;
  4101. channels->min = channels->max = usb_rx_cfg.channels;
  4102. break;
  4103. case MSM_BACKEND_DAI_USB_TX:
  4104. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4105. usb_tx_cfg.bit_format);
  4106. rate->min = rate->max = usb_tx_cfg.sample_rate;
  4107. channels->min = channels->max = usb_tx_cfg.channels;
  4108. break;
  4109. case MSM_BACKEND_DAI_AFE_PCM_RX:
  4110. channels->min = channels->max = proxy_rx_cfg.channels;
  4111. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  4112. break;
  4113. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  4114. channels->min = channels->max =
  4115. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4116. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4117. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  4118. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  4119. break;
  4120. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  4121. channels->min = channels->max =
  4122. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4123. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4124. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  4125. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  4126. break;
  4127. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  4128. channels->min = channels->max =
  4129. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4130. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4131. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4132. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4133. break;
  4134. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  4135. channels->min = channels->max =
  4136. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4137. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4138. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  4139. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  4140. break;
  4141. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  4142. channels->min = channels->max =
  4143. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4144. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4145. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  4146. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  4147. break;
  4148. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  4149. channels->min = channels->max =
  4150. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4151. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4152. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  4153. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  4154. break;
  4155. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  4156. channels->min = channels->max =
  4157. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4158. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4159. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4160. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4161. break;
  4162. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  4163. channels->min = channels->max =
  4164. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4165. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4166. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  4167. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4168. break;
  4169. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  4170. channels->min = channels->max =
  4171. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4172. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4173. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4174. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4175. break;
  4176. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  4177. channels->min = channels->max =
  4178. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4179. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4180. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  4181. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4182. break;
  4183. case MSM_BACKEND_DAI_AUXPCM_RX:
  4184. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4185. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  4186. rate->min = rate->max =
  4187. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  4188. channels->min = channels->max =
  4189. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  4190. break;
  4191. case MSM_BACKEND_DAI_AUXPCM_TX:
  4192. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4193. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  4194. rate->min = rate->max =
  4195. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  4196. channels->min = channels->max =
  4197. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  4198. break;
  4199. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  4200. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4201. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  4202. rate->min = rate->max =
  4203. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  4204. channels->min = channels->max =
  4205. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  4206. break;
  4207. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  4208. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4209. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  4210. rate->min = rate->max =
  4211. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  4212. channels->min = channels->max =
  4213. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  4214. break;
  4215. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  4216. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4217. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  4218. rate->min = rate->max =
  4219. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  4220. channels->min = channels->max =
  4221. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  4222. break;
  4223. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  4224. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4225. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  4226. rate->min = rate->max =
  4227. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  4228. channels->min = channels->max =
  4229. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  4230. break;
  4231. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  4232. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4233. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  4234. rate->min = rate->max =
  4235. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  4236. channels->min = channels->max =
  4237. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  4238. break;
  4239. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  4240. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4241. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  4242. rate->min = rate->max =
  4243. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  4244. channels->min = channels->max =
  4245. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  4246. break;
  4247. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  4248. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4249. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  4250. rate->min = rate->max =
  4251. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  4252. channels->min = channels->max =
  4253. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  4254. break;
  4255. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  4256. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4257. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  4258. rate->min = rate->max =
  4259. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  4260. channels->min = channels->max =
  4261. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  4262. break;
  4263. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  4264. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4265. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  4266. rate->min = rate->max =
  4267. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  4268. channels->min = channels->max =
  4269. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  4270. break;
  4271. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  4272. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4273. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  4274. rate->min = rate->max =
  4275. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  4276. channels->min = channels->max =
  4277. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  4278. break;
  4279. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4280. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4281. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  4282. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  4283. channels->min = channels->max =
  4284. mi2s_rx_cfg[PRIM_MI2S].channels;
  4285. break;
  4286. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4287. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4288. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  4289. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  4290. channels->min = channels->max =
  4291. mi2s_tx_cfg[PRIM_MI2S].channels;
  4292. break;
  4293. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4294. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4295. mi2s_rx_cfg[SEC_MI2S].bit_format);
  4296. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  4297. channels->min = channels->max =
  4298. mi2s_rx_cfg[SEC_MI2S].channels;
  4299. break;
  4300. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4301. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4302. mi2s_tx_cfg[SEC_MI2S].bit_format);
  4303. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  4304. channels->min = channels->max =
  4305. mi2s_tx_cfg[SEC_MI2S].channels;
  4306. break;
  4307. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4308. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4309. mi2s_rx_cfg[TERT_MI2S].bit_format);
  4310. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  4311. channels->min = channels->max =
  4312. mi2s_rx_cfg[TERT_MI2S].channels;
  4313. break;
  4314. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4315. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4316. mi2s_tx_cfg[TERT_MI2S].bit_format);
  4317. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  4318. channels->min = channels->max =
  4319. mi2s_tx_cfg[TERT_MI2S].channels;
  4320. break;
  4321. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4322. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4323. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  4324. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  4325. channels->min = channels->max =
  4326. mi2s_rx_cfg[QUAT_MI2S].channels;
  4327. break;
  4328. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4329. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4330. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  4331. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  4332. channels->min = channels->max =
  4333. mi2s_tx_cfg[QUAT_MI2S].channels;
  4334. break;
  4335. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4336. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4337. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  4338. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  4339. channels->min = channels->max =
  4340. mi2s_rx_cfg[QUIN_MI2S].channels;
  4341. break;
  4342. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4343. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4344. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  4345. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  4346. channels->min = channels->max =
  4347. mi2s_tx_cfg[QUIN_MI2S].channels;
  4348. break;
  4349. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  4350. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4351. mi2s_rx_cfg[SEN_MI2S].bit_format);
  4352. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  4353. channels->min = channels->max =
  4354. mi2s_rx_cfg[SEN_MI2S].channels;
  4355. break;
  4356. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4357. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4358. mi2s_tx_cfg[SEN_MI2S].bit_format);
  4359. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  4360. channels->min = channels->max =
  4361. mi2s_tx_cfg[SEN_MI2S].channels;
  4362. break;
  4363. case MSM_BACKEND_DAI_PRI_META_MI2S_RX:
  4364. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4365. meta_mi2s_rx_cfg[PRIM_META_MI2S].bit_format);
  4366. rate->min = rate->max =
  4367. meta_mi2s_rx_cfg[PRIM_META_MI2S].sample_rate;
  4368. channels->min = channels->max =
  4369. meta_mi2s_rx_cfg[PRIM_META_MI2S].channels;
  4370. break;
  4371. case MSM_BACKEND_DAI_SEC_META_MI2S_RX:
  4372. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4373. meta_mi2s_rx_cfg[SEC_META_MI2S].bit_format);
  4374. rate->min = rate->max =
  4375. meta_mi2s_rx_cfg[SEC_META_MI2S].sample_rate;
  4376. channels->min = channels->max =
  4377. meta_mi2s_rx_cfg[SEC_META_MI2S].channels;
  4378. break;
  4379. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4380. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4381. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4382. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4383. cdc_dma_rx_cfg[idx].bit_format);
  4384. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  4385. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  4386. break;
  4387. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4388. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4389. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4390. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4391. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4392. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4393. cdc_dma_tx_cfg[idx].bit_format);
  4394. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  4395. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  4396. break;
  4397. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4398. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4399. SNDRV_PCM_FORMAT_S32_LE);
  4400. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  4401. channels->min = channels->max = msm_vi_feed_tx_ch;
  4402. break;
  4403. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  4404. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4405. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  4406. rate->min = rate->max =
  4407. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  4408. channels->min = channels->max =
  4409. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  4410. break;
  4411. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  4412. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4413. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  4414. rate->min = rate->max =
  4415. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  4416. channels->min = channels->max =
  4417. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  4418. break;
  4419. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  4420. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4421. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  4422. rate->min = rate->max =
  4423. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  4424. channels->min = channels->max =
  4425. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  4426. break;
  4427. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  4428. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4429. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  4430. rate->min = rate->max =
  4431. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  4432. channels->min = channels->max =
  4433. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  4434. break;
  4435. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  4436. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4437. afe_lb_tx_cfg.bit_format);
  4438. rate->min = rate->max = afe_lb_tx_cfg.sample_rate;
  4439. channels->min = channels->max = afe_lb_tx_cfg.channels;
  4440. break;
  4441. default:
  4442. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  4443. break;
  4444. }
  4445. return rc;
  4446. }
  4447. static int msm_afe_set_config(struct snd_soc_component *component)
  4448. {
  4449. int ret = 0;
  4450. void *config_data = NULL;
  4451. if (!msm_codec_fn.get_afe_config_fn) {
  4452. dev_err(component->dev, "%s: codec get afe config not init'ed\n",
  4453. __func__);
  4454. return -EINVAL;
  4455. }
  4456. config_data = msm_codec_fn.get_afe_config_fn(component,
  4457. AFE_CDC_REGISTERS_CONFIG);
  4458. if (config_data) {
  4459. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  4460. if (ret) {
  4461. dev_err(component->dev,
  4462. "%s: Failed to set codec registers config %d\n",
  4463. __func__, ret);
  4464. return ret;
  4465. }
  4466. }
  4467. config_data = msm_codec_fn.get_afe_config_fn(component,
  4468. AFE_CDC_REGISTER_PAGE_CONFIG);
  4469. if (config_data) {
  4470. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  4471. 0);
  4472. if (ret)
  4473. dev_err(component->dev,
  4474. "%s: Failed to set cdc register page config\n",
  4475. __func__);
  4476. }
  4477. config_data = msm_codec_fn.get_afe_config_fn(component,
  4478. AFE_SLIMBUS_SLAVE_CONFIG);
  4479. if (config_data) {
  4480. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  4481. if (ret) {
  4482. dev_err(component->dev,
  4483. "%s: Failed to set slimbus slave config %d\n",
  4484. __func__, ret);
  4485. return ret;
  4486. }
  4487. }
  4488. return 0;
  4489. }
  4490. static void msm_afe_clear_config(void)
  4491. {
  4492. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  4493. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  4494. }
  4495. static int msm_adsp_power_up_config(struct snd_soc_component *component,
  4496. struct snd_card *card)
  4497. {
  4498. int ret = 0;
  4499. unsigned long timeout;
  4500. int adsp_ready = 0;
  4501. bool snd_card_online = 0;
  4502. timeout = jiffies +
  4503. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  4504. do {
  4505. if (!snd_card_online) {
  4506. snd_card_online = snd_card_is_online_state(card);
  4507. pr_debug("%s: Sound card is %s\n", __func__,
  4508. snd_card_online ? "Online" : "Offline");
  4509. }
  4510. if (!adsp_ready) {
  4511. adsp_ready = q6core_is_adsp_ready();
  4512. pr_debug("%s: ADSP Audio is %s\n", __func__,
  4513. adsp_ready ? "ready" : "not ready");
  4514. }
  4515. if (snd_card_online && adsp_ready)
  4516. break;
  4517. /*
  4518. * Sound card/ADSP will be coming up after subsystem restart and
  4519. * it might not be fully up when the control reaches
  4520. * here. So, wait for 50msec before checking ADSP state
  4521. */
  4522. msleep(50);
  4523. } while (time_after(timeout, jiffies));
  4524. if (!snd_card_online || !adsp_ready) {
  4525. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  4526. __func__,
  4527. snd_card_online ? "Online" : "Offline",
  4528. adsp_ready ? "ready" : "not ready");
  4529. ret = -ETIMEDOUT;
  4530. goto err;
  4531. }
  4532. ret = msm_afe_set_config(component);
  4533. if (ret)
  4534. pr_err("%s: Failed to set AFE config. err %d\n",
  4535. __func__, ret);
  4536. return 0;
  4537. err:
  4538. return ret;
  4539. }
  4540. static int qcs405_notifier_service_cb(struct notifier_block *this,
  4541. unsigned long opcode, void *ptr)
  4542. {
  4543. int ret;
  4544. struct snd_soc_card *card = NULL;
  4545. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  4546. struct snd_soc_pcm_runtime *rtd;
  4547. struct snd_soc_dai *codec_dai;
  4548. struct snd_soc_component *component;
  4549. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  4550. switch (opcode) {
  4551. case AUDIO_NOTIFIER_SERVICE_DOWN:
  4552. /*
  4553. * Use flag to ignore initial boot notifications
  4554. * On initial boot msm_adsp_power_up_config is
  4555. * called on init. There is no need to clear
  4556. * and set the config again on initial boot.
  4557. */
  4558. if (is_initial_boot)
  4559. break;
  4560. msm_afe_clear_config();
  4561. break;
  4562. case AUDIO_NOTIFIER_SERVICE_UP:
  4563. if (is_initial_boot) {
  4564. is_initial_boot = false;
  4565. break;
  4566. }
  4567. if (!spdev)
  4568. return -EINVAL;
  4569. card = platform_get_drvdata(spdev);
  4570. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  4571. if (!rtd) {
  4572. dev_err(card->dev,
  4573. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  4574. __func__, be_dl_name);
  4575. ret = -EINVAL;
  4576. goto err;
  4577. }
  4578. codec_dai = rtd->codec_dai;
  4579. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec"))
  4580. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4581. ret = msm_adsp_power_up_config(component, card->snd_card);
  4582. if (ret < 0) {
  4583. dev_err(card->dev,
  4584. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  4585. __func__, ret);
  4586. goto err;
  4587. }
  4588. break;
  4589. default:
  4590. break;
  4591. }
  4592. err:
  4593. return NOTIFY_OK;
  4594. }
  4595. static struct notifier_block service_nb = {
  4596. .notifier_call = qcs405_notifier_service_cb,
  4597. .priority = -INT_MAX,
  4598. };
  4599. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4600. {
  4601. int ret = 0;
  4602. void *config_data;
  4603. struct snd_soc_component *component;
  4604. struct snd_soc_dapm_context *dapm;
  4605. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4606. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4607. struct snd_card *card;
  4608. struct msm_asoc_mach_data *pdata =
  4609. snd_soc_card_get_drvdata(rtd->card);
  4610. /*
  4611. * Codec SLIMBUS configuration
  4612. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4613. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4614. * TX14, TX15, TX16
  4615. */
  4616. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4617. 151, 152, 153, 154, 155, 156};
  4618. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4619. 134, 135, 136, 137, 138, 139,
  4620. 140, 141, 142, 143};
  4621. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4622. rtd->pmdown_time = 0;
  4623. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) {
  4624. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4625. dapm = snd_soc_component_get_dapm(component);
  4626. }
  4627. ret = snd_soc_add_component_controls(component, msm_snd_sb_controls,
  4628. ARRAY_SIZE(msm_snd_sb_controls));
  4629. if (ret < 0) {
  4630. pr_err("%s: add_codec_controls failed, err %d\n",
  4631. __func__, ret);
  4632. return ret;
  4633. }
  4634. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4635. ARRAY_SIZE(msm_dapm_widgets));
  4636. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4637. ARRAY_SIZE(wcd_audio_paths));
  4638. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4639. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4640. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4641. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4642. snd_soc_dapm_sync(dapm);
  4643. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4644. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4645. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4646. ret = msm_adsp_power_up_config(component, rtd->card->snd_card);
  4647. if (ret) {
  4648. dev_err(component->dev, "%s: Failed to set AFE config %d\n",
  4649. __func__, ret);
  4650. goto err;
  4651. }
  4652. config_data = msm_codec_fn.get_afe_config_fn(component,
  4653. AFE_AANC_VERSION);
  4654. if (config_data) {
  4655. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4656. if (ret) {
  4657. dev_err(component->dev, "%s: Failed to set aanc version %d\n",
  4658. __func__, ret);
  4659. goto err;
  4660. }
  4661. }
  4662. card = rtd->card->snd_card;
  4663. if (!pdata->codec_root)
  4664. pdata->codec_root = snd_info_create_subdir(card->module,
  4665. "codecs", card->proc_root);
  4666. if (!pdata->codec_root) {
  4667. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4668. __func__);
  4669. ret = 0;
  4670. goto err;
  4671. }
  4672. tasha_codec_info_create_codec_entry(pdata->codec_root, component);
  4673. codec_reg_done = true;
  4674. return 0;
  4675. err:
  4676. return ret;
  4677. }
  4678. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4679. {
  4680. int ret = 0;
  4681. struct snd_soc_component *component;
  4682. struct snd_soc_dapm_context *dapm;
  4683. struct snd_card *card;
  4684. struct msm_asoc_mach_data *pdata =
  4685. snd_soc_card_get_drvdata(rtd->card);
  4686. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4687. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4688. if (!component) {
  4689. pr_err("%s: component is NULL\n", __func__);
  4690. return -EINVAL;
  4691. }
  4692. dapm = snd_soc_component_get_dapm(component);
  4693. ret = snd_soc_add_component_controls(component, msm_snd_va_controls,
  4694. ARRAY_SIZE(msm_snd_va_controls));
  4695. if (ret < 0) {
  4696. dev_err(component->dev, "%s: add_component_controls for va failed, err %d\n",
  4697. __func__, ret);
  4698. return ret;
  4699. }
  4700. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4701. ARRAY_SIZE(msm_va_dapm_widgets));
  4702. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4703. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4704. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4705. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4706. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4707. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4708. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4709. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4710. snd_soc_dapm_sync(dapm);
  4711. card = rtd->card->snd_card;
  4712. if (!pdata->codec_root)
  4713. pdata->codec_root = snd_info_create_subdir(card->module,
  4714. "codecs", card->proc_root);
  4715. if (!pdata->codec_root) {
  4716. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4717. __func__);
  4718. ret = 0;
  4719. goto done;
  4720. }
  4721. bolero_info_create_codec_entry(pdata->codec_root, component);
  4722. done:
  4723. return ret;
  4724. }
  4725. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4726. {
  4727. int ret = 0;
  4728. struct snd_soc_component *component = NULL;
  4729. struct snd_soc_dapm_context *dapm = NULL;
  4730. struct snd_soc_component *aux_comp = NULL;
  4731. struct snd_card *card = NULL;
  4732. struct msm_asoc_mach_data *pdata =
  4733. snd_soc_card_get_drvdata(rtd->card);
  4734. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4735. if (!component) {
  4736. pr_err("%s: component is NULL\n", __func__);
  4737. return -EINVAL;
  4738. }
  4739. dapm = snd_soc_component_get_dapm(component);
  4740. ret = snd_soc_add_component_controls(component, msm_snd_wsa_controls,
  4741. ARRAY_SIZE(msm_snd_wsa_controls));
  4742. if (ret < 0) {
  4743. dev_err(component->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4744. __func__, ret);
  4745. return ret;
  4746. }
  4747. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4748. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4749. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4750. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4751. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4752. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4753. snd_soc_dapm_sync(dapm);
  4754. /*
  4755. * Send speaker configuration only for WSA8810.
  4756. * Default configuration is for WSA8815.
  4757. */
  4758. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4759. __func__, rtd->card->num_aux_devs);
  4760. if (rtd->card->num_aux_devs &&
  4761. !list_empty(&rtd->card->component_dev_list)) {
  4762. aux_comp = list_first_entry(
  4763. &rtd->card->component_dev_list,
  4764. struct snd_soc_component,
  4765. card_aux_list);
  4766. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4767. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4768. wsa_macro_set_spkr_mode(component,
  4769. WSA_MACRO_SPKR_MODE_1);
  4770. wsa_macro_set_spkr_gain_offset(component,
  4771. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4772. }
  4773. }
  4774. card = rtd->card->snd_card;
  4775. if (!pdata->codec_root)
  4776. pdata->codec_root = snd_info_create_subdir(card->module,
  4777. "codecs", card->proc_root);
  4778. if (!pdata->codec_root) {
  4779. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  4780. __func__);
  4781. ret = 0;
  4782. goto done;
  4783. }
  4784. bolero_info_create_codec_entry(pdata->codec_root, component);
  4785. done:
  4786. return ret;
  4787. }
  4788. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4789. {
  4790. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4791. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161, 162};
  4792. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4793. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4794. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4795. }
  4796. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4797. struct snd_pcm_hw_params *params)
  4798. {
  4799. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4800. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4801. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4802. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4803. int ret = 0;
  4804. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4805. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4806. u32 user_set_tx_ch = 0;
  4807. u32 rx_ch_count;
  4808. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4809. ret = snd_soc_dai_get_channel_map(codec_dai,
  4810. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4811. if (ret < 0) {
  4812. pr_err("%s: failed to get codec chan map, err:%d\n",
  4813. __func__, ret);
  4814. goto err;
  4815. }
  4816. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4817. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4818. slim_rx_cfg[5].channels);
  4819. rx_ch_count = slim_rx_cfg[5].channels;
  4820. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4821. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4822. slim_rx_cfg[2].channels);
  4823. rx_ch_count = slim_rx_cfg[2].channels;
  4824. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4825. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4826. slim_rx_cfg[6].channels);
  4827. rx_ch_count = slim_rx_cfg[6].channels;
  4828. } else {
  4829. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4830. slim_rx_cfg[0].channels);
  4831. rx_ch_count = slim_rx_cfg[0].channels;
  4832. }
  4833. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4834. rx_ch_count, rx_ch);
  4835. if (ret < 0) {
  4836. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4837. __func__, ret);
  4838. goto err;
  4839. }
  4840. } else {
  4841. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4842. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4843. ret = snd_soc_dai_get_channel_map(codec_dai,
  4844. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4845. if (ret < 0) {
  4846. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4847. __func__, ret);
  4848. goto err;
  4849. }
  4850. /* For <codec>_tx1 case */
  4851. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4852. user_set_tx_ch = slim_tx_cfg[0].channels;
  4853. /* For <codec>_tx3 case */
  4854. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4855. user_set_tx_ch = slim_tx_cfg[1].channels;
  4856. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4857. user_set_tx_ch = msm_vi_feed_tx_ch;
  4858. else
  4859. user_set_tx_ch = tx_ch_cnt;
  4860. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4861. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4862. tx_ch_cnt, dai_link->id);
  4863. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4864. user_set_tx_ch, tx_ch, 0, 0);
  4865. if (ret < 0)
  4866. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4867. __func__, ret);
  4868. }
  4869. err:
  4870. return ret;
  4871. }
  4872. static int msm_snd_auxpcm_startup(struct snd_pcm_substream *substream)
  4873. {
  4874. int ret = 0;
  4875. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4876. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4877. ret = qcs405_send_island_vad_config(dai_link->id);
  4878. if (ret) {
  4879. pr_err("%s: send island/vad cfg failed, err = %d\n",
  4880. __func__, ret);
  4881. }
  4882. return ret;
  4883. }
  4884. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  4885. {
  4886. int ret = 0;
  4887. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4888. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4889. ret = qcs405_send_island_vad_config(dai_link->id);
  4890. if (ret) {
  4891. pr_err("%s: send island/vad cfg failed, err = %d\n",
  4892. __func__, ret);
  4893. }
  4894. return ret;
  4895. }
  4896. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4897. struct snd_pcm_hw_params *params)
  4898. {
  4899. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4900. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4901. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4902. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4903. int ret = 0;
  4904. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4905. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4906. u32 user_set_tx_ch = 0;
  4907. u32 user_set_rx_ch = 0;
  4908. u32 ch_id;
  4909. ret = snd_soc_dai_get_channel_map(codec_dai,
  4910. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4911. &rx_ch_cdc_dma);
  4912. if (ret < 0) {
  4913. pr_err("%s: failed to get codec chan map, err:%d\n",
  4914. __func__, ret);
  4915. goto err;
  4916. }
  4917. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4918. switch (dai_link->id) {
  4919. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4920. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4921. {
  4922. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4923. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4924. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4925. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4926. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4927. user_set_rx_ch, &rx_ch_cdc_dma);
  4928. if (ret < 0) {
  4929. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4930. __func__, ret);
  4931. goto err;
  4932. }
  4933. }
  4934. break;
  4935. }
  4936. } else {
  4937. switch (dai_link->id) {
  4938. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4939. {
  4940. user_set_tx_ch = msm_vi_feed_tx_ch;
  4941. }
  4942. break;
  4943. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4944. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4945. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4946. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4947. {
  4948. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4949. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4950. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4951. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4952. }
  4953. break;
  4954. }
  4955. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4956. &tx_ch_cdc_dma, 0, 0);
  4957. if (ret < 0) {
  4958. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4959. __func__, ret);
  4960. goto err;
  4961. }
  4962. }
  4963. err:
  4964. return ret;
  4965. }
  4966. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4967. struct snd_pcm_hw_params *params)
  4968. {
  4969. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4970. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4971. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4972. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4973. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4974. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4975. int ret;
  4976. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4977. codec_dai->name, codec_dai->id);
  4978. ret = snd_soc_dai_get_channel_map(codec_dai,
  4979. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4980. if (ret) {
  4981. dev_err(rtd->dev,
  4982. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4983. __func__, ret);
  4984. goto err;
  4985. }
  4986. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4987. __func__, tx_ch_cnt, dai_link->id);
  4988. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4989. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4990. if (ret)
  4991. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4992. __func__, ret);
  4993. err:
  4994. return ret;
  4995. }
  4996. static int msm_get_port_id(int be_id)
  4997. {
  4998. int afe_port_id;
  4999. switch (be_id) {
  5000. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  5001. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  5002. break;
  5003. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  5004. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  5005. break;
  5006. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  5007. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  5008. break;
  5009. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  5010. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  5011. break;
  5012. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  5013. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  5014. break;
  5015. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  5016. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  5017. break;
  5018. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  5019. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  5020. break;
  5021. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  5022. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  5023. break;
  5024. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  5025. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  5026. break;
  5027. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  5028. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  5029. break;
  5030. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  5031. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  5032. break;
  5033. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  5034. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  5035. break;
  5036. default:
  5037. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  5038. afe_port_id = -EINVAL;
  5039. }
  5040. return afe_port_id;
  5041. }
  5042. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  5043. {
  5044. u32 bit_per_sample;
  5045. switch (bit_format) {
  5046. case SNDRV_PCM_FORMAT_S32_LE:
  5047. case SNDRV_PCM_FORMAT_S24_3LE:
  5048. case SNDRV_PCM_FORMAT_S24_LE:
  5049. bit_per_sample = 32;
  5050. break;
  5051. case SNDRV_PCM_FORMAT_S16_LE:
  5052. default:
  5053. bit_per_sample = 16;
  5054. break;
  5055. }
  5056. return bit_per_sample;
  5057. }
  5058. static void update_mi2s_clk_val(int dai_id, int stream)
  5059. {
  5060. u32 bit_per_sample;
  5061. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  5062. bit_per_sample =
  5063. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  5064. mi2s_clk[dai_id].clk_freq_in_hz =
  5065. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  5066. } else {
  5067. bit_per_sample =
  5068. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  5069. mi2s_clk[dai_id].clk_freq_in_hz =
  5070. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  5071. }
  5072. }
  5073. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  5074. {
  5075. int ret = 0;
  5076. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5077. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5078. int port_id = 0;
  5079. int index = cpu_dai->id;
  5080. port_id = msm_get_port_id(rtd->dai_link->id);
  5081. if (port_id < 0) {
  5082. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  5083. ret = port_id;
  5084. goto err;
  5085. }
  5086. if (enable) {
  5087. update_mi2s_clk_val(index, substream->stream);
  5088. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  5089. mi2s_clk[index].clk_freq_in_hz);
  5090. }
  5091. mi2s_clk[index].enable = enable;
  5092. ret = afe_set_lpass_clock_v2(port_id,
  5093. &mi2s_clk[index]);
  5094. if (ret < 0) {
  5095. dev_err(rtd->card->dev,
  5096. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  5097. __func__, port_id, ret);
  5098. goto err;
  5099. }
  5100. err:
  5101. return ret;
  5102. }
  5103. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  5104. struct snd_pcm_hw_params *params)
  5105. {
  5106. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5107. struct snd_interval *rate = hw_param_interval(params,
  5108. SNDRV_PCM_HW_PARAM_RATE);
  5109. struct snd_interval *channels = hw_param_interval(params,
  5110. SNDRV_PCM_HW_PARAM_CHANNELS);
  5111. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  5112. channels->min = channels->max =
  5113. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  5114. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  5115. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  5116. rate->min = rate->max =
  5117. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  5118. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  5119. channels->min = channels->max =
  5120. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  5121. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  5122. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  5123. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  5124. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  5125. channels->min = channels->max =
  5126. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  5127. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  5128. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  5129. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  5130. } else {
  5131. pr_err("%s: dai id 0x%x not supported\n",
  5132. __func__, cpu_dai->id);
  5133. return -EINVAL;
  5134. }
  5135. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  5136. __func__, cpu_dai->id, channels->max, rate->max,
  5137. params_format(params));
  5138. return 0;
  5139. }
  5140. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  5141. struct snd_pcm_hw_params *params)
  5142. {
  5143. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5144. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5145. int ret = 0;
  5146. int slot_width = 32;
  5147. int channels, slots = 8;
  5148. unsigned int slot_mask, rate, clk_freq;
  5149. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  5150. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  5151. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  5152. switch (cpu_dai->id) {
  5153. case AFE_PORT_ID_PRIMARY_TDM_RX:
  5154. channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  5155. break;
  5156. case AFE_PORT_ID_SECONDARY_TDM_RX:
  5157. channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  5158. break;
  5159. case AFE_PORT_ID_TERTIARY_TDM_RX:
  5160. channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  5161. break;
  5162. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  5163. channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  5164. break;
  5165. case AFE_PORT_ID_QUINARY_TDM_RX:
  5166. channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  5167. break;
  5168. case AFE_PORT_ID_PRIMARY_TDM_TX:
  5169. channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  5170. break;
  5171. case AFE_PORT_ID_SECONDARY_TDM_TX:
  5172. channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  5173. break;
  5174. case AFE_PORT_ID_TERTIARY_TDM_TX:
  5175. channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  5176. break;
  5177. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  5178. channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  5179. break;
  5180. case AFE_PORT_ID_QUINARY_TDM_TX:
  5181. channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  5182. break;
  5183. default:
  5184. pr_err("%s: dai id 0x%x not supported\n",
  5185. __func__, cpu_dai->id);
  5186. return -EINVAL;
  5187. }
  5188. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  5189. /*2 slot config - bits 0 and 1 set for the first two slots */
  5190. slot_mask = 0x0000FFFF >> (16-channels);
  5191. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  5192. __func__, slot_width, slots);
  5193. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  5194. slots, slot_width);
  5195. if (ret < 0) {
  5196. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  5197. __func__, ret);
  5198. goto end;
  5199. }
  5200. ret = snd_soc_dai_set_channel_map(cpu_dai,
  5201. 0, NULL, channels, slot_offset);
  5202. if (ret < 0) {
  5203. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  5204. __func__, ret);
  5205. goto end;
  5206. }
  5207. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  5208. /*2 slot config - bits 0 and 1 set for the first two slots */
  5209. slot_mask = 0x0000FFFF >> (16-channels);
  5210. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  5211. __func__, slot_width, slots);
  5212. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  5213. slots, slot_width);
  5214. if (ret < 0) {
  5215. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  5216. __func__, ret);
  5217. goto end;
  5218. }
  5219. ret = snd_soc_dai_set_channel_map(cpu_dai,
  5220. channels, slot_offset, 0, NULL);
  5221. if (ret < 0) {
  5222. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  5223. __func__, ret);
  5224. goto end;
  5225. }
  5226. } else {
  5227. ret = -EINVAL;
  5228. pr_err("%s: invalid use case, err:%d\n",
  5229. __func__, ret);
  5230. goto end;
  5231. }
  5232. rate = params_rate(params);
  5233. clk_freq = rate * slot_width * slots;
  5234. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  5235. if (ret < 0)
  5236. pr_err("%s: failed to set tdm clk, err:%d\n",
  5237. __func__, ret);
  5238. end:
  5239. return ret;
  5240. }
  5241. static int msm_get_tdm_mode(u32 port_id)
  5242. {
  5243. u32 tdm_mode;
  5244. switch (port_id) {
  5245. case AFE_PORT_ID_PRIMARY_TDM_RX:
  5246. case AFE_PORT_ID_PRIMARY_TDM_TX:
  5247. tdm_mode = TDM_PRI;
  5248. break;
  5249. case AFE_PORT_ID_SECONDARY_TDM_RX:
  5250. case AFE_PORT_ID_SECONDARY_TDM_TX:
  5251. tdm_mode = TDM_SEC;
  5252. break;
  5253. case AFE_PORT_ID_TERTIARY_TDM_RX:
  5254. case AFE_PORT_ID_TERTIARY_TDM_TX:
  5255. tdm_mode = TDM_TERT;
  5256. break;
  5257. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  5258. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  5259. tdm_mode = TDM_QUAT;
  5260. break;
  5261. case AFE_PORT_ID_QUINARY_TDM_RX:
  5262. case AFE_PORT_ID_QUINARY_TDM_TX:
  5263. tdm_mode = TDM_QUIN;
  5264. break;
  5265. default:
  5266. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  5267. tdm_mode = -EINVAL;
  5268. }
  5269. return tdm_mode;
  5270. }
  5271. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  5272. {
  5273. int ret = 0;
  5274. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5275. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5276. struct snd_soc_card *card = rtd->card;
  5277. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5278. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5279. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  5280. if (tdm_mode >= TDM_INTERFACE_MAX) {
  5281. ret = -EINVAL;
  5282. pr_err("%s: Invalid TDM interface %d\n",
  5283. __func__, ret);
  5284. return ret;
  5285. }
  5286. if (pdata->mi2s_gpio_p[tdm_mode]) {
  5287. ret = msm_cdc_pinctrl_select_active_state(
  5288. pdata->mi2s_gpio_p[tdm_mode]);
  5289. if (ret)
  5290. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  5291. __func__, ret);
  5292. }
  5293. /* Enable Mic bias for TDM Mics */
  5294. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  5295. if (pdata->tdm_micb_supply) {
  5296. ret = regulator_set_voltage(pdata->tdm_micb_supply,
  5297. pdata->tdm_micb_voltage,
  5298. pdata->tdm_micb_voltage);
  5299. if (ret) {
  5300. pr_err("%s: Setting voltage failed, err = %d\n",
  5301. __func__, ret);
  5302. return ret;
  5303. }
  5304. ret = regulator_set_load(pdata->tdm_micb_supply,
  5305. pdata->tdm_micb_current);
  5306. if (ret) {
  5307. pr_err("%s: Setting current failed, err = %d\n",
  5308. __func__, ret);
  5309. return ret;
  5310. }
  5311. ret = regulator_enable(pdata->tdm_micb_supply);
  5312. if (ret) {
  5313. pr_err("%s: regulator enable failed, err = %d\n",
  5314. __func__, ret);
  5315. return ret;
  5316. }
  5317. }
  5318. }
  5319. ret = qcs405_send_island_vad_config(dai_link->id);
  5320. if (ret) {
  5321. pr_err("%s: send island/vad cfg failed, err = %d\n",
  5322. __func__, ret);
  5323. return ret;
  5324. }
  5325. return ret;
  5326. }
  5327. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  5328. {
  5329. int ret = 0;
  5330. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5331. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5332. struct snd_soc_card *card = rtd->card;
  5333. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5334. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  5335. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  5336. if (pdata->tdm_micb_supply) {
  5337. ret = regulator_disable(pdata->tdm_micb_supply);
  5338. if (ret)
  5339. pr_err("%s: regulator disable failed, err = %d\n",
  5340. __func__, ret);
  5341. regulator_set_voltage(pdata->tdm_micb_supply, 0,
  5342. pdata->tdm_micb_voltage);
  5343. regulator_set_load(pdata->tdm_micb_supply, 0);
  5344. }
  5345. }
  5346. if (pdata->mi2s_gpio_p[tdm_mode]) {
  5347. ret = msm_cdc_pinctrl_select_sleep_state(
  5348. pdata->mi2s_gpio_p[tdm_mode]);
  5349. if (ret)
  5350. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  5351. __func__, ret);
  5352. }
  5353. }
  5354. static struct snd_soc_ops qcs405_tdm_be_ops = {
  5355. .hw_params = qcs405_tdm_snd_hw_params,
  5356. .startup = qcs405_tdm_snd_startup,
  5357. .shutdown = qcs405_tdm_snd_shutdown
  5358. };
  5359. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  5360. {
  5361. cpumask_t mask;
  5362. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  5363. pm_qos_remove_request(&substream->latency_pm_qos_req);
  5364. cpumask_clear(&mask);
  5365. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  5366. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  5367. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  5368. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  5369. pm_qos_add_request(&substream->latency_pm_qos_req,
  5370. PM_QOS_CPU_DMA_LATENCY,
  5371. MSM_LL_QOS_VALUE);
  5372. return 0;
  5373. }
  5374. static struct snd_soc_ops msm_fe_qos_ops = {
  5375. .prepare = msm_fe_qos_prepare,
  5376. };
  5377. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  5378. {
  5379. int ret = 0;
  5380. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5381. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5382. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5383. int index = cpu_dai->id;
  5384. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  5385. struct snd_soc_card *card = rtd->card;
  5386. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5387. dev_dbg(rtd->card->dev,
  5388. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5389. __func__, substream->name, substream->stream,
  5390. cpu_dai->name, cpu_dai->id);
  5391. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5392. ret = -EINVAL;
  5393. dev_err(rtd->card->dev,
  5394. "%s: CPU DAI id (%d) out of range\n",
  5395. __func__, cpu_dai->id);
  5396. goto err;
  5397. }
  5398. /*
  5399. * Mutex protection in case the same MI2S
  5400. * interface using for both TX and RX so
  5401. * that the same clock won't be enable twice.
  5402. */
  5403. mutex_lock(&mi2s_intf_conf[index].lock);
  5404. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  5405. /* Check if msm needs to provide the clock to the interface */
  5406. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  5407. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  5408. fmt = SND_SOC_DAIFMT_CBM_CFM;
  5409. }
  5410. ret = msm_mi2s_set_sclk(substream, true);
  5411. if (ret < 0) {
  5412. dev_err(rtd->card->dev,
  5413. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  5414. __func__, ret);
  5415. goto clean_up;
  5416. }
  5417. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  5418. if (ret < 0) {
  5419. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  5420. __func__, index, ret);
  5421. goto clk_off;
  5422. }
  5423. if (pdata->mi2s_gpio_p[index])
  5424. msm_cdc_pinctrl_select_active_state(
  5425. pdata->mi2s_gpio_p[index]);
  5426. }
  5427. ret = qcs405_send_island_vad_config(dai_link->id);
  5428. if (ret) {
  5429. pr_err("%s: send island/vad cfg failed, err = %d\n",
  5430. __func__, ret);
  5431. return ret;
  5432. }
  5433. clk_off:
  5434. if (ret < 0)
  5435. msm_mi2s_set_sclk(substream, false);
  5436. clean_up:
  5437. if (ret < 0)
  5438. mi2s_intf_conf[index].ref_cnt--;
  5439. mutex_unlock(&mi2s_intf_conf[index].lock);
  5440. err:
  5441. return ret;
  5442. }
  5443. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  5444. {
  5445. int ret;
  5446. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5447. int index = rtd->cpu_dai->id;
  5448. struct snd_soc_card *card = rtd->card;
  5449. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5450. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5451. substream->name, substream->stream);
  5452. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5453. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  5454. return;
  5455. }
  5456. mutex_lock(&mi2s_intf_conf[index].lock);
  5457. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  5458. if (pdata->mi2s_gpio_p[index])
  5459. msm_cdc_pinctrl_select_sleep_state(
  5460. pdata->mi2s_gpio_p[index]);
  5461. ret = msm_mi2s_set_sclk(substream, false);
  5462. if (ret < 0)
  5463. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  5464. __func__, index, ret);
  5465. }
  5466. mutex_unlock(&mi2s_intf_conf[index].lock);
  5467. }
  5468. static int msm_meta_mi2s_set_sclk(struct snd_pcm_substream *substream,
  5469. int member_id, bool enable)
  5470. {
  5471. int ret = 0;
  5472. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5473. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5474. int be_id = 0;
  5475. int port_id = 0;
  5476. int index = cpu_dai->id;
  5477. u32 bit_per_sample = 0;
  5478. switch (member_id) {
  5479. case PRIM_MI2S:
  5480. be_id = MSM_BACKEND_DAI_PRI_MI2S_RX;
  5481. break;
  5482. case SEC_MI2S:
  5483. be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX;
  5484. break;
  5485. case TERT_MI2S:
  5486. be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX;
  5487. break;
  5488. case QUAT_MI2S:
  5489. be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX;
  5490. break;
  5491. default:
  5492. dev_err(rtd->card->dev, "%s: Invalid member_id\n", __func__);
  5493. ret = -EINVAL;
  5494. goto err;
  5495. }
  5496. port_id = msm_get_port_id(be_id);
  5497. if (port_id < 0) {
  5498. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  5499. ret = port_id;
  5500. goto err;
  5501. }
  5502. if (enable) {
  5503. bit_per_sample =
  5504. get_mi2s_bits_per_sample(
  5505. meta_mi2s_rx_cfg[index].bit_format);
  5506. mi2s_clk[member_id].clk_freq_in_hz =
  5507. meta_mi2s_rx_cfg[index].sample_rate * 2 *
  5508. bit_per_sample;
  5509. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  5510. mi2s_clk[member_id].clk_freq_in_hz);
  5511. }
  5512. mi2s_clk[member_id].enable = enable;
  5513. ret = afe_set_lpass_clock_v2(port_id, &mi2s_clk[member_id]);
  5514. if (ret < 0) {
  5515. dev_err(rtd->card->dev,
  5516. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  5517. __func__, port_id, ret);
  5518. goto err;
  5519. }
  5520. err:
  5521. return ret;
  5522. }
  5523. static int msm_meta_mi2s_snd_startup(struct snd_pcm_substream *substream)
  5524. {
  5525. int ret = 0;
  5526. int i = 0;
  5527. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5528. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5529. int index = cpu_dai->id;
  5530. int member_port = 0;
  5531. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  5532. struct snd_soc_card *card = rtd->card;
  5533. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5534. dev_dbg(rtd->card->dev,
  5535. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5536. __func__, substream->name, substream->stream,
  5537. cpu_dai->name, cpu_dai->id);
  5538. if (index < PRIM_META_MI2S || index >= META_MI2S_MAX) {
  5539. ret = -EINVAL;
  5540. dev_err(rtd->card->dev,
  5541. "%s: CPU DAI id (%d) out of range\n",
  5542. __func__, cpu_dai->id);
  5543. goto err;
  5544. }
  5545. for (i = 0; i < meta_mi2s_intf_conf[index].num_member_ports; i++) {
  5546. member_port = meta_mi2s_intf_conf[index].member_port[i];
  5547. if (!mi2s_intf_conf[member_port].msm_is_mi2s_master) {
  5548. mi2s_clk[member_port].clk_id =
  5549. mi2s_ebit_clk[member_port];
  5550. fmt = SND_SOC_DAIFMT_CBM_CFM;
  5551. }
  5552. ret = msm_meta_mi2s_set_sclk(substream, member_port, true);
  5553. if (ret < 0) {
  5554. dev_err(rtd->card->dev,
  5555. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  5556. __func__, ret);
  5557. goto clk_off;
  5558. }
  5559. meta_mi2s_intf_conf[index].clk_enable[i] = true;
  5560. if (i == 0) {
  5561. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  5562. if (ret < 0) {
  5563. pr_err("%s: set fmt cpu dai failed for META_MI2S (%d), err:%d\n",
  5564. __func__, index, ret);
  5565. goto clk_off;
  5566. }
  5567. }
  5568. if (pdata->mi2s_gpio_p[member_port])
  5569. msm_cdc_pinctrl_select_active_state(
  5570. pdata->mi2s_gpio_p[member_port]);
  5571. }
  5572. return 0;
  5573. clk_off:
  5574. for (i = 0; i < meta_mi2s_intf_conf[index].num_member_ports; i++) {
  5575. member_port = meta_mi2s_intf_conf[index].member_port[i];
  5576. if (pdata->mi2s_gpio_p[member_port])
  5577. msm_cdc_pinctrl_select_sleep_state(
  5578. pdata->mi2s_gpio_p[member_port]);
  5579. if (meta_mi2s_intf_conf[index].clk_enable[i]) {
  5580. msm_meta_mi2s_set_sclk(substream, member_port, false);
  5581. meta_mi2s_intf_conf[index].clk_enable[i] = false;
  5582. }
  5583. }
  5584. err:
  5585. return ret;
  5586. }
  5587. static void msm_meta_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  5588. {
  5589. int ret = 0;
  5590. int i = 0;
  5591. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5592. int index = rtd->cpu_dai->id;
  5593. int member_port = 0;
  5594. struct snd_soc_card *card = rtd->card;
  5595. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5596. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5597. substream->name, substream->stream);
  5598. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5599. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  5600. return;
  5601. }
  5602. for (i = 0; i < meta_mi2s_intf_conf[index].num_member_ports; i++) {
  5603. member_port = meta_mi2s_intf_conf[index].member_port[i];
  5604. if (pdata->mi2s_gpio_p[member_port])
  5605. msm_cdc_pinctrl_select_sleep_state(
  5606. pdata->mi2s_gpio_p[member_port]);
  5607. ret = msm_meta_mi2s_set_sclk(substream, member_port, false);
  5608. if (ret < 0)
  5609. pr_err("%s:clock disable failed for META MI2S (%d); ret=%d\n",
  5610. __func__, index, ret);
  5611. }
  5612. }
  5613. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  5614. {
  5615. int ret = 0;
  5616. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5617. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5618. int port_id = cpu_dai->id;
  5619. struct afe_clk_set clk_cfg;
  5620. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  5621. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  5622. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  5623. clk_cfg.enable = enable;
  5624. /* Set core clock (based on sample rate for RX, fixed for TX) */
  5625. switch (port_id) {
  5626. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5627. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  5628. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  5629. clk_cfg.clk_freq_in_hz =
  5630. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5631. break;
  5632. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5633. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  5634. clk_cfg.clk_freq_in_hz =
  5635. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5636. break;
  5637. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  5638. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  5639. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5640. break;
  5641. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  5642. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  5643. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5644. break;
  5645. }
  5646. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5647. if (ret < 0) {
  5648. dev_err(rtd->card->dev,
  5649. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  5650. __func__, port_id, ret);
  5651. goto err;
  5652. }
  5653. /* Set NPL clock for RX in addition */
  5654. switch (port_id) {
  5655. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5656. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  5657. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5658. if (ret < 0) {
  5659. dev_err(rtd->card->dev,
  5660. "%s: afe NPL failed port 0x%x, err:%d\n",
  5661. __func__, port_id, ret);
  5662. goto err;
  5663. }
  5664. break;
  5665. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5666. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  5667. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5668. if (ret < 0) {
  5669. dev_err(rtd->card->dev,
  5670. "%s: afe NPL failed for port 0x%x, err:%d\n",
  5671. __func__, port_id, ret);
  5672. goto err;
  5673. }
  5674. break;
  5675. }
  5676. if (enable) {
  5677. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  5678. clk_cfg.clk_freq_in_hz);
  5679. }
  5680. err:
  5681. return ret;
  5682. }
  5683. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  5684. {
  5685. int ret = 0;
  5686. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5687. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5688. int port_id = cpu_dai->id;
  5689. dev_dbg(rtd->card->dev,
  5690. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5691. __func__, substream->name, substream->stream,
  5692. cpu_dai->name, cpu_dai->id);
  5693. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5694. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5695. ret = -EINVAL;
  5696. dev_err(rtd->card->dev,
  5697. "%s: CPU DAI id (%d) out of range\n",
  5698. __func__, cpu_dai->id);
  5699. goto err;
  5700. }
  5701. ret = msm_spdif_set_clk(substream, true);
  5702. if (ret < 0) {
  5703. dev_err(rtd->card->dev,
  5704. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  5705. __func__, port_id, ret);
  5706. }
  5707. err:
  5708. return ret;
  5709. }
  5710. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  5711. {
  5712. int ret;
  5713. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5714. int port_id = rtd->cpu_dai->id;
  5715. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5716. substream->name, substream->stream);
  5717. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5718. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5719. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  5720. return;
  5721. }
  5722. ret = msm_spdif_set_clk(substream, false);
  5723. if (ret < 0)
  5724. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  5725. __func__, port_id, ret);
  5726. }
  5727. static struct snd_soc_ops msm_mi2s_be_ops = {
  5728. .startup = msm_mi2s_snd_startup,
  5729. .shutdown = msm_mi2s_snd_shutdown,
  5730. };
  5731. static struct snd_soc_ops msm_meta_mi2s_be_ops = {
  5732. .startup = msm_meta_mi2s_snd_startup,
  5733. .shutdown = msm_meta_mi2s_snd_shutdown,
  5734. };
  5735. static struct snd_soc_ops msm_auxpcm_be_ops = {
  5736. .startup = msm_snd_auxpcm_startup,
  5737. };
  5738. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  5739. .startup = msm_snd_cdc_dma_startup,
  5740. .hw_params = msm_snd_cdc_dma_hw_params,
  5741. };
  5742. static struct snd_soc_ops msm_be_ops = {
  5743. .hw_params = msm_snd_hw_params,
  5744. };
  5745. static struct snd_soc_ops msm_wcn_ops = {
  5746. .hw_params = msm_wcn_hw_params,
  5747. };
  5748. static struct snd_soc_ops msm_spdif_be_ops = {
  5749. .startup = msm_spdif_snd_startup,
  5750. .shutdown = msm_spdif_snd_shutdown,
  5751. };
  5752. /* Digital audio interface glue - connects codec <---> CPU */
  5753. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5754. /* FrontEnd DAI Links */
  5755. {
  5756. .name = MSM_DAILINK_NAME(Media1),
  5757. .stream_name = "MultiMedia1",
  5758. .cpu_dai_name = "MultiMedia1",
  5759. .platform_name = "msm-pcm-dsp.0",
  5760. .dynamic = 1,
  5761. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5762. .dpcm_playback = 1,
  5763. .dpcm_capture = 1,
  5764. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5765. SND_SOC_DPCM_TRIGGER_POST},
  5766. .codec_dai_name = "snd-soc-dummy-dai",
  5767. .codec_name = "snd-soc-dummy",
  5768. .ignore_suspend = 1,
  5769. /* this dainlink has playback support */
  5770. .ignore_pmdown_time = 1,
  5771. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5772. },
  5773. {
  5774. .name = MSM_DAILINK_NAME(Media2),
  5775. .stream_name = "MultiMedia2",
  5776. .cpu_dai_name = "MultiMedia2",
  5777. .platform_name = "msm-pcm-dsp.0",
  5778. .dynamic = 1,
  5779. .dpcm_playback = 1,
  5780. .dpcm_capture = 1,
  5781. .codec_dai_name = "snd-soc-dummy-dai",
  5782. .codec_name = "snd-soc-dummy",
  5783. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5784. SND_SOC_DPCM_TRIGGER_POST},
  5785. .ignore_suspend = 1,
  5786. /* this dainlink has playback support */
  5787. .ignore_pmdown_time = 1,
  5788. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5789. },
  5790. {
  5791. .name = "VoiceMMode1",
  5792. .stream_name = "VoiceMMode1",
  5793. .cpu_dai_name = "VoiceMMode1",
  5794. .platform_name = "msm-pcm-voice",
  5795. .dynamic = 1,
  5796. .dpcm_playback = 1,
  5797. .dpcm_capture = 1,
  5798. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5799. SND_SOC_DPCM_TRIGGER_POST},
  5800. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5801. .ignore_suspend = 1,
  5802. .ignore_pmdown_time = 1,
  5803. .codec_dai_name = "snd-soc-dummy-dai",
  5804. .codec_name = "snd-soc-dummy",
  5805. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5806. },
  5807. {
  5808. .name = "MSM VoIP",
  5809. .stream_name = "VoIP",
  5810. .cpu_dai_name = "VoIP",
  5811. .platform_name = "msm-voip-dsp",
  5812. .dynamic = 1,
  5813. .dpcm_playback = 1,
  5814. .dpcm_capture = 1,
  5815. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5816. SND_SOC_DPCM_TRIGGER_POST},
  5817. .codec_dai_name = "snd-soc-dummy-dai",
  5818. .codec_name = "snd-soc-dummy",
  5819. .ignore_suspend = 1,
  5820. /* this dainlink has playback support */
  5821. .ignore_pmdown_time = 1,
  5822. .id = MSM_FRONTEND_DAI_VOIP,
  5823. },
  5824. {
  5825. .name = MSM_DAILINK_NAME(ULL),
  5826. .stream_name = "MultiMedia3",
  5827. .cpu_dai_name = "MultiMedia3",
  5828. .platform_name = "msm-pcm-dsp.2",
  5829. .dynamic = 1,
  5830. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5831. .dpcm_playback = 1,
  5832. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5833. SND_SOC_DPCM_TRIGGER_POST},
  5834. .codec_dai_name = "snd-soc-dummy-dai",
  5835. .codec_name = "snd-soc-dummy",
  5836. .ignore_suspend = 1,
  5837. /* this dainlink has playback support */
  5838. .ignore_pmdown_time = 1,
  5839. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5840. },
  5841. /* Hostless PCM purpose */
  5842. {
  5843. .name = "SLIMBUS_0 Hostless",
  5844. .stream_name = "SLIMBUS_0 Hostless",
  5845. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5846. .platform_name = "msm-pcm-hostless",
  5847. .dynamic = 1,
  5848. .dpcm_playback = 1,
  5849. .dpcm_capture = 1,
  5850. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5851. SND_SOC_DPCM_TRIGGER_POST},
  5852. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5853. .ignore_suspend = 1,
  5854. /* this dailink has playback support */
  5855. .ignore_pmdown_time = 1,
  5856. .codec_dai_name = "snd-soc-dummy-dai",
  5857. .codec_name = "snd-soc-dummy",
  5858. },
  5859. {
  5860. .name = "MSM AFE-PCM RX",
  5861. .stream_name = "AFE-PROXY RX",
  5862. .cpu_dai_name = "msm-dai-q6-dev.241",
  5863. .codec_name = "msm-stub-codec.1",
  5864. .codec_dai_name = "msm-stub-rx",
  5865. .platform_name = "msm-pcm-afe",
  5866. .dpcm_playback = 1,
  5867. .ignore_suspend = 1,
  5868. /* this dainlink has playback support */
  5869. .ignore_pmdown_time = 1,
  5870. },
  5871. {
  5872. .name = "MSM AFE-PCM TX",
  5873. .stream_name = "AFE-PROXY TX",
  5874. .cpu_dai_name = "msm-dai-q6-dev.240",
  5875. .codec_name = "msm-stub-codec.1",
  5876. .codec_dai_name = "msm-stub-tx",
  5877. .platform_name = "msm-pcm-afe",
  5878. .dpcm_capture = 1,
  5879. .ignore_suspend = 1,
  5880. },
  5881. {
  5882. .name = MSM_DAILINK_NAME(Compress1),
  5883. .stream_name = "Compress1",
  5884. .cpu_dai_name = "MultiMedia4",
  5885. .platform_name = "msm-compress-dsp",
  5886. .dynamic = 1,
  5887. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5888. .dpcm_playback = 1,
  5889. .dpcm_capture = 1,
  5890. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5891. SND_SOC_DPCM_TRIGGER_POST},
  5892. .codec_dai_name = "snd-soc-dummy-dai",
  5893. .codec_name = "snd-soc-dummy",
  5894. .ignore_suspend = 1,
  5895. .ignore_pmdown_time = 1,
  5896. /* this dainlink has playback support */
  5897. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5898. },
  5899. {
  5900. .name = "AUXPCM Hostless",
  5901. .stream_name = "AUXPCM Hostless",
  5902. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5903. .platform_name = "msm-pcm-hostless",
  5904. .dynamic = 1,
  5905. .dpcm_playback = 1,
  5906. .dpcm_capture = 1,
  5907. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5908. SND_SOC_DPCM_TRIGGER_POST},
  5909. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5910. .ignore_suspend = 1,
  5911. /* this dainlink has playback support */
  5912. .ignore_pmdown_time = 1,
  5913. .codec_dai_name = "snd-soc-dummy-dai",
  5914. .codec_name = "snd-soc-dummy",
  5915. },
  5916. {
  5917. .name = "SLIMBUS_1 Hostless",
  5918. .stream_name = "SLIMBUS_1 Hostless",
  5919. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5920. .platform_name = "msm-pcm-hostless",
  5921. .dynamic = 1,
  5922. .dpcm_playback = 1,
  5923. .dpcm_capture = 1,
  5924. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5925. SND_SOC_DPCM_TRIGGER_POST},
  5926. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5927. .ignore_suspend = 1,
  5928. /* this dailink has playback support */
  5929. .ignore_pmdown_time = 1,
  5930. .codec_dai_name = "snd-soc-dummy-dai",
  5931. .codec_name = "snd-soc-dummy",
  5932. },
  5933. {
  5934. .name = "SLIMBUS_3 Hostless",
  5935. .stream_name = "SLIMBUS_3 Hostless",
  5936. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5937. .platform_name = "msm-pcm-hostless",
  5938. .dynamic = 1,
  5939. .dpcm_playback = 1,
  5940. .dpcm_capture = 1,
  5941. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5942. SND_SOC_DPCM_TRIGGER_POST},
  5943. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5944. .ignore_suspend = 1,
  5945. /* this dailink has playback support */
  5946. .ignore_pmdown_time = 1,
  5947. .codec_dai_name = "snd-soc-dummy-dai",
  5948. .codec_name = "snd-soc-dummy",
  5949. },
  5950. {
  5951. .name = "SLIMBUS_4 Hostless",
  5952. .stream_name = "SLIMBUS_4 Hostless",
  5953. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5954. .platform_name = "msm-pcm-hostless",
  5955. .dynamic = 1,
  5956. .dpcm_playback = 1,
  5957. .dpcm_capture = 1,
  5958. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5959. SND_SOC_DPCM_TRIGGER_POST},
  5960. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5961. .ignore_suspend = 1,
  5962. /* this dailink has playback support */
  5963. .ignore_pmdown_time = 1,
  5964. .codec_dai_name = "snd-soc-dummy-dai",
  5965. .codec_name = "snd-soc-dummy",
  5966. },
  5967. {
  5968. .name = MSM_DAILINK_NAME(LowLatency),
  5969. .stream_name = "MultiMedia5",
  5970. .cpu_dai_name = "MultiMedia5",
  5971. .platform_name = "msm-pcm-dsp.1",
  5972. .dynamic = 1,
  5973. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5974. .dpcm_playback = 1,
  5975. .dpcm_capture = 1,
  5976. .codec_dai_name = "snd-soc-dummy-dai",
  5977. .codec_name = "snd-soc-dummy",
  5978. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5979. SND_SOC_DPCM_TRIGGER_POST},
  5980. .ignore_suspend = 1,
  5981. /* this dainlink has playback support */
  5982. .ignore_pmdown_time = 1,
  5983. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5984. .ops = &msm_fe_qos_ops,
  5985. },
  5986. {
  5987. .name = "Listen 1 Audio Service",
  5988. .stream_name = "Listen 1 Audio Service",
  5989. .cpu_dai_name = "LSM1",
  5990. .platform_name = "msm-lsm-client",
  5991. .dynamic = 1,
  5992. .dpcm_capture = 1,
  5993. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5994. SND_SOC_DPCM_TRIGGER_POST },
  5995. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5996. .ignore_suspend = 1,
  5997. .codec_dai_name = "snd-soc-dummy-dai",
  5998. .codec_name = "snd-soc-dummy",
  5999. .id = MSM_FRONTEND_DAI_LSM1,
  6000. },
  6001. /* Multiple Tunnel instances */
  6002. {
  6003. .name = MSM_DAILINK_NAME(Compress2),
  6004. .stream_name = "Compress2",
  6005. .cpu_dai_name = "MultiMedia7",
  6006. .platform_name = "msm-compress-dsp",
  6007. .dynamic = 1,
  6008. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6009. .dpcm_playback = 1,
  6010. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6011. SND_SOC_DPCM_TRIGGER_POST},
  6012. .codec_dai_name = "snd-soc-dummy-dai",
  6013. .codec_name = "snd-soc-dummy",
  6014. .ignore_suspend = 1,
  6015. .ignore_pmdown_time = 1,
  6016. /* this dainlink has playback support */
  6017. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  6018. },
  6019. {
  6020. .name = MSM_DAILINK_NAME(MultiMedia10),
  6021. .stream_name = "MultiMedia10",
  6022. .cpu_dai_name = "MultiMedia10",
  6023. .platform_name = "msm-pcm-dsp.1",
  6024. .dynamic = 1,
  6025. .dpcm_playback = 1,
  6026. .dpcm_capture = 1,
  6027. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6028. SND_SOC_DPCM_TRIGGER_POST},
  6029. .codec_dai_name = "snd-soc-dummy-dai",
  6030. .codec_name = "snd-soc-dummy",
  6031. .ignore_suspend = 1,
  6032. .ignore_pmdown_time = 1,
  6033. /* this dainlink has playback support */
  6034. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  6035. },
  6036. {
  6037. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  6038. .stream_name = "MM_NOIRQ",
  6039. .cpu_dai_name = "MultiMedia8",
  6040. .platform_name = "msm-pcm-dsp-noirq",
  6041. .dynamic = 1,
  6042. .dpcm_playback = 1,
  6043. .dpcm_capture = 1,
  6044. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6045. SND_SOC_DPCM_TRIGGER_POST},
  6046. .codec_dai_name = "snd-soc-dummy-dai",
  6047. .codec_name = "snd-soc-dummy",
  6048. .ignore_suspend = 1,
  6049. .ignore_pmdown_time = 1,
  6050. /* this dainlink has playback support */
  6051. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  6052. .ops = &msm_fe_qos_ops,
  6053. },
  6054. /* HDMI Hostless */
  6055. {
  6056. .name = "HDMI_RX_HOSTLESS",
  6057. .stream_name = "HDMI_RX_HOSTLESS",
  6058. .cpu_dai_name = "HDMI_HOSTLESS",
  6059. .platform_name = "msm-pcm-hostless",
  6060. .dynamic = 1,
  6061. .dpcm_playback = 1,
  6062. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6063. SND_SOC_DPCM_TRIGGER_POST},
  6064. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6065. .ignore_suspend = 1,
  6066. .ignore_pmdown_time = 1,
  6067. .codec_dai_name = "snd-soc-dummy-dai",
  6068. .codec_name = "snd-soc-dummy",
  6069. },
  6070. {
  6071. .name = "VoiceMMode2",
  6072. .stream_name = "VoiceMMode2",
  6073. .cpu_dai_name = "VoiceMMode2",
  6074. .platform_name = "msm-pcm-voice",
  6075. .dynamic = 1,
  6076. .dpcm_playback = 1,
  6077. .dpcm_capture = 1,
  6078. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6079. SND_SOC_DPCM_TRIGGER_POST},
  6080. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6081. .ignore_suspend = 1,
  6082. .ignore_pmdown_time = 1,
  6083. .codec_dai_name = "snd-soc-dummy-dai",
  6084. .codec_name = "snd-soc-dummy",
  6085. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  6086. },
  6087. /* LSM FE */
  6088. {
  6089. .name = "Listen 2 Audio Service",
  6090. .stream_name = "Listen 2 Audio Service",
  6091. .cpu_dai_name = "LSM2",
  6092. .platform_name = "msm-lsm-client",
  6093. .dynamic = 1,
  6094. .dpcm_capture = 1,
  6095. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6096. SND_SOC_DPCM_TRIGGER_POST },
  6097. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6098. .ignore_suspend = 1,
  6099. .codec_dai_name = "snd-soc-dummy-dai",
  6100. .codec_name = "snd-soc-dummy",
  6101. .id = MSM_FRONTEND_DAI_LSM2,
  6102. },
  6103. {
  6104. .name = "Listen 3 Audio Service",
  6105. .stream_name = "Listen 3 Audio Service",
  6106. .cpu_dai_name = "LSM3",
  6107. .platform_name = "msm-lsm-client",
  6108. .dynamic = 1,
  6109. .dpcm_capture = 1,
  6110. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6111. SND_SOC_DPCM_TRIGGER_POST },
  6112. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6113. .ignore_suspend = 1,
  6114. .codec_dai_name = "snd-soc-dummy-dai",
  6115. .codec_name = "snd-soc-dummy",
  6116. .id = MSM_FRONTEND_DAI_LSM3,
  6117. },
  6118. {
  6119. .name = "Listen 4 Audio Service",
  6120. .stream_name = "Listen 4 Audio Service",
  6121. .cpu_dai_name = "LSM4",
  6122. .platform_name = "msm-lsm-client",
  6123. .dynamic = 1,
  6124. .dpcm_capture = 1,
  6125. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6126. SND_SOC_DPCM_TRIGGER_POST },
  6127. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6128. .ignore_suspend = 1,
  6129. .codec_dai_name = "snd-soc-dummy-dai",
  6130. .codec_name = "snd-soc-dummy",
  6131. .id = MSM_FRONTEND_DAI_LSM4,
  6132. },
  6133. {
  6134. .name = "Listen 5 Audio Service",
  6135. .stream_name = "Listen 5 Audio Service",
  6136. .cpu_dai_name = "LSM5",
  6137. .platform_name = "msm-lsm-client",
  6138. .dynamic = 1,
  6139. .dpcm_capture = 1,
  6140. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6141. SND_SOC_DPCM_TRIGGER_POST },
  6142. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6143. .ignore_suspend = 1,
  6144. .codec_dai_name = "snd-soc-dummy-dai",
  6145. .codec_name = "snd-soc-dummy",
  6146. .id = MSM_FRONTEND_DAI_LSM5,
  6147. },
  6148. {
  6149. .name = "Listen 6 Audio Service",
  6150. .stream_name = "Listen 6 Audio Service",
  6151. .cpu_dai_name = "LSM6",
  6152. .platform_name = "msm-lsm-client",
  6153. .dynamic = 1,
  6154. .dpcm_capture = 1,
  6155. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6156. SND_SOC_DPCM_TRIGGER_POST },
  6157. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6158. .ignore_suspend = 1,
  6159. .codec_dai_name = "snd-soc-dummy-dai",
  6160. .codec_name = "snd-soc-dummy",
  6161. .id = MSM_FRONTEND_DAI_LSM6,
  6162. },
  6163. {
  6164. .name = "Listen 7 Audio Service",
  6165. .stream_name = "Listen 7 Audio Service",
  6166. .cpu_dai_name = "LSM7",
  6167. .platform_name = "msm-lsm-client",
  6168. .dynamic = 1,
  6169. .dpcm_capture = 1,
  6170. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6171. SND_SOC_DPCM_TRIGGER_POST },
  6172. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6173. .ignore_suspend = 1,
  6174. .codec_dai_name = "snd-soc-dummy-dai",
  6175. .codec_name = "snd-soc-dummy",
  6176. .id = MSM_FRONTEND_DAI_LSM7,
  6177. },
  6178. {
  6179. .name = "Listen 8 Audio Service",
  6180. .stream_name = "Listen 8 Audio Service",
  6181. .cpu_dai_name = "LSM8",
  6182. .platform_name = "msm-lsm-client",
  6183. .dynamic = 1,
  6184. .dpcm_capture = 1,
  6185. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6186. SND_SOC_DPCM_TRIGGER_POST },
  6187. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6188. .ignore_suspend = 1,
  6189. .codec_dai_name = "snd-soc-dummy-dai",
  6190. .codec_name = "snd-soc-dummy",
  6191. .id = MSM_FRONTEND_DAI_LSM8,
  6192. },
  6193. {
  6194. .name = MSM_DAILINK_NAME(Media9),
  6195. .stream_name = "MultiMedia9",
  6196. .cpu_dai_name = "MultiMedia9",
  6197. .platform_name = "msm-pcm-dsp.0",
  6198. .dynamic = 1,
  6199. .dpcm_playback = 1,
  6200. .dpcm_capture = 1,
  6201. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6202. SND_SOC_DPCM_TRIGGER_POST},
  6203. .codec_dai_name = "snd-soc-dummy-dai",
  6204. .codec_name = "snd-soc-dummy",
  6205. .ignore_suspend = 1,
  6206. /* this dainlink has playback support */
  6207. .ignore_pmdown_time = 1,
  6208. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  6209. },
  6210. {
  6211. .name = MSM_DAILINK_NAME(Compress4),
  6212. .stream_name = "Compress4",
  6213. .cpu_dai_name = "MultiMedia11",
  6214. .platform_name = "msm-compress-dsp",
  6215. .dynamic = 1,
  6216. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6217. .dpcm_playback = 1,
  6218. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6219. SND_SOC_DPCM_TRIGGER_POST},
  6220. .codec_dai_name = "snd-soc-dummy-dai",
  6221. .codec_name = "snd-soc-dummy",
  6222. .ignore_suspend = 1,
  6223. .ignore_pmdown_time = 1,
  6224. /* this dainlink has playback support */
  6225. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  6226. },
  6227. {
  6228. .name = MSM_DAILINK_NAME(Compress5),
  6229. .stream_name = "Compress5",
  6230. .cpu_dai_name = "MultiMedia12",
  6231. .platform_name = "msm-compress-dsp",
  6232. .dynamic = 1,
  6233. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6234. .dpcm_playback = 1,
  6235. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6236. SND_SOC_DPCM_TRIGGER_POST},
  6237. .codec_dai_name = "snd-soc-dummy-dai",
  6238. .codec_name = "snd-soc-dummy",
  6239. .ignore_suspend = 1,
  6240. .ignore_pmdown_time = 1,
  6241. /* this dainlink has playback support */
  6242. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  6243. },
  6244. {
  6245. .name = MSM_DAILINK_NAME(Compress6),
  6246. .stream_name = "Compress6",
  6247. .cpu_dai_name = "MultiMedia13",
  6248. .platform_name = "msm-compress-dsp",
  6249. .dynamic = 1,
  6250. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6251. .dpcm_playback = 1,
  6252. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6253. SND_SOC_DPCM_TRIGGER_POST},
  6254. .codec_dai_name = "snd-soc-dummy-dai",
  6255. .codec_name = "snd-soc-dummy",
  6256. .ignore_suspend = 1,
  6257. .ignore_pmdown_time = 1,
  6258. /* this dainlink has playback support */
  6259. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  6260. },
  6261. {
  6262. .name = MSM_DAILINK_NAME(Compress7),
  6263. .stream_name = "Compress7",
  6264. .cpu_dai_name = "MultiMedia14",
  6265. .platform_name = "msm-compress-dsp",
  6266. .dynamic = 1,
  6267. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6268. .dpcm_playback = 1,
  6269. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6270. SND_SOC_DPCM_TRIGGER_POST},
  6271. .codec_dai_name = "snd-soc-dummy-dai",
  6272. .codec_name = "snd-soc-dummy",
  6273. .ignore_suspend = 1,
  6274. .ignore_pmdown_time = 1,
  6275. /* this dainlink has playback support */
  6276. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  6277. },
  6278. {
  6279. .name = MSM_DAILINK_NAME(Compress8),
  6280. .stream_name = "Compress8",
  6281. .cpu_dai_name = "MultiMedia15",
  6282. .platform_name = "msm-compress-dsp",
  6283. .dynamic = 1,
  6284. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6285. .dpcm_playback = 1,
  6286. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6287. SND_SOC_DPCM_TRIGGER_POST},
  6288. .codec_dai_name = "snd-soc-dummy-dai",
  6289. .codec_name = "snd-soc-dummy",
  6290. .ignore_suspend = 1,
  6291. .ignore_pmdown_time = 1,
  6292. /* this dainlink has playback support */
  6293. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  6294. },
  6295. {
  6296. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  6297. .stream_name = "MM_NOIRQ_2",
  6298. .cpu_dai_name = "MultiMedia16",
  6299. .platform_name = "msm-pcm-dsp-noirq",
  6300. .dynamic = 1,
  6301. .dpcm_playback = 1,
  6302. .dpcm_capture = 1,
  6303. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6304. SND_SOC_DPCM_TRIGGER_POST},
  6305. .codec_dai_name = "snd-soc-dummy-dai",
  6306. .codec_name = "snd-soc-dummy",
  6307. .ignore_suspend = 1,
  6308. .ignore_pmdown_time = 1,
  6309. /* this dainlink has playback support */
  6310. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  6311. },
  6312. {
  6313. .name = "SLIMBUS_8 Hostless",
  6314. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  6315. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  6316. .platform_name = "msm-pcm-hostless",
  6317. .dynamic = 1,
  6318. .dpcm_capture = 1,
  6319. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6320. SND_SOC_DPCM_TRIGGER_POST},
  6321. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6322. .ignore_suspend = 1,
  6323. .codec_dai_name = "snd-soc-dummy-dai",
  6324. .codec_name = "snd-soc-dummy",
  6325. },
  6326. /* Hostless PCM purpose */
  6327. {
  6328. .name = "CDC_DMA Hostless",
  6329. .stream_name = "CDC_DMA Hostless",
  6330. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  6331. .platform_name = "msm-pcm-hostless",
  6332. .dynamic = 1,
  6333. .dpcm_playback = 1,
  6334. .dpcm_capture = 1,
  6335. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6336. SND_SOC_DPCM_TRIGGER_POST},
  6337. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6338. .ignore_suspend = 1,
  6339. /* this dailink has playback support */
  6340. .ignore_pmdown_time = 1,
  6341. .codec_dai_name = "snd-soc-dummy-dai",
  6342. .codec_name = "snd-soc-dummy",
  6343. },
  6344. };
  6345. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  6346. {
  6347. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  6348. .stream_name = "WSA CDC DMA0 Capture",
  6349. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  6350. .platform_name = "msm-pcm-hostless",
  6351. .codec_name = "bolero_codec",
  6352. .codec_dai_name = "wsa_macro_vifeedback",
  6353. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  6354. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6355. .ignore_suspend = 1,
  6356. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6357. .ops = &msm_cdc_dma_be_ops,
  6358. },
  6359. };
  6360. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  6361. {
  6362. .name = MSM_DAILINK_NAME(ASM Loopback),
  6363. .stream_name = "MultiMedia6",
  6364. .cpu_dai_name = "MultiMedia6",
  6365. .platform_name = "msm-pcm-loopback",
  6366. .dynamic = 1,
  6367. .dpcm_playback = 1,
  6368. .dpcm_capture = 1,
  6369. .codec_dai_name = "snd-soc-dummy-dai",
  6370. .codec_name = "snd-soc-dummy",
  6371. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6372. SND_SOC_DPCM_TRIGGER_POST},
  6373. .ignore_suspend = 1,
  6374. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6375. .ignore_pmdown_time = 1,
  6376. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  6377. },
  6378. {
  6379. .name = "USB Audio Hostless",
  6380. .stream_name = "USB Audio Hostless",
  6381. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  6382. .platform_name = "msm-pcm-hostless",
  6383. .dynamic = 1,
  6384. .dpcm_playback = 1,
  6385. .dpcm_capture = 1,
  6386. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6387. SND_SOC_DPCM_TRIGGER_POST},
  6388. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6389. .ignore_suspend = 1,
  6390. .ignore_pmdown_time = 1,
  6391. .codec_dai_name = "snd-soc-dummy-dai",
  6392. .codec_name = "snd-soc-dummy",
  6393. },
  6394. {
  6395. .name = "SLIMBUS_7 Hostless",
  6396. .stream_name = "SLIMBUS_7 Hostless",
  6397. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  6398. .platform_name = "msm-pcm-hostless",
  6399. .dynamic = 1,
  6400. .dpcm_capture = 1,
  6401. .dpcm_playback = 1,
  6402. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6403. SND_SOC_DPCM_TRIGGER_POST},
  6404. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6405. .ignore_suspend = 1,
  6406. .ignore_pmdown_time = 1,
  6407. .codec_dai_name = "snd-soc-dummy-dai",
  6408. .codec_name = "snd-soc-dummy",
  6409. },
  6410. {
  6411. .name = MSM_DAILINK_NAME(Compr Capture2),
  6412. .stream_name = "Compr Capture2",
  6413. .cpu_dai_name = "MultiMedia18",
  6414. .platform_name = "msm-compress-dsp",
  6415. .dynamic = 1,
  6416. .dpcm_capture = 1,
  6417. .codec_dai_name = "snd-soc-dummy-dai",
  6418. .codec_name = "snd-soc-dummy",
  6419. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6420. SND_SOC_DPCM_TRIGGER_POST},
  6421. .ignore_pmdown_time = 1,
  6422. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  6423. },
  6424. {
  6425. .name = MSM_DAILINK_NAME(Transcode Loopback Playback),
  6426. .stream_name = "Transcode Loopback Playback",
  6427. .cpu_dai_name = "MultiMedia26",
  6428. .platform_name = "msm-transcode-loopback",
  6429. .dynamic = 1,
  6430. .dpcm_playback = 1,
  6431. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6432. SND_SOC_DPCM_TRIGGER_POST},
  6433. .codec_dai_name = "snd-soc-dummy-dai",
  6434. .codec_name = "snd-soc-dummy",
  6435. .ignore_suspend = 1,
  6436. .ignore_pmdown_time = 1,
  6437. /* this dailink has playback support */
  6438. .id = MSM_FRONTEND_DAI_MULTIMEDIA26,
  6439. },
  6440. {
  6441. .name = MSM_DAILINK_NAME(Transcode Loopback Capture),
  6442. .stream_name = "Transcode Loopback Capture",
  6443. .cpu_dai_name = "MultiMedia27",
  6444. .platform_name = "msm-transcode-loopback",
  6445. .dynamic = 1,
  6446. .dpcm_capture = 1,
  6447. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6448. SND_SOC_DPCM_TRIGGER_POST},
  6449. .codec_dai_name = "snd-soc-dummy-dai",
  6450. .codec_name = "snd-soc-dummy",
  6451. .ignore_suspend = 1,
  6452. .ignore_pmdown_time = 1,
  6453. .id = MSM_FRONTEND_DAI_MULTIMEDIA27,
  6454. },
  6455. {
  6456. .name = MSM_DAILINK_NAME(Compr Capture3),
  6457. .stream_name = "Compr Capture3",
  6458. .cpu_dai_name = "MultiMedia19",
  6459. .platform_name = "msm-compress-dsp",
  6460. .dynamic = 1,
  6461. .dpcm_capture = 1,
  6462. .codec_dai_name = "snd-soc-dummy-dai",
  6463. .codec_name = "snd-soc-dummy",
  6464. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6465. SND_SOC_DPCM_TRIGGER_POST},
  6466. .ignore_pmdown_time = 1,
  6467. .id = MSM_FRONTEND_DAI_MULTIMEDIA19,
  6468. },
  6469. {
  6470. .name = MSM_DAILINK_NAME(Compr Capture4),
  6471. .stream_name = "Compr Capture4",
  6472. .cpu_dai_name = "MultiMedia28",
  6473. .platform_name = "msm-compress-dsp",
  6474. .dynamic = 1,
  6475. .dpcm_capture = 1,
  6476. .codec_dai_name = "snd-soc-dummy-dai",
  6477. .codec_name = "snd-soc-dummy",
  6478. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6479. SND_SOC_DPCM_TRIGGER_POST},
  6480. .ignore_pmdown_time = 1,
  6481. .id = MSM_FRONTEND_DAI_MULTIMEDIA28,
  6482. },
  6483. {
  6484. .name = MSM_DAILINK_NAME(Compr Capture5),
  6485. .stream_name = "Compr Capture5",
  6486. .cpu_dai_name = "MultiMedia29",
  6487. .platform_name = "msm-compress-dsp",
  6488. .dynamic = 1,
  6489. .dpcm_capture = 1,
  6490. .codec_dai_name = "snd-soc-dummy-dai",
  6491. .codec_name = "snd-soc-dummy",
  6492. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6493. SND_SOC_DPCM_TRIGGER_POST},
  6494. .ignore_pmdown_time = 1,
  6495. .id = MSM_FRONTEND_DAI_MULTIMEDIA29,
  6496. },
  6497. {
  6498. .name = MSM_DAILINK_NAME(Compr Capture6),
  6499. .stream_name = "Compr Capture6",
  6500. .cpu_dai_name = "MultiMedia30",
  6501. .platform_name = "msm-compress-dsp",
  6502. .dynamic = 1,
  6503. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6504. .dpcm_capture = 1,
  6505. .codec_dai_name = "snd-soc-dummy-dai",
  6506. .codec_name = "snd-soc-dummy",
  6507. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6508. SND_SOC_DPCM_TRIGGER_POST},
  6509. .ignore_pmdown_time = 1,
  6510. .id = MSM_FRONTEND_DAI_MULTIMEDIA30,
  6511. },
  6512. };
  6513. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  6514. /* Backend AFE DAI Links */
  6515. {
  6516. .name = LPASS_BE_AFE_PCM_RX,
  6517. .stream_name = "AFE Playback",
  6518. .cpu_dai_name = "msm-dai-q6-dev.224",
  6519. .platform_name = "msm-pcm-routing",
  6520. .codec_name = "msm-stub-codec.1",
  6521. .codec_dai_name = "msm-stub-rx",
  6522. .no_pcm = 1,
  6523. .dpcm_playback = 1,
  6524. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  6525. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6526. /* this dainlink has playback support */
  6527. .ignore_pmdown_time = 1,
  6528. .ignore_suspend = 1,
  6529. },
  6530. {
  6531. .name = LPASS_BE_AFE_PCM_TX,
  6532. .stream_name = "AFE Capture",
  6533. .cpu_dai_name = "msm-dai-q6-dev.225",
  6534. .platform_name = "msm-pcm-routing",
  6535. .codec_name = "msm-stub-codec.1",
  6536. .codec_dai_name = "msm-stub-tx",
  6537. .no_pcm = 1,
  6538. .dpcm_capture = 1,
  6539. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  6540. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6541. .ignore_suspend = 1,
  6542. },
  6543. /* Incall Record Uplink BACK END DAI Link */
  6544. {
  6545. .name = LPASS_BE_INCALL_RECORD_TX,
  6546. .stream_name = "Voice Uplink Capture",
  6547. .cpu_dai_name = "msm-dai-q6-dev.32772",
  6548. .platform_name = "msm-pcm-routing",
  6549. .codec_name = "msm-stub-codec.1",
  6550. .codec_dai_name = "msm-stub-tx",
  6551. .no_pcm = 1,
  6552. .dpcm_capture = 1,
  6553. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  6554. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6555. .ignore_suspend = 1,
  6556. },
  6557. /* Incall Record Downlink BACK END DAI Link */
  6558. {
  6559. .name = LPASS_BE_INCALL_RECORD_RX,
  6560. .stream_name = "Voice Downlink Capture",
  6561. .cpu_dai_name = "msm-dai-q6-dev.32771",
  6562. .platform_name = "msm-pcm-routing",
  6563. .codec_name = "msm-stub-codec.1",
  6564. .codec_dai_name = "msm-stub-tx",
  6565. .no_pcm = 1,
  6566. .dpcm_capture = 1,
  6567. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  6568. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6569. .ignore_suspend = 1,
  6570. },
  6571. /* Incall Music BACK END DAI Link */
  6572. {
  6573. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  6574. .stream_name = "Voice Farend Playback",
  6575. .cpu_dai_name = "msm-dai-q6-dev.32773",
  6576. .platform_name = "msm-pcm-routing",
  6577. .codec_name = "msm-stub-codec.1",
  6578. .codec_dai_name = "msm-stub-rx",
  6579. .no_pcm = 1,
  6580. .dpcm_playback = 1,
  6581. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  6582. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6583. .ignore_suspend = 1,
  6584. .ignore_pmdown_time = 1,
  6585. },
  6586. /* Incall Music 2 BACK END DAI Link */
  6587. {
  6588. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  6589. .stream_name = "Voice2 Farend Playback",
  6590. .cpu_dai_name = "msm-dai-q6-dev.32770",
  6591. .platform_name = "msm-pcm-routing",
  6592. .codec_name = "msm-stub-codec.1",
  6593. .codec_dai_name = "msm-stub-rx",
  6594. .no_pcm = 1,
  6595. .dpcm_playback = 1,
  6596. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  6597. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6598. .ignore_suspend = 1,
  6599. .ignore_pmdown_time = 1,
  6600. },
  6601. {
  6602. .name = LPASS_BE_USB_AUDIO_RX,
  6603. .stream_name = "USB Audio Playback",
  6604. .cpu_dai_name = "msm-dai-q6-dev.28672",
  6605. .platform_name = "msm-pcm-routing",
  6606. .codec_name = "msm-stub-codec.1",
  6607. .codec_dai_name = "msm-stub-rx",
  6608. .no_pcm = 1,
  6609. .dpcm_playback = 1,
  6610. .id = MSM_BACKEND_DAI_USB_RX,
  6611. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6612. .ignore_pmdown_time = 1,
  6613. .ignore_suspend = 1,
  6614. },
  6615. {
  6616. .name = LPASS_BE_USB_AUDIO_TX,
  6617. .stream_name = "USB Audio Capture",
  6618. .cpu_dai_name = "msm-dai-q6-dev.28673",
  6619. .platform_name = "msm-pcm-routing",
  6620. .codec_name = "msm-stub-codec.1",
  6621. .codec_dai_name = "msm-stub-tx",
  6622. .no_pcm = 1,
  6623. .dpcm_capture = 1,
  6624. .id = MSM_BACKEND_DAI_USB_TX,
  6625. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6626. .ignore_suspend = 1,
  6627. },
  6628. {
  6629. .name = LPASS_BE_PRI_TDM_RX_0,
  6630. .stream_name = "Primary TDM0 Playback",
  6631. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  6632. .platform_name = "msm-pcm-routing",
  6633. .codec_name = "msm-stub-codec.1",
  6634. .codec_dai_name = "msm-stub-rx",
  6635. .no_pcm = 1,
  6636. .dpcm_playback = 1,
  6637. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  6638. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6639. .ops = &qcs405_tdm_be_ops,
  6640. .ignore_suspend = 1,
  6641. .ignore_pmdown_time = 1,
  6642. },
  6643. {
  6644. .name = LPASS_BE_PRI_TDM_TX_0,
  6645. .stream_name = "Primary TDM0 Capture",
  6646. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  6647. .platform_name = "msm-pcm-routing",
  6648. .codec_name = "msm-stub-codec.1",
  6649. .codec_dai_name = "msm-stub-tx",
  6650. .no_pcm = 1,
  6651. .dpcm_capture = 1,
  6652. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  6653. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6654. .ops = &qcs405_tdm_be_ops,
  6655. .ignore_suspend = 1,
  6656. },
  6657. {
  6658. .name = LPASS_BE_SEC_TDM_RX_0,
  6659. .stream_name = "Secondary TDM0 Playback",
  6660. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  6661. .platform_name = "msm-pcm-routing",
  6662. .codec_name = "msm-stub-codec.1",
  6663. .codec_dai_name = "msm-stub-rx",
  6664. .no_pcm = 1,
  6665. .dpcm_playback = 1,
  6666. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  6667. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6668. .ops = &qcs405_tdm_be_ops,
  6669. .ignore_suspend = 1,
  6670. .ignore_pmdown_time = 1,
  6671. },
  6672. {
  6673. .name = LPASS_BE_SEC_TDM_TX_0,
  6674. .stream_name = "Secondary TDM0 Capture",
  6675. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  6676. .platform_name = "msm-pcm-routing",
  6677. .codec_name = "msm-stub-codec.1",
  6678. .codec_dai_name = "msm-stub-tx",
  6679. .no_pcm = 1,
  6680. .dpcm_capture = 1,
  6681. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  6682. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6683. .ops = &qcs405_tdm_be_ops,
  6684. .ignore_suspend = 1,
  6685. },
  6686. {
  6687. .name = LPASS_BE_TERT_TDM_RX_0,
  6688. .stream_name = "Tertiary TDM0 Playback",
  6689. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  6690. .platform_name = "msm-pcm-routing",
  6691. .codec_name = "msm-stub-codec.1",
  6692. .codec_dai_name = "msm-stub-rx",
  6693. .no_pcm = 1,
  6694. .dpcm_playback = 1,
  6695. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  6696. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6697. .ops = &qcs405_tdm_be_ops,
  6698. .ignore_suspend = 1,
  6699. .ignore_pmdown_time = 1,
  6700. },
  6701. {
  6702. .name = LPASS_BE_TERT_TDM_TX_0,
  6703. .stream_name = "Tertiary TDM0 Capture",
  6704. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  6705. .platform_name = "msm-pcm-routing",
  6706. .codec_name = "msm-stub-codec.1",
  6707. .codec_dai_name = "msm-stub-tx",
  6708. .no_pcm = 1,
  6709. .dpcm_capture = 1,
  6710. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  6711. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6712. .ops = &qcs405_tdm_be_ops,
  6713. .ignore_suspend = 1,
  6714. },
  6715. {
  6716. .name = LPASS_BE_QUAT_TDM_RX_0,
  6717. .stream_name = "Quaternary TDM0 Playback",
  6718. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  6719. .platform_name = "msm-pcm-routing",
  6720. .codec_name = "msm-stub-codec.1",
  6721. .codec_dai_name = "msm-stub-rx",
  6722. .no_pcm = 1,
  6723. .dpcm_playback = 1,
  6724. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  6725. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6726. .ops = &qcs405_tdm_be_ops,
  6727. .ignore_suspend = 1,
  6728. .ignore_pmdown_time = 1,
  6729. },
  6730. {
  6731. .name = LPASS_BE_QUAT_TDM_TX_0,
  6732. .stream_name = "Quaternary TDM0 Capture",
  6733. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  6734. .platform_name = "msm-pcm-routing",
  6735. .codec_name = "msm-stub-codec.1",
  6736. .codec_dai_name = "msm-stub-tx",
  6737. .no_pcm = 1,
  6738. .dpcm_capture = 1,
  6739. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  6740. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6741. .ops = &qcs405_tdm_be_ops,
  6742. .ignore_suspend = 1,
  6743. },
  6744. {
  6745. .name = LPASS_BE_QUIN_TDM_RX_0,
  6746. .stream_name = "Quinary TDM0 Playback",
  6747. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  6748. .platform_name = "msm-pcm-routing",
  6749. .codec_name = "msm-stub-codec.1",
  6750. .codec_dai_name = "msm-stub-rx",
  6751. .no_pcm = 1,
  6752. .dpcm_playback = 1,
  6753. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  6754. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6755. .ops = &qcs405_tdm_be_ops,
  6756. .ignore_suspend = 1,
  6757. .ignore_pmdown_time = 1,
  6758. },
  6759. {
  6760. .name = LPASS_BE_QUIN_TDM_TX_0,
  6761. .stream_name = "Quinary TDM0 Capture",
  6762. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  6763. .platform_name = "msm-pcm-routing",
  6764. .codec_name = "msm-stub-codec.1",
  6765. .codec_dai_name = "msm-stub-tx",
  6766. .no_pcm = 1,
  6767. .dpcm_capture = 1,
  6768. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  6769. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6770. .ops = &qcs405_tdm_be_ops,
  6771. .ignore_suspend = 1,
  6772. },
  6773. };
  6774. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  6775. {
  6776. .name = LPASS_BE_SLIMBUS_0_RX,
  6777. .stream_name = "Slimbus Playback",
  6778. .cpu_dai_name = "msm-dai-q6-dev.16384",
  6779. .platform_name = "msm-pcm-routing",
  6780. .codec_name = "tasha_codec",
  6781. .codec_dai_name = "tasha_mix_rx1",
  6782. .no_pcm = 1,
  6783. .dpcm_playback = 1,
  6784. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  6785. .init = &msm_audrx_init,
  6786. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6787. /* this dainlink has playback support */
  6788. .ignore_pmdown_time = 1,
  6789. .ignore_suspend = 1,
  6790. .ops = &msm_be_ops,
  6791. },
  6792. {
  6793. .name = LPASS_BE_SLIMBUS_0_TX,
  6794. .stream_name = "Slimbus Capture",
  6795. .cpu_dai_name = "msm-dai-q6-dev.16385",
  6796. .platform_name = "msm-pcm-routing",
  6797. .codec_name = "tasha_codec",
  6798. .codec_dai_name = "tasha_tx1",
  6799. .no_pcm = 1,
  6800. .dpcm_capture = 1,
  6801. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  6802. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6803. .ignore_suspend = 1,
  6804. .ops = &msm_be_ops,
  6805. },
  6806. {
  6807. .name = LPASS_BE_SLIMBUS_1_RX,
  6808. .stream_name = "Slimbus1 Playback",
  6809. .cpu_dai_name = "msm-dai-q6-dev.16386",
  6810. .platform_name = "msm-pcm-routing",
  6811. .codec_name = "tasha_codec",
  6812. .codec_dai_name = "tasha_mix_rx1",
  6813. .no_pcm = 1,
  6814. .dpcm_playback = 1,
  6815. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  6816. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6817. .ops = &msm_be_ops,
  6818. /* dai link has playback support */
  6819. .ignore_pmdown_time = 1,
  6820. .ignore_suspend = 1,
  6821. },
  6822. {
  6823. .name = LPASS_BE_SLIMBUS_1_TX,
  6824. .stream_name = "Slimbus1 Capture",
  6825. .cpu_dai_name = "msm-dai-q6-dev.16387",
  6826. .platform_name = "msm-pcm-routing",
  6827. .codec_name = "tasha_codec",
  6828. .codec_dai_name = "tasha_tx3",
  6829. .no_pcm = 1,
  6830. .dpcm_capture = 1,
  6831. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  6832. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6833. .ops = &msm_be_ops,
  6834. .ignore_suspend = 1,
  6835. },
  6836. {
  6837. .name = LPASS_BE_SLIMBUS_2_RX,
  6838. .stream_name = "Slimbus2 Playback",
  6839. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6840. .platform_name = "msm-pcm-routing",
  6841. .codec_name = "tasha_codec",
  6842. .codec_dai_name = "tasha_rx2",
  6843. .no_pcm = 1,
  6844. .dpcm_playback = 1,
  6845. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6846. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6847. .ops = &msm_be_ops,
  6848. .ignore_pmdown_time = 1,
  6849. .ignore_suspend = 1,
  6850. },
  6851. {
  6852. .name = LPASS_BE_SLIMBUS_3_RX,
  6853. .stream_name = "Slimbus3 Playback",
  6854. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6855. .platform_name = "msm-pcm-routing",
  6856. .codec_name = "tasha_codec",
  6857. .codec_dai_name = "tasha_mix_rx1",
  6858. .no_pcm = 1,
  6859. .dpcm_playback = 1,
  6860. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6861. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6862. .ops = &msm_be_ops,
  6863. /* dai link has playback support */
  6864. .ignore_pmdown_time = 1,
  6865. .ignore_suspend = 1,
  6866. },
  6867. {
  6868. .name = LPASS_BE_SLIMBUS_3_TX,
  6869. .stream_name = "Slimbus3 Capture",
  6870. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6871. .platform_name = "msm-pcm-routing",
  6872. .codec_name = "tasha_codec",
  6873. .codec_dai_name = "tasha_tx1",
  6874. .no_pcm = 1,
  6875. .dpcm_capture = 1,
  6876. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6877. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6878. .ops = &msm_be_ops,
  6879. .ignore_suspend = 1,
  6880. },
  6881. {
  6882. .name = LPASS_BE_SLIMBUS_4_RX,
  6883. .stream_name = "Slimbus4 Playback",
  6884. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6885. .platform_name = "msm-pcm-routing",
  6886. .codec_name = "tasha_codec",
  6887. .codec_dai_name = "tasha_mix_rx1",
  6888. .no_pcm = 1,
  6889. .dpcm_playback = 1,
  6890. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6891. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6892. .ops = &msm_be_ops,
  6893. /* dai link has playback support */
  6894. .ignore_pmdown_time = 1,
  6895. .ignore_suspend = 1,
  6896. },
  6897. {
  6898. .name = LPASS_BE_SLIMBUS_5_RX,
  6899. .stream_name = "Slimbus5 Playback",
  6900. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6901. .platform_name = "msm-pcm-routing",
  6902. .codec_name = "tasha_codec",
  6903. .codec_dai_name = "tasha_rx3",
  6904. .no_pcm = 1,
  6905. .dpcm_playback = 1,
  6906. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6907. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6908. .ops = &msm_be_ops,
  6909. /* dai link has playback support */
  6910. .ignore_pmdown_time = 1,
  6911. .ignore_suspend = 1,
  6912. },
  6913. {
  6914. .name = LPASS_BE_SLIMBUS_6_RX,
  6915. .stream_name = "Slimbus6 Playback",
  6916. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6917. .platform_name = "msm-pcm-routing",
  6918. .codec_name = "tasha_codec",
  6919. .codec_dai_name = "tasha_rx4",
  6920. .no_pcm = 1,
  6921. .dpcm_playback = 1,
  6922. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6923. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6924. .ops = &msm_be_ops,
  6925. /* dai link has playback support */
  6926. .ignore_pmdown_time = 1,
  6927. .ignore_suspend = 1,
  6928. },
  6929. /* Slimbus VI Recording */
  6930. {
  6931. .name = LPASS_BE_SLIMBUS_TX_VI,
  6932. .stream_name = "Slimbus4 Capture",
  6933. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6934. .platform_name = "msm-pcm-routing",
  6935. .codec_name = "tasha_codec",
  6936. .codec_dai_name = "tasha_vifeedback",
  6937. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6938. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6939. .ops = &msm_be_ops,
  6940. .ignore_suspend = 1,
  6941. .no_pcm = 1,
  6942. .dpcm_capture = 1,
  6943. .ignore_pmdown_time = 1,
  6944. },
  6945. };
  6946. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6947. {
  6948. .name = LPASS_BE_SLIMBUS_7_RX,
  6949. .stream_name = "Slimbus7 Playback",
  6950. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6951. .platform_name = "msm-pcm-routing",
  6952. .codec_name = "btfmslim_slave",
  6953. /* BT codec driver determines capabilities based on
  6954. * dai name, bt codecdai name should always contains
  6955. * supported usecase information
  6956. */
  6957. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6958. .no_pcm = 1,
  6959. .dpcm_playback = 1,
  6960. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6961. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6962. .ops = &msm_wcn_ops,
  6963. /* dai link has playback support */
  6964. .ignore_pmdown_time = 1,
  6965. .ignore_suspend = 1,
  6966. },
  6967. {
  6968. .name = LPASS_BE_SLIMBUS_7_TX,
  6969. .stream_name = "Slimbus7 Capture",
  6970. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6971. .platform_name = "msm-pcm-routing",
  6972. .codec_name = "btfmslim_slave",
  6973. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6974. .no_pcm = 1,
  6975. .dpcm_capture = 1,
  6976. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6977. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6978. .ops = &msm_wcn_ops,
  6979. .ignore_suspend = 1,
  6980. },
  6981. {
  6982. .name = LPASS_BE_SLIMBUS_8_TX,
  6983. .stream_name = "Slimbus8 Capture",
  6984. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6985. .platform_name = "msm-pcm-routing",
  6986. .codec_name = "btfmslim_slave",
  6987. .codec_dai_name = "btfm_fm_slim_tx",
  6988. .no_pcm = 1,
  6989. .dpcm_capture = 1,
  6990. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6991. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6992. .init = &msm_wcn_init,
  6993. .ops = &msm_wcn_ops,
  6994. .ignore_suspend = 1,
  6995. },
  6996. {
  6997. .name = LPASS_BE_SLIMBUS_9_TX,
  6998. .stream_name = "Slimbus9 Capture",
  6999. .cpu_dai_name = "msm-dai-q6-dev.16403",
  7000. .platform_name = "msm-pcm-routing",
  7001. .codec_name = "btfmslim_slave",
  7002. .codec_dai_name = "btfm_bt_split_a2dp_slim_tx",
  7003. .no_pcm = 1,
  7004. .dpcm_capture = 1,
  7005. .id = MSM_BACKEND_DAI_SLIMBUS_9_TX,
  7006. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7007. .ops = &msm_wcn_ops,
  7008. .ignore_suspend = 1,
  7009. },
  7010. };
  7011. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  7012. {
  7013. .name = LPASS_BE_PRI_MI2S_RX,
  7014. .stream_name = "Primary MI2S Playback",
  7015. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  7016. .platform_name = "msm-pcm-routing",
  7017. .codec_name = "msm-stub-codec.1",
  7018. .codec_dai_name = "msm-stub-rx",
  7019. .no_pcm = 1,
  7020. .dpcm_playback = 1,
  7021. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  7022. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7023. .ops = &msm_mi2s_be_ops,
  7024. .ignore_suspend = 1,
  7025. .ignore_pmdown_time = 1,
  7026. },
  7027. {
  7028. .name = LPASS_BE_PRI_MI2S_TX,
  7029. .stream_name = "Primary MI2S Capture",
  7030. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  7031. .platform_name = "msm-pcm-routing",
  7032. .codec_name = "msm-stub-codec.1",
  7033. .codec_dai_name = "msm-stub-tx",
  7034. .no_pcm = 1,
  7035. .dpcm_capture = 1,
  7036. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  7037. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7038. .ops = &msm_mi2s_be_ops,
  7039. .ignore_suspend = 1,
  7040. },
  7041. {
  7042. .name = LPASS_BE_SEC_MI2S_RX,
  7043. .stream_name = "Secondary MI2S Playback",
  7044. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  7045. .platform_name = "msm-pcm-routing",
  7046. .codec_name = "msm-stub-codec.1",
  7047. .codec_dai_name = "msm-stub-rx",
  7048. .no_pcm = 1,
  7049. .dpcm_playback = 1,
  7050. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  7051. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7052. .ops = &msm_mi2s_be_ops,
  7053. .ignore_suspend = 1,
  7054. .ignore_pmdown_time = 1,
  7055. },
  7056. {
  7057. .name = LPASS_BE_SEC_MI2S_TX,
  7058. .stream_name = "Secondary MI2S Capture",
  7059. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  7060. .platform_name = "msm-pcm-routing",
  7061. .codec_name = "msm-stub-codec.1",
  7062. .codec_dai_name = "msm-stub-tx",
  7063. .no_pcm = 1,
  7064. .dpcm_capture = 1,
  7065. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  7066. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7067. .ops = &msm_mi2s_be_ops,
  7068. .ignore_suspend = 1,
  7069. },
  7070. {
  7071. .name = LPASS_BE_TERT_MI2S_RX,
  7072. .stream_name = "Tertiary MI2S Playback",
  7073. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  7074. .platform_name = "msm-pcm-routing",
  7075. .codec_name = "msm-stub-codec.1",
  7076. .codec_dai_name = "msm-stub-rx",
  7077. .no_pcm = 1,
  7078. .dpcm_playback = 1,
  7079. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  7080. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7081. .ops = &msm_mi2s_be_ops,
  7082. .ignore_suspend = 1,
  7083. .ignore_pmdown_time = 1,
  7084. },
  7085. {
  7086. .name = LPASS_BE_TERT_MI2S_TX,
  7087. .stream_name = "Tertiary MI2S Capture",
  7088. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  7089. .platform_name = "msm-pcm-routing",
  7090. .codec_name = "msm-stub-codec.1",
  7091. .codec_dai_name = "msm-stub-tx",
  7092. .no_pcm = 1,
  7093. .dpcm_capture = 1,
  7094. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  7095. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7096. .ops = &msm_mi2s_be_ops,
  7097. .ignore_suspend = 1,
  7098. },
  7099. {
  7100. .name = LPASS_BE_QUAT_MI2S_RX,
  7101. .stream_name = "Quaternary MI2S Playback",
  7102. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  7103. .platform_name = "msm-pcm-routing",
  7104. .codec_name = "msm-stub-codec.1",
  7105. .codec_dai_name = "msm-stub-rx",
  7106. .no_pcm = 1,
  7107. .dpcm_playback = 1,
  7108. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  7109. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7110. .ops = &msm_mi2s_be_ops,
  7111. .ignore_suspend = 1,
  7112. .ignore_pmdown_time = 1,
  7113. },
  7114. {
  7115. .name = LPASS_BE_QUAT_MI2S_TX,
  7116. .stream_name = "Quaternary MI2S Capture",
  7117. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  7118. .platform_name = "msm-pcm-routing",
  7119. .codec_name = "msm-stub-codec.1",
  7120. .codec_dai_name = "msm-stub-tx",
  7121. .no_pcm = 1,
  7122. .dpcm_capture = 1,
  7123. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  7124. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7125. .ops = &msm_mi2s_be_ops,
  7126. .ignore_suspend = 1,
  7127. },
  7128. {
  7129. .name = LPASS_BE_QUIN_MI2S_RX,
  7130. .stream_name = "Quinary MI2S Playback",
  7131. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  7132. .platform_name = "msm-pcm-routing",
  7133. .codec_name = "msm-stub-codec.1",
  7134. .codec_dai_name = "msm-stub-rx",
  7135. .no_pcm = 1,
  7136. .dpcm_playback = 1,
  7137. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  7138. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7139. .ops = &msm_mi2s_be_ops,
  7140. .ignore_suspend = 1,
  7141. .ignore_pmdown_time = 1,
  7142. },
  7143. {
  7144. .name = LPASS_BE_QUIN_MI2S_TX,
  7145. .stream_name = "Quinary MI2S Capture",
  7146. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  7147. .platform_name = "msm-pcm-routing",
  7148. .codec_name = "msm-stub-codec.1",
  7149. .codec_dai_name = "msm-stub-tx",
  7150. .no_pcm = 1,
  7151. .dpcm_capture = 1,
  7152. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  7153. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7154. .ops = &msm_mi2s_be_ops,
  7155. .ignore_suspend = 1,
  7156. },
  7157. };
  7158. static struct snd_soc_dai_link msm_meta_mi2s_be_dai_links[] = {
  7159. {
  7160. .name = LPASS_BE_PRI_META_MI2S_RX,
  7161. .stream_name = "Primary META MI2S Playback",
  7162. .cpu_dai_name = "msm-dai-q6-meta-mi2s.4864",
  7163. .platform_name = "msm-pcm-routing",
  7164. .codec_name = "msm-stub-codec.1",
  7165. .codec_dai_name = "msm-stub-rx",
  7166. .no_pcm = 1,
  7167. .dpcm_playback = 1,
  7168. .id = MSM_BACKEND_DAI_PRI_META_MI2S_RX,
  7169. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7170. .ops = &msm_meta_mi2s_be_ops,
  7171. .ignore_suspend = 1,
  7172. .ignore_pmdown_time = 1,
  7173. },
  7174. {
  7175. .name = LPASS_BE_SEC_META_MI2S_RX,
  7176. .stream_name = "Secondary META MI2S Playback",
  7177. .cpu_dai_name = "msm-dai-q6-meta-mi2s.4866",
  7178. .platform_name = "msm-pcm-routing",
  7179. .codec_name = "msm-stub-codec.1",
  7180. .codec_dai_name = "msm-stub-rx",
  7181. .no_pcm = 1,
  7182. .dpcm_playback = 1,
  7183. .id = MSM_BACKEND_DAI_SEC_META_MI2S_RX,
  7184. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7185. .ops = &msm_meta_mi2s_be_ops,
  7186. .ignore_suspend = 1,
  7187. .ignore_pmdown_time = 1,
  7188. },
  7189. };
  7190. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  7191. /* Primary AUX PCM Backend DAI Links */
  7192. {
  7193. .name = LPASS_BE_AUXPCM_RX,
  7194. .stream_name = "AUX PCM Playback",
  7195. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  7196. .platform_name = "msm-pcm-routing",
  7197. .codec_name = "msm-stub-codec.1",
  7198. .codec_dai_name = "msm-stub-rx",
  7199. .no_pcm = 1,
  7200. .dpcm_playback = 1,
  7201. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  7202. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7203. .ops = &msm_auxpcm_be_ops,
  7204. .ignore_pmdown_time = 1,
  7205. .ignore_suspend = 1,
  7206. },
  7207. {
  7208. .name = LPASS_BE_AUXPCM_TX,
  7209. .stream_name = "AUX PCM Capture",
  7210. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  7211. .platform_name = "msm-pcm-routing",
  7212. .codec_name = "msm-stub-codec.1",
  7213. .codec_dai_name = "msm-stub-tx",
  7214. .no_pcm = 1,
  7215. .dpcm_capture = 1,
  7216. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  7217. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7218. .ops = &msm_auxpcm_be_ops,
  7219. .ignore_suspend = 1,
  7220. },
  7221. /* Secondary AUX PCM Backend DAI Links */
  7222. {
  7223. .name = LPASS_BE_SEC_AUXPCM_RX,
  7224. .stream_name = "Sec AUX PCM Playback",
  7225. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  7226. .platform_name = "msm-pcm-routing",
  7227. .codec_name = "msm-stub-codec.1",
  7228. .codec_dai_name = "msm-stub-rx",
  7229. .no_pcm = 1,
  7230. .dpcm_playback = 1,
  7231. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  7232. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7233. .ops = &msm_auxpcm_be_ops,
  7234. .ignore_pmdown_time = 1,
  7235. .ignore_suspend = 1,
  7236. },
  7237. {
  7238. .name = LPASS_BE_SEC_AUXPCM_TX,
  7239. .stream_name = "Sec AUX PCM Capture",
  7240. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  7241. .platform_name = "msm-pcm-routing",
  7242. .codec_name = "msm-stub-codec.1",
  7243. .codec_dai_name = "msm-stub-tx",
  7244. .no_pcm = 1,
  7245. .dpcm_capture = 1,
  7246. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  7247. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7248. .ops = &msm_auxpcm_be_ops,
  7249. .ignore_suspend = 1,
  7250. },
  7251. /* Tertiary AUX PCM Backend DAI Links */
  7252. {
  7253. .name = LPASS_BE_TERT_AUXPCM_RX,
  7254. .stream_name = "Tert AUX PCM Playback",
  7255. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  7256. .platform_name = "msm-pcm-routing",
  7257. .codec_name = "msm-stub-codec.1",
  7258. .codec_dai_name = "msm-stub-rx",
  7259. .no_pcm = 1,
  7260. .dpcm_playback = 1,
  7261. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  7262. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7263. .ops = &msm_auxpcm_be_ops,
  7264. .ignore_suspend = 1,
  7265. },
  7266. {
  7267. .name = LPASS_BE_TERT_AUXPCM_TX,
  7268. .stream_name = "Tert AUX PCM Capture",
  7269. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  7270. .platform_name = "msm-pcm-routing",
  7271. .codec_name = "msm-stub-codec.1",
  7272. .codec_dai_name = "msm-stub-tx",
  7273. .no_pcm = 1,
  7274. .dpcm_capture = 1,
  7275. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  7276. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7277. .ops = &msm_auxpcm_be_ops,
  7278. .ignore_suspend = 1,
  7279. },
  7280. /* Quaternary AUX PCM Backend DAI Links */
  7281. {
  7282. .name = LPASS_BE_QUAT_AUXPCM_RX,
  7283. .stream_name = "Quat AUX PCM Playback",
  7284. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  7285. .platform_name = "msm-pcm-routing",
  7286. .codec_name = "msm-stub-codec.1",
  7287. .codec_dai_name = "msm-stub-rx",
  7288. .no_pcm = 1,
  7289. .dpcm_playback = 1,
  7290. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  7291. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7292. .ops = &msm_auxpcm_be_ops,
  7293. .ignore_pmdown_time = 1,
  7294. .ignore_suspend = 1,
  7295. },
  7296. {
  7297. .name = LPASS_BE_QUAT_AUXPCM_TX,
  7298. .stream_name = "Quat AUX PCM Capture",
  7299. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  7300. .platform_name = "msm-pcm-routing",
  7301. .codec_name = "msm-stub-codec.1",
  7302. .codec_dai_name = "msm-stub-tx",
  7303. .no_pcm = 1,
  7304. .dpcm_capture = 1,
  7305. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  7306. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7307. .ops = &msm_auxpcm_be_ops,
  7308. .ignore_suspend = 1,
  7309. },
  7310. /* Quinary AUX PCM Backend DAI Links */
  7311. {
  7312. .name = LPASS_BE_QUIN_AUXPCM_RX,
  7313. .stream_name = "Quin AUX PCM Playback",
  7314. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  7315. .platform_name = "msm-pcm-routing",
  7316. .codec_name = "msm-stub-codec.1",
  7317. .codec_dai_name = "msm-stub-rx",
  7318. .no_pcm = 1,
  7319. .dpcm_playback = 1,
  7320. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  7321. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7322. .ops = &msm_auxpcm_be_ops,
  7323. .ignore_pmdown_time = 1,
  7324. .ignore_suspend = 1,
  7325. },
  7326. {
  7327. .name = LPASS_BE_QUIN_AUXPCM_TX,
  7328. .stream_name = "Quin AUX PCM Capture",
  7329. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  7330. .platform_name = "msm-pcm-routing",
  7331. .codec_name = "msm-stub-codec.1",
  7332. .codec_dai_name = "msm-stub-tx",
  7333. .no_pcm = 1,
  7334. .dpcm_capture = 1,
  7335. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  7336. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7337. .ops = &msm_auxpcm_be_ops,
  7338. .ignore_suspend = 1,
  7339. },
  7340. };
  7341. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  7342. /* WSA CDC DMA Backend DAI Links */
  7343. {
  7344. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  7345. .stream_name = "WSA CDC DMA0 Playback",
  7346. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  7347. .platform_name = "msm-pcm-routing",
  7348. .codec_name = "bolero_codec",
  7349. .codec_dai_name = "wsa_macro_rx1",
  7350. .no_pcm = 1,
  7351. .dpcm_playback = 1,
  7352. .init = &msm_wsa_cdc_dma_init,
  7353. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  7354. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7355. .ignore_pmdown_time = 1,
  7356. .ignore_suspend = 1,
  7357. .ops = &msm_cdc_dma_be_ops,
  7358. },
  7359. {
  7360. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  7361. .stream_name = "WSA CDC DMA1 Playback",
  7362. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  7363. .platform_name = "msm-pcm-routing",
  7364. .codec_name = "bolero_codec",
  7365. .codec_dai_name = "wsa_macro_rx_mix",
  7366. .no_pcm = 1,
  7367. .dpcm_playback = 1,
  7368. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  7369. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7370. .ignore_pmdown_time = 1,
  7371. .ignore_suspend = 1,
  7372. .ops = &msm_cdc_dma_be_ops,
  7373. },
  7374. {
  7375. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  7376. .stream_name = "WSA CDC DMA1 Capture",
  7377. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  7378. .platform_name = "msm-pcm-routing",
  7379. .codec_name = "bolero_codec",
  7380. .codec_dai_name = "wsa_macro_echo",
  7381. .no_pcm = 1,
  7382. .dpcm_capture = 1,
  7383. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  7384. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7385. .ignore_suspend = 1,
  7386. .ops = &msm_cdc_dma_be_ops,
  7387. },
  7388. };
  7389. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  7390. {
  7391. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  7392. .stream_name = "VA CDC DMA0 Capture",
  7393. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  7394. .platform_name = "msm-pcm-routing",
  7395. .codec_name = "bolero_codec",
  7396. .codec_dai_name = "va_macro_tx1",
  7397. .no_pcm = 1,
  7398. .dpcm_capture = 1,
  7399. .init = &msm_va_cdc_dma_init,
  7400. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  7401. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7402. .ignore_suspend = 1,
  7403. .ops = &msm_cdc_dma_be_ops,
  7404. },
  7405. {
  7406. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  7407. .stream_name = "VA CDC DMA1 Capture",
  7408. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  7409. .platform_name = "msm-pcm-routing",
  7410. .codec_name = "bolero_codec",
  7411. .codec_dai_name = "va_macro_tx2",
  7412. .no_pcm = 1,
  7413. .dpcm_capture = 1,
  7414. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  7415. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7416. .ignore_suspend = 1,
  7417. .ops = &msm_cdc_dma_be_ops,
  7418. },
  7419. };
  7420. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  7421. {
  7422. .name = LPASS_BE_PRI_SPDIF_RX,
  7423. .stream_name = "Primary SPDIF Playback",
  7424. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  7425. .platform_name = "msm-pcm-routing",
  7426. .codec_name = "msm-stub-codec.1",
  7427. .codec_dai_name = "msm-stub-rx",
  7428. .no_pcm = 1,
  7429. .dpcm_playback = 1,
  7430. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  7431. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7432. .ops = &msm_spdif_be_ops,
  7433. .ignore_suspend = 1,
  7434. .ignore_pmdown_time = 1,
  7435. },
  7436. {
  7437. .name = LPASS_BE_PRI_SPDIF_TX,
  7438. .stream_name = "Primary SPDIF Capture",
  7439. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  7440. .platform_name = "msm-pcm-routing",
  7441. .codec_name = "msm-stub-codec.1",
  7442. .codec_dai_name = "msm-stub-tx",
  7443. .no_pcm = 1,
  7444. .dpcm_capture = 1,
  7445. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  7446. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7447. .ops = &msm_spdif_be_ops,
  7448. .ignore_suspend = 1,
  7449. },
  7450. {
  7451. .name = LPASS_BE_SEC_SPDIF_RX,
  7452. .stream_name = "Secondary SPDIF Playback",
  7453. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  7454. .platform_name = "msm-pcm-routing",
  7455. .codec_name = "msm-stub-codec.1",
  7456. .codec_dai_name = "msm-stub-rx",
  7457. .no_pcm = 1,
  7458. .dpcm_playback = 1,
  7459. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  7460. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7461. .ops = &msm_spdif_be_ops,
  7462. .ignore_suspend = 1,
  7463. .ignore_pmdown_time = 1,
  7464. },
  7465. {
  7466. .name = LPASS_BE_SEC_SPDIF_TX,
  7467. .stream_name = "Secondary SPDIF Capture",
  7468. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  7469. .platform_name = "msm-pcm-routing",
  7470. .codec_name = "msm-stub-codec.1",
  7471. .codec_dai_name = "msm-stub-tx",
  7472. .no_pcm = 1,
  7473. .dpcm_capture = 1,
  7474. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  7475. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7476. .ops = &msm_spdif_be_ops,
  7477. .ignore_suspend = 1,
  7478. },
  7479. };
  7480. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  7481. {
  7482. .name = LPASS_BE_AFE_LOOPBACK_TX,
  7483. .stream_name = "AFE Loopback Capture",
  7484. .cpu_dai_name = "msm-dai-q6-dev.24577",
  7485. .platform_name = "msm-pcm-routing",
  7486. .codec_name = "msm-stub-codec.1",
  7487. .codec_dai_name = "msm-stub-tx",
  7488. .no_pcm = 1,
  7489. .dpcm_capture = 1,
  7490. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  7491. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7492. .ignore_pmdown_time = 1,
  7493. .ignore_suspend = 1,
  7494. },
  7495. };
  7496. static struct snd_soc_dai_link msm_qcs405_dai_links[
  7497. ARRAY_SIZE(msm_common_dai_links) +
  7498. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  7499. ARRAY_SIZE(msm_common_be_dai_links) +
  7500. ARRAY_SIZE(msm_tasha_be_dai_links) +
  7501. ARRAY_SIZE(msm_wcn_be_dai_links) +
  7502. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  7503. ARRAY_SIZE(msm_meta_mi2s_be_dai_links) +
  7504. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  7505. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  7506. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  7507. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  7508. ARRAY_SIZE(msm_spdif_be_dai_links) +
  7509. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link)];
  7510. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  7511. {
  7512. int ret = 0;
  7513. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  7514. &service_nb);
  7515. if (ret < 0)
  7516. pr_err("%s: Audio notifier register failed ret = %d\n",
  7517. __func__, ret);
  7518. return ret;
  7519. }
  7520. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  7521. struct snd_ctl_elem_value *ucontrol)
  7522. {
  7523. int ret = 0;
  7524. int port_id;
  7525. uint32_t vad_enable = ucontrol->value.integer.value[0];
  7526. uint32_t preroll_config = ucontrol->value.integer.value[1];
  7527. uint32_t vad_intf = ucontrol->value.integer.value[2];
  7528. if ((preroll_config < 0) || (preroll_config > 1000) ||
  7529. (vad_enable < 0) || (vad_enable > 1) ||
  7530. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  7531. pr_err("%s: Invalid arguments\n", __func__);
  7532. ret = -EINVAL;
  7533. goto done;
  7534. }
  7535. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  7536. vad_enable, preroll_config, vad_intf);
  7537. ret = msm_island_vad_get_portid_from_beid(vad_intf, &port_id);
  7538. if (ret) {
  7539. pr_err("%s: Invalid vad interface\n", __func__);
  7540. goto done;
  7541. }
  7542. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  7543. done:
  7544. return ret;
  7545. }
  7546. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  7547. {
  7548. int ret = 0;
  7549. uint32_t tasha_codec = 0;
  7550. ret = afe_cal_init_hwdep(card);
  7551. if (ret) {
  7552. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  7553. ret = 0;
  7554. }
  7555. /* tasha late probe when it is present */
  7556. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  7557. &tasha_codec);
  7558. if (ret) {
  7559. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  7560. ret = 0;
  7561. } else {
  7562. if (tasha_codec) {
  7563. ret = msm_snd_card_tasha_late_probe(card);
  7564. if (ret)
  7565. dev_err(card->dev, "%s: tasha late probe err\n",
  7566. __func__);
  7567. }
  7568. }
  7569. return ret;
  7570. }
  7571. struct snd_soc_card snd_soc_card_qcs405_msm = {
  7572. .name = "qcs405-snd-card",
  7573. .controls = msm_snd_controls,
  7574. .num_controls = ARRAY_SIZE(msm_snd_controls),
  7575. .late_probe = msm_snd_card_codec_late_probe,
  7576. };
  7577. static int msm_populate_dai_link_component_of_node(
  7578. struct snd_soc_card *card)
  7579. {
  7580. int i, index, ret = 0;
  7581. struct device *cdev = card->dev;
  7582. struct snd_soc_dai_link *dai_link = card->dai_link;
  7583. struct device_node *np;
  7584. if (!cdev) {
  7585. pr_err("%s: Sound card device memory NULL\n", __func__);
  7586. return -ENODEV;
  7587. }
  7588. for (i = 0; i < card->num_links; i++) {
  7589. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  7590. continue;
  7591. /* populate platform_of_node for snd card dai links */
  7592. if (dai_link[i].platform_name &&
  7593. !dai_link[i].platform_of_node) {
  7594. index = of_property_match_string(cdev->of_node,
  7595. "asoc-platform-names",
  7596. dai_link[i].platform_name);
  7597. if (index < 0) {
  7598. pr_err("%s: No match found for platform name: %s\n",
  7599. __func__, dai_link[i].platform_name);
  7600. ret = index;
  7601. goto err;
  7602. }
  7603. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  7604. index);
  7605. if (!np) {
  7606. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  7607. __func__, dai_link[i].platform_name,
  7608. index);
  7609. ret = -ENODEV;
  7610. goto err;
  7611. }
  7612. dai_link[i].platform_of_node = np;
  7613. dai_link[i].platform_name = NULL;
  7614. }
  7615. /* populate cpu_of_node for snd card dai links */
  7616. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  7617. index = of_property_match_string(cdev->of_node,
  7618. "asoc-cpu-names",
  7619. dai_link[i].cpu_dai_name);
  7620. if (index >= 0) {
  7621. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  7622. index);
  7623. if (!np) {
  7624. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  7625. __func__,
  7626. dai_link[i].cpu_dai_name);
  7627. ret = -ENODEV;
  7628. goto err;
  7629. }
  7630. dai_link[i].cpu_of_node = np;
  7631. dai_link[i].cpu_dai_name = NULL;
  7632. }
  7633. }
  7634. /* populate codec_of_node for snd card dai links */
  7635. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  7636. index = of_property_match_string(cdev->of_node,
  7637. "asoc-codec-names",
  7638. dai_link[i].codec_name);
  7639. if (index < 0)
  7640. continue;
  7641. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  7642. index);
  7643. if (!np) {
  7644. pr_err("%s: retrieving phandle for codec %s failed\n",
  7645. __func__, dai_link[i].codec_name);
  7646. ret = -ENODEV;
  7647. goto err;
  7648. }
  7649. dai_link[i].codec_of_node = np;
  7650. dai_link[i].codec_name = NULL;
  7651. }
  7652. }
  7653. err:
  7654. return ret;
  7655. }
  7656. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  7657. /* FrontEnd DAI Links */
  7658. {
  7659. .name = "MSMSTUB Media1",
  7660. .stream_name = "MultiMedia1",
  7661. .cpu_dai_name = "MultiMedia1",
  7662. .platform_name = "msm-pcm-dsp.0",
  7663. .dynamic = 1,
  7664. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  7665. .dpcm_playback = 1,
  7666. .dpcm_capture = 1,
  7667. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  7668. SND_SOC_DPCM_TRIGGER_POST},
  7669. .codec_dai_name = "snd-soc-dummy-dai",
  7670. .codec_name = "snd-soc-dummy",
  7671. .ignore_suspend = 1,
  7672. /* this dainlink has playback support */
  7673. .ignore_pmdown_time = 1,
  7674. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  7675. },
  7676. };
  7677. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  7678. /* Backend DAI Links */
  7679. {
  7680. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  7681. .stream_name = "VA CDC DMA0 Capture",
  7682. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  7683. .platform_name = "msm-pcm-routing",
  7684. .codec_name = "bolero_codec",
  7685. .codec_dai_name = "va_macro_tx1",
  7686. .no_pcm = 1,
  7687. .dpcm_capture = 1,
  7688. .init = &msm_va_cdc_dma_init,
  7689. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  7690. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7691. .ignore_suspend = 1,
  7692. .ops = &msm_cdc_dma_be_ops,
  7693. },
  7694. {
  7695. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  7696. .stream_name = "VA CDC DMA1 Capture",
  7697. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  7698. .platform_name = "msm-pcm-routing",
  7699. .codec_name = "bolero_codec",
  7700. .codec_dai_name = "va_macro_tx2",
  7701. .no_pcm = 1,
  7702. .dpcm_capture = 1,
  7703. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  7704. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7705. .ignore_suspend = 1,
  7706. .ops = &msm_cdc_dma_be_ops,
  7707. },
  7708. };
  7709. static struct snd_soc_dai_link msm_stub_dai_links[
  7710. ARRAY_SIZE(msm_stub_fe_dai_links) +
  7711. ARRAY_SIZE(msm_stub_be_dai_links)];
  7712. struct snd_soc_card snd_soc_card_stub_msm = {
  7713. .name = "qcs405-stub-snd-card",
  7714. };
  7715. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  7716. { .compatible = "qcom,qcs405-asoc-snd",
  7717. .data = "codec"},
  7718. { .compatible = "qcom,qcs405-asoc-snd-stub",
  7719. .data = "stub_codec"},
  7720. {},
  7721. };
  7722. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  7723. {
  7724. struct snd_soc_card *card = NULL;
  7725. struct snd_soc_dai_link *dailink;
  7726. int total_links = 0;
  7727. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  7728. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  7729. uint32_t spdif_audio_intf = 0, wcn_audio_intf = 0;
  7730. uint32_t afe_loopback_intf = 0, meta_mi2s_intf = 0;
  7731. const struct of_device_id *match;
  7732. char __iomem *spdif_cfg, *spdif_pin_ctl;
  7733. int rc = 0;
  7734. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  7735. if (!match) {
  7736. dev_err(dev, "%s: No DT match found for sound card\n",
  7737. __func__);
  7738. return NULL;
  7739. }
  7740. if (!strcmp(match->data, "codec")) {
  7741. card = &snd_soc_card_qcs405_msm;
  7742. memcpy(msm_qcs405_dai_links + total_links,
  7743. msm_common_dai_links,
  7744. sizeof(msm_common_dai_links));
  7745. total_links += ARRAY_SIZE(msm_common_dai_links);
  7746. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  7747. &wsa_bolero_codec);
  7748. if (rc) {
  7749. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  7750. __func__);
  7751. } else {
  7752. if (wsa_bolero_codec) {
  7753. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  7754. __func__);
  7755. memcpy(msm_qcs405_dai_links + total_links,
  7756. msm_bolero_fe_dai_links,
  7757. sizeof(msm_bolero_fe_dai_links));
  7758. total_links +=
  7759. ARRAY_SIZE(msm_bolero_fe_dai_links);
  7760. }
  7761. }
  7762. memcpy(msm_qcs405_dai_links + total_links,
  7763. msm_common_misc_fe_dai_links,
  7764. sizeof(msm_common_misc_fe_dai_links));
  7765. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  7766. memcpy(msm_qcs405_dai_links + total_links,
  7767. msm_common_be_dai_links,
  7768. sizeof(msm_common_be_dai_links));
  7769. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  7770. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  7771. &tasha_codec);
  7772. if (rc) {
  7773. dev_dbg(dev, "%s: No DT match tasha codec\n",
  7774. __func__);
  7775. } else {
  7776. if (tasha_codec) {
  7777. memcpy(msm_qcs405_dai_links + total_links,
  7778. msm_tasha_be_dai_links,
  7779. sizeof(msm_tasha_be_dai_links));
  7780. total_links +=
  7781. ARRAY_SIZE(msm_tasha_be_dai_links);
  7782. }
  7783. }
  7784. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  7785. &va_bolero_codec);
  7786. if (rc) {
  7787. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  7788. __func__);
  7789. } else {
  7790. if (va_bolero_codec) {
  7791. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  7792. __func__);
  7793. memcpy(msm_qcs405_dai_links + total_links,
  7794. msm_va_cdc_dma_be_dai_links,
  7795. sizeof(msm_va_cdc_dma_be_dai_links));
  7796. total_links +=
  7797. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  7798. }
  7799. }
  7800. if (wsa_bolero_codec) {
  7801. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  7802. __func__);
  7803. memcpy(msm_qcs405_dai_links + total_links,
  7804. msm_wsa_cdc_dma_be_dai_links,
  7805. sizeof(msm_wsa_cdc_dma_be_dai_links));
  7806. total_links +=
  7807. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  7808. }
  7809. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  7810. &mi2s_audio_intf);
  7811. if (rc) {
  7812. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  7813. __func__);
  7814. } else {
  7815. if (mi2s_audio_intf) {
  7816. memcpy(msm_qcs405_dai_links + total_links,
  7817. msm_mi2s_be_dai_links,
  7818. sizeof(msm_mi2s_be_dai_links));
  7819. total_links +=
  7820. ARRAY_SIZE(msm_mi2s_be_dai_links);
  7821. }
  7822. }
  7823. rc = of_property_read_u32(dev->of_node, "qcom,meta-mi2s-intf",
  7824. &meta_mi2s_intf);
  7825. if (rc) {
  7826. dev_dbg(dev, "%s: No DT match META-MI2S interface\n",
  7827. __func__);
  7828. } else {
  7829. if (meta_mi2s_intf) {
  7830. memcpy(msm_qcs405_dai_links + total_links,
  7831. msm_meta_mi2s_be_dai_links,
  7832. sizeof(msm_meta_mi2s_be_dai_links));
  7833. total_links +=
  7834. ARRAY_SIZE(msm_meta_mi2s_be_dai_links);
  7835. }
  7836. }
  7837. rc = of_property_read_u32(dev->of_node,
  7838. "qcom,auxpcm-audio-intf",
  7839. &auxpcm_audio_intf);
  7840. if (rc) {
  7841. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  7842. __func__);
  7843. } else {
  7844. if (auxpcm_audio_intf) {
  7845. memcpy(msm_qcs405_dai_links + total_links,
  7846. msm_auxpcm_be_dai_links,
  7847. sizeof(msm_auxpcm_be_dai_links));
  7848. total_links +=
  7849. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  7850. }
  7851. }
  7852. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  7853. &spdif_audio_intf);
  7854. if (rc) {
  7855. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  7856. __func__);
  7857. } else {
  7858. if (spdif_audio_intf) {
  7859. memcpy(msm_qcs405_dai_links + total_links,
  7860. msm_spdif_be_dai_links,
  7861. sizeof(msm_spdif_be_dai_links));
  7862. total_links +=
  7863. ARRAY_SIZE(msm_spdif_be_dai_links);
  7864. /* enable spdif coax pins */
  7865. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  7866. spdif_pin_ctl =
  7867. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  7868. iowrite32(0xc0, spdif_cfg);
  7869. iowrite32(0x2220, spdif_pin_ctl);
  7870. }
  7871. }
  7872. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  7873. &wcn_audio_intf);
  7874. if (rc) {
  7875. dev_dbg(dev, "%s: No DT match WCN audio interface\n",
  7876. __func__);
  7877. } else {
  7878. if (wcn_audio_intf) {
  7879. memcpy(msm_qcs405_dai_links + total_links,
  7880. msm_wcn_be_dai_links,
  7881. sizeof(msm_wcn_be_dai_links));
  7882. total_links +=
  7883. ARRAY_SIZE(msm_wcn_be_dai_links);
  7884. }
  7885. }
  7886. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  7887. &afe_loopback_intf);
  7888. if (rc) {
  7889. dev_dbg(dev, "%s: No DT match AFE loopback audio interface\n",
  7890. __func__);
  7891. } else {
  7892. if (afe_loopback_intf) {
  7893. memcpy(msm_qcs405_dai_links + total_links,
  7894. msm_afe_rxtx_lb_be_dai_link,
  7895. sizeof(msm_afe_rxtx_lb_be_dai_link));
  7896. total_links +=
  7897. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  7898. }
  7899. }
  7900. dailink = msm_qcs405_dai_links;
  7901. } else if (!strcmp(match->data, "stub_codec")) {
  7902. card = &snd_soc_card_stub_msm;
  7903. memcpy(msm_stub_dai_links + total_links,
  7904. msm_stub_fe_dai_links,
  7905. sizeof(msm_stub_fe_dai_links));
  7906. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  7907. memcpy(msm_stub_dai_links + total_links,
  7908. msm_stub_be_dai_links,
  7909. sizeof(msm_stub_be_dai_links));
  7910. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  7911. dailink = msm_stub_dai_links;
  7912. }
  7913. if (card) {
  7914. card->dai_link = dailink;
  7915. card->num_links = total_links;
  7916. }
  7917. return card;
  7918. }
  7919. static int msm_wsa881x_init(struct snd_soc_component *component)
  7920. {
  7921. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7922. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7923. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  7924. SPKR_L_BOOST, SPKR_L_VI};
  7925. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  7926. SPKR_R_BOOST, SPKR_R_VI};
  7927. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  7928. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  7929. struct msm_asoc_mach_data *pdata;
  7930. struct snd_soc_dapm_context *dapm;
  7931. int ret = 0;
  7932. if (!component) {
  7933. pr_err("%s component is NULL\n", __func__);
  7934. return -EINVAL;
  7935. }
  7936. dapm = snd_soc_component_get_dapm(component);
  7937. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  7938. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  7939. __func__, component->name);
  7940. wsa881x_set_channel_map(component, &spkleft_ports[0],
  7941. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7942. &ch_rate[0], &spkleft_port_types[0]);
  7943. if (dapm->component) {
  7944. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  7945. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  7946. }
  7947. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  7948. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  7949. __func__, component->name);
  7950. wsa881x_set_channel_map(component, &spkright_ports[0],
  7951. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7952. &ch_rate[0], &spkright_port_types[0]);
  7953. if (dapm->component) {
  7954. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7955. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7956. }
  7957. } else {
  7958. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  7959. component->name);
  7960. ret = -EINVAL;
  7961. goto err;
  7962. }
  7963. pdata = snd_soc_card_get_drvdata(component->card);
  7964. if (pdata && pdata->codec_root)
  7965. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7966. component);
  7967. err:
  7968. return ret;
  7969. }
  7970. static int msm_init_wsa_dev(struct platform_device *pdev,
  7971. struct snd_soc_card *card)
  7972. {
  7973. struct device_node *wsa_of_node;
  7974. u32 wsa_max_devs;
  7975. u32 wsa_dev_cnt;
  7976. int i;
  7977. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7978. const char *wsa_auxdev_name_prefix[1];
  7979. char *dev_name_str = NULL;
  7980. int found = 0;
  7981. int ret = 0;
  7982. /* Get maximum WSA device count for this platform */
  7983. ret = of_property_read_u32(pdev->dev.of_node,
  7984. "qcom,wsa-max-devs", &wsa_max_devs);
  7985. if (ret) {
  7986. dev_info(&pdev->dev,
  7987. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7988. __func__, pdev->dev.of_node->full_name, ret);
  7989. card->num_aux_devs = 0;
  7990. return 0;
  7991. }
  7992. if (wsa_max_devs == 0) {
  7993. dev_warn(&pdev->dev,
  7994. "%s: Max WSA devices is 0 for this target?\n",
  7995. __func__);
  7996. card->num_aux_devs = 0;
  7997. return 0;
  7998. }
  7999. /* Get count of WSA device phandles for this platform */
  8000. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  8001. "qcom,wsa-devs", NULL);
  8002. if (wsa_dev_cnt == -ENOENT) {
  8003. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  8004. __func__);
  8005. goto err;
  8006. } else if (wsa_dev_cnt <= 0) {
  8007. dev_err(&pdev->dev,
  8008. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  8009. __func__, wsa_dev_cnt);
  8010. ret = -EINVAL;
  8011. goto err;
  8012. }
  8013. /*
  8014. * Expect total phandles count to be NOT less than maximum possible
  8015. * WSA count. However, if it is less, then assign same value to
  8016. * max count as well.
  8017. */
  8018. if (wsa_dev_cnt < wsa_max_devs) {
  8019. dev_dbg(&pdev->dev,
  8020. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  8021. __func__, wsa_max_devs, wsa_dev_cnt);
  8022. wsa_max_devs = wsa_dev_cnt;
  8023. }
  8024. /* Make sure prefix string passed for each WSA device */
  8025. ret = of_property_count_strings(pdev->dev.of_node,
  8026. "qcom,wsa-aux-dev-prefix");
  8027. if (ret != wsa_dev_cnt) {
  8028. dev_err(&pdev->dev,
  8029. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  8030. __func__, wsa_dev_cnt, ret);
  8031. ret = -EINVAL;
  8032. goto err;
  8033. }
  8034. /*
  8035. * Alloc mem to store phandle and index info of WSA device, if already
  8036. * registered with ALSA core
  8037. */
  8038. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  8039. sizeof(struct msm_wsa881x_dev_info),
  8040. GFP_KERNEL);
  8041. if (!wsa881x_dev_info) {
  8042. ret = -ENOMEM;
  8043. goto err;
  8044. }
  8045. /*
  8046. * search and check whether all WSA devices are already
  8047. * registered with ALSA core or not. If found a node, store
  8048. * the node and the index in a local array of struct for later
  8049. * use.
  8050. */
  8051. for (i = 0; i < wsa_dev_cnt; i++) {
  8052. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  8053. "qcom,wsa-devs", i);
  8054. if (unlikely(!wsa_of_node)) {
  8055. /* we should not be here */
  8056. dev_err(&pdev->dev,
  8057. "%s: wsa dev node is not present\n",
  8058. __func__);
  8059. ret = -EINVAL;
  8060. goto err_free_dev_info;
  8061. }
  8062. if (soc_find_component(wsa_of_node, NULL)) {
  8063. /* WSA device registered with ALSA core */
  8064. wsa881x_dev_info[found].of_node = wsa_of_node;
  8065. wsa881x_dev_info[found].index = i;
  8066. found++;
  8067. if (found == wsa_max_devs)
  8068. break;
  8069. }
  8070. }
  8071. if (found < wsa_max_devs) {
  8072. dev_err(&pdev->dev,
  8073. "%s: failed to find %d components. Found only %d\n",
  8074. __func__, wsa_max_devs, found);
  8075. return -EPROBE_DEFER;
  8076. }
  8077. dev_info(&pdev->dev,
  8078. "%s: found %d wsa881x devices registered with ALSA core\n",
  8079. __func__, found);
  8080. card->num_aux_devs = wsa_max_devs;
  8081. card->num_configs = wsa_max_devs;
  8082. /* Alloc array of AUX devs struct */
  8083. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  8084. sizeof(struct snd_soc_aux_dev),
  8085. GFP_KERNEL);
  8086. if (!msm_aux_dev) {
  8087. ret = -ENOMEM;
  8088. goto err_free_dev_info;
  8089. }
  8090. /* Alloc array of codec conf struct */
  8091. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  8092. sizeof(struct snd_soc_codec_conf),
  8093. GFP_KERNEL);
  8094. if (!msm_codec_conf) {
  8095. ret = -ENOMEM;
  8096. goto err_free_aux_dev;
  8097. }
  8098. for (i = 0; i < card->num_aux_devs; i++) {
  8099. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  8100. GFP_KERNEL);
  8101. if (!dev_name_str) {
  8102. ret = -ENOMEM;
  8103. goto err_free_cdc_conf;
  8104. }
  8105. ret = of_property_read_string_index(pdev->dev.of_node,
  8106. "qcom,wsa-aux-dev-prefix",
  8107. wsa881x_dev_info[i].index,
  8108. wsa_auxdev_name_prefix);
  8109. if (ret) {
  8110. dev_err(&pdev->dev,
  8111. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  8112. __func__, ret);
  8113. ret = -EINVAL;
  8114. goto err_free_dev_name_str;
  8115. }
  8116. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  8117. msm_aux_dev[i].name = dev_name_str;
  8118. msm_aux_dev[i].codec_name = NULL;
  8119. msm_aux_dev[i].codec_of_node =
  8120. wsa881x_dev_info[i].of_node;
  8121. msm_aux_dev[i].init = msm_wsa881x_init;
  8122. msm_codec_conf[i].dev_name = NULL;
  8123. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  8124. msm_codec_conf[i].of_node =
  8125. wsa881x_dev_info[i].of_node;
  8126. }
  8127. card->codec_conf = msm_codec_conf;
  8128. card->aux_dev = msm_aux_dev;
  8129. return 0;
  8130. err_free_dev_name_str:
  8131. devm_kfree(&pdev->dev, dev_name_str);
  8132. err_free_cdc_conf:
  8133. devm_kfree(&pdev->dev, msm_codec_conf);
  8134. err_free_aux_dev:
  8135. devm_kfree(&pdev->dev, msm_aux_dev);
  8136. err_free_dev_info:
  8137. devm_kfree(&pdev->dev, wsa881x_dev_info);
  8138. err:
  8139. return ret;
  8140. }
  8141. static int msm_csra66x0_init(struct snd_soc_component *component)
  8142. {
  8143. if (!component) {
  8144. pr_err("%s component is NULL\n", __func__);
  8145. return -EINVAL;
  8146. }
  8147. return 0;
  8148. }
  8149. static int msm_init_csra_dev(struct platform_device *pdev,
  8150. struct snd_soc_card *card)
  8151. {
  8152. struct device_node *csra_of_node;
  8153. u32 csra_max_devs;
  8154. u32 csra_dev_cnt;
  8155. char *dev_name_str = NULL;
  8156. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  8157. const char *csra_auxdev_name_prefix[1];
  8158. int i;
  8159. int found = 0;
  8160. int ret = 0;
  8161. /* Get maximum CSRA device count for this platform */
  8162. ret = of_property_read_u32(pdev->dev.of_node,
  8163. "qcom,csra-max-devs", &csra_max_devs);
  8164. if (ret) {
  8165. dev_info(&pdev->dev,
  8166. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  8167. __func__, pdev->dev.of_node->full_name, ret);
  8168. card->num_aux_devs = 0;
  8169. return 0;
  8170. }
  8171. if (csra_max_devs == 0) {
  8172. dev_warn(&pdev->dev,
  8173. "%s: Max CSRA devices is 0 for this target?\n",
  8174. __func__);
  8175. return 0;
  8176. }
  8177. /* Get count of CSRA device phandles for this platform */
  8178. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  8179. "qcom,csra-devs", NULL);
  8180. if (csra_dev_cnt == -ENOENT) {
  8181. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  8182. __func__);
  8183. goto err;
  8184. } else if (csra_dev_cnt <= 0) {
  8185. dev_err(&pdev->dev,
  8186. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  8187. __func__, csra_dev_cnt);
  8188. ret = -EINVAL;
  8189. goto err;
  8190. }
  8191. /*
  8192. * Expect total phandles count to be NOT less than maximum possible
  8193. * CSRA count. However, if it is less, then assign same value to
  8194. * max count as well.
  8195. */
  8196. if (csra_dev_cnt < csra_max_devs) {
  8197. dev_dbg(&pdev->dev,
  8198. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  8199. __func__, csra_max_devs, csra_dev_cnt);
  8200. csra_max_devs = csra_dev_cnt;
  8201. }
  8202. /* Make sure prefix string passed for each CSRA device */
  8203. ret = of_property_count_strings(pdev->dev.of_node,
  8204. "qcom,csra-aux-dev-prefix");
  8205. if (ret != csra_dev_cnt) {
  8206. dev_err(&pdev->dev,
  8207. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  8208. __func__, csra_dev_cnt, ret);
  8209. ret = -EINVAL;
  8210. goto err;
  8211. }
  8212. /*
  8213. * Alloc mem to store phandle and index info of CSRA device, if already
  8214. * registered with ALSA core
  8215. */
  8216. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  8217. sizeof(struct msm_csra66x0_dev_info),
  8218. GFP_KERNEL);
  8219. if (!csra66x0_dev_info) {
  8220. ret = -ENOMEM;
  8221. goto err;
  8222. }
  8223. /*
  8224. * search and check whether all CSRA devices are already
  8225. * registered with ALSA core or not. If found a node, store
  8226. * the node and the index in a local array of struct for later
  8227. * use.
  8228. */
  8229. for (i = 0; i < csra_dev_cnt; i++) {
  8230. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  8231. "qcom,csra-devs", i);
  8232. if (unlikely(!csra_of_node)) {
  8233. /* we should not be here */
  8234. dev_err(&pdev->dev,
  8235. "%s: csra dev node is not present\n",
  8236. __func__);
  8237. ret = -EINVAL;
  8238. goto err_free_dev_info;
  8239. }
  8240. if (soc_find_component(csra_of_node, NULL)) {
  8241. /* CSRA device registered with ALSA core */
  8242. csra66x0_dev_info[found].of_node = csra_of_node;
  8243. csra66x0_dev_info[found].index = i;
  8244. found++;
  8245. if (found == csra_max_devs)
  8246. break;
  8247. }
  8248. }
  8249. if (found < csra_max_devs) {
  8250. dev_dbg(&pdev->dev,
  8251. "%s: failed to find %d components. Found only %d\n",
  8252. __func__, csra_max_devs, found);
  8253. return -EPROBE_DEFER;
  8254. }
  8255. dev_info(&pdev->dev,
  8256. "%s: found %d csra66x0 devices registered with ALSA core\n",
  8257. __func__, found);
  8258. card->num_aux_devs = csra_max_devs;
  8259. card->num_configs = csra_max_devs;
  8260. /* Alloc array of AUX devs struct */
  8261. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  8262. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  8263. if (!msm_aux_dev) {
  8264. ret = -ENOMEM;
  8265. goto err_free_dev_info;
  8266. }
  8267. /* Alloc array of codec conf struct */
  8268. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  8269. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  8270. if (!msm_codec_conf) {
  8271. ret = -ENOMEM;
  8272. goto err_free_aux_dev;
  8273. }
  8274. for (i = 0; i < card->num_aux_devs; i++) {
  8275. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  8276. GFP_KERNEL);
  8277. if (!dev_name_str) {
  8278. ret = -ENOMEM;
  8279. goto err_free_cdc_conf;
  8280. }
  8281. ret = of_property_read_string_index(pdev->dev.of_node,
  8282. "qcom,csra-aux-dev-prefix",
  8283. csra66x0_dev_info[i].index,
  8284. csra_auxdev_name_prefix);
  8285. if (ret) {
  8286. dev_err(&pdev->dev,
  8287. "%s: failed to read csra aux dev prefix, ret = %d\n",
  8288. __func__, ret);
  8289. ret = -EINVAL;
  8290. goto err_free_dev_name_str;
  8291. }
  8292. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  8293. msm_aux_dev[i].name = dev_name_str;
  8294. msm_aux_dev[i].codec_name = NULL;
  8295. msm_aux_dev[i].codec_of_node =
  8296. csra66x0_dev_info[i].of_node;
  8297. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  8298. msm_codec_conf[i].dev_name = NULL;
  8299. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  8300. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  8301. }
  8302. card->codec_conf = msm_codec_conf;
  8303. card->aux_dev = msm_aux_dev;
  8304. return 0;
  8305. err_free_dev_name_str:
  8306. devm_kfree(&pdev->dev, dev_name_str);
  8307. err_free_cdc_conf:
  8308. devm_kfree(&pdev->dev, msm_codec_conf);
  8309. err_free_aux_dev:
  8310. devm_kfree(&pdev->dev, msm_aux_dev);
  8311. err_free_dev_info:
  8312. devm_kfree(&pdev->dev, csra66x0_dev_info);
  8313. err:
  8314. return ret;
  8315. }
  8316. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  8317. {
  8318. int count;
  8319. u32 mi2s_master_slave[MI2S_MAX];
  8320. int ret;
  8321. for (count = 0; count < MI2S_MAX; count++) {
  8322. mutex_init(&mi2s_intf_conf[count].lock);
  8323. mi2s_intf_conf[count].ref_cnt = 0;
  8324. }
  8325. ret = of_property_read_u32_array(pdev->dev.of_node,
  8326. "qcom,msm-mi2s-master",
  8327. mi2s_master_slave, MI2S_MAX);
  8328. if (ret) {
  8329. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  8330. __func__);
  8331. } else {
  8332. for (count = 0; count < MI2S_MAX; count++) {
  8333. mi2s_intf_conf[count].msm_is_mi2s_master =
  8334. mi2s_master_slave[count];
  8335. }
  8336. }
  8337. }
  8338. static void msm_i2s_auxpcm_deinit(void)
  8339. {
  8340. int count;
  8341. for (count = 0; count < MI2S_MAX; count++) {
  8342. mutex_destroy(&mi2s_intf_conf[count].lock);
  8343. mi2s_intf_conf[count].ref_cnt = 0;
  8344. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  8345. }
  8346. }
  8347. static void msm_meta_mi2s_init(struct platform_device *pdev)
  8348. {
  8349. int rc = 0;
  8350. int i = 0;
  8351. int index = 0;
  8352. bool parse_of = false;
  8353. struct snd_soc_card *card = platform_get_drvdata(pdev);
  8354. struct snd_soc_dai_link *dai_link = card->dai_link;
  8355. dev_dbg(&pdev->dev, "%s: read from DT\n", __func__);
  8356. for (index = 0; index < META_MI2S_MAX; index++) {
  8357. meta_mi2s_intf_conf[index].num_member_ports = 0;
  8358. meta_mi2s_intf_conf[index].member_port[0] = 0;
  8359. meta_mi2s_intf_conf[index].member_port[1] = 0;
  8360. meta_mi2s_intf_conf[index].member_port[2] = 0;
  8361. meta_mi2s_intf_conf[index].member_port[3] = 0;
  8362. meta_mi2s_intf_conf[index].clk_enable[0] = false;
  8363. meta_mi2s_intf_conf[index].clk_enable[1] = false;
  8364. meta_mi2s_intf_conf[index].clk_enable[2] = false;
  8365. meta_mi2s_intf_conf[index].clk_enable[3] = false;
  8366. }
  8367. /* get member port info to set matching clocks for involved ports */
  8368. for (i = 0; i < card->num_links; i++) {
  8369. if (dai_link[i].id == MSM_BACKEND_DAI_PRI_META_MI2S_RX) {
  8370. parse_of = true;
  8371. index = PRIM_META_MI2S;
  8372. } else if (dai_link[i].id == MSM_BACKEND_DAI_SEC_META_MI2S_RX) {
  8373. parse_of = true;
  8374. index = SEC_META_MI2S;
  8375. } else {
  8376. parse_of = false;
  8377. }
  8378. if (parse_of && dai_link[i].cpu_of_node) {
  8379. rc = of_property_read_u32(dai_link[i].cpu_of_node,
  8380. "qcom,msm-mi2s-num-members",
  8381. &meta_mi2s_intf_conf[index].num_member_ports);
  8382. if (rc) {
  8383. dev_err(&pdev->dev, "%s: invalid num from DT file %s\n",
  8384. __func__, "qcom,msm-mi2s-num-members");
  8385. }
  8386. if (meta_mi2s_intf_conf[index].num_member_ports >
  8387. MAX_NUM_I2S_META_PORT_MEMBER_PORTS) {
  8388. dev_err(&pdev->dev, "%s: num-members %d too large from DT file\n",
  8389. __func__,
  8390. meta_mi2s_intf_conf[index].num_member_ports);
  8391. }
  8392. if (meta_mi2s_intf_conf[index].num_member_ports > 0) {
  8393. rc = of_property_read_u32_array(
  8394. dai_link[i].cpu_of_node,
  8395. "qcom,msm-mi2s-member-id",
  8396. meta_mi2s_intf_conf[index].member_port,
  8397. meta_mi2s_intf_conf[index].num_member_ports);
  8398. if (rc) {
  8399. dev_err(&pdev->dev, "%s: member-id from DT file %s\n",
  8400. __func__,
  8401. "qcom,msm-mi2s-member-id");
  8402. }
  8403. }
  8404. dev_dbg(&pdev->dev, "dev name %s num-members=%d\n",
  8405. dev_name(&pdev->dev),
  8406. meta_mi2s_intf_conf[index].num_member_ports);
  8407. dev_dbg(&pdev->dev, "member array (%d, %d, %d, %d)\n",
  8408. meta_mi2s_intf_conf[index].member_port[0],
  8409. meta_mi2s_intf_conf[index].member_port[1],
  8410. meta_mi2s_intf_conf[index].member_port[2],
  8411. meta_mi2s_intf_conf[index].member_port[3]);
  8412. }
  8413. }
  8414. }
  8415. static int msm_scan_i2c_addr(struct platform_device *pdev,
  8416. uint32_t busnum, uint32_t addr)
  8417. {
  8418. struct i2c_adapter *adap;
  8419. u8 rbuf;
  8420. struct i2c_msg msg;
  8421. int status = 0;
  8422. adap = i2c_get_adapter(busnum);
  8423. if (!adap) {
  8424. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  8425. __func__, busnum);
  8426. return -EBUSY;
  8427. }
  8428. /* to test presence, read one byte from device */
  8429. msg.addr = addr;
  8430. msg.flags = I2C_M_RD;
  8431. msg.len = 1;
  8432. msg.buf = &rbuf;
  8433. status = i2c_transfer(adap, &msg, 1);
  8434. i2c_put_adapter(adap);
  8435. if (status != 1) {
  8436. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  8437. __func__, addr);
  8438. return -ENODEV;
  8439. }
  8440. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  8441. __func__, addr);
  8442. return 0;
  8443. }
  8444. static int msm_detect_ep92_dev(struct platform_device *pdev,
  8445. struct snd_soc_card *card)
  8446. {
  8447. int i;
  8448. uint32_t ep92_busnum = 0;
  8449. uint32_t ep92_reg = 0;
  8450. const char *ep92_name = NULL;
  8451. struct snd_soc_dai_link *dai;
  8452. int rc = 0;
  8453. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  8454. &ep92_busnum);
  8455. if (rc) {
  8456. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  8457. return 0;
  8458. }
  8459. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  8460. &ep92_reg);
  8461. if (rc) {
  8462. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  8463. return 0;
  8464. }
  8465. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  8466. &ep92_name);
  8467. if (rc) {
  8468. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  8469. return 0;
  8470. }
  8471. /* check I2C bus for connected ep92 chip */
  8472. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  8473. /* check a second time after a short delay */
  8474. msleep(20);
  8475. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  8476. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  8477. __func__);
  8478. /* continue with snd_card registration without ep92 */
  8479. return 0;
  8480. }
  8481. }
  8482. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  8483. /* update codec info in MI2S dai link */
  8484. dai = &msm_mi2s_be_dai_links[0];
  8485. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  8486. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  8487. dev_dbg(&pdev->dev,
  8488. "%s: Set Sec MI2S dai to ep92 codec\n",
  8489. __func__);
  8490. dai->codec_name = ep92_name;
  8491. dai->codec_dai_name = "ep92-hdmi";
  8492. break;
  8493. }
  8494. dai++;
  8495. }
  8496. /* update codec info in SPDIF dai link */
  8497. dai = &msm_spdif_be_dai_links[0];
  8498. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  8499. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  8500. dev_dbg(&pdev->dev,
  8501. "%s: Set Sec SPDIF dai to ep92 codec\n",
  8502. __func__);
  8503. dai->codec_name = ep92_name;
  8504. dai->codec_dai_name = "ep92-arc";
  8505. break;
  8506. }
  8507. dai++;
  8508. }
  8509. return 0;
  8510. }
  8511. static int msm_asoc_machine_probe(struct platform_device *pdev)
  8512. {
  8513. struct snd_soc_card *card;
  8514. struct msm_asoc_mach_data *pdata;
  8515. int ret;
  8516. u32 val;
  8517. const char *micb_supply_str = "tdm-vdd-micb-supply";
  8518. const char *micb_supply_str1 = "tdm-vdd-micb";
  8519. const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage";
  8520. const char *micb_current_str = "qcom,tdm-vdd-micb-current";
  8521. if (!pdev->dev.of_node) {
  8522. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  8523. return -EINVAL;
  8524. }
  8525. pdata = devm_kzalloc(&pdev->dev,
  8526. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  8527. if (!pdata)
  8528. return -ENOMEM;
  8529. /* test for ep92 HDMI bridge and update dai links accordingly */
  8530. ret = msm_detect_ep92_dev(pdev, card);
  8531. if (ret)
  8532. goto err;
  8533. card = populate_snd_card_dailinks(&pdev->dev);
  8534. if (!card) {
  8535. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  8536. ret = -EINVAL;
  8537. goto err;
  8538. }
  8539. card->dev = &pdev->dev;
  8540. platform_set_drvdata(pdev, card);
  8541. snd_soc_card_set_drvdata(card, pdata);
  8542. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  8543. if (ret) {
  8544. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  8545. ret);
  8546. goto err;
  8547. }
  8548. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  8549. if (ret) {
  8550. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  8551. ret);
  8552. goto err;
  8553. }
  8554. ret = msm_populate_dai_link_component_of_node(card);
  8555. if (ret) {
  8556. ret = -EPROBE_DEFER;
  8557. goto err;
  8558. }
  8559. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  8560. if (ret) {
  8561. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  8562. val = 0;
  8563. }
  8564. if (val) {
  8565. pdata->codec_is_csra = true;
  8566. mi2s_rx_cfg[PRIM_MI2S].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  8567. meta_mi2s_rx_cfg[PRIM_META_MI2S].bit_format =
  8568. SNDRV_PCM_FORMAT_S24_LE;
  8569. ret = msm_init_csra_dev(pdev, card);
  8570. if (ret)
  8571. goto err;
  8572. } else {
  8573. pdata->codec_is_csra = false;
  8574. ret = msm_init_wsa_dev(pdev, card);
  8575. if (ret)
  8576. goto err;
  8577. }
  8578. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8579. "qcom,cdc-dmic01-gpios", 0);
  8580. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8581. "qcom,cdc-dmic23-gpios", 0);
  8582. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8583. "qcom,cdc-dmic45-gpios", 0);
  8584. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8585. "qcom,cdc-dmic67-gpios", 0);
  8586. pdata->lineout_booster_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8587. "qcom,lineout-booster-gpio", 0);
  8588. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8589. "qcom,pri-mi2s-gpios", 0);
  8590. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8591. "qcom,sec-mi2s-gpios", 0);
  8592. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8593. "qcom,tert-mi2s-gpios", 0);
  8594. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8595. "qcom,quat-mi2s-gpios", 0);
  8596. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8597. "qcom,quin-mi2s-gpios", 0);
  8598. if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) {
  8599. pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev,
  8600. micb_supply_str1);
  8601. if (IS_ERR(pdata->tdm_micb_supply)) {
  8602. ret = PTR_ERR(pdata->tdm_micb_supply);
  8603. dev_err(&pdev->dev,
  8604. "%s:Failed to get micbias supply for TDM Mic %d\n",
  8605. __func__, ret);
  8606. }
  8607. ret = of_property_read_u32(pdev->dev.of_node,
  8608. micb_voltage_str,
  8609. &pdata->tdm_micb_voltage);
  8610. if (ret) {
  8611. dev_err(&pdev->dev,
  8612. "%s:Looking up %s property in node %s failed\n",
  8613. __func__, micb_voltage_str,
  8614. pdev->dev.of_node->full_name);
  8615. }
  8616. ret = of_property_read_u32(pdev->dev.of_node,
  8617. micb_current_str,
  8618. &pdata->tdm_micb_current);
  8619. if (ret) {
  8620. dev_err(&pdev->dev,
  8621. "%s:Looking up %s property in node %s failed\n",
  8622. __func__, micb_current_str,
  8623. pdev->dev.of_node->full_name);
  8624. }
  8625. }
  8626. ret = devm_snd_soc_register_card(&pdev->dev, card);
  8627. if (ret == -EPROBE_DEFER) {
  8628. if (codec_reg_done)
  8629. ret = -EINVAL;
  8630. goto err;
  8631. } else if (ret) {
  8632. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  8633. ret);
  8634. goto err;
  8635. }
  8636. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  8637. spdev = pdev;
  8638. ret = msm_mdf_mem_init();
  8639. if (ret)
  8640. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  8641. ret);
  8642. msm_i2s_auxpcm_init(pdev);
  8643. msm_meta_mi2s_init(pdev);
  8644. is_initial_boot = true;
  8645. return 0;
  8646. err:
  8647. return ret;
  8648. }
  8649. static int msm_asoc_machine_remove(struct platform_device *pdev)
  8650. {
  8651. audio_notifier_deregister("qcs405");
  8652. msm_i2s_auxpcm_deinit();
  8653. msm_mdf_mem_deinit();
  8654. return 0;
  8655. }
  8656. static struct platform_driver qcs405_asoc_machine_driver = {
  8657. .driver = {
  8658. .name = DRV_NAME,
  8659. .owner = THIS_MODULE,
  8660. .pm = &snd_soc_pm_ops,
  8661. .of_match_table = qcs405_asoc_machine_of_match,
  8662. .suppress_bind_attrs = true,
  8663. },
  8664. .probe = msm_asoc_machine_probe,
  8665. .remove = msm_asoc_machine_remove,
  8666. };
  8667. module_platform_driver(qcs405_asoc_machine_driver);
  8668. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  8669. MODULE_LICENSE("GPL v2");
  8670. MODULE_ALIAS("platform:" DRV_NAME);
  8671. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);