kona.c 231 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <sound/core.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/info.h>
  22. #include <soc/snd_event.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <soc/swr-common.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include "asoc/msm-cdc-pinctrl.h"
  30. #include "asoc/wcd-mbhc-v2.h"
  31. #include "codecs/wcd938x/wcd938x-mbhc.h"
  32. #include "codecs/wsa881x.h"
  33. #include "codecs/wcd938x/wcd938x.h"
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include <dt-bindings/sound/audio-codec-port-types.h>
  36. #include "codecs/bolero/wsa-macro.h"
  37. #include "kona-port-config.h"
  38. #define DRV_NAME "kona-asoc-snd"
  39. #define __CHIPSET__ "KONA "
  40. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define WCD9XXX_MBHC_DEF_RLOADS 5
  55. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  56. #define CODEC_EXT_CLK_RATE 9600000
  57. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  58. #define DEV_NAME_STR_LEN 32
  59. #define WCD_MBHC_HS_V_MAX 1600
  60. #define TDM_CHANNEL_MAX 8
  61. #define DEV_NAME_STR_LEN 32
  62. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  63. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  64. #define WSA8810_NAME_1 "wsa881x.20170211"
  65. #define WSA8810_NAME_2 "wsa881x.20170212"
  66. #define WCN_CDC_SLIM_RX_CH_MAX 2
  67. #define WCN_CDC_SLIM_TX_CH_MAX 2
  68. #define WCN_CDC_SLIM_TX_CH_MAX_LITO 3
  69. enum {
  70. RX_PATH = 0,
  71. TX_PATH,
  72. MAX_PATH,
  73. };
  74. enum {
  75. TDM_0 = 0,
  76. TDM_1,
  77. TDM_2,
  78. TDM_3,
  79. TDM_4,
  80. TDM_5,
  81. TDM_6,
  82. TDM_7,
  83. TDM_PORT_MAX,
  84. };
  85. #define TDM_MAX_SLOTS 8
  86. #define TDM_SLOT_WIDTH_BITS 32
  87. enum {
  88. TDM_PRI = 0,
  89. TDM_SEC,
  90. TDM_TERT,
  91. TDM_QUAT,
  92. TDM_QUIN,
  93. TDM_SEN,
  94. TDM_INTERFACE_MAX,
  95. };
  96. enum {
  97. PRIM_AUX_PCM = 0,
  98. SEC_AUX_PCM,
  99. TERT_AUX_PCM,
  100. QUAT_AUX_PCM,
  101. QUIN_AUX_PCM,
  102. SEN_AUX_PCM,
  103. AUX_PCM_MAX,
  104. };
  105. enum {
  106. PRIM_MI2S = 0,
  107. SEC_MI2S,
  108. TERT_MI2S,
  109. QUAT_MI2S,
  110. QUIN_MI2S,
  111. SEN_MI2S,
  112. MI2S_MAX,
  113. };
  114. enum {
  115. WSA_CDC_DMA_RX_0 = 0,
  116. WSA_CDC_DMA_RX_1,
  117. RX_CDC_DMA_RX_0,
  118. RX_CDC_DMA_RX_1,
  119. RX_CDC_DMA_RX_2,
  120. RX_CDC_DMA_RX_3,
  121. RX_CDC_DMA_RX_5,
  122. CDC_DMA_RX_MAX,
  123. };
  124. enum {
  125. WSA_CDC_DMA_TX_0 = 0,
  126. WSA_CDC_DMA_TX_1,
  127. WSA_CDC_DMA_TX_2,
  128. TX_CDC_DMA_TX_0,
  129. TX_CDC_DMA_TX_3,
  130. TX_CDC_DMA_TX_4,
  131. VA_CDC_DMA_TX_0,
  132. VA_CDC_DMA_TX_1,
  133. VA_CDC_DMA_TX_2,
  134. CDC_DMA_TX_MAX,
  135. };
  136. enum {
  137. SLIM_RX_7 = 0,
  138. SLIM_RX_MAX,
  139. };
  140. enum {
  141. SLIM_TX_7 = 0,
  142. SLIM_TX_8,
  143. SLIM_TX_MAX,
  144. };
  145. enum {
  146. AFE_LOOPBACK_TX_IDX = 0,
  147. AFE_LOOPBACK_TX_IDX_MAX,
  148. };
  149. struct msm_asoc_mach_data {
  150. struct snd_info_entry *codec_root;
  151. int usbc_en2_gpio; /* used by gpio driver API */
  152. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  153. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  154. struct device_node *dmic45_gpio_p; /* used by pinctrl API */
  155. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  156. atomic_t mi2s_gpio_ref_count[MI2S_MAX]; /* used by pinctrl API */
  157. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  158. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  159. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  160. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  161. bool is_afe_config_done;
  162. struct device_node *fsa_handle;
  163. };
  164. struct tdm_port {
  165. u32 mode;
  166. u32 channel;
  167. };
  168. struct tdm_dev_config {
  169. unsigned int tdm_slot_offset[TDM_MAX_SLOTS];
  170. };
  171. enum {
  172. EXT_DISP_RX_IDX_DP = 0,
  173. EXT_DISP_RX_IDX_DP1,
  174. EXT_DISP_RX_IDX_MAX,
  175. };
  176. struct msm_wsa881x_dev_info {
  177. struct device_node *of_node;
  178. u32 index;
  179. };
  180. struct aux_codec_dev_info {
  181. struct device_node *of_node;
  182. u32 index;
  183. };
  184. struct dev_config {
  185. u32 sample_rate;
  186. u32 bit_format;
  187. u32 channels;
  188. };
  189. /* Default configuration of slimbus channels */
  190. static struct dev_config slim_rx_cfg[] = {
  191. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  192. };
  193. static struct dev_config slim_tx_cfg[] = {
  194. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  195. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  196. };
  197. /* Default configuration of external display BE */
  198. static struct dev_config ext_disp_rx_cfg[] = {
  199. [EXT_DISP_RX_IDX_DP] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  200. [EXT_DISP_RX_IDX_DP1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  201. };
  202. static struct dev_config usb_rx_cfg = {
  203. .sample_rate = SAMPLING_RATE_48KHZ,
  204. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  205. .channels = 2,
  206. };
  207. static struct dev_config usb_tx_cfg = {
  208. .sample_rate = SAMPLING_RATE_48KHZ,
  209. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  210. .channels = 1,
  211. };
  212. static struct dev_config proxy_rx_cfg = {
  213. .sample_rate = SAMPLING_RATE_48KHZ,
  214. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  215. .channels = 2,
  216. };
  217. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  218. {
  219. AFE_API_VERSION_I2S_CONFIG,
  220. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  221. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  222. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  223. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  224. 0,
  225. },
  226. {
  227. AFE_API_VERSION_I2S_CONFIG,
  228. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  229. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  230. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  231. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  232. 0,
  233. },
  234. {
  235. AFE_API_VERSION_I2S_CONFIG,
  236. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  237. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  238. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  239. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  240. 0,
  241. },
  242. {
  243. AFE_API_VERSION_I2S_CONFIG,
  244. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  245. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  246. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  247. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  248. 0,
  249. },
  250. {
  251. AFE_API_VERSION_I2S_CONFIG,
  252. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  253. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  254. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  255. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  256. 0,
  257. },
  258. {
  259. AFE_API_VERSION_I2S_CONFIG,
  260. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  261. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  262. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  263. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  264. 0,
  265. },
  266. };
  267. struct mi2s_conf {
  268. struct mutex lock;
  269. u32 ref_cnt;
  270. u32 msm_is_mi2s_master;
  271. };
  272. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  273. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  274. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  275. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  276. };
  277. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  278. /* Default configuration of TDM channels */
  279. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  280. { /* PRI TDM */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  289. },
  290. { /* SEC TDM */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  299. },
  300. { /* TERT TDM */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  309. },
  310. { /* QUAT TDM */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  315. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  316. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  317. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  318. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  319. },
  320. { /* QUIN TDM */
  321. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  322. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  323. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  324. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  325. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  326. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  327. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  328. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  329. },
  330. { /* SEN TDM */
  331. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  332. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  333. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  334. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  335. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  336. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  337. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  338. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  339. },
  340. };
  341. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  342. { /* PRI TDM */
  343. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  344. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  345. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  346. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  347. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  348. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  349. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  350. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  351. },
  352. { /* SEC TDM */
  353. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  354. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  355. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  356. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  357. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  358. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  359. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  360. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  361. },
  362. { /* TERT TDM */
  363. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  364. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  365. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  366. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  367. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  368. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  369. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  370. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  371. },
  372. { /* QUAT TDM */
  373. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  374. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  375. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  376. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  377. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  378. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  379. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  380. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  381. },
  382. { /* QUIN TDM */
  383. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  384. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  385. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  386. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  387. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  388. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  389. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  390. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  391. },
  392. { /* SEN TDM */
  393. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  394. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  395. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  396. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  397. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  398. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  399. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  400. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  401. },
  402. };
  403. /* Default configuration of AUX PCM channels */
  404. static struct dev_config aux_pcm_rx_cfg[] = {
  405. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  406. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  407. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  408. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  409. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  410. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  411. };
  412. static struct dev_config aux_pcm_tx_cfg[] = {
  413. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  414. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  415. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  416. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  417. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  418. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  419. };
  420. /* Default configuration of MI2S channels */
  421. static struct dev_config mi2s_rx_cfg[] = {
  422. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  423. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  424. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  425. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  426. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  427. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  428. };
  429. static struct dev_config mi2s_tx_cfg[] = {
  430. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  431. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  432. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  433. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  434. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  435. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  436. };
  437. static struct tdm_dev_config pri_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  438. { /* PRI TDM */
  439. { {0, 4, 0xFFFF} }, /* RX_0 */
  440. { {8, 12, 0xFFFF} }, /* RX_1 */
  441. { {16, 20, 0xFFFF} }, /* RX_2 */
  442. { {24, 28, 0xFFFF} }, /* RX_3 */
  443. { {0xFFFF} }, /* RX_4 */
  444. { {0xFFFF} }, /* RX_5 */
  445. { {0xFFFF} }, /* RX_6 */
  446. { {0xFFFF} }, /* RX_7 */
  447. },
  448. {
  449. { {0, 4, 8, 12, 0xFFFF} }, /* TX_0 */
  450. { {8, 12, 0xFFFF} }, /* TX_1 */
  451. { {16, 20, 0xFFFF} }, /* TX_2 */
  452. { {24, 28, 0xFFFF} }, /* TX_3 */
  453. { {0xFFFF} }, /* TX_4 */
  454. { {0xFFFF} }, /* TX_5 */
  455. { {0xFFFF} }, /* TX_6 */
  456. { {0xFFFF} }, /* TX_7 */
  457. },
  458. };
  459. static struct tdm_dev_config sec_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  460. { /* SEC TDM */
  461. { {0, 4, 0xFFFF} }, /* RX_0 */
  462. { {8, 12, 0xFFFF} }, /* RX_1 */
  463. { {16, 20, 0xFFFF} }, /* RX_2 */
  464. { {24, 28, 0xFFFF} }, /* RX_3 */
  465. { {0xFFFF} }, /* RX_4 */
  466. { {0xFFFF} }, /* RX_5 */
  467. { {0xFFFF} }, /* RX_6 */
  468. { {0xFFFF} }, /* RX_7 */
  469. },
  470. {
  471. { {0, 4, 0xFFFF} }, /* TX_0 */
  472. { {8, 12, 0xFFFF} }, /* TX_1 */
  473. { {16, 20, 0xFFFF} }, /* TX_2 */
  474. { {24, 28, 0xFFFF} }, /* TX_3 */
  475. { {0xFFFF} }, /* TX_4 */
  476. { {0xFFFF} }, /* TX_5 */
  477. { {0xFFFF} }, /* TX_6 */
  478. { {0xFFFF} }, /* TX_7 */
  479. },
  480. };
  481. static struct tdm_dev_config tert_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  482. { /* TERT TDM */
  483. { {0, 4, 0xFFFF} }, /* RX_0 */
  484. { {8, 12, 0xFFFF} }, /* RX_1 */
  485. { {16, 20, 0xFFFF} }, /* RX_2 */
  486. { {24, 28, 0xFFFF} }, /* RX_3 */
  487. { {0xFFFF} }, /* RX_4 */
  488. { {0xFFFF} }, /* RX_5 */
  489. { {0xFFFF} }, /* RX_6 */
  490. { {0xFFFF} }, /* RX_7 */
  491. },
  492. {
  493. { {0, 4, 0xFFFF} }, /* TX_0 */
  494. { {8, 12, 0xFFFF} }, /* TX_1 */
  495. { {16, 20, 0xFFFF} }, /* TX_2 */
  496. { {24, 28, 0xFFFF} }, /* TX_3 */
  497. { {0xFFFF} }, /* TX_4 */
  498. { {0xFFFF} }, /* TX_5 */
  499. { {0xFFFF} }, /* TX_6 */
  500. { {0xFFFF} }, /* TX_7 */
  501. },
  502. };
  503. static struct tdm_dev_config quat_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  504. { /* QUAT TDM */
  505. { {0, 4, 0xFFFF} }, /* RX_0 */
  506. { {8, 12, 0xFFFF} }, /* RX_1 */
  507. { {16, 20, 0xFFFF} }, /* RX_2 */
  508. { {24, 28, 0xFFFF} }, /* RX_3 */
  509. { {0xFFFF} }, /* RX_4 */
  510. { {0xFFFF} }, /* RX_5 */
  511. { {0xFFFF} }, /* RX_6 */
  512. { {0xFFFF} }, /* RX_7 */
  513. },
  514. {
  515. { {0, 4, 0xFFFF} }, /* TX_0 */
  516. { {8, 12, 0xFFFF} }, /* TX_1 */
  517. { {16, 20, 0xFFFF} }, /* TX_2 */
  518. { {24, 28, 0xFFFF} }, /* TX_3 */
  519. { {0xFFFF} }, /* TX_4 */
  520. { {0xFFFF} }, /* TX_5 */
  521. { {0xFFFF} }, /* TX_6 */
  522. { {0xFFFF} }, /* TX_7 */
  523. },
  524. };
  525. static struct tdm_dev_config quin_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  526. { /* QUIN TDM */
  527. { {0, 4, 0xFFFF} }, /* RX_0 */
  528. { {8, 12, 0xFFFF} }, /* RX_1 */
  529. { {16, 20, 0xFFFF} }, /* RX_2 */
  530. { {24, 28, 0xFFFF} }, /* RX_3 */
  531. { {0xFFFF} }, /* RX_4 */
  532. { {0xFFFF} }, /* RX_5 */
  533. { {0xFFFF} }, /* RX_6 */
  534. { {0xFFFF} }, /* RX_7 */
  535. },
  536. {
  537. { {0, 4, 0xFFFF} }, /* TX_0 */
  538. { {8, 12, 0xFFFF} }, /* TX_1 */
  539. { {16, 20, 0xFFFF} }, /* TX_2 */
  540. { {24, 28, 0xFFFF} }, /* TX_3 */
  541. { {0xFFFF} }, /* TX_4 */
  542. { {0xFFFF} }, /* TX_5 */
  543. { {0xFFFF} }, /* TX_6 */
  544. { {0xFFFF} }, /* TX_7 */
  545. },
  546. };
  547. static struct tdm_dev_config sen_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  548. { /* SEN TDM */
  549. { {0, 4, 0xFFFF} }, /* RX_0 */
  550. { {8, 12, 0xFFFF} }, /* RX_1 */
  551. { {16, 20, 0xFFFF} }, /* RX_2 */
  552. { {24, 28, 0xFFFF} }, /* RX_3 */
  553. { {0xFFFF} }, /* RX_4 */
  554. { {0xFFFF} }, /* RX_5 */
  555. { {0xFFFF} }, /* RX_6 */
  556. { {0xFFFF} }, /* RX_7 */
  557. },
  558. {
  559. { {0, 4, 0xFFFF} }, /* TX_0 */
  560. { {8, 12, 0xFFFF} }, /* TX_1 */
  561. { {16, 20, 0xFFFF} }, /* TX_2 */
  562. { {24, 28, 0xFFFF} }, /* TX_3 */
  563. { {0xFFFF} }, /* TX_4 */
  564. { {0xFFFF} }, /* TX_5 */
  565. { {0xFFFF} }, /* TX_6 */
  566. { {0xFFFF} }, /* TX_7 */
  567. },
  568. };
  569. static void *tdm_cfg[TDM_INTERFACE_MAX] = {
  570. pri_tdm_dev_config,
  571. sec_tdm_dev_config,
  572. tert_tdm_dev_config,
  573. quat_tdm_dev_config,
  574. quin_tdm_dev_config,
  575. sen_tdm_dev_config,
  576. };
  577. /* Default configuration of Codec DMA Interface RX */
  578. static struct dev_config cdc_dma_rx_cfg[] = {
  579. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  580. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  581. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  582. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  583. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  584. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  585. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  586. };
  587. /* Default configuration of Codec DMA Interface TX */
  588. static struct dev_config cdc_dma_tx_cfg[] = {
  589. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  590. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  591. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  592. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  593. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  594. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  595. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  596. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  597. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  598. };
  599. static struct dev_config afe_loopback_tx_cfg[] = {
  600. [AFE_LOOPBACK_TX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  601. };
  602. static int msm_vi_feed_tx_ch = 2;
  603. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  604. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  605. "S32_LE"};
  606. static char const *cdc80_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"};
  607. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  608. "Six", "Seven", "Eight"};
  609. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  610. "KHZ_16", "KHZ_22P05",
  611. "KHZ_32", "KHZ_44P1", "KHZ_48",
  612. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  613. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  614. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  615. "Five", "Six", "Seven",
  616. "Eight"};
  617. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  618. "KHZ_48", "KHZ_176P4",
  619. "KHZ_352P8"};
  620. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  621. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  622. "Five", "Six", "Seven", "Eight"};
  623. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  624. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  625. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  626. "KHZ_48", "KHZ_96", "KHZ_192"};
  627. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  628. "Five", "Six", "Seven",
  629. "Eight"};
  630. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  631. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  632. "Five", "Six", "Seven",
  633. "Eight"};
  634. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  635. "KHZ_16", "KHZ_22P05",
  636. "KHZ_32", "KHZ_44P1", "KHZ_48",
  637. "KHZ_88P2", "KHZ_96",
  638. "KHZ_176P4", "KHZ_192",
  639. "KHZ_352P8", "KHZ_384"};
  640. static char const *cdc80_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  641. "KHZ_16", "KHZ_22P05",
  642. "KHZ_32", "KHZ_44P1", "KHZ_48",
  643. "KHZ_88P2", "KHZ_96",
  644. "KHZ_176P4", "KHZ_192"};
  645. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
  646. "S24_3LE"};
  647. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  648. "KHZ_192", "KHZ_32", "KHZ_44P1",
  649. "KHZ_88P2", "KHZ_176P4"};
  650. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  651. "KHZ_44P1", "KHZ_48",
  652. "KHZ_88P2", "KHZ_96"};
  653. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  654. "KHZ_44P1", "KHZ_48",
  655. "KHZ_88P2", "KHZ_96"};
  656. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  657. "KHZ_44P1", "KHZ_48",
  658. "KHZ_88P2", "KHZ_96"};
  659. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  660. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  661. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  662. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  663. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  664. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  665. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  666. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  667. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  668. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  669. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  670. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  671. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  672. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  673. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  674. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  675. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  676. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  677. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  678. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  679. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  680. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  681. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  682. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  683. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  684. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  685. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  686. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  687. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  688. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  689. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  690. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  691. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  692. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  693. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  694. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  695. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  696. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  697. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  698. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  699. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  700. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  701. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  702. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  703. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  704. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  705. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  706. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  707. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  708. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  709. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  710. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  711. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  712. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  713. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  714. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  715. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  716. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  717. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  718. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  719. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  720. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  721. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  722. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  723. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  724. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  725. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  726. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  727. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  728. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  729. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  730. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  731. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  732. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  733. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  734. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  735. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  736. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  737. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  738. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  739. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  740. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  741. cdc_dma_sample_rate_text);
  742. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  743. cdc_dma_sample_rate_text);
  744. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  745. cdc_dma_sample_rate_text);
  746. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  747. cdc_dma_sample_rate_text);
  748. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  749. cdc_dma_sample_rate_text);
  750. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  751. cdc_dma_sample_rate_text);
  752. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  753. cdc_dma_sample_rate_text);
  754. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  755. cdc_dma_sample_rate_text);
  756. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  757. cdc_dma_sample_rate_text);
  758. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  759. cdc_dma_sample_rate_text);
  760. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  761. cdc_dma_sample_rate_text);
  762. /* WCD9380 */
  763. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_format, cdc80_bit_format_text);
  764. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_format, cdc80_bit_format_text);
  765. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_format, cdc80_bit_format_text);
  766. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_format, cdc80_bit_format_text);
  767. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_format, cdc80_bit_format_text);
  768. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_sample_rate,
  769. cdc80_dma_sample_rate_text);
  770. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_sample_rate,
  771. cdc80_dma_sample_rate_text);
  772. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_sample_rate,
  773. cdc80_dma_sample_rate_text);
  774. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_sample_rate,
  775. cdc80_dma_sample_rate_text);
  776. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_sample_rate,
  777. cdc80_dma_sample_rate_text);
  778. /* WCD9385 */
  779. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_format, bit_format_text);
  780. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_format, bit_format_text);
  781. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_format, bit_format_text);
  782. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_format, bit_format_text);
  783. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_format, bit_format_text);
  784. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_sample_rate,
  785. cdc_dma_sample_rate_text);
  786. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_sample_rate,
  787. cdc_dma_sample_rate_text);
  788. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_sample_rate,
  789. cdc_dma_sample_rate_text);
  790. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_sample_rate,
  791. cdc_dma_sample_rate_text);
  792. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_sample_rate,
  793. cdc_dma_sample_rate_text);
  794. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  795. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  796. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  797. ext_disp_sample_rate_text);
  798. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  799. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  800. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  801. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  802. static bool is_initial_boot;
  803. static bool codec_reg_done;
  804. static struct snd_soc_aux_dev *msm_aux_dev;
  805. static struct snd_soc_codec_conf *msm_codec_conf;
  806. static struct snd_soc_card snd_soc_card_kona_msm;
  807. static int dmic_0_1_gpio_cnt;
  808. static int dmic_2_3_gpio_cnt;
  809. static int dmic_4_5_gpio_cnt;
  810. static void *def_wcd_mbhc_cal(void);
  811. /*
  812. * Need to report LINEIN
  813. * if R/L channel impedance is larger than 5K ohm
  814. */
  815. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  816. .read_fw_bin = false,
  817. .calibration = NULL,
  818. .detect_extn_cable = true,
  819. .mono_stero_detection = false,
  820. .swap_gnd_mic = NULL,
  821. .hs_ext_micbias = true,
  822. .key_code[0] = KEY_MEDIA,
  823. .key_code[1] = KEY_VOICECOMMAND,
  824. .key_code[2] = KEY_VOLUMEUP,
  825. .key_code[3] = KEY_VOLUMEDOWN,
  826. .key_code[4] = 0,
  827. .key_code[5] = 0,
  828. .key_code[6] = 0,
  829. .key_code[7] = 0,
  830. .linein_th = 5000,
  831. .moisture_en = false,
  832. .mbhc_micbias = MIC_BIAS_2,
  833. .anc_micbias = MIC_BIAS_2,
  834. .enable_anc_mic_detect = false,
  835. .moisture_duty_cycle_en = true,
  836. };
  837. static inline int param_is_mask(int p)
  838. {
  839. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  840. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  841. }
  842. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  843. int n)
  844. {
  845. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  846. }
  847. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  848. unsigned int bit)
  849. {
  850. if (bit >= SNDRV_MASK_MAX)
  851. return;
  852. if (param_is_mask(n)) {
  853. struct snd_mask *m = param_to_mask(p, n);
  854. m->bits[0] = 0;
  855. m->bits[1] = 0;
  856. m->bits[bit >> 5] |= (1 << (bit & 31));
  857. }
  858. }
  859. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  860. struct snd_ctl_elem_value *ucontrol)
  861. {
  862. int sample_rate_val = 0;
  863. switch (usb_rx_cfg.sample_rate) {
  864. case SAMPLING_RATE_384KHZ:
  865. sample_rate_val = 12;
  866. break;
  867. case SAMPLING_RATE_352P8KHZ:
  868. sample_rate_val = 11;
  869. break;
  870. case SAMPLING_RATE_192KHZ:
  871. sample_rate_val = 10;
  872. break;
  873. case SAMPLING_RATE_176P4KHZ:
  874. sample_rate_val = 9;
  875. break;
  876. case SAMPLING_RATE_96KHZ:
  877. sample_rate_val = 8;
  878. break;
  879. case SAMPLING_RATE_88P2KHZ:
  880. sample_rate_val = 7;
  881. break;
  882. case SAMPLING_RATE_48KHZ:
  883. sample_rate_val = 6;
  884. break;
  885. case SAMPLING_RATE_44P1KHZ:
  886. sample_rate_val = 5;
  887. break;
  888. case SAMPLING_RATE_32KHZ:
  889. sample_rate_val = 4;
  890. break;
  891. case SAMPLING_RATE_22P05KHZ:
  892. sample_rate_val = 3;
  893. break;
  894. case SAMPLING_RATE_16KHZ:
  895. sample_rate_val = 2;
  896. break;
  897. case SAMPLING_RATE_11P025KHZ:
  898. sample_rate_val = 1;
  899. break;
  900. case SAMPLING_RATE_8KHZ:
  901. default:
  902. sample_rate_val = 0;
  903. break;
  904. }
  905. ucontrol->value.integer.value[0] = sample_rate_val;
  906. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  907. usb_rx_cfg.sample_rate);
  908. return 0;
  909. }
  910. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  911. struct snd_ctl_elem_value *ucontrol)
  912. {
  913. switch (ucontrol->value.integer.value[0]) {
  914. case 12:
  915. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  916. break;
  917. case 11:
  918. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  919. break;
  920. case 10:
  921. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  922. break;
  923. case 9:
  924. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  925. break;
  926. case 8:
  927. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  928. break;
  929. case 7:
  930. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  931. break;
  932. case 6:
  933. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  934. break;
  935. case 5:
  936. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  937. break;
  938. case 4:
  939. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  940. break;
  941. case 3:
  942. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  943. break;
  944. case 2:
  945. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  946. break;
  947. case 1:
  948. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  949. break;
  950. case 0:
  951. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  952. break;
  953. default:
  954. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  955. break;
  956. }
  957. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  958. __func__, ucontrol->value.integer.value[0],
  959. usb_rx_cfg.sample_rate);
  960. return 0;
  961. }
  962. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  963. struct snd_ctl_elem_value *ucontrol)
  964. {
  965. int sample_rate_val = 0;
  966. switch (usb_tx_cfg.sample_rate) {
  967. case SAMPLING_RATE_384KHZ:
  968. sample_rate_val = 12;
  969. break;
  970. case SAMPLING_RATE_352P8KHZ:
  971. sample_rate_val = 11;
  972. break;
  973. case SAMPLING_RATE_192KHZ:
  974. sample_rate_val = 10;
  975. break;
  976. case SAMPLING_RATE_176P4KHZ:
  977. sample_rate_val = 9;
  978. break;
  979. case SAMPLING_RATE_96KHZ:
  980. sample_rate_val = 8;
  981. break;
  982. case SAMPLING_RATE_88P2KHZ:
  983. sample_rate_val = 7;
  984. break;
  985. case SAMPLING_RATE_48KHZ:
  986. sample_rate_val = 6;
  987. break;
  988. case SAMPLING_RATE_44P1KHZ:
  989. sample_rate_val = 5;
  990. break;
  991. case SAMPLING_RATE_32KHZ:
  992. sample_rate_val = 4;
  993. break;
  994. case SAMPLING_RATE_22P05KHZ:
  995. sample_rate_val = 3;
  996. break;
  997. case SAMPLING_RATE_16KHZ:
  998. sample_rate_val = 2;
  999. break;
  1000. case SAMPLING_RATE_11P025KHZ:
  1001. sample_rate_val = 1;
  1002. break;
  1003. case SAMPLING_RATE_8KHZ:
  1004. sample_rate_val = 0;
  1005. break;
  1006. default:
  1007. sample_rate_val = 6;
  1008. break;
  1009. }
  1010. ucontrol->value.integer.value[0] = sample_rate_val;
  1011. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1012. usb_tx_cfg.sample_rate);
  1013. return 0;
  1014. }
  1015. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1016. struct snd_ctl_elem_value *ucontrol)
  1017. {
  1018. switch (ucontrol->value.integer.value[0]) {
  1019. case 12:
  1020. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1021. break;
  1022. case 11:
  1023. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1024. break;
  1025. case 10:
  1026. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1027. break;
  1028. case 9:
  1029. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1030. break;
  1031. case 8:
  1032. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1033. break;
  1034. case 7:
  1035. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1036. break;
  1037. case 6:
  1038. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1039. break;
  1040. case 5:
  1041. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1042. break;
  1043. case 4:
  1044. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1045. break;
  1046. case 3:
  1047. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1048. break;
  1049. case 2:
  1050. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1051. break;
  1052. case 1:
  1053. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1054. break;
  1055. case 0:
  1056. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1057. break;
  1058. default:
  1059. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1060. break;
  1061. }
  1062. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1063. __func__, ucontrol->value.integer.value[0],
  1064. usb_tx_cfg.sample_rate);
  1065. return 0;
  1066. }
  1067. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  1068. struct snd_ctl_elem_value *ucontrol)
  1069. {
  1070. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  1071. afe_loopback_tx_cfg[0].channels);
  1072. ucontrol->value.enumerated.item[0] =
  1073. afe_loopback_tx_cfg[0].channels - 1;
  1074. return 0;
  1075. }
  1076. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  1077. struct snd_ctl_elem_value *ucontrol)
  1078. {
  1079. afe_loopback_tx_cfg[0].channels =
  1080. ucontrol->value.enumerated.item[0] + 1;
  1081. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  1082. afe_loopback_tx_cfg[0].channels);
  1083. return 1;
  1084. }
  1085. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1086. struct snd_ctl_elem_value *ucontrol)
  1087. {
  1088. switch (usb_rx_cfg.bit_format) {
  1089. case SNDRV_PCM_FORMAT_S32_LE:
  1090. ucontrol->value.integer.value[0] = 3;
  1091. break;
  1092. case SNDRV_PCM_FORMAT_S24_3LE:
  1093. ucontrol->value.integer.value[0] = 2;
  1094. break;
  1095. case SNDRV_PCM_FORMAT_S24_LE:
  1096. ucontrol->value.integer.value[0] = 1;
  1097. break;
  1098. case SNDRV_PCM_FORMAT_S16_LE:
  1099. default:
  1100. ucontrol->value.integer.value[0] = 0;
  1101. break;
  1102. }
  1103. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1104. __func__, usb_rx_cfg.bit_format,
  1105. ucontrol->value.integer.value[0]);
  1106. return 0;
  1107. }
  1108. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1109. struct snd_ctl_elem_value *ucontrol)
  1110. {
  1111. int rc = 0;
  1112. switch (ucontrol->value.integer.value[0]) {
  1113. case 3:
  1114. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1115. break;
  1116. case 2:
  1117. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1118. break;
  1119. case 1:
  1120. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1121. break;
  1122. case 0:
  1123. default:
  1124. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1125. break;
  1126. }
  1127. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1128. __func__, usb_rx_cfg.bit_format,
  1129. ucontrol->value.integer.value[0]);
  1130. return rc;
  1131. }
  1132. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1133. struct snd_ctl_elem_value *ucontrol)
  1134. {
  1135. switch (usb_tx_cfg.bit_format) {
  1136. case SNDRV_PCM_FORMAT_S32_LE:
  1137. ucontrol->value.integer.value[0] = 3;
  1138. break;
  1139. case SNDRV_PCM_FORMAT_S24_3LE:
  1140. ucontrol->value.integer.value[0] = 2;
  1141. break;
  1142. case SNDRV_PCM_FORMAT_S24_LE:
  1143. ucontrol->value.integer.value[0] = 1;
  1144. break;
  1145. case SNDRV_PCM_FORMAT_S16_LE:
  1146. default:
  1147. ucontrol->value.integer.value[0] = 0;
  1148. break;
  1149. }
  1150. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1151. __func__, usb_tx_cfg.bit_format,
  1152. ucontrol->value.integer.value[0]);
  1153. return 0;
  1154. }
  1155. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1156. struct snd_ctl_elem_value *ucontrol)
  1157. {
  1158. int rc = 0;
  1159. switch (ucontrol->value.integer.value[0]) {
  1160. case 3:
  1161. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1162. break;
  1163. case 2:
  1164. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1165. break;
  1166. case 1:
  1167. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1168. break;
  1169. case 0:
  1170. default:
  1171. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1172. break;
  1173. }
  1174. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1175. __func__, usb_tx_cfg.bit_format,
  1176. ucontrol->value.integer.value[0]);
  1177. return rc;
  1178. }
  1179. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1180. struct snd_ctl_elem_value *ucontrol)
  1181. {
  1182. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1183. usb_rx_cfg.channels);
  1184. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1185. return 0;
  1186. }
  1187. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1188. struct snd_ctl_elem_value *ucontrol)
  1189. {
  1190. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1191. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1192. return 1;
  1193. }
  1194. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1195. struct snd_ctl_elem_value *ucontrol)
  1196. {
  1197. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1198. usb_tx_cfg.channels);
  1199. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1200. return 0;
  1201. }
  1202. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1203. struct snd_ctl_elem_value *ucontrol)
  1204. {
  1205. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1206. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1207. return 1;
  1208. }
  1209. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  1210. struct snd_ctl_elem_value *ucontrol)
  1211. {
  1212. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  1213. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  1214. ucontrol->value.integer.value[0]);
  1215. return 0;
  1216. }
  1217. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1218. struct snd_ctl_elem_value *ucontrol)
  1219. {
  1220. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1221. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1222. return 1;
  1223. }
  1224. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  1225. {
  1226. int idx = 0;
  1227. if (strnstr(kcontrol->id.name, "Display Port RX",
  1228. sizeof("Display Port RX"))) {
  1229. idx = EXT_DISP_RX_IDX_DP;
  1230. } else if (strnstr(kcontrol->id.name, "Display Port1 RX",
  1231. sizeof("Display Port1 RX"))) {
  1232. idx = EXT_DISP_RX_IDX_DP1;
  1233. } else {
  1234. pr_err("%s: unsupported BE: %s\n",
  1235. __func__, kcontrol->id.name);
  1236. idx = -EINVAL;
  1237. }
  1238. return idx;
  1239. }
  1240. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  1241. struct snd_ctl_elem_value *ucontrol)
  1242. {
  1243. int idx = ext_disp_get_port_idx(kcontrol);
  1244. if (idx < 0)
  1245. return idx;
  1246. switch (ext_disp_rx_cfg[idx].bit_format) {
  1247. case SNDRV_PCM_FORMAT_S24_3LE:
  1248. ucontrol->value.integer.value[0] = 2;
  1249. break;
  1250. case SNDRV_PCM_FORMAT_S24_LE:
  1251. ucontrol->value.integer.value[0] = 1;
  1252. break;
  1253. case SNDRV_PCM_FORMAT_S16_LE:
  1254. default:
  1255. ucontrol->value.integer.value[0] = 0;
  1256. break;
  1257. }
  1258. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1259. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1260. ucontrol->value.integer.value[0]);
  1261. return 0;
  1262. }
  1263. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  1264. struct snd_ctl_elem_value *ucontrol)
  1265. {
  1266. int idx = ext_disp_get_port_idx(kcontrol);
  1267. if (idx < 0)
  1268. return idx;
  1269. switch (ucontrol->value.integer.value[0]) {
  1270. case 2:
  1271. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1272. break;
  1273. case 1:
  1274. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1275. break;
  1276. case 0:
  1277. default:
  1278. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1279. break;
  1280. }
  1281. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1282. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1283. ucontrol->value.integer.value[0]);
  1284. return 0;
  1285. }
  1286. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  1287. struct snd_ctl_elem_value *ucontrol)
  1288. {
  1289. int idx = ext_disp_get_port_idx(kcontrol);
  1290. if (idx < 0)
  1291. return idx;
  1292. ucontrol->value.integer.value[0] =
  1293. ext_disp_rx_cfg[idx].channels - 2;
  1294. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1295. idx, ext_disp_rx_cfg[idx].channels);
  1296. return 0;
  1297. }
  1298. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  1299. struct snd_ctl_elem_value *ucontrol)
  1300. {
  1301. int idx = ext_disp_get_port_idx(kcontrol);
  1302. if (idx < 0)
  1303. return idx;
  1304. ext_disp_rx_cfg[idx].channels =
  1305. ucontrol->value.integer.value[0] + 2;
  1306. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1307. idx, ext_disp_rx_cfg[idx].channels);
  1308. return 1;
  1309. }
  1310. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1311. struct snd_ctl_elem_value *ucontrol)
  1312. {
  1313. int sample_rate_val;
  1314. int idx = ext_disp_get_port_idx(kcontrol);
  1315. if (idx < 0)
  1316. return idx;
  1317. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1318. case SAMPLING_RATE_176P4KHZ:
  1319. sample_rate_val = 6;
  1320. break;
  1321. case SAMPLING_RATE_88P2KHZ:
  1322. sample_rate_val = 5;
  1323. break;
  1324. case SAMPLING_RATE_44P1KHZ:
  1325. sample_rate_val = 4;
  1326. break;
  1327. case SAMPLING_RATE_32KHZ:
  1328. sample_rate_val = 3;
  1329. break;
  1330. case SAMPLING_RATE_192KHZ:
  1331. sample_rate_val = 2;
  1332. break;
  1333. case SAMPLING_RATE_96KHZ:
  1334. sample_rate_val = 1;
  1335. break;
  1336. case SAMPLING_RATE_48KHZ:
  1337. default:
  1338. sample_rate_val = 0;
  1339. break;
  1340. }
  1341. ucontrol->value.integer.value[0] = sample_rate_val;
  1342. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1343. idx, ext_disp_rx_cfg[idx].sample_rate);
  1344. return 0;
  1345. }
  1346. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1347. struct snd_ctl_elem_value *ucontrol)
  1348. {
  1349. int idx = ext_disp_get_port_idx(kcontrol);
  1350. if (idx < 0)
  1351. return idx;
  1352. switch (ucontrol->value.integer.value[0]) {
  1353. case 6:
  1354. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
  1355. break;
  1356. case 5:
  1357. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
  1358. break;
  1359. case 4:
  1360. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
  1361. break;
  1362. case 3:
  1363. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
  1364. break;
  1365. case 2:
  1366. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1367. break;
  1368. case 1:
  1369. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1370. break;
  1371. case 0:
  1372. default:
  1373. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1374. break;
  1375. }
  1376. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1377. __func__, ucontrol->value.integer.value[0], idx,
  1378. ext_disp_rx_cfg[idx].sample_rate);
  1379. return 0;
  1380. }
  1381. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1382. struct snd_ctl_elem_value *ucontrol)
  1383. {
  1384. pr_debug("%s: proxy_rx channels = %d\n",
  1385. __func__, proxy_rx_cfg.channels);
  1386. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1387. return 0;
  1388. }
  1389. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1390. struct snd_ctl_elem_value *ucontrol)
  1391. {
  1392. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1393. pr_debug("%s: proxy_rx channels = %d\n",
  1394. __func__, proxy_rx_cfg.channels);
  1395. return 1;
  1396. }
  1397. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1398. struct tdm_port *port)
  1399. {
  1400. if (port) {
  1401. if (strnstr(kcontrol->id.name, "PRI",
  1402. sizeof(kcontrol->id.name))) {
  1403. port->mode = TDM_PRI;
  1404. } else if (strnstr(kcontrol->id.name, "SEC",
  1405. sizeof(kcontrol->id.name))) {
  1406. port->mode = TDM_SEC;
  1407. } else if (strnstr(kcontrol->id.name, "TERT",
  1408. sizeof(kcontrol->id.name))) {
  1409. port->mode = TDM_TERT;
  1410. } else if (strnstr(kcontrol->id.name, "QUAT",
  1411. sizeof(kcontrol->id.name))) {
  1412. port->mode = TDM_QUAT;
  1413. } else if (strnstr(kcontrol->id.name, "QUIN",
  1414. sizeof(kcontrol->id.name))) {
  1415. port->mode = TDM_QUIN;
  1416. } else if (strnstr(kcontrol->id.name, "SEN",
  1417. sizeof(kcontrol->id.name))) {
  1418. port->mode = TDM_SEN;
  1419. } else {
  1420. pr_err("%s: unsupported mode in: %s\n",
  1421. __func__, kcontrol->id.name);
  1422. return -EINVAL;
  1423. }
  1424. if (strnstr(kcontrol->id.name, "RX_0",
  1425. sizeof(kcontrol->id.name)) ||
  1426. strnstr(kcontrol->id.name, "TX_0",
  1427. sizeof(kcontrol->id.name))) {
  1428. port->channel = TDM_0;
  1429. } else if (strnstr(kcontrol->id.name, "RX_1",
  1430. sizeof(kcontrol->id.name)) ||
  1431. strnstr(kcontrol->id.name, "TX_1",
  1432. sizeof(kcontrol->id.name))) {
  1433. port->channel = TDM_1;
  1434. } else if (strnstr(kcontrol->id.name, "RX_2",
  1435. sizeof(kcontrol->id.name)) ||
  1436. strnstr(kcontrol->id.name, "TX_2",
  1437. sizeof(kcontrol->id.name))) {
  1438. port->channel = TDM_2;
  1439. } else if (strnstr(kcontrol->id.name, "RX_3",
  1440. sizeof(kcontrol->id.name)) ||
  1441. strnstr(kcontrol->id.name, "TX_3",
  1442. sizeof(kcontrol->id.name))) {
  1443. port->channel = TDM_3;
  1444. } else if (strnstr(kcontrol->id.name, "RX_4",
  1445. sizeof(kcontrol->id.name)) ||
  1446. strnstr(kcontrol->id.name, "TX_4",
  1447. sizeof(kcontrol->id.name))) {
  1448. port->channel = TDM_4;
  1449. } else if (strnstr(kcontrol->id.name, "RX_5",
  1450. sizeof(kcontrol->id.name)) ||
  1451. strnstr(kcontrol->id.name, "TX_5",
  1452. sizeof(kcontrol->id.name))) {
  1453. port->channel = TDM_5;
  1454. } else if (strnstr(kcontrol->id.name, "RX_6",
  1455. sizeof(kcontrol->id.name)) ||
  1456. strnstr(kcontrol->id.name, "TX_6",
  1457. sizeof(kcontrol->id.name))) {
  1458. port->channel = TDM_6;
  1459. } else if (strnstr(kcontrol->id.name, "RX_7",
  1460. sizeof(kcontrol->id.name)) ||
  1461. strnstr(kcontrol->id.name, "TX_7",
  1462. sizeof(kcontrol->id.name))) {
  1463. port->channel = TDM_7;
  1464. } else {
  1465. pr_err("%s: unsupported channel in: %s\n",
  1466. __func__, kcontrol->id.name);
  1467. return -EINVAL;
  1468. }
  1469. } else {
  1470. return -EINVAL;
  1471. }
  1472. return 0;
  1473. }
  1474. static int tdm_get_sample_rate(int value)
  1475. {
  1476. int sample_rate = 0;
  1477. switch (value) {
  1478. case 0:
  1479. sample_rate = SAMPLING_RATE_8KHZ;
  1480. break;
  1481. case 1:
  1482. sample_rate = SAMPLING_RATE_16KHZ;
  1483. break;
  1484. case 2:
  1485. sample_rate = SAMPLING_RATE_32KHZ;
  1486. break;
  1487. case 3:
  1488. sample_rate = SAMPLING_RATE_48KHZ;
  1489. break;
  1490. case 4:
  1491. sample_rate = SAMPLING_RATE_176P4KHZ;
  1492. break;
  1493. case 5:
  1494. sample_rate = SAMPLING_RATE_352P8KHZ;
  1495. break;
  1496. default:
  1497. sample_rate = SAMPLING_RATE_48KHZ;
  1498. break;
  1499. }
  1500. return sample_rate;
  1501. }
  1502. static int tdm_get_sample_rate_val(int sample_rate)
  1503. {
  1504. int sample_rate_val = 0;
  1505. switch (sample_rate) {
  1506. case SAMPLING_RATE_8KHZ:
  1507. sample_rate_val = 0;
  1508. break;
  1509. case SAMPLING_RATE_16KHZ:
  1510. sample_rate_val = 1;
  1511. break;
  1512. case SAMPLING_RATE_32KHZ:
  1513. sample_rate_val = 2;
  1514. break;
  1515. case SAMPLING_RATE_48KHZ:
  1516. sample_rate_val = 3;
  1517. break;
  1518. case SAMPLING_RATE_176P4KHZ:
  1519. sample_rate_val = 4;
  1520. break;
  1521. case SAMPLING_RATE_352P8KHZ:
  1522. sample_rate_val = 5;
  1523. break;
  1524. default:
  1525. sample_rate_val = 3;
  1526. break;
  1527. }
  1528. return sample_rate_val;
  1529. }
  1530. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1531. struct snd_ctl_elem_value *ucontrol)
  1532. {
  1533. struct tdm_port port;
  1534. int ret = tdm_get_port_idx(kcontrol, &port);
  1535. if (ret) {
  1536. pr_err("%s: unsupported control: %s\n",
  1537. __func__, kcontrol->id.name);
  1538. } else {
  1539. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1540. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1541. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1542. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1543. ucontrol->value.enumerated.item[0]);
  1544. }
  1545. return ret;
  1546. }
  1547. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1548. struct snd_ctl_elem_value *ucontrol)
  1549. {
  1550. struct tdm_port port;
  1551. int ret = tdm_get_port_idx(kcontrol, &port);
  1552. if (ret) {
  1553. pr_err("%s: unsupported control: %s\n",
  1554. __func__, kcontrol->id.name);
  1555. } else {
  1556. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1557. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1558. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1559. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1560. ucontrol->value.enumerated.item[0]);
  1561. }
  1562. return ret;
  1563. }
  1564. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1565. struct snd_ctl_elem_value *ucontrol)
  1566. {
  1567. struct tdm_port port;
  1568. int ret = tdm_get_port_idx(kcontrol, &port);
  1569. if (ret) {
  1570. pr_err("%s: unsupported control: %s\n",
  1571. __func__, kcontrol->id.name);
  1572. } else {
  1573. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1574. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1575. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1576. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1577. ucontrol->value.enumerated.item[0]);
  1578. }
  1579. return ret;
  1580. }
  1581. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1582. struct snd_ctl_elem_value *ucontrol)
  1583. {
  1584. struct tdm_port port;
  1585. int ret = tdm_get_port_idx(kcontrol, &port);
  1586. if (ret) {
  1587. pr_err("%s: unsupported control: %s\n",
  1588. __func__, kcontrol->id.name);
  1589. } else {
  1590. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1591. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1592. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1593. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1594. ucontrol->value.enumerated.item[0]);
  1595. }
  1596. return ret;
  1597. }
  1598. static int tdm_get_format(int value)
  1599. {
  1600. int format = 0;
  1601. switch (value) {
  1602. case 0:
  1603. format = SNDRV_PCM_FORMAT_S16_LE;
  1604. break;
  1605. case 1:
  1606. format = SNDRV_PCM_FORMAT_S24_LE;
  1607. break;
  1608. case 2:
  1609. format = SNDRV_PCM_FORMAT_S32_LE;
  1610. break;
  1611. default:
  1612. format = SNDRV_PCM_FORMAT_S16_LE;
  1613. break;
  1614. }
  1615. return format;
  1616. }
  1617. static int tdm_get_format_val(int format)
  1618. {
  1619. int value = 0;
  1620. switch (format) {
  1621. case SNDRV_PCM_FORMAT_S16_LE:
  1622. value = 0;
  1623. break;
  1624. case SNDRV_PCM_FORMAT_S24_LE:
  1625. value = 1;
  1626. break;
  1627. case SNDRV_PCM_FORMAT_S32_LE:
  1628. value = 2;
  1629. break;
  1630. default:
  1631. value = 0;
  1632. break;
  1633. }
  1634. return value;
  1635. }
  1636. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1637. struct snd_ctl_elem_value *ucontrol)
  1638. {
  1639. struct tdm_port port;
  1640. int ret = tdm_get_port_idx(kcontrol, &port);
  1641. if (ret) {
  1642. pr_err("%s: unsupported control: %s\n",
  1643. __func__, kcontrol->id.name);
  1644. } else {
  1645. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1646. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1647. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1648. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1649. ucontrol->value.enumerated.item[0]);
  1650. }
  1651. return ret;
  1652. }
  1653. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1654. struct snd_ctl_elem_value *ucontrol)
  1655. {
  1656. struct tdm_port port;
  1657. int ret = tdm_get_port_idx(kcontrol, &port);
  1658. if (ret) {
  1659. pr_err("%s: unsupported control: %s\n",
  1660. __func__, kcontrol->id.name);
  1661. } else {
  1662. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1663. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1664. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1665. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1666. ucontrol->value.enumerated.item[0]);
  1667. }
  1668. return ret;
  1669. }
  1670. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1671. struct snd_ctl_elem_value *ucontrol)
  1672. {
  1673. struct tdm_port port;
  1674. int ret = tdm_get_port_idx(kcontrol, &port);
  1675. if (ret) {
  1676. pr_err("%s: unsupported control: %s\n",
  1677. __func__, kcontrol->id.name);
  1678. } else {
  1679. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1680. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1681. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1682. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1683. ucontrol->value.enumerated.item[0]);
  1684. }
  1685. return ret;
  1686. }
  1687. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1688. struct snd_ctl_elem_value *ucontrol)
  1689. {
  1690. struct tdm_port port;
  1691. int ret = tdm_get_port_idx(kcontrol, &port);
  1692. if (ret) {
  1693. pr_err("%s: unsupported control: %s\n",
  1694. __func__, kcontrol->id.name);
  1695. } else {
  1696. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1697. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1698. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1699. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1700. ucontrol->value.enumerated.item[0]);
  1701. }
  1702. return ret;
  1703. }
  1704. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1705. struct snd_ctl_elem_value *ucontrol)
  1706. {
  1707. struct tdm_port port;
  1708. int ret = tdm_get_port_idx(kcontrol, &port);
  1709. if (ret) {
  1710. pr_err("%s: unsupported control: %s\n",
  1711. __func__, kcontrol->id.name);
  1712. } else {
  1713. ucontrol->value.enumerated.item[0] =
  1714. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1715. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1716. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1717. ucontrol->value.enumerated.item[0]);
  1718. }
  1719. return ret;
  1720. }
  1721. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1722. struct snd_ctl_elem_value *ucontrol)
  1723. {
  1724. struct tdm_port port;
  1725. int ret = tdm_get_port_idx(kcontrol, &port);
  1726. if (ret) {
  1727. pr_err("%s: unsupported control: %s\n",
  1728. __func__, kcontrol->id.name);
  1729. } else {
  1730. tdm_rx_cfg[port.mode][port.channel].channels =
  1731. ucontrol->value.enumerated.item[0] + 1;
  1732. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1733. tdm_rx_cfg[port.mode][port.channel].channels,
  1734. ucontrol->value.enumerated.item[0] + 1);
  1735. }
  1736. return ret;
  1737. }
  1738. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1739. struct snd_ctl_elem_value *ucontrol)
  1740. {
  1741. struct tdm_port port;
  1742. int ret = tdm_get_port_idx(kcontrol, &port);
  1743. if (ret) {
  1744. pr_err("%s: unsupported control: %s\n",
  1745. __func__, kcontrol->id.name);
  1746. } else {
  1747. ucontrol->value.enumerated.item[0] =
  1748. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1749. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1750. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1751. ucontrol->value.enumerated.item[0]);
  1752. }
  1753. return ret;
  1754. }
  1755. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1756. struct snd_ctl_elem_value *ucontrol)
  1757. {
  1758. struct tdm_port port;
  1759. int ret = tdm_get_port_idx(kcontrol, &port);
  1760. if (ret) {
  1761. pr_err("%s: unsupported control: %s\n",
  1762. __func__, kcontrol->id.name);
  1763. } else {
  1764. tdm_tx_cfg[port.mode][port.channel].channels =
  1765. ucontrol->value.enumerated.item[0] + 1;
  1766. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1767. tdm_tx_cfg[port.mode][port.channel].channels,
  1768. ucontrol->value.enumerated.item[0] + 1);
  1769. }
  1770. return ret;
  1771. }
  1772. static int tdm_slot_map_put(struct snd_kcontrol *kcontrol,
  1773. struct snd_ctl_elem_value *ucontrol)
  1774. {
  1775. int slot_index = 0;
  1776. int interface = ucontrol->value.integer.value[0];
  1777. int channel = ucontrol->value.integer.value[1];
  1778. unsigned int offset_val = 0;
  1779. unsigned int *slot_offset = NULL;
  1780. struct tdm_dev_config *config = NULL;
  1781. if (interface < 0 || interface >= (TDM_INTERFACE_MAX * MAX_PATH)) {
  1782. pr_err("%s: incorrect interface = %d\n", __func__, interface);
  1783. return -EINVAL;
  1784. }
  1785. if (channel < 0 || channel >= TDM_PORT_MAX) {
  1786. pr_err("%s: incorrect channel = %d\n", __func__, channel);
  1787. return -EINVAL;
  1788. }
  1789. pr_debug("%s: interface = %d, channel = %d\n", __func__,
  1790. interface, channel);
  1791. config = ((struct tdm_dev_config *) tdm_cfg[interface / MAX_PATH]) +
  1792. ((interface % MAX_PATH) * TDM_PORT_MAX) + channel;
  1793. slot_offset = config->tdm_slot_offset;
  1794. for (slot_index = 0; slot_index < TDM_MAX_SLOTS; slot_index++) {
  1795. offset_val = ucontrol->value.integer.value[MAX_PATH +
  1796. slot_index];
  1797. /* Offset value can only be 0, 4, 8, ..28 */
  1798. if (offset_val % 4 == 0 && offset_val <= 28)
  1799. slot_offset[slot_index] = offset_val;
  1800. pr_debug("%s: slot offset[%d] = %d\n", __func__,
  1801. slot_index, slot_offset[slot_index]);
  1802. }
  1803. return 0;
  1804. }
  1805. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1806. {
  1807. int idx = 0;
  1808. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1809. sizeof("PRIM_AUX_PCM"))) {
  1810. idx = PRIM_AUX_PCM;
  1811. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1812. sizeof("SEC_AUX_PCM"))) {
  1813. idx = SEC_AUX_PCM;
  1814. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1815. sizeof("TERT_AUX_PCM"))) {
  1816. idx = TERT_AUX_PCM;
  1817. } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  1818. sizeof("QUAT_AUX_PCM"))) {
  1819. idx = QUAT_AUX_PCM;
  1820. } else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  1821. sizeof("QUIN_AUX_PCM"))) {
  1822. idx = QUIN_AUX_PCM;
  1823. } else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  1824. sizeof("SEN_AUX_PCM"))) {
  1825. idx = SEN_AUX_PCM;
  1826. } else {
  1827. pr_err("%s: unsupported port: %s\n",
  1828. __func__, kcontrol->id.name);
  1829. idx = -EINVAL;
  1830. }
  1831. return idx;
  1832. }
  1833. static int aux_pcm_get_sample_rate(int value)
  1834. {
  1835. int sample_rate = 0;
  1836. switch (value) {
  1837. case 1:
  1838. sample_rate = SAMPLING_RATE_16KHZ;
  1839. break;
  1840. case 0:
  1841. default:
  1842. sample_rate = SAMPLING_RATE_8KHZ;
  1843. break;
  1844. }
  1845. return sample_rate;
  1846. }
  1847. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1848. {
  1849. int sample_rate_val = 0;
  1850. switch (sample_rate) {
  1851. case SAMPLING_RATE_16KHZ:
  1852. sample_rate_val = 1;
  1853. break;
  1854. case SAMPLING_RATE_8KHZ:
  1855. default:
  1856. sample_rate_val = 0;
  1857. break;
  1858. }
  1859. return sample_rate_val;
  1860. }
  1861. static int mi2s_auxpcm_get_format(int value)
  1862. {
  1863. int format = 0;
  1864. switch (value) {
  1865. case 0:
  1866. format = SNDRV_PCM_FORMAT_S16_LE;
  1867. break;
  1868. case 1:
  1869. format = SNDRV_PCM_FORMAT_S24_LE;
  1870. break;
  1871. case 2:
  1872. format = SNDRV_PCM_FORMAT_S24_3LE;
  1873. break;
  1874. case 3:
  1875. format = SNDRV_PCM_FORMAT_S32_LE;
  1876. break;
  1877. default:
  1878. format = SNDRV_PCM_FORMAT_S16_LE;
  1879. break;
  1880. }
  1881. return format;
  1882. }
  1883. static int mi2s_auxpcm_get_format_value(int format)
  1884. {
  1885. int value = 0;
  1886. switch (format) {
  1887. case SNDRV_PCM_FORMAT_S16_LE:
  1888. value = 0;
  1889. break;
  1890. case SNDRV_PCM_FORMAT_S24_LE:
  1891. value = 1;
  1892. break;
  1893. case SNDRV_PCM_FORMAT_S24_3LE:
  1894. value = 2;
  1895. break;
  1896. case SNDRV_PCM_FORMAT_S32_LE:
  1897. value = 3;
  1898. break;
  1899. default:
  1900. value = 0;
  1901. break;
  1902. }
  1903. return value;
  1904. }
  1905. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1906. struct snd_ctl_elem_value *ucontrol)
  1907. {
  1908. int idx = aux_pcm_get_port_idx(kcontrol);
  1909. if (idx < 0)
  1910. return idx;
  1911. ucontrol->value.enumerated.item[0] =
  1912. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1913. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1914. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1915. ucontrol->value.enumerated.item[0]);
  1916. return 0;
  1917. }
  1918. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1919. struct snd_ctl_elem_value *ucontrol)
  1920. {
  1921. int idx = aux_pcm_get_port_idx(kcontrol);
  1922. if (idx < 0)
  1923. return idx;
  1924. aux_pcm_rx_cfg[idx].sample_rate =
  1925. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1926. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1927. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1928. ucontrol->value.enumerated.item[0]);
  1929. return 0;
  1930. }
  1931. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1932. struct snd_ctl_elem_value *ucontrol)
  1933. {
  1934. int idx = aux_pcm_get_port_idx(kcontrol);
  1935. if (idx < 0)
  1936. return idx;
  1937. ucontrol->value.enumerated.item[0] =
  1938. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1939. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1940. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1941. ucontrol->value.enumerated.item[0]);
  1942. return 0;
  1943. }
  1944. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1945. struct snd_ctl_elem_value *ucontrol)
  1946. {
  1947. int idx = aux_pcm_get_port_idx(kcontrol);
  1948. if (idx < 0)
  1949. return idx;
  1950. aux_pcm_tx_cfg[idx].sample_rate =
  1951. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1952. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1953. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1954. ucontrol->value.enumerated.item[0]);
  1955. return 0;
  1956. }
  1957. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1958. struct snd_ctl_elem_value *ucontrol)
  1959. {
  1960. int idx = aux_pcm_get_port_idx(kcontrol);
  1961. if (idx < 0)
  1962. return idx;
  1963. ucontrol->value.enumerated.item[0] =
  1964. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1965. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1966. idx, aux_pcm_rx_cfg[idx].bit_format,
  1967. ucontrol->value.enumerated.item[0]);
  1968. return 0;
  1969. }
  1970. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1971. struct snd_ctl_elem_value *ucontrol)
  1972. {
  1973. int idx = aux_pcm_get_port_idx(kcontrol);
  1974. if (idx < 0)
  1975. return idx;
  1976. aux_pcm_rx_cfg[idx].bit_format =
  1977. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1978. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1979. idx, aux_pcm_rx_cfg[idx].bit_format,
  1980. ucontrol->value.enumerated.item[0]);
  1981. return 0;
  1982. }
  1983. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1984. struct snd_ctl_elem_value *ucontrol)
  1985. {
  1986. int idx = aux_pcm_get_port_idx(kcontrol);
  1987. if (idx < 0)
  1988. return idx;
  1989. ucontrol->value.enumerated.item[0] =
  1990. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1991. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1992. idx, aux_pcm_tx_cfg[idx].bit_format,
  1993. ucontrol->value.enumerated.item[0]);
  1994. return 0;
  1995. }
  1996. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1997. struct snd_ctl_elem_value *ucontrol)
  1998. {
  1999. int idx = aux_pcm_get_port_idx(kcontrol);
  2000. if (idx < 0)
  2001. return idx;
  2002. aux_pcm_tx_cfg[idx].bit_format =
  2003. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2004. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2005. idx, aux_pcm_tx_cfg[idx].bit_format,
  2006. ucontrol->value.enumerated.item[0]);
  2007. return 0;
  2008. }
  2009. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2010. {
  2011. int idx = 0;
  2012. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2013. sizeof("PRIM_MI2S_RX"))) {
  2014. idx = PRIM_MI2S;
  2015. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2016. sizeof("SEC_MI2S_RX"))) {
  2017. idx = SEC_MI2S;
  2018. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2019. sizeof("TERT_MI2S_RX"))) {
  2020. idx = TERT_MI2S;
  2021. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2022. sizeof("QUAT_MI2S_RX"))) {
  2023. idx = QUAT_MI2S;
  2024. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2025. sizeof("QUIN_MI2S_RX"))) {
  2026. idx = QUIN_MI2S;
  2027. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2028. sizeof("SEN_MI2S_RX"))) {
  2029. idx = SEN_MI2S;
  2030. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2031. sizeof("PRIM_MI2S_TX"))) {
  2032. idx = PRIM_MI2S;
  2033. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2034. sizeof("SEC_MI2S_TX"))) {
  2035. idx = SEC_MI2S;
  2036. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2037. sizeof("TERT_MI2S_TX"))) {
  2038. idx = TERT_MI2S;
  2039. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2040. sizeof("QUAT_MI2S_TX"))) {
  2041. idx = QUAT_MI2S;
  2042. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2043. sizeof("QUIN_MI2S_TX"))) {
  2044. idx = QUIN_MI2S;
  2045. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2046. sizeof("SEN_MI2S_TX"))) {
  2047. idx = SEN_MI2S;
  2048. } else {
  2049. pr_err("%s: unsupported channel: %s\n",
  2050. __func__, kcontrol->id.name);
  2051. idx = -EINVAL;
  2052. }
  2053. return idx;
  2054. }
  2055. static int mi2s_get_sample_rate(int value)
  2056. {
  2057. int sample_rate = 0;
  2058. switch (value) {
  2059. case 0:
  2060. sample_rate = SAMPLING_RATE_8KHZ;
  2061. break;
  2062. case 1:
  2063. sample_rate = SAMPLING_RATE_11P025KHZ;
  2064. break;
  2065. case 2:
  2066. sample_rate = SAMPLING_RATE_16KHZ;
  2067. break;
  2068. case 3:
  2069. sample_rate = SAMPLING_RATE_22P05KHZ;
  2070. break;
  2071. case 4:
  2072. sample_rate = SAMPLING_RATE_32KHZ;
  2073. break;
  2074. case 5:
  2075. sample_rate = SAMPLING_RATE_44P1KHZ;
  2076. break;
  2077. case 6:
  2078. sample_rate = SAMPLING_RATE_48KHZ;
  2079. break;
  2080. case 7:
  2081. sample_rate = SAMPLING_RATE_96KHZ;
  2082. break;
  2083. case 8:
  2084. sample_rate = SAMPLING_RATE_192KHZ;
  2085. break;
  2086. default:
  2087. sample_rate = SAMPLING_RATE_48KHZ;
  2088. break;
  2089. }
  2090. return sample_rate;
  2091. }
  2092. static int mi2s_get_sample_rate_val(int sample_rate)
  2093. {
  2094. int sample_rate_val = 0;
  2095. switch (sample_rate) {
  2096. case SAMPLING_RATE_8KHZ:
  2097. sample_rate_val = 0;
  2098. break;
  2099. case SAMPLING_RATE_11P025KHZ:
  2100. sample_rate_val = 1;
  2101. break;
  2102. case SAMPLING_RATE_16KHZ:
  2103. sample_rate_val = 2;
  2104. break;
  2105. case SAMPLING_RATE_22P05KHZ:
  2106. sample_rate_val = 3;
  2107. break;
  2108. case SAMPLING_RATE_32KHZ:
  2109. sample_rate_val = 4;
  2110. break;
  2111. case SAMPLING_RATE_44P1KHZ:
  2112. sample_rate_val = 5;
  2113. break;
  2114. case SAMPLING_RATE_48KHZ:
  2115. sample_rate_val = 6;
  2116. break;
  2117. case SAMPLING_RATE_96KHZ:
  2118. sample_rate_val = 7;
  2119. break;
  2120. case SAMPLING_RATE_192KHZ:
  2121. sample_rate_val = 8;
  2122. break;
  2123. default:
  2124. sample_rate_val = 6;
  2125. break;
  2126. }
  2127. return sample_rate_val;
  2128. }
  2129. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2130. struct snd_ctl_elem_value *ucontrol)
  2131. {
  2132. int idx = mi2s_get_port_idx(kcontrol);
  2133. if (idx < 0)
  2134. return idx;
  2135. ucontrol->value.enumerated.item[0] =
  2136. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2137. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2138. idx, mi2s_rx_cfg[idx].sample_rate,
  2139. ucontrol->value.enumerated.item[0]);
  2140. return 0;
  2141. }
  2142. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2143. struct snd_ctl_elem_value *ucontrol)
  2144. {
  2145. int idx = mi2s_get_port_idx(kcontrol);
  2146. if (idx < 0)
  2147. return idx;
  2148. mi2s_rx_cfg[idx].sample_rate =
  2149. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2150. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2151. idx, mi2s_rx_cfg[idx].sample_rate,
  2152. ucontrol->value.enumerated.item[0]);
  2153. return 0;
  2154. }
  2155. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2156. struct snd_ctl_elem_value *ucontrol)
  2157. {
  2158. int idx = mi2s_get_port_idx(kcontrol);
  2159. if (idx < 0)
  2160. return idx;
  2161. ucontrol->value.enumerated.item[0] =
  2162. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2163. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2164. idx, mi2s_tx_cfg[idx].sample_rate,
  2165. ucontrol->value.enumerated.item[0]);
  2166. return 0;
  2167. }
  2168. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2169. struct snd_ctl_elem_value *ucontrol)
  2170. {
  2171. int idx = mi2s_get_port_idx(kcontrol);
  2172. if (idx < 0)
  2173. return idx;
  2174. mi2s_tx_cfg[idx].sample_rate =
  2175. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2176. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2177. idx, mi2s_tx_cfg[idx].sample_rate,
  2178. ucontrol->value.enumerated.item[0]);
  2179. return 0;
  2180. }
  2181. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2182. struct snd_ctl_elem_value *ucontrol)
  2183. {
  2184. int idx = mi2s_get_port_idx(kcontrol);
  2185. if (idx < 0)
  2186. return idx;
  2187. ucontrol->value.enumerated.item[0] =
  2188. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2189. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2190. idx, mi2s_rx_cfg[idx].bit_format,
  2191. ucontrol->value.enumerated.item[0]);
  2192. return 0;
  2193. }
  2194. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2195. struct snd_ctl_elem_value *ucontrol)
  2196. {
  2197. int idx = mi2s_get_port_idx(kcontrol);
  2198. if (idx < 0)
  2199. return idx;
  2200. mi2s_rx_cfg[idx].bit_format =
  2201. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2202. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2203. idx, mi2s_rx_cfg[idx].bit_format,
  2204. ucontrol->value.enumerated.item[0]);
  2205. return 0;
  2206. }
  2207. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2208. struct snd_ctl_elem_value *ucontrol)
  2209. {
  2210. int idx = mi2s_get_port_idx(kcontrol);
  2211. if (idx < 0)
  2212. return idx;
  2213. ucontrol->value.enumerated.item[0] =
  2214. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2215. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2216. idx, mi2s_tx_cfg[idx].bit_format,
  2217. ucontrol->value.enumerated.item[0]);
  2218. return 0;
  2219. }
  2220. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2221. struct snd_ctl_elem_value *ucontrol)
  2222. {
  2223. int idx = mi2s_get_port_idx(kcontrol);
  2224. if (idx < 0)
  2225. return idx;
  2226. mi2s_tx_cfg[idx].bit_format =
  2227. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2228. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2229. idx, mi2s_tx_cfg[idx].bit_format,
  2230. ucontrol->value.enumerated.item[0]);
  2231. return 0;
  2232. }
  2233. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2234. struct snd_ctl_elem_value *ucontrol)
  2235. {
  2236. int idx = mi2s_get_port_idx(kcontrol);
  2237. if (idx < 0)
  2238. return idx;
  2239. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2240. idx, mi2s_rx_cfg[idx].channels);
  2241. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2242. return 0;
  2243. }
  2244. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2245. struct snd_ctl_elem_value *ucontrol)
  2246. {
  2247. int idx = mi2s_get_port_idx(kcontrol);
  2248. if (idx < 0)
  2249. return idx;
  2250. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2251. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2252. idx, mi2s_rx_cfg[idx].channels);
  2253. return 1;
  2254. }
  2255. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2256. struct snd_ctl_elem_value *ucontrol)
  2257. {
  2258. int idx = mi2s_get_port_idx(kcontrol);
  2259. if (idx < 0)
  2260. return idx;
  2261. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2262. idx, mi2s_tx_cfg[idx].channels);
  2263. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2264. return 0;
  2265. }
  2266. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2267. struct snd_ctl_elem_value *ucontrol)
  2268. {
  2269. int idx = mi2s_get_port_idx(kcontrol);
  2270. if (idx < 0)
  2271. return idx;
  2272. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2273. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2274. idx, mi2s_tx_cfg[idx].channels);
  2275. return 1;
  2276. }
  2277. static int msm_get_port_id(int be_id)
  2278. {
  2279. int afe_port_id = 0;
  2280. switch (be_id) {
  2281. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2282. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2283. break;
  2284. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2285. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2286. break;
  2287. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2288. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2289. break;
  2290. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2291. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2292. break;
  2293. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2294. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2295. break;
  2296. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2297. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2298. break;
  2299. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2300. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2301. break;
  2302. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2303. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2304. break;
  2305. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2306. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  2307. break;
  2308. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2309. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  2310. break;
  2311. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  2312. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  2313. break;
  2314. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  2315. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  2316. break;
  2317. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2318. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  2319. break;
  2320. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2321. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_1;
  2322. break;
  2323. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2324. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_2;
  2325. break;
  2326. default:
  2327. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  2328. afe_port_id = -EINVAL;
  2329. }
  2330. return afe_port_id;
  2331. }
  2332. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2333. {
  2334. u32 bit_per_sample = 0;
  2335. switch (bit_format) {
  2336. case SNDRV_PCM_FORMAT_S32_LE:
  2337. case SNDRV_PCM_FORMAT_S24_3LE:
  2338. case SNDRV_PCM_FORMAT_S24_LE:
  2339. bit_per_sample = 32;
  2340. break;
  2341. case SNDRV_PCM_FORMAT_S16_LE:
  2342. default:
  2343. bit_per_sample = 16;
  2344. break;
  2345. }
  2346. return bit_per_sample;
  2347. }
  2348. static void update_mi2s_clk_val(int dai_id, int stream)
  2349. {
  2350. u32 bit_per_sample = 0;
  2351. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2352. bit_per_sample =
  2353. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2354. mi2s_clk[dai_id].clk_freq_in_hz =
  2355. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2356. } else {
  2357. bit_per_sample =
  2358. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2359. mi2s_clk[dai_id].clk_freq_in_hz =
  2360. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2361. }
  2362. }
  2363. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2364. {
  2365. int ret = 0;
  2366. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2367. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2368. int port_id = 0;
  2369. int index = cpu_dai->id;
  2370. port_id = msm_get_port_id(rtd->dai_link->id);
  2371. if (port_id < 0) {
  2372. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2373. ret = port_id;
  2374. goto err;
  2375. }
  2376. if (enable) {
  2377. update_mi2s_clk_val(index, substream->stream);
  2378. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2379. mi2s_clk[index].clk_freq_in_hz);
  2380. }
  2381. mi2s_clk[index].enable = enable;
  2382. ret = afe_set_lpass_clock_v2(port_id,
  2383. &mi2s_clk[index]);
  2384. if (ret < 0) {
  2385. dev_err(rtd->card->dev,
  2386. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2387. __func__, port_id, ret);
  2388. goto err;
  2389. }
  2390. err:
  2391. return ret;
  2392. }
  2393. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  2394. {
  2395. int idx = 0;
  2396. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  2397. sizeof("WSA_CDC_DMA_RX_0")))
  2398. idx = WSA_CDC_DMA_RX_0;
  2399. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  2400. sizeof("WSA_CDC_DMA_RX_0")))
  2401. idx = WSA_CDC_DMA_RX_1;
  2402. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  2403. sizeof("RX_CDC_DMA_RX_0")))
  2404. idx = RX_CDC_DMA_RX_0;
  2405. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  2406. sizeof("RX_CDC_DMA_RX_1")))
  2407. idx = RX_CDC_DMA_RX_1;
  2408. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  2409. sizeof("RX_CDC_DMA_RX_2")))
  2410. idx = RX_CDC_DMA_RX_2;
  2411. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  2412. sizeof("RX_CDC_DMA_RX_3")))
  2413. idx = RX_CDC_DMA_RX_3;
  2414. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  2415. sizeof("RX_CDC_DMA_RX_5")))
  2416. idx = RX_CDC_DMA_RX_5;
  2417. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  2418. sizeof("WSA_CDC_DMA_TX_0")))
  2419. idx = WSA_CDC_DMA_TX_0;
  2420. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  2421. sizeof("WSA_CDC_DMA_TX_1")))
  2422. idx = WSA_CDC_DMA_TX_1;
  2423. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  2424. sizeof("WSA_CDC_DMA_TX_2")))
  2425. idx = WSA_CDC_DMA_TX_2;
  2426. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  2427. sizeof("TX_CDC_DMA_TX_0")))
  2428. idx = TX_CDC_DMA_TX_0;
  2429. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  2430. sizeof("TX_CDC_DMA_TX_3")))
  2431. idx = TX_CDC_DMA_TX_3;
  2432. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  2433. sizeof("TX_CDC_DMA_TX_4")))
  2434. idx = TX_CDC_DMA_TX_4;
  2435. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  2436. sizeof("VA_CDC_DMA_TX_0")))
  2437. idx = VA_CDC_DMA_TX_0;
  2438. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  2439. sizeof("VA_CDC_DMA_TX_1")))
  2440. idx = VA_CDC_DMA_TX_1;
  2441. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  2442. sizeof("VA_CDC_DMA_TX_2")))
  2443. idx = VA_CDC_DMA_TX_2;
  2444. else {
  2445. pr_err("%s: unsupported channel: %s\n",
  2446. __func__, kcontrol->id.name);
  2447. return -EINVAL;
  2448. }
  2449. return idx;
  2450. }
  2451. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  2452. struct snd_ctl_elem_value *ucontrol)
  2453. {
  2454. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2455. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2456. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2457. return ch_num;
  2458. }
  2459. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2460. cdc_dma_rx_cfg[ch_num].channels - 1);
  2461. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  2462. return 0;
  2463. }
  2464. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  2465. struct snd_ctl_elem_value *ucontrol)
  2466. {
  2467. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2468. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2469. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2470. return ch_num;
  2471. }
  2472. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2473. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2474. cdc_dma_rx_cfg[ch_num].channels);
  2475. return 1;
  2476. }
  2477. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  2478. struct snd_ctl_elem_value *ucontrol)
  2479. {
  2480. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2481. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2482. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2483. return ch_num;
  2484. }
  2485. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  2486. case SNDRV_PCM_FORMAT_S32_LE:
  2487. ucontrol->value.integer.value[0] = 3;
  2488. break;
  2489. case SNDRV_PCM_FORMAT_S24_3LE:
  2490. ucontrol->value.integer.value[0] = 2;
  2491. break;
  2492. case SNDRV_PCM_FORMAT_S24_LE:
  2493. ucontrol->value.integer.value[0] = 1;
  2494. break;
  2495. case SNDRV_PCM_FORMAT_S16_LE:
  2496. default:
  2497. ucontrol->value.integer.value[0] = 0;
  2498. break;
  2499. }
  2500. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2501. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2502. ucontrol->value.integer.value[0]);
  2503. return 0;
  2504. }
  2505. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  2506. struct snd_ctl_elem_value *ucontrol)
  2507. {
  2508. int rc = 0;
  2509. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2510. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2511. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2512. return ch_num;
  2513. }
  2514. switch (ucontrol->value.integer.value[0]) {
  2515. case 3:
  2516. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2517. break;
  2518. case 2:
  2519. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2520. break;
  2521. case 1:
  2522. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2523. break;
  2524. case 0:
  2525. default:
  2526. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2527. break;
  2528. }
  2529. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2530. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2531. ucontrol->value.integer.value[0]);
  2532. return rc;
  2533. }
  2534. static int cdc_dma_get_sample_rate_val(int sample_rate)
  2535. {
  2536. int sample_rate_val = 0;
  2537. switch (sample_rate) {
  2538. case SAMPLING_RATE_8KHZ:
  2539. sample_rate_val = 0;
  2540. break;
  2541. case SAMPLING_RATE_11P025KHZ:
  2542. sample_rate_val = 1;
  2543. break;
  2544. case SAMPLING_RATE_16KHZ:
  2545. sample_rate_val = 2;
  2546. break;
  2547. case SAMPLING_RATE_22P05KHZ:
  2548. sample_rate_val = 3;
  2549. break;
  2550. case SAMPLING_RATE_32KHZ:
  2551. sample_rate_val = 4;
  2552. break;
  2553. case SAMPLING_RATE_44P1KHZ:
  2554. sample_rate_val = 5;
  2555. break;
  2556. case SAMPLING_RATE_48KHZ:
  2557. sample_rate_val = 6;
  2558. break;
  2559. case SAMPLING_RATE_88P2KHZ:
  2560. sample_rate_val = 7;
  2561. break;
  2562. case SAMPLING_RATE_96KHZ:
  2563. sample_rate_val = 8;
  2564. break;
  2565. case SAMPLING_RATE_176P4KHZ:
  2566. sample_rate_val = 9;
  2567. break;
  2568. case SAMPLING_RATE_192KHZ:
  2569. sample_rate_val = 10;
  2570. break;
  2571. case SAMPLING_RATE_352P8KHZ:
  2572. sample_rate_val = 11;
  2573. break;
  2574. case SAMPLING_RATE_384KHZ:
  2575. sample_rate_val = 12;
  2576. break;
  2577. default:
  2578. sample_rate_val = 6;
  2579. break;
  2580. }
  2581. return sample_rate_val;
  2582. }
  2583. static int cdc_dma_get_sample_rate(int value)
  2584. {
  2585. int sample_rate = 0;
  2586. switch (value) {
  2587. case 0:
  2588. sample_rate = SAMPLING_RATE_8KHZ;
  2589. break;
  2590. case 1:
  2591. sample_rate = SAMPLING_RATE_11P025KHZ;
  2592. break;
  2593. case 2:
  2594. sample_rate = SAMPLING_RATE_16KHZ;
  2595. break;
  2596. case 3:
  2597. sample_rate = SAMPLING_RATE_22P05KHZ;
  2598. break;
  2599. case 4:
  2600. sample_rate = SAMPLING_RATE_32KHZ;
  2601. break;
  2602. case 5:
  2603. sample_rate = SAMPLING_RATE_44P1KHZ;
  2604. break;
  2605. case 6:
  2606. sample_rate = SAMPLING_RATE_48KHZ;
  2607. break;
  2608. case 7:
  2609. sample_rate = SAMPLING_RATE_88P2KHZ;
  2610. break;
  2611. case 8:
  2612. sample_rate = SAMPLING_RATE_96KHZ;
  2613. break;
  2614. case 9:
  2615. sample_rate = SAMPLING_RATE_176P4KHZ;
  2616. break;
  2617. case 10:
  2618. sample_rate = SAMPLING_RATE_192KHZ;
  2619. break;
  2620. case 11:
  2621. sample_rate = SAMPLING_RATE_352P8KHZ;
  2622. break;
  2623. case 12:
  2624. sample_rate = SAMPLING_RATE_384KHZ;
  2625. break;
  2626. default:
  2627. sample_rate = SAMPLING_RATE_48KHZ;
  2628. break;
  2629. }
  2630. return sample_rate;
  2631. }
  2632. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2633. struct snd_ctl_elem_value *ucontrol)
  2634. {
  2635. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2636. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2637. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2638. return ch_num;
  2639. }
  2640. ucontrol->value.enumerated.item[0] =
  2641. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2642. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2643. cdc_dma_rx_cfg[ch_num].sample_rate);
  2644. return 0;
  2645. }
  2646. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2647. struct snd_ctl_elem_value *ucontrol)
  2648. {
  2649. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2650. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2651. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2652. return ch_num;
  2653. }
  2654. cdc_dma_rx_cfg[ch_num].sample_rate =
  2655. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2656. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2657. __func__, ucontrol->value.enumerated.item[0],
  2658. cdc_dma_rx_cfg[ch_num].sample_rate);
  2659. return 0;
  2660. }
  2661. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2662. struct snd_ctl_elem_value *ucontrol)
  2663. {
  2664. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2665. if (ch_num < 0) {
  2666. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2667. return ch_num;
  2668. }
  2669. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2670. cdc_dma_tx_cfg[ch_num].channels);
  2671. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2672. return 0;
  2673. }
  2674. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2675. struct snd_ctl_elem_value *ucontrol)
  2676. {
  2677. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2678. if (ch_num < 0) {
  2679. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2680. return ch_num;
  2681. }
  2682. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2683. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2684. cdc_dma_tx_cfg[ch_num].channels);
  2685. return 1;
  2686. }
  2687. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2688. struct snd_ctl_elem_value *ucontrol)
  2689. {
  2690. int sample_rate_val;
  2691. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2692. if (ch_num < 0) {
  2693. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2694. return ch_num;
  2695. }
  2696. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2697. case SAMPLING_RATE_384KHZ:
  2698. sample_rate_val = 12;
  2699. break;
  2700. case SAMPLING_RATE_352P8KHZ:
  2701. sample_rate_val = 11;
  2702. break;
  2703. case SAMPLING_RATE_192KHZ:
  2704. sample_rate_val = 10;
  2705. break;
  2706. case SAMPLING_RATE_176P4KHZ:
  2707. sample_rate_val = 9;
  2708. break;
  2709. case SAMPLING_RATE_96KHZ:
  2710. sample_rate_val = 8;
  2711. break;
  2712. case SAMPLING_RATE_88P2KHZ:
  2713. sample_rate_val = 7;
  2714. break;
  2715. case SAMPLING_RATE_48KHZ:
  2716. sample_rate_val = 6;
  2717. break;
  2718. case SAMPLING_RATE_44P1KHZ:
  2719. sample_rate_val = 5;
  2720. break;
  2721. case SAMPLING_RATE_32KHZ:
  2722. sample_rate_val = 4;
  2723. break;
  2724. case SAMPLING_RATE_22P05KHZ:
  2725. sample_rate_val = 3;
  2726. break;
  2727. case SAMPLING_RATE_16KHZ:
  2728. sample_rate_val = 2;
  2729. break;
  2730. case SAMPLING_RATE_11P025KHZ:
  2731. sample_rate_val = 1;
  2732. break;
  2733. case SAMPLING_RATE_8KHZ:
  2734. sample_rate_val = 0;
  2735. break;
  2736. default:
  2737. sample_rate_val = 6;
  2738. break;
  2739. }
  2740. ucontrol->value.integer.value[0] = sample_rate_val;
  2741. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2742. cdc_dma_tx_cfg[ch_num].sample_rate);
  2743. return 0;
  2744. }
  2745. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2746. struct snd_ctl_elem_value *ucontrol)
  2747. {
  2748. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2749. if (ch_num < 0) {
  2750. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2751. return ch_num;
  2752. }
  2753. switch (ucontrol->value.integer.value[0]) {
  2754. case 12:
  2755. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2756. break;
  2757. case 11:
  2758. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2759. break;
  2760. case 10:
  2761. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2762. break;
  2763. case 9:
  2764. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2765. break;
  2766. case 8:
  2767. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2768. break;
  2769. case 7:
  2770. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2771. break;
  2772. case 6:
  2773. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2774. break;
  2775. case 5:
  2776. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2777. break;
  2778. case 4:
  2779. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2780. break;
  2781. case 3:
  2782. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2783. break;
  2784. case 2:
  2785. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2786. break;
  2787. case 1:
  2788. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2789. break;
  2790. case 0:
  2791. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2792. break;
  2793. default:
  2794. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2795. break;
  2796. }
  2797. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2798. __func__, ucontrol->value.integer.value[0],
  2799. cdc_dma_tx_cfg[ch_num].sample_rate);
  2800. return 0;
  2801. }
  2802. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2803. struct snd_ctl_elem_value *ucontrol)
  2804. {
  2805. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2806. if (ch_num < 0) {
  2807. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2808. return ch_num;
  2809. }
  2810. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2811. case SNDRV_PCM_FORMAT_S32_LE:
  2812. ucontrol->value.integer.value[0] = 3;
  2813. break;
  2814. case SNDRV_PCM_FORMAT_S24_3LE:
  2815. ucontrol->value.integer.value[0] = 2;
  2816. break;
  2817. case SNDRV_PCM_FORMAT_S24_LE:
  2818. ucontrol->value.integer.value[0] = 1;
  2819. break;
  2820. case SNDRV_PCM_FORMAT_S16_LE:
  2821. default:
  2822. ucontrol->value.integer.value[0] = 0;
  2823. break;
  2824. }
  2825. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2826. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2827. ucontrol->value.integer.value[0]);
  2828. return 0;
  2829. }
  2830. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2831. struct snd_ctl_elem_value *ucontrol)
  2832. {
  2833. int rc = 0;
  2834. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2835. if (ch_num < 0) {
  2836. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2837. return ch_num;
  2838. }
  2839. switch (ucontrol->value.integer.value[0]) {
  2840. case 3:
  2841. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2842. break;
  2843. case 2:
  2844. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2845. break;
  2846. case 1:
  2847. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2848. break;
  2849. case 0:
  2850. default:
  2851. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2852. break;
  2853. }
  2854. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2855. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2856. ucontrol->value.integer.value[0]);
  2857. return rc;
  2858. }
  2859. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2860. {
  2861. int idx = 0;
  2862. switch (be_id) {
  2863. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  2864. idx = WSA_CDC_DMA_RX_0;
  2865. break;
  2866. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  2867. idx = WSA_CDC_DMA_TX_0;
  2868. break;
  2869. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  2870. idx = WSA_CDC_DMA_RX_1;
  2871. break;
  2872. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  2873. idx = WSA_CDC_DMA_TX_1;
  2874. break;
  2875. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  2876. idx = WSA_CDC_DMA_TX_2;
  2877. break;
  2878. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2879. idx = RX_CDC_DMA_RX_0;
  2880. break;
  2881. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2882. idx = RX_CDC_DMA_RX_1;
  2883. break;
  2884. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2885. idx = RX_CDC_DMA_RX_2;
  2886. break;
  2887. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2888. idx = RX_CDC_DMA_RX_3;
  2889. break;
  2890. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2891. idx = RX_CDC_DMA_RX_5;
  2892. break;
  2893. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2894. idx = TX_CDC_DMA_TX_0;
  2895. break;
  2896. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2897. idx = TX_CDC_DMA_TX_3;
  2898. break;
  2899. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2900. idx = TX_CDC_DMA_TX_4;
  2901. break;
  2902. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2903. idx = VA_CDC_DMA_TX_0;
  2904. break;
  2905. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2906. idx = VA_CDC_DMA_TX_1;
  2907. break;
  2908. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2909. idx = VA_CDC_DMA_TX_2;
  2910. break;
  2911. default:
  2912. idx = RX_CDC_DMA_RX_0;
  2913. break;
  2914. }
  2915. return idx;
  2916. }
  2917. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2918. struct snd_ctl_elem_value *ucontrol)
  2919. {
  2920. /*
  2921. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2922. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2923. * value.
  2924. */
  2925. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2926. case SAMPLING_RATE_96KHZ:
  2927. ucontrol->value.integer.value[0] = 5;
  2928. break;
  2929. case SAMPLING_RATE_88P2KHZ:
  2930. ucontrol->value.integer.value[0] = 4;
  2931. break;
  2932. case SAMPLING_RATE_48KHZ:
  2933. ucontrol->value.integer.value[0] = 3;
  2934. break;
  2935. case SAMPLING_RATE_44P1KHZ:
  2936. ucontrol->value.integer.value[0] = 2;
  2937. break;
  2938. case SAMPLING_RATE_16KHZ:
  2939. ucontrol->value.integer.value[0] = 1;
  2940. break;
  2941. case SAMPLING_RATE_8KHZ:
  2942. default:
  2943. ucontrol->value.integer.value[0] = 0;
  2944. break;
  2945. }
  2946. pr_debug("%s: sample rate = %d\n", __func__,
  2947. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2948. return 0;
  2949. }
  2950. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2951. struct snd_ctl_elem_value *ucontrol)
  2952. {
  2953. switch (ucontrol->value.integer.value[0]) {
  2954. case 1:
  2955. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2956. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2957. break;
  2958. case 2:
  2959. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2960. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2961. break;
  2962. case 3:
  2963. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2964. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2965. break;
  2966. case 4:
  2967. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2968. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2969. break;
  2970. case 5:
  2971. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2972. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2973. break;
  2974. case 0:
  2975. default:
  2976. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2977. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2978. break;
  2979. }
  2980. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2981. __func__,
  2982. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2983. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2984. ucontrol->value.enumerated.item[0]);
  2985. return 0;
  2986. }
  2987. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2988. struct snd_ctl_elem_value *ucontrol)
  2989. {
  2990. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2991. case SAMPLING_RATE_96KHZ:
  2992. ucontrol->value.integer.value[0] = 5;
  2993. break;
  2994. case SAMPLING_RATE_88P2KHZ:
  2995. ucontrol->value.integer.value[0] = 4;
  2996. break;
  2997. case SAMPLING_RATE_48KHZ:
  2998. ucontrol->value.integer.value[0] = 3;
  2999. break;
  3000. case SAMPLING_RATE_44P1KHZ:
  3001. ucontrol->value.integer.value[0] = 2;
  3002. break;
  3003. case SAMPLING_RATE_16KHZ:
  3004. ucontrol->value.integer.value[0] = 1;
  3005. break;
  3006. case SAMPLING_RATE_8KHZ:
  3007. default:
  3008. ucontrol->value.integer.value[0] = 0;
  3009. break;
  3010. }
  3011. pr_debug("%s: sample rate rx = %d\n", __func__,
  3012. slim_rx_cfg[SLIM_RX_7].sample_rate);
  3013. return 0;
  3014. }
  3015. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  3016. struct snd_ctl_elem_value *ucontrol)
  3017. {
  3018. switch (ucontrol->value.integer.value[0]) {
  3019. case 1:
  3020. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  3021. break;
  3022. case 2:
  3023. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  3024. break;
  3025. case 3:
  3026. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  3027. break;
  3028. case 4:
  3029. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  3030. break;
  3031. case 5:
  3032. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  3033. break;
  3034. case 0:
  3035. default:
  3036. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  3037. break;
  3038. }
  3039. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  3040. __func__,
  3041. slim_rx_cfg[SLIM_RX_7].sample_rate,
  3042. ucontrol->value.enumerated.item[0]);
  3043. return 0;
  3044. }
  3045. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  3046. struct snd_ctl_elem_value *ucontrol)
  3047. {
  3048. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  3049. case SAMPLING_RATE_96KHZ:
  3050. ucontrol->value.integer.value[0] = 5;
  3051. break;
  3052. case SAMPLING_RATE_88P2KHZ:
  3053. ucontrol->value.integer.value[0] = 4;
  3054. break;
  3055. case SAMPLING_RATE_48KHZ:
  3056. ucontrol->value.integer.value[0] = 3;
  3057. break;
  3058. case SAMPLING_RATE_44P1KHZ:
  3059. ucontrol->value.integer.value[0] = 2;
  3060. break;
  3061. case SAMPLING_RATE_16KHZ:
  3062. ucontrol->value.integer.value[0] = 1;
  3063. break;
  3064. case SAMPLING_RATE_8KHZ:
  3065. default:
  3066. ucontrol->value.integer.value[0] = 0;
  3067. break;
  3068. }
  3069. pr_debug("%s: sample rate tx = %d\n", __func__,
  3070. slim_tx_cfg[SLIM_TX_7].sample_rate);
  3071. return 0;
  3072. }
  3073. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  3074. struct snd_ctl_elem_value *ucontrol)
  3075. {
  3076. switch (ucontrol->value.integer.value[0]) {
  3077. case 1:
  3078. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  3079. break;
  3080. case 2:
  3081. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  3082. break;
  3083. case 3:
  3084. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  3085. break;
  3086. case 4:
  3087. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  3088. break;
  3089. case 5:
  3090. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  3091. break;
  3092. case 0:
  3093. default:
  3094. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  3095. break;
  3096. }
  3097. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  3098. __func__,
  3099. slim_tx_cfg[SLIM_TX_7].sample_rate,
  3100. ucontrol->value.enumerated.item[0]);
  3101. return 0;
  3102. }
  3103. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  3104. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  3105. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3106. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  3107. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3108. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  3109. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3110. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  3111. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3112. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  3113. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3114. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  3115. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3116. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  3117. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3118. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  3119. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3120. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  3121. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3122. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  3123. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3124. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  3125. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3126. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  3127. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3128. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  3129. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3130. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  3131. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3132. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  3133. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3134. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  3135. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3136. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  3137. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3138. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  3139. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3140. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  3141. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3142. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  3143. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3144. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  3145. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3146. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  3147. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3148. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  3149. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3150. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  3151. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3152. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  3153. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3154. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  3155. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3156. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  3157. wsa_cdc_dma_rx_0_sample_rate,
  3158. cdc_dma_rx_sample_rate_get,
  3159. cdc_dma_rx_sample_rate_put),
  3160. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  3161. wsa_cdc_dma_rx_1_sample_rate,
  3162. cdc_dma_rx_sample_rate_get,
  3163. cdc_dma_rx_sample_rate_put),
  3164. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  3165. wsa_cdc_dma_tx_0_sample_rate,
  3166. cdc_dma_tx_sample_rate_get,
  3167. cdc_dma_tx_sample_rate_put),
  3168. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  3169. wsa_cdc_dma_tx_1_sample_rate,
  3170. cdc_dma_tx_sample_rate_get,
  3171. cdc_dma_tx_sample_rate_put),
  3172. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  3173. wsa_cdc_dma_tx_2_sample_rate,
  3174. cdc_dma_tx_sample_rate_get,
  3175. cdc_dma_tx_sample_rate_put),
  3176. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  3177. tx_cdc_dma_tx_0_sample_rate,
  3178. cdc_dma_tx_sample_rate_get,
  3179. cdc_dma_tx_sample_rate_put),
  3180. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  3181. tx_cdc_dma_tx_3_sample_rate,
  3182. cdc_dma_tx_sample_rate_get,
  3183. cdc_dma_tx_sample_rate_put),
  3184. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  3185. tx_cdc_dma_tx_4_sample_rate,
  3186. cdc_dma_tx_sample_rate_get,
  3187. cdc_dma_tx_sample_rate_put),
  3188. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3189. va_cdc_dma_tx_0_sample_rate,
  3190. cdc_dma_tx_sample_rate_get,
  3191. cdc_dma_tx_sample_rate_put),
  3192. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3193. va_cdc_dma_tx_1_sample_rate,
  3194. cdc_dma_tx_sample_rate_get,
  3195. cdc_dma_tx_sample_rate_put),
  3196. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  3197. va_cdc_dma_tx_2_sample_rate,
  3198. cdc_dma_tx_sample_rate_get,
  3199. cdc_dma_tx_sample_rate_put),
  3200. };
  3201. static const struct snd_kcontrol_new msm_int_wcd9380_snd_controls[] = {
  3202. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc80_dma_rx_0_format,
  3203. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3204. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc80_dma_rx_1_format,
  3205. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3206. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc80_dma_rx_2_format,
  3207. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3208. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc80_dma_rx_3_format,
  3209. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3210. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc80_dma_rx_5_format,
  3211. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3212. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  3213. rx_cdc80_dma_rx_0_sample_rate,
  3214. cdc_dma_rx_sample_rate_get,
  3215. cdc_dma_rx_sample_rate_put),
  3216. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  3217. rx_cdc80_dma_rx_1_sample_rate,
  3218. cdc_dma_rx_sample_rate_get,
  3219. cdc_dma_rx_sample_rate_put),
  3220. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  3221. rx_cdc80_dma_rx_2_sample_rate,
  3222. cdc_dma_rx_sample_rate_get,
  3223. cdc_dma_rx_sample_rate_put),
  3224. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  3225. rx_cdc80_dma_rx_3_sample_rate,
  3226. cdc_dma_rx_sample_rate_get,
  3227. cdc_dma_rx_sample_rate_put),
  3228. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  3229. rx_cdc80_dma_rx_5_sample_rate,
  3230. cdc_dma_rx_sample_rate_get,
  3231. cdc_dma_rx_sample_rate_put),
  3232. };
  3233. static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = {
  3234. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc85_dma_rx_0_format,
  3235. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3236. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc85_dma_rx_1_format,
  3237. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3238. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc85_dma_rx_2_format,
  3239. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3240. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc85_dma_rx_3_format,
  3241. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3242. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc85_dma_rx_5_format,
  3243. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3244. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  3245. rx_cdc85_dma_rx_0_sample_rate,
  3246. cdc_dma_rx_sample_rate_get,
  3247. cdc_dma_rx_sample_rate_put),
  3248. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  3249. rx_cdc85_dma_rx_1_sample_rate,
  3250. cdc_dma_rx_sample_rate_get,
  3251. cdc_dma_rx_sample_rate_put),
  3252. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  3253. rx_cdc85_dma_rx_2_sample_rate,
  3254. cdc_dma_rx_sample_rate_get,
  3255. cdc_dma_rx_sample_rate_put),
  3256. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  3257. rx_cdc85_dma_rx_3_sample_rate,
  3258. cdc_dma_rx_sample_rate_get,
  3259. cdc_dma_rx_sample_rate_put),
  3260. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  3261. rx_cdc85_dma_rx_5_sample_rate,
  3262. cdc_dma_rx_sample_rate_get,
  3263. cdc_dma_rx_sample_rate_put),
  3264. };
  3265. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  3266. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3267. usb_audio_rx_sample_rate_get,
  3268. usb_audio_rx_sample_rate_put),
  3269. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3270. usb_audio_tx_sample_rate_get,
  3271. usb_audio_tx_sample_rate_put),
  3272. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3273. tdm_rx_sample_rate_get,
  3274. tdm_rx_sample_rate_put),
  3275. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3276. tdm_rx_sample_rate_get,
  3277. tdm_rx_sample_rate_put),
  3278. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3279. tdm_rx_sample_rate_get,
  3280. tdm_rx_sample_rate_put),
  3281. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3282. tdm_rx_sample_rate_get,
  3283. tdm_rx_sample_rate_put),
  3284. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3285. tdm_rx_sample_rate_get,
  3286. tdm_rx_sample_rate_put),
  3287. SOC_ENUM_EXT("SEN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3288. tdm_rx_sample_rate_get,
  3289. tdm_rx_sample_rate_put),
  3290. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3291. tdm_tx_sample_rate_get,
  3292. tdm_tx_sample_rate_put),
  3293. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3294. tdm_tx_sample_rate_get,
  3295. tdm_tx_sample_rate_put),
  3296. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3297. tdm_tx_sample_rate_get,
  3298. tdm_tx_sample_rate_put),
  3299. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3300. tdm_tx_sample_rate_get,
  3301. tdm_tx_sample_rate_put),
  3302. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3303. tdm_tx_sample_rate_get,
  3304. tdm_tx_sample_rate_put),
  3305. SOC_ENUM_EXT("SEN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3306. tdm_tx_sample_rate_get,
  3307. tdm_tx_sample_rate_put),
  3308. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3309. aux_pcm_rx_sample_rate_get,
  3310. aux_pcm_rx_sample_rate_put),
  3311. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3312. aux_pcm_rx_sample_rate_get,
  3313. aux_pcm_rx_sample_rate_put),
  3314. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3315. aux_pcm_rx_sample_rate_get,
  3316. aux_pcm_rx_sample_rate_put),
  3317. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3318. aux_pcm_rx_sample_rate_get,
  3319. aux_pcm_rx_sample_rate_put),
  3320. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3321. aux_pcm_rx_sample_rate_get,
  3322. aux_pcm_rx_sample_rate_put),
  3323. SOC_ENUM_EXT("SEN_AUX_PCM_RX SampleRate", sen_aux_pcm_rx_sample_rate,
  3324. aux_pcm_rx_sample_rate_get,
  3325. aux_pcm_rx_sample_rate_put),
  3326. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3327. aux_pcm_tx_sample_rate_get,
  3328. aux_pcm_tx_sample_rate_put),
  3329. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3330. aux_pcm_tx_sample_rate_get,
  3331. aux_pcm_tx_sample_rate_put),
  3332. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3333. aux_pcm_tx_sample_rate_get,
  3334. aux_pcm_tx_sample_rate_put),
  3335. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3336. aux_pcm_tx_sample_rate_get,
  3337. aux_pcm_tx_sample_rate_put),
  3338. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3339. aux_pcm_tx_sample_rate_get,
  3340. aux_pcm_tx_sample_rate_put),
  3341. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3342. aux_pcm_tx_sample_rate_get,
  3343. aux_pcm_tx_sample_rate_put),
  3344. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3345. mi2s_rx_sample_rate_get,
  3346. mi2s_rx_sample_rate_put),
  3347. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3348. mi2s_rx_sample_rate_get,
  3349. mi2s_rx_sample_rate_put),
  3350. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3351. mi2s_rx_sample_rate_get,
  3352. mi2s_rx_sample_rate_put),
  3353. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3354. mi2s_rx_sample_rate_get,
  3355. mi2s_rx_sample_rate_put),
  3356. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3357. mi2s_rx_sample_rate_get,
  3358. mi2s_rx_sample_rate_put),
  3359. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3360. mi2s_rx_sample_rate_get,
  3361. mi2s_rx_sample_rate_put),
  3362. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3363. mi2s_tx_sample_rate_get,
  3364. mi2s_tx_sample_rate_put),
  3365. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3366. mi2s_tx_sample_rate_get,
  3367. mi2s_tx_sample_rate_put),
  3368. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3369. mi2s_tx_sample_rate_get,
  3370. mi2s_tx_sample_rate_put),
  3371. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3372. mi2s_tx_sample_rate_get,
  3373. mi2s_tx_sample_rate_put),
  3374. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3375. mi2s_tx_sample_rate_get,
  3376. mi2s_tx_sample_rate_put),
  3377. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3378. mi2s_tx_sample_rate_get,
  3379. mi2s_tx_sample_rate_put),
  3380. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3381. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3382. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3383. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3384. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3385. tdm_rx_format_get,
  3386. tdm_rx_format_put),
  3387. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3388. tdm_rx_format_get,
  3389. tdm_rx_format_put),
  3390. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3391. tdm_rx_format_get,
  3392. tdm_rx_format_put),
  3393. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3394. tdm_rx_format_get,
  3395. tdm_rx_format_put),
  3396. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3397. tdm_rx_format_get,
  3398. tdm_rx_format_put),
  3399. SOC_ENUM_EXT("SEN_TDM_RX_0 Format", tdm_rx_format,
  3400. tdm_rx_format_get,
  3401. tdm_rx_format_put),
  3402. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3403. tdm_tx_format_get,
  3404. tdm_tx_format_put),
  3405. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3406. tdm_tx_format_get,
  3407. tdm_tx_format_put),
  3408. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3409. tdm_tx_format_get,
  3410. tdm_tx_format_put),
  3411. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3412. tdm_tx_format_get,
  3413. tdm_tx_format_put),
  3414. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3415. tdm_tx_format_get,
  3416. tdm_tx_format_put),
  3417. SOC_ENUM_EXT("SEN_TDM_TX_0 Format", tdm_tx_format,
  3418. tdm_tx_format_get,
  3419. tdm_tx_format_put),
  3420. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3421. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3422. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3423. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3424. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3425. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3426. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3427. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3428. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3429. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3430. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3431. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3432. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3433. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3434. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3435. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3436. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3437. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3438. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3439. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3440. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3441. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3442. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3443. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3444. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3445. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3446. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3447. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3448. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3449. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3450. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3451. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3452. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3453. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3454. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3455. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3456. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3457. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3458. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3459. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3460. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3461. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3462. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3463. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3464. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3465. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3466. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3467. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3468. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3469. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3470. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3471. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3472. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3473. proxy_rx_ch_get, proxy_rx_ch_put),
  3474. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3475. tdm_rx_ch_get,
  3476. tdm_rx_ch_put),
  3477. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3478. tdm_rx_ch_get,
  3479. tdm_rx_ch_put),
  3480. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3481. tdm_rx_ch_get,
  3482. tdm_rx_ch_put),
  3483. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3484. tdm_rx_ch_get,
  3485. tdm_rx_ch_put),
  3486. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3487. tdm_rx_ch_get,
  3488. tdm_rx_ch_put),
  3489. SOC_ENUM_EXT("SEN_TDM_RX_0 Channels", tdm_rx_chs,
  3490. tdm_rx_ch_get,
  3491. tdm_rx_ch_put),
  3492. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3493. tdm_tx_ch_get,
  3494. tdm_tx_ch_put),
  3495. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3496. tdm_tx_ch_get,
  3497. tdm_tx_ch_put),
  3498. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3499. tdm_tx_ch_get,
  3500. tdm_tx_ch_put),
  3501. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3502. tdm_tx_ch_get,
  3503. tdm_tx_ch_put),
  3504. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3505. tdm_tx_ch_get,
  3506. tdm_tx_ch_put),
  3507. SOC_ENUM_EXT("SEN_TDM_TX_0 Channels", tdm_tx_chs,
  3508. tdm_tx_ch_get,
  3509. tdm_tx_ch_put),
  3510. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3511. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3512. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3513. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3514. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3515. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3516. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3517. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3518. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3519. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3520. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3521. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3522. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3523. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3524. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3525. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3526. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3527. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3528. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3529. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3530. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3531. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3532. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3533. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3534. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  3535. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  3536. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  3537. ext_disp_rx_format_get, ext_disp_rx_format_put),
  3538. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  3539. ext_disp_rx_sample_rate_get,
  3540. ext_disp_rx_sample_rate_put),
  3541. SOC_ENUM_EXT("Display Port1 RX Channels", ext_disp_rx_chs,
  3542. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  3543. SOC_ENUM_EXT("Display Port1 RX Bit Format", ext_disp_rx_format,
  3544. ext_disp_rx_format_get, ext_disp_rx_format_put),
  3545. SOC_ENUM_EXT("Display Port1 RX SampleRate", ext_disp_rx_sample_rate,
  3546. ext_disp_rx_sample_rate_get,
  3547. ext_disp_rx_sample_rate_put),
  3548. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3549. msm_bt_sample_rate_get,
  3550. msm_bt_sample_rate_put),
  3551. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  3552. msm_bt_sample_rate_rx_get,
  3553. msm_bt_sample_rate_rx_put),
  3554. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  3555. msm_bt_sample_rate_tx_get,
  3556. msm_bt_sample_rate_tx_put),
  3557. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  3558. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  3559. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3560. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3561. SOC_SINGLE_MULTI_EXT("TDM Slot Map", SND_SOC_NOPM, 0, 255, 0,
  3562. TDM_MAX_SLOTS + MAX_PATH, NULL, tdm_slot_map_put),
  3563. };
  3564. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3565. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3566. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3567. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3568. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3569. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3570. aux_pcm_rx_sample_rate_get,
  3571. aux_pcm_rx_sample_rate_put),
  3572. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3573. aux_pcm_tx_sample_rate_get,
  3574. aux_pcm_tx_sample_rate_put),
  3575. };
  3576. static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
  3577. {
  3578. int idx;
  3579. switch (be_id) {
  3580. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3581. idx = EXT_DISP_RX_IDX_DP;
  3582. break;
  3583. case MSM_BACKEND_DAI_DISPLAY_PORT_RX_1:
  3584. idx = EXT_DISP_RX_IDX_DP1;
  3585. break;
  3586. default:
  3587. pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
  3588. idx = -EINVAL;
  3589. break;
  3590. }
  3591. return idx;
  3592. }
  3593. static int kona_send_island_va_config(int32_t be_id)
  3594. {
  3595. int rc = 0;
  3596. int port_id = 0xFFFF;
  3597. port_id = msm_get_port_id(be_id);
  3598. if (port_id < 0) {
  3599. pr_err("%s: Invalid island interface, be_id: %d\n",
  3600. __func__, be_id);
  3601. rc = -EINVAL;
  3602. } else {
  3603. /*
  3604. * send island mode config
  3605. * This should be the first configuration
  3606. */
  3607. rc = afe_send_port_island_mode(port_id);
  3608. if (rc)
  3609. pr_err("%s: afe send island mode failed %d\n",
  3610. __func__, rc);
  3611. }
  3612. return rc;
  3613. }
  3614. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3615. struct snd_pcm_hw_params *params)
  3616. {
  3617. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3618. struct snd_interval *rate = hw_param_interval(params,
  3619. SNDRV_PCM_HW_PARAM_RATE);
  3620. struct snd_interval *channels = hw_param_interval(params,
  3621. SNDRV_PCM_HW_PARAM_CHANNELS);
  3622. int idx = 0, rc = 0;
  3623. pr_debug("%s: dai_id= %d, format = %d, rate = %d\n",
  3624. __func__, dai_link->id, params_format(params),
  3625. params_rate(params));
  3626. switch (dai_link->id) {
  3627. case MSM_BACKEND_DAI_USB_RX:
  3628. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3629. usb_rx_cfg.bit_format);
  3630. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3631. channels->min = channels->max = usb_rx_cfg.channels;
  3632. break;
  3633. case MSM_BACKEND_DAI_USB_TX:
  3634. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3635. usb_tx_cfg.bit_format);
  3636. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3637. channels->min = channels->max = usb_tx_cfg.channels;
  3638. break;
  3639. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3640. case MSM_BACKEND_DAI_DISPLAY_PORT_RX_1:
  3641. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  3642. if (idx < 0) {
  3643. pr_err("%s: Incorrect ext disp idx %d\n",
  3644. __func__, idx);
  3645. rc = idx;
  3646. goto done;
  3647. }
  3648. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3649. ext_disp_rx_cfg[idx].bit_format);
  3650. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  3651. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  3652. break;
  3653. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3654. channels->min = channels->max = proxy_rx_cfg.channels;
  3655. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3656. break;
  3657. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3658. channels->min = channels->max =
  3659. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3660. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3661. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3662. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3663. break;
  3664. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3665. channels->min = channels->max =
  3666. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3667. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3668. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3669. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3670. break;
  3671. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3672. channels->min = channels->max =
  3673. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3674. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3675. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3676. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3677. break;
  3678. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3679. channels->min = channels->max =
  3680. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3681. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3682. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3683. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3684. break;
  3685. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3686. channels->min = channels->max =
  3687. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3688. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3689. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3690. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3691. break;
  3692. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3693. channels->min = channels->max =
  3694. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3695. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3696. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3697. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3698. break;
  3699. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3700. channels->min = channels->max =
  3701. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3702. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3703. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3704. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3705. break;
  3706. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3707. channels->min = channels->max =
  3708. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3709. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3710. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3711. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3712. break;
  3713. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3714. channels->min = channels->max =
  3715. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3716. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3717. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3718. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3719. break;
  3720. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3721. channels->min = channels->max =
  3722. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3723. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3724. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3725. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3726. break;
  3727. case MSM_BACKEND_DAI_SEN_TDM_RX_0:
  3728. channels->min = channels->max =
  3729. tdm_rx_cfg[TDM_SEN][TDM_0].channels;
  3730. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3731. tdm_rx_cfg[TDM_SEN][TDM_0].bit_format);
  3732. rate->min = rate->max = tdm_rx_cfg[TDM_SEN][TDM_0].sample_rate;
  3733. break;
  3734. case MSM_BACKEND_DAI_SEN_TDM_TX_0:
  3735. channels->min = channels->max =
  3736. tdm_tx_cfg[TDM_SEN][TDM_0].channels;
  3737. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3738. tdm_tx_cfg[TDM_SEN][TDM_0].bit_format);
  3739. rate->min = rate->max = tdm_tx_cfg[TDM_SEN][TDM_0].sample_rate;
  3740. break;
  3741. case MSM_BACKEND_DAI_AUXPCM_RX:
  3742. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3743. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3744. rate->min = rate->max =
  3745. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3746. channels->min = channels->max =
  3747. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3748. break;
  3749. case MSM_BACKEND_DAI_AUXPCM_TX:
  3750. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3751. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3752. rate->min = rate->max =
  3753. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3754. channels->min = channels->max =
  3755. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3756. break;
  3757. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3758. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3759. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3760. rate->min = rate->max =
  3761. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3762. channels->min = channels->max =
  3763. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3764. break;
  3765. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3766. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3767. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3768. rate->min = rate->max =
  3769. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3770. channels->min = channels->max =
  3771. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3772. break;
  3773. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3774. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3775. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3776. rate->min = rate->max =
  3777. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3778. channels->min = channels->max =
  3779. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3780. break;
  3781. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3782. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3783. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3784. rate->min = rate->max =
  3785. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3786. channels->min = channels->max =
  3787. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3788. break;
  3789. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3790. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3791. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3792. rate->min = rate->max =
  3793. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3794. channels->min = channels->max =
  3795. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3796. break;
  3797. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3798. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3799. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3800. rate->min = rate->max =
  3801. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3802. channels->min = channels->max =
  3803. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3804. break;
  3805. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3806. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3807. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3808. rate->min = rate->max =
  3809. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3810. channels->min = channels->max =
  3811. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3812. break;
  3813. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3814. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3815. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3816. rate->min = rate->max =
  3817. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3818. channels->min = channels->max =
  3819. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3820. break;
  3821. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3822. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3823. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3824. rate->min = rate->max =
  3825. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3826. channels->min = channels->max =
  3827. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3828. break;
  3829. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3830. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3831. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3832. rate->min = rate->max =
  3833. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3834. channels->min = channels->max =
  3835. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3836. break;
  3837. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3838. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3839. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3840. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3841. channels->min = channels->max =
  3842. mi2s_rx_cfg[PRIM_MI2S].channels;
  3843. break;
  3844. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3845. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3846. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3847. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3848. channels->min = channels->max =
  3849. mi2s_tx_cfg[PRIM_MI2S].channels;
  3850. break;
  3851. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3852. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3853. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3854. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3855. channels->min = channels->max =
  3856. mi2s_rx_cfg[SEC_MI2S].channels;
  3857. break;
  3858. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3859. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3860. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3861. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3862. channels->min = channels->max =
  3863. mi2s_tx_cfg[SEC_MI2S].channels;
  3864. break;
  3865. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3866. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3867. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3868. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3869. channels->min = channels->max =
  3870. mi2s_rx_cfg[TERT_MI2S].channels;
  3871. break;
  3872. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3873. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3874. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3875. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3876. channels->min = channels->max =
  3877. mi2s_tx_cfg[TERT_MI2S].channels;
  3878. break;
  3879. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3880. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3881. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3882. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3883. channels->min = channels->max =
  3884. mi2s_rx_cfg[QUAT_MI2S].channels;
  3885. break;
  3886. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3887. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3888. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3889. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3890. channels->min = channels->max =
  3891. mi2s_tx_cfg[QUAT_MI2S].channels;
  3892. break;
  3893. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3894. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3895. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3896. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3897. channels->min = channels->max =
  3898. mi2s_rx_cfg[QUIN_MI2S].channels;
  3899. break;
  3900. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3901. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3902. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3903. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3904. channels->min = channels->max =
  3905. mi2s_tx_cfg[QUIN_MI2S].channels;
  3906. break;
  3907. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3908. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3909. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3910. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  3911. channels->min = channels->max =
  3912. mi2s_rx_cfg[SEN_MI2S].channels;
  3913. break;
  3914. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  3915. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3916. mi2s_tx_cfg[SEN_MI2S].bit_format);
  3917. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  3918. channels->min = channels->max =
  3919. mi2s_tx_cfg[SEN_MI2S].channels;
  3920. break;
  3921. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3922. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3923. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3924. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3925. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3926. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3927. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3928. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3929. cdc_dma_rx_cfg[idx].bit_format);
  3930. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3931. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3932. break;
  3933. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3934. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3935. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3936. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3937. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3938. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3939. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3940. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3941. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3942. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3943. cdc_dma_tx_cfg[idx].bit_format);
  3944. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3945. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3946. break;
  3947. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3948. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3949. SNDRV_PCM_FORMAT_S32_LE);
  3950. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3951. channels->min = channels->max = msm_vi_feed_tx_ch;
  3952. break;
  3953. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3954. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3955. slim_rx_cfg[SLIM_RX_7].bit_format);
  3956. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3957. channels->min = channels->max =
  3958. slim_rx_cfg[SLIM_RX_7].channels;
  3959. break;
  3960. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3961. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3962. channels->min = channels->max =
  3963. slim_tx_cfg[SLIM_TX_7].channels;
  3964. break;
  3965. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3966. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3967. channels->min = channels->max =
  3968. slim_tx_cfg[SLIM_TX_8].channels;
  3969. break;
  3970. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3971. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3972. afe_loopback_tx_cfg[idx].bit_format);
  3973. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3974. channels->min = channels->max =
  3975. afe_loopback_tx_cfg[idx].channels;
  3976. break;
  3977. default:
  3978. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3979. break;
  3980. }
  3981. done:
  3982. return rc;
  3983. }
  3984. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3985. {
  3986. struct snd_soc_card *card = component->card;
  3987. struct msm_asoc_mach_data *pdata =
  3988. snd_soc_card_get_drvdata(card);
  3989. if (!pdata->fsa_handle)
  3990. return false;
  3991. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3992. }
  3993. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3994. {
  3995. int value = 0;
  3996. bool ret = false;
  3997. struct snd_soc_card *card;
  3998. struct msm_asoc_mach_data *pdata;
  3999. if (!component) {
  4000. pr_err("%s component is NULL\n", __func__);
  4001. return false;
  4002. }
  4003. card = component->card;
  4004. pdata = snd_soc_card_get_drvdata(card);
  4005. if (!pdata)
  4006. return false;
  4007. if (wcd_mbhc_cfg.enable_usbc_analog)
  4008. return msm_usbc_swap_gnd_mic(component, active);
  4009. /* if usbc is not defined, swap using us_euro_gpio_p */
  4010. if (pdata->us_euro_gpio_p) {
  4011. value = msm_cdc_pinctrl_get_state(
  4012. pdata->us_euro_gpio_p);
  4013. if (value)
  4014. msm_cdc_pinctrl_select_sleep_state(
  4015. pdata->us_euro_gpio_p);
  4016. else
  4017. msm_cdc_pinctrl_select_active_state(
  4018. pdata->us_euro_gpio_p);
  4019. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  4020. __func__, value, !value);
  4021. ret = true;
  4022. }
  4023. return ret;
  4024. }
  4025. static int kona_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4026. struct snd_pcm_hw_params *params)
  4027. {
  4028. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4029. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4030. int ret = 0;
  4031. int slot_width = TDM_SLOT_WIDTH_BITS;
  4032. int channels, slots = TDM_MAX_SLOTS;
  4033. unsigned int slot_mask, rate, clk_freq;
  4034. unsigned int *slot_offset;
  4035. struct tdm_dev_config *config;
  4036. unsigned int path_dir = 0, interface = 0, channel_interface = 0;
  4037. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4038. if (cpu_dai->id < AFE_PORT_ID_TDM_PORT_RANGE_START) {
  4039. pr_err("%s: dai id 0x%x not supported\n",
  4040. __func__, cpu_dai->id);
  4041. return -EINVAL;
  4042. }
  4043. /* RX or TX */
  4044. path_dir = cpu_dai->id % MAX_PATH;
  4045. /* PRI, SEC, TERT, QUAT, QUIN, ... */
  4046. interface = (cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START)
  4047. / (MAX_PATH * TDM_PORT_MAX);
  4048. /* 0, 1, 2, .. 7 */
  4049. channel_interface =
  4050. ((cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START) / MAX_PATH)
  4051. % TDM_PORT_MAX;
  4052. pr_debug("%s: path dir: %u, interface %u, channel interface %u\n",
  4053. __func__, path_dir, interface, channel_interface);
  4054. config = ((struct tdm_dev_config *) tdm_cfg[interface]) +
  4055. (path_dir * TDM_PORT_MAX) + channel_interface;
  4056. slot_offset = config->tdm_slot_offset;
  4057. if (path_dir)
  4058. channels = tdm_tx_cfg[interface][channel_interface].channels;
  4059. else
  4060. channels = tdm_rx_cfg[interface][channel_interface].channels;
  4061. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4062. /*2 slot config - bits 0 and 1 set for the first two slots */
  4063. slot_mask = 0x0000FFFF >> (16 - slots);
  4064. pr_debug("%s: tdm rx slot_width %d slots %d slot_mask %x\n",
  4065. __func__, slot_width, slots, slot_mask);
  4066. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4067. slots, slot_width);
  4068. if (ret < 0) {
  4069. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4070. __func__, ret);
  4071. goto end;
  4072. }
  4073. pr_debug("%s: tdm rx channels: %d\n", __func__, channels);
  4074. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4075. 0, NULL, channels, slot_offset);
  4076. if (ret < 0) {
  4077. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4078. __func__, ret);
  4079. goto end;
  4080. }
  4081. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4082. /*2 slot config - bits 0 and 1 set for the first two slots */
  4083. slot_mask = 0x0000FFFF >> (16 - slots);
  4084. pr_debug("%s: tdm tx slot_width %d slots %d slot_mask %x\n",
  4085. __func__, slot_width, slots, slot_mask);
  4086. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4087. slots, slot_width);
  4088. if (ret < 0) {
  4089. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4090. __func__, ret);
  4091. goto end;
  4092. }
  4093. pr_debug("%s: tdm tx channels: %d\n", __func__, channels);
  4094. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4095. channels, slot_offset, 0, NULL);
  4096. if (ret < 0) {
  4097. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4098. __func__, ret);
  4099. goto end;
  4100. }
  4101. } else {
  4102. ret = -EINVAL;
  4103. pr_err("%s: invalid use case, err:%d\n",
  4104. __func__, ret);
  4105. goto end;
  4106. }
  4107. rate = params_rate(params);
  4108. clk_freq = rate * slot_width * slots;
  4109. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4110. if (ret < 0)
  4111. pr_err("%s: failed to set tdm clk, err:%d\n",
  4112. __func__, ret);
  4113. end:
  4114. return ret;
  4115. }
  4116. static int msm_get_tdm_mode(u32 port_id)
  4117. {
  4118. int tdm_mode;
  4119. switch (port_id) {
  4120. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4121. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4122. tdm_mode = TDM_PRI;
  4123. break;
  4124. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4125. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4126. tdm_mode = TDM_SEC;
  4127. break;
  4128. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4129. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4130. tdm_mode = TDM_TERT;
  4131. break;
  4132. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4133. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4134. tdm_mode = TDM_QUAT;
  4135. break;
  4136. case AFE_PORT_ID_QUINARY_TDM_RX:
  4137. case AFE_PORT_ID_QUINARY_TDM_TX:
  4138. tdm_mode = TDM_QUIN;
  4139. break;
  4140. case AFE_PORT_ID_SENARY_TDM_RX:
  4141. case AFE_PORT_ID_SENARY_TDM_TX:
  4142. tdm_mode = TDM_SEN;
  4143. break;
  4144. default:
  4145. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  4146. tdm_mode = -EINVAL;
  4147. }
  4148. return tdm_mode;
  4149. }
  4150. static int kona_tdm_snd_startup(struct snd_pcm_substream *substream)
  4151. {
  4152. int ret = 0;
  4153. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4154. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4155. struct snd_soc_card *card = rtd->card;
  4156. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4157. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4158. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  4159. ret = -EINVAL;
  4160. pr_err("%s: Invalid TDM interface %d\n",
  4161. __func__, ret);
  4162. return ret;
  4163. }
  4164. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4165. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  4166. == 0) {
  4167. ret = msm_cdc_pinctrl_select_active_state(
  4168. pdata->mi2s_gpio_p[tdm_mode]);
  4169. if (ret) {
  4170. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  4171. __func__, ret);
  4172. goto done;
  4173. }
  4174. }
  4175. atomic_inc(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  4176. }
  4177. done:
  4178. return ret;
  4179. }
  4180. static void kona_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4181. {
  4182. int ret = 0;
  4183. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4184. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4185. struct snd_soc_card *card = rtd->card;
  4186. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4187. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4188. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  4189. ret = -EINVAL;
  4190. pr_err("%s: Invalid TDM interface %d\n",
  4191. __func__, ret);
  4192. return;
  4193. }
  4194. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4195. atomic_dec(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  4196. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  4197. == 0) {
  4198. ret = msm_cdc_pinctrl_select_sleep_state(
  4199. pdata->mi2s_gpio_p[tdm_mode]);
  4200. if (ret)
  4201. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  4202. __func__, ret);
  4203. }
  4204. }
  4205. }
  4206. static int kona_aux_snd_startup(struct snd_pcm_substream *substream)
  4207. {
  4208. int ret = 0;
  4209. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4210. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4211. struct snd_soc_card *card = rtd->card;
  4212. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4213. u32 aux_mode = cpu_dai->id - 1;
  4214. if (aux_mode >= AUX_PCM_MAX) {
  4215. ret = -EINVAL;
  4216. pr_err("%s: Invalid AUX interface %d\n",
  4217. __func__, ret);
  4218. return ret;
  4219. }
  4220. if (pdata->mi2s_gpio_p[aux_mode]) {
  4221. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  4222. == 0) {
  4223. ret = msm_cdc_pinctrl_select_active_state(
  4224. pdata->mi2s_gpio_p[aux_mode]);
  4225. if (ret) {
  4226. pr_err("%s: AUX GPIO pinctrl set active failed with %d\n",
  4227. __func__, ret);
  4228. goto done;
  4229. }
  4230. }
  4231. atomic_inc(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  4232. }
  4233. done:
  4234. return ret;
  4235. }
  4236. static void kona_aux_snd_shutdown(struct snd_pcm_substream *substream)
  4237. {
  4238. int ret = 0;
  4239. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4240. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4241. struct snd_soc_card *card = rtd->card;
  4242. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4243. u32 aux_mode = cpu_dai->id - 1;
  4244. if (aux_mode >= AUX_PCM_MAX) {
  4245. pr_err("%s: Invalid AUX interface %d\n",
  4246. __func__, ret);
  4247. return;
  4248. }
  4249. if (pdata->mi2s_gpio_p[aux_mode]) {
  4250. atomic_dec(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  4251. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  4252. == 0) {
  4253. ret = msm_cdc_pinctrl_select_sleep_state(
  4254. pdata->mi2s_gpio_p[aux_mode]);
  4255. if (ret)
  4256. pr_err("%s: AUX GPIO pinctrl set sleep failed with %d\n",
  4257. __func__, ret);
  4258. }
  4259. }
  4260. }
  4261. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  4262. {
  4263. int ret = 0;
  4264. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4265. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4266. switch (dai_link->id) {
  4267. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4268. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4269. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4270. ret = kona_send_island_va_config(dai_link->id);
  4271. if (ret)
  4272. pr_err("%s: send island va cfg failed, err: %d\n",
  4273. __func__, ret);
  4274. break;
  4275. }
  4276. return ret;
  4277. }
  4278. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4279. struct snd_pcm_hw_params *params)
  4280. {
  4281. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4282. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4283. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4284. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4285. int ret = 0;
  4286. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4287. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4288. u32 user_set_tx_ch = 0;
  4289. u32 user_set_rx_ch = 0;
  4290. u32 ch_id;
  4291. ret = snd_soc_dai_get_channel_map(codec_dai,
  4292. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4293. &rx_ch_cdc_dma);
  4294. if (ret < 0) {
  4295. pr_err("%s: failed to get codec chan map, err:%d\n",
  4296. __func__, ret);
  4297. goto err;
  4298. }
  4299. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4300. switch (dai_link->id) {
  4301. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4302. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4303. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  4304. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  4305. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  4306. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  4307. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  4308. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  4309. {
  4310. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4311. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4312. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4313. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4314. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4315. user_set_rx_ch, &rx_ch_cdc_dma);
  4316. if (ret < 0) {
  4317. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4318. __func__, ret);
  4319. goto err;
  4320. }
  4321. }
  4322. break;
  4323. }
  4324. } else {
  4325. switch (dai_link->id) {
  4326. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4327. {
  4328. user_set_tx_ch = msm_vi_feed_tx_ch;
  4329. }
  4330. break;
  4331. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4332. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4333. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  4334. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  4335. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  4336. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4337. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4338. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4339. {
  4340. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4341. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4342. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4343. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4344. }
  4345. break;
  4346. }
  4347. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4348. &tx_ch_cdc_dma, 0, 0);
  4349. if (ret < 0) {
  4350. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4351. __func__, ret);
  4352. goto err;
  4353. }
  4354. }
  4355. err:
  4356. return ret;
  4357. }
  4358. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4359. {
  4360. cpumask_t mask;
  4361. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4362. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4363. cpumask_clear(&mask);
  4364. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4365. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4366. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4367. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4368. pm_qos_add_request(&substream->latency_pm_qos_req,
  4369. PM_QOS_CPU_DMA_LATENCY,
  4370. MSM_LL_QOS_VALUE);
  4371. return 0;
  4372. }
  4373. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4374. {
  4375. int ret = 0;
  4376. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4377. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4378. int index = cpu_dai->id;
  4379. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4380. struct snd_soc_card *card = rtd->card;
  4381. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4382. dev_dbg(rtd->card->dev,
  4383. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4384. __func__, substream->name, substream->stream,
  4385. cpu_dai->name, cpu_dai->id);
  4386. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4387. ret = -EINVAL;
  4388. dev_err(rtd->card->dev,
  4389. "%s: CPU DAI id (%d) out of range\n",
  4390. __func__, cpu_dai->id);
  4391. goto err;
  4392. }
  4393. /*
  4394. * Mutex protection in case the same MI2S
  4395. * interface using for both TX and RX so
  4396. * that the same clock won't be enable twice.
  4397. */
  4398. mutex_lock(&mi2s_intf_conf[index].lock);
  4399. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4400. /* Check if msm needs to provide the clock to the interface */
  4401. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4402. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4403. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4404. }
  4405. ret = msm_mi2s_set_sclk(substream, true);
  4406. if (ret < 0) {
  4407. dev_err(rtd->card->dev,
  4408. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4409. __func__, ret);
  4410. goto clean_up;
  4411. }
  4412. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4413. if (ret < 0) {
  4414. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4415. __func__, index, ret);
  4416. goto clk_off;
  4417. }
  4418. if (pdata->mi2s_gpio_p[index]) {
  4419. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4420. == 0) {
  4421. ret = msm_cdc_pinctrl_select_active_state(
  4422. pdata->mi2s_gpio_p[index]);
  4423. if (ret) {
  4424. pr_err("%s: MI2S GPIO pinctrl set active failed with %d\n",
  4425. __func__, ret);
  4426. goto clk_off;
  4427. }
  4428. }
  4429. atomic_inc(&(pdata->mi2s_gpio_ref_count[index]));
  4430. }
  4431. }
  4432. clk_off:
  4433. if (ret < 0)
  4434. msm_mi2s_set_sclk(substream, false);
  4435. clean_up:
  4436. if (ret < 0)
  4437. mi2s_intf_conf[index].ref_cnt--;
  4438. mutex_unlock(&mi2s_intf_conf[index].lock);
  4439. err:
  4440. return ret;
  4441. }
  4442. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4443. {
  4444. int ret = 0;
  4445. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4446. int index = rtd->cpu_dai->id;
  4447. struct snd_soc_card *card = rtd->card;
  4448. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4449. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4450. substream->name, substream->stream);
  4451. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4452. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4453. return;
  4454. }
  4455. mutex_lock(&mi2s_intf_conf[index].lock);
  4456. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4457. if (pdata->mi2s_gpio_p[index]) {
  4458. atomic_dec(&(pdata->mi2s_gpio_ref_count[index]));
  4459. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4460. == 0) {
  4461. ret = msm_cdc_pinctrl_select_sleep_state(
  4462. pdata->mi2s_gpio_p[index]);
  4463. if (ret)
  4464. pr_err("%s: MI2S GPIO pinctrl set sleep failed with %d\n",
  4465. __func__, ret);
  4466. }
  4467. }
  4468. ret = msm_mi2s_set_sclk(substream, false);
  4469. if (ret < 0)
  4470. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4471. __func__, index, ret);
  4472. }
  4473. mutex_unlock(&mi2s_intf_conf[index].lock);
  4474. }
  4475. static int msm_wcn_hw_params_lito(struct snd_pcm_substream *substream,
  4476. struct snd_pcm_hw_params *params)
  4477. {
  4478. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4479. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4480. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4481. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4482. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO];
  4483. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4484. int ret = 0;
  4485. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4486. codec_dai->name, codec_dai->id);
  4487. ret = snd_soc_dai_get_channel_map(codec_dai,
  4488. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4489. if (ret) {
  4490. dev_err(rtd->dev,
  4491. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4492. __func__, ret);
  4493. goto err;
  4494. }
  4495. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4496. __func__, tx_ch_cnt, dai_link->id);
  4497. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4498. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4499. if (ret)
  4500. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4501. __func__, ret);
  4502. err:
  4503. return ret;
  4504. }
  4505. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4506. struct snd_pcm_hw_params *params)
  4507. {
  4508. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4509. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4510. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4511. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4512. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4513. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4514. int ret = 0;
  4515. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4516. codec_dai->name, codec_dai->id);
  4517. ret = snd_soc_dai_get_channel_map(codec_dai,
  4518. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4519. if (ret) {
  4520. dev_err(rtd->dev,
  4521. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4522. __func__, ret);
  4523. goto err;
  4524. }
  4525. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4526. __func__, tx_ch_cnt, dai_link->id);
  4527. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4528. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4529. if (ret)
  4530. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4531. __func__, ret);
  4532. err:
  4533. return ret;
  4534. }
  4535. static struct snd_soc_ops kona_aux_be_ops = {
  4536. .startup = kona_aux_snd_startup,
  4537. .shutdown = kona_aux_snd_shutdown
  4538. };
  4539. static struct snd_soc_ops kona_tdm_be_ops = {
  4540. .hw_params = kona_tdm_snd_hw_params,
  4541. .startup = kona_tdm_snd_startup,
  4542. .shutdown = kona_tdm_snd_shutdown
  4543. };
  4544. static struct snd_soc_ops msm_mi2s_be_ops = {
  4545. .startup = msm_mi2s_snd_startup,
  4546. .shutdown = msm_mi2s_snd_shutdown,
  4547. };
  4548. static struct snd_soc_ops msm_fe_qos_ops = {
  4549. .prepare = msm_fe_qos_prepare,
  4550. };
  4551. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4552. .startup = msm_snd_cdc_dma_startup,
  4553. .hw_params = msm_snd_cdc_dma_hw_params,
  4554. };
  4555. static struct snd_soc_ops msm_wcn_ops = {
  4556. .hw_params = msm_wcn_hw_params,
  4557. };
  4558. static struct snd_soc_ops msm_wcn_ops_lito = {
  4559. .hw_params = msm_wcn_hw_params_lito,
  4560. };
  4561. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  4562. struct snd_kcontrol *kcontrol, int event)
  4563. {
  4564. struct msm_asoc_mach_data *pdata = NULL;
  4565. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  4566. int ret = 0;
  4567. u32 dmic_idx;
  4568. int *dmic_gpio_cnt;
  4569. struct device_node *dmic_gpio;
  4570. char *wname;
  4571. wname = strpbrk(w->name, "012345");
  4572. if (!wname) {
  4573. dev_err(component->dev, "%s: widget not found\n", __func__);
  4574. return -EINVAL;
  4575. }
  4576. ret = kstrtouint(wname, 10, &dmic_idx);
  4577. if (ret < 0) {
  4578. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  4579. __func__);
  4580. return -EINVAL;
  4581. }
  4582. pdata = snd_soc_card_get_drvdata(component->card);
  4583. switch (dmic_idx) {
  4584. case 0:
  4585. case 1:
  4586. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  4587. dmic_gpio = pdata->dmic01_gpio_p;
  4588. break;
  4589. case 2:
  4590. case 3:
  4591. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  4592. dmic_gpio = pdata->dmic23_gpio_p;
  4593. break;
  4594. case 4:
  4595. case 5:
  4596. dmic_gpio_cnt = &dmic_4_5_gpio_cnt;
  4597. dmic_gpio = pdata->dmic45_gpio_p;
  4598. break;
  4599. default:
  4600. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  4601. __func__);
  4602. return -EINVAL;
  4603. }
  4604. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  4605. __func__, event, dmic_idx, *dmic_gpio_cnt);
  4606. switch (event) {
  4607. case SND_SOC_DAPM_PRE_PMU:
  4608. (*dmic_gpio_cnt)++;
  4609. if (*dmic_gpio_cnt == 1) {
  4610. ret = msm_cdc_pinctrl_select_active_state(
  4611. dmic_gpio);
  4612. if (ret < 0) {
  4613. pr_err("%s: gpio set cannot be activated %sd",
  4614. __func__, "dmic_gpio");
  4615. return ret;
  4616. }
  4617. }
  4618. break;
  4619. case SND_SOC_DAPM_POST_PMD:
  4620. (*dmic_gpio_cnt)--;
  4621. if (*dmic_gpio_cnt == 0) {
  4622. ret = msm_cdc_pinctrl_select_sleep_state(
  4623. dmic_gpio);
  4624. if (ret < 0) {
  4625. pr_err("%s: gpio set cannot be de-activated %sd",
  4626. __func__, "dmic_gpio");
  4627. return ret;
  4628. }
  4629. }
  4630. break;
  4631. default:
  4632. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  4633. return -EINVAL;
  4634. }
  4635. return 0;
  4636. }
  4637. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  4638. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  4639. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  4640. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  4641. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  4642. SND_SOC_DAPM_MIC("Analog Mic5", NULL),
  4643. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  4644. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  4645. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  4646. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  4647. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  4648. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  4649. SND_SOC_DAPM_MIC("Digital Mic6", NULL),
  4650. SND_SOC_DAPM_MIC("Digital Mic7", NULL),
  4651. };
  4652. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4653. {
  4654. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4655. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160};
  4656. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4657. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4658. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4659. }
  4660. static int msm_wcn_init_lito(struct snd_soc_pcm_runtime *rtd)
  4661. {
  4662. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4663. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO] = {159, 160, 161};
  4664. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4665. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4666. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4667. }
  4668. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4669. {
  4670. int ret = -EINVAL;
  4671. struct snd_soc_component *component;
  4672. struct snd_soc_dapm_context *dapm;
  4673. struct snd_card *card;
  4674. struct snd_info_entry *entry;
  4675. struct snd_soc_component *aux_comp;
  4676. struct msm_asoc_mach_data *pdata =
  4677. snd_soc_card_get_drvdata(rtd->card);
  4678. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4679. if (!component) {
  4680. pr_err("%s: could not find component for bolero_codec\n",
  4681. __func__);
  4682. return ret;
  4683. }
  4684. dapm = snd_soc_component_get_dapm(component);
  4685. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  4686. ARRAY_SIZE(msm_int_snd_controls));
  4687. if (ret < 0) {
  4688. pr_err("%s: add_component_controls failed: %d\n",
  4689. __func__, ret);
  4690. return ret;
  4691. }
  4692. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  4693. ARRAY_SIZE(msm_common_snd_controls));
  4694. if (ret < 0) {
  4695. pr_err("%s: add common snd controls failed: %d\n",
  4696. __func__, ret);
  4697. return ret;
  4698. }
  4699. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  4700. ARRAY_SIZE(msm_int_dapm_widgets));
  4701. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4702. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4703. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4704. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4705. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4706. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4707. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4708. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4709. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  4710. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  4711. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4712. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4713. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
  4714. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4715. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4716. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4717. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4718. snd_soc_dapm_sync(dapm);
  4719. /*
  4720. * Send speaker configuration only for WSA8810.
  4721. * Default configuration is for WSA8815.
  4722. */
  4723. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4724. __func__, rtd->card->num_aux_devs);
  4725. if (rtd->card->num_aux_devs &&
  4726. !list_empty(&rtd->card->component_dev_list)) {
  4727. list_for_each_entry(aux_comp,
  4728. &rtd->card->aux_comp_list,
  4729. card_aux_list) {
  4730. if (aux_comp->name != NULL && (
  4731. !strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4732. !strcmp(aux_comp->name, WSA8810_NAME_2))) {
  4733. wsa_macro_set_spkr_mode(component,
  4734. WSA_MACRO_SPKR_MODE_1);
  4735. wsa_macro_set_spkr_gain_offset(component,
  4736. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4737. }
  4738. }
  4739. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map),
  4740. sm_port_map);
  4741. }
  4742. card = rtd->card->snd_card;
  4743. if (!pdata->codec_root) {
  4744. entry = snd_info_create_subdir(card->module, "codecs",
  4745. card->proc_root);
  4746. if (!entry) {
  4747. pr_debug("%s: Cannot create codecs module entry\n",
  4748. __func__);
  4749. ret = 0;
  4750. goto err;
  4751. }
  4752. pdata->codec_root = entry;
  4753. }
  4754. bolero_info_create_codec_entry(pdata->codec_root, component);
  4755. bolero_register_wake_irq(component, false);
  4756. codec_reg_done = true;
  4757. return 0;
  4758. err:
  4759. return ret;
  4760. }
  4761. static void *def_wcd_mbhc_cal(void)
  4762. {
  4763. void *wcd_mbhc_cal;
  4764. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  4765. u16 *btn_high;
  4766. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  4767. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  4768. if (!wcd_mbhc_cal)
  4769. return NULL;
  4770. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  4771. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  4772. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  4773. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  4774. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  4775. btn_high[0] = 75;
  4776. btn_high[1] = 150;
  4777. btn_high[2] = 237;
  4778. btn_high[3] = 500;
  4779. btn_high[4] = 500;
  4780. btn_high[5] = 500;
  4781. btn_high[6] = 500;
  4782. btn_high[7] = 500;
  4783. return wcd_mbhc_cal;
  4784. }
  4785. /* Digital audio interface glue - connects codec <---> CPU */
  4786. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4787. /* FrontEnd DAI Links */
  4788. {/* hw:x,0 */
  4789. .name = MSM_DAILINK_NAME(Media1),
  4790. .stream_name = "MultiMedia1",
  4791. .cpu_dai_name = "MultiMedia1",
  4792. .platform_name = "msm-pcm-dsp.0",
  4793. .dynamic = 1,
  4794. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4795. .dpcm_playback = 1,
  4796. .dpcm_capture = 1,
  4797. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4798. SND_SOC_DPCM_TRIGGER_POST},
  4799. .codec_dai_name = "snd-soc-dummy-dai",
  4800. .codec_name = "snd-soc-dummy",
  4801. .ignore_suspend = 1,
  4802. /* this dainlink has playback support */
  4803. .ignore_pmdown_time = 1,
  4804. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4805. },
  4806. {/* hw:x,1 */
  4807. .name = MSM_DAILINK_NAME(Media2),
  4808. .stream_name = "MultiMedia2",
  4809. .cpu_dai_name = "MultiMedia2",
  4810. .platform_name = "msm-pcm-dsp.0",
  4811. .dynamic = 1,
  4812. .dpcm_playback = 1,
  4813. .dpcm_capture = 1,
  4814. .codec_dai_name = "snd-soc-dummy-dai",
  4815. .codec_name = "snd-soc-dummy",
  4816. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4817. SND_SOC_DPCM_TRIGGER_POST},
  4818. .ignore_suspend = 1,
  4819. /* this dainlink has playback support */
  4820. .ignore_pmdown_time = 1,
  4821. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4822. },
  4823. {/* hw:x,2 */
  4824. .name = "VoiceMMode1",
  4825. .stream_name = "VoiceMMode1",
  4826. .cpu_dai_name = "VoiceMMode1",
  4827. .platform_name = "msm-pcm-voice",
  4828. .dynamic = 1,
  4829. .dpcm_playback = 1,
  4830. .dpcm_capture = 1,
  4831. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4832. SND_SOC_DPCM_TRIGGER_POST},
  4833. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4834. .ignore_suspend = 1,
  4835. .ignore_pmdown_time = 1,
  4836. .codec_dai_name = "snd-soc-dummy-dai",
  4837. .codec_name = "snd-soc-dummy",
  4838. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4839. },
  4840. {/* hw:x,3 */
  4841. .name = "MSM VoIP",
  4842. .stream_name = "VoIP",
  4843. .cpu_dai_name = "VoIP",
  4844. .platform_name = "msm-voip-dsp",
  4845. .dynamic = 1,
  4846. .dpcm_playback = 1,
  4847. .dpcm_capture = 1,
  4848. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4849. SND_SOC_DPCM_TRIGGER_POST},
  4850. .codec_dai_name = "snd-soc-dummy-dai",
  4851. .codec_name = "snd-soc-dummy",
  4852. .ignore_suspend = 1,
  4853. /* this dainlink has playback support */
  4854. .ignore_pmdown_time = 1,
  4855. .id = MSM_FRONTEND_DAI_VOIP,
  4856. },
  4857. {/* hw:x,4 */
  4858. .name = MSM_DAILINK_NAME(ULL),
  4859. .stream_name = "MultiMedia3",
  4860. .cpu_dai_name = "MultiMedia3",
  4861. .platform_name = "msm-pcm-dsp.2",
  4862. .dynamic = 1,
  4863. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4864. .dpcm_playback = 1,
  4865. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4866. SND_SOC_DPCM_TRIGGER_POST},
  4867. .codec_dai_name = "snd-soc-dummy-dai",
  4868. .codec_name = "snd-soc-dummy",
  4869. .ignore_suspend = 1,
  4870. /* this dainlink has playback support */
  4871. .ignore_pmdown_time = 1,
  4872. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4873. },
  4874. {/* hw:x,5 */
  4875. .name = "MSM AFE-PCM RX",
  4876. .stream_name = "AFE-PROXY RX",
  4877. .cpu_dai_name = "msm-dai-q6-dev.241",
  4878. .codec_name = "msm-stub-codec.1",
  4879. .codec_dai_name = "msm-stub-rx",
  4880. .platform_name = "msm-pcm-afe",
  4881. .dpcm_playback = 1,
  4882. .ignore_suspend = 1,
  4883. /* this dainlink has playback support */
  4884. .ignore_pmdown_time = 1,
  4885. },
  4886. {/* hw:x,6 */
  4887. .name = "MSM AFE-PCM TX",
  4888. .stream_name = "AFE-PROXY TX",
  4889. .cpu_dai_name = "msm-dai-q6-dev.240",
  4890. .codec_name = "msm-stub-codec.1",
  4891. .codec_dai_name = "msm-stub-tx",
  4892. .platform_name = "msm-pcm-afe",
  4893. .dpcm_capture = 1,
  4894. .ignore_suspend = 1,
  4895. },
  4896. {/* hw:x,7 */
  4897. .name = MSM_DAILINK_NAME(Compress1),
  4898. .stream_name = "Compress1",
  4899. .cpu_dai_name = "MultiMedia4",
  4900. .platform_name = "msm-compress-dsp",
  4901. .dynamic = 1,
  4902. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4903. .dpcm_playback = 1,
  4904. .dpcm_capture = 1,
  4905. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4906. SND_SOC_DPCM_TRIGGER_POST},
  4907. .codec_dai_name = "snd-soc-dummy-dai",
  4908. .codec_name = "snd-soc-dummy",
  4909. .ignore_suspend = 1,
  4910. .ignore_pmdown_time = 1,
  4911. /* this dainlink has playback support */
  4912. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4913. },
  4914. /* Hostless PCM purpose */
  4915. {/* hw:x,8 */
  4916. .name = "AUXPCM Hostless",
  4917. .stream_name = "AUXPCM Hostless",
  4918. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4919. .platform_name = "msm-pcm-hostless",
  4920. .dynamic = 1,
  4921. .dpcm_playback = 1,
  4922. .dpcm_capture = 1,
  4923. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4924. SND_SOC_DPCM_TRIGGER_POST},
  4925. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4926. .ignore_suspend = 1,
  4927. /* this dainlink has playback support */
  4928. .ignore_pmdown_time = 1,
  4929. .codec_dai_name = "snd-soc-dummy-dai",
  4930. .codec_name = "snd-soc-dummy",
  4931. },
  4932. {/* hw:x,9 */
  4933. .name = MSM_DAILINK_NAME(LowLatency),
  4934. .stream_name = "MultiMedia5",
  4935. .cpu_dai_name = "MultiMedia5",
  4936. .platform_name = "msm-pcm-dsp.1",
  4937. .dynamic = 1,
  4938. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4939. .dpcm_playback = 1,
  4940. .dpcm_capture = 1,
  4941. .codec_dai_name = "snd-soc-dummy-dai",
  4942. .codec_name = "snd-soc-dummy",
  4943. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4944. SND_SOC_DPCM_TRIGGER_POST},
  4945. .ignore_suspend = 1,
  4946. /* this dainlink has playback support */
  4947. .ignore_pmdown_time = 1,
  4948. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4949. .ops = &msm_fe_qos_ops,
  4950. },
  4951. {/* hw:x,10 */
  4952. .name = "Listen 1 Audio Service",
  4953. .stream_name = "Listen 1 Audio Service",
  4954. .cpu_dai_name = "LSM1",
  4955. .platform_name = "msm-lsm-client",
  4956. .dynamic = 1,
  4957. .dpcm_capture = 1,
  4958. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4959. SND_SOC_DPCM_TRIGGER_POST },
  4960. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4961. .ignore_suspend = 1,
  4962. .codec_dai_name = "snd-soc-dummy-dai",
  4963. .codec_name = "snd-soc-dummy",
  4964. .id = MSM_FRONTEND_DAI_LSM1,
  4965. },
  4966. /* Multiple Tunnel instances */
  4967. {/* hw:x,11 */
  4968. .name = MSM_DAILINK_NAME(Compress2),
  4969. .stream_name = "Compress2",
  4970. .cpu_dai_name = "MultiMedia7",
  4971. .platform_name = "msm-compress-dsp",
  4972. .dynamic = 1,
  4973. .dpcm_playback = 1,
  4974. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4975. SND_SOC_DPCM_TRIGGER_POST},
  4976. .codec_dai_name = "snd-soc-dummy-dai",
  4977. .codec_name = "snd-soc-dummy",
  4978. .ignore_suspend = 1,
  4979. .ignore_pmdown_time = 1,
  4980. /* this dainlink has playback support */
  4981. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4982. },
  4983. {/* hw:x,12 */
  4984. .name = MSM_DAILINK_NAME(MultiMedia10),
  4985. .stream_name = "MultiMedia10",
  4986. .cpu_dai_name = "MultiMedia10",
  4987. .platform_name = "msm-pcm-dsp.1",
  4988. .dynamic = 1,
  4989. .dpcm_playback = 1,
  4990. .dpcm_capture = 1,
  4991. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4992. SND_SOC_DPCM_TRIGGER_POST},
  4993. .codec_dai_name = "snd-soc-dummy-dai",
  4994. .codec_name = "snd-soc-dummy",
  4995. .ignore_suspend = 1,
  4996. .ignore_pmdown_time = 1,
  4997. /* this dainlink has playback support */
  4998. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4999. },
  5000. {/* hw:x,13 */
  5001. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5002. .stream_name = "MM_NOIRQ",
  5003. .cpu_dai_name = "MultiMedia8",
  5004. .platform_name = "msm-pcm-dsp-noirq",
  5005. .dynamic = 1,
  5006. .dpcm_playback = 1,
  5007. .dpcm_capture = 1,
  5008. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5009. SND_SOC_DPCM_TRIGGER_POST},
  5010. .codec_dai_name = "snd-soc-dummy-dai",
  5011. .codec_name = "snd-soc-dummy",
  5012. .ignore_suspend = 1,
  5013. .ignore_pmdown_time = 1,
  5014. /* this dainlink has playback support */
  5015. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5016. .ops = &msm_fe_qos_ops,
  5017. },
  5018. /* HDMI Hostless */
  5019. {/* hw:x,14 */
  5020. .name = "HDMI_RX_HOSTLESS",
  5021. .stream_name = "HDMI_RX_HOSTLESS",
  5022. .cpu_dai_name = "HDMI_HOSTLESS",
  5023. .platform_name = "msm-pcm-hostless",
  5024. .dynamic = 1,
  5025. .dpcm_playback = 1,
  5026. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5027. SND_SOC_DPCM_TRIGGER_POST},
  5028. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5029. .ignore_suspend = 1,
  5030. .ignore_pmdown_time = 1,
  5031. .codec_dai_name = "snd-soc-dummy-dai",
  5032. .codec_name = "snd-soc-dummy",
  5033. },
  5034. {/* hw:x,15 */
  5035. .name = "VoiceMMode2",
  5036. .stream_name = "VoiceMMode2",
  5037. .cpu_dai_name = "VoiceMMode2",
  5038. .platform_name = "msm-pcm-voice",
  5039. .dynamic = 1,
  5040. .dpcm_playback = 1,
  5041. .dpcm_capture = 1,
  5042. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5043. SND_SOC_DPCM_TRIGGER_POST},
  5044. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5045. .ignore_suspend = 1,
  5046. .ignore_pmdown_time = 1,
  5047. .codec_dai_name = "snd-soc-dummy-dai",
  5048. .codec_name = "snd-soc-dummy",
  5049. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5050. },
  5051. /* LSM FE */
  5052. {/* hw:x,16 */
  5053. .name = "Listen 2 Audio Service",
  5054. .stream_name = "Listen 2 Audio Service",
  5055. .cpu_dai_name = "LSM2",
  5056. .platform_name = "msm-lsm-client",
  5057. .dynamic = 1,
  5058. .dpcm_capture = 1,
  5059. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5060. SND_SOC_DPCM_TRIGGER_POST },
  5061. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5062. .ignore_suspend = 1,
  5063. .codec_dai_name = "snd-soc-dummy-dai",
  5064. .codec_name = "snd-soc-dummy",
  5065. .id = MSM_FRONTEND_DAI_LSM2,
  5066. },
  5067. {/* hw:x,17 */
  5068. .name = "Listen 3 Audio Service",
  5069. .stream_name = "Listen 3 Audio Service",
  5070. .cpu_dai_name = "LSM3",
  5071. .platform_name = "msm-lsm-client",
  5072. .dynamic = 1,
  5073. .dpcm_capture = 1,
  5074. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5075. SND_SOC_DPCM_TRIGGER_POST },
  5076. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5077. .ignore_suspend = 1,
  5078. .codec_dai_name = "snd-soc-dummy-dai",
  5079. .codec_name = "snd-soc-dummy",
  5080. .id = MSM_FRONTEND_DAI_LSM3,
  5081. },
  5082. {/* hw:x,18 */
  5083. .name = "Listen 4 Audio Service",
  5084. .stream_name = "Listen 4 Audio Service",
  5085. .cpu_dai_name = "LSM4",
  5086. .platform_name = "msm-lsm-client",
  5087. .dynamic = 1,
  5088. .dpcm_capture = 1,
  5089. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5090. SND_SOC_DPCM_TRIGGER_POST },
  5091. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5092. .ignore_suspend = 1,
  5093. .codec_dai_name = "snd-soc-dummy-dai",
  5094. .codec_name = "snd-soc-dummy",
  5095. .id = MSM_FRONTEND_DAI_LSM4,
  5096. },
  5097. {/* hw:x,19 */
  5098. .name = "Listen 5 Audio Service",
  5099. .stream_name = "Listen 5 Audio Service",
  5100. .cpu_dai_name = "LSM5",
  5101. .platform_name = "msm-lsm-client",
  5102. .dynamic = 1,
  5103. .dpcm_capture = 1,
  5104. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5105. SND_SOC_DPCM_TRIGGER_POST },
  5106. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5107. .ignore_suspend = 1,
  5108. .codec_dai_name = "snd-soc-dummy-dai",
  5109. .codec_name = "snd-soc-dummy",
  5110. .id = MSM_FRONTEND_DAI_LSM5,
  5111. },
  5112. {/* hw:x,20 */
  5113. .name = "Listen 6 Audio Service",
  5114. .stream_name = "Listen 6 Audio Service",
  5115. .cpu_dai_name = "LSM6",
  5116. .platform_name = "msm-lsm-client",
  5117. .dynamic = 1,
  5118. .dpcm_capture = 1,
  5119. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5120. SND_SOC_DPCM_TRIGGER_POST },
  5121. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5122. .ignore_suspend = 1,
  5123. .codec_dai_name = "snd-soc-dummy-dai",
  5124. .codec_name = "snd-soc-dummy",
  5125. .id = MSM_FRONTEND_DAI_LSM6,
  5126. },
  5127. {/* hw:x,21 */
  5128. .name = "Listen 7 Audio Service",
  5129. .stream_name = "Listen 7 Audio Service",
  5130. .cpu_dai_name = "LSM7",
  5131. .platform_name = "msm-lsm-client",
  5132. .dynamic = 1,
  5133. .dpcm_capture = 1,
  5134. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5135. SND_SOC_DPCM_TRIGGER_POST },
  5136. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5137. .ignore_suspend = 1,
  5138. .codec_dai_name = "snd-soc-dummy-dai",
  5139. .codec_name = "snd-soc-dummy",
  5140. .id = MSM_FRONTEND_DAI_LSM7,
  5141. },
  5142. {/* hw:x,22 */
  5143. .name = "Listen 8 Audio Service",
  5144. .stream_name = "Listen 8 Audio Service",
  5145. .cpu_dai_name = "LSM8",
  5146. .platform_name = "msm-lsm-client",
  5147. .dynamic = 1,
  5148. .dpcm_capture = 1,
  5149. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5150. SND_SOC_DPCM_TRIGGER_POST },
  5151. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5152. .ignore_suspend = 1,
  5153. .codec_dai_name = "snd-soc-dummy-dai",
  5154. .codec_name = "snd-soc-dummy",
  5155. .id = MSM_FRONTEND_DAI_LSM8,
  5156. },
  5157. {/* hw:x,23 */
  5158. .name = MSM_DAILINK_NAME(Media9),
  5159. .stream_name = "MultiMedia9",
  5160. .cpu_dai_name = "MultiMedia9",
  5161. .platform_name = "msm-pcm-dsp.0",
  5162. .dynamic = 1,
  5163. .dpcm_playback = 1,
  5164. .dpcm_capture = 1,
  5165. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5166. SND_SOC_DPCM_TRIGGER_POST},
  5167. .codec_dai_name = "snd-soc-dummy-dai",
  5168. .codec_name = "snd-soc-dummy",
  5169. .ignore_suspend = 1,
  5170. /* this dainlink has playback support */
  5171. .ignore_pmdown_time = 1,
  5172. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5173. },
  5174. {/* hw:x,24 */
  5175. .name = MSM_DAILINK_NAME(Compress4),
  5176. .stream_name = "Compress4",
  5177. .cpu_dai_name = "MultiMedia11",
  5178. .platform_name = "msm-compress-dsp",
  5179. .dynamic = 1,
  5180. .dpcm_playback = 1,
  5181. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5182. SND_SOC_DPCM_TRIGGER_POST},
  5183. .codec_dai_name = "snd-soc-dummy-dai",
  5184. .codec_name = "snd-soc-dummy",
  5185. .ignore_suspend = 1,
  5186. .ignore_pmdown_time = 1,
  5187. /* this dainlink has playback support */
  5188. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5189. },
  5190. {/* hw:x,25 */
  5191. .name = MSM_DAILINK_NAME(Compress5),
  5192. .stream_name = "Compress5",
  5193. .cpu_dai_name = "MultiMedia12",
  5194. .platform_name = "msm-compress-dsp",
  5195. .dynamic = 1,
  5196. .dpcm_playback = 1,
  5197. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5198. SND_SOC_DPCM_TRIGGER_POST},
  5199. .codec_dai_name = "snd-soc-dummy-dai",
  5200. .codec_name = "snd-soc-dummy",
  5201. .ignore_suspend = 1,
  5202. .ignore_pmdown_time = 1,
  5203. /* this dainlink has playback support */
  5204. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5205. },
  5206. {/* hw:x,26 */
  5207. .name = MSM_DAILINK_NAME(Compress6),
  5208. .stream_name = "Compress6",
  5209. .cpu_dai_name = "MultiMedia13",
  5210. .platform_name = "msm-compress-dsp",
  5211. .dynamic = 1,
  5212. .dpcm_playback = 1,
  5213. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5214. SND_SOC_DPCM_TRIGGER_POST},
  5215. .codec_dai_name = "snd-soc-dummy-dai",
  5216. .codec_name = "snd-soc-dummy",
  5217. .ignore_suspend = 1,
  5218. .ignore_pmdown_time = 1,
  5219. /* this dainlink has playback support */
  5220. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5221. },
  5222. {/* hw:x,27 */
  5223. .name = MSM_DAILINK_NAME(Compress7),
  5224. .stream_name = "Compress7",
  5225. .cpu_dai_name = "MultiMedia14",
  5226. .platform_name = "msm-compress-dsp",
  5227. .dynamic = 1,
  5228. .dpcm_playback = 1,
  5229. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5230. SND_SOC_DPCM_TRIGGER_POST},
  5231. .codec_dai_name = "snd-soc-dummy-dai",
  5232. .codec_name = "snd-soc-dummy",
  5233. .ignore_suspend = 1,
  5234. .ignore_pmdown_time = 1,
  5235. /* this dainlink has playback support */
  5236. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5237. },
  5238. {/* hw:x,28 */
  5239. .name = MSM_DAILINK_NAME(Compress8),
  5240. .stream_name = "Compress8",
  5241. .cpu_dai_name = "MultiMedia15",
  5242. .platform_name = "msm-compress-dsp",
  5243. .dynamic = 1,
  5244. .dpcm_playback = 1,
  5245. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5246. SND_SOC_DPCM_TRIGGER_POST},
  5247. .codec_dai_name = "snd-soc-dummy-dai",
  5248. .codec_name = "snd-soc-dummy",
  5249. .ignore_suspend = 1,
  5250. .ignore_pmdown_time = 1,
  5251. /* this dainlink has playback support */
  5252. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5253. },
  5254. {/* hw:x,29 */
  5255. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5256. .stream_name = "MM_NOIRQ_2",
  5257. .cpu_dai_name = "MultiMedia16",
  5258. .platform_name = "msm-pcm-dsp-noirq",
  5259. .dynamic = 1,
  5260. .dpcm_playback = 1,
  5261. .dpcm_capture = 1,
  5262. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5263. SND_SOC_DPCM_TRIGGER_POST},
  5264. .codec_dai_name = "snd-soc-dummy-dai",
  5265. .codec_name = "snd-soc-dummy",
  5266. .ignore_suspend = 1,
  5267. .ignore_pmdown_time = 1,
  5268. /* this dainlink has playback support */
  5269. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5270. .ops = &msm_fe_qos_ops,
  5271. },
  5272. {/* hw:x,30 */
  5273. .name = "CDC_DMA Hostless",
  5274. .stream_name = "CDC_DMA Hostless",
  5275. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5276. .platform_name = "msm-pcm-hostless",
  5277. .dynamic = 1,
  5278. .dpcm_playback = 1,
  5279. .dpcm_capture = 1,
  5280. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5281. SND_SOC_DPCM_TRIGGER_POST},
  5282. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5283. .ignore_suspend = 1,
  5284. /* this dailink has playback support */
  5285. .ignore_pmdown_time = 1,
  5286. .codec_dai_name = "snd-soc-dummy-dai",
  5287. .codec_name = "snd-soc-dummy",
  5288. },
  5289. {/* hw:x,31 */
  5290. .name = "TX3_CDC_DMA Hostless",
  5291. .stream_name = "TX3_CDC_DMA Hostless",
  5292. .cpu_dai_name = "TX3_CDC_DMA_HOSTLESS",
  5293. .platform_name = "msm-pcm-hostless",
  5294. .dynamic = 1,
  5295. .dpcm_capture = 1,
  5296. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5297. SND_SOC_DPCM_TRIGGER_POST},
  5298. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5299. .ignore_suspend = 1,
  5300. .codec_dai_name = "snd-soc-dummy-dai",
  5301. .codec_name = "snd-soc-dummy",
  5302. },
  5303. {/* hw:x,32 */
  5304. .name = "Tertiary MI2S TX_Hostless",
  5305. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  5306. .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
  5307. .platform_name = "msm-pcm-hostless",
  5308. .dynamic = 1,
  5309. .dpcm_capture = 1,
  5310. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5311. SND_SOC_DPCM_TRIGGER_POST},
  5312. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5313. .ignore_suspend = 1,
  5314. .ignore_pmdown_time = 1,
  5315. .codec_dai_name = "snd-soc-dummy-dai",
  5316. .codec_name = "snd-soc-dummy",
  5317. },
  5318. };
  5319. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5320. {/* hw:x,33 */
  5321. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5322. .stream_name = "WSA CDC DMA0 Capture",
  5323. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5324. .platform_name = "msm-pcm-hostless",
  5325. .codec_name = "bolero_codec",
  5326. .codec_dai_name = "wsa_macro_vifeedback",
  5327. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5328. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5329. .ignore_suspend = 1,
  5330. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5331. .ops = &msm_cdc_dma_be_ops,
  5332. },
  5333. };
  5334. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5335. {/* hw:x,34 */
  5336. .name = MSM_DAILINK_NAME(ASM Loopback),
  5337. .stream_name = "MultiMedia6",
  5338. .cpu_dai_name = "MultiMedia6",
  5339. .platform_name = "msm-pcm-loopback",
  5340. .dynamic = 1,
  5341. .dpcm_playback = 1,
  5342. .dpcm_capture = 1,
  5343. .codec_dai_name = "snd-soc-dummy-dai",
  5344. .codec_name = "snd-soc-dummy",
  5345. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5346. SND_SOC_DPCM_TRIGGER_POST},
  5347. .ignore_suspend = 1,
  5348. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5349. .ignore_pmdown_time = 1,
  5350. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5351. },
  5352. {/* hw:x,35 */
  5353. .name = "USB Audio Hostless",
  5354. .stream_name = "USB Audio Hostless",
  5355. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5356. .platform_name = "msm-pcm-hostless",
  5357. .dynamic = 1,
  5358. .dpcm_playback = 1,
  5359. .dpcm_capture = 1,
  5360. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5361. SND_SOC_DPCM_TRIGGER_POST},
  5362. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5363. .ignore_suspend = 1,
  5364. .ignore_pmdown_time = 1,
  5365. .codec_dai_name = "snd-soc-dummy-dai",
  5366. .codec_name = "snd-soc-dummy",
  5367. },
  5368. {/* hw:x,36 */
  5369. .name = "SLIMBUS_7 Hostless",
  5370. .stream_name = "SLIMBUS_7 Hostless",
  5371. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5372. .platform_name = "msm-pcm-hostless",
  5373. .dynamic = 1,
  5374. .dpcm_capture = 1,
  5375. .dpcm_playback = 1,
  5376. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5377. SND_SOC_DPCM_TRIGGER_POST},
  5378. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5379. .ignore_suspend = 1,
  5380. .ignore_pmdown_time = 1,
  5381. .codec_dai_name = "snd-soc-dummy-dai",
  5382. .codec_name = "snd-soc-dummy",
  5383. },
  5384. {/* hw:x,37 */
  5385. .name = "Compress Capture",
  5386. .stream_name = "Compress9",
  5387. .cpu_dai_name = "MultiMedia17",
  5388. .platform_name = "msm-compress-dsp",
  5389. .dynamic = 1,
  5390. .dpcm_capture = 1,
  5391. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5392. SND_SOC_DPCM_TRIGGER_POST},
  5393. .codec_dai_name = "snd-soc-dummy-dai",
  5394. .codec_name = "snd-soc-dummy",
  5395. .ignore_suspend = 1,
  5396. .ignore_pmdown_time = 1,
  5397. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  5398. },
  5399. {/* hw:x,38 */
  5400. .name = "SLIMBUS_8 Hostless",
  5401. .stream_name = "SLIMBUS_8 Hostless",
  5402. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5403. .platform_name = "msm-pcm-hostless",
  5404. .dynamic = 1,
  5405. .dpcm_capture = 1,
  5406. .dpcm_playback = 1,
  5407. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5408. SND_SOC_DPCM_TRIGGER_POST},
  5409. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5410. .ignore_suspend = 1,
  5411. .ignore_pmdown_time = 1,
  5412. .codec_dai_name = "snd-soc-dummy-dai",
  5413. .codec_name = "snd-soc-dummy",
  5414. },
  5415. {/* hw:x,39 */
  5416. .name = LPASS_BE_TX_CDC_DMA_TX_5,
  5417. .stream_name = "TX CDC DMA5 Capture",
  5418. .cpu_dai_name = "msm-dai-cdc-dma-dev.45115",
  5419. .platform_name = "msm-pcm-hostless",
  5420. .codec_name = "bolero_codec",
  5421. .codec_dai_name = "tx_macro_tx3",
  5422. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_5,
  5423. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5424. .ignore_suspend = 1,
  5425. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5426. .ops = &msm_cdc_dma_be_ops,
  5427. },
  5428. };
  5429. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5430. /* Backend AFE DAI Links */
  5431. {
  5432. .name = LPASS_BE_AFE_PCM_RX,
  5433. .stream_name = "AFE Playback",
  5434. .cpu_dai_name = "msm-dai-q6-dev.224",
  5435. .platform_name = "msm-pcm-routing",
  5436. .codec_name = "msm-stub-codec.1",
  5437. .codec_dai_name = "msm-stub-rx",
  5438. .no_pcm = 1,
  5439. .dpcm_playback = 1,
  5440. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5441. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5442. /* this dainlink has playback support */
  5443. .ignore_pmdown_time = 1,
  5444. .ignore_suspend = 1,
  5445. },
  5446. {
  5447. .name = LPASS_BE_AFE_PCM_TX,
  5448. .stream_name = "AFE Capture",
  5449. .cpu_dai_name = "msm-dai-q6-dev.225",
  5450. .platform_name = "msm-pcm-routing",
  5451. .codec_name = "msm-stub-codec.1",
  5452. .codec_dai_name = "msm-stub-tx",
  5453. .no_pcm = 1,
  5454. .dpcm_capture = 1,
  5455. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5456. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5457. .ignore_suspend = 1,
  5458. },
  5459. /* Incall Record Uplink BACK END DAI Link */
  5460. {
  5461. .name = LPASS_BE_INCALL_RECORD_TX,
  5462. .stream_name = "Voice Uplink Capture",
  5463. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5464. .platform_name = "msm-pcm-routing",
  5465. .codec_name = "msm-stub-codec.1",
  5466. .codec_dai_name = "msm-stub-tx",
  5467. .no_pcm = 1,
  5468. .dpcm_capture = 1,
  5469. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5470. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5471. .ignore_suspend = 1,
  5472. },
  5473. /* Incall Record Downlink BACK END DAI Link */
  5474. {
  5475. .name = LPASS_BE_INCALL_RECORD_RX,
  5476. .stream_name = "Voice Downlink Capture",
  5477. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5478. .platform_name = "msm-pcm-routing",
  5479. .codec_name = "msm-stub-codec.1",
  5480. .codec_dai_name = "msm-stub-tx",
  5481. .no_pcm = 1,
  5482. .dpcm_capture = 1,
  5483. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5484. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5485. .ignore_suspend = 1,
  5486. },
  5487. /* Incall Music BACK END DAI Link */
  5488. {
  5489. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5490. .stream_name = "Voice Farend Playback",
  5491. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5492. .platform_name = "msm-pcm-routing",
  5493. .codec_name = "msm-stub-codec.1",
  5494. .codec_dai_name = "msm-stub-rx",
  5495. .no_pcm = 1,
  5496. .dpcm_playback = 1,
  5497. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5498. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5499. .ignore_suspend = 1,
  5500. .ignore_pmdown_time = 1,
  5501. },
  5502. /* Incall Music 2 BACK END DAI Link */
  5503. {
  5504. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5505. .stream_name = "Voice2 Farend Playback",
  5506. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5507. .platform_name = "msm-pcm-routing",
  5508. .codec_name = "msm-stub-codec.1",
  5509. .codec_dai_name = "msm-stub-rx",
  5510. .no_pcm = 1,
  5511. .dpcm_playback = 1,
  5512. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5513. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5514. .ignore_suspend = 1,
  5515. .ignore_pmdown_time = 1,
  5516. },
  5517. {
  5518. .name = LPASS_BE_USB_AUDIO_RX,
  5519. .stream_name = "USB Audio Playback",
  5520. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5521. .platform_name = "msm-pcm-routing",
  5522. .codec_name = "msm-stub-codec.1",
  5523. .codec_dai_name = "msm-stub-rx",
  5524. .dynamic_be = 1,
  5525. .no_pcm = 1,
  5526. .dpcm_playback = 1,
  5527. .id = MSM_BACKEND_DAI_USB_RX,
  5528. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5529. .ignore_pmdown_time = 1,
  5530. .ignore_suspend = 1,
  5531. },
  5532. {
  5533. .name = LPASS_BE_USB_AUDIO_TX,
  5534. .stream_name = "USB Audio Capture",
  5535. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5536. .platform_name = "msm-pcm-routing",
  5537. .codec_name = "msm-stub-codec.1",
  5538. .codec_dai_name = "msm-stub-tx",
  5539. .no_pcm = 1,
  5540. .dpcm_capture = 1,
  5541. .id = MSM_BACKEND_DAI_USB_TX,
  5542. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5543. .ignore_suspend = 1,
  5544. },
  5545. {
  5546. .name = LPASS_BE_PRI_TDM_RX_0,
  5547. .stream_name = "Primary TDM0 Playback",
  5548. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5549. .platform_name = "msm-pcm-routing",
  5550. .codec_name = "msm-stub-codec.1",
  5551. .codec_dai_name = "msm-stub-rx",
  5552. .no_pcm = 1,
  5553. .dpcm_playback = 1,
  5554. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5555. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5556. .ops = &kona_tdm_be_ops,
  5557. .ignore_suspend = 1,
  5558. .ignore_pmdown_time = 1,
  5559. },
  5560. {
  5561. .name = LPASS_BE_PRI_TDM_TX_0,
  5562. .stream_name = "Primary TDM0 Capture",
  5563. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5564. .platform_name = "msm-pcm-routing",
  5565. .codec_name = "msm-stub-codec.1",
  5566. .codec_dai_name = "msm-stub-tx",
  5567. .no_pcm = 1,
  5568. .dpcm_capture = 1,
  5569. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5570. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5571. .ops = &kona_tdm_be_ops,
  5572. .ignore_suspend = 1,
  5573. },
  5574. {
  5575. .name = LPASS_BE_SEC_TDM_RX_0,
  5576. .stream_name = "Secondary TDM0 Playback",
  5577. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5578. .platform_name = "msm-pcm-routing",
  5579. .codec_name = "msm-stub-codec.1",
  5580. .codec_dai_name = "msm-stub-rx",
  5581. .no_pcm = 1,
  5582. .dpcm_playback = 1,
  5583. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5584. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5585. .ops = &kona_tdm_be_ops,
  5586. .ignore_suspend = 1,
  5587. .ignore_pmdown_time = 1,
  5588. },
  5589. {
  5590. .name = LPASS_BE_SEC_TDM_TX_0,
  5591. .stream_name = "Secondary TDM0 Capture",
  5592. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5593. .platform_name = "msm-pcm-routing",
  5594. .codec_name = "msm-stub-codec.1",
  5595. .codec_dai_name = "msm-stub-tx",
  5596. .no_pcm = 1,
  5597. .dpcm_capture = 1,
  5598. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5599. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5600. .ops = &kona_tdm_be_ops,
  5601. .ignore_suspend = 1,
  5602. },
  5603. {
  5604. .name = LPASS_BE_TERT_TDM_RX_0,
  5605. .stream_name = "Tertiary TDM0 Playback",
  5606. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5607. .platform_name = "msm-pcm-routing",
  5608. .codec_name = "msm-stub-codec.1",
  5609. .codec_dai_name = "msm-stub-rx",
  5610. .no_pcm = 1,
  5611. .dpcm_playback = 1,
  5612. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5613. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5614. .ops = &kona_tdm_be_ops,
  5615. .ignore_suspend = 1,
  5616. .ignore_pmdown_time = 1,
  5617. },
  5618. {
  5619. .name = LPASS_BE_TERT_TDM_TX_0,
  5620. .stream_name = "Tertiary TDM0 Capture",
  5621. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5622. .platform_name = "msm-pcm-routing",
  5623. .codec_name = "msm-stub-codec.1",
  5624. .codec_dai_name = "msm-stub-tx",
  5625. .no_pcm = 1,
  5626. .dpcm_capture = 1,
  5627. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5628. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5629. .ops = &kona_tdm_be_ops,
  5630. .ignore_suspend = 1,
  5631. },
  5632. {
  5633. .name = LPASS_BE_QUAT_TDM_RX_0,
  5634. .stream_name = "Quaternary TDM0 Playback",
  5635. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5636. .platform_name = "msm-pcm-routing",
  5637. .codec_name = "msm-stub-codec.1",
  5638. .codec_dai_name = "msm-stub-rx",
  5639. .no_pcm = 1,
  5640. .dpcm_playback = 1,
  5641. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5642. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5643. .ops = &kona_tdm_be_ops,
  5644. .ignore_suspend = 1,
  5645. .ignore_pmdown_time = 1,
  5646. },
  5647. {
  5648. .name = LPASS_BE_QUAT_TDM_TX_0,
  5649. .stream_name = "Quaternary TDM0 Capture",
  5650. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5651. .platform_name = "msm-pcm-routing",
  5652. .codec_name = "msm-stub-codec.1",
  5653. .codec_dai_name = "msm-stub-tx",
  5654. .no_pcm = 1,
  5655. .dpcm_capture = 1,
  5656. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5657. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5658. .ops = &kona_tdm_be_ops,
  5659. .ignore_suspend = 1,
  5660. },
  5661. {
  5662. .name = LPASS_BE_QUIN_TDM_RX_0,
  5663. .stream_name = "Quinary TDM0 Playback",
  5664. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5665. .platform_name = "msm-pcm-routing",
  5666. .codec_name = "msm-stub-codec.1",
  5667. .codec_dai_name = "msm-stub-rx",
  5668. .no_pcm = 1,
  5669. .dpcm_playback = 1,
  5670. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5671. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5672. .ops = &kona_tdm_be_ops,
  5673. .ignore_suspend = 1,
  5674. .ignore_pmdown_time = 1,
  5675. },
  5676. {
  5677. .name = LPASS_BE_QUIN_TDM_TX_0,
  5678. .stream_name = "Quinary TDM0 Capture",
  5679. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5680. .platform_name = "msm-pcm-routing",
  5681. .codec_name = "msm-stub-codec.1",
  5682. .codec_dai_name = "msm-stub-tx",
  5683. .no_pcm = 1,
  5684. .dpcm_capture = 1,
  5685. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5686. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5687. .ops = &kona_tdm_be_ops,
  5688. .ignore_suspend = 1,
  5689. },
  5690. {
  5691. .name = LPASS_BE_SEN_TDM_RX_0,
  5692. .stream_name = "Senary TDM0 Playback",
  5693. .cpu_dai_name = "msm-dai-q6-tdm.36944",
  5694. .platform_name = "msm-pcm-routing",
  5695. .codec_name = "msm-stub-codec.1",
  5696. .codec_dai_name = "msm-stub-rx",
  5697. .no_pcm = 1,
  5698. .dpcm_playback = 1,
  5699. .id = MSM_BACKEND_DAI_SEN_TDM_RX_0,
  5700. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5701. .ops = &kona_tdm_be_ops,
  5702. .ignore_suspend = 1,
  5703. .ignore_pmdown_time = 1,
  5704. },
  5705. {
  5706. .name = LPASS_BE_SEN_TDM_TX_0,
  5707. .stream_name = "Senary TDM0 Capture",
  5708. .cpu_dai_name = "msm-dai-q6-tdm.36945",
  5709. .platform_name = "msm-pcm-routing",
  5710. .codec_name = "msm-stub-codec.1",
  5711. .codec_dai_name = "msm-stub-tx",
  5712. .no_pcm = 1,
  5713. .dpcm_capture = 1,
  5714. .id = MSM_BACKEND_DAI_SEN_TDM_TX_0,
  5715. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5716. .ops = &kona_tdm_be_ops,
  5717. .ignore_suspend = 1,
  5718. },
  5719. };
  5720. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5721. {
  5722. .name = LPASS_BE_SLIMBUS_7_RX,
  5723. .stream_name = "Slimbus7 Playback",
  5724. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5725. .platform_name = "msm-pcm-routing",
  5726. .codec_name = "btfmslim_slave",
  5727. /* BT codec driver determines capabilities based on
  5728. * dai name, bt codecdai name should always contains
  5729. * supported usecase information
  5730. */
  5731. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5732. .no_pcm = 1,
  5733. .dpcm_playback = 1,
  5734. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5735. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5736. .init = &msm_wcn_init,
  5737. .ops = &msm_wcn_ops,
  5738. /* dai link has playback support */
  5739. .ignore_pmdown_time = 1,
  5740. .ignore_suspend = 1,
  5741. },
  5742. {
  5743. .name = LPASS_BE_SLIMBUS_7_TX,
  5744. .stream_name = "Slimbus7 Capture",
  5745. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5746. .platform_name = "msm-pcm-routing",
  5747. .codec_name = "btfmslim_slave",
  5748. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5749. .no_pcm = 1,
  5750. .dpcm_capture = 1,
  5751. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5752. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5753. .ops = &msm_wcn_ops,
  5754. .ignore_suspend = 1,
  5755. },
  5756. };
  5757. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  5758. {
  5759. .name = LPASS_BE_SLIMBUS_7_RX,
  5760. .stream_name = "Slimbus7 Playback",
  5761. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5762. .platform_name = "msm-pcm-routing",
  5763. .codec_name = "btfmslim_slave",
  5764. /* BT codec driver determines capabilities based on
  5765. * dai name, bt codecdai name should always contains
  5766. * supported usecase information
  5767. */
  5768. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5769. .no_pcm = 1,
  5770. .dpcm_playback = 1,
  5771. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5772. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5773. .init = &msm_wcn_init_lito,
  5774. .ops = &msm_wcn_ops_lito,
  5775. /* dai link has playback support */
  5776. .ignore_pmdown_time = 1,
  5777. .ignore_suspend = 1,
  5778. },
  5779. {
  5780. .name = LPASS_BE_SLIMBUS_7_TX,
  5781. .stream_name = "Slimbus7 Capture",
  5782. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5783. .platform_name = "msm-pcm-routing",
  5784. .codec_name = "btfmslim_slave",
  5785. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5786. .no_pcm = 1,
  5787. .dpcm_capture = 1,
  5788. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5789. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5790. .ops = &msm_wcn_ops_lito,
  5791. .ignore_suspend = 1,
  5792. },
  5793. {
  5794. .name = LPASS_BE_SLIMBUS_8_TX,
  5795. .stream_name = "Slimbus8 Capture",
  5796. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5797. .platform_name = "msm-pcm-routing",
  5798. .codec_name = "btfmslim_slave",
  5799. .codec_dai_name = "btfm_fm_slim_tx",
  5800. .no_pcm = 1,
  5801. .dpcm_capture = 1,
  5802. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5803. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5804. .ops = &msm_wcn_ops_lito,
  5805. .ignore_suspend = 1,
  5806. },
  5807. };
  5808. static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
  5809. /* DISP PORT BACK END DAI Link */
  5810. {
  5811. .name = LPASS_BE_DISPLAY_PORT,
  5812. .stream_name = "Display Port Playback",
  5813. .cpu_dai_name = "msm-dai-q6-dp.0",
  5814. .platform_name = "msm-pcm-routing",
  5815. .codec_name = "msm-ext-disp-audio-codec-rx",
  5816. .codec_dai_name = "msm_dp_audio_codec_rx_dai",
  5817. .no_pcm = 1,
  5818. .dpcm_playback = 1,
  5819. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
  5820. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5821. .ignore_pmdown_time = 1,
  5822. .ignore_suspend = 1,
  5823. },
  5824. /* DISP PORT 1 BACK END DAI Link */
  5825. {
  5826. .name = LPASS_BE_DISPLAY_PORT1,
  5827. .stream_name = "Display Port1 Playback",
  5828. .cpu_dai_name = "msm-dai-q6-dp.1",
  5829. .platform_name = "msm-pcm-routing",
  5830. .codec_name = "msm-ext-disp-audio-codec-rx",
  5831. .codec_dai_name = "msm_dp_audio_codec_rx1_dai",
  5832. .no_pcm = 1,
  5833. .dpcm_playback = 1,
  5834. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX_1,
  5835. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5836. .ignore_pmdown_time = 1,
  5837. .ignore_suspend = 1,
  5838. },
  5839. };
  5840. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5841. {
  5842. .name = LPASS_BE_PRI_MI2S_RX,
  5843. .stream_name = "Primary MI2S Playback",
  5844. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5845. .platform_name = "msm-pcm-routing",
  5846. .codec_name = "msm-stub-codec.1",
  5847. .codec_dai_name = "msm-stub-rx",
  5848. .no_pcm = 1,
  5849. .dpcm_playback = 1,
  5850. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5851. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5852. .ops = &msm_mi2s_be_ops,
  5853. .ignore_suspend = 1,
  5854. .ignore_pmdown_time = 1,
  5855. },
  5856. {
  5857. .name = LPASS_BE_PRI_MI2S_TX,
  5858. .stream_name = "Primary MI2S Capture",
  5859. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5860. .platform_name = "msm-pcm-routing",
  5861. .codec_name = "msm-stub-codec.1",
  5862. .codec_dai_name = "msm-stub-tx",
  5863. .no_pcm = 1,
  5864. .dpcm_capture = 1,
  5865. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5866. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5867. .ops = &msm_mi2s_be_ops,
  5868. .ignore_suspend = 1,
  5869. },
  5870. {
  5871. .name = LPASS_BE_SEC_MI2S_RX,
  5872. .stream_name = "Secondary MI2S Playback",
  5873. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5874. .platform_name = "msm-pcm-routing",
  5875. .codec_name = "msm-stub-codec.1",
  5876. .codec_dai_name = "msm-stub-rx",
  5877. .no_pcm = 1,
  5878. .dpcm_playback = 1,
  5879. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5880. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5881. .ops = &msm_mi2s_be_ops,
  5882. .ignore_suspend = 1,
  5883. .ignore_pmdown_time = 1,
  5884. },
  5885. {
  5886. .name = LPASS_BE_SEC_MI2S_TX,
  5887. .stream_name = "Secondary MI2S Capture",
  5888. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5889. .platform_name = "msm-pcm-routing",
  5890. .codec_name = "msm-stub-codec.1",
  5891. .codec_dai_name = "msm-stub-tx",
  5892. .no_pcm = 1,
  5893. .dpcm_capture = 1,
  5894. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5895. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5896. .ops = &msm_mi2s_be_ops,
  5897. .ignore_suspend = 1,
  5898. },
  5899. {
  5900. .name = LPASS_BE_TERT_MI2S_RX,
  5901. .stream_name = "Tertiary MI2S Playback",
  5902. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5903. .platform_name = "msm-pcm-routing",
  5904. .codec_name = "msm-stub-codec.1",
  5905. .codec_dai_name = "msm-stub-rx",
  5906. .no_pcm = 1,
  5907. .dpcm_playback = 1,
  5908. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5909. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5910. .ops = &msm_mi2s_be_ops,
  5911. .ignore_suspend = 1,
  5912. .ignore_pmdown_time = 1,
  5913. },
  5914. {
  5915. .name = LPASS_BE_TERT_MI2S_TX,
  5916. .stream_name = "Tertiary MI2S Capture",
  5917. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5918. .platform_name = "msm-pcm-routing",
  5919. .codec_name = "msm-stub-codec.1",
  5920. .codec_dai_name = "msm-stub-tx",
  5921. .no_pcm = 1,
  5922. .dpcm_capture = 1,
  5923. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5924. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5925. .ops = &msm_mi2s_be_ops,
  5926. .ignore_suspend = 1,
  5927. },
  5928. {
  5929. .name = LPASS_BE_QUAT_MI2S_RX,
  5930. .stream_name = "Quaternary MI2S Playback",
  5931. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5932. .platform_name = "msm-pcm-routing",
  5933. .codec_name = "msm-stub-codec.1",
  5934. .codec_dai_name = "msm-stub-rx",
  5935. .no_pcm = 1,
  5936. .dpcm_playback = 1,
  5937. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5938. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5939. .ops = &msm_mi2s_be_ops,
  5940. .ignore_suspend = 1,
  5941. .ignore_pmdown_time = 1,
  5942. },
  5943. {
  5944. .name = LPASS_BE_QUAT_MI2S_TX,
  5945. .stream_name = "Quaternary MI2S Capture",
  5946. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5947. .platform_name = "msm-pcm-routing",
  5948. .codec_name = "msm-stub-codec.1",
  5949. .codec_dai_name = "msm-stub-tx",
  5950. .no_pcm = 1,
  5951. .dpcm_capture = 1,
  5952. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5953. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5954. .ops = &msm_mi2s_be_ops,
  5955. .ignore_suspend = 1,
  5956. },
  5957. {
  5958. .name = LPASS_BE_QUIN_MI2S_RX,
  5959. .stream_name = "Quinary MI2S Playback",
  5960. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5961. .platform_name = "msm-pcm-routing",
  5962. .codec_name = "msm-stub-codec.1",
  5963. .codec_dai_name = "msm-stub-rx",
  5964. .no_pcm = 1,
  5965. .dpcm_playback = 1,
  5966. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5967. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5968. .ops = &msm_mi2s_be_ops,
  5969. .ignore_suspend = 1,
  5970. .ignore_pmdown_time = 1,
  5971. },
  5972. {
  5973. .name = LPASS_BE_QUIN_MI2S_TX,
  5974. .stream_name = "Quinary MI2S Capture",
  5975. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5976. .platform_name = "msm-pcm-routing",
  5977. .codec_name = "msm-stub-codec.1",
  5978. .codec_dai_name = "msm-stub-tx",
  5979. .no_pcm = 1,
  5980. .dpcm_capture = 1,
  5981. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5982. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5983. .ops = &msm_mi2s_be_ops,
  5984. .ignore_suspend = 1,
  5985. },
  5986. {
  5987. .name = LPASS_BE_SENARY_MI2S_RX,
  5988. .stream_name = "Senary MI2S Playback",
  5989. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  5990. .platform_name = "msm-pcm-routing",
  5991. .codec_name = "msm-stub-codec.1",
  5992. .codec_dai_name = "msm-stub-rx",
  5993. .no_pcm = 1,
  5994. .dpcm_playback = 1,
  5995. .id = MSM_BACKEND_DAI_SENARY_MI2S_RX,
  5996. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5997. .ops = &msm_mi2s_be_ops,
  5998. .ignore_suspend = 1,
  5999. .ignore_pmdown_time = 1,
  6000. },
  6001. {
  6002. .name = LPASS_BE_SENARY_MI2S_TX,
  6003. .stream_name = "Senary MI2S Capture",
  6004. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  6005. .platform_name = "msm-pcm-routing",
  6006. .codec_name = "msm-stub-codec.1",
  6007. .codec_dai_name = "msm-stub-tx",
  6008. .no_pcm = 1,
  6009. .dpcm_capture = 1,
  6010. .id = MSM_BACKEND_DAI_SENARY_MI2S_TX,
  6011. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6012. .ops = &msm_mi2s_be_ops,
  6013. .ignore_suspend = 1,
  6014. },
  6015. };
  6016. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6017. /* Primary AUX PCM Backend DAI Links */
  6018. {
  6019. .name = LPASS_BE_AUXPCM_RX,
  6020. .stream_name = "AUX PCM Playback",
  6021. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6022. .platform_name = "msm-pcm-routing",
  6023. .codec_name = "msm-stub-codec.1",
  6024. .codec_dai_name = "msm-stub-rx",
  6025. .no_pcm = 1,
  6026. .dpcm_playback = 1,
  6027. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6028. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6029. .ops = &kona_aux_be_ops,
  6030. .ignore_pmdown_time = 1,
  6031. .ignore_suspend = 1,
  6032. },
  6033. {
  6034. .name = LPASS_BE_AUXPCM_TX,
  6035. .stream_name = "AUX PCM Capture",
  6036. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6037. .platform_name = "msm-pcm-routing",
  6038. .codec_name = "msm-stub-codec.1",
  6039. .codec_dai_name = "msm-stub-tx",
  6040. .no_pcm = 1,
  6041. .dpcm_capture = 1,
  6042. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6043. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6044. .ops = &kona_aux_be_ops,
  6045. .ignore_suspend = 1,
  6046. },
  6047. /* Secondary AUX PCM Backend DAI Links */
  6048. {
  6049. .name = LPASS_BE_SEC_AUXPCM_RX,
  6050. .stream_name = "Sec AUX PCM Playback",
  6051. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6052. .platform_name = "msm-pcm-routing",
  6053. .codec_name = "msm-stub-codec.1",
  6054. .codec_dai_name = "msm-stub-rx",
  6055. .no_pcm = 1,
  6056. .dpcm_playback = 1,
  6057. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6058. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6059. .ops = &kona_aux_be_ops,
  6060. .ignore_pmdown_time = 1,
  6061. .ignore_suspend = 1,
  6062. },
  6063. {
  6064. .name = LPASS_BE_SEC_AUXPCM_TX,
  6065. .stream_name = "Sec AUX PCM Capture",
  6066. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6067. .platform_name = "msm-pcm-routing",
  6068. .codec_name = "msm-stub-codec.1",
  6069. .codec_dai_name = "msm-stub-tx",
  6070. .no_pcm = 1,
  6071. .dpcm_capture = 1,
  6072. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6073. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6074. .ops = &kona_aux_be_ops,
  6075. .ignore_suspend = 1,
  6076. },
  6077. /* Tertiary AUX PCM Backend DAI Links */
  6078. {
  6079. .name = LPASS_BE_TERT_AUXPCM_RX,
  6080. .stream_name = "Tert AUX PCM Playback",
  6081. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6082. .platform_name = "msm-pcm-routing",
  6083. .codec_name = "msm-stub-codec.1",
  6084. .codec_dai_name = "msm-stub-rx",
  6085. .no_pcm = 1,
  6086. .dpcm_playback = 1,
  6087. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6088. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6089. .ops = &kona_aux_be_ops,
  6090. .ignore_suspend = 1,
  6091. },
  6092. {
  6093. .name = LPASS_BE_TERT_AUXPCM_TX,
  6094. .stream_name = "Tert AUX PCM Capture",
  6095. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6096. .platform_name = "msm-pcm-routing",
  6097. .codec_name = "msm-stub-codec.1",
  6098. .codec_dai_name = "msm-stub-tx",
  6099. .no_pcm = 1,
  6100. .dpcm_capture = 1,
  6101. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6102. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6103. .ops = &kona_aux_be_ops,
  6104. .ignore_suspend = 1,
  6105. },
  6106. /* Quaternary AUX PCM Backend DAI Links */
  6107. {
  6108. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6109. .stream_name = "Quat AUX PCM Playback",
  6110. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6111. .platform_name = "msm-pcm-routing",
  6112. .codec_name = "msm-stub-codec.1",
  6113. .codec_dai_name = "msm-stub-rx",
  6114. .no_pcm = 1,
  6115. .dpcm_playback = 1,
  6116. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6117. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6118. .ops = &kona_aux_be_ops,
  6119. .ignore_suspend = 1,
  6120. },
  6121. {
  6122. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6123. .stream_name = "Quat AUX PCM Capture",
  6124. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6125. .platform_name = "msm-pcm-routing",
  6126. .codec_name = "msm-stub-codec.1",
  6127. .codec_dai_name = "msm-stub-tx",
  6128. .no_pcm = 1,
  6129. .dpcm_capture = 1,
  6130. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6131. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6132. .ops = &kona_aux_be_ops,
  6133. .ignore_suspend = 1,
  6134. },
  6135. /* Quinary AUX PCM Backend DAI Links */
  6136. {
  6137. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6138. .stream_name = "Quin AUX PCM Playback",
  6139. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6140. .platform_name = "msm-pcm-routing",
  6141. .codec_name = "msm-stub-codec.1",
  6142. .codec_dai_name = "msm-stub-rx",
  6143. .no_pcm = 1,
  6144. .dpcm_playback = 1,
  6145. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6146. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6147. .ops = &kona_aux_be_ops,
  6148. .ignore_suspend = 1,
  6149. },
  6150. {
  6151. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6152. .stream_name = "Quin AUX PCM Capture",
  6153. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6154. .platform_name = "msm-pcm-routing",
  6155. .codec_name = "msm-stub-codec.1",
  6156. .codec_dai_name = "msm-stub-tx",
  6157. .no_pcm = 1,
  6158. .dpcm_capture = 1,
  6159. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6160. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6161. .ops = &kona_aux_be_ops,
  6162. .ignore_suspend = 1,
  6163. },
  6164. /* Senary AUX PCM Backend DAI Links */
  6165. {
  6166. .name = LPASS_BE_SEN_AUXPCM_RX,
  6167. .stream_name = "Sen AUX PCM Playback",
  6168. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  6169. .platform_name = "msm-pcm-routing",
  6170. .codec_name = "msm-stub-codec.1",
  6171. .codec_dai_name = "msm-stub-rx",
  6172. .no_pcm = 1,
  6173. .dpcm_playback = 1,
  6174. .id = MSM_BACKEND_DAI_SEN_AUXPCM_RX,
  6175. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6176. .ops = &kona_aux_be_ops,
  6177. .ignore_suspend = 1,
  6178. },
  6179. {
  6180. .name = LPASS_BE_SEN_AUXPCM_TX,
  6181. .stream_name = "Sen AUX PCM Capture",
  6182. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  6183. .platform_name = "msm-pcm-routing",
  6184. .codec_name = "msm-stub-codec.1",
  6185. .codec_dai_name = "msm-stub-tx",
  6186. .no_pcm = 1,
  6187. .dpcm_capture = 1,
  6188. .id = MSM_BACKEND_DAI_SEN_AUXPCM_TX,
  6189. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6190. .ops = &kona_aux_be_ops,
  6191. .ignore_suspend = 1,
  6192. },
  6193. };
  6194. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6195. /* WSA CDC DMA Backend DAI Links */
  6196. {
  6197. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6198. .stream_name = "WSA CDC DMA0 Playback",
  6199. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6200. .platform_name = "msm-pcm-routing",
  6201. .codec_name = "bolero_codec",
  6202. .codec_dai_name = "wsa_macro_rx1",
  6203. .no_pcm = 1,
  6204. .dpcm_playback = 1,
  6205. .init = &msm_int_audrx_init,
  6206. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6207. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6208. .ignore_pmdown_time = 1,
  6209. .ignore_suspend = 1,
  6210. .ops = &msm_cdc_dma_be_ops,
  6211. },
  6212. {
  6213. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6214. .stream_name = "WSA CDC DMA1 Playback",
  6215. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6216. .platform_name = "msm-pcm-routing",
  6217. .codec_name = "bolero_codec",
  6218. .codec_dai_name = "wsa_macro_rx_mix",
  6219. .no_pcm = 1,
  6220. .dpcm_playback = 1,
  6221. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6222. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6223. .ignore_pmdown_time = 1,
  6224. .ignore_suspend = 1,
  6225. .ops = &msm_cdc_dma_be_ops,
  6226. },
  6227. {
  6228. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6229. .stream_name = "WSA CDC DMA1 Capture",
  6230. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6231. .platform_name = "msm-pcm-routing",
  6232. .codec_name = "bolero_codec",
  6233. .codec_dai_name = "wsa_macro_echo",
  6234. .no_pcm = 1,
  6235. .dpcm_capture = 1,
  6236. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6237. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6238. .ignore_suspend = 1,
  6239. .ops = &msm_cdc_dma_be_ops,
  6240. },
  6241. };
  6242. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  6243. /* RX CDC DMA Backend DAI Links */
  6244. {
  6245. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  6246. .stream_name = "RX CDC DMA0 Playback",
  6247. .cpu_dai_name = "msm-dai-cdc-dma-dev.45104",
  6248. .platform_name = "msm-pcm-routing",
  6249. .codec_name = "bolero_codec",
  6250. .codec_dai_name = "rx_macro_rx1",
  6251. .dynamic_be = 1,
  6252. .no_pcm = 1,
  6253. .dpcm_playback = 1,
  6254. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  6255. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6256. .ignore_pmdown_time = 1,
  6257. .ignore_suspend = 1,
  6258. .ops = &msm_cdc_dma_be_ops,
  6259. },
  6260. {
  6261. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  6262. .stream_name = "RX CDC DMA1 Playback",
  6263. .cpu_dai_name = "msm-dai-cdc-dma-dev.45106",
  6264. .platform_name = "msm-pcm-routing",
  6265. .codec_name = "bolero_codec",
  6266. .codec_dai_name = "rx_macro_rx2",
  6267. .dynamic_be = 1,
  6268. .no_pcm = 1,
  6269. .dpcm_playback = 1,
  6270. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  6271. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6272. .ignore_pmdown_time = 1,
  6273. .ignore_suspend = 1,
  6274. .ops = &msm_cdc_dma_be_ops,
  6275. },
  6276. {
  6277. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  6278. .stream_name = "RX CDC DMA2 Playback",
  6279. .cpu_dai_name = "msm-dai-cdc-dma-dev.45108",
  6280. .platform_name = "msm-pcm-routing",
  6281. .codec_name = "bolero_codec",
  6282. .codec_dai_name = "rx_macro_rx3",
  6283. .dynamic_be = 1,
  6284. .no_pcm = 1,
  6285. .dpcm_playback = 1,
  6286. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  6287. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6288. .ignore_pmdown_time = 1,
  6289. .ignore_suspend = 1,
  6290. .ops = &msm_cdc_dma_be_ops,
  6291. },
  6292. {
  6293. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  6294. .stream_name = "RX CDC DMA3 Playback",
  6295. .cpu_dai_name = "msm-dai-cdc-dma-dev.45110",
  6296. .platform_name = "msm-pcm-routing",
  6297. .codec_name = "bolero_codec",
  6298. .codec_dai_name = "rx_macro_rx4",
  6299. .dynamic_be = 1,
  6300. .no_pcm = 1,
  6301. .dpcm_playback = 1,
  6302. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  6303. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6304. .ignore_pmdown_time = 1,
  6305. .ignore_suspend = 1,
  6306. .ops = &msm_cdc_dma_be_ops,
  6307. },
  6308. /* TX CDC DMA Backend DAI Links */
  6309. {
  6310. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  6311. .stream_name = "TX CDC DMA3 Capture",
  6312. .cpu_dai_name = "msm-dai-cdc-dma-dev.45111",
  6313. .platform_name = "msm-pcm-routing",
  6314. .codec_name = "bolero_codec",
  6315. .codec_dai_name = "tx_macro_tx1",
  6316. .no_pcm = 1,
  6317. .dpcm_capture = 1,
  6318. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  6319. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6320. .ignore_suspend = 1,
  6321. .ops = &msm_cdc_dma_be_ops,
  6322. },
  6323. {
  6324. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  6325. .stream_name = "TX CDC DMA4 Capture",
  6326. .cpu_dai_name = "msm-dai-cdc-dma-dev.45113",
  6327. .platform_name = "msm-pcm-routing",
  6328. .codec_name = "bolero_codec",
  6329. .codec_dai_name = "tx_macro_tx2",
  6330. .no_pcm = 1,
  6331. .dpcm_capture = 1,
  6332. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  6333. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6334. .ignore_suspend = 1,
  6335. .ops = &msm_cdc_dma_be_ops,
  6336. },
  6337. };
  6338. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6339. {
  6340. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6341. .stream_name = "VA CDC DMA0 Capture",
  6342. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6343. .platform_name = "msm-pcm-routing",
  6344. .codec_name = "bolero_codec",
  6345. .codec_dai_name = "va_macro_tx1",
  6346. .no_pcm = 1,
  6347. .dpcm_capture = 1,
  6348. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6349. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6350. .ignore_suspend = 1,
  6351. .ops = &msm_cdc_dma_be_ops,
  6352. },
  6353. {
  6354. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6355. .stream_name = "VA CDC DMA1 Capture",
  6356. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6357. .platform_name = "msm-pcm-routing",
  6358. .codec_name = "bolero_codec",
  6359. .codec_dai_name = "va_macro_tx2",
  6360. .no_pcm = 1,
  6361. .dpcm_capture = 1,
  6362. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6363. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6364. .ignore_suspend = 1,
  6365. .ops = &msm_cdc_dma_be_ops,
  6366. },
  6367. {
  6368. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  6369. .stream_name = "VA CDC DMA2 Capture",
  6370. .cpu_dai_name = "msm-dai-cdc-dma-dev.45093",
  6371. .platform_name = "msm-pcm-routing",
  6372. .codec_name = "bolero_codec",
  6373. .codec_dai_name = "va_macro_tx3",
  6374. .no_pcm = 1,
  6375. .dpcm_capture = 1,
  6376. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  6377. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6378. .ignore_suspend = 1,
  6379. .ops = &msm_cdc_dma_be_ops,
  6380. },
  6381. };
  6382. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  6383. {
  6384. .name = LPASS_BE_AFE_LOOPBACK_TX,
  6385. .stream_name = "AFE Loopback Capture",
  6386. .cpu_dai_name = "msm-dai-q6-dev.24577",
  6387. .platform_name = "msm-pcm-routing",
  6388. .codec_name = "msm-stub-codec.1",
  6389. .codec_dai_name = "msm-stub-tx",
  6390. .no_pcm = 1,
  6391. .dpcm_capture = 1,
  6392. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  6393. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6394. .ignore_pmdown_time = 1,
  6395. .ignore_suspend = 1,
  6396. },
  6397. };
  6398. static struct snd_soc_dai_link msm_kona_dai_links[
  6399. ARRAY_SIZE(msm_common_dai_links) +
  6400. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6401. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6402. ARRAY_SIZE(msm_common_be_dai_links) +
  6403. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6404. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6405. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6406. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  6407. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6408. ARRAY_SIZE(ext_disp_be_dai_link) +
  6409. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6410. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  6411. ARRAY_SIZE(msm_wcn_btfm_be_dai_links)];
  6412. static int msm_populate_dai_link_component_of_node(
  6413. struct snd_soc_card *card)
  6414. {
  6415. int i, index, ret = 0;
  6416. struct device *cdev = card->dev;
  6417. struct snd_soc_dai_link *dai_link = card->dai_link;
  6418. struct device_node *np;
  6419. if (!cdev) {
  6420. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  6421. return -ENODEV;
  6422. }
  6423. for (i = 0; i < card->num_links; i++) {
  6424. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6425. continue;
  6426. /* populate platform_of_node for snd card dai links */
  6427. if (dai_link[i].platform_name &&
  6428. !dai_link[i].platform_of_node) {
  6429. index = of_property_match_string(cdev->of_node,
  6430. "asoc-platform-names",
  6431. dai_link[i].platform_name);
  6432. if (index < 0) {
  6433. dev_err(cdev, "%s: No match found for platform name: %s\n",
  6434. __func__, dai_link[i].platform_name);
  6435. ret = index;
  6436. goto err;
  6437. }
  6438. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6439. index);
  6440. if (!np) {
  6441. dev_err(cdev, "%s: retrieving phandle for platform %s, index %d failed\n",
  6442. __func__, dai_link[i].platform_name,
  6443. index);
  6444. ret = -ENODEV;
  6445. goto err;
  6446. }
  6447. dai_link[i].platform_of_node = np;
  6448. dai_link[i].platform_name = NULL;
  6449. }
  6450. /* populate cpu_of_node for snd card dai links */
  6451. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6452. index = of_property_match_string(cdev->of_node,
  6453. "asoc-cpu-names",
  6454. dai_link[i].cpu_dai_name);
  6455. if (index >= 0) {
  6456. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6457. index);
  6458. if (!np) {
  6459. dev_err(cdev, "%s: retrieving phandle for cpu dai %s failed\n",
  6460. __func__,
  6461. dai_link[i].cpu_dai_name);
  6462. ret = -ENODEV;
  6463. goto err;
  6464. }
  6465. dai_link[i].cpu_of_node = np;
  6466. dai_link[i].cpu_dai_name = NULL;
  6467. }
  6468. }
  6469. /* populate codec_of_node for snd card dai links */
  6470. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6471. index = of_property_match_string(cdev->of_node,
  6472. "asoc-codec-names",
  6473. dai_link[i].codec_name);
  6474. if (index < 0)
  6475. continue;
  6476. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6477. index);
  6478. if (!np) {
  6479. dev_err(cdev, "%s: retrieving phandle for codec %s failed\n",
  6480. __func__, dai_link[i].codec_name);
  6481. ret = -ENODEV;
  6482. goto err;
  6483. }
  6484. dai_link[i].codec_of_node = np;
  6485. dai_link[i].codec_name = NULL;
  6486. }
  6487. }
  6488. err:
  6489. return ret;
  6490. }
  6491. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  6492. {
  6493. int ret = -EINVAL;
  6494. struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  6495. if (!component) {
  6496. pr_err("* %s: No match for msm-stub-codec component\n", __func__);
  6497. return ret;
  6498. }
  6499. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  6500. ARRAY_SIZE(msm_snd_controls));
  6501. if (ret < 0) {
  6502. dev_err(component->dev,
  6503. "%s: add_codec_controls failed, err = %d\n",
  6504. __func__, ret);
  6505. return ret;
  6506. }
  6507. return ret;
  6508. }
  6509. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  6510. struct snd_pcm_hw_params *params)
  6511. {
  6512. return 0;
  6513. }
  6514. static struct snd_soc_ops msm_stub_be_ops = {
  6515. .hw_params = msm_snd_stub_hw_params,
  6516. };
  6517. struct snd_soc_card snd_soc_card_stub_msm = {
  6518. .name = "kona-stub-snd-card",
  6519. };
  6520. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6521. /* FrontEnd DAI Links */
  6522. {
  6523. .name = "MSMSTUB Media1",
  6524. .stream_name = "MultiMedia1",
  6525. .cpu_dai_name = "MultiMedia1",
  6526. .platform_name = "msm-pcm-dsp.0",
  6527. .dynamic = 1,
  6528. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6529. .dpcm_playback = 1,
  6530. .dpcm_capture = 1,
  6531. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6532. SND_SOC_DPCM_TRIGGER_POST},
  6533. .codec_dai_name = "snd-soc-dummy-dai",
  6534. .codec_name = "snd-soc-dummy",
  6535. .ignore_suspend = 1,
  6536. /* this dainlink has playback support */
  6537. .ignore_pmdown_time = 1,
  6538. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6539. },
  6540. };
  6541. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6542. /* Backend DAI Links */
  6543. {
  6544. .name = LPASS_BE_AUXPCM_RX,
  6545. .stream_name = "AUX PCM Playback",
  6546. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6547. .platform_name = "msm-pcm-routing",
  6548. .codec_name = "msm-stub-codec.1",
  6549. .codec_dai_name = "msm-stub-rx",
  6550. .no_pcm = 1,
  6551. .dpcm_playback = 1,
  6552. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6553. .init = &msm_audrx_stub_init,
  6554. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6555. .ignore_pmdown_time = 1,
  6556. .ignore_suspend = 1,
  6557. .ops = &msm_stub_be_ops,
  6558. },
  6559. {
  6560. .name = LPASS_BE_AUXPCM_TX,
  6561. .stream_name = "AUX PCM Capture",
  6562. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6563. .platform_name = "msm-pcm-routing",
  6564. .codec_name = "msm-stub-codec.1",
  6565. .codec_dai_name = "msm-stub-tx",
  6566. .no_pcm = 1,
  6567. .dpcm_capture = 1,
  6568. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6569. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6570. .ignore_suspend = 1,
  6571. .ops = &msm_stub_be_ops,
  6572. },
  6573. };
  6574. static struct snd_soc_dai_link msm_stub_dai_links[
  6575. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6576. ARRAY_SIZE(msm_stub_be_dai_links)];
  6577. static const struct of_device_id kona_asoc_machine_of_match[] = {
  6578. { .compatible = "qcom,kona-asoc-snd",
  6579. .data = "codec"},
  6580. { .compatible = "qcom,kona-asoc-snd-stub",
  6581. .data = "stub_codec"},
  6582. {},
  6583. };
  6584. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6585. {
  6586. struct snd_soc_card *card = NULL;
  6587. struct snd_soc_dai_link *dailink = NULL;
  6588. int len_1 = 0;
  6589. int len_2 = 0;
  6590. int total_links = 0;
  6591. int rc = 0;
  6592. u32 mi2s_audio_intf = 0;
  6593. u32 auxpcm_audio_intf = 0;
  6594. u32 val = 0;
  6595. u32 wcn_btfm_intf = 0;
  6596. const struct of_device_id *match;
  6597. match = of_match_node(kona_asoc_machine_of_match, dev->of_node);
  6598. if (!match) {
  6599. dev_err(dev, "%s: No DT match found for sound card\n",
  6600. __func__);
  6601. return NULL;
  6602. }
  6603. if (!strcmp(match->data, "codec")) {
  6604. card = &snd_soc_card_kona_msm;
  6605. memcpy(msm_kona_dai_links + total_links,
  6606. msm_common_dai_links,
  6607. sizeof(msm_common_dai_links));
  6608. total_links += ARRAY_SIZE(msm_common_dai_links);
  6609. memcpy(msm_kona_dai_links + total_links,
  6610. msm_bolero_fe_dai_links,
  6611. sizeof(msm_bolero_fe_dai_links));
  6612. total_links +=
  6613. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6614. memcpy(msm_kona_dai_links + total_links,
  6615. msm_common_misc_fe_dai_links,
  6616. sizeof(msm_common_misc_fe_dai_links));
  6617. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6618. memcpy(msm_kona_dai_links + total_links,
  6619. msm_common_be_dai_links,
  6620. sizeof(msm_common_be_dai_links));
  6621. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6622. memcpy(msm_kona_dai_links + total_links,
  6623. msm_wsa_cdc_dma_be_dai_links,
  6624. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6625. total_links +=
  6626. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6627. memcpy(msm_kona_dai_links + total_links,
  6628. msm_rx_tx_cdc_dma_be_dai_links,
  6629. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  6630. total_links +=
  6631. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
  6632. memcpy(msm_kona_dai_links + total_links,
  6633. msm_va_cdc_dma_be_dai_links,
  6634. sizeof(msm_va_cdc_dma_be_dai_links));
  6635. total_links +=
  6636. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6637. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6638. &mi2s_audio_intf);
  6639. if (rc) {
  6640. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6641. __func__);
  6642. } else {
  6643. if (mi2s_audio_intf) {
  6644. memcpy(msm_kona_dai_links + total_links,
  6645. msm_mi2s_be_dai_links,
  6646. sizeof(msm_mi2s_be_dai_links));
  6647. total_links +=
  6648. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6649. }
  6650. }
  6651. rc = of_property_read_u32(dev->of_node,
  6652. "qcom,auxpcm-audio-intf",
  6653. &auxpcm_audio_intf);
  6654. if (rc) {
  6655. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6656. __func__);
  6657. } else {
  6658. if (auxpcm_audio_intf) {
  6659. memcpy(msm_kona_dai_links + total_links,
  6660. msm_auxpcm_be_dai_links,
  6661. sizeof(msm_auxpcm_be_dai_links));
  6662. total_links +=
  6663. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6664. }
  6665. }
  6666. rc = of_property_read_u32(dev->of_node,
  6667. "qcom,ext-disp-audio-rx", &val);
  6668. if (!rc && val) {
  6669. dev_dbg(dev, "%s(): ext disp audio support present\n",
  6670. __func__);
  6671. memcpy(msm_kona_dai_links + total_links,
  6672. ext_disp_be_dai_link,
  6673. sizeof(ext_disp_be_dai_link));
  6674. total_links += ARRAY_SIZE(ext_disp_be_dai_link);
  6675. }
  6676. rc = of_property_read_u32(dev->of_node, "qcom,wcn-bt", &val);
  6677. if (!rc && val) {
  6678. dev_dbg(dev, "%s(): WCN BT support present\n",
  6679. __func__);
  6680. memcpy(msm_kona_dai_links + total_links,
  6681. msm_wcn_be_dai_links,
  6682. sizeof(msm_wcn_be_dai_links));
  6683. total_links += ARRAY_SIZE(msm_wcn_be_dai_links);
  6684. }
  6685. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  6686. &val);
  6687. if (!rc && val) {
  6688. memcpy(msm_kona_dai_links + total_links,
  6689. msm_afe_rxtx_lb_be_dai_link,
  6690. sizeof(msm_afe_rxtx_lb_be_dai_link));
  6691. total_links +=
  6692. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  6693. }
  6694. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  6695. &wcn_btfm_intf);
  6696. if (rc) {
  6697. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  6698. __func__);
  6699. } else {
  6700. if (wcn_btfm_intf) {
  6701. memcpy(msm_kona_dai_links + total_links,
  6702. msm_wcn_btfm_be_dai_links,
  6703. sizeof(msm_wcn_btfm_be_dai_links));
  6704. total_links +=
  6705. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  6706. }
  6707. }
  6708. dailink = msm_kona_dai_links;
  6709. } else if(!strcmp(match->data, "stub_codec")) {
  6710. card = &snd_soc_card_stub_msm;
  6711. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  6712. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  6713. memcpy(msm_stub_dai_links,
  6714. msm_stub_fe_dai_links,
  6715. sizeof(msm_stub_fe_dai_links));
  6716. memcpy(msm_stub_dai_links + len_1,
  6717. msm_stub_be_dai_links,
  6718. sizeof(msm_stub_be_dai_links));
  6719. dailink = msm_stub_dai_links;
  6720. total_links = len_2;
  6721. }
  6722. if (card) {
  6723. card->dai_link = dailink;
  6724. card->num_links = total_links;
  6725. }
  6726. return card;
  6727. }
  6728. static int msm_wsa881x_init(struct snd_soc_component *component)
  6729. {
  6730. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6731. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6732. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6733. SPKR_L_BOOST, SPKR_L_VI};
  6734. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6735. SPKR_R_BOOST, SPKR_R_VI};
  6736. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6737. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6738. struct msm_asoc_mach_data *pdata;
  6739. struct snd_soc_dapm_context *dapm;
  6740. struct snd_card *card;
  6741. struct snd_info_entry *entry;
  6742. int ret = 0;
  6743. if (!component) {
  6744. pr_err("%s component is NULL\n", __func__);
  6745. return -EINVAL;
  6746. }
  6747. card = component->card->snd_card;
  6748. dapm = snd_soc_component_get_dapm(component);
  6749. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6750. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  6751. __func__, component->name);
  6752. wsa881x_set_channel_map(component, &spkleft_ports[0],
  6753. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6754. &ch_rate[0], &spkleft_port_types[0]);
  6755. if (dapm->component) {
  6756. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6757. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6758. }
  6759. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6760. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  6761. __func__, component->name);
  6762. wsa881x_set_channel_map(component, &spkright_ports[0],
  6763. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6764. &ch_rate[0], &spkright_port_types[0]);
  6765. if (dapm->component) {
  6766. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6767. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6768. }
  6769. } else {
  6770. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  6771. component->name);
  6772. ret = -EINVAL;
  6773. goto err;
  6774. }
  6775. pdata = snd_soc_card_get_drvdata(component->card);
  6776. if (!pdata->codec_root) {
  6777. entry = snd_info_create_subdir(card->module, "codecs",
  6778. card->proc_root);
  6779. if (!entry) {
  6780. pr_err("%s: Cannot create codecs module entry\n",
  6781. __func__);
  6782. ret = 0;
  6783. goto err;
  6784. }
  6785. pdata->codec_root = entry;
  6786. }
  6787. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6788. component);
  6789. err:
  6790. return ret;
  6791. }
  6792. static int msm_aux_codec_init(struct snd_soc_component *component)
  6793. {
  6794. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  6795. int ret = 0;
  6796. int codec_variant = -1;
  6797. void *mbhc_calibration;
  6798. struct snd_info_entry *entry;
  6799. struct snd_card *card = component->card->snd_card;
  6800. struct msm_asoc_mach_data *pdata;
  6801. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  6802. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  6803. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  6804. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  6805. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  6806. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  6807. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  6808. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  6809. snd_soc_dapm_sync(dapm);
  6810. pdata = snd_soc_card_get_drvdata(component->card);
  6811. if (!pdata->codec_root) {
  6812. entry = snd_info_create_subdir(card->module, "codecs",
  6813. card->proc_root);
  6814. if (!entry) {
  6815. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  6816. __func__);
  6817. ret = 0;
  6818. goto mbhc_cfg_cal;
  6819. }
  6820. pdata->codec_root = entry;
  6821. }
  6822. wcd938x_info_create_codec_entry(pdata->codec_root, component);
  6823. codec_variant = wcd938x_get_codec_variant(component);
  6824. dev_dbg(component->dev, "%s: variant %d\n", __func__, codec_variant);
  6825. if (codec_variant == WCD9380)
  6826. ret = snd_soc_add_component_controls(component,
  6827. msm_int_wcd9380_snd_controls,
  6828. ARRAY_SIZE(msm_int_wcd9380_snd_controls));
  6829. else if (codec_variant == WCD9385)
  6830. ret = snd_soc_add_component_controls(component,
  6831. msm_int_wcd9385_snd_controls,
  6832. ARRAY_SIZE(msm_int_wcd9385_snd_controls));
  6833. if (ret < 0) {
  6834. dev_err(component->dev, "%s: add codec specific snd controls failed: %d\n",
  6835. __func__, ret);
  6836. return ret;
  6837. }
  6838. mbhc_cfg_cal:
  6839. mbhc_calibration = def_wcd_mbhc_cal();
  6840. if (!mbhc_calibration)
  6841. return -ENOMEM;
  6842. wcd_mbhc_cfg.calibration = mbhc_calibration;
  6843. ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  6844. if (ret) {
  6845. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  6846. __func__, ret);
  6847. goto err_hs_detect;
  6848. }
  6849. return 0;
  6850. err_hs_detect:
  6851. kfree(mbhc_calibration);
  6852. return ret;
  6853. }
  6854. static int msm_init_aux_dev(struct platform_device *pdev,
  6855. struct snd_soc_card *card)
  6856. {
  6857. struct device_node *wsa_of_node;
  6858. struct device_node *aux_codec_of_node;
  6859. u32 wsa_max_devs;
  6860. u32 wsa_dev_cnt;
  6861. u32 codec_max_aux_devs = 0;
  6862. u32 codec_aux_dev_cnt = 0;
  6863. int i;
  6864. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6865. struct aux_codec_dev_info *aux_cdc_dev_info;
  6866. const char *auxdev_name_prefix[1];
  6867. char *dev_name_str = NULL;
  6868. int found = 0;
  6869. int codecs_found = 0;
  6870. int ret = 0;
  6871. /* Get maximum WSA device count for this platform */
  6872. ret = of_property_read_u32(pdev->dev.of_node,
  6873. "qcom,wsa-max-devs", &wsa_max_devs);
  6874. if (ret) {
  6875. dev_info(&pdev->dev,
  6876. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6877. __func__, pdev->dev.of_node->full_name, ret);
  6878. wsa_max_devs = 0;
  6879. goto codec_aux_dev;
  6880. }
  6881. if (wsa_max_devs == 0) {
  6882. dev_warn(&pdev->dev,
  6883. "%s: Max WSA devices is 0 for this target?\n",
  6884. __func__);
  6885. goto codec_aux_dev;
  6886. }
  6887. /* Get count of WSA device phandles for this platform */
  6888. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6889. "qcom,wsa-devs", NULL);
  6890. if (wsa_dev_cnt == -ENOENT) {
  6891. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6892. __func__);
  6893. goto err;
  6894. } else if (wsa_dev_cnt <= 0) {
  6895. dev_err(&pdev->dev,
  6896. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6897. __func__, wsa_dev_cnt);
  6898. ret = -EINVAL;
  6899. goto err;
  6900. }
  6901. /*
  6902. * Expect total phandles count to be NOT less than maximum possible
  6903. * WSA count. However, if it is less, then assign same value to
  6904. * max count as well.
  6905. */
  6906. if (wsa_dev_cnt < wsa_max_devs) {
  6907. dev_dbg(&pdev->dev,
  6908. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6909. __func__, wsa_max_devs, wsa_dev_cnt);
  6910. wsa_max_devs = wsa_dev_cnt;
  6911. }
  6912. /* Make sure prefix string passed for each WSA device */
  6913. ret = of_property_count_strings(pdev->dev.of_node,
  6914. "qcom,wsa-aux-dev-prefix");
  6915. if (ret != wsa_dev_cnt) {
  6916. dev_err(&pdev->dev,
  6917. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6918. __func__, wsa_dev_cnt, ret);
  6919. ret = -EINVAL;
  6920. goto err;
  6921. }
  6922. /*
  6923. * Alloc mem to store phandle and index info of WSA device, if already
  6924. * registered with ALSA core
  6925. */
  6926. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6927. sizeof(struct msm_wsa881x_dev_info),
  6928. GFP_KERNEL);
  6929. if (!wsa881x_dev_info) {
  6930. ret = -ENOMEM;
  6931. goto err;
  6932. }
  6933. /*
  6934. * search and check whether all WSA devices are already
  6935. * registered with ALSA core or not. If found a node, store
  6936. * the node and the index in a local array of struct for later
  6937. * use.
  6938. */
  6939. for (i = 0; i < wsa_dev_cnt; i++) {
  6940. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6941. "qcom,wsa-devs", i);
  6942. if (unlikely(!wsa_of_node)) {
  6943. /* we should not be here */
  6944. dev_err(&pdev->dev,
  6945. "%s: wsa dev node is not present\n",
  6946. __func__);
  6947. ret = -EINVAL;
  6948. goto err;
  6949. }
  6950. if (soc_find_component(wsa_of_node, NULL)) {
  6951. /* WSA device registered with ALSA core */
  6952. wsa881x_dev_info[found].of_node = wsa_of_node;
  6953. wsa881x_dev_info[found].index = i;
  6954. found++;
  6955. if (found == wsa_max_devs)
  6956. break;
  6957. }
  6958. }
  6959. if (found < wsa_max_devs) {
  6960. dev_dbg(&pdev->dev,
  6961. "%s: failed to find %d components. Found only %d\n",
  6962. __func__, wsa_max_devs, found);
  6963. return -EPROBE_DEFER;
  6964. }
  6965. dev_info(&pdev->dev,
  6966. "%s: found %d wsa881x devices registered with ALSA core\n",
  6967. __func__, found);
  6968. codec_aux_dev:
  6969. /* Get maximum aux codec device count for this platform */
  6970. ret = of_property_read_u32(pdev->dev.of_node,
  6971. "qcom,codec-max-aux-devs",
  6972. &codec_max_aux_devs);
  6973. if (ret) {
  6974. dev_err(&pdev->dev,
  6975. "%s: codec-max-aux-devs property missing in DT %s, ret = %d\n",
  6976. __func__, pdev->dev.of_node->full_name, ret);
  6977. codec_max_aux_devs = 0;
  6978. goto aux_dev_register;
  6979. }
  6980. if (codec_max_aux_devs == 0) {
  6981. dev_dbg(&pdev->dev,
  6982. "%s: Max aux codec devices is 0 for this target?\n",
  6983. __func__);
  6984. goto aux_dev_register;
  6985. }
  6986. /* Get count of aux codec device phandles for this platform */
  6987. codec_aux_dev_cnt = of_count_phandle_with_args(
  6988. pdev->dev.of_node,
  6989. "qcom,codec-aux-devs", NULL);
  6990. if (codec_aux_dev_cnt == -ENOENT) {
  6991. dev_warn(&pdev->dev, "%s: No aux codec defined in DT.\n",
  6992. __func__);
  6993. goto err;
  6994. } else if (codec_aux_dev_cnt <= 0) {
  6995. dev_err(&pdev->dev,
  6996. "%s: Error reading aux codec device from DT, dev_cnt=%d\n",
  6997. __func__, codec_aux_dev_cnt);
  6998. ret = -EINVAL;
  6999. goto err;
  7000. }
  7001. /*
  7002. * Expect total phandles count to be NOT less than maximum possible
  7003. * AUX device count. However, if it is less, then assign same value to
  7004. * max count as well.
  7005. */
  7006. if (codec_aux_dev_cnt < codec_max_aux_devs) {
  7007. dev_dbg(&pdev->dev,
  7008. "%s: codec_max_aux_devs = %d cannot exceed codec_aux_dev_cnt = %d\n",
  7009. __func__, codec_max_aux_devs,
  7010. codec_aux_dev_cnt);
  7011. codec_max_aux_devs = codec_aux_dev_cnt;
  7012. }
  7013. /*
  7014. * Alloc mem to store phandle and index info of aux codec
  7015. * if already registered with ALSA core
  7016. */
  7017. aux_cdc_dev_info = devm_kcalloc(&pdev->dev, codec_aux_dev_cnt,
  7018. sizeof(struct aux_codec_dev_info),
  7019. GFP_KERNEL);
  7020. if (!aux_cdc_dev_info) {
  7021. ret = -ENOMEM;
  7022. goto err;
  7023. }
  7024. /*
  7025. * search and check whether all aux codecs are already
  7026. * registered with ALSA core or not. If found a node, store
  7027. * the node and the index in a local array of struct for later
  7028. * use.
  7029. */
  7030. for (i = 0; i < codec_aux_dev_cnt; i++) {
  7031. aux_codec_of_node = of_parse_phandle(pdev->dev.of_node,
  7032. "qcom,codec-aux-devs", i);
  7033. if (unlikely(!aux_codec_of_node)) {
  7034. /* we should not be here */
  7035. dev_err(&pdev->dev,
  7036. "%s: aux codec dev node is not present\n",
  7037. __func__);
  7038. ret = -EINVAL;
  7039. goto err;
  7040. }
  7041. if (soc_find_component(aux_codec_of_node, NULL)) {
  7042. /* AUX codec registered with ALSA core */
  7043. aux_cdc_dev_info[codecs_found].of_node =
  7044. aux_codec_of_node;
  7045. aux_cdc_dev_info[codecs_found].index = i;
  7046. codecs_found++;
  7047. }
  7048. }
  7049. if (codecs_found < codec_aux_dev_cnt) {
  7050. dev_dbg(&pdev->dev,
  7051. "%s: failed to find %d components. Found only %d\n",
  7052. __func__, codec_aux_dev_cnt, codecs_found);
  7053. return -EPROBE_DEFER;
  7054. }
  7055. dev_info(&pdev->dev,
  7056. "%s: found %d AUX codecs registered with ALSA core\n",
  7057. __func__, codecs_found);
  7058. aux_dev_register:
  7059. card->num_aux_devs = wsa_max_devs + codec_aux_dev_cnt;
  7060. card->num_configs = wsa_max_devs + codec_aux_dev_cnt;
  7061. /* Alloc array of AUX devs struct */
  7062. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7063. sizeof(struct snd_soc_aux_dev),
  7064. GFP_KERNEL);
  7065. if (!msm_aux_dev) {
  7066. ret = -ENOMEM;
  7067. goto err;
  7068. }
  7069. /* Alloc array of codec conf struct */
  7070. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_configs,
  7071. sizeof(struct snd_soc_codec_conf),
  7072. GFP_KERNEL);
  7073. if (!msm_codec_conf) {
  7074. ret = -ENOMEM;
  7075. goto err;
  7076. }
  7077. for (i = 0; i < wsa_max_devs; i++) {
  7078. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7079. GFP_KERNEL);
  7080. if (!dev_name_str) {
  7081. ret = -ENOMEM;
  7082. goto err;
  7083. }
  7084. ret = of_property_read_string_index(pdev->dev.of_node,
  7085. "qcom,wsa-aux-dev-prefix",
  7086. wsa881x_dev_info[i].index,
  7087. auxdev_name_prefix);
  7088. if (ret) {
  7089. dev_err(&pdev->dev,
  7090. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7091. __func__, ret);
  7092. ret = -EINVAL;
  7093. goto err;
  7094. }
  7095. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7096. msm_aux_dev[i].name = dev_name_str;
  7097. msm_aux_dev[i].codec_name = NULL;
  7098. msm_aux_dev[i].codec_of_node =
  7099. wsa881x_dev_info[i].of_node;
  7100. msm_aux_dev[i].init = msm_wsa881x_init;
  7101. msm_codec_conf[i].dev_name = NULL;
  7102. msm_codec_conf[i].name_prefix = auxdev_name_prefix[0];
  7103. msm_codec_conf[i].of_node =
  7104. wsa881x_dev_info[i].of_node;
  7105. }
  7106. for (i = 0; i < codec_aux_dev_cnt; i++) {
  7107. msm_aux_dev[wsa_max_devs + i].name = NULL;
  7108. msm_aux_dev[wsa_max_devs + i].codec_name = NULL;
  7109. msm_aux_dev[wsa_max_devs + i].codec_of_node =
  7110. aux_cdc_dev_info[i].of_node;
  7111. msm_aux_dev[wsa_max_devs + i].init = msm_aux_codec_init;
  7112. msm_codec_conf[wsa_max_devs + i].dev_name = NULL;
  7113. msm_codec_conf[wsa_max_devs + i].name_prefix =
  7114. NULL;
  7115. msm_codec_conf[wsa_max_devs + i].of_node =
  7116. aux_cdc_dev_info[i].of_node;
  7117. }
  7118. card->codec_conf = msm_codec_conf;
  7119. card->aux_dev = msm_aux_dev;
  7120. err:
  7121. return ret;
  7122. }
  7123. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7124. {
  7125. int count = 0;
  7126. u32 mi2s_master_slave[MI2S_MAX];
  7127. int ret = 0;
  7128. for (count = 0; count < MI2S_MAX; count++) {
  7129. mutex_init(&mi2s_intf_conf[count].lock);
  7130. mi2s_intf_conf[count].ref_cnt = 0;
  7131. }
  7132. ret = of_property_read_u32_array(pdev->dev.of_node,
  7133. "qcom,msm-mi2s-master",
  7134. mi2s_master_slave, MI2S_MAX);
  7135. if (ret) {
  7136. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7137. __func__);
  7138. } else {
  7139. for (count = 0; count < MI2S_MAX; count++) {
  7140. mi2s_intf_conf[count].msm_is_mi2s_master =
  7141. mi2s_master_slave[count];
  7142. }
  7143. }
  7144. }
  7145. static void msm_i2s_auxpcm_deinit(void)
  7146. {
  7147. int count = 0;
  7148. for (count = 0; count < MI2S_MAX; count++) {
  7149. mutex_destroy(&mi2s_intf_conf[count].lock);
  7150. mi2s_intf_conf[count].ref_cnt = 0;
  7151. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7152. }
  7153. }
  7154. static int kona_ssr_enable(struct device *dev, void *data)
  7155. {
  7156. struct platform_device *pdev = to_platform_device(dev);
  7157. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7158. int ret = 0;
  7159. if (!card) {
  7160. dev_err(dev, "%s: card is NULL\n", __func__);
  7161. ret = -EINVAL;
  7162. goto err;
  7163. }
  7164. if (!strcmp(card->name, "kona-stub-snd-card")) {
  7165. /* TODO */
  7166. dev_dbg(dev, "%s: TODO \n", __func__);
  7167. }
  7168. snd_soc_card_change_online_state(card, 1);
  7169. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  7170. err:
  7171. return ret;
  7172. }
  7173. static void kona_ssr_disable(struct device *dev, void *data)
  7174. {
  7175. struct platform_device *pdev = to_platform_device(dev);
  7176. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7177. if (!card) {
  7178. dev_err(dev, "%s: card is NULL\n", __func__);
  7179. return;
  7180. }
  7181. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  7182. snd_soc_card_change_online_state(card, 0);
  7183. if (!strcmp(card->name, "kona-stub-snd-card")) {
  7184. /* TODO */
  7185. dev_dbg(dev, "%s: TODO \n", __func__);
  7186. }
  7187. }
  7188. static const struct snd_event_ops kona_ssr_ops = {
  7189. .enable = kona_ssr_enable,
  7190. .disable = kona_ssr_disable,
  7191. };
  7192. static int msm_audio_ssr_compare(struct device *dev, void *data)
  7193. {
  7194. struct device_node *node = data;
  7195. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  7196. __func__, dev->of_node, node);
  7197. return (dev->of_node && dev->of_node == node);
  7198. }
  7199. static int msm_audio_ssr_register(struct device *dev)
  7200. {
  7201. struct device_node *np = dev->of_node;
  7202. struct snd_event_clients *ssr_clients = NULL;
  7203. struct device_node *node = NULL;
  7204. int ret = 0;
  7205. int i = 0;
  7206. for (i = 0; ; i++) {
  7207. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  7208. if (!node)
  7209. break;
  7210. snd_event_mstr_add_client(&ssr_clients,
  7211. msm_audio_ssr_compare, node);
  7212. }
  7213. ret = snd_event_master_register(dev, &kona_ssr_ops,
  7214. ssr_clients, NULL);
  7215. if (!ret)
  7216. snd_event_notify(dev, SND_EVENT_UP);
  7217. return ret;
  7218. }
  7219. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7220. {
  7221. struct snd_soc_card *card = NULL;
  7222. struct msm_asoc_mach_data *pdata = NULL;
  7223. const char *mbhc_audio_jack_type = NULL;
  7224. int ret = 0;
  7225. uint index = 0;
  7226. if (!pdev->dev.of_node) {
  7227. dev_err(&pdev->dev, "%s: No platform supplied from device tree\n", __func__);
  7228. return -EINVAL;
  7229. }
  7230. pdata = devm_kzalloc(&pdev->dev,
  7231. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7232. if (!pdata)
  7233. return -ENOMEM;
  7234. card = populate_snd_card_dailinks(&pdev->dev);
  7235. if (!card) {
  7236. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7237. ret = -EINVAL;
  7238. goto err;
  7239. }
  7240. card->dev = &pdev->dev;
  7241. platform_set_drvdata(pdev, card);
  7242. snd_soc_card_set_drvdata(card, pdata);
  7243. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7244. if (ret) {
  7245. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  7246. __func__, ret);
  7247. goto err;
  7248. }
  7249. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7250. if (ret) {
  7251. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  7252. __func__, ret);
  7253. goto err;
  7254. }
  7255. ret = msm_populate_dai_link_component_of_node(card);
  7256. if (ret) {
  7257. ret = -EPROBE_DEFER;
  7258. goto err;
  7259. }
  7260. ret = msm_init_aux_dev(pdev, card);
  7261. if (ret)
  7262. goto err;
  7263. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7264. if (ret == -EPROBE_DEFER) {
  7265. if (codec_reg_done)
  7266. ret = -EINVAL;
  7267. goto err;
  7268. } else if (ret) {
  7269. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  7270. __func__, ret);
  7271. goto err;
  7272. }
  7273. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  7274. __func__, card->name);
  7275. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7276. "qcom,hph-en1-gpio", 0);
  7277. if (!pdata->hph_en1_gpio_p) {
  7278. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  7279. __func__, "qcom,hph-en1-gpio",
  7280. pdev->dev.of_node->full_name);
  7281. }
  7282. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7283. "qcom,hph-en0-gpio", 0);
  7284. if (!pdata->hph_en0_gpio_p) {
  7285. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  7286. __func__, "qcom,hph-en0-gpio",
  7287. pdev->dev.of_node->full_name);
  7288. }
  7289. ret = of_property_read_string(pdev->dev.of_node,
  7290. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  7291. if (ret) {
  7292. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  7293. __func__, "qcom,mbhc-audio-jack-type",
  7294. pdev->dev.of_node->full_name);
  7295. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  7296. } else {
  7297. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  7298. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  7299. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  7300. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  7301. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  7302. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  7303. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  7304. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  7305. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  7306. } else {
  7307. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  7308. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  7309. }
  7310. }
  7311. /*
  7312. * Parse US-Euro gpio info from DT. Report no error if us-euro
  7313. * entry is not found in DT file as some targets do not support
  7314. * US-Euro detection
  7315. */
  7316. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7317. "qcom,us-euro-gpios", 0);
  7318. if (!pdata->us_euro_gpio_p) {
  7319. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  7320. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  7321. } else {
  7322. dev_dbg(&pdev->dev, "%s detected\n",
  7323. "qcom,us-euro-gpios");
  7324. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  7325. }
  7326. if (wcd_mbhc_cfg.enable_usbc_analog)
  7327. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  7328. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  7329. "fsa4480-i2c-handle", 0);
  7330. if (!pdata->fsa_handle)
  7331. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  7332. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  7333. msm_i2s_auxpcm_init(pdev);
  7334. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7335. "qcom,cdc-dmic01-gpios",
  7336. 0);
  7337. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7338. "qcom,cdc-dmic23-gpios",
  7339. 0);
  7340. pdata->dmic45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7341. "qcom,cdc-dmic45-gpios",
  7342. 0);
  7343. if (pdata->dmic01_gpio_p)
  7344. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic01_gpio_p, false);
  7345. if (pdata->dmic23_gpio_p)
  7346. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic23_gpio_p, false);
  7347. if (pdata->dmic45_gpio_p)
  7348. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic45_gpio_p, false);
  7349. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7350. "qcom,pri-mi2s-gpios", 0);
  7351. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7352. "qcom,sec-mi2s-gpios", 0);
  7353. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7354. "qcom,tert-mi2s-gpios", 0);
  7355. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7356. "qcom,quat-mi2s-gpios", 0);
  7357. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7358. "qcom,quin-mi2s-gpios", 0);
  7359. pdata->mi2s_gpio_p[SEN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7360. "qcom,sen-mi2s-gpios", 0);
  7361. for (index = PRIM_MI2S; index < MI2S_MAX; index++)
  7362. atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0);
  7363. ret = msm_audio_ssr_register(&pdev->dev);
  7364. if (ret)
  7365. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  7366. __func__, ret);
  7367. is_initial_boot = true;
  7368. return 0;
  7369. err:
  7370. devm_kfree(&pdev->dev, pdata);
  7371. return ret;
  7372. }
  7373. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7374. {
  7375. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7376. snd_event_master_deregister(&pdev->dev);
  7377. snd_soc_unregister_card(card);
  7378. msm_i2s_auxpcm_deinit();
  7379. return 0;
  7380. }
  7381. static struct platform_driver kona_asoc_machine_driver = {
  7382. .driver = {
  7383. .name = DRV_NAME,
  7384. .owner = THIS_MODULE,
  7385. .pm = &snd_soc_pm_ops,
  7386. .of_match_table = kona_asoc_machine_of_match,
  7387. .suppress_bind_attrs = true,
  7388. },
  7389. .probe = msm_asoc_machine_probe,
  7390. .remove = msm_asoc_machine_remove,
  7391. };
  7392. module_platform_driver(kona_asoc_machine_driver);
  7393. MODULE_DESCRIPTION("ALSA SoC msm");
  7394. MODULE_LICENSE("GPL v2");
  7395. MODULE_ALIAS("platform:" DRV_NAME);
  7396. MODULE_DEVICE_TABLE(of, kona_asoc_machine_of_match);