dp_tx.c 95 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include "qdf_net_types.h"
  27. #include <wlan_cfg.h>
  28. #ifdef MESH_MODE_SUPPORT
  29. #include "if_meta_hdr.h"
  30. #endif
  31. #ifdef TX_PER_PDEV_DESC_POOL
  32. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  33. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  34. #else /* QCA_LL_TX_FLOW_CONTROL_V2 */
  35. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  36. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  37. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  38. #else
  39. #ifdef TX_PER_VDEV_DESC_POOL
  40. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  41. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  42. #else
  43. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  44. #define DP_TX_GET_RING_ID(vdev) vdev->pdev->soc->tx_ring_map[qdf_get_cpu()]
  45. #endif /* TX_PER_VDEV_DESC_POOL */
  46. #endif /* TX_PER_PDEV_DESC_POOL */
  47. /* TODO Add support in TSO */
  48. #define DP_DESC_NUM_FRAG(x) 0
  49. /* disable TQM_BYPASS */
  50. #define TQM_BYPASS_WAR 0
  51. /* invalid peer id for reinject*/
  52. #define DP_INVALID_PEER 0XFFFE
  53. /*mapping between hal encrypt type and cdp_sec_type*/
  54. #define MAX_CDP_SEC_TYPE 12
  55. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  56. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  57. HAL_TX_ENCRYPT_TYPE_WEP_128,
  58. HAL_TX_ENCRYPT_TYPE_WEP_104,
  59. HAL_TX_ENCRYPT_TYPE_WEP_40,
  60. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  61. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  62. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  63. HAL_TX_ENCRYPT_TYPE_WAPI,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  65. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  66. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  68. /**
  69. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  70. * @vdev: DP Virtual device handle
  71. * @nbuf: Buffer pointer
  72. * @queue: queue ids container for nbuf
  73. *
  74. * TX packet queue has 2 instances, software descriptors id and dma ring id
  75. * Based on tx feature and hardware configuration queue id combination could be
  76. * different.
  77. * For example -
  78. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  79. * With no XPS,lock based resource protection, Descriptor pool ids are different
  80. * for each vdev, dma ring id will be same as single pdev id
  81. *
  82. * Return: None
  83. */
  84. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  85. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  86. {
  87. /* get flow id */
  88. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  89. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  90. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  91. "%s, pool_id:%d ring_id: %d",
  92. __func__, queue->desc_pool_id, queue->ring_id);
  93. return;
  94. }
  95. #if defined(FEATURE_TSO)
  96. /**
  97. * dp_tx_tso_desc_release() - Release the tso segment
  98. * after unmapping all the fragments
  99. *
  100. * @pdev - physical device handle
  101. * @tx_desc - Tx software descriptor
  102. */
  103. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  104. struct dp_tx_desc_s *tx_desc)
  105. {
  106. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  107. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  108. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  109. "%s %d TSO desc is NULL!",
  110. __func__, __LINE__);
  111. qdf_assert(0);
  112. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  113. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  114. "%s %d TSO common info is NULL!",
  115. __func__, __LINE__);
  116. qdf_assert(0);
  117. } else {
  118. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  119. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  120. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  121. tso_num_desc->num_seg.tso_cmn_num_seg--;
  122. qdf_nbuf_unmap_tso_segment(soc->osdev,
  123. tx_desc->tso_desc, false);
  124. } else {
  125. tso_num_desc->num_seg.tso_cmn_num_seg--;
  126. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  127. qdf_nbuf_unmap_tso_segment(soc->osdev,
  128. tx_desc->tso_desc, true);
  129. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  130. tx_desc->tso_num_desc);
  131. tx_desc->tso_num_desc = NULL;
  132. }
  133. dp_tx_tso_desc_free(soc,
  134. tx_desc->pool_id, tx_desc->tso_desc);
  135. tx_desc->tso_desc = NULL;
  136. }
  137. }
  138. #else
  139. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  140. struct dp_tx_desc_s *tx_desc)
  141. {
  142. return;
  143. }
  144. #endif
  145. /**
  146. * dp_tx_desc_release() - Release Tx Descriptor
  147. * @tx_desc : Tx Descriptor
  148. * @desc_pool_id: Descriptor Pool ID
  149. *
  150. * Deallocate all resources attached to Tx descriptor and free the Tx
  151. * descriptor.
  152. *
  153. * Return:
  154. */
  155. static void
  156. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  157. {
  158. struct dp_pdev *pdev = tx_desc->pdev;
  159. struct dp_soc *soc;
  160. uint8_t comp_status = 0;
  161. qdf_assert(pdev);
  162. soc = pdev->soc;
  163. if (tx_desc->frm_type == dp_tx_frm_tso)
  164. dp_tx_tso_desc_release(soc, tx_desc);
  165. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  166. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  167. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  168. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  169. qdf_atomic_dec(&pdev->num_tx_outstanding);
  170. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  171. qdf_atomic_dec(&pdev->num_tx_exception);
  172. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  173. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  174. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  175. else
  176. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  177. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  178. "Tx Completion Release desc %d status %d outstanding %d",
  179. tx_desc->id, comp_status,
  180. qdf_atomic_read(&pdev->num_tx_outstanding));
  181. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  182. return;
  183. }
  184. /**
  185. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  186. * @vdev: DP vdev Handle
  187. * @nbuf: skb
  188. *
  189. * Prepares and fills HTT metadata in the frame pre-header for special frames
  190. * that should be transmitted using varying transmit parameters.
  191. * There are 2 VDEV modes that currently needs this special metadata -
  192. * 1) Mesh Mode
  193. * 2) DSRC Mode
  194. *
  195. * Return: HTT metadata size
  196. *
  197. */
  198. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  199. uint32_t *meta_data)
  200. {
  201. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  202. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  203. uint8_t htt_desc_size;
  204. /* Size rounded of multiple of 8 bytes */
  205. uint8_t htt_desc_size_aligned;
  206. uint8_t *hdr = NULL;
  207. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  208. /*
  209. * Metadata - HTT MSDU Extension header
  210. */
  211. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  212. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  213. if (vdev->mesh_vdev) {
  214. /* Fill and add HTT metaheader */
  215. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  216. if (hdr == NULL) {
  217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  218. "Error in filling HTT metadata\n");
  219. return 0;
  220. }
  221. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  222. } else if (vdev->opmode == wlan_op_mode_ocb) {
  223. /* Todo - Add support for DSRC */
  224. }
  225. return htt_desc_size_aligned;
  226. }
  227. /**
  228. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  229. * @tso_seg: TSO segment to process
  230. * @ext_desc: Pointer to MSDU extension descriptor
  231. *
  232. * Return: void
  233. */
  234. #if defined(FEATURE_TSO)
  235. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  236. void *ext_desc)
  237. {
  238. uint8_t num_frag;
  239. uint32_t tso_flags;
  240. /*
  241. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  242. * tcp_flag_mask
  243. *
  244. * Checksum enable flags are set in TCL descriptor and not in Extension
  245. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  246. */
  247. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  248. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  249. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  250. tso_seg->tso_flags.ip_len);
  251. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  252. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  253. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  254. uint32_t lo = 0;
  255. uint32_t hi = 0;
  256. qdf_dmaaddr_to_32s(
  257. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  258. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  259. tso_seg->tso_frags[num_frag].length);
  260. }
  261. return;
  262. }
  263. #else
  264. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  265. void *ext_desc)
  266. {
  267. return;
  268. }
  269. #endif
  270. #if defined(FEATURE_TSO)
  271. /**
  272. * dp_tx_free_tso_seg() - Loop through the tso segments
  273. * allocated and free them
  274. *
  275. * @soc: soc handle
  276. * @free_seg: list of tso segments
  277. * @msdu_info: msdu descriptor
  278. *
  279. * Return - void
  280. */
  281. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  282. struct qdf_tso_seg_elem_t *free_seg,
  283. struct dp_tx_msdu_info_s *msdu_info)
  284. {
  285. struct qdf_tso_seg_elem_t *next_seg;
  286. while (free_seg) {
  287. next_seg = free_seg->next;
  288. dp_tx_tso_desc_free(soc,
  289. msdu_info->tx_queue.desc_pool_id,
  290. free_seg);
  291. free_seg = next_seg;
  292. }
  293. }
  294. /**
  295. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  296. * allocated and free them
  297. *
  298. * @soc: soc handle
  299. * @free_seg: list of tso segments
  300. * @msdu_info: msdu descriptor
  301. * Return - void
  302. */
  303. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  304. struct qdf_tso_num_seg_elem_t *free_seg,
  305. struct dp_tx_msdu_info_s *msdu_info)
  306. {
  307. struct qdf_tso_num_seg_elem_t *next_seg;
  308. while (free_seg) {
  309. next_seg = free_seg->next;
  310. dp_tso_num_seg_free(soc,
  311. msdu_info->tx_queue.desc_pool_id,
  312. free_seg);
  313. free_seg = next_seg;
  314. }
  315. }
  316. /**
  317. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  318. * @vdev: virtual device handle
  319. * @msdu: network buffer
  320. * @msdu_info: meta data associated with the msdu
  321. *
  322. * Return: QDF_STATUS_SUCCESS success
  323. */
  324. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  325. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  326. {
  327. struct qdf_tso_seg_elem_t *tso_seg;
  328. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  329. struct dp_soc *soc = vdev->pdev->soc;
  330. struct qdf_tso_info_t *tso_info;
  331. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  332. tso_info = &msdu_info->u.tso_info;
  333. tso_info->curr_seg = NULL;
  334. tso_info->tso_seg_list = NULL;
  335. tso_info->num_segs = num_seg;
  336. msdu_info->frm_type = dp_tx_frm_tso;
  337. tso_info->tso_num_seg_list = NULL;
  338. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  339. while (num_seg) {
  340. tso_seg = dp_tx_tso_desc_alloc(
  341. soc, msdu_info->tx_queue.desc_pool_id);
  342. if (tso_seg) {
  343. tso_seg->next = tso_info->tso_seg_list;
  344. tso_info->tso_seg_list = tso_seg;
  345. num_seg--;
  346. } else {
  347. struct qdf_tso_seg_elem_t *free_seg =
  348. tso_info->tso_seg_list;
  349. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  350. return QDF_STATUS_E_NOMEM;
  351. }
  352. }
  353. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  354. tso_num_seg = dp_tso_num_seg_alloc(soc,
  355. msdu_info->tx_queue.desc_pool_id);
  356. if (tso_num_seg) {
  357. tso_num_seg->next = tso_info->tso_num_seg_list;
  358. tso_info->tso_num_seg_list = tso_num_seg;
  359. } else {
  360. /* Bug: free tso_num_seg and tso_seg */
  361. /* Free the already allocated num of segments */
  362. struct qdf_tso_seg_elem_t *free_seg =
  363. tso_info->tso_seg_list;
  364. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  365. __func__);
  366. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  367. return QDF_STATUS_E_NOMEM;
  368. }
  369. msdu_info->num_seg =
  370. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  371. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  372. msdu_info->num_seg);
  373. if (!(msdu_info->num_seg)) {
  374. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  375. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  376. msdu_info);
  377. return QDF_STATUS_E_INVAL;
  378. }
  379. tso_info->curr_seg = tso_info->tso_seg_list;
  380. return QDF_STATUS_SUCCESS;
  381. }
  382. #else
  383. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  384. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  385. {
  386. return QDF_STATUS_E_NOMEM;
  387. }
  388. #endif
  389. /**
  390. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  391. * @vdev: DP Vdev handle
  392. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  393. * @desc_pool_id: Descriptor Pool ID
  394. *
  395. * Return:
  396. */
  397. static
  398. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  399. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  400. {
  401. uint8_t i;
  402. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  403. struct dp_tx_seg_info_s *seg_info;
  404. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  405. struct dp_soc *soc = vdev->pdev->soc;
  406. /* Allocate an extension descriptor */
  407. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  408. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  409. if (!msdu_ext_desc) {
  410. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  411. return NULL;
  412. }
  413. if (msdu_info->exception_fw &&
  414. qdf_unlikely(vdev->mesh_vdev)) {
  415. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  416. &msdu_info->meta_data[0],
  417. sizeof(struct htt_tx_msdu_desc_ext2_t));
  418. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  419. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  420. } else
  421. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  422. switch (msdu_info->frm_type) {
  423. case dp_tx_frm_sg:
  424. case dp_tx_frm_me:
  425. case dp_tx_frm_raw:
  426. seg_info = msdu_info->u.sg_info.curr_seg;
  427. /* Update the buffer pointers in MSDU Extension Descriptor */
  428. for (i = 0; i < seg_info->frag_cnt; i++) {
  429. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  430. seg_info->frags[i].paddr_lo,
  431. seg_info->frags[i].paddr_hi,
  432. seg_info->frags[i].len);
  433. }
  434. break;
  435. case dp_tx_frm_tso:
  436. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  437. &cached_ext_desc[0]);
  438. break;
  439. default:
  440. break;
  441. }
  442. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  443. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  444. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  445. msdu_ext_desc->vaddr);
  446. return msdu_ext_desc;
  447. }
  448. /**
  449. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  450. * @vdev: DP vdev handle
  451. * @nbuf: skb
  452. * @desc_pool_id: Descriptor pool ID
  453. * @meta_data: Metadata to the fw
  454. * @tx_exc_metadata: Handle that holds exception path metadata
  455. * Allocate and prepare Tx descriptor with msdu information.
  456. *
  457. * Return: Pointer to Tx Descriptor on success,
  458. * NULL on failure
  459. */
  460. static
  461. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  462. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  463. struct dp_tx_msdu_info_s *msdu_info,
  464. struct cdp_tx_exception_metadata *tx_exc_metadata)
  465. {
  466. uint8_t align_pad;
  467. uint8_t is_exception = 0;
  468. uint8_t htt_hdr_size;
  469. struct ether_header *eh;
  470. struct dp_tx_desc_s *tx_desc;
  471. struct dp_pdev *pdev = vdev->pdev;
  472. struct dp_soc *soc = pdev->soc;
  473. /* Allocate software Tx descriptor */
  474. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  475. if (qdf_unlikely(!tx_desc)) {
  476. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  477. return NULL;
  478. }
  479. /* Flow control/Congestion Control counters */
  480. qdf_atomic_inc(&pdev->num_tx_outstanding);
  481. /* Initialize the SW tx descriptor */
  482. tx_desc->nbuf = nbuf;
  483. tx_desc->frm_type = dp_tx_frm_std;
  484. tx_desc->tx_encap_type = (tx_exc_metadata ?
  485. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  486. tx_desc->vdev = vdev;
  487. tx_desc->pdev = pdev;
  488. tx_desc->msdu_ext_desc = NULL;
  489. tx_desc->pkt_offset = 0;
  490. /*
  491. * For special modes (vdev_type == ocb or mesh), data frames should be
  492. * transmitted using varying transmit parameters (tx spec) which include
  493. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  494. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  495. * These frames are sent as exception packets to firmware.
  496. *
  497. * HW requirement is that metadata should always point to a
  498. * 8-byte aligned address. So we add alignment pad to start of buffer.
  499. * HTT Metadata should be ensured to be multiple of 8-bytes,
  500. * to get 8-byte aligned start address along with align_pad added
  501. *
  502. * |-----------------------------|
  503. * | |
  504. * |-----------------------------| <-----Buffer Pointer Address given
  505. * | | ^ in HW descriptor (aligned)
  506. * | HTT Metadata | |
  507. * | | |
  508. * | | | Packet Offset given in descriptor
  509. * | | |
  510. * |-----------------------------| |
  511. * | Alignment Pad | v
  512. * |-----------------------------| <----- Actual buffer start address
  513. * | SKB Data | (Unaligned)
  514. * | |
  515. * | |
  516. * | |
  517. * | |
  518. * | |
  519. * |-----------------------------|
  520. */
  521. if (qdf_unlikely((msdu_info->exception_fw)) ||
  522. (vdev->opmode == wlan_op_mode_ocb)) {
  523. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  524. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  525. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  526. "qdf_nbuf_push_head failed\n");
  527. goto failure;
  528. }
  529. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  530. msdu_info->meta_data);
  531. if (htt_hdr_size == 0)
  532. goto failure;
  533. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  534. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  535. is_exception = 1;
  536. }
  537. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  538. qdf_nbuf_map(soc->osdev, nbuf,
  539. QDF_DMA_TO_DEVICE))) {
  540. /* Handle failure */
  541. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  542. "qdf_nbuf_map failed\n");
  543. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  544. goto failure;
  545. }
  546. if (qdf_unlikely(vdev->nawds_enabled)) {
  547. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  548. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  549. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  550. is_exception = 1;
  551. }
  552. }
  553. #if !TQM_BYPASS_WAR
  554. if (is_exception || tx_exc_metadata)
  555. #endif
  556. {
  557. /* Temporary WAR due to TQM VP issues */
  558. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  559. qdf_atomic_inc(&pdev->num_tx_exception);
  560. }
  561. return tx_desc;
  562. failure:
  563. dp_tx_desc_release(tx_desc, desc_pool_id);
  564. return NULL;
  565. }
  566. /**
  567. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  568. * @vdev: DP vdev handle
  569. * @nbuf: skb
  570. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  571. * @desc_pool_id : Descriptor Pool ID
  572. *
  573. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  574. * information. For frames wth fragments, allocate and prepare
  575. * an MSDU extension descriptor
  576. *
  577. * Return: Pointer to Tx Descriptor on success,
  578. * NULL on failure
  579. */
  580. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  581. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  582. uint8_t desc_pool_id)
  583. {
  584. struct dp_tx_desc_s *tx_desc;
  585. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  586. struct dp_pdev *pdev = vdev->pdev;
  587. struct dp_soc *soc = pdev->soc;
  588. /* Allocate software Tx descriptor */
  589. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  590. if (!tx_desc) {
  591. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  592. return NULL;
  593. }
  594. /* Flow control/Congestion Control counters */
  595. qdf_atomic_inc(&pdev->num_tx_outstanding);
  596. /* Initialize the SW tx descriptor */
  597. tx_desc->nbuf = nbuf;
  598. tx_desc->frm_type = msdu_info->frm_type;
  599. tx_desc->tx_encap_type = vdev->tx_encap_type;
  600. tx_desc->vdev = vdev;
  601. tx_desc->pdev = pdev;
  602. tx_desc->pkt_offset = 0;
  603. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  604. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  605. /* Handle scattered frames - TSO/SG/ME */
  606. /* Allocate and prepare an extension descriptor for scattered frames */
  607. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  608. if (!msdu_ext_desc) {
  609. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  610. "%s Tx Extension Descriptor Alloc Fail\n",
  611. __func__);
  612. goto failure;
  613. }
  614. #if TQM_BYPASS_WAR
  615. /* Temporary WAR due to TQM VP issues */
  616. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  617. qdf_atomic_inc(&pdev->num_tx_exception);
  618. #endif
  619. if (qdf_unlikely(msdu_info->exception_fw))
  620. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  621. tx_desc->msdu_ext_desc = msdu_ext_desc;
  622. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  623. return tx_desc;
  624. failure:
  625. dp_tx_desc_release(tx_desc, desc_pool_id);
  626. return NULL;
  627. }
  628. /**
  629. * dp_tx_prepare_raw() - Prepare RAW packet TX
  630. * @vdev: DP vdev handle
  631. * @nbuf: buffer pointer
  632. * @seg_info: Pointer to Segment info Descriptor to be prepared
  633. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  634. * descriptor
  635. *
  636. * Return:
  637. */
  638. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  639. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  640. {
  641. qdf_nbuf_t curr_nbuf = NULL;
  642. uint16_t total_len = 0;
  643. qdf_dma_addr_t paddr;
  644. int32_t i;
  645. int32_t mapped_buf_num = 0;
  646. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  647. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  648. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  649. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  650. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  651. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  652. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  653. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  654. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  655. QDF_DMA_TO_DEVICE)) {
  656. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  657. "%s dma map error \n", __func__);
  658. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  659. mapped_buf_num = i;
  660. goto error;
  661. }
  662. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  663. seg_info->frags[i].paddr_lo = paddr;
  664. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  665. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  666. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  667. total_len += qdf_nbuf_len(curr_nbuf);
  668. }
  669. seg_info->frag_cnt = i;
  670. seg_info->total_len = total_len;
  671. seg_info->next = NULL;
  672. sg_info->curr_seg = seg_info;
  673. msdu_info->frm_type = dp_tx_frm_raw;
  674. msdu_info->num_seg = 1;
  675. return nbuf;
  676. error:
  677. i = 0;
  678. while (nbuf) {
  679. curr_nbuf = nbuf;
  680. if (i < mapped_buf_num) {
  681. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  682. i++;
  683. }
  684. nbuf = qdf_nbuf_next(nbuf);
  685. qdf_nbuf_free(curr_nbuf);
  686. }
  687. return NULL;
  688. }
  689. /**
  690. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  691. * @soc: DP Soc Handle
  692. * @vdev: DP vdev handle
  693. * @tx_desc: Tx Descriptor Handle
  694. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  695. * @fw_metadata: Metadata to send to Target Firmware along with frame
  696. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  697. * @tx_exc_metadata: Handle that holds exception path meta data
  698. *
  699. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  700. * from software Tx descriptor
  701. *
  702. * Return:
  703. */
  704. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  705. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  706. uint16_t fw_metadata, uint8_t ring_id,
  707. struct cdp_tx_exception_metadata
  708. *tx_exc_metadata)
  709. {
  710. uint8_t type;
  711. uint16_t length;
  712. void *hal_tx_desc, *hal_tx_desc_cached;
  713. qdf_dma_addr_t dma_addr;
  714. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  715. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  716. tx_exc_metadata->sec_type : vdev->sec_type);
  717. /* Return Buffer Manager ID */
  718. uint8_t bm_id = ring_id;
  719. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  720. hal_tx_desc_cached = (void *) cached_desc;
  721. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  722. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  723. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  724. type = HAL_TX_BUF_TYPE_EXT_DESC;
  725. dma_addr = tx_desc->msdu_ext_desc->paddr;
  726. } else {
  727. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  728. type = HAL_TX_BUF_TYPE_BUFFER;
  729. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  730. }
  731. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  732. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  733. dma_addr , bm_id, tx_desc->id, type);
  734. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  735. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  736. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  737. hal_tx_desc_set_lmac_id(hal_tx_desc_cached,
  738. HAL_TX_DESC_DEFAULT_LMAC_ID);
  739. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  740. vdev->dscp_tid_map_id);
  741. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  742. sec_type_map[sec_type]);
  743. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  744. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  745. __func__, length, type, (uint64_t)dma_addr,
  746. tx_desc->pkt_offset, tx_desc->id);
  747. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  748. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  749. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  750. vdev->hal_desc_addr_search_flags);
  751. /* verify checksum offload configuration*/
  752. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  753. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  754. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  755. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  756. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  757. }
  758. if (tid != HTT_TX_EXT_TID_INVALID)
  759. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  760. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  761. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  762. /* Sync cached descriptor with HW */
  763. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  764. if (!hal_tx_desc) {
  765. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  766. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  767. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  768. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  769. return QDF_STATUS_E_RESOURCES;
  770. }
  771. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  772. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  773. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  774. /*
  775. * If one packet is enqueued in HW, PM usage count needs to be
  776. * incremented by one to prevent future runtime suspend. This
  777. * should be tied with the success of enqueuing. It will be
  778. * decremented after the packet has been sent.
  779. */
  780. hif_pm_runtime_get_noresume(soc->hif_handle);
  781. return QDF_STATUS_SUCCESS;
  782. }
  783. /**
  784. * dp_cce_classify() - Classify the frame based on CCE rules
  785. * @vdev: DP vdev handle
  786. * @nbuf: skb
  787. *
  788. * Classify frames based on CCE rules
  789. * Return: bool( true if classified,
  790. * else false)
  791. */
  792. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  793. {
  794. struct ether_header *eh = NULL;
  795. uint16_t ether_type;
  796. qdf_llc_t *llcHdr;
  797. qdf_nbuf_t nbuf_clone = NULL;
  798. qdf_dot3_qosframe_t *qos_wh = NULL;
  799. /* for mesh packets don't do any classification */
  800. if (qdf_unlikely(vdev->mesh_vdev))
  801. return false;
  802. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  803. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  804. ether_type = eh->ether_type;
  805. llcHdr = (qdf_llc_t *)(nbuf->data +
  806. sizeof(struct ether_header));
  807. } else {
  808. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  809. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  810. if (qdf_unlikely(
  811. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  812. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  813. ether_type = *(uint16_t *)(nbuf->data
  814. + QDF_IEEE80211_4ADDR_HDR_LEN
  815. + sizeof(qdf_llc_t)
  816. - sizeof(ether_type));
  817. llcHdr = (qdf_llc_t *)(nbuf->data +
  818. QDF_IEEE80211_4ADDR_HDR_LEN);
  819. } else {
  820. ether_type = *(uint16_t *)(nbuf->data
  821. + QDF_IEEE80211_3ADDR_HDR_LEN
  822. + sizeof(qdf_llc_t)
  823. - sizeof(ether_type));
  824. llcHdr = (qdf_llc_t *)(nbuf->data +
  825. QDF_IEEE80211_3ADDR_HDR_LEN);
  826. }
  827. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  828. && (ether_type ==
  829. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  830. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  831. return true;
  832. }
  833. }
  834. return false;
  835. }
  836. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  837. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  838. sizeof(*llcHdr));
  839. nbuf_clone = qdf_nbuf_clone(nbuf);
  840. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  841. if (ether_type == htons(ETHERTYPE_8021Q)) {
  842. qdf_nbuf_pull_head(nbuf_clone,
  843. sizeof(qdf_net_vlanhdr_t));
  844. }
  845. } else {
  846. if (ether_type == htons(ETHERTYPE_8021Q)) {
  847. nbuf_clone = qdf_nbuf_clone(nbuf);
  848. qdf_nbuf_pull_head(nbuf_clone,
  849. sizeof(qdf_net_vlanhdr_t));
  850. }
  851. }
  852. if (qdf_unlikely(nbuf_clone))
  853. nbuf = nbuf_clone;
  854. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  855. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  856. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  857. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  858. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  859. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  860. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  861. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  862. if (qdf_unlikely(nbuf_clone != NULL))
  863. qdf_nbuf_free(nbuf_clone);
  864. return true;
  865. }
  866. if (qdf_unlikely(nbuf_clone != NULL))
  867. qdf_nbuf_free(nbuf_clone);
  868. return false;
  869. }
  870. /**
  871. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  872. * @vdev: DP vdev handle
  873. * @nbuf: skb
  874. *
  875. * Extract the DSCP or PCP information from frame and map into TID value.
  876. * Software based TID classification is required when more than 2 DSCP-TID
  877. * mapping tables are needed.
  878. * Hardware supports 2 DSCP-TID mapping tables
  879. *
  880. * Return: void
  881. */
  882. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  883. struct dp_tx_msdu_info_s *msdu_info)
  884. {
  885. uint8_t tos = 0, dscp_tid_override = 0;
  886. uint8_t *hdr_ptr, *L3datap;
  887. uint8_t is_mcast = 0;
  888. struct ether_header *eh = NULL;
  889. qdf_ethervlan_header_t *evh = NULL;
  890. uint16_t ether_type;
  891. qdf_llc_t *llcHdr;
  892. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  893. /* for mesh packets don't do any classification */
  894. if (qdf_unlikely(vdev->mesh_vdev))
  895. return;
  896. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  897. eh = (struct ether_header *) nbuf->data;
  898. hdr_ptr = eh->ether_dhost;
  899. L3datap = hdr_ptr + sizeof(struct ether_header);
  900. } else {
  901. qdf_dot3_qosframe_t *qos_wh =
  902. (qdf_dot3_qosframe_t *) nbuf->data;
  903. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  904. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  905. return;
  906. }
  907. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  908. ether_type = eh->ether_type;
  909. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  910. /*
  911. * Check if packet is dot3 or eth2 type.
  912. */
  913. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  914. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  915. sizeof(*llcHdr));
  916. if (ether_type == htons(ETHERTYPE_8021Q)) {
  917. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  918. sizeof(*llcHdr);
  919. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  920. + sizeof(*llcHdr) +
  921. sizeof(qdf_net_vlanhdr_t));
  922. } else {
  923. L3datap = hdr_ptr + sizeof(struct ether_header) +
  924. sizeof(*llcHdr);
  925. }
  926. } else {
  927. if (ether_type == htons(ETHERTYPE_8021Q)) {
  928. evh = (qdf_ethervlan_header_t *) eh;
  929. ether_type = evh->ether_type;
  930. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  931. }
  932. }
  933. /*
  934. * Find priority from IP TOS DSCP field
  935. */
  936. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  937. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  938. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  939. /* Only for unicast frames */
  940. if (!is_mcast) {
  941. /* send it on VO queue */
  942. msdu_info->tid = DP_VO_TID;
  943. }
  944. } else {
  945. /*
  946. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  947. * from TOS byte.
  948. */
  949. tos = ip->ip_tos;
  950. dscp_tid_override = 1;
  951. }
  952. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  953. /* TODO
  954. * use flowlabel
  955. *igmpmld cases to be handled in phase 2
  956. */
  957. unsigned long ver_pri_flowlabel;
  958. unsigned long pri;
  959. ver_pri_flowlabel = *(unsigned long *) L3datap;
  960. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  961. DP_IPV6_PRIORITY_SHIFT;
  962. tos = pri;
  963. dscp_tid_override = 1;
  964. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  965. msdu_info->tid = DP_VO_TID;
  966. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  967. /* Only for unicast frames */
  968. if (!is_mcast) {
  969. /* send ucast arp on VO queue */
  970. msdu_info->tid = DP_VO_TID;
  971. }
  972. }
  973. /*
  974. * Assign all MCAST packets to BE
  975. */
  976. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  977. if (is_mcast) {
  978. tos = 0;
  979. dscp_tid_override = 1;
  980. }
  981. }
  982. if (dscp_tid_override == 1) {
  983. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  984. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  985. }
  986. return;
  987. }
  988. #ifdef CONVERGED_TDLS_ENABLE
  989. /**
  990. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  991. * @tx_desc: TX descriptor
  992. *
  993. * Return: None
  994. */
  995. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  996. {
  997. if (tx_desc->vdev) {
  998. if (tx_desc->vdev->is_tdls_frame)
  999. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1000. tx_desc->vdev->is_tdls_frame = false;
  1001. }
  1002. }
  1003. /**
  1004. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1005. * @tx_desc: TX descriptor
  1006. * @vdev: datapath vdev handle
  1007. *
  1008. * Return: None
  1009. */
  1010. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1011. struct dp_vdev *vdev)
  1012. {
  1013. struct hal_tx_completion_status ts = {0};
  1014. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1015. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1016. if (vdev->tx_non_std_data_callback.func) {
  1017. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1018. vdev->tx_non_std_data_callback.func(
  1019. vdev->tx_non_std_data_callback.ctxt,
  1020. nbuf, ts.status);
  1021. return;
  1022. }
  1023. }
  1024. #endif
  1025. /**
  1026. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1027. * @vdev: DP vdev handle
  1028. * @nbuf: skb
  1029. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1030. * @meta_data: Metadata to the fw
  1031. * @tx_q: Tx queue to be used for this Tx frame
  1032. * @peer_id: peer_id of the peer in case of NAWDS frames
  1033. * @tx_exc_metadata: Handle that holds exception path metadata
  1034. *
  1035. * Return: NULL on success,
  1036. * nbuf when it fails to send
  1037. */
  1038. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1039. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1040. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1041. {
  1042. struct dp_pdev *pdev = vdev->pdev;
  1043. struct dp_soc *soc = pdev->soc;
  1044. struct dp_tx_desc_s *tx_desc;
  1045. QDF_STATUS status;
  1046. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1047. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1048. uint16_t htt_tcl_metadata = 0;
  1049. uint8_t tid = msdu_info->tid;
  1050. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  1051. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1052. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1053. msdu_info, tx_exc_metadata);
  1054. if (!tx_desc) {
  1055. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1056. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  1057. __func__, vdev, tx_q->desc_pool_id);
  1058. return nbuf;
  1059. }
  1060. if (qdf_unlikely(soc->cce_disable)) {
  1061. if (dp_cce_classify(vdev, nbuf) == true) {
  1062. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1063. tid = DP_VO_TID;
  1064. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1065. }
  1066. }
  1067. dp_tx_update_tdls_flags(tx_desc);
  1068. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1069. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1070. "%s %d : HAL RING Access Failed -- %pK\n",
  1071. __func__, __LINE__, hal_srng);
  1072. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1073. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1074. goto fail_return;
  1075. }
  1076. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1077. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1078. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1079. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1080. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1081. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1082. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1083. peer_id);
  1084. } else
  1085. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1086. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1087. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1088. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1089. if (status != QDF_STATUS_SUCCESS) {
  1090. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1091. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1092. __func__, tx_desc, tx_q->ring_id);
  1093. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1094. goto fail_return;
  1095. }
  1096. nbuf = NULL;
  1097. fail_return:
  1098. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1099. hal_srng_access_end(soc->hal_soc, hal_srng);
  1100. hif_pm_runtime_put(soc->hif_handle);
  1101. } else {
  1102. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1103. }
  1104. return nbuf;
  1105. }
  1106. /**
  1107. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1108. * @vdev: DP vdev handle
  1109. * @nbuf: skb
  1110. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1111. *
  1112. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1113. *
  1114. * Return: NULL on success,
  1115. * nbuf when it fails to send
  1116. */
  1117. #if QDF_LOCK_STATS
  1118. static noinline
  1119. #else
  1120. static
  1121. #endif
  1122. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1123. struct dp_tx_msdu_info_s *msdu_info)
  1124. {
  1125. uint8_t i;
  1126. struct dp_pdev *pdev = vdev->pdev;
  1127. struct dp_soc *soc = pdev->soc;
  1128. struct dp_tx_desc_s *tx_desc;
  1129. bool is_cce_classified = false;
  1130. QDF_STATUS status;
  1131. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1132. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1133. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1134. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1135. "%s %d : HAL RING Access Failed -- %pK\n",
  1136. __func__, __LINE__, hal_srng);
  1137. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1138. return nbuf;
  1139. }
  1140. if (qdf_unlikely(soc->cce_disable)) {
  1141. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1142. if (is_cce_classified) {
  1143. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1144. msdu_info->tid = DP_VO_TID;
  1145. }
  1146. }
  1147. if (msdu_info->frm_type == dp_tx_frm_me)
  1148. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1149. i = 0;
  1150. /* Print statement to track i and num_seg */
  1151. /*
  1152. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1153. * descriptors using information in msdu_info
  1154. */
  1155. while (i < msdu_info->num_seg) {
  1156. /*
  1157. * Setup Tx descriptor for an MSDU, and MSDU extension
  1158. * descriptor
  1159. */
  1160. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1161. tx_q->desc_pool_id);
  1162. if (!tx_desc) {
  1163. if (msdu_info->frm_type == dp_tx_frm_me) {
  1164. dp_tx_me_free_buf(pdev,
  1165. (void *)(msdu_info->u.sg_info
  1166. .curr_seg->frags[0].vaddr));
  1167. }
  1168. goto done;
  1169. }
  1170. if (msdu_info->frm_type == dp_tx_frm_me) {
  1171. tx_desc->me_buffer =
  1172. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1173. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1174. }
  1175. if (is_cce_classified)
  1176. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1177. /*
  1178. * Enqueue the Tx MSDU descriptor to HW for transmit
  1179. */
  1180. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1181. vdev->htt_tcl_metadata, tx_q->ring_id, NULL);
  1182. if (status != QDF_STATUS_SUCCESS) {
  1183. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1184. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1185. __func__, tx_desc, tx_q->ring_id);
  1186. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1187. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1188. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1189. goto done;
  1190. }
  1191. /*
  1192. * TODO
  1193. * if tso_info structure can be modified to have curr_seg
  1194. * as first element, following 2 blocks of code (for TSO and SG)
  1195. * can be combined into 1
  1196. */
  1197. /*
  1198. * For frames with multiple segments (TSO, ME), jump to next
  1199. * segment.
  1200. */
  1201. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1202. if (msdu_info->u.tso_info.curr_seg->next) {
  1203. msdu_info->u.tso_info.curr_seg =
  1204. msdu_info->u.tso_info.curr_seg->next;
  1205. /*
  1206. * If this is a jumbo nbuf, then increment the number of
  1207. * nbuf users for each additional segment of the msdu.
  1208. * This will ensure that the skb is freed only after
  1209. * receiving tx completion for all segments of an nbuf
  1210. */
  1211. qdf_nbuf_inc_users(nbuf);
  1212. /* Check with MCL if this is needed */
  1213. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1214. }
  1215. }
  1216. /*
  1217. * For Multicast-Unicast converted packets,
  1218. * each converted frame (for a client) is represented as
  1219. * 1 segment
  1220. */
  1221. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1222. (msdu_info->frm_type == dp_tx_frm_me)) {
  1223. if (msdu_info->u.sg_info.curr_seg->next) {
  1224. msdu_info->u.sg_info.curr_seg =
  1225. msdu_info->u.sg_info.curr_seg->next;
  1226. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1227. }
  1228. }
  1229. i++;
  1230. }
  1231. nbuf = NULL;
  1232. done:
  1233. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1234. hal_srng_access_end(soc->hal_soc, hal_srng);
  1235. hif_pm_runtime_put(soc->hif_handle);
  1236. } else {
  1237. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1238. }
  1239. return nbuf;
  1240. }
  1241. /**
  1242. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1243. * for SG frames
  1244. * @vdev: DP vdev handle
  1245. * @nbuf: skb
  1246. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1247. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1248. *
  1249. * Return: NULL on success,
  1250. * nbuf when it fails to send
  1251. */
  1252. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1253. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1254. {
  1255. uint32_t cur_frag, nr_frags;
  1256. qdf_dma_addr_t paddr;
  1257. struct dp_tx_sg_info_s *sg_info;
  1258. sg_info = &msdu_info->u.sg_info;
  1259. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1260. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1261. QDF_DMA_TO_DEVICE)) {
  1262. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1263. "dma map error\n");
  1264. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1265. qdf_nbuf_free(nbuf);
  1266. return NULL;
  1267. }
  1268. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1269. seg_info->frags[0].paddr_lo = paddr;
  1270. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1271. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1272. seg_info->frags[0].vaddr = (void *) nbuf;
  1273. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1274. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1275. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1276. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1277. "frag dma map error\n");
  1278. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1279. qdf_nbuf_free(nbuf);
  1280. return NULL;
  1281. }
  1282. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1283. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1284. seg_info->frags[cur_frag + 1].paddr_hi =
  1285. ((uint64_t) paddr) >> 32;
  1286. seg_info->frags[cur_frag + 1].len =
  1287. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1288. }
  1289. seg_info->frag_cnt = (cur_frag + 1);
  1290. seg_info->total_len = qdf_nbuf_len(nbuf);
  1291. seg_info->next = NULL;
  1292. sg_info->curr_seg = seg_info;
  1293. msdu_info->frm_type = dp_tx_frm_sg;
  1294. msdu_info->num_seg = 1;
  1295. return nbuf;
  1296. }
  1297. #ifdef MESH_MODE_SUPPORT
  1298. /**
  1299. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1300. and prepare msdu_info for mesh frames.
  1301. * @vdev: DP vdev handle
  1302. * @nbuf: skb
  1303. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1304. *
  1305. * Return: NULL on failure,
  1306. * nbuf when extracted successfully
  1307. */
  1308. static
  1309. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1310. struct dp_tx_msdu_info_s *msdu_info)
  1311. {
  1312. struct meta_hdr_s *mhdr;
  1313. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1314. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1315. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1316. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1317. msdu_info->exception_fw = 0;
  1318. goto remove_meta_hdr;
  1319. }
  1320. msdu_info->exception_fw = 1;
  1321. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1322. meta_data->host_tx_desc_pool = 1;
  1323. meta_data->update_peer_cache = 1;
  1324. meta_data->learning_frame = 1;
  1325. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1326. meta_data->power = mhdr->power;
  1327. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1328. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1329. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1330. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1331. meta_data->dyn_bw = 1;
  1332. meta_data->valid_pwr = 1;
  1333. meta_data->valid_mcs_mask = 1;
  1334. meta_data->valid_nss_mask = 1;
  1335. meta_data->valid_preamble_type = 1;
  1336. meta_data->valid_retries = 1;
  1337. meta_data->valid_bw_info = 1;
  1338. }
  1339. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1340. meta_data->encrypt_type = 0;
  1341. meta_data->valid_encrypt_type = 1;
  1342. meta_data->learning_frame = 0;
  1343. }
  1344. meta_data->valid_key_flags = 1;
  1345. meta_data->key_flags = (mhdr->keyix & 0x3);
  1346. remove_meta_hdr:
  1347. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1348. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1349. "qdf_nbuf_pull_head failed\n");
  1350. qdf_nbuf_free(nbuf);
  1351. return NULL;
  1352. }
  1353. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1354. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1355. else
  1356. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1357. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1358. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1359. " tid %d to_fw %d\n",
  1360. __func__, msdu_info->meta_data[0],
  1361. msdu_info->meta_data[1],
  1362. msdu_info->meta_data[2],
  1363. msdu_info->meta_data[3],
  1364. msdu_info->meta_data[4],
  1365. msdu_info->meta_data[5],
  1366. msdu_info->tid, msdu_info->exception_fw);
  1367. return nbuf;
  1368. }
  1369. #else
  1370. static
  1371. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1372. struct dp_tx_msdu_info_s *msdu_info)
  1373. {
  1374. return nbuf;
  1375. }
  1376. #endif
  1377. #ifdef DP_FEATURE_NAWDS_TX
  1378. /**
  1379. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1380. * @vdev: dp_vdev handle
  1381. * @nbuf: skb
  1382. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1383. * @tx_q: Tx queue to be used for this Tx frame
  1384. * @meta_data: Meta date for mesh
  1385. * @peer_id: peer_id of the peer in case of NAWDS frames
  1386. *
  1387. * return: NULL on success nbuf on failure
  1388. */
  1389. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1390. struct dp_tx_msdu_info_s *msdu_info)
  1391. {
  1392. struct dp_peer *peer = NULL;
  1393. struct dp_soc *soc = vdev->pdev->soc;
  1394. struct dp_ast_entry *ast_entry = NULL;
  1395. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1396. uint16_t peer_id = HTT_INVALID_PEER;
  1397. struct dp_peer *sa_peer = NULL;
  1398. qdf_nbuf_t nbuf_copy;
  1399. qdf_spin_lock_bh(&(soc->ast_lock));
  1400. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1401. if (ast_entry)
  1402. sa_peer = ast_entry->peer;
  1403. qdf_spin_unlock_bh(&(soc->ast_lock));
  1404. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1405. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1406. (peer->nawds_enabled)) {
  1407. if (sa_peer == peer) {
  1408. QDF_TRACE(QDF_MODULE_ID_DP,
  1409. QDF_TRACE_LEVEL_DEBUG,
  1410. " %s: broadcast multicast packet",
  1411. __func__);
  1412. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1413. continue;
  1414. }
  1415. nbuf_copy = qdf_nbuf_copy(nbuf);
  1416. if (!nbuf_copy) {
  1417. QDF_TRACE(QDF_MODULE_ID_DP,
  1418. QDF_TRACE_LEVEL_ERROR,
  1419. "nbuf copy failed");
  1420. }
  1421. peer_id = peer->peer_ids[0];
  1422. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1423. msdu_info, peer_id, NULL);
  1424. if (nbuf_copy != NULL) {
  1425. qdf_nbuf_free(nbuf_copy);
  1426. continue;
  1427. }
  1428. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1429. 1, qdf_nbuf_len(nbuf));
  1430. }
  1431. }
  1432. if (peer_id == HTT_INVALID_PEER)
  1433. return nbuf;
  1434. return NULL;
  1435. }
  1436. #endif
  1437. /**
  1438. * dp_check_exc_metadata() - Checks if parameters are valid
  1439. * @tx_exc - holds all exception path parameters
  1440. *
  1441. * Returns true when all the parameters are valid else false
  1442. *
  1443. */
  1444. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1445. {
  1446. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1447. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1448. tx_exc->sec_type > cdp_num_sec_types) {
  1449. return false;
  1450. }
  1451. return true;
  1452. }
  1453. /**
  1454. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1455. * @vap_dev: DP vdev handle
  1456. * @nbuf: skb
  1457. * @tx_exc_metadata: Handle that holds exception path meta data
  1458. *
  1459. * Entry point for Core Tx layer (DP_TX) invoked from
  1460. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1461. *
  1462. * Return: NULL on success,
  1463. * nbuf when it fails to send
  1464. */
  1465. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1466. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1467. {
  1468. struct ether_header *eh = NULL;
  1469. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1470. struct dp_tx_msdu_info_s msdu_info;
  1471. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1472. msdu_info.tid = tx_exc_metadata->tid;
  1473. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1474. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1475. "%s , skb %pM",
  1476. __func__, nbuf->data);
  1477. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1478. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1479. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1480. "Invalid parameters in exception path");
  1481. goto fail;
  1482. }
  1483. /* Basic sanity checks for unsupported packets */
  1484. /* MESH mode */
  1485. if (qdf_unlikely(vdev->mesh_vdev)) {
  1486. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1487. "Mesh mode is not supported in exception path");
  1488. goto fail;
  1489. }
  1490. /* TSO or SG */
  1491. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1492. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1493. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1494. "TSO and SG are not supported in exception path");
  1495. goto fail;
  1496. }
  1497. /* RAW */
  1498. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1499. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1500. "Raw frame is not supported in exception path");
  1501. goto fail;
  1502. }
  1503. /* Mcast enhancement*/
  1504. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1505. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1506. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1507. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW\n");
  1508. }
  1509. }
  1510. /*
  1511. * Get HW Queue to use for this frame.
  1512. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1513. * dedicated for data and 1 for command.
  1514. * "queue_id" maps to one hardware ring.
  1515. * With each ring, we also associate a unique Tx descriptor pool
  1516. * to minimize lock contention for these resources.
  1517. */
  1518. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1519. /* Reset the control block */
  1520. qdf_nbuf_reset_ctxt(nbuf);
  1521. /* Single linear frame */
  1522. /*
  1523. * If nbuf is a simple linear frame, use send_single function to
  1524. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1525. * SRNG. There is no need to setup a MSDU extension descriptor.
  1526. */
  1527. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1528. tx_exc_metadata->peer_id, tx_exc_metadata);
  1529. return nbuf;
  1530. fail:
  1531. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1532. "pkt send failed");
  1533. return nbuf;
  1534. }
  1535. /**
  1536. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1537. * @vap_dev: DP vdev handle
  1538. * @nbuf: skb
  1539. *
  1540. * Entry point for Core Tx layer (DP_TX) invoked from
  1541. * hard_start_xmit in OSIF/HDD
  1542. *
  1543. * Return: NULL on success,
  1544. * nbuf when it fails to send
  1545. */
  1546. #ifdef MESH_MODE_SUPPORT
  1547. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1548. {
  1549. struct meta_hdr_s *mhdr;
  1550. qdf_nbuf_t nbuf_mesh = NULL;
  1551. qdf_nbuf_t nbuf_clone = NULL;
  1552. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1553. uint8_t no_enc_frame = 0;
  1554. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1555. if (nbuf_mesh == NULL) {
  1556. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1557. "qdf_nbuf_unshare failed\n");
  1558. return nbuf;
  1559. }
  1560. nbuf = nbuf_mesh;
  1561. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1562. if ((vdev->sec_type != cdp_sec_type_none) &&
  1563. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1564. no_enc_frame = 1;
  1565. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1566. !no_enc_frame) {
  1567. nbuf_clone = qdf_nbuf_clone(nbuf);
  1568. if (nbuf_clone == NULL) {
  1569. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1570. "qdf_nbuf_clone failed\n");
  1571. return nbuf;
  1572. }
  1573. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1574. }
  1575. if (nbuf_clone) {
  1576. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1577. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1578. } else
  1579. qdf_nbuf_free(nbuf_clone);
  1580. }
  1581. if (no_enc_frame)
  1582. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1583. else
  1584. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1585. nbuf = dp_tx_send(vap_dev, nbuf);
  1586. if ((nbuf == NULL) && no_enc_frame) {
  1587. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1588. }
  1589. return nbuf;
  1590. }
  1591. #else
  1592. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1593. {
  1594. return dp_tx_send(vap_dev, nbuf);
  1595. }
  1596. #endif
  1597. /**
  1598. * dp_tx_send() - Transmit a frame on a given VAP
  1599. * @vap_dev: DP vdev handle
  1600. * @nbuf: skb
  1601. *
  1602. * Entry point for Core Tx layer (DP_TX) invoked from
  1603. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1604. * cases
  1605. *
  1606. * Return: NULL on success,
  1607. * nbuf when it fails to send
  1608. */
  1609. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1610. {
  1611. struct ether_header *eh = NULL;
  1612. struct dp_tx_msdu_info_s msdu_info;
  1613. struct dp_tx_seg_info_s seg_info;
  1614. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1615. uint16_t peer_id = HTT_INVALID_PEER;
  1616. qdf_nbuf_t nbuf_mesh = NULL;
  1617. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1618. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1619. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1620. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1621. "%s , skb %pM",
  1622. __func__, nbuf->data);
  1623. /*
  1624. * Set Default Host TID value to invalid TID
  1625. * (TID override disabled)
  1626. */
  1627. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1628. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1629. if (qdf_unlikely(vdev->mesh_vdev)) {
  1630. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1631. &msdu_info);
  1632. if (nbuf_mesh == NULL) {
  1633. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1634. "Extracting mesh metadata failed\n");
  1635. return nbuf;
  1636. }
  1637. nbuf = nbuf_mesh;
  1638. }
  1639. /*
  1640. * Get HW Queue to use for this frame.
  1641. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1642. * dedicated for data and 1 for command.
  1643. * "queue_id" maps to one hardware ring.
  1644. * With each ring, we also associate a unique Tx descriptor pool
  1645. * to minimize lock contention for these resources.
  1646. */
  1647. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1648. /*
  1649. * TCL H/W supports 2 DSCP-TID mapping tables.
  1650. * Table 1 - Default DSCP-TID mapping table
  1651. * Table 2 - 1 DSCP-TID override table
  1652. *
  1653. * If we need a different DSCP-TID mapping for this vap,
  1654. * call tid_classify to extract DSCP/ToS from frame and
  1655. * map to a TID and store in msdu_info. This is later used
  1656. * to fill in TCL Input descriptor (per-packet TID override).
  1657. */
  1658. if (vdev->dscp_tid_map_id > 1)
  1659. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1660. /* Reset the control block */
  1661. qdf_nbuf_reset_ctxt(nbuf);
  1662. /*
  1663. * Classify the frame and call corresponding
  1664. * "prepare" function which extracts the segment (TSO)
  1665. * and fragmentation information (for TSO , SG, ME, or Raw)
  1666. * into MSDU_INFO structure which is later used to fill
  1667. * SW and HW descriptors.
  1668. */
  1669. if (qdf_nbuf_is_tso(nbuf)) {
  1670. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1671. "%s TSO frame %pK\n", __func__, vdev);
  1672. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1673. qdf_nbuf_len(nbuf));
  1674. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1675. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1676. return nbuf;
  1677. }
  1678. goto send_multiple;
  1679. }
  1680. /* SG */
  1681. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1682. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1683. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1684. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1685. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1686. qdf_nbuf_len(nbuf));
  1687. goto send_multiple;
  1688. }
  1689. #ifdef ATH_SUPPORT_IQUE
  1690. /* Mcast to Ucast Conversion*/
  1691. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1692. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1693. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1694. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1695. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1696. DP_STATS_INC_PKT(vdev,
  1697. tx_i.mcast_en.mcast_pkt, 1,
  1698. qdf_nbuf_len(nbuf));
  1699. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1700. QDF_STATUS_SUCCESS) {
  1701. return NULL;
  1702. }
  1703. }
  1704. }
  1705. #endif
  1706. /* RAW */
  1707. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1708. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1709. if (nbuf == NULL)
  1710. return NULL;
  1711. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1712. "%s Raw frame %pK\n", __func__, vdev);
  1713. goto send_multiple;
  1714. }
  1715. /* Single linear frame */
  1716. /*
  1717. * If nbuf is a simple linear frame, use send_single function to
  1718. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1719. * SRNG. There is no need to setup a MSDU extension descriptor.
  1720. */
  1721. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1722. return nbuf;
  1723. send_multiple:
  1724. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1725. return nbuf;
  1726. }
  1727. /**
  1728. * dp_tx_reinject_handler() - Tx Reinject Handler
  1729. * @tx_desc: software descriptor head pointer
  1730. * @status : Tx completion status from HTT descriptor
  1731. *
  1732. * This function reinjects frames back to Target.
  1733. * Todo - Host queue needs to be added
  1734. *
  1735. * Return: none
  1736. */
  1737. static
  1738. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1739. {
  1740. struct dp_vdev *vdev;
  1741. struct dp_peer *peer = NULL;
  1742. uint32_t peer_id = HTT_INVALID_PEER;
  1743. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1744. qdf_nbuf_t nbuf_copy = NULL;
  1745. struct dp_tx_msdu_info_s msdu_info;
  1746. struct dp_peer *sa_peer = NULL;
  1747. struct dp_ast_entry *ast_entry = NULL;
  1748. struct dp_soc *soc = NULL;
  1749. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1750. #ifdef WDS_VENDOR_EXTENSION
  1751. int is_mcast = 0, is_ucast = 0;
  1752. int num_peers_3addr = 0;
  1753. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1754. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1755. #endif
  1756. vdev = tx_desc->vdev;
  1757. soc = vdev->pdev->soc;
  1758. qdf_assert(vdev);
  1759. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1760. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1761. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1762. "%s Tx reinject path\n", __func__);
  1763. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1764. qdf_nbuf_len(tx_desc->nbuf));
  1765. qdf_spin_lock_bh(&(soc->ast_lock));
  1766. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1767. if (ast_entry)
  1768. sa_peer = ast_entry->peer;
  1769. qdf_spin_unlock_bh(&(soc->ast_lock));
  1770. #ifdef WDS_VENDOR_EXTENSION
  1771. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1772. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1773. } else {
  1774. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1775. }
  1776. is_ucast = !is_mcast;
  1777. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1778. if (peer->bss_peer)
  1779. continue;
  1780. /* Detect wds peers that use 3-addr framing for mcast.
  1781. * if there are any, the bss_peer is used to send the
  1782. * the mcast frame using 3-addr format. all wds enabled
  1783. * peers that use 4-addr framing for mcast frames will
  1784. * be duplicated and sent as 4-addr frames below.
  1785. */
  1786. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1787. num_peers_3addr = 1;
  1788. break;
  1789. }
  1790. }
  1791. #endif
  1792. if (qdf_unlikely(vdev->mesh_vdev)) {
  1793. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1794. } else {
  1795. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1796. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1797. #ifdef WDS_VENDOR_EXTENSION
  1798. /*
  1799. * . if 3-addr STA, then send on BSS Peer
  1800. * . if Peer WDS enabled and accept 4-addr mcast,
  1801. * send mcast on that peer only
  1802. * . if Peer WDS enabled and accept 4-addr ucast,
  1803. * send ucast on that peer only
  1804. */
  1805. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1806. (peer->wds_enabled &&
  1807. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1808. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1809. #else
  1810. ((peer->bss_peer &&
  1811. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1812. peer->nawds_enabled)) {
  1813. #endif
  1814. peer_id = DP_INVALID_PEER;
  1815. if (peer->nawds_enabled) {
  1816. peer_id = peer->peer_ids[0];
  1817. if (sa_peer == peer) {
  1818. QDF_TRACE(
  1819. QDF_MODULE_ID_DP,
  1820. QDF_TRACE_LEVEL_DEBUG,
  1821. " %s: multicast packet",
  1822. __func__);
  1823. DP_STATS_INC(peer,
  1824. tx.nawds_mcast_drop, 1);
  1825. continue;
  1826. }
  1827. }
  1828. nbuf_copy = qdf_nbuf_copy(nbuf);
  1829. if (!nbuf_copy) {
  1830. QDF_TRACE(QDF_MODULE_ID_DP,
  1831. QDF_TRACE_LEVEL_DEBUG,
  1832. FL("nbuf copy failed"));
  1833. break;
  1834. }
  1835. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1836. nbuf_copy,
  1837. &msdu_info,
  1838. peer_id,
  1839. NULL);
  1840. if (nbuf_copy) {
  1841. QDF_TRACE(QDF_MODULE_ID_DP,
  1842. QDF_TRACE_LEVEL_DEBUG,
  1843. FL("pkt send failed"));
  1844. qdf_nbuf_free(nbuf_copy);
  1845. } else {
  1846. if (peer_id != DP_INVALID_PEER)
  1847. DP_STATS_INC_PKT(peer,
  1848. tx.nawds_mcast,
  1849. 1, qdf_nbuf_len(nbuf));
  1850. }
  1851. }
  1852. }
  1853. }
  1854. if (vdev->nawds_enabled) {
  1855. peer_id = DP_INVALID_PEER;
  1856. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1857. 1, qdf_nbuf_len(nbuf));
  1858. nbuf = dp_tx_send_msdu_single(vdev,
  1859. nbuf,
  1860. &msdu_info,
  1861. peer_id, NULL);
  1862. if (nbuf) {
  1863. QDF_TRACE(QDF_MODULE_ID_DP,
  1864. QDF_TRACE_LEVEL_DEBUG,
  1865. FL("pkt send failed"));
  1866. qdf_nbuf_free(nbuf);
  1867. }
  1868. } else
  1869. qdf_nbuf_free(nbuf);
  1870. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1871. }
  1872. /**
  1873. * dp_tx_inspect_handler() - Tx Inspect Handler
  1874. * @tx_desc: software descriptor head pointer
  1875. * @status : Tx completion status from HTT descriptor
  1876. *
  1877. * Handles Tx frames sent back to Host for inspection
  1878. * (ProxyARP)
  1879. *
  1880. * Return: none
  1881. */
  1882. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1883. {
  1884. struct dp_soc *soc;
  1885. struct dp_pdev *pdev = tx_desc->pdev;
  1886. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1887. "%s Tx inspect path\n",
  1888. __func__);
  1889. qdf_assert(pdev);
  1890. soc = pdev->soc;
  1891. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1892. qdf_nbuf_len(tx_desc->nbuf));
  1893. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1894. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1895. }
  1896. #ifdef FEATURE_PERPKT_INFO
  1897. /**
  1898. * dp_get_completion_indication_for_stack() - send completion to stack
  1899. * @soc : dp_soc handle
  1900. * @pdev: dp_pdev handle
  1901. * @peer_id: peer_id of the peer for which completion came
  1902. * @ppdu_id: ppdu_id
  1903. * @first_msdu: first msdu
  1904. * @last_msdu: last msdu
  1905. * @netbuf: Buffer pointer for free
  1906. *
  1907. * This function is used for indication whether buffer needs to be
  1908. * send to stack for free or not
  1909. */
  1910. QDF_STATUS
  1911. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1912. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1913. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1914. {
  1915. struct tx_capture_hdr *ppdu_hdr;
  1916. struct dp_peer *peer = NULL;
  1917. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1918. return QDF_STATUS_E_NOSUPPORT;
  1919. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1920. dp_peer_find_by_id(soc, peer_id);
  1921. if (!peer) {
  1922. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1923. FL("Peer Invalid"));
  1924. return QDF_STATUS_E_INVAL;
  1925. }
  1926. if (pdev->mcopy_mode) {
  1927. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  1928. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  1929. return QDF_STATUS_E_INVAL;
  1930. }
  1931. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  1932. pdev->m_copy_id.tx_peer_id = peer_id;
  1933. }
  1934. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1935. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1936. FL("No headroom"));
  1937. return QDF_STATUS_E_NOMEM;
  1938. }
  1939. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1940. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  1941. IEEE80211_ADDR_LEN);
  1942. ppdu_hdr->ppdu_id = ppdu_id;
  1943. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1944. IEEE80211_ADDR_LEN);
  1945. ppdu_hdr->peer_id = peer_id;
  1946. ppdu_hdr->first_msdu = first_msdu;
  1947. ppdu_hdr->last_msdu = last_msdu;
  1948. return QDF_STATUS_SUCCESS;
  1949. }
  1950. /**
  1951. * dp_send_completion_to_stack() - send completion to stack
  1952. * @soc : dp_soc handle
  1953. * @pdev: dp_pdev handle
  1954. * @peer_id: peer_id of the peer for which completion came
  1955. * @ppdu_id: ppdu_id
  1956. * @netbuf: Buffer pointer for free
  1957. *
  1958. * This function is used to send completion to stack
  1959. * to free buffer
  1960. */
  1961. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1962. uint16_t peer_id, uint32_t ppdu_id,
  1963. qdf_nbuf_t netbuf)
  1964. {
  1965. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  1966. netbuf, peer_id,
  1967. WDI_NO_VAL, pdev->pdev_id);
  1968. }
  1969. #else
  1970. static QDF_STATUS
  1971. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1972. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1973. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1974. {
  1975. return QDF_STATUS_E_NOSUPPORT;
  1976. }
  1977. static void
  1978. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1979. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1980. {
  1981. }
  1982. #endif
  1983. /**
  1984. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1985. * @soc: Soc handle
  1986. * @desc: software Tx descriptor to be processed
  1987. *
  1988. * Return: none
  1989. */
  1990. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1991. struct dp_tx_desc_s *desc)
  1992. {
  1993. struct dp_vdev *vdev = desc->vdev;
  1994. qdf_nbuf_t nbuf = desc->nbuf;
  1995. /* If it is TDLS mgmt, don't unmap or free the frame */
  1996. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1997. return dp_non_std_tx_comp_free_buff(desc, vdev);
  1998. /* 0 : MSDU buffer, 1 : MLE */
  1999. if (desc->msdu_ext_desc) {
  2000. /* TSO free */
  2001. if (hal_tx_ext_desc_get_tso_enable(
  2002. desc->msdu_ext_desc->vaddr)) {
  2003. /* If remaining number of segment is 0
  2004. * actual TSO may unmap and free */
  2005. if (qdf_nbuf_get_users(nbuf) == 1)
  2006. __qdf_nbuf_unmap_single(soc->osdev,
  2007. nbuf,
  2008. QDF_DMA_TO_DEVICE);
  2009. qdf_nbuf_free(nbuf);
  2010. return;
  2011. }
  2012. }
  2013. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2014. if (qdf_likely(!vdev->mesh_vdev))
  2015. qdf_nbuf_free(nbuf);
  2016. else {
  2017. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2018. qdf_nbuf_free(nbuf);
  2019. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2020. } else
  2021. vdev->osif_tx_free_ext((nbuf));
  2022. }
  2023. }
  2024. /**
  2025. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2026. * @vdev: pointer to dp dev handler
  2027. * @status : Tx completion status from HTT descriptor
  2028. *
  2029. * Handles MEC notify event sent from fw to Host
  2030. *
  2031. * Return: none
  2032. */
  2033. #ifdef FEATURE_WDS
  2034. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2035. {
  2036. struct dp_soc *soc;
  2037. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2038. struct dp_peer *peer;
  2039. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2040. if (!vdev->wds_enabled)
  2041. return;
  2042. soc = vdev->pdev->soc;
  2043. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2044. peer = TAILQ_FIRST(&vdev->peer_list);
  2045. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2046. if (!peer) {
  2047. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2048. FL("peer is NULL"));
  2049. return;
  2050. }
  2051. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2052. "%s Tx MEC Handler\n",
  2053. __func__);
  2054. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2055. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2056. status[(DP_MAC_ADDR_LEN - 2) + i];
  2057. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2058. dp_peer_add_ast(soc,
  2059. peer,
  2060. mac_addr,
  2061. CDP_TXRX_AST_TYPE_MEC,
  2062. flags);
  2063. }
  2064. #endif
  2065. /**
  2066. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2067. * @tx_desc: software descriptor head pointer
  2068. * @status : Tx completion status from HTT descriptor
  2069. *
  2070. * This function will process HTT Tx indication messages from Target
  2071. *
  2072. * Return: none
  2073. */
  2074. static
  2075. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2076. {
  2077. uint8_t tx_status;
  2078. struct dp_pdev *pdev;
  2079. struct dp_vdev *vdev;
  2080. struct dp_soc *soc;
  2081. uint32_t *htt_status_word = (uint32_t *) status;
  2082. qdf_assert(tx_desc->pdev);
  2083. pdev = tx_desc->pdev;
  2084. vdev = tx_desc->vdev;
  2085. soc = pdev->soc;
  2086. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  2087. switch (tx_status) {
  2088. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2089. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2090. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2091. {
  2092. dp_tx_comp_free_buf(soc, tx_desc);
  2093. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2094. break;
  2095. }
  2096. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2097. {
  2098. dp_tx_reinject_handler(tx_desc, status);
  2099. break;
  2100. }
  2101. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2102. {
  2103. dp_tx_inspect_handler(tx_desc, status);
  2104. break;
  2105. }
  2106. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2107. {
  2108. dp_tx_mec_handler(vdev, status);
  2109. break;
  2110. }
  2111. default:
  2112. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2113. "%s Invalid HTT tx_status %d\n",
  2114. __func__, tx_status);
  2115. break;
  2116. }
  2117. }
  2118. #ifdef MESH_MODE_SUPPORT
  2119. /**
  2120. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2121. * in mesh meta header
  2122. * @tx_desc: software descriptor head pointer
  2123. * @ts: pointer to tx completion stats
  2124. * Return: none
  2125. */
  2126. static
  2127. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2128. struct hal_tx_completion_status *ts)
  2129. {
  2130. struct meta_hdr_s *mhdr;
  2131. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2132. if (!tx_desc->msdu_ext_desc) {
  2133. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2134. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2135. "netbuf %pK offset %d\n",
  2136. netbuf, tx_desc->pkt_offset);
  2137. return;
  2138. }
  2139. }
  2140. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2141. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2142. "netbuf %pK offset %d\n", netbuf,
  2143. sizeof(struct meta_hdr_s));
  2144. return;
  2145. }
  2146. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2147. mhdr->rssi = ts->ack_frame_rssi;
  2148. mhdr->channel = tx_desc->pdev->operating_channel;
  2149. }
  2150. #else
  2151. static
  2152. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2153. struct hal_tx_completion_status *ts)
  2154. {
  2155. }
  2156. #endif
  2157. /**
  2158. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2159. * @peer: Handle to DP peer
  2160. * @ts: pointer to HAL Tx completion stats
  2161. * @length: MSDU length
  2162. *
  2163. * Return: None
  2164. */
  2165. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2166. struct hal_tx_completion_status *ts, uint32_t length)
  2167. {
  2168. struct dp_pdev *pdev = peer->vdev->pdev;
  2169. struct dp_soc *soc = pdev->soc;
  2170. uint8_t mcs, pkt_type;
  2171. mcs = ts->mcs;
  2172. pkt_type = ts->pkt_type;
  2173. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2174. return;
  2175. if (peer->bss_peer) {
  2176. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2177. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2178. } else {
  2179. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  2180. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2181. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2182. }
  2183. }
  2184. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2185. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2186. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2187. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2188. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2189. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2190. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2191. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2192. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2193. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2194. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2195. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2196. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2197. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2198. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2199. return;
  2200. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2201. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2202. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2203. if (!(soc->process_tx_status))
  2204. return;
  2205. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2206. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2207. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2208. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2209. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2210. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2211. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2212. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2213. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2214. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2215. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2216. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2217. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2218. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2219. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2220. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2221. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2222. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2223. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2224. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2225. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2226. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2227. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2228. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2229. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2230. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2231. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2232. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2233. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2234. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  2235. &peer->stats, ts->peer_id,
  2236. UPDATE_PEER_STATS);
  2237. }
  2238. }
  2239. /**
  2240. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2241. * @tx_desc: software descriptor head pointer
  2242. * @length: packet length
  2243. *
  2244. * Return: none
  2245. */
  2246. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2247. uint32_t length)
  2248. {
  2249. struct hal_tx_completion_status ts;
  2250. struct dp_soc *soc = NULL;
  2251. struct dp_vdev *vdev = tx_desc->vdev;
  2252. struct dp_peer *peer = NULL;
  2253. struct ether_header *eh =
  2254. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2255. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2256. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2257. "-------------------- \n"
  2258. "Tx Completion Stats: \n"
  2259. "-------------------- \n"
  2260. "ack_frame_rssi = %d \n"
  2261. "first_msdu = %d \n"
  2262. "last_msdu = %d \n"
  2263. "msdu_part_of_amsdu = %d \n"
  2264. "rate_stats valid = %d \n"
  2265. "bw = %d \n"
  2266. "pkt_type = %d \n"
  2267. "stbc = %d \n"
  2268. "ldpc = %d \n"
  2269. "sgi = %d \n"
  2270. "mcs = %d \n"
  2271. "ofdma = %d \n"
  2272. "tones_in_ru = %d \n"
  2273. "tsf = %d \n"
  2274. "ppdu_id = %d \n"
  2275. "transmit_cnt = %d \n"
  2276. "tid = %d \n"
  2277. "peer_id = %d \n",
  2278. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2279. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2280. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2281. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2282. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2283. ts.peer_id);
  2284. if (!vdev) {
  2285. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2286. "invalid vdev");
  2287. goto out;
  2288. }
  2289. soc = vdev->pdev->soc;
  2290. /* Update SoC level stats */
  2291. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2292. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2293. /* Update per-packet stats */
  2294. if (qdf_unlikely(vdev->mesh_vdev) &&
  2295. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2296. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2297. /* Update peer level stats */
  2298. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2299. if (!peer) {
  2300. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2301. "invalid peer");
  2302. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2303. goto out;
  2304. }
  2305. if (qdf_likely(peer->vdev->tx_encap_type ==
  2306. htt_cmn_pkt_type_ethernet)) {
  2307. if (peer->bss_peer && IEEE80211_IS_BROADCAST(eh->ether_dhost))
  2308. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2309. }
  2310. dp_tx_update_peer_stats(peer, &ts, length);
  2311. out:
  2312. return;
  2313. }
  2314. /**
  2315. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2316. * @soc: core txrx main context
  2317. * @comp_head: software descriptor head pointer
  2318. *
  2319. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2320. * and release the software descriptors after processing is complete
  2321. *
  2322. * Return: none
  2323. */
  2324. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2325. struct dp_tx_desc_s *comp_head)
  2326. {
  2327. struct dp_tx_desc_s *desc;
  2328. struct dp_tx_desc_s *next;
  2329. struct hal_tx_completion_status ts = {0};
  2330. uint32_t length;
  2331. struct dp_peer *peer;
  2332. DP_HIST_INIT();
  2333. desc = comp_head;
  2334. while (desc) {
  2335. hal_tx_comp_get_status(&desc->comp, &ts);
  2336. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2337. length = qdf_nbuf_len(desc->nbuf);
  2338. dp_tx_comp_process_tx_status(desc, length);
  2339. /*currently m_copy/tx_capture is not supported for scatter gather packets*/
  2340. if (!(desc->msdu_ext_desc) && (dp_get_completion_indication_for_stack(soc,
  2341. desc->pdev, ts.peer_id, ts.ppdu_id,
  2342. ts.first_msdu, ts.last_msdu,
  2343. desc->nbuf) == QDF_STATUS_SUCCESS)) {
  2344. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2345. QDF_DMA_TO_DEVICE);
  2346. dp_send_completion_to_stack(soc, desc->pdev, ts.peer_id,
  2347. ts.ppdu_id, desc->nbuf);
  2348. } else {
  2349. dp_tx_comp_free_buf(soc, desc);
  2350. }
  2351. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2352. next = desc->next;
  2353. dp_tx_desc_release(desc, desc->pool_id);
  2354. desc = next;
  2355. }
  2356. DP_TX_HIST_STATS_PER_PDEV();
  2357. }
  2358. /**
  2359. * dp_tx_comp_handler() - Tx completion handler
  2360. * @soc: core txrx main context
  2361. * @ring_id: completion ring id
  2362. * @quota: No. of packets/descriptors that can be serviced in one loop
  2363. *
  2364. * This function will collect hardware release ring element contents and
  2365. * handle descriptor contents. Based on contents, free packet or handle error
  2366. * conditions
  2367. *
  2368. * Return: none
  2369. */
  2370. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2371. {
  2372. void *tx_comp_hal_desc;
  2373. uint8_t buffer_src;
  2374. uint8_t pool_id;
  2375. uint32_t tx_desc_id;
  2376. struct dp_tx_desc_s *tx_desc = NULL;
  2377. struct dp_tx_desc_s *head_desc = NULL;
  2378. struct dp_tx_desc_s *tail_desc = NULL;
  2379. uint32_t num_processed;
  2380. uint32_t count;
  2381. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2382. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2383. "%s %d : HAL RING Access Failed -- %pK\n",
  2384. __func__, __LINE__, hal_srng);
  2385. return 0;
  2386. }
  2387. num_processed = 0;
  2388. count = 0;
  2389. /* Find head descriptor from completion ring */
  2390. while (qdf_likely(tx_comp_hal_desc =
  2391. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2392. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2393. /* If this buffer was not released by TQM or FW, then it is not
  2394. * Tx completion indication, assert */
  2395. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2396. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2397. QDF_TRACE(QDF_MODULE_ID_DP,
  2398. QDF_TRACE_LEVEL_FATAL,
  2399. "Tx comp release_src != TQM | FW");
  2400. qdf_assert_always(0);
  2401. }
  2402. /* Get descriptor id */
  2403. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2404. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2405. DP_TX_DESC_ID_POOL_OS;
  2406. /* Pool ID is out of limit. Error */
  2407. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  2408. soc->wlan_cfg_ctx)) {
  2409. QDF_TRACE(QDF_MODULE_ID_DP,
  2410. QDF_TRACE_LEVEL_FATAL,
  2411. "Tx Comp pool id %d not valid",
  2412. pool_id);
  2413. qdf_assert_always(0);
  2414. }
  2415. /* Find Tx descriptor */
  2416. tx_desc = dp_tx_desc_find(soc, pool_id,
  2417. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2418. DP_TX_DESC_ID_PAGE_OS,
  2419. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2420. DP_TX_DESC_ID_OFFSET_OS);
  2421. /*
  2422. * If the release source is FW, process the HTT status
  2423. */
  2424. if (qdf_unlikely(buffer_src ==
  2425. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2426. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2427. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2428. htt_tx_status);
  2429. dp_tx_process_htt_completion(tx_desc,
  2430. htt_tx_status);
  2431. } else {
  2432. /* Pool id is not matching. Error */
  2433. if (tx_desc->pool_id != pool_id) {
  2434. QDF_TRACE(QDF_MODULE_ID_DP,
  2435. QDF_TRACE_LEVEL_FATAL,
  2436. "Tx Comp pool id %d not matched %d",
  2437. pool_id, tx_desc->pool_id);
  2438. qdf_assert_always(0);
  2439. }
  2440. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2441. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2442. QDF_TRACE(QDF_MODULE_ID_DP,
  2443. QDF_TRACE_LEVEL_FATAL,
  2444. "Txdesc invalid, flgs = %x,id = %d",
  2445. tx_desc->flags, tx_desc_id);
  2446. qdf_assert_always(0);
  2447. }
  2448. /* First ring descriptor on the cycle */
  2449. if (!head_desc) {
  2450. head_desc = tx_desc;
  2451. tail_desc = tx_desc;
  2452. }
  2453. tail_desc->next = tx_desc;
  2454. tx_desc->next = NULL;
  2455. tail_desc = tx_desc;
  2456. /* Collect hw completion contents */
  2457. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2458. &tx_desc->comp, 1);
  2459. }
  2460. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2461. /* Decrement PM usage count if the packet has been sent.*/
  2462. hif_pm_runtime_put(soc->hif_handle);
  2463. /*
  2464. * Processed packet count is more than given quota
  2465. * stop to processing
  2466. */
  2467. if ((num_processed >= quota))
  2468. break;
  2469. count++;
  2470. }
  2471. hal_srng_access_end(soc->hal_soc, hal_srng);
  2472. /* Process the reaped descriptors */
  2473. if (head_desc)
  2474. dp_tx_comp_process_desc(soc, head_desc);
  2475. return num_processed;
  2476. }
  2477. #ifdef CONVERGED_TDLS_ENABLE
  2478. /**
  2479. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2480. *
  2481. * @data_vdev - which vdev should transmit the tx data frames
  2482. * @tx_spec - what non-standard handling to apply to the tx data frames
  2483. * @msdu_list - NULL-terminated list of tx MSDUs
  2484. *
  2485. * Return: NULL on success,
  2486. * nbuf when it fails to send
  2487. */
  2488. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2489. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2490. {
  2491. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2492. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2493. vdev->is_tdls_frame = true;
  2494. return dp_tx_send(vdev_handle, msdu_list);
  2495. }
  2496. #endif
  2497. /**
  2498. * dp_tx_vdev_attach() - attach vdev to dp tx
  2499. * @vdev: virtual device instance
  2500. *
  2501. * Return: QDF_STATUS_SUCCESS: success
  2502. * QDF_STATUS_E_RESOURCES: Error return
  2503. */
  2504. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2505. {
  2506. /*
  2507. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2508. */
  2509. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2510. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2511. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2512. vdev->vdev_id);
  2513. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2514. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2515. /*
  2516. * Set HTT Extension Valid bit to 0 by default
  2517. */
  2518. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2519. dp_tx_vdev_update_search_flags(vdev);
  2520. return QDF_STATUS_SUCCESS;
  2521. }
  2522. /**
  2523. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2524. * @vdev: virtual device instance
  2525. *
  2526. * Return: void
  2527. *
  2528. */
  2529. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2530. {
  2531. /*
  2532. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2533. * for TDLS link
  2534. *
  2535. * Enable AddrY (SA based search) only for non-WDS STA and
  2536. * ProxySTA VAP modes.
  2537. *
  2538. * In all other VAP modes, only DA based search should be
  2539. * enabled
  2540. */
  2541. if (vdev->opmode == wlan_op_mode_sta &&
  2542. vdev->tdls_link_connected)
  2543. vdev->hal_desc_addr_search_flags =
  2544. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2545. else if ((vdev->opmode == wlan_op_mode_sta &&
  2546. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2547. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2548. else
  2549. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2550. }
  2551. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2552. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2553. {
  2554. }
  2555. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2556. /* dp_tx_desc_flush() - release resources associated
  2557. * to tx_desc
  2558. * @vdev: virtual device instance
  2559. *
  2560. * This function will free all outstanding Tx buffers,
  2561. * including ME buffer for which either free during
  2562. * completion didn't happened or completion is not
  2563. * received.
  2564. */
  2565. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2566. {
  2567. uint8_t i, num_pool;
  2568. uint32_t j;
  2569. uint32_t num_desc;
  2570. struct dp_soc *soc = vdev->pdev->soc;
  2571. struct dp_tx_desc_s *tx_desc = NULL;
  2572. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2573. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2574. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2575. for (i = 0; i < num_pool; i++) {
  2576. for (j = 0; j < num_desc; j++) {
  2577. tx_desc_pool = &((soc)->tx_desc[(i)]);
  2578. if (tx_desc_pool &&
  2579. tx_desc_pool->desc_pages.cacheable_pages) {
  2580. tx_desc = dp_tx_desc_find(soc, i,
  2581. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2582. DP_TX_DESC_ID_PAGE_OS,
  2583. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2584. DP_TX_DESC_ID_OFFSET_OS);
  2585. if (tx_desc && (tx_desc->vdev == vdev) &&
  2586. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2587. dp_tx_comp_free_buf(soc, tx_desc);
  2588. dp_tx_desc_release(tx_desc, i);
  2589. }
  2590. }
  2591. }
  2592. }
  2593. }
  2594. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2595. /**
  2596. * dp_tx_vdev_detach() - detach vdev from dp tx
  2597. * @vdev: virtual device instance
  2598. *
  2599. * Return: QDF_STATUS_SUCCESS: success
  2600. * QDF_STATUS_E_RESOURCES: Error return
  2601. */
  2602. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2603. {
  2604. dp_tx_desc_flush(vdev);
  2605. return QDF_STATUS_SUCCESS;
  2606. }
  2607. /**
  2608. * dp_tx_pdev_attach() - attach pdev to dp tx
  2609. * @pdev: physical device instance
  2610. *
  2611. * Return: QDF_STATUS_SUCCESS: success
  2612. * QDF_STATUS_E_RESOURCES: Error return
  2613. */
  2614. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2615. {
  2616. struct dp_soc *soc = pdev->soc;
  2617. /* Initialize Flow control counters */
  2618. qdf_atomic_init(&pdev->num_tx_exception);
  2619. qdf_atomic_init(&pdev->num_tx_outstanding);
  2620. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2621. /* Initialize descriptors in TCL Ring */
  2622. hal_tx_init_data_ring(soc->hal_soc,
  2623. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2624. }
  2625. return QDF_STATUS_SUCCESS;
  2626. }
  2627. /**
  2628. * dp_tx_pdev_detach() - detach pdev from dp tx
  2629. * @pdev: physical device instance
  2630. *
  2631. * Return: QDF_STATUS_SUCCESS: success
  2632. * QDF_STATUS_E_RESOURCES: Error return
  2633. */
  2634. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2635. {
  2636. dp_tx_me_exit(pdev);
  2637. return QDF_STATUS_SUCCESS;
  2638. }
  2639. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2640. /* Pools will be allocated dynamically */
  2641. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2642. int num_desc)
  2643. {
  2644. uint8_t i;
  2645. for (i = 0; i < num_pool; i++) {
  2646. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2647. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2648. }
  2649. return 0;
  2650. }
  2651. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2652. {
  2653. uint8_t i;
  2654. for (i = 0; i < num_pool; i++)
  2655. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2656. }
  2657. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2658. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2659. int num_desc)
  2660. {
  2661. uint8_t i;
  2662. /* Allocate software Tx descriptor pools */
  2663. for (i = 0; i < num_pool; i++) {
  2664. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2665. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2666. "%s Tx Desc Pool alloc %d failed %pK\n",
  2667. __func__, i, soc);
  2668. return ENOMEM;
  2669. }
  2670. }
  2671. return 0;
  2672. }
  2673. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2674. {
  2675. uint8_t i;
  2676. for (i = 0; i < num_pool; i++) {
  2677. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  2678. if (dp_tx_desc_pool_free(soc, i)) {
  2679. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2680. "%s Tx Desc Pool Free failed\n", __func__);
  2681. }
  2682. }
  2683. }
  2684. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2685. /**
  2686. * dp_tx_soc_detach() - detach soc from dp tx
  2687. * @soc: core txrx main context
  2688. *
  2689. * This function will detach dp tx into main device context
  2690. * will free dp tx resource and initialize resources
  2691. *
  2692. * Return: QDF_STATUS_SUCCESS: success
  2693. * QDF_STATUS_E_RESOURCES: Error return
  2694. */
  2695. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2696. {
  2697. uint8_t num_pool;
  2698. uint16_t num_desc;
  2699. uint16_t num_ext_desc;
  2700. uint8_t i;
  2701. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2702. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2703. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2704. dp_tx_flow_control_deinit(soc);
  2705. dp_tx_delete_static_pools(soc, num_pool);
  2706. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2707. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2708. __func__, num_pool, num_desc);
  2709. for (i = 0; i < num_pool; i++) {
  2710. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2711. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2712. "%s Tx Ext Desc Pool Free failed\n",
  2713. __func__);
  2714. return QDF_STATUS_E_RESOURCES;
  2715. }
  2716. }
  2717. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2718. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2719. __func__, num_pool, num_ext_desc);
  2720. for (i = 0; i < num_pool; i++) {
  2721. dp_tx_tso_desc_pool_free(soc, i);
  2722. }
  2723. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2724. "%s TSO Desc Pool %d Free descs = %d\n",
  2725. __func__, num_pool, num_desc);
  2726. for (i = 0; i < num_pool; i++)
  2727. dp_tx_tso_num_seg_pool_free(soc, i);
  2728. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2729. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2730. __func__, num_pool, num_desc);
  2731. return QDF_STATUS_SUCCESS;
  2732. }
  2733. /**
  2734. * dp_tx_soc_attach() - attach soc to dp tx
  2735. * @soc: core txrx main context
  2736. *
  2737. * This function will attach dp tx into main device context
  2738. * will allocate dp tx resource and initialize resources
  2739. *
  2740. * Return: QDF_STATUS_SUCCESS: success
  2741. * QDF_STATUS_E_RESOURCES: Error return
  2742. */
  2743. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2744. {
  2745. uint8_t i;
  2746. uint8_t num_pool;
  2747. uint32_t num_desc;
  2748. uint32_t num_ext_desc;
  2749. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2750. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2751. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2752. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2753. goto fail;
  2754. dp_tx_flow_control_init(soc);
  2755. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2756. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2757. __func__, num_pool, num_desc);
  2758. /* Allocate extension tx descriptor pools */
  2759. for (i = 0; i < num_pool; i++) {
  2760. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2761. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2762. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2763. i, soc);
  2764. goto fail;
  2765. }
  2766. }
  2767. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2768. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2769. __func__, num_pool, num_ext_desc);
  2770. for (i = 0; i < num_pool; i++) {
  2771. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2772. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2773. "TSO Desc Pool alloc %d failed %pK\n",
  2774. i, soc);
  2775. goto fail;
  2776. }
  2777. }
  2778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2779. "%s TSO Desc Alloc %d, descs = %d\n",
  2780. __func__, num_pool, num_desc);
  2781. for (i = 0; i < num_pool; i++) {
  2782. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2783. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2784. "TSO Num of seg Pool alloc %d failed %pK\n",
  2785. i, soc);
  2786. goto fail;
  2787. }
  2788. }
  2789. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2790. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2791. __func__, num_pool, num_desc);
  2792. /* Initialize descriptors in TCL Rings */
  2793. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2794. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2795. hal_tx_init_data_ring(soc->hal_soc,
  2796. soc->tcl_data_ring[i].hal_srng);
  2797. }
  2798. }
  2799. /*
  2800. * todo - Add a runtime config option to enable this.
  2801. */
  2802. /*
  2803. * Due to multiple issues on NPR EMU, enable it selectively
  2804. * only for NPR EMU, should be removed, once NPR platforms
  2805. * are stable.
  2806. */
  2807. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  2808. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2809. "%s HAL Tx init Success\n", __func__);
  2810. return QDF_STATUS_SUCCESS;
  2811. fail:
  2812. /* Detach will take care of freeing only allocated resources */
  2813. dp_tx_soc_detach(soc);
  2814. return QDF_STATUS_E_RESOURCES;
  2815. }
  2816. /*
  2817. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2818. * pdev: pointer to DP PDEV structure
  2819. * seg_info_head: Pointer to the head of list
  2820. *
  2821. * return: void
  2822. */
  2823. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2824. struct dp_tx_seg_info_s *seg_info_head)
  2825. {
  2826. struct dp_tx_me_buf_t *mc_uc_buf;
  2827. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2828. qdf_nbuf_t nbuf = NULL;
  2829. uint64_t phy_addr;
  2830. while (seg_info_head) {
  2831. nbuf = seg_info_head->nbuf;
  2832. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2833. seg_info_head->frags[0].vaddr;
  2834. phy_addr = seg_info_head->frags[0].paddr_hi;
  2835. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2836. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2837. phy_addr,
  2838. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2839. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2840. qdf_nbuf_free(nbuf);
  2841. seg_info_new = seg_info_head;
  2842. seg_info_head = seg_info_head->next;
  2843. qdf_mem_free(seg_info_new);
  2844. }
  2845. }
  2846. /**
  2847. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2848. * @vdev: DP VDEV handle
  2849. * @nbuf: Multicast nbuf
  2850. * @newmac: Table of the clients to which packets have to be sent
  2851. * @new_mac_cnt: No of clients
  2852. *
  2853. * return: no of converted packets
  2854. */
  2855. uint16_t
  2856. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2857. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2858. {
  2859. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2860. struct dp_pdev *pdev = vdev->pdev;
  2861. struct ether_header *eh;
  2862. uint8_t *data;
  2863. uint16_t len;
  2864. /* reference to frame dst addr */
  2865. uint8_t *dstmac;
  2866. /* copy of original frame src addr */
  2867. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2868. /* local index into newmac */
  2869. uint8_t new_mac_idx = 0;
  2870. struct dp_tx_me_buf_t *mc_uc_buf;
  2871. qdf_nbuf_t nbuf_clone;
  2872. struct dp_tx_msdu_info_s msdu_info;
  2873. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2874. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2875. struct dp_tx_seg_info_s *seg_info_new;
  2876. struct dp_tx_frag_info_s data_frag;
  2877. qdf_dma_addr_t paddr_data;
  2878. qdf_dma_addr_t paddr_mcbuf = 0;
  2879. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2880. QDF_STATUS status;
  2881. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2882. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2883. eh = (struct ether_header *) nbuf;
  2884. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2885. len = qdf_nbuf_len(nbuf);
  2886. data = qdf_nbuf_data(nbuf);
  2887. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2888. QDF_DMA_TO_DEVICE);
  2889. if (status) {
  2890. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2891. "Mapping failure Error:%d", status);
  2892. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2893. qdf_nbuf_free(nbuf);
  2894. return 1;
  2895. }
  2896. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2897. /*preparing data fragment*/
  2898. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2899. data_frag.paddr_lo = (uint32_t)paddr_data;
  2900. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  2901. data_frag.len = len - DP_MAC_ADDR_LEN;
  2902. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2903. dstmac = newmac[new_mac_idx];
  2904. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2905. "added mac addr (%pM)", dstmac);
  2906. /* Check for NULL Mac Address */
  2907. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2908. continue;
  2909. /* frame to self mac. skip */
  2910. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2911. continue;
  2912. /*
  2913. * TODO: optimize to avoid malloc in per-packet path
  2914. * For eg. seg_pool can be made part of vdev structure
  2915. */
  2916. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2917. if (!seg_info_new) {
  2918. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2919. "alloc failed");
  2920. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2921. goto fail_seg_alloc;
  2922. }
  2923. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2924. if (mc_uc_buf == NULL)
  2925. goto fail_buf_alloc;
  2926. /*
  2927. * TODO: Check if we need to clone the nbuf
  2928. * Or can we just use the reference for all cases
  2929. */
  2930. if (new_mac_idx < (new_mac_cnt - 1)) {
  2931. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2932. if (nbuf_clone == NULL) {
  2933. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2934. goto fail_clone;
  2935. }
  2936. } else {
  2937. /*
  2938. * Update the ref
  2939. * to account for frame sent without cloning
  2940. */
  2941. qdf_nbuf_ref(nbuf);
  2942. nbuf_clone = nbuf;
  2943. }
  2944. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2945. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2946. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2947. &paddr_mcbuf);
  2948. if (status) {
  2949. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2950. "Mapping failure Error:%d", status);
  2951. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2952. goto fail_map;
  2953. }
  2954. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2955. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2956. seg_info_new->frags[0].paddr_hi =
  2957. ((uint64_t) paddr_mcbuf >> 32);
  2958. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2959. seg_info_new->frags[1] = data_frag;
  2960. seg_info_new->nbuf = nbuf_clone;
  2961. seg_info_new->frag_cnt = 2;
  2962. seg_info_new->total_len = len;
  2963. seg_info_new->next = NULL;
  2964. if (seg_info_head == NULL)
  2965. seg_info_head = seg_info_new;
  2966. else
  2967. seg_info_tail->next = seg_info_new;
  2968. seg_info_tail = seg_info_new;
  2969. }
  2970. if (!seg_info_head) {
  2971. goto free_return;
  2972. }
  2973. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2974. msdu_info.num_seg = new_mac_cnt;
  2975. msdu_info.frm_type = dp_tx_frm_me;
  2976. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2977. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2978. while (seg_info_head->next) {
  2979. seg_info_new = seg_info_head;
  2980. seg_info_head = seg_info_head->next;
  2981. qdf_mem_free(seg_info_new);
  2982. }
  2983. qdf_mem_free(seg_info_head);
  2984. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2985. qdf_nbuf_free(nbuf);
  2986. return new_mac_cnt;
  2987. fail_map:
  2988. qdf_nbuf_free(nbuf_clone);
  2989. fail_clone:
  2990. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2991. fail_buf_alloc:
  2992. qdf_mem_free(seg_info_new);
  2993. fail_seg_alloc:
  2994. dp_tx_me_mem_free(pdev, seg_info_head);
  2995. free_return:
  2996. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2997. qdf_nbuf_free(nbuf);
  2998. return 1;
  2999. }