main.c 105 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/elf.h>
  9. #include <linux/jiffies.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_wakeup.h>
  15. #include <linux/reboot.h>
  16. #include <linux/rwsem.h>
  17. #include <linux/suspend.h>
  18. #include <linux/timer.h>
  19. #include <linux/version.h>
  20. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0))
  21. #include <linux/panic_notifier.h>
  22. #endif
  23. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  24. #include <soc/qcom/minidump.h>
  25. #endif
  26. #include "cnss_plat_ipc_qmi.h"
  27. #include "cnss_utils.h"
  28. #include "main.h"
  29. #include "bus.h"
  30. #include "debug.h"
  31. #include "genl.h"
  32. #include "reg.h"
  33. #define CNSS_DUMP_FORMAT_VER 0x11
  34. #define CNSS_DUMP_FORMAT_VER_V2 0x22
  35. #define CNSS_DUMP_MAGIC_VER_V2 0x42445953
  36. #define CNSS_DUMP_NAME "CNSS_WLAN"
  37. #define CNSS_DUMP_DESC_SIZE 0x1000
  38. #define CNSS_DUMP_SEG_VER 0x1
  39. #define FILE_SYSTEM_READY 1
  40. #define FW_READY_TIMEOUT 20000
  41. #define FW_ASSERT_TIMEOUT 5000
  42. #define CNSS_EVENT_PENDING 2989
  43. #define POWER_RESET_MIN_DELAY_MS 100
  44. #define CNSS_QUIRKS_DEFAULT 0
  45. #ifdef CONFIG_CNSS_EMULATION
  46. #define CNSS_MHI_TIMEOUT_DEFAULT 90000
  47. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 2000
  48. #define CNSS_QMI_TIMEOUT_DEFAULT 90000
  49. #else
  50. #define CNSS_MHI_TIMEOUT_DEFAULT 0
  51. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
  52. #define CNSS_QMI_TIMEOUT_DEFAULT 10000
  53. #endif
  54. #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
  55. #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
  56. #define CNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  57. #define CNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  58. #define CNSS_DAEMON_CONNECT_TIMEOUT_MS 30000
  59. #define CNSS_CAL_DB_FILE_NAME "wlfw_cal_db.bin"
  60. #define CNSS_CAL_START_PROBE_WAIT_RETRY_MAX 100
  61. #define CNSS_CAL_START_PROBE_WAIT_MS 500
  62. enum cnss_cal_db_op {
  63. CNSS_CAL_DB_UPLOAD,
  64. CNSS_CAL_DB_DOWNLOAD,
  65. CNSS_CAL_DB_INVALID_OP,
  66. };
  67. enum cnss_recovery_type {
  68. CNSS_WLAN_RECOVERY = 0x1,
  69. CNSS_PCSS_RECOVERY = 0x2,
  70. };
  71. static struct cnss_plat_data *plat_env;
  72. static bool cnss_allow_driver_loading;
  73. static DECLARE_RWSEM(cnss_pm_sem);
  74. static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = {
  75. "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin",
  76. "utfbd30.bin", "epping30.bin", "evicted30.bin"
  77. };
  78. static struct cnss_fw_files FW_FILES_DEFAULT = {
  79. "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin",
  80. "utfbd.bin", "epping.bin", "evicted.bin"
  81. };
  82. struct cnss_driver_event {
  83. struct list_head list;
  84. enum cnss_driver_event_type type;
  85. bool sync;
  86. struct completion complete;
  87. int ret;
  88. void *data;
  89. };
  90. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  91. struct cnss_plat_data *plat_priv)
  92. {
  93. plat_env = plat_priv;
  94. }
  95. bool cnss_check_driver_loading_allowed(void)
  96. {
  97. return cnss_allow_driver_loading;
  98. }
  99. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev)
  100. {
  101. return plat_env;
  102. }
  103. /**
  104. * cnss_get_mem_seg_count - Get segment count of memory
  105. * @type: memory type
  106. * @seg: segment count
  107. *
  108. * Return: 0 on success, negative value on failure
  109. */
  110. int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg)
  111. {
  112. struct cnss_plat_data *plat_priv;
  113. plat_priv = cnss_get_plat_priv(NULL);
  114. if (!plat_priv)
  115. return -ENODEV;
  116. switch (type) {
  117. case CNSS_REMOTE_MEM_TYPE_FW:
  118. *seg = plat_priv->fw_mem_seg_len;
  119. break;
  120. case CNSS_REMOTE_MEM_TYPE_QDSS:
  121. *seg = plat_priv->qdss_mem_seg_len;
  122. break;
  123. default:
  124. return -EINVAL;
  125. }
  126. return 0;
  127. }
  128. EXPORT_SYMBOL(cnss_get_mem_seg_count);
  129. /**
  130. * cnss_get_mem_segment_info - Get memory info of different type
  131. * @type: memory type
  132. * @segment: array to save the segment info
  133. * @seg: segment count
  134. *
  135. * Return: 0 on success, negative value on failure
  136. */
  137. int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  138. struct cnss_mem_segment segment[],
  139. u32 segment_count)
  140. {
  141. struct cnss_plat_data *plat_priv;
  142. u32 i;
  143. plat_priv = cnss_get_plat_priv(NULL);
  144. if (!plat_priv)
  145. return -ENODEV;
  146. switch (type) {
  147. case CNSS_REMOTE_MEM_TYPE_FW:
  148. if (segment_count > plat_priv->fw_mem_seg_len)
  149. segment_count = plat_priv->fw_mem_seg_len;
  150. for (i = 0; i < segment_count; i++) {
  151. segment[i].size = plat_priv->fw_mem[i].size;
  152. segment[i].va = plat_priv->fw_mem[i].va;
  153. segment[i].pa = plat_priv->fw_mem[i].pa;
  154. }
  155. break;
  156. case CNSS_REMOTE_MEM_TYPE_QDSS:
  157. if (segment_count > plat_priv->qdss_mem_seg_len)
  158. segment_count = plat_priv->qdss_mem_seg_len;
  159. for (i = 0; i < segment_count; i++) {
  160. segment[i].size = plat_priv->qdss_mem[i].size;
  161. segment[i].va = plat_priv->qdss_mem[i].va;
  162. segment[i].pa = plat_priv->qdss_mem[i].pa;
  163. }
  164. break;
  165. default:
  166. return -EINVAL;
  167. }
  168. return 0;
  169. }
  170. EXPORT_SYMBOL(cnss_get_mem_segment_info);
  171. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  172. enum cnss_feature_v01 feature)
  173. {
  174. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  175. return -EINVAL;
  176. plat_priv->feature_list |= 1 << feature;
  177. return 0;
  178. }
  179. int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
  180. enum cnss_feature_v01 feature)
  181. {
  182. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  183. return -EINVAL;
  184. plat_priv->feature_list &= ~(1 << feature);
  185. return 0;
  186. }
  187. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  188. u64 *feature_list)
  189. {
  190. if (unlikely(!plat_priv))
  191. return -EINVAL;
  192. *feature_list = plat_priv->feature_list;
  193. return 0;
  194. }
  195. static int cnss_pm_notify(struct notifier_block *b,
  196. unsigned long event, void *p)
  197. {
  198. switch (event) {
  199. case PM_SUSPEND_PREPARE:
  200. down_write(&cnss_pm_sem);
  201. break;
  202. case PM_POST_SUSPEND:
  203. up_write(&cnss_pm_sem);
  204. break;
  205. }
  206. return NOTIFY_DONE;
  207. }
  208. static struct notifier_block cnss_pm_notifier = {
  209. .notifier_call = cnss_pm_notify,
  210. };
  211. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv)
  212. {
  213. if (atomic_inc_return(&plat_priv->pm_count) != 1)
  214. return;
  215. cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n",
  216. plat_priv->driver_state,
  217. atomic_read(&plat_priv->pm_count));
  218. pm_stay_awake(&plat_priv->plat_dev->dev);
  219. }
  220. void cnss_pm_relax(struct cnss_plat_data *plat_priv)
  221. {
  222. int r = atomic_dec_return(&plat_priv->pm_count);
  223. WARN_ON(r < 0);
  224. if (r != 0)
  225. return;
  226. cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n",
  227. plat_priv->driver_state,
  228. atomic_read(&plat_priv->pm_count));
  229. pm_relax(&plat_priv->plat_dev->dev);
  230. }
  231. void cnss_lock_pm_sem(struct device *dev)
  232. {
  233. down_read(&cnss_pm_sem);
  234. }
  235. EXPORT_SYMBOL(cnss_lock_pm_sem);
  236. void cnss_release_pm_sem(struct device *dev)
  237. {
  238. up_read(&cnss_pm_sem);
  239. }
  240. EXPORT_SYMBOL(cnss_release_pm_sem);
  241. int cnss_get_fw_files_for_target(struct device *dev,
  242. struct cnss_fw_files *pfw_files,
  243. u32 target_type, u32 target_version)
  244. {
  245. if (!pfw_files)
  246. return -ENODEV;
  247. switch (target_version) {
  248. case QCA6174_REV3_VERSION:
  249. case QCA6174_REV3_2_VERSION:
  250. memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files));
  251. break;
  252. default:
  253. memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files));
  254. cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X",
  255. target_type, target_version);
  256. break;
  257. }
  258. return 0;
  259. }
  260. EXPORT_SYMBOL(cnss_get_fw_files_for_target);
  261. int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
  262. {
  263. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  264. if (!plat_priv)
  265. return -ENODEV;
  266. if (!cap)
  267. return -EINVAL;
  268. *cap = plat_priv->cap;
  269. cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);
  270. return 0;
  271. }
  272. EXPORT_SYMBOL(cnss_get_platform_cap);
  273. void cnss_request_pm_qos(struct device *dev, u32 qos_val)
  274. {
  275. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  276. if (!plat_priv)
  277. return;
  278. cpu_latency_qos_add_request(&plat_priv->qos_request, qos_val);
  279. }
  280. EXPORT_SYMBOL(cnss_request_pm_qos);
  281. void cnss_remove_pm_qos(struct device *dev)
  282. {
  283. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  284. if (!plat_priv)
  285. return;
  286. cpu_latency_qos_remove_request(&plat_priv->qos_request);
  287. }
  288. EXPORT_SYMBOL(cnss_remove_pm_qos);
  289. int cnss_wlan_enable(struct device *dev,
  290. struct cnss_wlan_enable_cfg *config,
  291. enum cnss_driver_mode mode,
  292. const char *host_version)
  293. {
  294. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  295. int ret = 0;
  296. if (!plat_priv)
  297. return -ENODEV;
  298. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  299. return 0;
  300. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  301. return 0;
  302. if (!config || !host_version) {
  303. cnss_pr_err("Invalid config or host_version pointer\n");
  304. return -EINVAL;
  305. }
  306. cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n",
  307. mode, config, host_version);
  308. if (mode == CNSS_WALTEST || mode == CNSS_CCPM)
  309. goto skip_cfg;
  310. ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version);
  311. if (ret)
  312. goto out;
  313. skip_cfg:
  314. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode);
  315. out:
  316. return ret;
  317. }
  318. EXPORT_SYMBOL(cnss_wlan_enable);
  319. int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
  320. {
  321. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  322. int ret = 0;
  323. if (!plat_priv)
  324. return -ENODEV;
  325. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  326. return 0;
  327. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  328. return 0;
  329. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  330. cnss_bus_free_qdss_mem(plat_priv);
  331. return ret;
  332. }
  333. EXPORT_SYMBOL(cnss_wlan_disable);
  334. int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
  335. u32 data_len, u8 *output)
  336. {
  337. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  338. int ret = 0;
  339. if (!plat_priv) {
  340. cnss_pr_err("plat_priv is NULL!\n");
  341. return -EINVAL;
  342. }
  343. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  344. return 0;
  345. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  346. cnss_pr_err("Invalid state for athdiag read: 0x%lx\n",
  347. plat_priv->driver_state);
  348. ret = -EINVAL;
  349. goto out;
  350. }
  351. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type,
  352. data_len, output);
  353. out:
  354. return ret;
  355. }
  356. EXPORT_SYMBOL(cnss_athdiag_read);
  357. int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type,
  358. u32 data_len, u8 *input)
  359. {
  360. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  361. int ret = 0;
  362. if (!plat_priv) {
  363. cnss_pr_err("plat_priv is NULL!\n");
  364. return -EINVAL;
  365. }
  366. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  367. return 0;
  368. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  369. cnss_pr_err("Invalid state for athdiag write: 0x%lx\n",
  370. plat_priv->driver_state);
  371. ret = -EINVAL;
  372. goto out;
  373. }
  374. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type,
  375. data_len, input);
  376. out:
  377. return ret;
  378. }
  379. EXPORT_SYMBOL(cnss_athdiag_write);
  380. int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode)
  381. {
  382. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  383. if (!plat_priv)
  384. return -ENODEV;
  385. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  386. return 0;
  387. return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode);
  388. }
  389. EXPORT_SYMBOL(cnss_set_fw_log_mode);
  390. int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed)
  391. {
  392. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  393. if (!plat_priv)
  394. return -EINVAL;
  395. if (plat_priv->device_id != QCA6490_DEVICE_ID ||
  396. !plat_priv->fw_pcie_gen_switch)
  397. return -EOPNOTSUPP;
  398. if (pcie_gen_speed < QMI_PCIE_GEN_SPEED_1_V01 ||
  399. pcie_gen_speed > QMI_PCIE_GEN_SPEED_3_V01)
  400. return -EINVAL;
  401. cnss_pr_dbg("WLAN provided PCIE gen speed: %d\n", pcie_gen_speed);
  402. plat_priv->pcie_gen_speed = pcie_gen_speed;
  403. return 0;
  404. }
  405. EXPORT_SYMBOL(cnss_set_pcie_gen_speed);
  406. static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv)
  407. {
  408. int ret = 0;
  409. if (!plat_priv)
  410. return -ENODEV;
  411. set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  412. ret = cnss_wlfw_tgt_cap_send_sync(plat_priv);
  413. if (ret)
  414. goto out;
  415. if (plat_priv->hds_enabled)
  416. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_HDS);
  417. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB);
  418. cnss_wlfw_ini_file_send_sync(plat_priv, WLFW_CONN_ROAM_INI_V01);
  419. ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv,
  420. plat_priv->ctrl_params.bdf_type);
  421. if (ret)
  422. goto out;
  423. ret = cnss_bus_load_m3(plat_priv);
  424. if (ret)
  425. goto out;
  426. ret = cnss_wlfw_m3_dnld_send_sync(plat_priv);
  427. if (ret)
  428. goto out;
  429. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  430. return 0;
  431. out:
  432. return ret;
  433. }
  434. static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv)
  435. {
  436. int ret = 0;
  437. if (!plat_priv->antenna) {
  438. ret = cnss_wlfw_antenna_switch_send_sync(plat_priv);
  439. if (ret)
  440. goto out;
  441. }
  442. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) {
  443. ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv);
  444. if (ret)
  445. goto out;
  446. }
  447. ret = cnss_wlfw_antenna_grant_send_sync(plat_priv);
  448. if (ret)
  449. goto out;
  450. return 0;
  451. out:
  452. return ret;
  453. }
  454. static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv)
  455. {
  456. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state))
  457. coex_antenna_switch_to_mdm_send_sync_msg(plat_priv);
  458. }
  459. static int cnss_setup_dms_mac(struct cnss_plat_data *plat_priv)
  460. {
  461. u32 i;
  462. int ret = 0;
  463. struct cnss_plat_ipc_daemon_config *cfg;
  464. ret = cnss_qmi_get_dms_mac(plat_priv);
  465. if (ret == 0 && plat_priv->dms.mac_valid)
  466. goto qmi_send;
  467. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  468. * Thus assert on failure to get MAC from DMS even after retries
  469. */
  470. if (plat_priv->use_nv_mac) {
  471. /* Check if Daemon says platform support DMS MAC provisioning */
  472. cfg = cnss_plat_ipc_qmi_daemon_config();
  473. if (cfg) {
  474. if (!cfg->dms_mac_addr_supported) {
  475. cnss_pr_err("DMS MAC address not supported\n");
  476. CNSS_ASSERT(0);
  477. return -EINVAL;
  478. }
  479. }
  480. for (i = 0; i < CNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  481. if (plat_priv->dms.mac_valid)
  482. break;
  483. ret = cnss_qmi_get_dms_mac(plat_priv);
  484. if (ret == 0)
  485. break;
  486. msleep(CNSS_DMS_QMI_CONNECTION_WAIT_MS);
  487. }
  488. if (!plat_priv->dms.mac_valid) {
  489. cnss_pr_err("Unable to get MAC from DMS after retries\n");
  490. CNSS_ASSERT(0);
  491. return -EINVAL;
  492. }
  493. }
  494. qmi_send:
  495. if (plat_priv->dms.mac_valid)
  496. ret =
  497. cnss_wlfw_wlan_mac_req_send_sync(plat_priv, plat_priv->dms.mac,
  498. ARRAY_SIZE(plat_priv->dms.mac));
  499. return ret;
  500. }
  501. static int cnss_cal_db_mem_update(struct cnss_plat_data *plat_priv,
  502. enum cnss_cal_db_op op, u32 *size)
  503. {
  504. int ret = 0;
  505. u32 timeout = cnss_get_timeout(plat_priv,
  506. CNSS_TIMEOUT_DAEMON_CONNECTION);
  507. enum cnss_plat_ipc_qmi_client_id_v01 client_id =
  508. CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01;
  509. if (op >= CNSS_CAL_DB_INVALID_OP)
  510. return -EINVAL;
  511. if (!plat_priv->cbc_file_download) {
  512. cnss_pr_info("CAL DB file not required as per BDF\n");
  513. return 0;
  514. }
  515. if (*size == 0) {
  516. cnss_pr_err("Invalid cal file size\n");
  517. return -EINVAL;
  518. }
  519. if (!test_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state)) {
  520. cnss_pr_info("Waiting for CNSS Daemon connection\n");
  521. ret = wait_for_completion_timeout(&plat_priv->daemon_connected,
  522. msecs_to_jiffies(timeout));
  523. if (!ret) {
  524. cnss_pr_err("Daemon not yet connected\n");
  525. CNSS_ASSERT(0);
  526. return ret;
  527. }
  528. }
  529. if (!plat_priv->cal_mem->va) {
  530. cnss_pr_err("CAL DB Memory not setup for FW\n");
  531. return -EINVAL;
  532. }
  533. /* Copy CAL DB file contents to/from CAL_TYPE_DDR mem allocated to FW */
  534. if (op == CNSS_CAL_DB_DOWNLOAD) {
  535. cnss_pr_dbg("Initiating Calibration file download to mem\n");
  536. ret = cnss_plat_ipc_qmi_file_download(client_id,
  537. CNSS_CAL_DB_FILE_NAME,
  538. plat_priv->cal_mem->va,
  539. size);
  540. } else {
  541. cnss_pr_dbg("Initiating Calibration mem upload to file\n");
  542. ret = cnss_plat_ipc_qmi_file_upload(client_id,
  543. CNSS_CAL_DB_FILE_NAME,
  544. plat_priv->cal_mem->va,
  545. *size);
  546. }
  547. if (ret)
  548. cnss_pr_err("Cal DB file %s %s failure\n",
  549. CNSS_CAL_DB_FILE_NAME,
  550. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload");
  551. else
  552. cnss_pr_dbg("Cal DB file %s %s size %d done\n",
  553. CNSS_CAL_DB_FILE_NAME,
  554. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload",
  555. *size);
  556. return ret;
  557. }
  558. static int cnss_cal_mem_upload_to_file(struct cnss_plat_data *plat_priv)
  559. {
  560. if (plat_priv->cal_file_size > plat_priv->cal_mem->size) {
  561. cnss_pr_err("Cal file size is larger than Cal DB Mem size\n");
  562. return -EINVAL;
  563. }
  564. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_UPLOAD,
  565. &plat_priv->cal_file_size);
  566. }
  567. static int cnss_cal_file_download_to_mem(struct cnss_plat_data *plat_priv,
  568. u32 *cal_file_size)
  569. {
  570. /* To download pass the total size of cal DB mem allocated.
  571. * After cal file is download to mem, its size is updated in
  572. * return pointer
  573. */
  574. *cal_file_size = plat_priv->cal_mem->size;
  575. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_DOWNLOAD,
  576. cal_file_size);
  577. }
  578. static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv)
  579. {
  580. int ret = 0;
  581. u32 cal_file_size = 0;
  582. if (!plat_priv)
  583. return -ENODEV;
  584. cnss_pr_dbg("Processing FW Init Done..\n");
  585. del_timer(&plat_priv->fw_boot_timer);
  586. set_bit(CNSS_FW_READY, &plat_priv->driver_state);
  587. clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
  588. cnss_wlfw_send_pcie_gen_speed_sync(plat_priv);
  589. if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) {
  590. clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state);
  591. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  592. }
  593. if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) {
  594. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  595. CNSS_WALTEST);
  596. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  597. cnss_request_antenna_sharing(plat_priv);
  598. cnss_cal_file_download_to_mem(plat_priv, &cal_file_size);
  599. cnss_wlfw_cal_report_req_send_sync(plat_priv, cal_file_size);
  600. plat_priv->cal_time = jiffies;
  601. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  602. CNSS_CALIBRATION);
  603. } else {
  604. ret = cnss_setup_dms_mac(plat_priv);
  605. ret = cnss_bus_call_driver_probe(plat_priv);
  606. }
  607. if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  608. goto out;
  609. else if (ret)
  610. goto shutdown;
  611. cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM);
  612. return 0;
  613. shutdown:
  614. cnss_bus_dev_shutdown(plat_priv);
  615. clear_bit(CNSS_FW_READY, &plat_priv->driver_state);
  616. clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  617. out:
  618. return ret;
  619. }
  620. static char *cnss_driver_event_to_str(enum cnss_driver_event_type type)
  621. {
  622. switch (type) {
  623. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  624. return "SERVER_ARRIVE";
  625. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  626. return "SERVER_EXIT";
  627. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  628. return "REQUEST_MEM";
  629. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  630. return "FW_MEM_READY";
  631. case CNSS_DRIVER_EVENT_FW_READY:
  632. return "FW_READY";
  633. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  634. return "COLD_BOOT_CAL_START";
  635. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  636. return "COLD_BOOT_CAL_DONE";
  637. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  638. return "REGISTER_DRIVER";
  639. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  640. return "UNREGISTER_DRIVER";
  641. case CNSS_DRIVER_EVENT_RECOVERY:
  642. return "RECOVERY";
  643. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  644. return "FORCE_FW_ASSERT";
  645. case CNSS_DRIVER_EVENT_POWER_UP:
  646. return "POWER_UP";
  647. case CNSS_DRIVER_EVENT_POWER_DOWN:
  648. return "POWER_DOWN";
  649. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  650. return "IDLE_RESTART";
  651. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  652. return "IDLE_SHUTDOWN";
  653. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  654. return "IMS_WFC_CALL_IND";
  655. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  656. return "WLFW_TWC_CFG_IND";
  657. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  658. return "QDSS_TRACE_REQ_MEM";
  659. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  660. return "FW_MEM_FILE_SAVE";
  661. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  662. return "QDSS_TRACE_FREE";
  663. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  664. return "QDSS_TRACE_REQ_DATA";
  665. case CNSS_DRIVER_EVENT_MAX:
  666. return "EVENT_MAX";
  667. }
  668. return "UNKNOWN";
  669. };
  670. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  671. enum cnss_driver_event_type type,
  672. u32 flags, void *data)
  673. {
  674. struct cnss_driver_event *event;
  675. unsigned long irq_flags;
  676. int gfp = GFP_KERNEL;
  677. int ret = 0;
  678. if (!plat_priv)
  679. return -ENODEV;
  680. cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n",
  681. cnss_driver_event_to_str(type), type,
  682. flags ? "-sync" : "", plat_priv->driver_state, flags);
  683. if (type >= CNSS_DRIVER_EVENT_MAX) {
  684. cnss_pr_err("Invalid Event type: %d, can't post", type);
  685. return -EINVAL;
  686. }
  687. if (in_interrupt() || irqs_disabled())
  688. gfp = GFP_ATOMIC;
  689. event = kzalloc(sizeof(*event), gfp);
  690. if (!event)
  691. return -ENOMEM;
  692. cnss_pm_stay_awake(plat_priv);
  693. event->type = type;
  694. event->data = data;
  695. init_completion(&event->complete);
  696. event->ret = CNSS_EVENT_PENDING;
  697. event->sync = !!(flags & CNSS_EVENT_SYNC);
  698. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  699. list_add_tail(&event->list, &plat_priv->event_list);
  700. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  701. queue_work(plat_priv->event_wq, &plat_priv->event_work);
  702. if (!(flags & CNSS_EVENT_SYNC))
  703. goto out;
  704. if (flags & CNSS_EVENT_UNKILLABLE)
  705. wait_for_completion(&event->complete);
  706. else if (flags & CNSS_EVENT_UNINTERRUPTIBLE)
  707. ret = wait_for_completion_killable(&event->complete);
  708. else
  709. ret = wait_for_completion_interruptible(&event->complete);
  710. cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  711. cnss_driver_event_to_str(type), type,
  712. plat_priv->driver_state, ret, event->ret);
  713. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  714. if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) {
  715. event->sync = false;
  716. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  717. ret = -EINTR;
  718. goto out;
  719. }
  720. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  721. ret = event->ret;
  722. kfree(event);
  723. out:
  724. cnss_pm_relax(plat_priv);
  725. return ret;
  726. }
  727. /**
  728. * cnss_get_timeout - Get timeout for corresponding type.
  729. * @plat_priv: Pointer to platform driver context.
  730. * @cnss_timeout_type: Timeout type.
  731. *
  732. * Return: Timeout in milliseconds.
  733. */
  734. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  735. enum cnss_timeout_type timeout_type)
  736. {
  737. unsigned int qmi_timeout = cnss_get_qmi_timeout(plat_priv);
  738. switch (timeout_type) {
  739. case CNSS_TIMEOUT_QMI:
  740. return qmi_timeout;
  741. case CNSS_TIMEOUT_POWER_UP:
  742. return (qmi_timeout << 2);
  743. case CNSS_TIMEOUT_IDLE_RESTART:
  744. /* In idle restart power up sequence, we have fw_boot_timer to
  745. * handle FW initialization failure.
  746. * It uses WLAN_MISSION_MODE_TIMEOUT, so setup 3x that time to
  747. * account for FW dump collection and FW re-initialization on
  748. * retry.
  749. */
  750. return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
  751. case CNSS_TIMEOUT_CALIBRATION:
  752. /* Similar to mission mode, in CBC if FW init fails
  753. * fw recovery is tried. Thus return 2x the CBC timeout.
  754. */
  755. return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
  756. case CNSS_TIMEOUT_WLAN_WATCHDOG:
  757. return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
  758. case CNSS_TIMEOUT_RDDM:
  759. return CNSS_RDDM_TIMEOUT_MS;
  760. case CNSS_TIMEOUT_RECOVERY:
  761. return RECOVERY_TIMEOUT;
  762. case CNSS_TIMEOUT_DAEMON_CONNECTION:
  763. return qmi_timeout + CNSS_DAEMON_CONNECT_TIMEOUT_MS;
  764. default:
  765. return qmi_timeout;
  766. }
  767. }
  768. unsigned int cnss_get_boot_timeout(struct device *dev)
  769. {
  770. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  771. if (!plat_priv) {
  772. cnss_pr_err("plat_priv is NULL\n");
  773. return 0;
  774. }
  775. return cnss_get_timeout(plat_priv, CNSS_TIMEOUT_QMI);
  776. }
  777. EXPORT_SYMBOL(cnss_get_boot_timeout);
  778. int cnss_power_up(struct device *dev)
  779. {
  780. int ret = 0;
  781. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  782. unsigned int timeout;
  783. if (!plat_priv) {
  784. cnss_pr_err("plat_priv is NULL\n");
  785. return -ENODEV;
  786. }
  787. cnss_pr_dbg("Powering up device\n");
  788. ret = cnss_driver_event_post(plat_priv,
  789. CNSS_DRIVER_EVENT_POWER_UP,
  790. CNSS_EVENT_SYNC, NULL);
  791. if (ret)
  792. goto out;
  793. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  794. goto out;
  795. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_POWER_UP);
  796. reinit_completion(&plat_priv->power_up_complete);
  797. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  798. msecs_to_jiffies(timeout));
  799. if (!ret) {
  800. cnss_pr_err("Timeout (%ums) waiting for power up to complete\n",
  801. timeout);
  802. ret = -EAGAIN;
  803. goto out;
  804. }
  805. return 0;
  806. out:
  807. return ret;
  808. }
  809. EXPORT_SYMBOL(cnss_power_up);
  810. int cnss_power_down(struct device *dev)
  811. {
  812. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  813. if (!plat_priv) {
  814. cnss_pr_err("plat_priv is NULL\n");
  815. return -ENODEV;
  816. }
  817. cnss_pr_dbg("Powering down device\n");
  818. return cnss_driver_event_post(plat_priv,
  819. CNSS_DRIVER_EVENT_POWER_DOWN,
  820. CNSS_EVENT_SYNC, NULL);
  821. }
  822. EXPORT_SYMBOL(cnss_power_down);
  823. int cnss_idle_restart(struct device *dev)
  824. {
  825. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  826. unsigned int timeout;
  827. int ret = 0;
  828. if (!plat_priv) {
  829. cnss_pr_err("plat_priv is NULL\n");
  830. return -ENODEV;
  831. }
  832. if (!mutex_trylock(&plat_priv->driver_ops_lock)) {
  833. cnss_pr_dbg("Another driver operation is in progress, ignore idle restart\n");
  834. return -EBUSY;
  835. }
  836. cnss_pr_dbg("Doing idle restart\n");
  837. reinit_completion(&plat_priv->power_up_complete);
  838. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  839. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  840. ret = -EINVAL;
  841. goto out;
  842. }
  843. ret = cnss_driver_event_post(plat_priv,
  844. CNSS_DRIVER_EVENT_IDLE_RESTART,
  845. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  846. if (ret)
  847. goto out;
  848. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  849. ret = cnss_bus_call_driver_probe(plat_priv);
  850. goto out;
  851. }
  852. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_IDLE_RESTART);
  853. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  854. msecs_to_jiffies(timeout));
  855. if (plat_priv->power_up_error) {
  856. ret = plat_priv->power_up_error;
  857. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  858. cnss_pr_dbg("Power up error:%d, exiting\n",
  859. plat_priv->power_up_error);
  860. goto out;
  861. }
  862. if (!ret) {
  863. /* This exception occurs after attempting retry of FW recovery.
  864. * Thus we can safely power off the device.
  865. */
  866. cnss_fatal_err("Timeout (%ums) waiting for idle restart to complete\n",
  867. timeout);
  868. ret = -ETIMEDOUT;
  869. cnss_power_down(dev);
  870. CNSS_ASSERT(0);
  871. goto out;
  872. }
  873. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  874. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  875. del_timer(&plat_priv->fw_boot_timer);
  876. ret = -EINVAL;
  877. goto out;
  878. }
  879. mutex_unlock(&plat_priv->driver_ops_lock);
  880. return 0;
  881. out:
  882. mutex_unlock(&plat_priv->driver_ops_lock);
  883. return ret;
  884. }
  885. EXPORT_SYMBOL(cnss_idle_restart);
  886. int cnss_idle_shutdown(struct device *dev)
  887. {
  888. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  889. unsigned int timeout;
  890. int ret;
  891. if (!plat_priv) {
  892. cnss_pr_err("plat_priv is NULL\n");
  893. return -ENODEV;
  894. }
  895. if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) {
  896. cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n");
  897. return -EAGAIN;
  898. }
  899. cnss_pr_dbg("Doing idle shutdown\n");
  900. if (!test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) &&
  901. !test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  902. goto skip_wait;
  903. reinit_completion(&plat_priv->recovery_complete);
  904. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY);
  905. ret = wait_for_completion_timeout(&plat_priv->recovery_complete,
  906. msecs_to_jiffies(timeout));
  907. if (!ret) {
  908. cnss_pr_err("Timeout (%ums) waiting for recovery to complete\n",
  909. timeout);
  910. CNSS_ASSERT(0);
  911. }
  912. skip_wait:
  913. return cnss_driver_event_post(plat_priv,
  914. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  915. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  916. }
  917. EXPORT_SYMBOL(cnss_idle_shutdown);
  918. static int cnss_get_resources(struct cnss_plat_data *plat_priv)
  919. {
  920. int ret = 0;
  921. ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
  922. if (ret) {
  923. cnss_pr_err("Failed to get vreg, err = %d\n", ret);
  924. goto out;
  925. }
  926. ret = cnss_get_clk(plat_priv);
  927. if (ret) {
  928. cnss_pr_err("Failed to get clocks, err = %d\n", ret);
  929. goto put_vreg;
  930. }
  931. ret = cnss_get_pinctrl(plat_priv);
  932. if (ret) {
  933. cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
  934. goto put_clk;
  935. }
  936. return 0;
  937. put_clk:
  938. cnss_put_clk(plat_priv);
  939. put_vreg:
  940. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  941. out:
  942. return ret;
  943. }
  944. static void cnss_put_resources(struct cnss_plat_data *plat_priv)
  945. {
  946. cnss_put_clk(plat_priv);
  947. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  948. }
  949. #if IS_ENABLED(CONFIG_ESOC) && IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  950. static int cnss_modem_notifier_nb(struct notifier_block *nb,
  951. unsigned long code,
  952. void *ss_handle)
  953. {
  954. struct cnss_plat_data *plat_priv =
  955. container_of(nb, struct cnss_plat_data, modem_nb);
  956. struct cnss_esoc_info *esoc_info;
  957. cnss_pr_dbg("Modem notifier: event %lu\n", code);
  958. if (!plat_priv)
  959. return NOTIFY_DONE;
  960. esoc_info = &plat_priv->esoc_info;
  961. if (code == SUBSYS_AFTER_POWERUP)
  962. esoc_info->modem_current_status = 1;
  963. else if (code == SUBSYS_BEFORE_SHUTDOWN)
  964. esoc_info->modem_current_status = 0;
  965. else
  966. return NOTIFY_DONE;
  967. if (!cnss_bus_call_driver_modem_status(plat_priv,
  968. esoc_info->modem_current_status))
  969. return NOTIFY_DONE;
  970. return NOTIFY_OK;
  971. }
  972. static int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  973. {
  974. int ret = 0;
  975. struct device *dev;
  976. struct cnss_esoc_info *esoc_info;
  977. struct esoc_desc *esoc_desc;
  978. const char *client_desc;
  979. dev = &plat_priv->plat_dev->dev;
  980. esoc_info = &plat_priv->esoc_info;
  981. esoc_info->notify_modem_status =
  982. of_property_read_bool(dev->of_node,
  983. "qcom,notify-modem-status");
  984. if (!esoc_info->notify_modem_status)
  985. goto out;
  986. ret = of_property_read_string_index(dev->of_node, "esoc-names", 0,
  987. &client_desc);
  988. if (ret) {
  989. cnss_pr_dbg("esoc-names is not defined in DT, skip!\n");
  990. } else {
  991. esoc_desc = devm_register_esoc_client(dev, client_desc);
  992. if (IS_ERR_OR_NULL(esoc_desc)) {
  993. ret = PTR_RET(esoc_desc);
  994. cnss_pr_err("Failed to register esoc_desc, err = %d\n",
  995. ret);
  996. goto out;
  997. }
  998. esoc_info->esoc_desc = esoc_desc;
  999. }
  1000. plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb;
  1001. esoc_info->modem_current_status = 0;
  1002. esoc_info->modem_notify_handler =
  1003. subsys_notif_register_notifier(esoc_info->esoc_desc ?
  1004. esoc_info->esoc_desc->name :
  1005. "modem", &plat_priv->modem_nb);
  1006. if (IS_ERR(esoc_info->modem_notify_handler)) {
  1007. ret = PTR_ERR(esoc_info->modem_notify_handler);
  1008. cnss_pr_err("Failed to register esoc notifier, err = %d\n",
  1009. ret);
  1010. goto unreg_esoc;
  1011. }
  1012. return 0;
  1013. unreg_esoc:
  1014. if (esoc_info->esoc_desc)
  1015. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1016. out:
  1017. return ret;
  1018. }
  1019. static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv)
  1020. {
  1021. struct device *dev;
  1022. struct cnss_esoc_info *esoc_info;
  1023. dev = &plat_priv->plat_dev->dev;
  1024. esoc_info = &plat_priv->esoc_info;
  1025. if (esoc_info->notify_modem_status)
  1026. subsys_notif_unregister_notifier
  1027. (esoc_info->modem_notify_handler,
  1028. &plat_priv->modem_nb);
  1029. if (esoc_info->esoc_desc)
  1030. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1031. }
  1032. #else
  1033. static inline int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1034. {
  1035. return 0;
  1036. }
  1037. static inline void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) {}
  1038. #endif
  1039. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1040. {
  1041. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1042. int ret = 0;
  1043. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1044. return 0;
  1045. enable_irq(sol_gpio->dev_sol_irq);
  1046. ret = enable_irq_wake(sol_gpio->dev_sol_irq);
  1047. if (ret)
  1048. cnss_pr_err("Failed to enable device SOL as wake IRQ, err = %d\n",
  1049. ret);
  1050. return ret;
  1051. }
  1052. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1053. {
  1054. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1055. int ret = 0;
  1056. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1057. return 0;
  1058. ret = disable_irq_wake(sol_gpio->dev_sol_irq);
  1059. if (ret)
  1060. cnss_pr_err("Failed to disable device SOL as wake IRQ, err = %d\n",
  1061. ret);
  1062. disable_irq(sol_gpio->dev_sol_irq);
  1063. return ret;
  1064. }
  1065. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv)
  1066. {
  1067. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1068. if (sol_gpio->dev_sol_gpio < 0)
  1069. return -EINVAL;
  1070. return gpio_get_value(sol_gpio->dev_sol_gpio);
  1071. }
  1072. static irqreturn_t cnss_dev_sol_handler(int irq, void *data)
  1073. {
  1074. struct cnss_plat_data *plat_priv = data;
  1075. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1076. sol_gpio->dev_sol_counter++;
  1077. cnss_pr_dbg("WLAN device SOL IRQ (%u) is asserted #%u\n",
  1078. irq, sol_gpio->dev_sol_counter);
  1079. /* Make sure abort current suspend */
  1080. cnss_pm_stay_awake(plat_priv);
  1081. cnss_pm_relax(plat_priv);
  1082. pm_system_wakeup();
  1083. cnss_bus_handle_dev_sol_irq(plat_priv);
  1084. return IRQ_HANDLED;
  1085. }
  1086. static int cnss_init_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1087. {
  1088. struct device *dev = &plat_priv->plat_dev->dev;
  1089. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1090. int ret = 0;
  1091. sol_gpio->dev_sol_gpio = of_get_named_gpio(dev->of_node,
  1092. "wlan-dev-sol-gpio", 0);
  1093. if (sol_gpio->dev_sol_gpio < 0)
  1094. goto out;
  1095. cnss_pr_dbg("Get device SOL GPIO (%d) from device node\n",
  1096. sol_gpio->dev_sol_gpio);
  1097. ret = gpio_request(sol_gpio->dev_sol_gpio, "wlan_dev_sol_gpio");
  1098. if (ret) {
  1099. cnss_pr_err("Failed to request device SOL GPIO, err = %d\n",
  1100. ret);
  1101. goto out;
  1102. }
  1103. gpio_direction_input(sol_gpio->dev_sol_gpio);
  1104. sol_gpio->dev_sol_irq = gpio_to_irq(sol_gpio->dev_sol_gpio);
  1105. ret = request_irq(sol_gpio->dev_sol_irq, cnss_dev_sol_handler,
  1106. IRQF_TRIGGER_FALLING, "wlan_dev_sol_irq", plat_priv);
  1107. if (ret) {
  1108. cnss_pr_err("Failed to request device SOL IRQ, err = %d\n", ret);
  1109. goto free_gpio;
  1110. }
  1111. return 0;
  1112. free_gpio:
  1113. gpio_free(sol_gpio->dev_sol_gpio);
  1114. out:
  1115. return ret;
  1116. }
  1117. static void cnss_deinit_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1118. {
  1119. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1120. if (sol_gpio->dev_sol_gpio < 0)
  1121. return;
  1122. free_irq(sol_gpio->dev_sol_irq, plat_priv);
  1123. gpio_free(sol_gpio->dev_sol_gpio);
  1124. }
  1125. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value)
  1126. {
  1127. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1128. if (sol_gpio->host_sol_gpio < 0)
  1129. return -EINVAL;
  1130. if (value)
  1131. cnss_pr_dbg("Assert host SOL GPIO\n");
  1132. gpio_set_value(sol_gpio->host_sol_gpio, value);
  1133. return 0;
  1134. }
  1135. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv)
  1136. {
  1137. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1138. if (sol_gpio->host_sol_gpio < 0)
  1139. return -EINVAL;
  1140. return gpio_get_value(sol_gpio->host_sol_gpio);
  1141. }
  1142. static int cnss_init_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1143. {
  1144. struct device *dev = &plat_priv->plat_dev->dev;
  1145. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1146. int ret = 0;
  1147. sol_gpio->host_sol_gpio = of_get_named_gpio(dev->of_node,
  1148. "wlan-host-sol-gpio", 0);
  1149. if (sol_gpio->host_sol_gpio < 0)
  1150. goto out;
  1151. cnss_pr_dbg("Get host SOL GPIO (%d) from device node\n",
  1152. sol_gpio->host_sol_gpio);
  1153. ret = gpio_request(sol_gpio->host_sol_gpio, "wlan_host_sol_gpio");
  1154. if (ret) {
  1155. cnss_pr_err("Failed to request host SOL GPIO, err = %d\n",
  1156. ret);
  1157. goto out;
  1158. }
  1159. gpio_direction_output(sol_gpio->host_sol_gpio, 0);
  1160. return 0;
  1161. out:
  1162. return ret;
  1163. }
  1164. static void cnss_deinit_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1165. {
  1166. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1167. if (sol_gpio->host_sol_gpio < 0)
  1168. return;
  1169. gpio_free(sol_gpio->host_sol_gpio);
  1170. }
  1171. static int cnss_init_sol_gpio(struct cnss_plat_data *plat_priv)
  1172. {
  1173. int ret;
  1174. ret = cnss_init_dev_sol_gpio(plat_priv);
  1175. if (ret)
  1176. goto out;
  1177. ret = cnss_init_host_sol_gpio(plat_priv);
  1178. if (ret)
  1179. goto deinit_dev_sol;
  1180. return 0;
  1181. deinit_dev_sol:
  1182. cnss_deinit_dev_sol_gpio(plat_priv);
  1183. out:
  1184. return ret;
  1185. }
  1186. static void cnss_deinit_sol_gpio(struct cnss_plat_data *plat_priv)
  1187. {
  1188. cnss_deinit_host_sol_gpio(plat_priv);
  1189. cnss_deinit_dev_sol_gpio(plat_priv);
  1190. }
  1191. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1192. static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc)
  1193. {
  1194. struct cnss_plat_data *plat_priv;
  1195. int ret = 0;
  1196. if (!subsys_desc->dev) {
  1197. cnss_pr_err("dev from subsys_desc is NULL\n");
  1198. return -ENODEV;
  1199. }
  1200. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1201. if (!plat_priv) {
  1202. cnss_pr_err("plat_priv is NULL\n");
  1203. return -ENODEV;
  1204. }
  1205. if (!plat_priv->driver_state) {
  1206. cnss_pr_dbg("Powerup is ignored\n");
  1207. return 0;
  1208. }
  1209. ret = cnss_bus_dev_powerup(plat_priv);
  1210. if (ret)
  1211. __pm_relax(plat_priv->recovery_ws);
  1212. return ret;
  1213. }
  1214. static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc,
  1215. bool force_stop)
  1216. {
  1217. struct cnss_plat_data *plat_priv;
  1218. if (!subsys_desc->dev) {
  1219. cnss_pr_err("dev from subsys_desc is NULL\n");
  1220. return -ENODEV;
  1221. }
  1222. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1223. if (!plat_priv) {
  1224. cnss_pr_err("plat_priv is NULL\n");
  1225. return -ENODEV;
  1226. }
  1227. if (!plat_priv->driver_state) {
  1228. cnss_pr_dbg("shutdown is ignored\n");
  1229. return 0;
  1230. }
  1231. return cnss_bus_dev_shutdown(plat_priv);
  1232. }
  1233. void cnss_device_crashed(struct device *dev)
  1234. {
  1235. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1236. struct cnss_subsys_info *subsys_info;
  1237. if (!plat_priv)
  1238. return;
  1239. subsys_info = &plat_priv->subsys_info;
  1240. if (subsys_info->subsys_device) {
  1241. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1242. subsys_set_crash_status(subsys_info->subsys_device, true);
  1243. subsystem_restart_dev(subsys_info->subsys_device);
  1244. }
  1245. }
  1246. EXPORT_SYMBOL(cnss_device_crashed);
  1247. static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc)
  1248. {
  1249. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1250. if (!plat_priv) {
  1251. cnss_pr_err("plat_priv is NULL\n");
  1252. return;
  1253. }
  1254. cnss_bus_dev_crash_shutdown(plat_priv);
  1255. }
  1256. static int cnss_subsys_ramdump(int enable,
  1257. const struct subsys_desc *subsys_desc)
  1258. {
  1259. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1260. if (!plat_priv) {
  1261. cnss_pr_err("plat_priv is NULL\n");
  1262. return -ENODEV;
  1263. }
  1264. if (!enable)
  1265. return 0;
  1266. return cnss_bus_dev_ramdump(plat_priv);
  1267. }
  1268. static void cnss_recovery_work_handler(struct work_struct *work)
  1269. {
  1270. }
  1271. #else
  1272. static void cnss_recovery_work_handler(struct work_struct *work)
  1273. {
  1274. int ret;
  1275. struct cnss_plat_data *plat_priv =
  1276. container_of(work, struct cnss_plat_data, recovery_work);
  1277. if (!plat_priv->recovery_enabled)
  1278. panic("subsys-restart: Resetting the SoC wlan crashed\n");
  1279. cnss_bus_dev_shutdown(plat_priv);
  1280. cnss_bus_dev_ramdump(plat_priv);
  1281. msleep(POWER_RESET_MIN_DELAY_MS);
  1282. ret = cnss_bus_dev_powerup(plat_priv);
  1283. if (ret)
  1284. __pm_relax(plat_priv->recovery_ws);
  1285. return;
  1286. }
  1287. void cnss_device_crashed(struct device *dev)
  1288. {
  1289. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1290. if (!plat_priv)
  1291. return;
  1292. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1293. schedule_work(&plat_priv->recovery_work);
  1294. }
  1295. EXPORT_SYMBOL(cnss_device_crashed);
  1296. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  1297. void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size)
  1298. {
  1299. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1300. struct cnss_ramdump_info *ramdump_info;
  1301. if (!plat_priv)
  1302. return NULL;
  1303. ramdump_info = &plat_priv->ramdump_info;
  1304. *size = ramdump_info->ramdump_size;
  1305. return ramdump_info->ramdump_va;
  1306. }
  1307. EXPORT_SYMBOL(cnss_get_virt_ramdump_mem);
  1308. static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason)
  1309. {
  1310. switch (reason) {
  1311. case CNSS_REASON_DEFAULT:
  1312. return "DEFAULT";
  1313. case CNSS_REASON_LINK_DOWN:
  1314. return "LINK_DOWN";
  1315. case CNSS_REASON_RDDM:
  1316. return "RDDM";
  1317. case CNSS_REASON_TIMEOUT:
  1318. return "TIMEOUT";
  1319. }
  1320. return "UNKNOWN";
  1321. };
  1322. static int cnss_do_recovery(struct cnss_plat_data *plat_priv,
  1323. enum cnss_recovery_reason reason)
  1324. {
  1325. plat_priv->recovery_count++;
  1326. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1327. goto self_recovery;
  1328. if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) {
  1329. cnss_pr_dbg("Skip device recovery\n");
  1330. return 0;
  1331. }
  1332. /* FW recovery sequence has multiple steps and firmware load requires
  1333. * linux PM in awake state. Thus hold the cnss wake source until
  1334. * WLAN MISSION enabled. CNSS_TIMEOUT_RECOVERY option should cover all
  1335. * time taken in this process.
  1336. */
  1337. pm_wakeup_ws_event(plat_priv->recovery_ws,
  1338. cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY),
  1339. true);
  1340. switch (reason) {
  1341. case CNSS_REASON_LINK_DOWN:
  1342. if (!cnss_bus_check_link_status(plat_priv)) {
  1343. cnss_pr_dbg("Skip link down recovery as link is already up\n");
  1344. return 0;
  1345. }
  1346. if (test_bit(LINK_DOWN_SELF_RECOVERY,
  1347. &plat_priv->ctrl_params.quirks))
  1348. goto self_recovery;
  1349. if (!cnss_bus_recover_link_down(plat_priv)) {
  1350. /* clear recovery bit here to avoid skipping
  1351. * the recovery work for RDDM later
  1352. */
  1353. clear_bit(CNSS_DRIVER_RECOVERY,
  1354. &plat_priv->driver_state);
  1355. return 0;
  1356. }
  1357. break;
  1358. case CNSS_REASON_RDDM:
  1359. cnss_bus_collect_dump_info(plat_priv, false);
  1360. break;
  1361. case CNSS_REASON_DEFAULT:
  1362. case CNSS_REASON_TIMEOUT:
  1363. break;
  1364. default:
  1365. cnss_pr_err("Unsupported recovery reason: %s(%d)\n",
  1366. cnss_recovery_reason_to_str(reason), reason);
  1367. break;
  1368. }
  1369. cnss_bus_device_crashed(plat_priv);
  1370. return 0;
  1371. self_recovery:
  1372. cnss_pr_dbg("Going for self recovery\n");
  1373. cnss_bus_dev_shutdown(plat_priv);
  1374. if (test_bit(LINK_DOWN_SELF_RECOVERY, &plat_priv->ctrl_params.quirks))
  1375. clear_bit(LINK_DOWN_SELF_RECOVERY,
  1376. &plat_priv->ctrl_params.quirks);
  1377. cnss_bus_dev_powerup(plat_priv);
  1378. return 0;
  1379. }
  1380. static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
  1381. void *data)
  1382. {
  1383. struct cnss_recovery_data *recovery_data = data;
  1384. int ret = 0;
  1385. cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n",
  1386. cnss_recovery_reason_to_str(recovery_data->reason),
  1387. recovery_data->reason);
  1388. if (!plat_priv->driver_state) {
  1389. cnss_pr_err("Improper driver state, ignore recovery\n");
  1390. ret = -EINVAL;
  1391. goto out;
  1392. }
  1393. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1394. cnss_pr_err("Reboot is in progress, ignore recovery\n");
  1395. ret = -EINVAL;
  1396. goto out;
  1397. }
  1398. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1399. cnss_pr_err("Recovery is already in progress\n");
  1400. CNSS_ASSERT(0);
  1401. ret = -EINVAL;
  1402. goto out;
  1403. }
  1404. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1405. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1406. cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n");
  1407. ret = -EINVAL;
  1408. goto out;
  1409. }
  1410. switch (plat_priv->device_id) {
  1411. case QCA6174_DEVICE_ID:
  1412. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1413. test_bit(CNSS_DRIVER_IDLE_RESTART,
  1414. &plat_priv->driver_state)) {
  1415. cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n");
  1416. ret = -EINVAL;
  1417. goto out;
  1418. }
  1419. break;
  1420. default:
  1421. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1422. set_bit(CNSS_FW_BOOT_RECOVERY,
  1423. &plat_priv->driver_state);
  1424. }
  1425. break;
  1426. }
  1427. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1428. ret = cnss_do_recovery(plat_priv, recovery_data->reason);
  1429. out:
  1430. kfree(data);
  1431. return ret;
  1432. }
  1433. int cnss_self_recovery(struct device *dev,
  1434. enum cnss_recovery_reason reason)
  1435. {
  1436. cnss_schedule_recovery(dev, reason);
  1437. return 0;
  1438. }
  1439. EXPORT_SYMBOL(cnss_self_recovery);
  1440. void cnss_schedule_recovery(struct device *dev,
  1441. enum cnss_recovery_reason reason)
  1442. {
  1443. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1444. struct cnss_recovery_data *data;
  1445. int gfp = GFP_KERNEL;
  1446. if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1447. cnss_bus_update_status(plat_priv, CNSS_FW_DOWN);
  1448. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1449. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1450. cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n");
  1451. return;
  1452. }
  1453. if (in_interrupt() || irqs_disabled())
  1454. gfp = GFP_ATOMIC;
  1455. data = kzalloc(sizeof(*data), gfp);
  1456. if (!data)
  1457. return;
  1458. data->reason = reason;
  1459. cnss_driver_event_post(plat_priv,
  1460. CNSS_DRIVER_EVENT_RECOVERY,
  1461. 0, data);
  1462. }
  1463. EXPORT_SYMBOL(cnss_schedule_recovery);
  1464. int cnss_force_fw_assert(struct device *dev)
  1465. {
  1466. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1467. if (!plat_priv) {
  1468. cnss_pr_err("plat_priv is NULL\n");
  1469. return -ENODEV;
  1470. }
  1471. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1472. cnss_pr_info("Forced FW assert is not supported\n");
  1473. return -EOPNOTSUPP;
  1474. }
  1475. if (cnss_bus_is_device_down(plat_priv)) {
  1476. cnss_pr_info("Device is already in bad state, ignore force assert\n");
  1477. return 0;
  1478. }
  1479. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1480. cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n");
  1481. return 0;
  1482. }
  1483. if (in_interrupt() || irqs_disabled())
  1484. cnss_driver_event_post(plat_priv,
  1485. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  1486. 0, NULL);
  1487. else
  1488. cnss_bus_force_fw_assert_hdlr(plat_priv);
  1489. return 0;
  1490. }
  1491. EXPORT_SYMBOL(cnss_force_fw_assert);
  1492. int cnss_force_collect_rddm(struct device *dev)
  1493. {
  1494. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1495. unsigned int timeout;
  1496. int ret = 0;
  1497. if (!plat_priv) {
  1498. cnss_pr_err("plat_priv is NULL\n");
  1499. return -ENODEV;
  1500. }
  1501. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1502. cnss_pr_info("Force collect rddm is not supported\n");
  1503. return -EOPNOTSUPP;
  1504. }
  1505. if (cnss_bus_is_device_down(plat_priv)) {
  1506. cnss_pr_info("Device is already in bad state, wait to collect rddm\n");
  1507. goto wait_rddm;
  1508. }
  1509. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1510. cnss_pr_info("Recovery is already in progress, wait to collect rddm\n");
  1511. goto wait_rddm;
  1512. }
  1513. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1514. test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1515. test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) ||
  1516. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1517. cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n");
  1518. return 0;
  1519. }
  1520. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1521. if (ret)
  1522. return ret;
  1523. wait_rddm:
  1524. reinit_completion(&plat_priv->rddm_complete);
  1525. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RDDM);
  1526. ret = wait_for_completion_timeout(&plat_priv->rddm_complete,
  1527. msecs_to_jiffies(timeout));
  1528. if (!ret) {
  1529. cnss_pr_err("Timeout (%ums) waiting for RDDM to complete\n",
  1530. timeout);
  1531. ret = -ETIMEDOUT;
  1532. } else if (ret > 0) {
  1533. ret = 0;
  1534. }
  1535. return ret;
  1536. }
  1537. EXPORT_SYMBOL(cnss_force_collect_rddm);
  1538. int cnss_qmi_send_get(struct device *dev)
  1539. {
  1540. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1541. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1542. return 0;
  1543. return cnss_bus_qmi_send_get(plat_priv);
  1544. }
  1545. EXPORT_SYMBOL(cnss_qmi_send_get);
  1546. int cnss_qmi_send_put(struct device *dev)
  1547. {
  1548. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1549. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1550. return 0;
  1551. return cnss_bus_qmi_send_put(plat_priv);
  1552. }
  1553. EXPORT_SYMBOL(cnss_qmi_send_put);
  1554. int cnss_qmi_send(struct device *dev, int type, void *cmd,
  1555. int cmd_len, void *cb_ctx,
  1556. int (*cb)(void *ctx, void *event, int event_len))
  1557. {
  1558. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1559. int ret;
  1560. if (!plat_priv)
  1561. return -ENODEV;
  1562. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1563. return -EINVAL;
  1564. plat_priv->get_info_cb = cb;
  1565. plat_priv->get_info_cb_ctx = cb_ctx;
  1566. ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
  1567. if (ret) {
  1568. plat_priv->get_info_cb = NULL;
  1569. plat_priv->get_info_cb_ctx = NULL;
  1570. }
  1571. return ret;
  1572. }
  1573. EXPORT_SYMBOL(cnss_qmi_send);
  1574. static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
  1575. {
  1576. int ret = 0;
  1577. u32 retry = 0, timeout;
  1578. if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
  1579. cnss_pr_dbg("Calibration complete. Ignore calibration req\n");
  1580. goto out;
  1581. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  1582. cnss_pr_dbg("Calibration in progress. Ignore new calibration req\n");
  1583. goto out;
  1584. }
  1585. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1586. test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state) ||
  1587. test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1588. cnss_pr_err("WLAN in mission mode before cold boot calibration\n");
  1589. CNSS_ASSERT(0);
  1590. return -EINVAL;
  1591. }
  1592. while (retry++ < CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1593. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  1594. break;
  1595. msleep(CNSS_CAL_START_PROBE_WAIT_MS);
  1596. if (retry == CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1597. cnss_pr_err("Calibration start failed as PCI probe not complete\n");
  1598. CNSS_ASSERT(0);
  1599. ret = -EINVAL;
  1600. goto mark_cal_fail;
  1601. }
  1602. }
  1603. set_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1604. if (test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state)) {
  1605. timeout = cnss_get_timeout(plat_priv,
  1606. CNSS_TIMEOUT_CALIBRATION);
  1607. cnss_pr_dbg("Restarting calibration %ds timeout\n",
  1608. timeout / 1000);
  1609. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1610. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1611. msecs_to_jiffies(timeout));
  1612. }
  1613. reinit_completion(&plat_priv->cal_complete);
  1614. ret = cnss_bus_dev_powerup(plat_priv);
  1615. mark_cal_fail:
  1616. if (ret) {
  1617. complete(&plat_priv->cal_complete);
  1618. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1619. /* Set CBC done in driver state to mark attempt and note error
  1620. * since calibration cannot be retried at boot.
  1621. */
  1622. plat_priv->cal_done = CNSS_CAL_FAILURE;
  1623. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1624. }
  1625. out:
  1626. return ret;
  1627. }
  1628. static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
  1629. void *data)
  1630. {
  1631. struct cnss_cal_info *cal_info = data;
  1632. if (!test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state) ||
  1633. test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state))
  1634. goto out;
  1635. switch (cal_info->cal_status) {
  1636. case CNSS_CAL_DONE:
  1637. cnss_pr_dbg("Calibration completed successfully\n");
  1638. plat_priv->cal_done = true;
  1639. break;
  1640. case CNSS_CAL_TIMEOUT:
  1641. case CNSS_CAL_FAILURE:
  1642. cnss_pr_dbg("Calibration failed. Status: %d, force shutdown\n",
  1643. cal_info->cal_status);
  1644. break;
  1645. default:
  1646. cnss_pr_err("Unknown calibration status: %u\n",
  1647. cal_info->cal_status);
  1648. break;
  1649. }
  1650. cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  1651. cnss_bus_free_qdss_mem(plat_priv);
  1652. cnss_release_antenna_sharing(plat_priv);
  1653. cnss_bus_dev_shutdown(plat_priv);
  1654. msleep(POWER_RESET_MIN_DELAY_MS);
  1655. complete(&plat_priv->cal_complete);
  1656. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1657. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1658. if (cal_info->cal_status == CNSS_CAL_DONE) {
  1659. cnss_cal_mem_upload_to_file(plat_priv);
  1660. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  1661. goto out;
  1662. cnss_pr_dbg("Schedule WLAN driver load\n");
  1663. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1664. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1665. 0);
  1666. }
  1667. out:
  1668. kfree(data);
  1669. return 0;
  1670. }
  1671. static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv)
  1672. {
  1673. int ret;
  1674. ret = cnss_bus_dev_powerup(plat_priv);
  1675. if (ret)
  1676. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1677. return ret;
  1678. }
  1679. static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv)
  1680. {
  1681. cnss_bus_dev_shutdown(plat_priv);
  1682. return 0;
  1683. }
  1684. static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv)
  1685. {
  1686. int ret = 0;
  1687. ret = cnss_bus_alloc_qdss_mem(plat_priv);
  1688. if (ret < 0)
  1689. return ret;
  1690. return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv);
  1691. }
  1692. static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
  1693. u32 mem_seg_len, u64 pa, u32 size)
  1694. {
  1695. int i = 0;
  1696. u64 offset = 0;
  1697. void *va = NULL;
  1698. u64 local_pa;
  1699. u32 local_size;
  1700. for (i = 0; i < mem_seg_len; i++) {
  1701. local_pa = (u64)fw_mem[i].pa;
  1702. local_size = (u32)fw_mem[i].size;
  1703. if (pa == local_pa && size <= local_size) {
  1704. va = fw_mem[i].va;
  1705. break;
  1706. }
  1707. if (pa > local_pa &&
  1708. pa < local_pa + local_size &&
  1709. pa + size <= local_pa + local_size) {
  1710. offset = pa - local_pa;
  1711. va = fw_mem[i].va + offset;
  1712. break;
  1713. }
  1714. }
  1715. return va;
  1716. }
  1717. static int cnss_fw_mem_file_save_hdlr(struct cnss_plat_data *plat_priv,
  1718. void *data)
  1719. {
  1720. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1721. struct cnss_fw_mem *fw_mem_seg;
  1722. int ret = 0L;
  1723. void *va = NULL;
  1724. u32 i, fw_mem_seg_len;
  1725. switch (event_data->mem_type) {
  1726. case QMI_WLFW_MEM_TYPE_DDR_V01:
  1727. if (!plat_priv->fw_mem_seg_len)
  1728. goto invalid_mem_save;
  1729. fw_mem_seg = plat_priv->fw_mem;
  1730. fw_mem_seg_len = plat_priv->fw_mem_seg_len;
  1731. break;
  1732. case QMI_WLFW_MEM_QDSS_V01:
  1733. if (!plat_priv->qdss_mem_seg_len)
  1734. goto invalid_mem_save;
  1735. fw_mem_seg = plat_priv->qdss_mem;
  1736. fw_mem_seg_len = plat_priv->qdss_mem_seg_len;
  1737. break;
  1738. default:
  1739. goto invalid_mem_save;
  1740. }
  1741. for (i = 0; i < event_data->mem_seg_len; i++) {
  1742. va = cnss_get_fw_mem_pa_to_va(fw_mem_seg, fw_mem_seg_len,
  1743. event_data->mem_seg[i].addr,
  1744. event_data->mem_seg[i].size);
  1745. if (!va) {
  1746. cnss_pr_err("Fail to find matching va of pa %pa for mem type: %d\n",
  1747. &event_data->mem_seg[i].addr,
  1748. event_data->mem_type);
  1749. ret = -EINVAL;
  1750. break;
  1751. }
  1752. ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS,
  1753. event_data->file_name,
  1754. event_data->mem_seg[i].size);
  1755. if (ret < 0) {
  1756. cnss_pr_err("Fail to save fw mem data: %d\n",
  1757. ret);
  1758. break;
  1759. }
  1760. }
  1761. kfree(data);
  1762. return ret;
  1763. invalid_mem_save:
  1764. cnss_pr_err("FW Mem type %d not allocated. Invalid save request\n",
  1765. event_data->mem_type);
  1766. kfree(data);
  1767. return -EINVAL;
  1768. }
  1769. static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv)
  1770. {
  1771. cnss_bus_free_qdss_mem(plat_priv);
  1772. return 0;
  1773. }
  1774. static int cnss_qdss_trace_req_data_hdlr(struct cnss_plat_data *plat_priv,
  1775. void *data)
  1776. {
  1777. int ret = 0;
  1778. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1779. if (!plat_priv)
  1780. return -ENODEV;
  1781. ret = cnss_wlfw_qdss_data_send_sync(plat_priv, event_data->file_name,
  1782. event_data->total_size);
  1783. kfree(data);
  1784. return ret;
  1785. }
  1786. static void cnss_driver_event_work(struct work_struct *work)
  1787. {
  1788. struct cnss_plat_data *plat_priv =
  1789. container_of(work, struct cnss_plat_data, event_work);
  1790. struct cnss_driver_event *event;
  1791. unsigned long flags;
  1792. int ret = 0;
  1793. if (!plat_priv) {
  1794. cnss_pr_err("plat_priv is NULL!\n");
  1795. return;
  1796. }
  1797. cnss_pm_stay_awake(plat_priv);
  1798. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1799. while (!list_empty(&plat_priv->event_list)) {
  1800. event = list_first_entry(&plat_priv->event_list,
  1801. struct cnss_driver_event, list);
  1802. list_del(&event->list);
  1803. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1804. cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n",
  1805. cnss_driver_event_to_str(event->type),
  1806. event->sync ? "-sync" : "", event->type,
  1807. plat_priv->driver_state);
  1808. switch (event->type) {
  1809. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  1810. ret = cnss_wlfw_server_arrive(plat_priv, event->data);
  1811. break;
  1812. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  1813. ret = cnss_wlfw_server_exit(plat_priv);
  1814. break;
  1815. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  1816. ret = cnss_bus_alloc_fw_mem(plat_priv);
  1817. if (ret)
  1818. break;
  1819. ret = cnss_wlfw_respond_mem_send_sync(plat_priv);
  1820. break;
  1821. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  1822. ret = cnss_fw_mem_ready_hdlr(plat_priv);
  1823. break;
  1824. case CNSS_DRIVER_EVENT_FW_READY:
  1825. ret = cnss_fw_ready_hdlr(plat_priv);
  1826. break;
  1827. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  1828. ret = cnss_cold_boot_cal_start_hdlr(plat_priv);
  1829. break;
  1830. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  1831. ret = cnss_cold_boot_cal_done_hdlr(plat_priv,
  1832. event->data);
  1833. break;
  1834. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  1835. ret = cnss_bus_register_driver_hdlr(plat_priv,
  1836. event->data);
  1837. break;
  1838. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  1839. ret = cnss_bus_unregister_driver_hdlr(plat_priv);
  1840. break;
  1841. case CNSS_DRIVER_EVENT_RECOVERY:
  1842. ret = cnss_driver_recovery_hdlr(plat_priv,
  1843. event->data);
  1844. break;
  1845. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  1846. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1847. break;
  1848. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  1849. set_bit(CNSS_DRIVER_IDLE_RESTART,
  1850. &plat_priv->driver_state);
  1851. /* fall through */
  1852. case CNSS_DRIVER_EVENT_POWER_UP:
  1853. ret = cnss_power_up_hdlr(plat_priv);
  1854. break;
  1855. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  1856. set_bit(CNSS_DRIVER_IDLE_SHUTDOWN,
  1857. &plat_priv->driver_state);
  1858. /* fall through */
  1859. case CNSS_DRIVER_EVENT_POWER_DOWN:
  1860. ret = cnss_power_down_hdlr(plat_priv);
  1861. break;
  1862. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  1863. ret = cnss_process_wfc_call_ind_event(plat_priv,
  1864. event->data);
  1865. break;
  1866. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  1867. ret = cnss_process_twt_cfg_ind_event(plat_priv,
  1868. event->data);
  1869. break;
  1870. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  1871. ret = cnss_qdss_trace_req_mem_hdlr(plat_priv);
  1872. break;
  1873. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  1874. ret = cnss_fw_mem_file_save_hdlr(plat_priv,
  1875. event->data);
  1876. break;
  1877. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  1878. ret = cnss_qdss_trace_free_hdlr(plat_priv);
  1879. break;
  1880. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  1881. ret = cnss_qdss_trace_req_data_hdlr(plat_priv,
  1882. event->data);
  1883. break;
  1884. default:
  1885. cnss_pr_err("Invalid driver event type: %d",
  1886. event->type);
  1887. kfree(event);
  1888. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1889. continue;
  1890. }
  1891. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1892. if (event->sync) {
  1893. event->ret = ret;
  1894. complete(&event->complete);
  1895. continue;
  1896. }
  1897. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1898. kfree(event);
  1899. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1900. }
  1901. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1902. cnss_pm_relax(plat_priv);
  1903. }
  1904. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1905. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  1906. {
  1907. int ret = 0;
  1908. struct cnss_subsys_info *subsys_info;
  1909. subsys_info = &plat_priv->subsys_info;
  1910. subsys_info->subsys_desc.name = "wlan";
  1911. subsys_info->subsys_desc.owner = THIS_MODULE;
  1912. subsys_info->subsys_desc.powerup = cnss_subsys_powerup;
  1913. subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown;
  1914. subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump;
  1915. subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown;
  1916. subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev;
  1917. subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc);
  1918. if (IS_ERR(subsys_info->subsys_device)) {
  1919. ret = PTR_ERR(subsys_info->subsys_device);
  1920. cnss_pr_err("Failed to register subsys, err = %d\n", ret);
  1921. goto out;
  1922. }
  1923. subsys_info->subsys_handle =
  1924. subsystem_get(subsys_info->subsys_desc.name);
  1925. if (!subsys_info->subsys_handle) {
  1926. cnss_pr_err("Failed to get subsys_handle!\n");
  1927. ret = -EINVAL;
  1928. goto unregister_subsys;
  1929. } else if (IS_ERR(subsys_info->subsys_handle)) {
  1930. ret = PTR_ERR(subsys_info->subsys_handle);
  1931. cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret);
  1932. goto unregister_subsys;
  1933. }
  1934. return 0;
  1935. unregister_subsys:
  1936. subsys_unregister(subsys_info->subsys_device);
  1937. out:
  1938. return ret;
  1939. }
  1940. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  1941. {
  1942. struct cnss_subsys_info *subsys_info;
  1943. subsys_info = &plat_priv->subsys_info;
  1944. subsystem_put(subsys_info->subsys_handle);
  1945. subsys_unregister(subsys_info->subsys_device);
  1946. }
  1947. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  1948. {
  1949. struct cnss_subsys_info *subsys_info = &plat_priv->subsys_info;
  1950. return create_ramdump_device(subsys_info->subsys_desc.name,
  1951. subsys_info->subsys_desc.dev);
  1952. }
  1953. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  1954. void *ramdump_dev)
  1955. {
  1956. destroy_ramdump_device(ramdump_dev);
  1957. }
  1958. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  1959. {
  1960. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  1961. struct ramdump_segment segment;
  1962. memset(&segment, 0, sizeof(segment));
  1963. segment.v_address = (void __iomem *)ramdump_info->ramdump_va;
  1964. segment.size = ramdump_info->ramdump_size;
  1965. return qcom_ramdump(ramdump_info->ramdump_dev, &segment, 1);
  1966. }
  1967. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  1968. {
  1969. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  1970. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  1971. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  1972. struct ramdump_segment *ramdump_segs, *s;
  1973. struct cnss_dump_meta_info meta_info = {0};
  1974. int i, ret = 0;
  1975. ramdump_segs = kcalloc(dump_data->nentries + 1,
  1976. sizeof(*ramdump_segs),
  1977. GFP_KERNEL);
  1978. if (!ramdump_segs)
  1979. return -ENOMEM;
  1980. s = ramdump_segs + 1;
  1981. for (i = 0; i < dump_data->nentries; i++) {
  1982. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  1983. cnss_pr_err("Unsupported dump type: %d",
  1984. dump_seg->type);
  1985. continue;
  1986. }
  1987. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  1988. meta_info.entry[dump_seg->type].type = dump_seg->type;
  1989. meta_info.entry[dump_seg->type].entry_start = i + 1;
  1990. }
  1991. meta_info.entry[dump_seg->type].entry_num++;
  1992. s->address = dump_seg->address;
  1993. s->v_address = (void __iomem *)dump_seg->v_address;
  1994. s->size = dump_seg->size;
  1995. s++;
  1996. dump_seg++;
  1997. }
  1998. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  1999. meta_info.version = CNSS_RAMDUMP_VERSION;
  2000. meta_info.chipset = plat_priv->device_id;
  2001. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2002. ramdump_segs->v_address = (void __iomem *)(&meta_info);
  2003. ramdump_segs->size = sizeof(meta_info);
  2004. ret = qcom_elf_ramdump(info_v2->ramdump_dev, ramdump_segs,
  2005. dump_data->nentries + 1);
  2006. kfree(ramdump_segs);
  2007. return ret;
  2008. }
  2009. #else
  2010. static int cnss_panic_handler(struct notifier_block *nb, unsigned long action,
  2011. void *data)
  2012. {
  2013. struct cnss_plat_data *plat_priv =
  2014. container_of(nb, struct cnss_plat_data, panic_nb);
  2015. cnss_bus_dev_crash_shutdown(plat_priv);
  2016. return NOTIFY_DONE;
  2017. }
  2018. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2019. {
  2020. int ret;
  2021. if (!plat_priv)
  2022. return -ENODEV;
  2023. plat_priv->panic_nb.notifier_call = cnss_panic_handler;
  2024. ret = atomic_notifier_chain_register(&panic_notifier_list,
  2025. &plat_priv->panic_nb);
  2026. if (ret) {
  2027. cnss_pr_err("Failed to register panic handler\n");
  2028. return -EINVAL;
  2029. }
  2030. return 0;
  2031. }
  2032. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2033. {
  2034. int ret;
  2035. ret = atomic_notifier_chain_unregister(&panic_notifier_list,
  2036. &plat_priv->panic_nb);
  2037. if (ret)
  2038. cnss_pr_err("Failed to unregister panic handler\n");
  2039. }
  2040. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2041. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2042. {
  2043. return &plat_priv->plat_dev->dev;
  2044. }
  2045. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2046. void *ramdump_dev)
  2047. {
  2048. }
  2049. #endif
  2050. #if IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  2051. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2052. {
  2053. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2054. struct qcom_dump_segment segment;
  2055. struct list_head head;
  2056. INIT_LIST_HEAD(&head);
  2057. memset(&segment, 0, sizeof(segment));
  2058. segment.va = ramdump_info->ramdump_va;
  2059. segment.size = ramdump_info->ramdump_size;
  2060. list_add(&segment.node, &head);
  2061. return qcom_dump(&head, ramdump_info->ramdump_dev);
  2062. }
  2063. #else
  2064. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2065. {
  2066. return 0;
  2067. }
  2068. /* Using completion event inside dynamically allocated ramdump_desc
  2069. * may result a race between freeing the event after setting it to
  2070. * complete inside dev coredump free callback and the thread that is
  2071. * waiting for completion.
  2072. */
  2073. DECLARE_COMPLETION(dump_done);
  2074. #define TIMEOUT_SAVE_DUMP_MS 30000
  2075. #define SIZEOF_ELF_STRUCT(__xhdr) \
  2076. static inline size_t sizeof_elf_##__xhdr(unsigned char class) \
  2077. { \
  2078. if (class == ELFCLASS32) \
  2079. return sizeof(struct elf32_##__xhdr); \
  2080. else \
  2081. return sizeof(struct elf64_##__xhdr); \
  2082. }
  2083. SIZEOF_ELF_STRUCT(phdr)
  2084. SIZEOF_ELF_STRUCT(hdr)
  2085. #define set_xhdr_property(__xhdr, arg, class, member, value) \
  2086. do { \
  2087. if (class == ELFCLASS32) \
  2088. ((struct elf32_##__xhdr *)arg)->member = value; \
  2089. else \
  2090. ((struct elf64_##__xhdr *)arg)->member = value; \
  2091. } while (0)
  2092. #define set_ehdr_property(arg, class, member, value) \
  2093. set_xhdr_property(hdr, arg, class, member, value)
  2094. #define set_phdr_property(arg, class, member, value) \
  2095. set_xhdr_property(phdr, arg, class, member, value)
  2096. /* These replace qcom_ramdump driver APIs called from common API
  2097. * cnss_do_elf_dump() by the ones defined here.
  2098. */
  2099. #define qcom_dump_segment cnss_qcom_dump_segment
  2100. #define qcom_elf_dump cnss_qcom_elf_dump
  2101. #define dump_enabled cnss_dump_enabled
  2102. struct cnss_qcom_dump_segment {
  2103. struct list_head node;
  2104. dma_addr_t da;
  2105. void *va;
  2106. size_t size;
  2107. };
  2108. struct cnss_qcom_ramdump_desc {
  2109. void *data;
  2110. struct completion dump_done;
  2111. };
  2112. static ssize_t cnss_qcom_devcd_readv(char *buffer, loff_t offset, size_t count,
  2113. void *data, size_t datalen)
  2114. {
  2115. struct cnss_qcom_ramdump_desc *desc = data;
  2116. return memory_read_from_buffer(buffer, count, &offset, desc->data,
  2117. datalen);
  2118. }
  2119. static void cnss_qcom_devcd_freev(void *data)
  2120. {
  2121. struct cnss_qcom_ramdump_desc *desc = data;
  2122. cnss_pr_dbg("Free dump data for dev coredump\n");
  2123. complete(&dump_done);
  2124. vfree(desc->data);
  2125. kfree(desc);
  2126. }
  2127. static int cnss_qcom_devcd_dump(struct device *dev, void *data, size_t datalen,
  2128. gfp_t gfp)
  2129. {
  2130. struct cnss_qcom_ramdump_desc *desc;
  2131. unsigned int timeout = TIMEOUT_SAVE_DUMP_MS;
  2132. int ret;
  2133. desc = kmalloc(sizeof(*desc), GFP_KERNEL);
  2134. if (!desc)
  2135. return -ENOMEM;
  2136. desc->data = data;
  2137. reinit_completion(&dump_done);
  2138. dev_coredumpm(dev, NULL, desc, datalen, gfp,
  2139. cnss_qcom_devcd_readv, cnss_qcom_devcd_freev);
  2140. ret = wait_for_completion_timeout(&dump_done,
  2141. msecs_to_jiffies(timeout));
  2142. if (!ret)
  2143. cnss_pr_err("Timeout waiting (%dms) for saving dump to file system\n",
  2144. timeout);
  2145. return ret ? 0 : -ETIMEDOUT;
  2146. }
  2147. /* Since the elf32 and elf64 identification is identical apart from
  2148. * the class, use elf32 by default.
  2149. */
  2150. static void init_elf_identification(struct elf32_hdr *ehdr, unsigned char class)
  2151. {
  2152. memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
  2153. ehdr->e_ident[EI_CLASS] = class;
  2154. ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
  2155. ehdr->e_ident[EI_VERSION] = EV_CURRENT;
  2156. ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
  2157. }
  2158. int cnss_qcom_elf_dump(struct list_head *segs, struct device *dev,
  2159. unsigned char class)
  2160. {
  2161. struct cnss_qcom_dump_segment *segment;
  2162. void *phdr, *ehdr;
  2163. size_t data_size, offset;
  2164. int phnum = 0;
  2165. void *data;
  2166. void __iomem *ptr;
  2167. if (!segs || list_empty(segs))
  2168. return -EINVAL;
  2169. data_size = sizeof_elf_hdr(class);
  2170. list_for_each_entry(segment, segs, node) {
  2171. data_size += sizeof_elf_phdr(class) + segment->size;
  2172. phnum++;
  2173. }
  2174. data = vmalloc(data_size);
  2175. if (!data)
  2176. return -ENOMEM;
  2177. cnss_pr_dbg("Creating ELF file with size %d\n", data_size);
  2178. ehdr = data;
  2179. memset(ehdr, 0, sizeof_elf_hdr(class));
  2180. init_elf_identification(ehdr, class);
  2181. set_ehdr_property(ehdr, class, e_type, ET_CORE);
  2182. set_ehdr_property(ehdr, class, e_machine, EM_NONE);
  2183. set_ehdr_property(ehdr, class, e_version, EV_CURRENT);
  2184. set_ehdr_property(ehdr, class, e_phoff, sizeof_elf_hdr(class));
  2185. set_ehdr_property(ehdr, class, e_ehsize, sizeof_elf_hdr(class));
  2186. set_ehdr_property(ehdr, class, e_phentsize, sizeof_elf_phdr(class));
  2187. set_ehdr_property(ehdr, class, e_phnum, phnum);
  2188. phdr = data + sizeof_elf_hdr(class);
  2189. offset = sizeof_elf_hdr(class) + sizeof_elf_phdr(class) * phnum;
  2190. list_for_each_entry(segment, segs, node) {
  2191. memset(phdr, 0, sizeof_elf_phdr(class));
  2192. set_phdr_property(phdr, class, p_type, PT_LOAD);
  2193. set_phdr_property(phdr, class, p_offset, offset);
  2194. set_phdr_property(phdr, class, p_vaddr, segment->da);
  2195. set_phdr_property(phdr, class, p_paddr, segment->da);
  2196. set_phdr_property(phdr, class, p_filesz, segment->size);
  2197. set_phdr_property(phdr, class, p_memsz, segment->size);
  2198. set_phdr_property(phdr, class, p_flags, PF_R | PF_W | PF_X);
  2199. set_phdr_property(phdr, class, p_align, 0);
  2200. if (segment->va) {
  2201. memcpy(data + offset, segment->va, segment->size);
  2202. } else {
  2203. ptr = devm_ioremap(dev, segment->da, segment->size);
  2204. if (!ptr) {
  2205. cnss_pr_err("Invalid coredump segment (%pad, %zu)\n",
  2206. &segment->da, segment->size);
  2207. memset(data + offset, 0xff, segment->size);
  2208. } else {
  2209. memcpy_fromio(data + offset, ptr,
  2210. segment->size);
  2211. }
  2212. }
  2213. offset += segment->size;
  2214. phdr += sizeof_elf_phdr(class);
  2215. }
  2216. return cnss_qcom_devcd_dump(dev, data, data_size, GFP_KERNEL);
  2217. }
  2218. /* Saving dump to file system is always needed in this case. */
  2219. static bool cnss_dump_enabled(void)
  2220. {
  2221. return true;
  2222. }
  2223. #endif /* CONFIG_QCOM_RAMDUMP */
  2224. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2225. {
  2226. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2227. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2228. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2229. struct qcom_dump_segment *seg;
  2230. struct cnss_dump_meta_info meta_info = {0};
  2231. struct list_head head;
  2232. int i, ret = 0;
  2233. if (!dump_enabled()) {
  2234. cnss_pr_info("Dump collection is not enabled\n");
  2235. return ret;
  2236. }
  2237. INIT_LIST_HEAD(&head);
  2238. for (i = 0; i < dump_data->nentries; i++) {
  2239. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2240. cnss_pr_err("Unsupported dump type: %d",
  2241. dump_seg->type);
  2242. continue;
  2243. }
  2244. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2245. if (!seg)
  2246. continue;
  2247. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2248. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2249. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2250. }
  2251. meta_info.entry[dump_seg->type].entry_num++;
  2252. seg->da = dump_seg->address;
  2253. seg->va = dump_seg->v_address;
  2254. seg->size = dump_seg->size;
  2255. list_add_tail(&seg->node, &head);
  2256. dump_seg++;
  2257. }
  2258. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2259. if (!seg)
  2260. goto do_elf_dump;
  2261. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2262. meta_info.version = CNSS_RAMDUMP_VERSION;
  2263. meta_info.chipset = plat_priv->device_id;
  2264. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2265. seg->va = &meta_info;
  2266. seg->size = sizeof(meta_info);
  2267. list_add(&seg->node, &head);
  2268. do_elf_dump:
  2269. ret = qcom_elf_dump(&head, info_v2->ramdump_dev, ELF_CLASS);
  2270. while (!list_empty(&head)) {
  2271. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2272. list_del(&seg->node);
  2273. kfree(seg);
  2274. }
  2275. return ret;
  2276. }
  2277. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  2278. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2279. static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv)
  2280. {
  2281. struct cnss_ramdump_info *ramdump_info;
  2282. struct msm_dump_entry dump_entry;
  2283. ramdump_info = &plat_priv->ramdump_info;
  2284. ramdump_info->dump_data.addr = ramdump_info->ramdump_pa;
  2285. ramdump_info->dump_data.len = ramdump_info->ramdump_size;
  2286. ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER;
  2287. ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2;
  2288. strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME,
  2289. sizeof(ramdump_info->dump_data.name));
  2290. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2291. dump_entry.addr = virt_to_phys(&ramdump_info->dump_data);
  2292. return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2293. &dump_entry);
  2294. }
  2295. static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv)
  2296. {
  2297. int ret = 0;
  2298. struct device *dev;
  2299. struct cnss_ramdump_info *ramdump_info;
  2300. u32 ramdump_size = 0;
  2301. dev = &plat_priv->plat_dev->dev;
  2302. ramdump_info = &plat_priv->ramdump_info;
  2303. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2304. &ramdump_size) == 0) {
  2305. ramdump_info->ramdump_va =
  2306. dma_alloc_coherent(dev, ramdump_size,
  2307. &ramdump_info->ramdump_pa,
  2308. GFP_KERNEL);
  2309. if (ramdump_info->ramdump_va)
  2310. ramdump_info->ramdump_size = ramdump_size;
  2311. }
  2312. cnss_pr_dbg("ramdump va: %pK, pa: %pa\n",
  2313. ramdump_info->ramdump_va, &ramdump_info->ramdump_pa);
  2314. if (ramdump_info->ramdump_size == 0) {
  2315. cnss_pr_info("Ramdump will not be collected");
  2316. goto out;
  2317. }
  2318. ret = cnss_init_dump_entry(plat_priv);
  2319. if (ret) {
  2320. cnss_pr_err("Failed to setup dump table, err = %d\n", ret);
  2321. goto free_ramdump;
  2322. }
  2323. ramdump_info->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2324. if (!ramdump_info->ramdump_dev) {
  2325. cnss_pr_err("Failed to create ramdump device!");
  2326. ret = -ENOMEM;
  2327. goto free_ramdump;
  2328. }
  2329. return 0;
  2330. free_ramdump:
  2331. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2332. ramdump_info->ramdump_va, ramdump_info->ramdump_pa);
  2333. out:
  2334. return ret;
  2335. }
  2336. static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv)
  2337. {
  2338. struct device *dev;
  2339. struct cnss_ramdump_info *ramdump_info;
  2340. dev = &plat_priv->plat_dev->dev;
  2341. ramdump_info = &plat_priv->ramdump_info;
  2342. if (ramdump_info->ramdump_dev)
  2343. cnss_destroy_ramdump_device(plat_priv,
  2344. ramdump_info->ramdump_dev);
  2345. if (ramdump_info->ramdump_va)
  2346. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2347. ramdump_info->ramdump_va,
  2348. ramdump_info->ramdump_pa);
  2349. }
  2350. /**
  2351. * cnss_ignore_dump_data_reg_fail - Ignore Ramdump table register failure
  2352. * @ret: Error returned by msm_dump_data_register_nominidump
  2353. *
  2354. * For Lahaina GKI boot, we dont have support for mem dump feature. So
  2355. * ignore failure.
  2356. *
  2357. * Return: Same given error code if mem dump feature enabled, 0 otherwise
  2358. */
  2359. static int cnss_ignore_dump_data_reg_fail(int ret)
  2360. {
  2361. return ret;
  2362. }
  2363. static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv)
  2364. {
  2365. int ret = 0;
  2366. struct cnss_ramdump_info_v2 *info_v2;
  2367. struct cnss_dump_data *dump_data;
  2368. struct msm_dump_entry dump_entry;
  2369. struct device *dev = &plat_priv->plat_dev->dev;
  2370. u32 ramdump_size = 0;
  2371. info_v2 = &plat_priv->ramdump_info_v2;
  2372. dump_data = &info_v2->dump_data;
  2373. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2374. &ramdump_size) == 0)
  2375. info_v2->ramdump_size = ramdump_size;
  2376. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2377. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2378. if (!info_v2->dump_data_vaddr)
  2379. return -ENOMEM;
  2380. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2381. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2382. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2383. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2384. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2385. sizeof(dump_data->name));
  2386. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2387. dump_entry.addr = virt_to_phys(dump_data);
  2388. ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2389. &dump_entry);
  2390. if (ret) {
  2391. ret = cnss_ignore_dump_data_reg_fail(ret);
  2392. cnss_pr_err("Failed to setup dump table, %s (%d)\n",
  2393. ret ? "Error" : "Ignoring", ret);
  2394. goto free_ramdump;
  2395. }
  2396. info_v2->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2397. if (!info_v2->ramdump_dev) {
  2398. cnss_pr_err("Failed to create ramdump device!\n");
  2399. ret = -ENOMEM;
  2400. goto free_ramdump;
  2401. }
  2402. return 0;
  2403. free_ramdump:
  2404. kfree(info_v2->dump_data_vaddr);
  2405. info_v2->dump_data_vaddr = NULL;
  2406. return ret;
  2407. }
  2408. static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv)
  2409. {
  2410. struct cnss_ramdump_info_v2 *info_v2;
  2411. info_v2 = &plat_priv->ramdump_info_v2;
  2412. if (info_v2->ramdump_dev)
  2413. cnss_destroy_ramdump_device(plat_priv, info_v2->ramdump_dev);
  2414. kfree(info_v2->dump_data_vaddr);
  2415. info_v2->dump_data_vaddr = NULL;
  2416. info_v2->dump_data_valid = false;
  2417. }
  2418. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2419. {
  2420. int ret = 0;
  2421. switch (plat_priv->device_id) {
  2422. case QCA6174_DEVICE_ID:
  2423. ret = cnss_register_ramdump_v1(plat_priv);
  2424. break;
  2425. case QCA6290_DEVICE_ID:
  2426. case QCA6390_DEVICE_ID:
  2427. case QCA6490_DEVICE_ID:
  2428. case KIWI_DEVICE_ID:
  2429. ret = cnss_register_ramdump_v2(plat_priv);
  2430. break;
  2431. default:
  2432. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2433. ret = -ENODEV;
  2434. break;
  2435. }
  2436. return ret;
  2437. }
  2438. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2439. {
  2440. switch (plat_priv->device_id) {
  2441. case QCA6174_DEVICE_ID:
  2442. cnss_unregister_ramdump_v1(plat_priv);
  2443. break;
  2444. case QCA6290_DEVICE_ID:
  2445. case QCA6390_DEVICE_ID:
  2446. case QCA6490_DEVICE_ID:
  2447. case KIWI_DEVICE_ID:
  2448. cnss_unregister_ramdump_v2(plat_priv);
  2449. break;
  2450. default:
  2451. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2452. break;
  2453. }
  2454. }
  2455. #else
  2456. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2457. {
  2458. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2459. struct cnss_dump_data *dump_data = dump_data = &info_v2->dump_data;
  2460. struct device *dev = &plat_priv->plat_dev->dev;
  2461. u32 ramdump_size = 0;
  2462. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2463. &ramdump_size) == 0)
  2464. info_v2->ramdump_size = ramdump_size;
  2465. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2466. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2467. if (!info_v2->dump_data_vaddr)
  2468. return -ENOMEM;
  2469. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2470. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2471. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2472. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2473. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2474. sizeof(dump_data->name));
  2475. info_v2->ramdump_dev = dev;
  2476. return 0;
  2477. }
  2478. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2479. {
  2480. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2481. info_v2->ramdump_dev = NULL;
  2482. kfree(info_v2->dump_data_vaddr);
  2483. info_v2->dump_data_vaddr = NULL;
  2484. info_v2->dump_data_valid = false;
  2485. }
  2486. #endif /* CONFIG_QCOM_MEMORY_DUMP_V2 */
  2487. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  2488. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2489. phys_addr_t *pa, unsigned long attrs)
  2490. {
  2491. struct sg_table sgt;
  2492. int ret;
  2493. ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
  2494. if (ret) {
  2495. cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
  2496. va, &dma, size, attrs);
  2497. return -EINVAL;
  2498. }
  2499. *pa = page_to_phys(sg_page(sgt.sgl));
  2500. sg_free_table(&sgt);
  2501. return 0;
  2502. }
  2503. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2504. enum cnss_fw_dump_type type, int seg_no,
  2505. void *va, phys_addr_t pa, size_t size)
  2506. {
  2507. struct md_region md_entry;
  2508. int ret;
  2509. switch (type) {
  2510. case CNSS_FW_IMAGE:
  2511. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2512. seg_no);
  2513. break;
  2514. case CNSS_FW_RDDM:
  2515. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2516. seg_no);
  2517. break;
  2518. case CNSS_FW_REMOTE_HEAP:
  2519. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2520. seg_no);
  2521. break;
  2522. default:
  2523. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2524. return -EINVAL;
  2525. }
  2526. md_entry.phys_addr = pa;
  2527. md_entry.virt_addr = (uintptr_t)va;
  2528. md_entry.size = size;
  2529. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2530. cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2531. md_entry.name, va, &pa, size);
  2532. ret = msm_minidump_add_region(&md_entry);
  2533. if (ret < 0)
  2534. cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
  2535. return ret;
  2536. }
  2537. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2538. enum cnss_fw_dump_type type, int seg_no,
  2539. void *va, phys_addr_t pa, size_t size)
  2540. {
  2541. struct md_region md_entry;
  2542. int ret;
  2543. switch (type) {
  2544. case CNSS_FW_IMAGE:
  2545. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2546. seg_no);
  2547. break;
  2548. case CNSS_FW_RDDM:
  2549. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2550. seg_no);
  2551. break;
  2552. case CNSS_FW_REMOTE_HEAP:
  2553. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2554. seg_no);
  2555. break;
  2556. default:
  2557. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2558. return -EINVAL;
  2559. }
  2560. md_entry.phys_addr = pa;
  2561. md_entry.virt_addr = (uintptr_t)va;
  2562. md_entry.size = size;
  2563. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2564. cnss_pr_dbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2565. md_entry.name, va, &pa, size);
  2566. ret = msm_minidump_remove_region(&md_entry);
  2567. if (ret)
  2568. cnss_pr_err("Failed to remove mini dump region, err = %d\n",
  2569. ret);
  2570. return ret;
  2571. }
  2572. #else
  2573. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2574. phys_addr_t *pa, unsigned long attrs)
  2575. {
  2576. return 0;
  2577. }
  2578. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2579. enum cnss_fw_dump_type type, int seg_no,
  2580. void *va, phys_addr_t pa, size_t size)
  2581. {
  2582. return 0;
  2583. }
  2584. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2585. enum cnss_fw_dump_type type, int seg_no,
  2586. void *va, phys_addr_t pa, size_t size)
  2587. {
  2588. return 0;
  2589. }
  2590. #endif /* CONFIG_QCOM_MINIDUMP */
  2591. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  2592. const struct firmware **fw_entry,
  2593. const char *filename)
  2594. {
  2595. if (IS_ENABLED(CONFIG_CNSS_REQ_FW_DIRECT))
  2596. return request_firmware_direct(fw_entry, filename,
  2597. &plat_priv->plat_dev->dev);
  2598. else
  2599. return firmware_request_nowarn(fw_entry, filename,
  2600. &plat_priv->plat_dev->dev);
  2601. }
  2602. #if IS_ENABLED(CONFIG_INTERCONNECT)
  2603. /**
  2604. * cnss_register_bus_scale() - Setup interconnect voting data
  2605. * @plat_priv: Platform data structure
  2606. *
  2607. * For different interconnect path configured in device tree setup voting data
  2608. * for list of bandwidth requirements.
  2609. *
  2610. * Result: 0 for success. -EINVAL if not configured
  2611. */
  2612. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2613. {
  2614. int ret = -EINVAL;
  2615. u32 idx, i, j, cfg_arr_size, *cfg_arr = NULL;
  2616. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2617. struct device *dev = &plat_priv->plat_dev->dev;
  2618. INIT_LIST_HEAD(&plat_priv->icc.list_head);
  2619. ret = of_property_read_u32(dev->of_node,
  2620. "qcom,icc-path-count",
  2621. &plat_priv->icc.path_count);
  2622. if (ret) {
  2623. cnss_pr_dbg("Platform Bus Interconnect path not configured\n");
  2624. return 0;
  2625. }
  2626. ret = of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  2627. "qcom,bus-bw-cfg-count",
  2628. &plat_priv->icc.bus_bw_cfg_count);
  2629. if (ret) {
  2630. cnss_pr_err("Failed to get Bus BW Config table size\n");
  2631. goto cleanup;
  2632. }
  2633. cfg_arr_size = plat_priv->icc.path_count *
  2634. plat_priv->icc.bus_bw_cfg_count * CNSS_ICC_VOTE_MAX;
  2635. cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
  2636. if (!cfg_arr) {
  2637. cnss_pr_err("Failed to alloc cfg table mem\n");
  2638. ret = -ENOMEM;
  2639. goto cleanup;
  2640. }
  2641. ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
  2642. "qcom,bus-bw-cfg", cfg_arr,
  2643. cfg_arr_size);
  2644. if (ret) {
  2645. cnss_pr_err("Invalid Bus BW Config Table\n");
  2646. goto cleanup;
  2647. }
  2648. cnss_pr_dbg("ICC Path_Count: %d BW_CFG_Count: %d\n",
  2649. plat_priv->icc.path_count, plat_priv->icc.bus_bw_cfg_count);
  2650. for (idx = 0; idx < plat_priv->icc.path_count; idx++) {
  2651. bus_bw_info = devm_kzalloc(dev, sizeof(*bus_bw_info),
  2652. GFP_KERNEL);
  2653. if (!bus_bw_info) {
  2654. ret = -ENOMEM;
  2655. goto out;
  2656. }
  2657. ret = of_property_read_string_index(dev->of_node,
  2658. "interconnect-names", idx,
  2659. &bus_bw_info->icc_name);
  2660. if (ret)
  2661. goto out;
  2662. bus_bw_info->icc_path =
  2663. of_icc_get(&plat_priv->plat_dev->dev,
  2664. bus_bw_info->icc_name);
  2665. if (IS_ERR(bus_bw_info->icc_path)) {
  2666. ret = PTR_ERR(bus_bw_info->icc_path);
  2667. if (ret != -EPROBE_DEFER) {
  2668. cnss_pr_err("Failed to get Interconnect path for %s. Err: %d\n",
  2669. bus_bw_info->icc_name, ret);
  2670. goto out;
  2671. }
  2672. }
  2673. bus_bw_info->cfg_table =
  2674. devm_kcalloc(dev, plat_priv->icc.bus_bw_cfg_count,
  2675. sizeof(*bus_bw_info->cfg_table),
  2676. GFP_KERNEL);
  2677. if (!bus_bw_info->cfg_table) {
  2678. ret = -ENOMEM;
  2679. goto out;
  2680. }
  2681. cnss_pr_dbg("ICC Vote CFG for path: %s\n",
  2682. bus_bw_info->icc_name);
  2683. for (i = 0, j = (idx * plat_priv->icc.bus_bw_cfg_count *
  2684. CNSS_ICC_VOTE_MAX);
  2685. i < plat_priv->icc.bus_bw_cfg_count;
  2686. i++, j += 2) {
  2687. bus_bw_info->cfg_table[i].avg_bw = cfg_arr[j];
  2688. bus_bw_info->cfg_table[i].peak_bw = cfg_arr[j + 1];
  2689. cnss_pr_dbg("ICC Vote BW: %d avg: %d peak: %d\n",
  2690. i, bus_bw_info->cfg_table[i].avg_bw,
  2691. bus_bw_info->cfg_table[i].peak_bw);
  2692. }
  2693. list_add_tail(&bus_bw_info->list,
  2694. &plat_priv->icc.list_head);
  2695. }
  2696. kfree(cfg_arr);
  2697. return 0;
  2698. out:
  2699. list_for_each_entry_safe(bus_bw_info, tmp,
  2700. &plat_priv->icc.list_head, list) {
  2701. list_del(&bus_bw_info->list);
  2702. }
  2703. cleanup:
  2704. kfree(cfg_arr);
  2705. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2706. return ret;
  2707. }
  2708. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv)
  2709. {
  2710. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2711. list_for_each_entry_safe(bus_bw_info, tmp,
  2712. &plat_priv->icc.list_head, list) {
  2713. list_del(&bus_bw_info->list);
  2714. if (bus_bw_info->icc_path)
  2715. icc_put(bus_bw_info->icc_path);
  2716. }
  2717. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2718. }
  2719. #else
  2720. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2721. {
  2722. return 0;
  2723. }
  2724. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) {}
  2725. #endif /* CONFIG_INTERCONNECT */
  2726. void cnss_daemon_connection_update_cb(void *cb_ctx, bool status)
  2727. {
  2728. struct cnss_plat_data *plat_priv = cb_ctx;
  2729. if (!plat_priv) {
  2730. cnss_pr_err("%s: Invalid context\n", __func__);
  2731. return;
  2732. }
  2733. if (status) {
  2734. cnss_pr_info("CNSS Daemon connected\n");
  2735. set_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2736. complete(&plat_priv->daemon_connected);
  2737. } else {
  2738. cnss_pr_info("CNSS Daemon disconnected\n");
  2739. reinit_completion(&plat_priv->daemon_connected);
  2740. clear_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2741. }
  2742. }
  2743. static ssize_t enable_hds_store(struct device *dev,
  2744. struct device_attribute *attr,
  2745. const char *buf, size_t count)
  2746. {
  2747. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2748. unsigned int enable_hds = 0;
  2749. if (!plat_priv)
  2750. return -ENODEV;
  2751. if (sscanf(buf, "%du", &enable_hds) != 1) {
  2752. cnss_pr_err("Invalid enable_hds sysfs command\n");
  2753. return -EINVAL;
  2754. }
  2755. if (enable_hds)
  2756. plat_priv->hds_enabled = true;
  2757. else
  2758. plat_priv->hds_enabled = false;
  2759. cnss_pr_dbg("%s HDS file download, count is %zu\n",
  2760. plat_priv->hds_enabled ? "Enable" : "Disable", count);
  2761. return count;
  2762. }
  2763. static ssize_t recovery_show(struct device *dev,
  2764. struct device_attribute *attr,
  2765. char *buf)
  2766. {
  2767. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2768. u32 buf_size = PAGE_SIZE;
  2769. u32 curr_len = 0;
  2770. u32 buf_written = 0;
  2771. if (!plat_priv)
  2772. return -ENODEV;
  2773. buf_written = scnprintf(buf, buf_size,
  2774. "Usage: echo [recovery_bitmap] > /sys/kernel/cnss/recovery\n"
  2775. "BIT0 -- wlan fw recovery\n"
  2776. "BIT1 -- wlan pcss recovery\n"
  2777. "---------------------------------\n");
  2778. curr_len += buf_written;
  2779. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  2780. "WLAN recovery %s[%d]\n",
  2781. plat_priv->recovery_enabled ? "Enabled" : "Disabled",
  2782. plat_priv->recovery_enabled);
  2783. curr_len += buf_written;
  2784. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  2785. "WLAN PCSS recovery %s[%d]\n",
  2786. plat_priv->recovery_pcss_enabled ? "Enabled" : "Disabled",
  2787. plat_priv->recovery_pcss_enabled);
  2788. curr_len += buf_written;
  2789. /*
  2790. * Now size of curr_len is not over page size for sure,
  2791. * later if new item or none-fixed size item added, need
  2792. * add check to make sure curr_len is not over page size.
  2793. */
  2794. return curr_len;
  2795. }
  2796. static ssize_t recovery_store(struct device *dev,
  2797. struct device_attribute *attr,
  2798. const char *buf, size_t count)
  2799. {
  2800. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2801. unsigned int recovery = 0;
  2802. int ret;
  2803. if (!plat_priv)
  2804. return -ENODEV;
  2805. if (sscanf(buf, "%du", &recovery) != 1) {
  2806. cnss_pr_err("Invalid recovery sysfs command\n");
  2807. return -EINVAL;
  2808. }
  2809. plat_priv->recovery_enabled = !!(recovery & CNSS_WLAN_RECOVERY);
  2810. plat_priv->recovery_pcss_enabled = !!(recovery & CNSS_PCSS_RECOVERY);
  2811. cnss_pr_dbg("%s WLAN recovery, count is %zu\n",
  2812. plat_priv->recovery_enabled ? "Enable" : "Disable", count);
  2813. cnss_pr_dbg("%s PCSS recovery, count is %zu\n",
  2814. plat_priv->recovery_pcss_enabled ? "Enable" : "Disable", count);
  2815. ret = cnss_send_subsys_restart_level_msg(plat_priv);
  2816. if (ret < 0) {
  2817. cnss_pr_err("pcss recovery setting failed with ret %d\n", ret);
  2818. plat_priv->recovery_pcss_enabled = false;
  2819. return -EINVAL;
  2820. }
  2821. return count;
  2822. }
  2823. static ssize_t shutdown_store(struct device *dev,
  2824. struct device_attribute *attr,
  2825. const char *buf, size_t count)
  2826. {
  2827. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2828. if (plat_priv) {
  2829. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  2830. del_timer(&plat_priv->fw_boot_timer);
  2831. complete_all(&plat_priv->power_up_complete);
  2832. complete_all(&plat_priv->cal_complete);
  2833. }
  2834. cnss_pr_dbg("Received shutdown notification\n");
  2835. return count;
  2836. }
  2837. static ssize_t fs_ready_store(struct device *dev,
  2838. struct device_attribute *attr,
  2839. const char *buf, size_t count)
  2840. {
  2841. int fs_ready = 0;
  2842. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2843. if (sscanf(buf, "%du", &fs_ready) != 1)
  2844. return -EINVAL;
  2845. cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n",
  2846. fs_ready, count);
  2847. if (!plat_priv) {
  2848. cnss_pr_err("plat_priv is NULL\n");
  2849. return count;
  2850. }
  2851. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) {
  2852. cnss_pr_dbg("QMI is bypassed\n");
  2853. return count;
  2854. }
  2855. switch (plat_priv->device_id) {
  2856. case QCA6290_DEVICE_ID:
  2857. case QCA6390_DEVICE_ID:
  2858. case QCA6490_DEVICE_ID:
  2859. case KIWI_DEVICE_ID:
  2860. break;
  2861. default:
  2862. cnss_pr_err("Not supported for device ID 0x%lx\n",
  2863. plat_priv->device_id);
  2864. return count;
  2865. }
  2866. if (fs_ready == FILE_SYSTEM_READY && plat_priv->cbc_enabled) {
  2867. cnss_driver_event_post(plat_priv,
  2868. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  2869. 0, NULL);
  2870. }
  2871. return count;
  2872. }
  2873. static ssize_t qdss_trace_start_store(struct device *dev,
  2874. struct device_attribute *attr,
  2875. const char *buf, size_t count)
  2876. {
  2877. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2878. wlfw_qdss_trace_start(plat_priv);
  2879. cnss_pr_dbg("Received QDSS start command\n");
  2880. return count;
  2881. }
  2882. static ssize_t qdss_trace_stop_store(struct device *dev,
  2883. struct device_attribute *attr,
  2884. const char *buf, size_t count)
  2885. {
  2886. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2887. u32 option = 0;
  2888. if (sscanf(buf, "%du", &option) != 1)
  2889. return -EINVAL;
  2890. wlfw_qdss_trace_stop(plat_priv, option);
  2891. cnss_pr_dbg("Received QDSS stop command\n");
  2892. return count;
  2893. }
  2894. static ssize_t qdss_conf_download_store(struct device *dev,
  2895. struct device_attribute *attr,
  2896. const char *buf, size_t count)
  2897. {
  2898. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2899. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  2900. cnss_pr_dbg("Received QDSS download config command\n");
  2901. return count;
  2902. }
  2903. static ssize_t hw_trace_override_store(struct device *dev,
  2904. struct device_attribute *attr,
  2905. const char *buf, size_t count)
  2906. {
  2907. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2908. int tmp = 0;
  2909. if (sscanf(buf, "%du", &tmp) != 1)
  2910. return -EINVAL;
  2911. plat_priv->hw_trc_override = tmp;
  2912. cnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  2913. return count;
  2914. }
  2915. static ssize_t charger_mode_store(struct device *dev,
  2916. struct device_attribute *attr,
  2917. const char *buf, size_t count)
  2918. {
  2919. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2920. int tmp = 0;
  2921. if (sscanf(buf, "%du", &tmp) != 1)
  2922. return -EINVAL;
  2923. plat_priv->charger_mode = tmp;
  2924. cnss_pr_dbg("Received Charger Mode: %d\n", tmp);
  2925. return count;
  2926. }
  2927. static DEVICE_ATTR_WO(fs_ready);
  2928. static DEVICE_ATTR_WO(shutdown);
  2929. static DEVICE_ATTR_RW(recovery);
  2930. static DEVICE_ATTR_WO(enable_hds);
  2931. static DEVICE_ATTR_WO(qdss_trace_start);
  2932. static DEVICE_ATTR_WO(qdss_trace_stop);
  2933. static DEVICE_ATTR_WO(qdss_conf_download);
  2934. static DEVICE_ATTR_WO(hw_trace_override);
  2935. static DEVICE_ATTR_WO(charger_mode);
  2936. static struct attribute *cnss_attrs[] = {
  2937. &dev_attr_fs_ready.attr,
  2938. &dev_attr_shutdown.attr,
  2939. &dev_attr_recovery.attr,
  2940. &dev_attr_enable_hds.attr,
  2941. &dev_attr_qdss_trace_start.attr,
  2942. &dev_attr_qdss_trace_stop.attr,
  2943. &dev_attr_qdss_conf_download.attr,
  2944. &dev_attr_hw_trace_override.attr,
  2945. &dev_attr_charger_mode.attr,
  2946. NULL,
  2947. };
  2948. static struct attribute_group cnss_attr_group = {
  2949. .attrs = cnss_attrs,
  2950. };
  2951. static int cnss_create_sysfs_link(struct cnss_plat_data *plat_priv)
  2952. {
  2953. struct device *dev = &plat_priv->plat_dev->dev;
  2954. int ret;
  2955. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "cnss");
  2956. if (ret) {
  2957. cnss_pr_err("Failed to create cnss link, err = %d\n",
  2958. ret);
  2959. goto out;
  2960. }
  2961. /* This is only for backward compatibility. */
  2962. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "shutdown_wlan");
  2963. if (ret) {
  2964. cnss_pr_err("Failed to create shutdown_wlan link, err = %d\n",
  2965. ret);
  2966. goto rm_cnss_link;
  2967. }
  2968. return 0;
  2969. rm_cnss_link:
  2970. sysfs_remove_link(kernel_kobj, "cnss");
  2971. out:
  2972. return ret;
  2973. }
  2974. static void cnss_remove_sysfs_link(struct cnss_plat_data *plat_priv)
  2975. {
  2976. sysfs_remove_link(kernel_kobj, "shutdown_wlan");
  2977. sysfs_remove_link(kernel_kobj, "cnss");
  2978. }
  2979. static int cnss_create_sysfs(struct cnss_plat_data *plat_priv)
  2980. {
  2981. int ret = 0;
  2982. ret = devm_device_add_group(&plat_priv->plat_dev->dev,
  2983. &cnss_attr_group);
  2984. if (ret) {
  2985. cnss_pr_err("Failed to create cnss device group, err = %d\n",
  2986. ret);
  2987. goto out;
  2988. }
  2989. cnss_create_sysfs_link(plat_priv);
  2990. return 0;
  2991. out:
  2992. return ret;
  2993. }
  2994. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  2995. {
  2996. cnss_remove_sysfs_link(plat_priv);
  2997. devm_device_remove_group(&plat_priv->plat_dev->dev, &cnss_attr_group);
  2998. }
  2999. static int cnss_event_work_init(struct cnss_plat_data *plat_priv)
  3000. {
  3001. spin_lock_init(&plat_priv->event_lock);
  3002. plat_priv->event_wq = alloc_workqueue("cnss_driver_event",
  3003. WQ_UNBOUND, 1);
  3004. if (!plat_priv->event_wq) {
  3005. cnss_pr_err("Failed to create event workqueue!\n");
  3006. return -EFAULT;
  3007. }
  3008. INIT_WORK(&plat_priv->event_work, cnss_driver_event_work);
  3009. INIT_LIST_HEAD(&plat_priv->event_list);
  3010. return 0;
  3011. }
  3012. static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
  3013. {
  3014. destroy_workqueue(plat_priv->event_wq);
  3015. }
  3016. static int cnss_reboot_notifier(struct notifier_block *nb,
  3017. unsigned long action,
  3018. void *data)
  3019. {
  3020. struct cnss_plat_data *plat_priv =
  3021. container_of(nb, struct cnss_plat_data, reboot_nb);
  3022. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  3023. del_timer(&plat_priv->fw_boot_timer);
  3024. complete_all(&plat_priv->power_up_complete);
  3025. complete_all(&plat_priv->cal_complete);
  3026. cnss_pr_dbg("Reboot is in progress with action %d\n", action);
  3027. return NOTIFY_DONE;
  3028. }
  3029. static int cnss_misc_init(struct cnss_plat_data *plat_priv)
  3030. {
  3031. int ret;
  3032. ret = cnss_init_sol_gpio(plat_priv);
  3033. if (ret)
  3034. return ret;
  3035. timer_setup(&plat_priv->fw_boot_timer,
  3036. cnss_bus_fw_boot_timeout_hdlr, 0);
  3037. ret = register_pm_notifier(&cnss_pm_notifier);
  3038. if (ret)
  3039. cnss_pr_err("Failed to register PM notifier, err = %d\n", ret);
  3040. plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
  3041. ret = register_reboot_notifier(&plat_priv->reboot_nb);
  3042. if (ret)
  3043. cnss_pr_err("Failed to register reboot notifier, err = %d\n",
  3044. ret);
  3045. ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
  3046. if (ret)
  3047. cnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  3048. ret);
  3049. INIT_WORK(&plat_priv->recovery_work, cnss_recovery_work_handler);
  3050. init_completion(&plat_priv->power_up_complete);
  3051. init_completion(&plat_priv->cal_complete);
  3052. init_completion(&plat_priv->rddm_complete);
  3053. init_completion(&plat_priv->recovery_complete);
  3054. init_completion(&plat_priv->daemon_connected);
  3055. mutex_init(&plat_priv->dev_lock);
  3056. mutex_init(&plat_priv->driver_ops_lock);
  3057. plat_priv->recovery_ws =
  3058. wakeup_source_register(&plat_priv->plat_dev->dev,
  3059. "CNSS_FW_RECOVERY");
  3060. if (!plat_priv->recovery_ws)
  3061. cnss_pr_err("Failed to setup FW recovery wake source\n");
  3062. ret = cnss_plat_ipc_register(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3063. cnss_daemon_connection_update_cb,
  3064. plat_priv);
  3065. if (ret)
  3066. cnss_pr_err("QMI IPC connection call back register failed, err = %d\n",
  3067. ret);
  3068. plat_priv->sram_dump = kcalloc(SRAM_DUMP_SIZE, 1, GFP_KERNEL);
  3069. return 0;
  3070. }
  3071. static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
  3072. {
  3073. cnss_plat_ipc_unregister(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3074. plat_priv);
  3075. complete_all(&plat_priv->recovery_complete);
  3076. complete_all(&plat_priv->rddm_complete);
  3077. complete_all(&plat_priv->cal_complete);
  3078. complete_all(&plat_priv->power_up_complete);
  3079. complete_all(&plat_priv->daemon_connected);
  3080. device_init_wakeup(&plat_priv->plat_dev->dev, false);
  3081. unregister_reboot_notifier(&plat_priv->reboot_nb);
  3082. unregister_pm_notifier(&cnss_pm_notifier);
  3083. del_timer(&plat_priv->fw_boot_timer);
  3084. wakeup_source_unregister(plat_priv->recovery_ws);
  3085. cnss_deinit_sol_gpio(plat_priv);
  3086. kfree(plat_priv->sram_dump);
  3087. }
  3088. static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
  3089. {
  3090. plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
  3091. plat_priv->cbc_enabled = !IS_ENABLED(CONFIG_CNSS_EMULATION) &&
  3092. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3093. "qcom,wlan-cbc-enabled");
  3094. plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
  3095. plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
  3096. plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
  3097. plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
  3098. plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
  3099. /* Set adsp_pc_enabled default value to true as ADSP pc is always
  3100. * enabled by default
  3101. */
  3102. plat_priv->adsp_pc_enabled = true;
  3103. }
  3104. static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
  3105. {
  3106. struct device *dev = &plat_priv->plat_dev->dev;
  3107. plat_priv->use_pm_domain =
  3108. of_property_read_bool(dev->of_node, "use-pm-domain");
  3109. cnss_pr_dbg("use-pm-domain is %d\n", plat_priv->use_pm_domain);
  3110. }
  3111. static void cnss_get_wlaon_pwr_ctrl_info(struct cnss_plat_data *plat_priv)
  3112. {
  3113. struct device *dev = &plat_priv->plat_dev->dev;
  3114. plat_priv->set_wlaon_pwr_ctrl =
  3115. of_property_read_bool(dev->of_node, "qcom,set-wlaon-pwr-ctrl");
  3116. cnss_pr_dbg("set_wlaon_pwr_ctrl is %d\n",
  3117. plat_priv->set_wlaon_pwr_ctrl);
  3118. }
  3119. static bool cnss_use_fw_path_with_prefix(struct cnss_plat_data *plat_priv)
  3120. {
  3121. return (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3122. "qcom,converged-dt") ||
  3123. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3124. "qcom,same-dt-multi-dev") ||
  3125. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3126. "qcom,multi-wlan-exchg"));
  3127. }
  3128. static const struct platform_device_id cnss_platform_id_table[] = {
  3129. { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, },
  3130. { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, },
  3131. { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, },
  3132. { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, },
  3133. { .name = "kiwi", .driver_data = KIWI_DEVICE_ID, },
  3134. { .name = "qcaconv", .driver_data = 0, },
  3135. { },
  3136. };
  3137. static const struct of_device_id cnss_of_match_table[] = {
  3138. {
  3139. .compatible = "qcom,cnss",
  3140. .data = (void *)&cnss_platform_id_table[0]},
  3141. {
  3142. .compatible = "qcom,cnss-qca6290",
  3143. .data = (void *)&cnss_platform_id_table[1]},
  3144. {
  3145. .compatible = "qcom,cnss-qca6390",
  3146. .data = (void *)&cnss_platform_id_table[2]},
  3147. {
  3148. .compatible = "qcom,cnss-qca6490",
  3149. .data = (void *)&cnss_platform_id_table[3]},
  3150. {
  3151. .compatible = "qcom,cnss-kiwi",
  3152. .data = (void *)&cnss_platform_id_table[4]},
  3153. {
  3154. .compatible = "qcom,cnss-qca-converged",
  3155. .data = (void *)&cnss_platform_id_table[5]},
  3156. { },
  3157. };
  3158. MODULE_DEVICE_TABLE(of, cnss_of_match_table);
  3159. static inline bool
  3160. cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
  3161. {
  3162. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3163. "use-nv-mac");
  3164. }
  3165. static int cnss_get_dev_cfg_node(struct cnss_plat_data *plat_priv)
  3166. {
  3167. struct device_node *child;
  3168. u32 id, i;
  3169. int id_n, device_identifier_gpio, ret;
  3170. u8 gpio_value;
  3171. if (!plat_priv->is_converged_dt)
  3172. return 0;
  3173. /* Parses the wlan_sw_ctrl gpio which is used to identify device */
  3174. ret = cnss_get_wlan_sw_ctrl(plat_priv);
  3175. if (ret) {
  3176. cnss_pr_dbg("Failed to parse wlan_sw_ctrl gpio, error:%d", ret);
  3177. return ret;
  3178. }
  3179. device_identifier_gpio = plat_priv->pinctrl_info.wlan_sw_ctrl_gpio;
  3180. gpio_value = gpio_get_value(device_identifier_gpio);
  3181. cnss_pr_dbg("Value of Device Identifier GPIO: %d\n", gpio_value);
  3182. for_each_available_child_of_node(plat_priv->plat_dev->dev.of_node,
  3183. child) {
  3184. if (strcmp(child->name, "chip_cfg"))
  3185. continue;
  3186. id_n = of_property_count_u32_elems(child, "supported-ids");
  3187. if (id_n <= 0) {
  3188. cnss_pr_err("Device id is NOT set\n");
  3189. return -EINVAL;
  3190. }
  3191. for (i = 0; i < id_n; i++) {
  3192. ret = of_property_read_u32_index(child,
  3193. "supported-ids",
  3194. i, &id);
  3195. if (ret) {
  3196. cnss_pr_err("Failed to read supported ids\n");
  3197. return -EINVAL;
  3198. }
  3199. if (gpio_value && id == QCA6490_DEVICE_ID) {
  3200. plat_priv->plat_dev->dev.of_node = child;
  3201. plat_priv->device_id = QCA6490_DEVICE_ID;
  3202. cnss_utils_update_device_type(CNSS_HSP_DEVICE_TYPE);
  3203. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3204. child->name, i, id);
  3205. return 0;
  3206. } else if (!gpio_value && id == KIWI_DEVICE_ID) {
  3207. plat_priv->plat_dev->dev.of_node = child;
  3208. plat_priv->device_id = KIWI_DEVICE_ID;
  3209. cnss_utils_update_device_type(CNSS_HMT_DEVICE_TYPE);
  3210. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3211. child->name, i, id);
  3212. return 0;
  3213. }
  3214. }
  3215. }
  3216. return -EINVAL;
  3217. }
  3218. static inline bool
  3219. cnss_is_converged_dt(struct cnss_plat_data *plat_priv)
  3220. {
  3221. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3222. "qcom,converged-dt");
  3223. }
  3224. static int cnss_probe(struct platform_device *plat_dev)
  3225. {
  3226. int ret = 0;
  3227. struct cnss_plat_data *plat_priv;
  3228. const struct of_device_id *of_id;
  3229. const struct platform_device_id *device_id;
  3230. int retry = 0;
  3231. if (cnss_get_plat_priv(plat_dev)) {
  3232. cnss_pr_err("Driver is already initialized!\n");
  3233. ret = -EEXIST;
  3234. goto out;
  3235. }
  3236. of_id = of_match_device(cnss_of_match_table, &plat_dev->dev);
  3237. if (!of_id || !of_id->data) {
  3238. cnss_pr_err("Failed to find of match device!\n");
  3239. ret = -ENODEV;
  3240. goto out;
  3241. }
  3242. device_id = of_id->data;
  3243. plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv),
  3244. GFP_KERNEL);
  3245. if (!plat_priv) {
  3246. ret = -ENOMEM;
  3247. goto out;
  3248. }
  3249. plat_priv->plat_dev = plat_dev;
  3250. plat_priv->device_id = device_id->driver_data;
  3251. plat_priv->is_converged_dt = cnss_is_converged_dt(plat_priv);
  3252. plat_priv->use_fw_path_with_prefix =
  3253. cnss_use_fw_path_with_prefix(plat_priv);
  3254. ret = cnss_get_dev_cfg_node(plat_priv);
  3255. if (ret) {
  3256. cnss_pr_err("Failed to get device cfg node, err = %d\n", ret);
  3257. goto reset_plat_dev;
  3258. }
  3259. plat_priv->bus_type = cnss_get_bus_type(plat_priv->device_id);
  3260. plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
  3261. cnss_set_plat_priv(plat_dev, plat_priv);
  3262. platform_set_drvdata(plat_dev, plat_priv);
  3263. INIT_LIST_HEAD(&plat_priv->vreg_list);
  3264. INIT_LIST_HEAD(&plat_priv->clk_list);
  3265. cnss_get_pm_domain_info(plat_priv);
  3266. cnss_get_wlaon_pwr_ctrl_info(plat_priv);
  3267. cnss_power_misc_params_init(plat_priv);
  3268. cnss_get_tcs_info(plat_priv);
  3269. cnss_get_cpr_info(plat_priv);
  3270. cnss_aop_mbox_init(plat_priv);
  3271. cnss_init_control_params(plat_priv);
  3272. ret = cnss_get_resources(plat_priv);
  3273. if (ret)
  3274. goto reset_ctx;
  3275. ret = cnss_register_esoc(plat_priv);
  3276. if (ret)
  3277. goto free_res;
  3278. ret = cnss_register_bus_scale(plat_priv);
  3279. if (ret)
  3280. goto unreg_esoc;
  3281. ret = cnss_create_sysfs(plat_priv);
  3282. if (ret)
  3283. goto unreg_bus_scale;
  3284. ret = cnss_event_work_init(plat_priv);
  3285. if (ret)
  3286. goto remove_sysfs;
  3287. ret = cnss_qmi_init(plat_priv);
  3288. if (ret)
  3289. goto deinit_event_work;
  3290. ret = cnss_dms_init(plat_priv);
  3291. if (ret)
  3292. goto deinit_qmi;
  3293. ret = cnss_debugfs_create(plat_priv);
  3294. if (ret)
  3295. goto deinit_dms;
  3296. ret = cnss_misc_init(plat_priv);
  3297. if (ret)
  3298. goto destroy_debugfs;
  3299. /* Make sure all platform related init are done before
  3300. * device power on and bus init.
  3301. */
  3302. if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks)) {
  3303. retry:
  3304. ret = cnss_power_on_device(plat_priv);
  3305. if (ret)
  3306. goto deinit_misc;
  3307. ret = cnss_bus_init(plat_priv);
  3308. if (ret) {
  3309. if ((ret != -EPROBE_DEFER) &&
  3310. retry++ < POWER_ON_RETRY_MAX_TIMES) {
  3311. cnss_power_off_device(plat_priv);
  3312. cnss_pr_dbg("Retry cnss_bus_init #%d\n", retry);
  3313. msleep(POWER_ON_RETRY_DELAY_MS * retry);
  3314. goto retry;
  3315. }
  3316. goto power_off;
  3317. }
  3318. }
  3319. cnss_register_coex_service(plat_priv);
  3320. cnss_register_ims_service(plat_priv);
  3321. ret = cnss_genl_init();
  3322. if (ret < 0)
  3323. cnss_pr_err("CNSS genl init failed %d\n", ret);
  3324. cnss_pr_info("Platform driver probed successfully.\n");
  3325. return 0;
  3326. power_off:
  3327. if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks))
  3328. cnss_power_off_device(plat_priv);
  3329. deinit_misc:
  3330. cnss_misc_deinit(plat_priv);
  3331. destroy_debugfs:
  3332. cnss_debugfs_destroy(plat_priv);
  3333. deinit_dms:
  3334. cnss_dms_deinit(plat_priv);
  3335. deinit_qmi:
  3336. cnss_qmi_deinit(plat_priv);
  3337. deinit_event_work:
  3338. cnss_event_work_deinit(plat_priv);
  3339. remove_sysfs:
  3340. cnss_remove_sysfs(plat_priv);
  3341. unreg_bus_scale:
  3342. cnss_unregister_bus_scale(plat_priv);
  3343. unreg_esoc:
  3344. cnss_unregister_esoc(plat_priv);
  3345. free_res:
  3346. cnss_put_resources(plat_priv);
  3347. reset_ctx:
  3348. platform_set_drvdata(plat_dev, NULL);
  3349. reset_plat_dev:
  3350. cnss_set_plat_priv(plat_dev, NULL);
  3351. out:
  3352. return ret;
  3353. }
  3354. static int cnss_remove(struct platform_device *plat_dev)
  3355. {
  3356. struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev);
  3357. cnss_genl_exit();
  3358. cnss_unregister_ims_service(plat_priv);
  3359. cnss_unregister_coex_service(plat_priv);
  3360. cnss_bus_deinit(plat_priv);
  3361. cnss_misc_deinit(plat_priv);
  3362. cnss_debugfs_destroy(plat_priv);
  3363. cnss_dms_deinit(plat_priv);
  3364. cnss_qmi_deinit(plat_priv);
  3365. cnss_event_work_deinit(plat_priv);
  3366. cnss_remove_sysfs(plat_priv);
  3367. cnss_unregister_bus_scale(plat_priv);
  3368. cnss_unregister_esoc(plat_priv);
  3369. cnss_put_resources(plat_priv);
  3370. if (!IS_ERR_OR_NULL(plat_priv->mbox_chan))
  3371. mbox_free_channel(plat_priv->mbox_chan);
  3372. platform_set_drvdata(plat_dev, NULL);
  3373. plat_env = NULL;
  3374. return 0;
  3375. }
  3376. static struct platform_driver cnss_platform_driver = {
  3377. .probe = cnss_probe,
  3378. .remove = cnss_remove,
  3379. .driver = {
  3380. .name = "cnss2",
  3381. .of_match_table = cnss_of_match_table,
  3382. #ifdef CONFIG_CNSS_ASYNC
  3383. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  3384. #endif
  3385. },
  3386. };
  3387. static bool cnss_check_compatible_node(void)
  3388. {
  3389. struct device_node *dn = NULL;
  3390. for_each_matching_node(dn, cnss_of_match_table) {
  3391. if (of_device_is_available(dn)) {
  3392. cnss_allow_driver_loading = true;
  3393. return true;
  3394. }
  3395. }
  3396. return false;
  3397. }
  3398. /**
  3399. * cnss_is_valid_dt_node_found - Check if valid device tree node present
  3400. *
  3401. * Valid device tree node means a node with "compatible" property from the
  3402. * device match table and "status" property is not disabled.
  3403. *
  3404. * Return: true if valid device tree node found, false if not found
  3405. */
  3406. static bool cnss_is_valid_dt_node_found(void)
  3407. {
  3408. struct device_node *dn = NULL;
  3409. for_each_matching_node(dn, cnss_of_match_table) {
  3410. if (of_device_is_available(dn))
  3411. break;
  3412. }
  3413. if (dn)
  3414. return true;
  3415. return false;
  3416. }
  3417. static int __init cnss_initialize(void)
  3418. {
  3419. int ret = 0;
  3420. if (!cnss_is_valid_dt_node_found())
  3421. return -ENODEV;
  3422. if (!cnss_check_compatible_node())
  3423. return ret;
  3424. cnss_debug_init();
  3425. ret = platform_driver_register(&cnss_platform_driver);
  3426. if (ret)
  3427. cnss_debug_deinit();
  3428. return ret;
  3429. }
  3430. static void __exit cnss_exit(void)
  3431. {
  3432. platform_driver_unregister(&cnss_platform_driver);
  3433. cnss_debug_deinit();
  3434. }
  3435. module_init(cnss_initialize);
  3436. module_exit(cnss_exit);
  3437. MODULE_LICENSE("GPL v2");
  3438. MODULE_DESCRIPTION("CNSS2 Platform Driver");