debug.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
  3. /* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */
  4. #include <linux/err.h>
  5. #include <linux/seq_file.h>
  6. #include <linux/debugfs.h>
  7. #include "main.h"
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "pci.h"
  11. #define MMIO_REG_ACCESS_MEM_TYPE 0xFF
  12. #define MMIO_REG_RAW_ACCESS_MEM_TYPE 0xFE
  13. #if IS_ENABLED(CONFIG_IPC_LOGGING)
  14. void *cnss_ipc_log_context;
  15. void *cnss_ipc_log_long_context;
  16. #endif
  17. static int cnss_pin_connect_show(struct seq_file *s, void *data)
  18. {
  19. struct cnss_plat_data *cnss_priv = s->private;
  20. seq_puts(s, "Pin connect results\n");
  21. seq_printf(s, "FW power pin result: %04x\n",
  22. cnss_priv->pin_result.fw_pwr_pin_result);
  23. seq_printf(s, "FW PHY IO pin result: %04x\n",
  24. cnss_priv->pin_result.fw_phy_io_pin_result);
  25. seq_printf(s, "FW RF pin result: %04x\n",
  26. cnss_priv->pin_result.fw_rf_pin_result);
  27. seq_printf(s, "Host pin result: %04x\n",
  28. cnss_priv->pin_result.host_pin_result);
  29. seq_puts(s, "\n");
  30. return 0;
  31. }
  32. static int cnss_pin_connect_open(struct inode *inode, struct file *file)
  33. {
  34. return single_open(file, cnss_pin_connect_show, inode->i_private);
  35. }
  36. static const struct file_operations cnss_pin_connect_fops = {
  37. .read = seq_read,
  38. .release = single_release,
  39. .open = cnss_pin_connect_open,
  40. .owner = THIS_MODULE,
  41. .llseek = seq_lseek,
  42. };
  43. static int cnss_stats_show_state(struct seq_file *s,
  44. struct cnss_plat_data *plat_priv)
  45. {
  46. enum cnss_driver_state i;
  47. int skip = 0;
  48. unsigned long state;
  49. seq_printf(s, "\nState: 0x%lx(", plat_priv->driver_state);
  50. for (i = 0, state = plat_priv->driver_state; state != 0;
  51. state >>= 1, i++) {
  52. if (!(state & 0x1))
  53. continue;
  54. if (skip++)
  55. seq_puts(s, " | ");
  56. switch (i) {
  57. case CNSS_QMI_WLFW_CONNECTED:
  58. seq_puts(s, "QMI_WLFW_CONNECTED");
  59. continue;
  60. case CNSS_FW_MEM_READY:
  61. seq_puts(s, "FW_MEM_READY");
  62. continue;
  63. case CNSS_FW_READY:
  64. seq_puts(s, "FW_READY");
  65. continue;
  66. case CNSS_IN_COLD_BOOT_CAL:
  67. seq_puts(s, "IN_COLD_BOOT_CAL");
  68. continue;
  69. case CNSS_DRIVER_LOADING:
  70. seq_puts(s, "DRIVER_LOADING");
  71. continue;
  72. case CNSS_DRIVER_UNLOADING:
  73. seq_puts(s, "DRIVER_UNLOADING");
  74. continue;
  75. case CNSS_DRIVER_IDLE_RESTART:
  76. seq_puts(s, "IDLE_RESTART");
  77. continue;
  78. case CNSS_DRIVER_IDLE_SHUTDOWN:
  79. seq_puts(s, "IDLE_SHUTDOWN");
  80. continue;
  81. case CNSS_DRIVER_PROBED:
  82. seq_puts(s, "DRIVER_PROBED");
  83. continue;
  84. case CNSS_DRIVER_RECOVERY:
  85. seq_puts(s, "DRIVER_RECOVERY");
  86. continue;
  87. case CNSS_FW_BOOT_RECOVERY:
  88. seq_puts(s, "FW_BOOT_RECOVERY");
  89. continue;
  90. case CNSS_DEV_ERR_NOTIFY:
  91. seq_puts(s, "DEV_ERR");
  92. continue;
  93. case CNSS_DRIVER_DEBUG:
  94. seq_puts(s, "DRIVER_DEBUG");
  95. continue;
  96. case CNSS_COEX_CONNECTED:
  97. seq_puts(s, "COEX_CONNECTED");
  98. continue;
  99. case CNSS_IMS_CONNECTED:
  100. seq_puts(s, "IMS_CONNECTED");
  101. continue;
  102. case CNSS_IN_SUSPEND_RESUME:
  103. seq_puts(s, "IN_SUSPEND_RESUME");
  104. continue;
  105. case CNSS_IN_REBOOT:
  106. seq_puts(s, "IN_REBOOT");
  107. continue;
  108. case CNSS_COLD_BOOT_CAL_DONE:
  109. seq_puts(s, "COLD_BOOT_CAL_DONE");
  110. continue;
  111. case CNSS_IN_PANIC:
  112. seq_puts(s, "IN_PANIC");
  113. continue;
  114. case CNSS_QMI_DEL_SERVER:
  115. seq_puts(s, "DEL_SERVER_IN_PROGRESS");
  116. continue;
  117. case CNSS_QMI_DMS_CONNECTED:
  118. seq_puts(s, "DMS_CONNECTED");
  119. continue;
  120. case CNSS_DAEMON_CONNECTED:
  121. seq_puts(s, "DAEMON_CONNECTED");
  122. continue;
  123. case CNSS_PCI_PROBE_DONE:
  124. seq_puts(s, "PCI PROBE DONE");
  125. continue;
  126. case CNSS_DRIVER_REGISTER:
  127. seq_puts(s, "DRIVER REGISTERED");
  128. continue;
  129. }
  130. seq_printf(s, "UNKNOWN-%d", i);
  131. }
  132. seq_puts(s, ")\n");
  133. return 0;
  134. }
  135. static int cnss_stats_show_gpio_state(struct seq_file *s,
  136. struct cnss_plat_data *plat_priv)
  137. {
  138. seq_printf(s, "\nHost SOL: %d", cnss_get_host_sol_value(plat_priv));
  139. seq_printf(s, "\nDev SOL: %d", cnss_get_dev_sol_value(plat_priv));
  140. return 0;
  141. }
  142. static int cnss_stats_show(struct seq_file *s, void *data)
  143. {
  144. struct cnss_plat_data *plat_priv = s->private;
  145. cnss_stats_show_state(s, plat_priv);
  146. cnss_stats_show_gpio_state(s, plat_priv);
  147. return 0;
  148. }
  149. static int cnss_stats_open(struct inode *inode, struct file *file)
  150. {
  151. return single_open(file, cnss_stats_show, inode->i_private);
  152. }
  153. static const struct file_operations cnss_stats_fops = {
  154. .read = seq_read,
  155. .release = single_release,
  156. .open = cnss_stats_open,
  157. .owner = THIS_MODULE,
  158. .llseek = seq_lseek,
  159. };
  160. static ssize_t cnss_dev_boot_debug_write(struct file *fp,
  161. const char __user *user_buf,
  162. size_t count, loff_t *off)
  163. {
  164. struct cnss_plat_data *plat_priv =
  165. ((struct seq_file *)fp->private_data)->private;
  166. struct cnss_pci_data *pci_priv;
  167. char buf[64];
  168. char *cmd;
  169. unsigned int len = 0;
  170. char *sptr, *token;
  171. const char *delim = " ";
  172. int ret = 0;
  173. if (!plat_priv)
  174. return -ENODEV;
  175. len = min(count, sizeof(buf) - 1);
  176. if (copy_from_user(buf, user_buf, len))
  177. return -EFAULT;
  178. buf[len] = '\0';
  179. sptr = buf;
  180. token = strsep(&sptr, delim);
  181. if (!token)
  182. return -EINVAL;
  183. cmd = token;
  184. cnss_pr_dbg("Received dev_boot debug command: %s\n", cmd);
  185. if (sysfs_streq(cmd, "on")) {
  186. ret = cnss_power_on_device(plat_priv);
  187. } else if (sysfs_streq(cmd, "off")) {
  188. cnss_power_off_device(plat_priv);
  189. } else if (sysfs_streq(cmd, "enumerate")) {
  190. ret = cnss_pci_init(plat_priv);
  191. } else if (sysfs_streq(cmd, "powerup")) {
  192. set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  193. ret = cnss_driver_event_post(plat_priv,
  194. CNSS_DRIVER_EVENT_POWER_UP,
  195. CNSS_EVENT_SYNC, NULL);
  196. } else if (sysfs_streq(cmd, "shutdown")) {
  197. ret = cnss_driver_event_post(plat_priv,
  198. CNSS_DRIVER_EVENT_POWER_DOWN,
  199. 0, NULL);
  200. clear_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  201. } else if (sysfs_streq(cmd, "assert_host_sol")) {
  202. ret = cnss_set_host_sol_value(plat_priv, 1);
  203. } else if (sysfs_streq(cmd, "deassert_host_sol")) {
  204. ret = cnss_set_host_sol_value(plat_priv, 0);
  205. } else if (sysfs_streq(cmd, "pdc_update")) {
  206. if (!sptr)
  207. return -EINVAL;
  208. ret = cnss_aop_send_msg(plat_priv, sptr);
  209. } else {
  210. pci_priv = plat_priv->bus_priv;
  211. if (!pci_priv)
  212. return -ENODEV;
  213. if (sysfs_streq(cmd, "download")) {
  214. set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  215. ret = cnss_pci_start_mhi(pci_priv);
  216. } else if (sysfs_streq(cmd, "linkup")) {
  217. ret = cnss_resume_pci_link(pci_priv);
  218. } else if (sysfs_streq(cmd, "linkdown")) {
  219. ret = cnss_suspend_pci_link(pci_priv);
  220. } else if (sysfs_streq(cmd, "assert")) {
  221. cnss_pr_info("FW Assert triggered for debug\n");
  222. ret = cnss_force_fw_assert(&pci_priv->pci_dev->dev);
  223. } else if (sysfs_streq(cmd, "set_cbc_done")) {
  224. cnss_pr_dbg("Force set cold boot cal done status\n");
  225. set_bit(CNSS_COLD_BOOT_CAL_DONE,
  226. &plat_priv->driver_state);
  227. } else {
  228. cnss_pr_err("Device boot debugfs command is invalid\n");
  229. ret = -EINVAL;
  230. }
  231. }
  232. if (ret < 0)
  233. return ret;
  234. return count;
  235. }
  236. static int cnss_dev_boot_debug_show(struct seq_file *s, void *data)
  237. {
  238. seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/dev_boot\n");
  239. seq_puts(s, "<action> can be one of below:\n");
  240. seq_puts(s, "on: turn on device power, assert WLAN_EN\n");
  241. seq_puts(s, "off: de-assert WLAN_EN, turn off device power\n");
  242. seq_puts(s, "enumerate: de-assert PERST, enumerate PCIe\n");
  243. seq_puts(s, "download: download FW and do QMI handshake with FW\n");
  244. seq_puts(s, "linkup: bring up PCIe link\n");
  245. seq_puts(s, "linkdown: bring down PCIe link\n");
  246. seq_puts(s, "powerup: full power on sequence to boot device, download FW and do QMI handshake with FW\n");
  247. seq_puts(s, "shutdown: full power off sequence to shutdown device\n");
  248. seq_puts(s, "assert: trigger firmware assert\n");
  249. seq_puts(s, "set_cbc_done: Set cold boot calibration done status\n");
  250. seq_puts(s, "\npdc_update usage:");
  251. seq_puts(s, "1. echo pdc_update {class: wlan_pdc ss: <pdc_ss>, res: <vreg>.<mode>, <seq>: <val>} > <debugfs_path>/cnss/dev_boot\n");
  252. seq_puts(s, "2. echo pdc_update {class: wlan_pdc ss: <pdc_ss>, res: pdc, enable: <val>} > <debugfs_path>/cnss/dev_boot\n");
  253. return 0;
  254. }
  255. static int cnss_dev_boot_debug_open(struct inode *inode, struct file *file)
  256. {
  257. return single_open(file, cnss_dev_boot_debug_show, inode->i_private);
  258. }
  259. static const struct file_operations cnss_dev_boot_debug_fops = {
  260. .read = seq_read,
  261. .write = cnss_dev_boot_debug_write,
  262. .release = single_release,
  263. .open = cnss_dev_boot_debug_open,
  264. .owner = THIS_MODULE,
  265. .llseek = seq_lseek,
  266. };
  267. static int cnss_reg_read_debug_show(struct seq_file *s, void *data)
  268. {
  269. struct cnss_plat_data *plat_priv = s->private;
  270. mutex_lock(&plat_priv->dev_lock);
  271. if (!plat_priv->diag_reg_read_buf) {
  272. seq_puts(s, "\nUsage: echo <mem_type> <offset> <data_len> > <debugfs_path>/cnss/reg_read\n");
  273. seq_puts(s, "Use mem_type = 0xff for register read by IO access, data_len will be ignored\n");
  274. seq_puts(s, "Use mem_type = 0xfe for register read by raw IO access which skips sanity checks, data_len will be ignored\n");
  275. seq_puts(s, "Use other mem_type for register read by QMI\n");
  276. mutex_unlock(&plat_priv->dev_lock);
  277. return 0;
  278. }
  279. seq_printf(s, "\nRegister read, address: 0x%x memory type: 0x%x length: 0x%x\n\n",
  280. plat_priv->diag_reg_read_addr,
  281. plat_priv->diag_reg_read_mem_type,
  282. plat_priv->diag_reg_read_len);
  283. seq_hex_dump(s, "", DUMP_PREFIX_OFFSET, 32, 4,
  284. plat_priv->diag_reg_read_buf,
  285. plat_priv->diag_reg_read_len, false);
  286. plat_priv->diag_reg_read_len = 0;
  287. kfree(plat_priv->diag_reg_read_buf);
  288. plat_priv->diag_reg_read_buf = NULL;
  289. mutex_unlock(&plat_priv->dev_lock);
  290. return 0;
  291. }
  292. static ssize_t cnss_reg_read_debug_write(struct file *fp,
  293. const char __user *user_buf,
  294. size_t count, loff_t *off)
  295. {
  296. struct cnss_plat_data *plat_priv =
  297. ((struct seq_file *)fp->private_data)->private;
  298. char buf[64];
  299. char *sptr, *token;
  300. unsigned int len = 0;
  301. u32 reg_offset, mem_type;
  302. u32 data_len = 0, reg_val = 0;
  303. u8 *reg_buf = NULL;
  304. const char *delim = " ";
  305. int ret = 0;
  306. len = min(count, sizeof(buf) - 1);
  307. if (copy_from_user(buf, user_buf, len))
  308. return -EFAULT;
  309. buf[len] = '\0';
  310. sptr = buf;
  311. token = strsep(&sptr, delim);
  312. if (!token)
  313. return -EINVAL;
  314. if (!sptr)
  315. return -EINVAL;
  316. if (kstrtou32(token, 0, &mem_type))
  317. return -EINVAL;
  318. token = strsep(&sptr, delim);
  319. if (!token)
  320. return -EINVAL;
  321. if (!sptr)
  322. return -EINVAL;
  323. if (kstrtou32(token, 0, &reg_offset))
  324. return -EINVAL;
  325. token = strsep(&sptr, delim);
  326. if (!token)
  327. return -EINVAL;
  328. if (kstrtou32(token, 0, &data_len))
  329. return -EINVAL;
  330. if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
  331. mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
  332. ret = cnss_bus_debug_reg_read(plat_priv, reg_offset, &reg_val,
  333. mem_type ==
  334. MMIO_REG_RAW_ACCESS_MEM_TYPE);
  335. if (ret)
  336. return ret;
  337. cnss_pr_dbg("Read 0x%x from register offset 0x%x\n", reg_val,
  338. reg_offset);
  339. return count;
  340. }
  341. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  342. cnss_pr_err("Firmware is not ready yet\n");
  343. return -EINVAL;
  344. }
  345. mutex_lock(&plat_priv->dev_lock);
  346. kfree(plat_priv->diag_reg_read_buf);
  347. plat_priv->diag_reg_read_buf = NULL;
  348. reg_buf = kzalloc(data_len, GFP_KERNEL);
  349. if (!reg_buf) {
  350. mutex_unlock(&plat_priv->dev_lock);
  351. return -ENOMEM;
  352. }
  353. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, reg_offset,
  354. mem_type, data_len,
  355. reg_buf);
  356. if (ret) {
  357. kfree(reg_buf);
  358. mutex_unlock(&plat_priv->dev_lock);
  359. return ret;
  360. }
  361. plat_priv->diag_reg_read_addr = reg_offset;
  362. plat_priv->diag_reg_read_mem_type = mem_type;
  363. plat_priv->diag_reg_read_len = data_len;
  364. plat_priv->diag_reg_read_buf = reg_buf;
  365. mutex_unlock(&plat_priv->dev_lock);
  366. return count;
  367. }
  368. static int cnss_reg_read_debug_open(struct inode *inode, struct file *file)
  369. {
  370. return single_open(file, cnss_reg_read_debug_show, inode->i_private);
  371. }
  372. static const struct file_operations cnss_reg_read_debug_fops = {
  373. .read = seq_read,
  374. .write = cnss_reg_read_debug_write,
  375. .open = cnss_reg_read_debug_open,
  376. .owner = THIS_MODULE,
  377. .llseek = seq_lseek,
  378. };
  379. static int cnss_reg_write_debug_show(struct seq_file *s, void *data)
  380. {
  381. seq_puts(s, "\nUsage: echo <mem_type> <offset> <reg_val> > <debugfs_path>/cnss/reg_write\n");
  382. seq_puts(s, "Use mem_type = 0xff for register write by IO access\n");
  383. seq_puts(s, "Use mem_type = 0xfe for register write by raw IO access which skips sanity checks\n");
  384. seq_puts(s, "Use other mem_type for register write by QMI\n");
  385. return 0;
  386. }
  387. static ssize_t cnss_reg_write_debug_write(struct file *fp,
  388. const char __user *user_buf,
  389. size_t count, loff_t *off)
  390. {
  391. struct cnss_plat_data *plat_priv =
  392. ((struct seq_file *)fp->private_data)->private;
  393. char buf[64];
  394. char *sptr, *token;
  395. unsigned int len = 0;
  396. u32 reg_offset, mem_type, reg_val;
  397. const char *delim = " ";
  398. int ret = 0;
  399. len = min(count, sizeof(buf) - 1);
  400. if (copy_from_user(buf, user_buf, len))
  401. return -EFAULT;
  402. buf[len] = '\0';
  403. sptr = buf;
  404. token = strsep(&sptr, delim);
  405. if (!token)
  406. return -EINVAL;
  407. if (!sptr)
  408. return -EINVAL;
  409. if (kstrtou32(token, 0, &mem_type))
  410. return -EINVAL;
  411. token = strsep(&sptr, delim);
  412. if (!token)
  413. return -EINVAL;
  414. if (!sptr)
  415. return -EINVAL;
  416. if (kstrtou32(token, 0, &reg_offset))
  417. return -EINVAL;
  418. token = strsep(&sptr, delim);
  419. if (!token)
  420. return -EINVAL;
  421. if (kstrtou32(token, 0, &reg_val))
  422. return -EINVAL;
  423. if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
  424. mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
  425. ret = cnss_bus_debug_reg_write(plat_priv, reg_offset, reg_val,
  426. mem_type ==
  427. MMIO_REG_RAW_ACCESS_MEM_TYPE);
  428. if (ret)
  429. return ret;
  430. cnss_pr_dbg("Wrote 0x%x to register offset 0x%x\n", reg_val,
  431. reg_offset);
  432. return count;
  433. }
  434. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  435. cnss_pr_err("Firmware is not ready yet\n");
  436. return -EINVAL;
  437. }
  438. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, reg_offset, mem_type,
  439. sizeof(u32),
  440. (u8 *)&reg_val);
  441. if (ret)
  442. return ret;
  443. return count;
  444. }
  445. static int cnss_reg_write_debug_open(struct inode *inode, struct file *file)
  446. {
  447. return single_open(file, cnss_reg_write_debug_show, inode->i_private);
  448. }
  449. static const struct file_operations cnss_reg_write_debug_fops = {
  450. .read = seq_read,
  451. .write = cnss_reg_write_debug_write,
  452. .open = cnss_reg_write_debug_open,
  453. .owner = THIS_MODULE,
  454. .llseek = seq_lseek,
  455. };
  456. static ssize_t cnss_runtime_pm_debug_write(struct file *fp,
  457. const char __user *user_buf,
  458. size_t count, loff_t *off)
  459. {
  460. struct cnss_plat_data *plat_priv =
  461. ((struct seq_file *)fp->private_data)->private;
  462. struct cnss_pci_data *pci_priv;
  463. char buf[64];
  464. char *cmd;
  465. unsigned int len = 0;
  466. int ret = 0;
  467. if (!plat_priv)
  468. return -ENODEV;
  469. pci_priv = plat_priv->bus_priv;
  470. if (!pci_priv)
  471. return -ENODEV;
  472. len = min(count, sizeof(buf) - 1);
  473. if (copy_from_user(buf, user_buf, len))
  474. return -EFAULT;
  475. buf[len] = '\0';
  476. cmd = buf;
  477. if (sysfs_streq(cmd, "usage_count")) {
  478. cnss_pci_pm_runtime_show_usage_count(pci_priv);
  479. } else if (sysfs_streq(cmd, "request_resume")) {
  480. ret = cnss_pci_pm_request_resume(pci_priv);
  481. } else if (sysfs_streq(cmd, "resume")) {
  482. ret = cnss_pci_pm_runtime_resume(pci_priv);
  483. } else if (sysfs_streq(cmd, "get")) {
  484. ret = cnss_pci_pm_runtime_get(pci_priv, RTPM_ID_CNSS);
  485. } else if (sysfs_streq(cmd, "get_noresume")) {
  486. cnss_pci_pm_runtime_get_noresume(pci_priv, RTPM_ID_CNSS);
  487. } else if (sysfs_streq(cmd, "put_autosuspend")) {
  488. ret = cnss_pci_pm_runtime_put_autosuspend(pci_priv,
  489. RTPM_ID_CNSS);
  490. } else if (sysfs_streq(cmd, "put_noidle")) {
  491. cnss_pci_pm_runtime_put_noidle(pci_priv, RTPM_ID_CNSS);
  492. } else if (sysfs_streq(cmd, "mark_last_busy")) {
  493. cnss_pci_pm_runtime_mark_last_busy(pci_priv);
  494. } else if (sysfs_streq(cmd, "resume_bus")) {
  495. cnss_pci_resume_bus(pci_priv);
  496. } else if (sysfs_streq(cmd, "suspend_bus")) {
  497. cnss_pci_suspend_bus(pci_priv);
  498. } else {
  499. cnss_pr_err("Runtime PM debugfs command is invalid\n");
  500. ret = -EINVAL;
  501. }
  502. if (ret < 0)
  503. return ret;
  504. return count;
  505. }
  506. static int cnss_runtime_pm_debug_show(struct seq_file *s, void *data)
  507. {
  508. struct cnss_plat_data *plat_priv = s->private;
  509. struct cnss_pci_data *pci_priv;
  510. int i;
  511. if (!plat_priv)
  512. return -ENODEV;
  513. pci_priv = plat_priv->bus_priv;
  514. if (!pci_priv)
  515. return -ENODEV;
  516. seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/runtime_pm\n");
  517. seq_puts(s, "<action> can be one of below:\n");
  518. seq_puts(s, "usage_count: get runtime PM usage count\n");
  519. seq_puts(s, "reques_resume: do async runtime PM resume\n");
  520. seq_puts(s, "resume: do sync runtime PM resume\n");
  521. seq_puts(s, "get: do runtime PM get\n");
  522. seq_puts(s, "get_noresume: do runtime PM get noresume\n");
  523. seq_puts(s, "put_noidle: do runtime PM put noidle\n");
  524. seq_puts(s, "put_autosuspend: do runtime PM put autosuspend\n");
  525. seq_puts(s, "mark_last_busy: do runtime PM mark last busy\n");
  526. seq_puts(s, "resume_bus: do bus resume only\n");
  527. seq_puts(s, "suspend_bus: do bus suspend only\n");
  528. seq_puts(s, "\nStats:\n");
  529. seq_printf(s, "%s: %u\n", "get count",
  530. atomic_read(&pci_priv->pm_stats.runtime_get));
  531. seq_printf(s, "%s: %u\n", "put count",
  532. atomic_read(&pci_priv->pm_stats.runtime_put));
  533. seq_printf(s, "%-10s%-10s%-10s%-15s%-15s\n",
  534. "id:", "get", "put", "get time(us)", "put time(us)");
  535. for (i = 0; i < RTPM_ID_MAX; i++) {
  536. seq_printf(s, "%d%-9s", i, ":");
  537. seq_printf(s, "%-10d",
  538. atomic_read(&pci_priv->pm_stats.runtime_get_id[i]));
  539. seq_printf(s, "%-10d",
  540. atomic_read(&pci_priv->pm_stats.runtime_put_id[i]));
  541. seq_printf(s, "%-15llu",
  542. pci_priv->pm_stats.runtime_get_timestamp_id[i]);
  543. seq_printf(s, "%-15llu\n",
  544. pci_priv->pm_stats.runtime_put_timestamp_id[i]);
  545. }
  546. return 0;
  547. }
  548. static int cnss_runtime_pm_debug_open(struct inode *inode, struct file *file)
  549. {
  550. return single_open(file, cnss_runtime_pm_debug_show, inode->i_private);
  551. }
  552. static const struct file_operations cnss_runtime_pm_debug_fops = {
  553. .read = seq_read,
  554. .write = cnss_runtime_pm_debug_write,
  555. .open = cnss_runtime_pm_debug_open,
  556. .owner = THIS_MODULE,
  557. .llseek = seq_lseek,
  558. };
  559. static int process_drv(struct cnss_plat_data *plat_priv, bool enabled)
  560. {
  561. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  562. cnss_pr_err("DRV cmd must be used before QMI ready\n");
  563. return -EINVAL;
  564. }
  565. enabled ? cnss_set_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01) :
  566. cnss_clear_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01);
  567. cnss_pr_info("%s DRV suspend\n", enabled ? "enable" : "disable");
  568. return 0;
  569. }
  570. static int process_quirks(struct cnss_plat_data *plat_priv, u32 val)
  571. {
  572. enum cnss_debug_quirks i;
  573. int ret = 0;
  574. unsigned long state;
  575. unsigned long quirks = 0;
  576. for (i = 0, state = val; i < QUIRK_MAX_VALUE; state >>= 1, i++) {
  577. switch (i) {
  578. case DISABLE_DRV:
  579. ret = process_drv(plat_priv, !(state & 0x1));
  580. if (!ret)
  581. quirks |= (state & 0x1) << i;
  582. continue;
  583. default:
  584. quirks |= (state & 0x1) << i;
  585. continue;
  586. }
  587. }
  588. plat_priv->ctrl_params.quirks = quirks;
  589. return 0;
  590. }
  591. static ssize_t cnss_control_params_debug_write(struct file *fp,
  592. const char __user *user_buf,
  593. size_t count, loff_t *off)
  594. {
  595. struct cnss_plat_data *plat_priv =
  596. ((struct seq_file *)fp->private_data)->private;
  597. char buf[64];
  598. char *sptr, *token;
  599. char *cmd;
  600. u32 val;
  601. unsigned int len = 0;
  602. const char *delim = " ";
  603. if (!plat_priv)
  604. return -ENODEV;
  605. len = min(count, sizeof(buf) - 1);
  606. if (copy_from_user(buf, user_buf, len))
  607. return -EFAULT;
  608. buf[len] = '\0';
  609. sptr = buf;
  610. token = strsep(&sptr, delim);
  611. if (!token)
  612. return -EINVAL;
  613. if (!sptr)
  614. return -EINVAL;
  615. cmd = token;
  616. token = strsep(&sptr, delim);
  617. if (!token)
  618. return -EINVAL;
  619. if (kstrtou32(token, 0, &val))
  620. return -EINVAL;
  621. if (strcmp(cmd, "quirks") == 0)
  622. process_quirks(plat_priv, val);
  623. else if (strcmp(cmd, "mhi_timeout") == 0)
  624. plat_priv->ctrl_params.mhi_timeout = val;
  625. else if (strcmp(cmd, "mhi_m2_timeout") == 0)
  626. plat_priv->ctrl_params.mhi_m2_timeout = val;
  627. else if (strcmp(cmd, "qmi_timeout") == 0)
  628. plat_priv->ctrl_params.qmi_timeout = val;
  629. else if (strcmp(cmd, "bdf_type") == 0)
  630. plat_priv->ctrl_params.bdf_type = val;
  631. else if (strcmp(cmd, "time_sync_period") == 0)
  632. plat_priv->ctrl_params.time_sync_period = val;
  633. else
  634. return -EINVAL;
  635. return count;
  636. }
  637. static int cnss_show_quirks_state(struct seq_file *s,
  638. struct cnss_plat_data *plat_priv)
  639. {
  640. enum cnss_debug_quirks i;
  641. int skip = 0;
  642. unsigned long state;
  643. seq_printf(s, "quirks: 0x%lx (", plat_priv->ctrl_params.quirks);
  644. for (i = 0, state = plat_priv->ctrl_params.quirks;
  645. state != 0; state >>= 1, i++) {
  646. if (!(state & 0x1))
  647. continue;
  648. if (skip++)
  649. seq_puts(s, " | ");
  650. switch (i) {
  651. case LINK_DOWN_SELF_RECOVERY:
  652. seq_puts(s, "LINK_DOWN_SELF_RECOVERY");
  653. continue;
  654. case SKIP_DEVICE_BOOT:
  655. seq_puts(s, "SKIP_DEVICE_BOOT");
  656. continue;
  657. case USE_CORE_ONLY_FW:
  658. seq_puts(s, "USE_CORE_ONLY_FW");
  659. continue;
  660. case SKIP_RECOVERY:
  661. seq_puts(s, "SKIP_RECOVERY");
  662. continue;
  663. case QMI_BYPASS:
  664. seq_puts(s, "QMI_BYPASS");
  665. continue;
  666. case ENABLE_WALTEST:
  667. seq_puts(s, "WALTEST");
  668. continue;
  669. case ENABLE_PCI_LINK_DOWN_PANIC:
  670. seq_puts(s, "PCI_LINK_DOWN_PANIC");
  671. continue;
  672. case FBC_BYPASS:
  673. seq_puts(s, "FBC_BYPASS");
  674. continue;
  675. case ENABLE_DAEMON_SUPPORT:
  676. seq_puts(s, "DAEMON_SUPPORT");
  677. continue;
  678. case DISABLE_DRV:
  679. seq_puts(s, "DISABLE_DRV");
  680. continue;
  681. case DISABLE_IO_COHERENCY:
  682. seq_puts(s, "DISABLE_IO_COHERENCY");
  683. continue;
  684. case IGNORE_PCI_LINK_FAILURE:
  685. seq_puts(s, "IGNORE_PCI_LINK_FAILURE");
  686. continue;
  687. case DISABLE_TIME_SYNC:
  688. seq_puts(s, "DISABLE_TIME_SYNC");
  689. continue;
  690. default:
  691. continue;
  692. }
  693. }
  694. seq_puts(s, ")\n");
  695. return 0;
  696. }
  697. static int cnss_control_params_debug_show(struct seq_file *s, void *data)
  698. {
  699. struct cnss_plat_data *cnss_priv = s->private;
  700. seq_puts(s, "\nUsage: echo <params_name> <value> > <debugfs_path>/cnss/control_params\n");
  701. seq_puts(s, "<params_name> can be one of below:\n");
  702. seq_puts(s, "quirks: Debug quirks for driver\n");
  703. seq_puts(s, "mhi_timeout: Timeout for MHI operation in milliseconds\n");
  704. seq_puts(s, "qmi_timeout: Timeout for QMI message in milliseconds\n");
  705. seq_puts(s, "bdf_type: Type of board data file to be downloaded\n");
  706. seq_puts(s, "time_sync_period: Time period to do time sync with device in milliseconds\n");
  707. seq_puts(s, "\nCurrent value:\n");
  708. cnss_show_quirks_state(s, cnss_priv);
  709. seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout);
  710. seq_printf(s, "mhi_m2_timeout: %u\n",
  711. cnss_priv->ctrl_params.mhi_m2_timeout);
  712. seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout);
  713. seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type);
  714. seq_printf(s, "time_sync_period: %u\n",
  715. cnss_priv->ctrl_params.time_sync_period);
  716. return 0;
  717. }
  718. static int cnss_control_params_debug_open(struct inode *inode,
  719. struct file *file)
  720. {
  721. return single_open(file, cnss_control_params_debug_show,
  722. inode->i_private);
  723. }
  724. static const struct file_operations cnss_control_params_debug_fops = {
  725. .read = seq_read,
  726. .write = cnss_control_params_debug_write,
  727. .open = cnss_control_params_debug_open,
  728. .owner = THIS_MODULE,
  729. .llseek = seq_lseek,
  730. };
  731. static ssize_t cnss_dynamic_feature_write(struct file *fp,
  732. const char __user *user_buf,
  733. size_t count, loff_t *off)
  734. {
  735. struct cnss_plat_data *plat_priv =
  736. ((struct seq_file *)fp->private_data)->private;
  737. int ret = 0;
  738. u64 val;
  739. ret = kstrtou64_from_user(user_buf, count, 0, &val);
  740. if (ret)
  741. return ret;
  742. plat_priv->dynamic_feature = val;
  743. ret = cnss_wlfw_dynamic_feature_mask_send_sync(plat_priv);
  744. if (ret < 0)
  745. return ret;
  746. return count;
  747. }
  748. static int cnss_dynamic_feature_show(struct seq_file *s, void *data)
  749. {
  750. struct cnss_plat_data *cnss_priv = s->private;
  751. seq_printf(s, "dynamic_feature: 0x%llx\n", cnss_priv->dynamic_feature);
  752. return 0;
  753. }
  754. static int cnss_dynamic_feature_open(struct inode *inode,
  755. struct file *file)
  756. {
  757. return single_open(file, cnss_dynamic_feature_show,
  758. inode->i_private);
  759. }
  760. static const struct file_operations cnss_dynamic_feature_fops = {
  761. .read = seq_read,
  762. .write = cnss_dynamic_feature_write,
  763. .open = cnss_dynamic_feature_open,
  764. .owner = THIS_MODULE,
  765. .llseek = seq_lseek,
  766. };
  767. #ifdef CONFIG_DEBUG_FS
  768. #ifdef CONFIG_CNSS2_DEBUG
  769. static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
  770. {
  771. struct dentry *root_dentry = plat_priv->root_dentry;
  772. debugfs_create_file("dev_boot", 0600, root_dentry, plat_priv,
  773. &cnss_dev_boot_debug_fops);
  774. debugfs_create_file("reg_read", 0600, root_dentry, plat_priv,
  775. &cnss_reg_read_debug_fops);
  776. debugfs_create_file("reg_write", 0600, root_dentry, plat_priv,
  777. &cnss_reg_write_debug_fops);
  778. debugfs_create_file("runtime_pm", 0600, root_dentry, plat_priv,
  779. &cnss_runtime_pm_debug_fops);
  780. debugfs_create_file("control_params", 0600, root_dentry, plat_priv,
  781. &cnss_control_params_debug_fops);
  782. debugfs_create_file("dynamic_feature", 0600, root_dentry, plat_priv,
  783. &cnss_dynamic_feature_fops);
  784. return 0;
  785. }
  786. #else
  787. static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
  788. {
  789. return 0;
  790. }
  791. #endif
  792. int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
  793. {
  794. int ret = 0;
  795. struct dentry *root_dentry;
  796. root_dentry = debugfs_create_dir("cnss", 0);
  797. if (IS_ERR(root_dentry)) {
  798. ret = PTR_ERR(root_dentry);
  799. cnss_pr_err("Unable to create debugfs %d\n", ret);
  800. goto out;
  801. }
  802. plat_priv->root_dentry = root_dentry;
  803. debugfs_create_file("pin_connect_result", 0644, root_dentry, plat_priv,
  804. &cnss_pin_connect_fops);
  805. debugfs_create_file("stats", 0644, root_dentry, plat_priv,
  806. &cnss_stats_fops);
  807. cnss_create_debug_only_node(plat_priv);
  808. out:
  809. return ret;
  810. }
  811. void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
  812. {
  813. debugfs_remove_recursive(plat_priv->root_dentry);
  814. }
  815. #else
  816. int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
  817. {
  818. plat_priv->root_dentry = NULL;
  819. return 0;
  820. }
  821. void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
  822. {
  823. }
  824. #endif
  825. #if IS_ENABLED(CONFIG_IPC_LOGGING)
  826. void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
  827. const char *log_level, char *fmt, ...)
  828. {
  829. struct va_format vaf;
  830. va_list va_args;
  831. va_start(va_args, fmt);
  832. vaf.fmt = fmt;
  833. vaf.va = &va_args;
  834. if (log_level)
  835. printk("%scnss: %pV", log_level, &vaf);
  836. ipc_log_string(log_ctx, "[%s] %s: %pV", process, fn, &vaf);
  837. va_end(va_args);
  838. }
  839. static int cnss_ipc_logging_init(void)
  840. {
  841. cnss_ipc_log_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
  842. "cnss", 0);
  843. if (!cnss_ipc_log_context) {
  844. cnss_pr_err("Unable to create IPC log context\n");
  845. return -EINVAL;
  846. }
  847. cnss_ipc_log_long_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
  848. "cnss-long", 0);
  849. if (!cnss_ipc_log_long_context) {
  850. cnss_pr_err("Unable to create IPC long log context\n");
  851. ipc_log_context_destroy(cnss_ipc_log_context);
  852. return -EINVAL;
  853. }
  854. return 0;
  855. }
  856. static void cnss_ipc_logging_deinit(void)
  857. {
  858. if (cnss_ipc_log_long_context) {
  859. ipc_log_context_destroy(cnss_ipc_log_long_context);
  860. cnss_ipc_log_long_context = NULL;
  861. }
  862. if (cnss_ipc_log_context) {
  863. ipc_log_context_destroy(cnss_ipc_log_context);
  864. cnss_ipc_log_context = NULL;
  865. }
  866. }
  867. #else
  868. static int cnss_ipc_logging_init(void) { return 0; }
  869. static void cnss_ipc_logging_deinit(void) {}
  870. void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
  871. const char *log_level, char *fmt, ...)
  872. {
  873. struct va_format vaf;
  874. va_list va_args;
  875. va_start(va_args, fmt);
  876. vaf.fmt = fmt;
  877. vaf.va = &va_args;
  878. if (log_level)
  879. printk("%scnss: %pV", log_level, &vaf);
  880. va_end(va_args);
  881. }
  882. #endif
  883. int cnss_debug_init(void)
  884. {
  885. return cnss_ipc_logging_init();
  886. }
  887. void cnss_debug_deinit(void)
  888. {
  889. cnss_ipc_logging_deinit();
  890. }