sdm660-common.c 95 KB

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  1. /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/input.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/of_device.h>
  17. #include <sound/pcm_params.h>
  18. #include <dsp/q6afe-v2.h>
  19. #include "msm-pcm-routing-v2.h"
  20. #include "sdm660-common.h"
  21. #include "sdm660-internal.h"
  22. #include "sdm660-external.h"
  23. #include "codecs/msm-cdc-pinctrl.h"
  24. #include "codecs/sdm660_cdc/msm-analog-cdc.h"
  25. #include "codecs/wsa881x.h"
  26. #define DRV_NAME "sdm660-asoc-snd"
  27. #define MSM_INT_DIGITAL_CODEC "msm-dig-codec"
  28. #define PMIC_INT_ANALOG_CODEC "analog-codec"
  29. #define DEV_NAME_STR_LEN 32
  30. #define DEFAULT_MCLK_RATE 9600000
  31. struct dev_config {
  32. u32 sample_rate;
  33. u32 bit_format;
  34. u32 channels;
  35. };
  36. enum {
  37. DP_RX_IDX,
  38. EXT_DISP_RX_IDX_MAX,
  39. };
  40. bool codec_reg_done;
  41. /* TDM default config */
  42. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  43. { /* PRI TDM */
  44. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  45. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  46. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  47. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  48. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  49. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  50. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  51. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  52. },
  53. { /* SEC TDM */
  54. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  55. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  56. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  57. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  58. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  59. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  60. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  61. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  62. },
  63. { /* TERT TDM */
  64. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  65. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  66. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  67. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  68. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  69. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  70. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  71. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  72. },
  73. { /* QUAT TDM */
  74. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  75. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  76. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  77. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  78. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  79. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  80. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  81. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  82. },
  83. { /* QUIN TDM */
  84. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  85. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  86. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  87. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  88. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  89. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  90. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  91. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  92. }
  93. };
  94. /* TDM default config */
  95. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  96. { /* PRI TDM */
  97. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  98. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  99. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  100. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  101. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  102. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  103. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  104. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  105. },
  106. { /* SEC TDM */
  107. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  108. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  109. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  110. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  111. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  112. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  113. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  114. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  115. },
  116. { /* TERT TDM */
  117. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  118. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  119. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  120. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  121. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  122. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  123. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  124. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  125. },
  126. { /* QUAT TDM */
  127. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  128. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  129. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  130. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  131. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  132. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  133. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  134. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  135. },
  136. { /* QUIN TDM */
  137. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  138. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  139. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  140. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  141. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  142. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  143. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  144. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  145. }
  146. };
  147. /* Default configuration of external display BE */
  148. static struct dev_config ext_disp_rx_cfg[] = {
  149. [DP_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  150. };
  151. static struct dev_config usb_rx_cfg = {
  152. .sample_rate = SAMPLING_RATE_48KHZ,
  153. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  154. .channels = 2,
  155. };
  156. static struct dev_config usb_tx_cfg = {
  157. .sample_rate = SAMPLING_RATE_48KHZ,
  158. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  159. .channels = 1,
  160. };
  161. enum {
  162. PRIM_AUX_PCM = 0,
  163. SEC_AUX_PCM,
  164. TERT_AUX_PCM,
  165. QUAT_AUX_PCM,
  166. QUIN_AUX_PCM,
  167. AUX_PCM_MAX,
  168. };
  169. enum {
  170. PCM_I2S_SEL_PRIM = 0,
  171. PCM_I2S_SEL_SEC,
  172. PCM_I2S_SEL_TERT,
  173. PCM_I2S_SEL_QUAT,
  174. PCM_I2S_SEL_QUIN,
  175. PCM_I2S_SEL_MAX,
  176. };
  177. struct mi2s_conf {
  178. struct mutex lock;
  179. u32 ref_cnt;
  180. u32 msm_is_mi2s_master;
  181. u32 msm_is_ext_mclk;
  182. };
  183. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  184. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  185. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  186. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  187. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  188. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  189. };
  190. struct msm_wsa881x_dev_info {
  191. struct device_node *of_node;
  192. u32 index;
  193. };
  194. static struct snd_soc_aux_dev *msm_aux_dev;
  195. static struct snd_soc_codec_conf *msm_codec_conf;
  196. static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active);
  197. static struct wcd_mbhc_config mbhc_cfg = {
  198. .read_fw_bin = false,
  199. .calibration = NULL,
  200. .detect_extn_cable = true,
  201. .mono_stero_detection = false,
  202. .swap_gnd_mic = NULL,
  203. .hs_ext_micbias = true,
  204. .key_code[0] = KEY_MEDIA,
  205. .key_code[1] = KEY_VOICECOMMAND,
  206. .key_code[2] = KEY_VOLUMEUP,
  207. .key_code[3] = KEY_VOLUMEDOWN,
  208. .key_code[4] = 0,
  209. .key_code[5] = 0,
  210. .key_code[6] = 0,
  211. .key_code[7] = 0,
  212. .linein_th = 5000,
  213. .moisture_en = false,
  214. .mbhc_micbias = 0,
  215. .anc_micbias = 0,
  216. .enable_anc_mic_detect = false,
  217. };
  218. static struct dev_config proxy_rx_cfg = {
  219. .sample_rate = SAMPLING_RATE_48KHZ,
  220. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  221. .channels = 2,
  222. };
  223. /* Default configuration of MI2S channels */
  224. static struct dev_config mi2s_rx_cfg[] = {
  225. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  226. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  227. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  228. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  229. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  230. };
  231. static struct dev_config mi2s_tx_cfg[] = {
  232. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  233. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  234. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  235. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  236. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  237. };
  238. static struct dev_config aux_pcm_rx_cfg[] = {
  239. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  240. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  241. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  242. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  243. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  244. };
  245. static struct dev_config aux_pcm_tx_cfg[] = {
  246. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  247. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  248. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  249. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  250. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  251. };
  252. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  253. "Six", "Seven", "Eight"};
  254. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  255. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_16",
  256. "KHZ_32", "KHZ_44P1", "KHZ_48",
  257. "KHZ_96", "KHZ_192"};
  258. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  259. "Five", "Six", "Seven",
  260. "Eight"};
  261. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  262. "S32_LE"};
  263. static char const *mi2s_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  264. "S32_LE"};
  265. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  266. "Five", "Six", "Seven", "Eight"};
  267. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  268. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  269. "KHZ_44P1", "KHZ_48", "KHZ_96",
  270. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  271. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  272. "Five", "Six", "Seven",
  273. "Eight"};
  274. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  275. "KHZ_16", "KHZ_22P05",
  276. "KHZ_32", "KHZ_44P1", "KHZ_48",
  277. "KHZ_96", "KHZ_192", "KHZ_384"};
  278. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE"};
  279. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  280. "KHZ_192"};
  281. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  282. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  283. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  284. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  285. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  286. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  287. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  288. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  289. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  290. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  291. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  292. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  293. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  294. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  295. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  296. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  297. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  298. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  299. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  300. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  301. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  302. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  303. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_format, mi2s_format_text);
  304. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_format, mi2s_format_text);
  305. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_format, mi2s_format_text);
  306. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_format, mi2s_format_text);
  307. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_format, mi2s_format_text);
  308. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_format, mi2s_format_text);
  309. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_format, mi2s_format_text);
  310. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_format, mi2s_format_text);
  311. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_format, mi2s_format_text);
  312. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_format, mi2s_format_text);
  313. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  314. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  315. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  316. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  317. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  318. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  319. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  320. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  321. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  322. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  323. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  324. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  325. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  326. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  327. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  328. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  329. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  330. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  331. ext_disp_sample_rate_text);
  332. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  333. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  334. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  335. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  336. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  337. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  338. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  339. {
  340. AFE_API_VERSION_I2S_CONFIG,
  341. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  342. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  343. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  344. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  345. 0,
  346. },
  347. {
  348. AFE_API_VERSION_I2S_CONFIG,
  349. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  350. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  351. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  352. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  353. 0,
  354. },
  355. {
  356. AFE_API_VERSION_I2S_CONFIG,
  357. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  358. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  359. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  360. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  361. 0,
  362. },
  363. {
  364. AFE_API_VERSION_I2S_CONFIG,
  365. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  366. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  367. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  368. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  369. 0,
  370. },
  371. {
  372. AFE_API_VERSION_I2S_CONFIG,
  373. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  374. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  375. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  376. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  377. 0,
  378. }
  379. };
  380. static struct afe_clk_set mi2s_mclk[MI2S_MAX] = {
  381. {
  382. AFE_API_VERSION_I2S_CONFIG,
  383. Q6AFE_LPASS_CLK_ID_MCLK_3,
  384. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  385. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  386. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  387. 0,
  388. },
  389. {
  390. AFE_API_VERSION_I2S_CONFIG,
  391. Q6AFE_LPASS_CLK_ID_MCLK_2,
  392. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  393. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  394. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  395. 0,
  396. },
  397. {
  398. AFE_API_VERSION_I2S_CONFIG,
  399. Q6AFE_LPASS_CLK_ID_MCLK_1,
  400. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  401. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  402. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  403. 0,
  404. },
  405. {
  406. AFE_API_VERSION_I2S_CONFIG,
  407. Q6AFE_LPASS_CLK_ID_MCLK_1,
  408. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  409. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  410. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  411. 0,
  412. },
  413. {
  414. AFE_API_VERSION_I2S_CONFIG,
  415. Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR,
  416. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  417. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  418. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  419. 0,
  420. }
  421. };
  422. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  423. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  424. struct snd_ctl_elem_value *ucontrol)
  425. {
  426. pr_debug("%s: proxy_rx channels = %d\n",
  427. __func__, proxy_rx_cfg.channels);
  428. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  429. return 0;
  430. }
  431. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  432. struct snd_ctl_elem_value *ucontrol)
  433. {
  434. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  435. pr_debug("%s: proxy_rx channels = %d\n",
  436. __func__, proxy_rx_cfg.channels);
  437. return 1;
  438. }
  439. static int tdm_get_sample_rate(int value)
  440. {
  441. int sample_rate = 0;
  442. switch (value) {
  443. case 0:
  444. sample_rate = SAMPLING_RATE_8KHZ;
  445. break;
  446. case 1:
  447. sample_rate = SAMPLING_RATE_16KHZ;
  448. break;
  449. case 2:
  450. sample_rate = SAMPLING_RATE_32KHZ;
  451. break;
  452. case 3:
  453. sample_rate = SAMPLING_RATE_44P1KHZ;
  454. break;
  455. case 4:
  456. sample_rate = SAMPLING_RATE_48KHZ;
  457. break;
  458. case 5:
  459. sample_rate = SAMPLING_RATE_96KHZ;
  460. break;
  461. case 6:
  462. sample_rate = SAMPLING_RATE_192KHZ;
  463. break;
  464. case 7:
  465. sample_rate = SAMPLING_RATE_352P8KHZ;
  466. break;
  467. case 8:
  468. sample_rate = SAMPLING_RATE_384KHZ;
  469. break;
  470. default:
  471. sample_rate = SAMPLING_RATE_48KHZ;
  472. break;
  473. }
  474. return sample_rate;
  475. }
  476. static int tdm_get_sample_rate_val(int sample_rate)
  477. {
  478. int sample_rate_val = 0;
  479. switch (sample_rate) {
  480. case SAMPLING_RATE_8KHZ:
  481. sample_rate_val = 0;
  482. break;
  483. case SAMPLING_RATE_16KHZ:
  484. sample_rate_val = 1;
  485. break;
  486. case SAMPLING_RATE_32KHZ:
  487. sample_rate_val = 2;
  488. break;
  489. case SAMPLING_RATE_44P1KHZ:
  490. sample_rate_val = 3;
  491. break;
  492. case SAMPLING_RATE_48KHZ:
  493. sample_rate_val = 4;
  494. break;
  495. case SAMPLING_RATE_96KHZ:
  496. sample_rate_val = 5;
  497. break;
  498. case SAMPLING_RATE_192KHZ:
  499. sample_rate_val = 6;
  500. break;
  501. case SAMPLING_RATE_352P8KHZ:
  502. sample_rate_val = 7;
  503. break;
  504. case SAMPLING_RATE_384KHZ:
  505. sample_rate_val = 8;
  506. break;
  507. default:
  508. sample_rate_val = 4;
  509. break;
  510. }
  511. return sample_rate_val;
  512. }
  513. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  514. struct tdm_port *port)
  515. {
  516. if (port) {
  517. if (strnstr(kcontrol->id.name, "PRI",
  518. sizeof(kcontrol->id.name))) {
  519. port->mode = TDM_PRI;
  520. } else if (strnstr(kcontrol->id.name, "SEC",
  521. sizeof(kcontrol->id.name))) {
  522. port->mode = TDM_SEC;
  523. } else if (strnstr(kcontrol->id.name, "TERT",
  524. sizeof(kcontrol->id.name))) {
  525. port->mode = TDM_TERT;
  526. } else if (strnstr(kcontrol->id.name, "QUAT",
  527. sizeof(kcontrol->id.name))) {
  528. port->mode = TDM_QUAT;
  529. } else if (strnstr(kcontrol->id.name, "QUIN",
  530. sizeof(kcontrol->id.name))) {
  531. port->mode = TDM_QUIN;
  532. } else {
  533. pr_err("%s: unsupported mode in: %s",
  534. __func__, kcontrol->id.name);
  535. return -EINVAL;
  536. }
  537. if (strnstr(kcontrol->id.name, "RX_0",
  538. sizeof(kcontrol->id.name)) ||
  539. strnstr(kcontrol->id.name, "TX_0",
  540. sizeof(kcontrol->id.name))) {
  541. port->channel = TDM_0;
  542. } else if (strnstr(kcontrol->id.name, "RX_1",
  543. sizeof(kcontrol->id.name)) ||
  544. strnstr(kcontrol->id.name, "TX_1",
  545. sizeof(kcontrol->id.name))) {
  546. port->channel = TDM_1;
  547. } else if (strnstr(kcontrol->id.name, "RX_2",
  548. sizeof(kcontrol->id.name)) ||
  549. strnstr(kcontrol->id.name, "TX_2",
  550. sizeof(kcontrol->id.name))) {
  551. port->channel = TDM_2;
  552. } else if (strnstr(kcontrol->id.name, "RX_3",
  553. sizeof(kcontrol->id.name)) ||
  554. strnstr(kcontrol->id.name, "TX_3",
  555. sizeof(kcontrol->id.name))) {
  556. port->channel = TDM_3;
  557. } else if (strnstr(kcontrol->id.name, "RX_4",
  558. sizeof(kcontrol->id.name)) ||
  559. strnstr(kcontrol->id.name, "TX_4",
  560. sizeof(kcontrol->id.name))) {
  561. port->channel = TDM_4;
  562. } else if (strnstr(kcontrol->id.name, "RX_5",
  563. sizeof(kcontrol->id.name)) ||
  564. strnstr(kcontrol->id.name, "TX_5",
  565. sizeof(kcontrol->id.name))) {
  566. port->channel = TDM_5;
  567. } else if (strnstr(kcontrol->id.name, "RX_6",
  568. sizeof(kcontrol->id.name)) ||
  569. strnstr(kcontrol->id.name, "TX_6",
  570. sizeof(kcontrol->id.name))) {
  571. port->channel = TDM_6;
  572. } else if (strnstr(kcontrol->id.name, "RX_7",
  573. sizeof(kcontrol->id.name)) ||
  574. strnstr(kcontrol->id.name, "TX_7",
  575. sizeof(kcontrol->id.name))) {
  576. port->channel = TDM_7;
  577. } else {
  578. pr_err("%s: unsupported channel in: %s",
  579. __func__, kcontrol->id.name);
  580. return -EINVAL;
  581. }
  582. } else
  583. return -EINVAL;
  584. return 0;
  585. }
  586. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  587. struct snd_ctl_elem_value *ucontrol)
  588. {
  589. struct tdm_port port;
  590. int ret = tdm_get_port_idx(kcontrol, &port);
  591. if (ret) {
  592. pr_err("%s: unsupported control: %s",
  593. __func__, kcontrol->id.name);
  594. } else {
  595. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  596. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  597. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  598. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  599. ucontrol->value.enumerated.item[0]);
  600. }
  601. return ret;
  602. }
  603. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  604. struct snd_ctl_elem_value *ucontrol)
  605. {
  606. struct tdm_port port;
  607. int ret = tdm_get_port_idx(kcontrol, &port);
  608. if (ret) {
  609. pr_err("%s: unsupported control: %s",
  610. __func__, kcontrol->id.name);
  611. } else {
  612. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  613. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  614. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  615. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  616. ucontrol->value.enumerated.item[0]);
  617. }
  618. return ret;
  619. }
  620. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  621. struct snd_ctl_elem_value *ucontrol)
  622. {
  623. struct tdm_port port;
  624. int ret = tdm_get_port_idx(kcontrol, &port);
  625. if (ret) {
  626. pr_err("%s: unsupported control: %s",
  627. __func__, kcontrol->id.name);
  628. } else {
  629. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  630. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  631. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  632. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  633. ucontrol->value.enumerated.item[0]);
  634. }
  635. return ret;
  636. }
  637. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  638. struct snd_ctl_elem_value *ucontrol)
  639. {
  640. struct tdm_port port;
  641. int ret = tdm_get_port_idx(kcontrol, &port);
  642. if (ret) {
  643. pr_err("%s: unsupported control: %s",
  644. __func__, kcontrol->id.name);
  645. } else {
  646. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  647. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  648. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  649. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  650. ucontrol->value.enumerated.item[0]);
  651. }
  652. return ret;
  653. }
  654. static int tdm_get_format(int value)
  655. {
  656. int format = 0;
  657. switch (value) {
  658. case 0:
  659. format = SNDRV_PCM_FORMAT_S16_LE;
  660. break;
  661. case 1:
  662. format = SNDRV_PCM_FORMAT_S24_LE;
  663. break;
  664. case 2:
  665. format = SNDRV_PCM_FORMAT_S32_LE;
  666. break;
  667. default:
  668. format = SNDRV_PCM_FORMAT_S16_LE;
  669. break;
  670. }
  671. return format;
  672. }
  673. static int tdm_get_format_val(int format)
  674. {
  675. int value = 0;
  676. switch (format) {
  677. case SNDRV_PCM_FORMAT_S16_LE:
  678. value = 0;
  679. break;
  680. case SNDRV_PCM_FORMAT_S24_LE:
  681. value = 1;
  682. break;
  683. case SNDRV_PCM_FORMAT_S32_LE:
  684. value = 2;
  685. break;
  686. default:
  687. value = 0;
  688. break;
  689. }
  690. return value;
  691. }
  692. static int mi2s_get_format(int value)
  693. {
  694. int format = 0;
  695. switch (value) {
  696. case 0:
  697. format = SNDRV_PCM_FORMAT_S16_LE;
  698. break;
  699. case 1:
  700. format = SNDRV_PCM_FORMAT_S24_LE;
  701. break;
  702. case 2:
  703. format = SNDRV_PCM_FORMAT_S24_3LE;
  704. break;
  705. case 3:
  706. format = SNDRV_PCM_FORMAT_S32_LE;
  707. break;
  708. default:
  709. format = SNDRV_PCM_FORMAT_S16_LE;
  710. break;
  711. }
  712. return format;
  713. }
  714. static int mi2s_get_format_value(int format)
  715. {
  716. int value = 0;
  717. switch (format) {
  718. case SNDRV_PCM_FORMAT_S16_LE:
  719. value = 0;
  720. break;
  721. case SNDRV_PCM_FORMAT_S24_LE:
  722. value = 1;
  723. break;
  724. case SNDRV_PCM_FORMAT_S24_3LE:
  725. value = 2;
  726. break;
  727. case SNDRV_PCM_FORMAT_S32_LE:
  728. value = 3;
  729. break;
  730. default:
  731. value = 0;
  732. break;
  733. }
  734. return value;
  735. }
  736. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  737. struct snd_ctl_elem_value *ucontrol)
  738. {
  739. struct tdm_port port;
  740. int ret = tdm_get_port_idx(kcontrol, &port);
  741. if (ret) {
  742. pr_err("%s: unsupported control: %s",
  743. __func__, kcontrol->id.name);
  744. } else {
  745. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  746. tdm_rx_cfg[port.mode][port.channel].bit_format);
  747. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  748. tdm_rx_cfg[port.mode][port.channel].bit_format,
  749. ucontrol->value.enumerated.item[0]);
  750. }
  751. return ret;
  752. }
  753. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  754. struct snd_ctl_elem_value *ucontrol)
  755. {
  756. struct tdm_port port;
  757. int ret = tdm_get_port_idx(kcontrol, &port);
  758. if (ret) {
  759. pr_err("%s: unsupported control: %s",
  760. __func__, kcontrol->id.name);
  761. } else {
  762. tdm_rx_cfg[port.mode][port.channel].bit_format =
  763. tdm_get_format(ucontrol->value.enumerated.item[0]);
  764. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  765. tdm_rx_cfg[port.mode][port.channel].bit_format,
  766. ucontrol->value.enumerated.item[0]);
  767. }
  768. return ret;
  769. }
  770. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  771. struct snd_ctl_elem_value *ucontrol)
  772. {
  773. struct tdm_port port;
  774. int ret = tdm_get_port_idx(kcontrol, &port);
  775. if (ret) {
  776. pr_err("%s: unsupported control: %s",
  777. __func__, kcontrol->id.name);
  778. } else {
  779. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  780. tdm_tx_cfg[port.mode][port.channel].bit_format);
  781. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  782. tdm_tx_cfg[port.mode][port.channel].bit_format,
  783. ucontrol->value.enumerated.item[0]);
  784. }
  785. return ret;
  786. }
  787. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  788. struct snd_ctl_elem_value *ucontrol)
  789. {
  790. struct tdm_port port;
  791. int ret = tdm_get_port_idx(kcontrol, &port);
  792. if (ret) {
  793. pr_err("%s: unsupported control: %s",
  794. __func__, kcontrol->id.name);
  795. } else {
  796. tdm_tx_cfg[port.mode][port.channel].bit_format =
  797. tdm_get_format(ucontrol->value.enumerated.item[0]);
  798. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  799. tdm_tx_cfg[port.mode][port.channel].bit_format,
  800. ucontrol->value.enumerated.item[0]);
  801. }
  802. return ret;
  803. }
  804. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  805. struct snd_ctl_elem_value *ucontrol)
  806. {
  807. struct tdm_port port;
  808. int ret = tdm_get_port_idx(kcontrol, &port);
  809. if (ret) {
  810. pr_err("%s: unsupported control: %s",
  811. __func__, kcontrol->id.name);
  812. } else {
  813. ucontrol->value.enumerated.item[0] =
  814. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  815. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  816. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  817. ucontrol->value.enumerated.item[0]);
  818. }
  819. return ret;
  820. }
  821. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  822. struct snd_ctl_elem_value *ucontrol)
  823. {
  824. struct tdm_port port;
  825. int ret = tdm_get_port_idx(kcontrol, &port);
  826. if (ret) {
  827. pr_err("%s: unsupported control: %s",
  828. __func__, kcontrol->id.name);
  829. } else {
  830. tdm_rx_cfg[port.mode][port.channel].channels =
  831. ucontrol->value.enumerated.item[0] + 1;
  832. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  833. tdm_rx_cfg[port.mode][port.channel].channels,
  834. ucontrol->value.enumerated.item[0] + 1);
  835. }
  836. return ret;
  837. }
  838. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  839. struct snd_ctl_elem_value *ucontrol)
  840. {
  841. struct tdm_port port;
  842. int ret = tdm_get_port_idx(kcontrol, &port);
  843. if (ret) {
  844. pr_err("%s: unsupported control: %s",
  845. __func__, kcontrol->id.name);
  846. } else {
  847. ucontrol->value.enumerated.item[0] =
  848. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  849. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  850. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  851. ucontrol->value.enumerated.item[0]);
  852. }
  853. return ret;
  854. }
  855. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  856. struct snd_ctl_elem_value *ucontrol)
  857. {
  858. struct tdm_port port;
  859. int ret = tdm_get_port_idx(kcontrol, &port);
  860. if (ret) {
  861. pr_err("%s: unsupported control: %s",
  862. __func__, kcontrol->id.name);
  863. } else {
  864. tdm_tx_cfg[port.mode][port.channel].channels =
  865. ucontrol->value.enumerated.item[0] + 1;
  866. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  867. tdm_tx_cfg[port.mode][port.channel].channels,
  868. ucontrol->value.enumerated.item[0] + 1);
  869. }
  870. return ret;
  871. }
  872. static int aux_pcm_get_sample_rate(int value)
  873. {
  874. int sample_rate;
  875. switch (value) {
  876. case 1:
  877. sample_rate = SAMPLING_RATE_16KHZ;
  878. break;
  879. case 0:
  880. default:
  881. sample_rate = SAMPLING_RATE_8KHZ;
  882. break;
  883. }
  884. return sample_rate;
  885. }
  886. static int aux_pcm_get_sample_rate_val(int sample_rate)
  887. {
  888. int sample_rate_val;
  889. switch (sample_rate) {
  890. case SAMPLING_RATE_16KHZ:
  891. sample_rate_val = 1;
  892. break;
  893. case SAMPLING_RATE_8KHZ:
  894. default:
  895. sample_rate_val = 0;
  896. break;
  897. }
  898. return sample_rate_val;
  899. }
  900. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  901. {
  902. int idx;
  903. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  904. sizeof("PRIM_AUX_PCM")))
  905. idx = PRIM_AUX_PCM;
  906. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  907. sizeof("SEC_AUX_PCM")))
  908. idx = SEC_AUX_PCM;
  909. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  910. sizeof("TERT_AUX_PCM")))
  911. idx = TERT_AUX_PCM;
  912. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  913. sizeof("QUAT_AUX_PCM")))
  914. idx = QUAT_AUX_PCM;
  915. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  916. sizeof("QUIN_AUX_PCM")))
  917. idx = QUIN_AUX_PCM;
  918. else {
  919. pr_err("%s: unsupported port: %s",
  920. __func__, kcontrol->id.name);
  921. idx = -EINVAL;
  922. }
  923. return idx;
  924. }
  925. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  926. struct snd_ctl_elem_value *ucontrol)
  927. {
  928. int idx = aux_pcm_get_port_idx(kcontrol);
  929. if (idx < 0)
  930. return idx;
  931. aux_pcm_rx_cfg[idx].sample_rate =
  932. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  933. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  934. idx, aux_pcm_rx_cfg[idx].sample_rate,
  935. ucontrol->value.enumerated.item[0]);
  936. return 0;
  937. }
  938. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  939. struct snd_ctl_elem_value *ucontrol)
  940. {
  941. int idx = aux_pcm_get_port_idx(kcontrol);
  942. if (idx < 0)
  943. return idx;
  944. ucontrol->value.enumerated.item[0] =
  945. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  946. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  947. idx, aux_pcm_rx_cfg[idx].sample_rate,
  948. ucontrol->value.enumerated.item[0]);
  949. return 0;
  950. }
  951. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  952. struct snd_ctl_elem_value *ucontrol)
  953. {
  954. int idx = aux_pcm_get_port_idx(kcontrol);
  955. if (idx < 0)
  956. return idx;
  957. aux_pcm_tx_cfg[idx].sample_rate =
  958. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  959. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  960. idx, aux_pcm_tx_cfg[idx].sample_rate,
  961. ucontrol->value.enumerated.item[0]);
  962. return 0;
  963. }
  964. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  965. struct snd_ctl_elem_value *ucontrol)
  966. {
  967. int idx = aux_pcm_get_port_idx(kcontrol);
  968. if (idx < 0)
  969. return idx;
  970. ucontrol->value.enumerated.item[0] =
  971. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  972. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  973. idx, aux_pcm_tx_cfg[idx].sample_rate,
  974. ucontrol->value.enumerated.item[0]);
  975. return 0;
  976. }
  977. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  978. {
  979. int idx;
  980. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  981. sizeof("PRIM_MI2S_RX")))
  982. idx = PRIM_MI2S;
  983. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  984. sizeof("SEC_MI2S_RX")))
  985. idx = SEC_MI2S;
  986. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  987. sizeof("TERT_MI2S_RX")))
  988. idx = TERT_MI2S;
  989. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  990. sizeof("QUAT_MI2S_RX")))
  991. idx = QUAT_MI2S;
  992. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  993. sizeof("QUIN_MI2S_RX")))
  994. idx = QUIN_MI2S;
  995. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  996. sizeof("PRIM_MI2S_TX")))
  997. idx = PRIM_MI2S;
  998. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  999. sizeof("SEC_MI2S_TX")))
  1000. idx = SEC_MI2S;
  1001. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1002. sizeof("TERT_MI2S_TX")))
  1003. idx = TERT_MI2S;
  1004. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1005. sizeof("QUAT_MI2S_TX")))
  1006. idx = QUAT_MI2S;
  1007. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  1008. sizeof("QUIN_MI2S_TX")))
  1009. idx = QUIN_MI2S;
  1010. else {
  1011. pr_err("%s: unsupported channel: %s",
  1012. __func__, kcontrol->id.name);
  1013. idx = -EINVAL;
  1014. }
  1015. return idx;
  1016. }
  1017. static int mi2s_get_sample_rate_val(int sample_rate)
  1018. {
  1019. int sample_rate_val;
  1020. switch (sample_rate) {
  1021. case SAMPLING_RATE_8KHZ:
  1022. sample_rate_val = 0;
  1023. break;
  1024. case SAMPLING_RATE_16KHZ:
  1025. sample_rate_val = 1;
  1026. break;
  1027. case SAMPLING_RATE_32KHZ:
  1028. sample_rate_val = 2;
  1029. break;
  1030. case SAMPLING_RATE_44P1KHZ:
  1031. sample_rate_val = 3;
  1032. break;
  1033. case SAMPLING_RATE_48KHZ:
  1034. sample_rate_val = 4;
  1035. break;
  1036. case SAMPLING_RATE_96KHZ:
  1037. sample_rate_val = 5;
  1038. break;
  1039. case SAMPLING_RATE_192KHZ:
  1040. sample_rate_val = 6;
  1041. break;
  1042. default:
  1043. sample_rate_val = 4;
  1044. break;
  1045. }
  1046. return sample_rate_val;
  1047. }
  1048. static int mi2s_get_sample_rate(int value)
  1049. {
  1050. int sample_rate;
  1051. switch (value) {
  1052. case 0:
  1053. sample_rate = SAMPLING_RATE_8KHZ;
  1054. break;
  1055. case 1:
  1056. sample_rate = SAMPLING_RATE_16KHZ;
  1057. break;
  1058. case 2:
  1059. sample_rate = SAMPLING_RATE_32KHZ;
  1060. break;
  1061. case 3:
  1062. sample_rate = SAMPLING_RATE_44P1KHZ;
  1063. break;
  1064. case 4:
  1065. sample_rate = SAMPLING_RATE_48KHZ;
  1066. break;
  1067. case 5:
  1068. sample_rate = SAMPLING_RATE_96KHZ;
  1069. break;
  1070. case 6:
  1071. sample_rate = SAMPLING_RATE_192KHZ;
  1072. break;
  1073. default:
  1074. sample_rate = SAMPLING_RATE_48KHZ;
  1075. break;
  1076. }
  1077. return sample_rate;
  1078. }
  1079. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1080. struct snd_ctl_elem_value *ucontrol)
  1081. {
  1082. int idx = mi2s_get_port_idx(kcontrol);
  1083. if (idx < 0)
  1084. return idx;
  1085. mi2s_rx_cfg[idx].sample_rate =
  1086. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1087. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1088. idx, mi2s_rx_cfg[idx].sample_rate,
  1089. ucontrol->value.enumerated.item[0]);
  1090. return 0;
  1091. }
  1092. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1093. struct snd_ctl_elem_value *ucontrol)
  1094. {
  1095. int idx = mi2s_get_port_idx(kcontrol);
  1096. if (idx < 0)
  1097. return idx;
  1098. ucontrol->value.enumerated.item[0] =
  1099. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1100. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1101. idx, mi2s_rx_cfg[idx].sample_rate,
  1102. ucontrol->value.enumerated.item[0]);
  1103. return 0;
  1104. }
  1105. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1106. struct snd_ctl_elem_value *ucontrol)
  1107. {
  1108. int idx = mi2s_get_port_idx(kcontrol);
  1109. if (idx < 0)
  1110. return idx;
  1111. mi2s_tx_cfg[idx].sample_rate =
  1112. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1113. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1114. idx, mi2s_tx_cfg[idx].sample_rate,
  1115. ucontrol->value.enumerated.item[0]);
  1116. return 0;
  1117. }
  1118. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1119. struct snd_ctl_elem_value *ucontrol)
  1120. {
  1121. int idx = mi2s_get_port_idx(kcontrol);
  1122. if (idx < 0)
  1123. return idx;
  1124. ucontrol->value.enumerated.item[0] =
  1125. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1126. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1127. idx, mi2s_tx_cfg[idx].sample_rate,
  1128. ucontrol->value.enumerated.item[0]);
  1129. return 0;
  1130. }
  1131. static int mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  1132. struct snd_ctl_elem_value *ucontrol)
  1133. {
  1134. int idx = mi2s_get_port_idx(kcontrol);
  1135. if (idx < 0)
  1136. return idx;
  1137. mi2s_tx_cfg[idx].bit_format =
  1138. mi2s_get_format(ucontrol->value.enumerated.item[0]);
  1139. pr_debug("%s: idx[%d] _tx_format = %d, item = %d\n", __func__,
  1140. idx, mi2s_tx_cfg[idx].bit_format,
  1141. ucontrol->value.enumerated.item[0]);
  1142. return 0;
  1143. }
  1144. static int mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1145. struct snd_ctl_elem_value *ucontrol)
  1146. {
  1147. int idx = mi2s_get_port_idx(kcontrol);
  1148. if (idx < 0)
  1149. return idx;
  1150. ucontrol->value.enumerated.item[0] =
  1151. mi2s_get_format_value(mi2s_tx_cfg[idx].bit_format);
  1152. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1153. idx, mi2s_tx_cfg[idx].bit_format,
  1154. ucontrol->value.enumerated.item[0]);
  1155. return 0;
  1156. }
  1157. static int mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1158. struct snd_ctl_elem_value *ucontrol)
  1159. {
  1160. int idx = mi2s_get_port_idx(kcontrol);
  1161. if (idx < 0)
  1162. return idx;
  1163. mi2s_rx_cfg[idx].bit_format =
  1164. mi2s_get_format(ucontrol->value.enumerated.item[0]);
  1165. pr_debug("%s: idx[%d] _rx_format = %d, item = %d\n", __func__,
  1166. idx, mi2s_rx_cfg[idx].bit_format,
  1167. ucontrol->value.enumerated.item[0]);
  1168. return 0;
  1169. }
  1170. static int mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1171. struct snd_ctl_elem_value *ucontrol)
  1172. {
  1173. int idx = mi2s_get_port_idx(kcontrol);
  1174. if (idx < 0)
  1175. return idx;
  1176. ucontrol->value.enumerated.item[0] =
  1177. mi2s_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1178. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1179. idx, mi2s_rx_cfg[idx].bit_format,
  1180. ucontrol->value.enumerated.item[0]);
  1181. return 0;
  1182. }
  1183. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  1184. struct snd_ctl_elem_value *ucontrol)
  1185. {
  1186. int idx = mi2s_get_port_idx(kcontrol);
  1187. if (idx < 0)
  1188. return idx;
  1189. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1190. idx, mi2s_rx_cfg[idx].channels);
  1191. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  1192. return 0;
  1193. }
  1194. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  1195. struct snd_ctl_elem_value *ucontrol)
  1196. {
  1197. int idx = mi2s_get_port_idx(kcontrol);
  1198. if (idx < 0)
  1199. return idx;
  1200. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1201. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1202. idx, mi2s_rx_cfg[idx].channels);
  1203. return 1;
  1204. }
  1205. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  1206. struct snd_ctl_elem_value *ucontrol)
  1207. {
  1208. int idx = mi2s_get_port_idx(kcontrol);
  1209. if (idx < 0)
  1210. return idx;
  1211. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1212. idx, mi2s_tx_cfg[idx].channels);
  1213. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  1214. return 0;
  1215. }
  1216. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  1217. struct snd_ctl_elem_value *ucontrol)
  1218. {
  1219. int idx = mi2s_get_port_idx(kcontrol);
  1220. if (idx < 0)
  1221. return idx;
  1222. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1223. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1224. idx, mi2s_tx_cfg[idx].channels);
  1225. return 1;
  1226. }
  1227. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1228. struct snd_ctl_elem_value *ucontrol)
  1229. {
  1230. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1231. usb_rx_cfg.channels);
  1232. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1233. return 0;
  1234. }
  1235. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1236. struct snd_ctl_elem_value *ucontrol)
  1237. {
  1238. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1239. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1240. return 1;
  1241. }
  1242. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1243. struct snd_ctl_elem_value *ucontrol)
  1244. {
  1245. int sample_rate_val;
  1246. switch (usb_rx_cfg.sample_rate) {
  1247. case SAMPLING_RATE_384KHZ:
  1248. sample_rate_val = 9;
  1249. break;
  1250. case SAMPLING_RATE_192KHZ:
  1251. sample_rate_val = 8;
  1252. break;
  1253. case SAMPLING_RATE_96KHZ:
  1254. sample_rate_val = 7;
  1255. break;
  1256. case SAMPLING_RATE_48KHZ:
  1257. sample_rate_val = 6;
  1258. break;
  1259. case SAMPLING_RATE_44P1KHZ:
  1260. sample_rate_val = 5;
  1261. break;
  1262. case SAMPLING_RATE_32KHZ:
  1263. sample_rate_val = 4;
  1264. break;
  1265. case SAMPLING_RATE_22P05KHZ:
  1266. sample_rate_val = 3;
  1267. break;
  1268. case SAMPLING_RATE_16KHZ:
  1269. sample_rate_val = 2;
  1270. break;
  1271. case SAMPLING_RATE_11P025KHZ:
  1272. sample_rate_val = 1;
  1273. break;
  1274. case SAMPLING_RATE_8KHZ:
  1275. default:
  1276. sample_rate_val = 0;
  1277. break;
  1278. }
  1279. ucontrol->value.integer.value[0] = sample_rate_val;
  1280. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1281. usb_rx_cfg.sample_rate);
  1282. return 0;
  1283. }
  1284. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1285. struct snd_ctl_elem_value *ucontrol)
  1286. {
  1287. switch (ucontrol->value.integer.value[0]) {
  1288. case 9:
  1289. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1290. break;
  1291. case 8:
  1292. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1293. break;
  1294. case 7:
  1295. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1296. break;
  1297. case 6:
  1298. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1299. break;
  1300. case 5:
  1301. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1302. break;
  1303. case 4:
  1304. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1305. break;
  1306. case 3:
  1307. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1308. break;
  1309. case 2:
  1310. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1311. break;
  1312. case 1:
  1313. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1314. break;
  1315. case 0:
  1316. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1317. break;
  1318. default:
  1319. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1320. break;
  1321. }
  1322. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1323. __func__, ucontrol->value.integer.value[0],
  1324. usb_rx_cfg.sample_rate);
  1325. return 0;
  1326. }
  1327. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1328. struct snd_ctl_elem_value *ucontrol)
  1329. {
  1330. switch (usb_rx_cfg.bit_format) {
  1331. case SNDRV_PCM_FORMAT_S32_LE:
  1332. ucontrol->value.integer.value[0] = 3;
  1333. break;
  1334. case SNDRV_PCM_FORMAT_S24_3LE:
  1335. ucontrol->value.integer.value[0] = 2;
  1336. break;
  1337. case SNDRV_PCM_FORMAT_S24_LE:
  1338. ucontrol->value.integer.value[0] = 1;
  1339. break;
  1340. case SNDRV_PCM_FORMAT_S16_LE:
  1341. default:
  1342. ucontrol->value.integer.value[0] = 0;
  1343. break;
  1344. }
  1345. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1346. __func__, usb_rx_cfg.bit_format,
  1347. ucontrol->value.integer.value[0]);
  1348. return 0;
  1349. }
  1350. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1351. struct snd_ctl_elem_value *ucontrol)
  1352. {
  1353. int rc = 0;
  1354. switch (ucontrol->value.integer.value[0]) {
  1355. case 3:
  1356. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1357. break;
  1358. case 2:
  1359. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1360. break;
  1361. case 1:
  1362. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1363. break;
  1364. case 0:
  1365. default:
  1366. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1367. break;
  1368. }
  1369. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1370. __func__, usb_rx_cfg.bit_format,
  1371. ucontrol->value.integer.value[0]);
  1372. return rc;
  1373. }
  1374. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1375. struct snd_ctl_elem_value *ucontrol)
  1376. {
  1377. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1378. usb_tx_cfg.channels);
  1379. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1380. return 0;
  1381. }
  1382. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1383. struct snd_ctl_elem_value *ucontrol)
  1384. {
  1385. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1386. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1387. return 1;
  1388. }
  1389. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1390. struct snd_ctl_elem_value *ucontrol)
  1391. {
  1392. int sample_rate_val;
  1393. switch (usb_tx_cfg.sample_rate) {
  1394. case SAMPLING_RATE_384KHZ:
  1395. sample_rate_val = 9;
  1396. break;
  1397. case SAMPLING_RATE_192KHZ:
  1398. sample_rate_val = 8;
  1399. break;
  1400. case SAMPLING_RATE_96KHZ:
  1401. sample_rate_val = 7;
  1402. break;
  1403. case SAMPLING_RATE_48KHZ:
  1404. sample_rate_val = 6;
  1405. break;
  1406. case SAMPLING_RATE_44P1KHZ:
  1407. sample_rate_val = 5;
  1408. break;
  1409. case SAMPLING_RATE_32KHZ:
  1410. sample_rate_val = 4;
  1411. break;
  1412. case SAMPLING_RATE_22P05KHZ:
  1413. sample_rate_val = 3;
  1414. break;
  1415. case SAMPLING_RATE_16KHZ:
  1416. sample_rate_val = 2;
  1417. break;
  1418. case SAMPLING_RATE_11P025KHZ:
  1419. sample_rate_val = 1;
  1420. break;
  1421. case SAMPLING_RATE_8KHZ:
  1422. sample_rate_val = 0;
  1423. break;
  1424. default:
  1425. sample_rate_val = 6;
  1426. break;
  1427. }
  1428. ucontrol->value.integer.value[0] = sample_rate_val;
  1429. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1430. usb_tx_cfg.sample_rate);
  1431. return 0;
  1432. }
  1433. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1434. struct snd_ctl_elem_value *ucontrol)
  1435. {
  1436. switch (ucontrol->value.integer.value[0]) {
  1437. case 9:
  1438. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1439. break;
  1440. case 8:
  1441. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1442. break;
  1443. case 7:
  1444. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1445. break;
  1446. case 6:
  1447. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1448. break;
  1449. case 5:
  1450. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1451. break;
  1452. case 4:
  1453. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1454. break;
  1455. case 3:
  1456. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1457. break;
  1458. case 2:
  1459. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1460. break;
  1461. case 1:
  1462. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1463. break;
  1464. case 0:
  1465. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1466. break;
  1467. default:
  1468. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1469. break;
  1470. }
  1471. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1472. __func__, ucontrol->value.integer.value[0],
  1473. usb_tx_cfg.sample_rate);
  1474. return 0;
  1475. }
  1476. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1477. struct snd_ctl_elem_value *ucontrol)
  1478. {
  1479. switch (usb_tx_cfg.bit_format) {
  1480. case SNDRV_PCM_FORMAT_S32_LE:
  1481. ucontrol->value.integer.value[0] = 3;
  1482. break;
  1483. case SNDRV_PCM_FORMAT_S24_3LE:
  1484. ucontrol->value.integer.value[0] = 2;
  1485. break;
  1486. case SNDRV_PCM_FORMAT_S24_LE:
  1487. ucontrol->value.integer.value[0] = 1;
  1488. break;
  1489. case SNDRV_PCM_FORMAT_S16_LE:
  1490. default:
  1491. ucontrol->value.integer.value[0] = 0;
  1492. break;
  1493. }
  1494. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1495. __func__, usb_tx_cfg.bit_format,
  1496. ucontrol->value.integer.value[0]);
  1497. return 0;
  1498. }
  1499. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1500. struct snd_ctl_elem_value *ucontrol)
  1501. {
  1502. int rc = 0;
  1503. switch (ucontrol->value.integer.value[0]) {
  1504. case 3:
  1505. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1506. break;
  1507. case 2:
  1508. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1509. break;
  1510. case 1:
  1511. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1512. break;
  1513. case 0:
  1514. default:
  1515. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1516. break;
  1517. }
  1518. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1519. __func__, usb_tx_cfg.bit_format,
  1520. ucontrol->value.integer.value[0]);
  1521. return rc;
  1522. }
  1523. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  1524. {
  1525. int idx;
  1526. if (strnstr(kcontrol->id.name, "Display Port RX",
  1527. sizeof("Display Port RX")))
  1528. idx = DP_RX_IDX;
  1529. else {
  1530. pr_err("%s: unsupported BE: %s",
  1531. __func__, kcontrol->id.name);
  1532. idx = -EINVAL;
  1533. }
  1534. return idx;
  1535. }
  1536. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  1537. struct snd_ctl_elem_value *ucontrol)
  1538. {
  1539. int idx = ext_disp_get_port_idx(kcontrol);
  1540. if (idx < 0)
  1541. return idx;
  1542. switch (ext_disp_rx_cfg[idx].bit_format) {
  1543. case SNDRV_PCM_FORMAT_S24_LE:
  1544. ucontrol->value.integer.value[0] = 1;
  1545. break;
  1546. case SNDRV_PCM_FORMAT_S16_LE:
  1547. default:
  1548. ucontrol->value.integer.value[0] = 0;
  1549. break;
  1550. }
  1551. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1552. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1553. ucontrol->value.integer.value[0]);
  1554. return 0;
  1555. }
  1556. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  1557. struct snd_ctl_elem_value *ucontrol)
  1558. {
  1559. int idx = ext_disp_get_port_idx(kcontrol);
  1560. if (idx < 0)
  1561. return idx;
  1562. switch (ucontrol->value.integer.value[0]) {
  1563. case 1:
  1564. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1565. break;
  1566. case 0:
  1567. default:
  1568. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1569. break;
  1570. }
  1571. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1572. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1573. ucontrol->value.integer.value[0]);
  1574. return 0;
  1575. }
  1576. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  1577. struct snd_ctl_elem_value *ucontrol)
  1578. {
  1579. int idx = ext_disp_get_port_idx(kcontrol);
  1580. if (idx < 0)
  1581. return idx;
  1582. ucontrol->value.integer.value[0] =
  1583. ext_disp_rx_cfg[idx].channels - 2;
  1584. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1585. idx, ext_disp_rx_cfg[idx].channels);
  1586. return 0;
  1587. }
  1588. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  1589. struct snd_ctl_elem_value *ucontrol)
  1590. {
  1591. int idx = ext_disp_get_port_idx(kcontrol);
  1592. if (idx < 0)
  1593. return idx;
  1594. ext_disp_rx_cfg[idx].channels =
  1595. ucontrol->value.integer.value[0] + 2;
  1596. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1597. idx, ext_disp_rx_cfg[idx].channels);
  1598. return 1;
  1599. }
  1600. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1601. struct snd_ctl_elem_value *ucontrol)
  1602. {
  1603. int sample_rate_val;
  1604. int idx = ext_disp_get_port_idx(kcontrol);
  1605. if (idx < 0)
  1606. return idx;
  1607. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1608. case SAMPLING_RATE_192KHZ:
  1609. sample_rate_val = 2;
  1610. break;
  1611. case SAMPLING_RATE_96KHZ:
  1612. sample_rate_val = 1;
  1613. break;
  1614. case SAMPLING_RATE_48KHZ:
  1615. default:
  1616. sample_rate_val = 0;
  1617. break;
  1618. }
  1619. ucontrol->value.integer.value[0] = sample_rate_val;
  1620. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1621. idx, ext_disp_rx_cfg[idx].sample_rate);
  1622. return 0;
  1623. }
  1624. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1625. struct snd_ctl_elem_value *ucontrol)
  1626. {
  1627. int idx = ext_disp_get_port_idx(kcontrol);
  1628. if (idx < 0)
  1629. return idx;
  1630. switch (ucontrol->value.integer.value[0]) {
  1631. case 2:
  1632. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1633. break;
  1634. case 1:
  1635. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1636. break;
  1637. case 0:
  1638. default:
  1639. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1640. break;
  1641. }
  1642. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1643. __func__, ucontrol->value.integer.value[0], idx,
  1644. ext_disp_rx_cfg[idx].sample_rate);
  1645. return 0;
  1646. }
  1647. const struct snd_kcontrol_new msm_common_snd_controls[] = {
  1648. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  1649. proxy_rx_ch_get, proxy_rx_ch_put),
  1650. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  1651. aux_pcm_rx_sample_rate_get,
  1652. aux_pcm_rx_sample_rate_put),
  1653. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  1654. aux_pcm_rx_sample_rate_get,
  1655. aux_pcm_rx_sample_rate_put),
  1656. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  1657. aux_pcm_rx_sample_rate_get,
  1658. aux_pcm_rx_sample_rate_put),
  1659. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  1660. aux_pcm_rx_sample_rate_get,
  1661. aux_pcm_rx_sample_rate_put),
  1662. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  1663. aux_pcm_rx_sample_rate_get,
  1664. aux_pcm_rx_sample_rate_put),
  1665. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  1666. aux_pcm_tx_sample_rate_get,
  1667. aux_pcm_tx_sample_rate_put),
  1668. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  1669. aux_pcm_tx_sample_rate_get,
  1670. aux_pcm_tx_sample_rate_put),
  1671. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  1672. aux_pcm_tx_sample_rate_get,
  1673. aux_pcm_tx_sample_rate_put),
  1674. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  1675. aux_pcm_tx_sample_rate_get,
  1676. aux_pcm_tx_sample_rate_put),
  1677. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  1678. aux_pcm_tx_sample_rate_get,
  1679. aux_pcm_tx_sample_rate_put),
  1680. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  1681. mi2s_rx_sample_rate_get,
  1682. mi2s_rx_sample_rate_put),
  1683. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  1684. mi2s_rx_sample_rate_get,
  1685. mi2s_rx_sample_rate_put),
  1686. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  1687. mi2s_rx_sample_rate_get,
  1688. mi2s_rx_sample_rate_put),
  1689. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  1690. mi2s_rx_sample_rate_get,
  1691. mi2s_rx_sample_rate_put),
  1692. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  1693. mi2s_rx_sample_rate_get,
  1694. mi2s_rx_sample_rate_put),
  1695. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  1696. mi2s_tx_sample_rate_get,
  1697. mi2s_tx_sample_rate_put),
  1698. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  1699. mi2s_tx_sample_rate_get,
  1700. mi2s_tx_sample_rate_put),
  1701. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  1702. mi2s_tx_sample_rate_get,
  1703. mi2s_tx_sample_rate_put),
  1704. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  1705. mi2s_tx_sample_rate_get,
  1706. mi2s_tx_sample_rate_put),
  1707. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  1708. mi2s_tx_sample_rate_get,
  1709. mi2s_tx_sample_rate_put),
  1710. SOC_ENUM_EXT("PRIM_MI2S_RX Format", prim_mi2s_rx_format,
  1711. mi2s_rx_format_get,
  1712. mi2s_rx_format_put),
  1713. SOC_ENUM_EXT("SEC_MI2S_RX Format", sec_mi2s_rx_format,
  1714. mi2s_rx_format_get,
  1715. mi2s_rx_format_put),
  1716. SOC_ENUM_EXT("TERT_MI2S_RX Format", tert_mi2s_rx_format,
  1717. mi2s_rx_format_get,
  1718. mi2s_rx_format_put),
  1719. SOC_ENUM_EXT("QUAT_MI2S_RX Format", quat_mi2s_rx_format,
  1720. mi2s_rx_format_get,
  1721. mi2s_rx_format_put),
  1722. SOC_ENUM_EXT("QUIN_MI2S_RX Format", quin_mi2s_rx_format,
  1723. mi2s_rx_format_get,
  1724. mi2s_rx_format_put),
  1725. SOC_ENUM_EXT("PRIM_MI2S_TX Format", prim_mi2s_tx_format,
  1726. mi2s_tx_format_get,
  1727. mi2s_tx_format_put),
  1728. SOC_ENUM_EXT("SEC_MI2S_TX Format", sec_mi2s_tx_format,
  1729. mi2s_tx_format_get,
  1730. mi2s_tx_format_put),
  1731. SOC_ENUM_EXT("TERT_MI2S_TX Format", tert_mi2s_tx_format,
  1732. mi2s_tx_format_get,
  1733. mi2s_tx_format_put),
  1734. SOC_ENUM_EXT("QUAT_MI2S_TX Format", quat_mi2s_tx_format,
  1735. mi2s_tx_format_get,
  1736. mi2s_tx_format_put),
  1737. SOC_ENUM_EXT("QUIN_MI2S_TX Format", quin_mi2s_tx_format,
  1738. mi2s_tx_format_get,
  1739. mi2s_tx_format_put),
  1740. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  1741. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1742. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  1743. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1744. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  1745. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1746. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  1747. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1748. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  1749. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1750. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  1751. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1752. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  1753. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1754. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  1755. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1756. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  1757. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1758. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  1759. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1760. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  1761. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  1762. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  1763. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  1764. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  1765. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  1766. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  1767. usb_audio_rx_format_get, usb_audio_rx_format_put),
  1768. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  1769. usb_audio_tx_format_get, usb_audio_tx_format_put),
  1770. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  1771. ext_disp_rx_format_get, ext_disp_rx_format_put),
  1772. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  1773. usb_audio_rx_sample_rate_get,
  1774. usb_audio_rx_sample_rate_put),
  1775. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  1776. usb_audio_tx_sample_rate_get,
  1777. usb_audio_tx_sample_rate_put),
  1778. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  1779. ext_disp_rx_sample_rate_get,
  1780. ext_disp_rx_sample_rate_put),
  1781. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1782. tdm_rx_sample_rate_get,
  1783. tdm_rx_sample_rate_put),
  1784. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1785. tdm_tx_sample_rate_get,
  1786. tdm_tx_sample_rate_put),
  1787. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  1788. tdm_rx_format_get,
  1789. tdm_rx_format_put),
  1790. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  1791. tdm_tx_format_get,
  1792. tdm_tx_format_put),
  1793. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  1794. tdm_rx_ch_get,
  1795. tdm_rx_ch_put),
  1796. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  1797. tdm_tx_ch_get,
  1798. tdm_tx_ch_put),
  1799. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1800. tdm_rx_sample_rate_get,
  1801. tdm_rx_sample_rate_put),
  1802. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1803. tdm_tx_sample_rate_get,
  1804. tdm_tx_sample_rate_put),
  1805. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  1806. tdm_rx_format_get,
  1807. tdm_rx_format_put),
  1808. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  1809. tdm_tx_format_get,
  1810. tdm_tx_format_put),
  1811. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  1812. tdm_rx_ch_get,
  1813. tdm_rx_ch_put),
  1814. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  1815. tdm_tx_ch_get,
  1816. tdm_tx_ch_put),
  1817. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1818. tdm_rx_sample_rate_get,
  1819. tdm_rx_sample_rate_put),
  1820. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1821. tdm_tx_sample_rate_get,
  1822. tdm_tx_sample_rate_put),
  1823. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  1824. tdm_rx_format_get,
  1825. tdm_rx_format_put),
  1826. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  1827. tdm_tx_format_get,
  1828. tdm_tx_format_put),
  1829. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  1830. tdm_rx_ch_get,
  1831. tdm_rx_ch_put),
  1832. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  1833. tdm_tx_ch_get,
  1834. tdm_tx_ch_put),
  1835. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1836. tdm_rx_sample_rate_get,
  1837. tdm_rx_sample_rate_put),
  1838. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1839. tdm_tx_sample_rate_get,
  1840. tdm_tx_sample_rate_put),
  1841. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  1842. tdm_rx_format_get,
  1843. tdm_rx_format_put),
  1844. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  1845. tdm_tx_format_get,
  1846. tdm_tx_format_put),
  1847. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  1848. tdm_rx_ch_get,
  1849. tdm_rx_ch_put),
  1850. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  1851. tdm_tx_ch_get,
  1852. tdm_tx_ch_put),
  1853. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1854. tdm_rx_sample_rate_get,
  1855. tdm_rx_sample_rate_put),
  1856. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1857. tdm_tx_sample_rate_get,
  1858. tdm_tx_sample_rate_put),
  1859. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  1860. tdm_rx_format_get,
  1861. tdm_rx_format_put),
  1862. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  1863. tdm_tx_format_get,
  1864. tdm_tx_format_put),
  1865. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  1866. tdm_rx_ch_get,
  1867. tdm_rx_ch_put),
  1868. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  1869. tdm_tx_ch_get,
  1870. tdm_tx_ch_put),
  1871. };
  1872. /**
  1873. * msm_common_snd_controls_size - to return controls size
  1874. *
  1875. * Return: returns size of common controls array
  1876. */
  1877. int msm_common_snd_controls_size(void)
  1878. {
  1879. return ARRAY_SIZE(msm_common_snd_controls);
  1880. }
  1881. EXPORT_SYMBOL(msm_common_snd_controls_size);
  1882. void msm_set_codec_reg_done(bool done)
  1883. {
  1884. codec_reg_done = done;
  1885. }
  1886. EXPORT_SYMBOL(msm_set_codec_reg_done);
  1887. static inline int param_is_mask(int p)
  1888. {
  1889. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  1890. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  1891. }
  1892. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  1893. int n)
  1894. {
  1895. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  1896. }
  1897. static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned int bit)
  1898. {
  1899. if (bit >= SNDRV_MASK_MAX)
  1900. return;
  1901. if (param_is_mask(n)) {
  1902. struct snd_mask *m = param_to_mask(p, n);
  1903. m->bits[0] = 0;
  1904. m->bits[1] = 0;
  1905. m->bits[bit >> 5] |= (1 << (bit & 31));
  1906. }
  1907. }
  1908. static int msm_ext_disp_get_idx_from_beid(int32_t id)
  1909. {
  1910. int idx;
  1911. switch (id) {
  1912. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  1913. idx = DP_RX_IDX;
  1914. break;
  1915. default:
  1916. pr_err("%s: Incorrect ext_disp id %d\n", __func__, id);
  1917. idx = -EINVAL;
  1918. break;
  1919. }
  1920. return idx;
  1921. }
  1922. /**
  1923. * msm_common_be_hw_params_fixup - updates settings of ALSA BE hw params.
  1924. *
  1925. * @rtd: runtime dailink instance
  1926. * @params: HW params of associated backend dailink.
  1927. *
  1928. * Returns 0.
  1929. */
  1930. int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  1931. struct snd_pcm_hw_params *params)
  1932. {
  1933. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  1934. struct snd_interval *rate = hw_param_interval(params,
  1935. SNDRV_PCM_HW_PARAM_RATE);
  1936. struct snd_interval *channels = hw_param_interval(params,
  1937. SNDRV_PCM_HW_PARAM_CHANNELS);
  1938. int rc = 0;
  1939. int idx;
  1940. pr_debug("%s: format = %d, rate = %d\n",
  1941. __func__, params_format(params), params_rate(params));
  1942. switch (dai_link->id) {
  1943. case MSM_BACKEND_DAI_USB_RX:
  1944. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1945. usb_rx_cfg.bit_format);
  1946. rate->min = rate->max = usb_rx_cfg.sample_rate;
  1947. channels->min = channels->max = usb_rx_cfg.channels;
  1948. break;
  1949. case MSM_BACKEND_DAI_USB_TX:
  1950. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1951. usb_tx_cfg.bit_format);
  1952. rate->min = rate->max = usb_tx_cfg.sample_rate;
  1953. channels->min = channels->max = usb_tx_cfg.channels;
  1954. break;
  1955. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  1956. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  1957. if (idx < 0) {
  1958. pr_err("%s: Incorrect ext disp idx %d\n",
  1959. __func__, idx);
  1960. rc = idx;
  1961. break;
  1962. }
  1963. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1964. ext_disp_rx_cfg[idx].bit_format);
  1965. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  1966. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  1967. break;
  1968. case MSM_BACKEND_DAI_AFE_PCM_RX:
  1969. channels->min = channels->max = proxy_rx_cfg.channels;
  1970. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  1971. break;
  1972. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  1973. channels->min = channels->max =
  1974. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  1975. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1976. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  1977. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  1978. break;
  1979. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  1980. channels->min = channels->max =
  1981. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  1982. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1983. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  1984. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  1985. break;
  1986. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  1987. channels->min = channels->max =
  1988. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  1989. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1990. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  1991. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  1992. break;
  1993. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  1994. channels->min = channels->max =
  1995. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  1996. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1997. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  1998. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  1999. break;
  2000. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  2001. channels->min = channels->max =
  2002. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  2003. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2004. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  2005. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  2006. break;
  2007. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  2008. channels->min = channels->max =
  2009. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  2010. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2011. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  2012. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  2013. break;
  2014. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  2015. channels->min = channels->max =
  2016. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  2017. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2018. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  2019. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2020. break;
  2021. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  2022. channels->min = channels->max =
  2023. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  2024. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2025. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  2026. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2027. break;
  2028. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  2029. channels->min = channels->max =
  2030. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  2031. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2032. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  2033. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  2034. break;
  2035. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  2036. channels->min = channels->max =
  2037. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  2038. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2039. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  2040. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  2041. break;
  2042. case MSM_BACKEND_DAI_AUXPCM_RX:
  2043. rate->min = rate->max =
  2044. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  2045. channels->min = channels->max =
  2046. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  2047. break;
  2048. case MSM_BACKEND_DAI_AUXPCM_TX:
  2049. rate->min = rate->max =
  2050. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  2051. channels->min = channels->max =
  2052. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  2053. break;
  2054. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  2055. rate->min = rate->max =
  2056. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  2057. channels->min = channels->max =
  2058. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  2059. break;
  2060. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  2061. rate->min = rate->max =
  2062. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  2063. channels->min = channels->max =
  2064. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  2065. break;
  2066. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  2067. rate->min = rate->max =
  2068. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  2069. channels->min = channels->max =
  2070. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  2071. break;
  2072. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  2073. rate->min = rate->max =
  2074. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  2075. channels->min = channels->max =
  2076. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  2077. break;
  2078. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  2079. rate->min = rate->max =
  2080. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  2081. channels->min = channels->max =
  2082. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  2083. break;
  2084. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  2085. rate->min = rate->max =
  2086. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  2087. channels->min = channels->max =
  2088. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  2089. break;
  2090. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  2091. rate->min = rate->max =
  2092. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  2093. channels->min = channels->max =
  2094. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  2095. break;
  2096. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  2097. rate->min = rate->max =
  2098. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  2099. channels->min = channels->max =
  2100. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  2101. break;
  2102. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2103. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  2104. channels->min = channels->max =
  2105. mi2s_rx_cfg[PRIM_MI2S].channels;
  2106. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2107. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  2108. break;
  2109. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2110. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  2111. channels->min = channels->max =
  2112. mi2s_tx_cfg[PRIM_MI2S].channels;
  2113. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2114. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  2115. break;
  2116. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2117. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  2118. channels->min = channels->max =
  2119. mi2s_rx_cfg[SEC_MI2S].channels;
  2120. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2121. mi2s_rx_cfg[SEC_MI2S].bit_format);
  2122. break;
  2123. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2124. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  2125. channels->min = channels->max =
  2126. mi2s_tx_cfg[SEC_MI2S].channels;
  2127. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2128. mi2s_tx_cfg[SEC_MI2S].bit_format);
  2129. break;
  2130. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2131. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  2132. channels->min = channels->max =
  2133. mi2s_rx_cfg[TERT_MI2S].channels;
  2134. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2135. mi2s_rx_cfg[TERT_MI2S].bit_format);
  2136. break;
  2137. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2138. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  2139. channels->min = channels->max =
  2140. mi2s_tx_cfg[TERT_MI2S].channels;
  2141. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2142. mi2s_tx_cfg[TERT_MI2S].bit_format);
  2143. break;
  2144. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2145. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  2146. channels->min = channels->max =
  2147. mi2s_rx_cfg[QUAT_MI2S].channels;
  2148. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2149. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  2150. break;
  2151. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2152. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  2153. channels->min = channels->max =
  2154. mi2s_tx_cfg[QUAT_MI2S].channels;
  2155. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2156. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  2157. break;
  2158. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2159. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  2160. channels->min = channels->max =
  2161. mi2s_rx_cfg[QUIN_MI2S].channels;
  2162. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2163. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  2164. break;
  2165. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2166. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  2167. channels->min = channels->max =
  2168. mi2s_tx_cfg[QUIN_MI2S].channels;
  2169. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2170. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  2171. break;
  2172. default:
  2173. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  2174. break;
  2175. }
  2176. return rc;
  2177. }
  2178. EXPORT_SYMBOL(msm_common_be_hw_params_fixup);
  2179. /**
  2180. * msm_aux_pcm_snd_startup - startup ops of auxpcm.
  2181. *
  2182. * @substream: PCM stream pointer of associated backend dailink
  2183. *
  2184. * Returns 0 on success or -EINVAL on error.
  2185. */
  2186. int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream)
  2187. {
  2188. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2189. dev_dbg(rtd->card->dev,
  2190. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2191. __func__, substream->name, substream->stream,
  2192. rtd->cpu_dai->name, rtd->cpu_dai->id);
  2193. return 0;
  2194. }
  2195. EXPORT_SYMBOL(msm_aux_pcm_snd_startup);
  2196. /**
  2197. * msm_aux_pcm_snd_shutdown - shutdown ops of auxpcm.
  2198. *
  2199. * @substream: PCM stream pointer of associated backend dailink
  2200. */
  2201. void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream)
  2202. {
  2203. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2204. dev_dbg(rtd->card->dev,
  2205. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2206. __func__,
  2207. substream->name, substream->stream,
  2208. rtd->cpu_dai->name, rtd->cpu_dai->id);
  2209. }
  2210. EXPORT_SYMBOL(msm_aux_pcm_snd_shutdown);
  2211. static int msm_get_port_id(int id)
  2212. {
  2213. int afe_port_id;
  2214. switch (id) {
  2215. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2216. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2217. break;
  2218. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2219. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2220. break;
  2221. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2222. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2223. break;
  2224. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2225. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2226. break;
  2227. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2228. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2229. break;
  2230. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2231. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2232. break;
  2233. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2234. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2235. break;
  2236. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2237. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2238. break;
  2239. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2240. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  2241. break;
  2242. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2243. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  2244. break;
  2245. default:
  2246. pr_err("%s: Invalid id: %d\n", __func__, id);
  2247. afe_port_id = -EINVAL;
  2248. }
  2249. return afe_port_id;
  2250. }
  2251. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2252. {
  2253. u32 bit_per_sample;
  2254. switch (bit_format) {
  2255. case SNDRV_PCM_FORMAT_S32_LE:
  2256. case SNDRV_PCM_FORMAT_S24_3LE:
  2257. case SNDRV_PCM_FORMAT_S24_LE:
  2258. bit_per_sample = 32;
  2259. break;
  2260. case SNDRV_PCM_FORMAT_S16_LE:
  2261. default:
  2262. bit_per_sample = 16;
  2263. break;
  2264. }
  2265. return bit_per_sample;
  2266. }
  2267. static void update_mi2s_clk_val(int dai_id, int stream)
  2268. {
  2269. u32 bit_per_sample;
  2270. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2271. bit_per_sample =
  2272. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2273. mi2s_clk[dai_id].clk_freq_in_hz =
  2274. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2275. } else {
  2276. bit_per_sample =
  2277. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2278. mi2s_clk[dai_id].clk_freq_in_hz =
  2279. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2280. }
  2281. }
  2282. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2283. {
  2284. int ret = 0;
  2285. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2286. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2287. int port_id = 0;
  2288. int index = cpu_dai->id;
  2289. port_id = msm_get_port_id(rtd->dai_link->id);
  2290. if (port_id < 0) {
  2291. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2292. ret = port_id;
  2293. goto done;
  2294. }
  2295. if (enable) {
  2296. update_mi2s_clk_val(index, substream->stream);
  2297. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2298. mi2s_clk[index].clk_freq_in_hz);
  2299. }
  2300. mi2s_clk[index].enable = enable;
  2301. ret = afe_set_lpass_clock_v2(port_id,
  2302. &mi2s_clk[index]);
  2303. if (ret < 0) {
  2304. dev_err(rtd->card->dev,
  2305. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2306. __func__, port_id, ret);
  2307. goto done;
  2308. }
  2309. done:
  2310. return ret;
  2311. }
  2312. /**
  2313. * msm_mi2s_snd_startup - startup ops of mi2s.
  2314. *
  2315. * @substream: PCM stream pointer of associated backend dailink
  2316. *
  2317. * Returns 0 on success or -EINVAL on error.
  2318. */
  2319. int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  2320. {
  2321. int ret = 0;
  2322. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2323. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2324. int port_id = msm_get_port_id(rtd->dai_link->id);
  2325. int index = cpu_dai->id;
  2326. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  2327. struct msm_asoc_mach_data *pdata =
  2328. snd_soc_card_get_drvdata(rtd->card);
  2329. dev_dbg(rtd->card->dev,
  2330. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2331. __func__, substream->name, substream->stream,
  2332. cpu_dai->name, cpu_dai->id);
  2333. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  2334. ret = -EINVAL;
  2335. dev_err(rtd->card->dev,
  2336. "%s: CPU DAI id (%d) out of range\n",
  2337. __func__, cpu_dai->id);
  2338. goto done;
  2339. }
  2340. /*
  2341. * Muxtex protection in case the same MI2S
  2342. * interface using for both TX and RX so
  2343. * that the same clock won't be enable twice.
  2344. */
  2345. mutex_lock(&mi2s_intf_conf[index].lock);
  2346. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  2347. /* Check if msm needs to provide the clock to the interface */
  2348. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  2349. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  2350. fmt = SND_SOC_DAIFMT_CBM_CFM;
  2351. }
  2352. ret = msm_mi2s_set_sclk(substream, true);
  2353. if (ret < 0) {
  2354. dev_err(rtd->card->dev,
  2355. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  2356. __func__, ret);
  2357. goto clean_up;
  2358. }
  2359. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  2360. if (ret < 0) {
  2361. dev_err(rtd->card->dev,
  2362. "%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  2363. __func__, index, ret);
  2364. goto clk_off;
  2365. }
  2366. if (mi2s_intf_conf[index].msm_is_ext_mclk) {
  2367. mi2s_mclk[index].enable = 1;
  2368. pr_debug("%s: Enabling mclk, clk_freq_in_hz = %u\n",
  2369. __func__, mi2s_mclk[index].clk_freq_in_hz);
  2370. ret = afe_set_lpass_clock_v2(port_id,
  2371. &mi2s_mclk[index]);
  2372. if (ret < 0) {
  2373. pr_err("%s: afe lpass mclk failed, err:%d\n",
  2374. __func__, ret);
  2375. goto clk_off;
  2376. }
  2377. }
  2378. if (pdata->mi2s_gpio_p[index])
  2379. msm_cdc_pinctrl_select_active_state(
  2380. pdata->mi2s_gpio_p[index]);
  2381. }
  2382. mutex_unlock(&mi2s_intf_conf[index].lock);
  2383. return 0;
  2384. clk_off:
  2385. if (ret < 0)
  2386. msm_mi2s_set_sclk(substream, false);
  2387. clean_up:
  2388. if (ret < 0)
  2389. mi2s_intf_conf[index].ref_cnt--;
  2390. mutex_unlock(&mi2s_intf_conf[index].lock);
  2391. done:
  2392. return ret;
  2393. }
  2394. EXPORT_SYMBOL(msm_mi2s_snd_startup);
  2395. /**
  2396. * msm_mi2s_snd_shutdown - shutdown ops of mi2s.
  2397. *
  2398. * @substream: PCM stream pointer of associated backend dailink
  2399. */
  2400. void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  2401. {
  2402. int ret;
  2403. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2404. int port_id = msm_get_port_id(rtd->dai_link->id);
  2405. int index = rtd->cpu_dai->id;
  2406. struct msm_asoc_mach_data *pdata =
  2407. snd_soc_card_get_drvdata(rtd->card);
  2408. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  2409. substream->name, substream->stream);
  2410. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  2411. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  2412. return;
  2413. }
  2414. mutex_lock(&mi2s_intf_conf[index].lock);
  2415. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  2416. if (pdata->mi2s_gpio_p[index])
  2417. msm_cdc_pinctrl_select_sleep_state(
  2418. pdata->mi2s_gpio_p[index]);
  2419. ret = msm_mi2s_set_sclk(substream, false);
  2420. if (ret < 0) {
  2421. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  2422. __func__, index, ret);
  2423. mi2s_intf_conf[index].ref_cnt++;
  2424. }
  2425. if (mi2s_intf_conf[index].msm_is_ext_mclk) {
  2426. mi2s_mclk[index].enable = 0;
  2427. pr_debug("%s: Disabling mclk, clk_freq_in_hz = %u\n",
  2428. __func__, mi2s_mclk[index].clk_freq_in_hz);
  2429. ret = afe_set_lpass_clock_v2(port_id,
  2430. &mi2s_mclk[index]);
  2431. if (ret < 0) {
  2432. pr_err("%s: mclk disable failed for MCLK (%d); ret=%d\n",
  2433. __func__, index, ret);
  2434. }
  2435. }
  2436. }
  2437. mutex_unlock(&mi2s_intf_conf[index].lock);
  2438. }
  2439. EXPORT_SYMBOL(msm_mi2s_snd_shutdown);
  2440. /* Validate whether US EU switch is present or not */
  2441. static int msm_prepare_us_euro(struct snd_soc_card *card)
  2442. {
  2443. struct msm_asoc_mach_data *pdata =
  2444. snd_soc_card_get_drvdata(card);
  2445. int ret = 0;
  2446. if (pdata->us_euro_gpio >= 0) {
  2447. dev_dbg(card->dev, "%s: us_euro gpio request %d", __func__,
  2448. pdata->us_euro_gpio);
  2449. ret = gpio_request(pdata->us_euro_gpio, "TASHA_CODEC_US_EURO");
  2450. if (ret) {
  2451. dev_err(card->dev,
  2452. "%s: Failed to request codec US/EURO gpio %d error %d\n",
  2453. __func__, pdata->us_euro_gpio, ret);
  2454. }
  2455. }
  2456. return ret;
  2457. }
  2458. static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active)
  2459. {
  2460. struct snd_soc_card *card = codec->component.card;
  2461. struct msm_asoc_mach_data *pdata =
  2462. snd_soc_card_get_drvdata(card);
  2463. int value = 0;
  2464. if (pdata->us_euro_gpio_p) {
  2465. value = msm_cdc_pinctrl_get_state(pdata->us_euro_gpio_p);
  2466. if (value)
  2467. msm_cdc_pinctrl_select_sleep_state(
  2468. pdata->us_euro_gpio_p);
  2469. else
  2470. msm_cdc_pinctrl_select_active_state(
  2471. pdata->us_euro_gpio_p);
  2472. } else if (pdata->us_euro_gpio >= 0) {
  2473. value = gpio_get_value_cansleep(pdata->us_euro_gpio);
  2474. gpio_set_value_cansleep(pdata->us_euro_gpio, !value);
  2475. }
  2476. pr_debug("%s: swap select switch %d to %d\n", __func__, value, !value);
  2477. return true;
  2478. }
  2479. static int msm_populate_dai_link_component_of_node(
  2480. struct msm_asoc_mach_data *pdata,
  2481. struct snd_soc_card *card)
  2482. {
  2483. int i, index, ret = 0;
  2484. struct device *cdev = card->dev;
  2485. struct snd_soc_dai_link *dai_link = card->dai_link;
  2486. struct device_node *phandle;
  2487. if (!cdev) {
  2488. pr_err("%s: Sound card device memory NULL\n", __func__);
  2489. return -ENODEV;
  2490. }
  2491. for (i = 0; i < card->num_links; i++) {
  2492. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  2493. continue;
  2494. /* populate platform_of_node for snd card dai links */
  2495. if (dai_link[i].platform_name &&
  2496. !dai_link[i].platform_of_node) {
  2497. index = of_property_match_string(cdev->of_node,
  2498. "asoc-platform-names",
  2499. dai_link[i].platform_name);
  2500. if (index < 0) {
  2501. pr_err("%s: No match found for platform name: %s\n",
  2502. __func__, dai_link[i].platform_name);
  2503. ret = index;
  2504. goto cpu_dai;
  2505. }
  2506. phandle = of_parse_phandle(cdev->of_node,
  2507. "asoc-platform",
  2508. index);
  2509. if (!phandle) {
  2510. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  2511. __func__, dai_link[i].platform_name,
  2512. index);
  2513. ret = -ENODEV;
  2514. goto err;
  2515. }
  2516. dai_link[i].platform_of_node = phandle;
  2517. dai_link[i].platform_name = NULL;
  2518. }
  2519. cpu_dai:
  2520. /* populate cpu_of_node for snd card dai links */
  2521. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  2522. index = of_property_match_string(cdev->of_node,
  2523. "asoc-cpu-names",
  2524. dai_link[i].cpu_dai_name);
  2525. if (index < 0)
  2526. goto codec_dai;
  2527. phandle = of_parse_phandle(cdev->of_node, "asoc-cpu",
  2528. index);
  2529. if (!phandle) {
  2530. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  2531. __func__, dai_link[i].cpu_dai_name);
  2532. ret = -ENODEV;
  2533. goto err;
  2534. }
  2535. dai_link[i].cpu_of_node = phandle;
  2536. dai_link[i].cpu_dai_name = NULL;
  2537. }
  2538. codec_dai:
  2539. /* populate codec_of_node for snd card dai links */
  2540. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  2541. index = of_property_match_string(cdev->of_node,
  2542. "asoc-codec-names",
  2543. dai_link[i].codec_name);
  2544. if (index < 0)
  2545. continue;
  2546. phandle = of_parse_phandle(cdev->of_node, "asoc-codec",
  2547. index);
  2548. if (!phandle) {
  2549. pr_err("%s: retrieving phandle for codec dai %s failed\n",
  2550. __func__, dai_link[i].codec_name);
  2551. ret = -ENODEV;
  2552. goto err;
  2553. }
  2554. dai_link[i].codec_of_node = phandle;
  2555. dai_link[i].codec_name = NULL;
  2556. }
  2557. if (pdata->snd_card_val == INT_SND_CARD) {
  2558. if ((dai_link[i].id ==
  2559. MSM_BACKEND_DAI_INT0_MI2S_RX) ||
  2560. (dai_link[i].id ==
  2561. MSM_BACKEND_DAI_INT1_MI2S_RX) ||
  2562. (dai_link[i].id ==
  2563. MSM_BACKEND_DAI_INT2_MI2S_TX) ||
  2564. (dai_link[i].id ==
  2565. MSM_BACKEND_DAI_INT3_MI2S_TX)) {
  2566. index = of_property_match_string(cdev->of_node,
  2567. "asoc-codec-names",
  2568. MSM_INT_DIGITAL_CODEC);
  2569. phandle = of_parse_phandle(cdev->of_node,
  2570. "asoc-codec",
  2571. index);
  2572. dai_link[i].codecs[DIG_CDC].of_node = phandle;
  2573. index = of_property_match_string(cdev->of_node,
  2574. "asoc-codec-names",
  2575. PMIC_INT_ANALOG_CODEC);
  2576. phandle = of_parse_phandle(cdev->of_node,
  2577. "asoc-codec",
  2578. index);
  2579. dai_link[i].codecs[ANA_CDC].of_node = phandle;
  2580. }
  2581. }
  2582. }
  2583. err:
  2584. return ret;
  2585. }
  2586. static int msm_wsa881x_init(struct snd_soc_component *component)
  2587. {
  2588. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106};
  2589. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107};
  2590. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  2591. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  2592. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  2593. struct msm_asoc_mach_data *pdata;
  2594. struct snd_soc_dapm_context *dapm =
  2595. snd_soc_codec_get_dapm(codec);
  2596. if (!codec) {
  2597. pr_err("%s codec is NULL\n", __func__);
  2598. return -EINVAL;
  2599. }
  2600. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  2601. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  2602. __func__, codec->component.name);
  2603. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  2604. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  2605. &ch_rate[0]);
  2606. if (dapm->component) {
  2607. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  2608. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  2609. }
  2610. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  2611. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  2612. __func__, codec->component.name);
  2613. wsa881x_set_channel_map(codec, &spkright_ports[0],
  2614. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  2615. &ch_rate[0]);
  2616. if (dapm->component) {
  2617. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  2618. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  2619. }
  2620. } else {
  2621. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  2622. codec->component.name);
  2623. return -EINVAL;
  2624. }
  2625. pdata = snd_soc_card_get_drvdata(component->card);
  2626. if (pdata && pdata->codec_root)
  2627. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  2628. codec);
  2629. return 0;
  2630. }
  2631. static int msm_init_wsa_dev(struct platform_device *pdev,
  2632. struct snd_soc_card *card)
  2633. {
  2634. struct device_node *wsa_of_node;
  2635. u32 wsa_max_devs;
  2636. u32 wsa_dev_cnt;
  2637. char *dev_name_str = NULL;
  2638. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  2639. const char *wsa_auxdev_name_prefix[1];
  2640. int found = 0;
  2641. int i;
  2642. int ret;
  2643. /* Get maximum WSA device count for this platform */
  2644. ret = of_property_read_u32(pdev->dev.of_node,
  2645. "qcom,wsa-max-devs", &wsa_max_devs);
  2646. if (ret) {
  2647. dev_dbg(&pdev->dev,
  2648. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  2649. __func__, pdev->dev.of_node->full_name, ret);
  2650. goto err_dt;
  2651. }
  2652. if (wsa_max_devs == 0) {
  2653. dev_warn(&pdev->dev,
  2654. "%s: Max WSA devices is 0 for this target?\n",
  2655. __func__);
  2656. goto err_dt;
  2657. }
  2658. /* Get count of WSA device phandles for this platform */
  2659. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  2660. "qcom,wsa-devs", NULL);
  2661. if (wsa_dev_cnt == -ENOENT) {
  2662. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  2663. __func__);
  2664. goto err_dt;
  2665. } else if (wsa_dev_cnt <= 0) {
  2666. dev_err(&pdev->dev,
  2667. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  2668. __func__, wsa_dev_cnt);
  2669. ret = -EINVAL;
  2670. goto err_dt;
  2671. }
  2672. /*
  2673. * Expect total phandles count to be NOT less than maximum possible
  2674. * WSA count. However, if it is less, then assign same value to
  2675. * max count as well.
  2676. */
  2677. if (wsa_dev_cnt < wsa_max_devs) {
  2678. dev_dbg(&pdev->dev,
  2679. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  2680. __func__, wsa_max_devs, wsa_dev_cnt);
  2681. wsa_max_devs = wsa_dev_cnt;
  2682. }
  2683. /* Make sure prefix string passed for each WSA device */
  2684. ret = of_property_count_strings(pdev->dev.of_node,
  2685. "qcom,wsa-aux-dev-prefix");
  2686. if (ret != wsa_dev_cnt) {
  2687. dev_err(&pdev->dev,
  2688. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  2689. __func__, wsa_dev_cnt, ret);
  2690. ret = -EINVAL;
  2691. goto err_dt;
  2692. }
  2693. /*
  2694. * Alloc mem to store phandle and index info of WSA device, if already
  2695. * registered with ALSA core
  2696. */
  2697. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  2698. sizeof(struct msm_wsa881x_dev_info),
  2699. GFP_KERNEL);
  2700. if (!wsa881x_dev_info) {
  2701. ret = -ENOMEM;
  2702. goto err_mem;
  2703. }
  2704. /*
  2705. * search and check whether all WSA devices are already
  2706. * registered with ALSA core or not. If found a node, store
  2707. * the node and the index in a local array of struct for later
  2708. * use.
  2709. */
  2710. for (i = 0; i < wsa_dev_cnt; i++) {
  2711. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  2712. "qcom,wsa-devs", i);
  2713. if (unlikely(!wsa_of_node)) {
  2714. /* we should not be here */
  2715. dev_err(&pdev->dev,
  2716. "%s: wsa dev node is not present\n",
  2717. __func__);
  2718. ret = -EINVAL;
  2719. goto err_dev_node;
  2720. }
  2721. if (soc_find_component(wsa_of_node, NULL)) {
  2722. /* WSA device registered with ALSA core */
  2723. wsa881x_dev_info[found].of_node = wsa_of_node;
  2724. wsa881x_dev_info[found].index = i;
  2725. found++;
  2726. if (found == wsa_max_devs)
  2727. break;
  2728. }
  2729. }
  2730. if (found < wsa_max_devs) {
  2731. dev_dbg(&pdev->dev,
  2732. "%s: failed to find %d components. Found only %d\n",
  2733. __func__, wsa_max_devs, found);
  2734. return -EPROBE_DEFER;
  2735. }
  2736. dev_info(&pdev->dev,
  2737. "%s: found %d wsa881x devices registered with ALSA core\n",
  2738. __func__, found);
  2739. card->num_aux_devs = wsa_max_devs;
  2740. card->num_configs = wsa_max_devs;
  2741. /* Alloc array of AUX devs struct */
  2742. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  2743. sizeof(struct snd_soc_aux_dev),
  2744. GFP_KERNEL);
  2745. if (!msm_aux_dev) {
  2746. ret = -ENOMEM;
  2747. goto err_auxdev_mem;
  2748. }
  2749. /* Alloc array of codec conf struct */
  2750. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  2751. sizeof(struct snd_soc_codec_conf),
  2752. GFP_KERNEL);
  2753. if (!msm_codec_conf) {
  2754. ret = -ENOMEM;
  2755. goto err_codec_conf;
  2756. }
  2757. for (i = 0; i < card->num_aux_devs; i++) {
  2758. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  2759. GFP_KERNEL);
  2760. if (!dev_name_str) {
  2761. ret = -ENOMEM;
  2762. goto err_dev_str;
  2763. }
  2764. ret = of_property_read_string_index(pdev->dev.of_node,
  2765. "qcom,wsa-aux-dev-prefix",
  2766. wsa881x_dev_info[i].index,
  2767. wsa_auxdev_name_prefix);
  2768. if (ret) {
  2769. dev_err(&pdev->dev,
  2770. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  2771. __func__, ret);
  2772. ret = -EINVAL;
  2773. goto err_dt_prop;
  2774. }
  2775. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  2776. msm_aux_dev[i].name = dev_name_str;
  2777. msm_aux_dev[i].codec_name = NULL;
  2778. msm_aux_dev[i].codec_of_node =
  2779. wsa881x_dev_info[i].of_node;
  2780. msm_aux_dev[i].init = msm_wsa881x_init;
  2781. msm_codec_conf[i].dev_name = NULL;
  2782. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  2783. msm_codec_conf[i].of_node = wsa881x_dev_info[i].of_node;
  2784. }
  2785. card->codec_conf = msm_codec_conf;
  2786. card->aux_dev = msm_aux_dev;
  2787. return 0;
  2788. err_dt_prop:
  2789. devm_kfree(&pdev->dev, dev_name_str);
  2790. err_dev_str:
  2791. devm_kfree(&pdev->dev, msm_codec_conf);
  2792. err_codec_conf:
  2793. devm_kfree(&pdev->dev, msm_aux_dev);
  2794. err_auxdev_mem:
  2795. err_dev_node:
  2796. devm_kfree(&pdev->dev, wsa881x_dev_info);
  2797. err_mem:
  2798. err_dt:
  2799. return ret;
  2800. }
  2801. static void msm_free_auxdev_mem(struct platform_device *pdev)
  2802. {
  2803. struct snd_soc_card *card = platform_get_drvdata(pdev);
  2804. int i;
  2805. if (card->num_aux_devs > 0) {
  2806. for (i = 0; i < card->num_aux_devs; i++) {
  2807. kfree(msm_aux_dev[i].codec_name);
  2808. kfree(msm_codec_conf[i].dev_name);
  2809. kfree(msm_codec_conf[i].name_prefix);
  2810. }
  2811. }
  2812. }
  2813. static void i2s_auxpcm_init(struct platform_device *pdev)
  2814. {
  2815. int count;
  2816. u32 mi2s_master_slave[MI2S_MAX];
  2817. u32 mi2s_ext_mclk[MI2S_MAX];
  2818. int ret;
  2819. for (count = 0; count < MI2S_MAX; count++) {
  2820. mutex_init(&mi2s_intf_conf[count].lock);
  2821. mi2s_intf_conf[count].ref_cnt = 0;
  2822. }
  2823. ret = of_property_read_u32_array(pdev->dev.of_node,
  2824. "qcom,msm-mi2s-master",
  2825. mi2s_master_slave, MI2S_MAX);
  2826. if (ret) {
  2827. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  2828. __func__);
  2829. } else {
  2830. for (count = 0; count < MI2S_MAX; count++) {
  2831. mi2s_intf_conf[count].msm_is_mi2s_master =
  2832. mi2s_master_slave[count];
  2833. }
  2834. }
  2835. ret = of_property_read_u32_array(pdev->dev.of_node,
  2836. "qcom,msm-mi2s-ext-mclk",
  2837. mi2s_ext_mclk, MI2S_MAX);
  2838. if (ret) {
  2839. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-ext-mclk in DT node\n",
  2840. __func__);
  2841. } else {
  2842. for (count = 0; count < MI2S_MAX; count++)
  2843. mi2s_intf_conf[count].msm_is_ext_mclk =
  2844. mi2s_ext_mclk[count];
  2845. }
  2846. }
  2847. static const struct of_device_id sdm660_asoc_machine_of_match[] = {
  2848. { .compatible = "qcom,sdm660-asoc-snd",
  2849. .data = "internal_codec"},
  2850. { .compatible = "qcom,sdm660-asoc-snd-tasha",
  2851. .data = "tasha_codec"},
  2852. { .compatible = "qcom,sdm660-asoc-snd-tavil",
  2853. .data = "tavil_codec"},
  2854. { .compatible = "qcom,sdm670-asoc-snd",
  2855. .data = "internal_codec"},
  2856. { .compatible = "qcom,sdm670-asoc-snd-tasha",
  2857. .data = "tasha_codec"},
  2858. { .compatible = "qcom,sdm670-asoc-snd-tavil",
  2859. .data = "tavil_codec"},
  2860. {},
  2861. };
  2862. static int msm_asoc_machine_probe(struct platform_device *pdev)
  2863. {
  2864. struct snd_soc_card *card = NULL;
  2865. struct msm_asoc_mach_data *pdata = NULL;
  2866. const char *mclk = "qcom,msm-mclk-freq";
  2867. int ret = -EINVAL, id;
  2868. const struct of_device_id *match;
  2869. pdata = devm_kzalloc(&pdev->dev,
  2870. sizeof(struct msm_asoc_mach_data),
  2871. GFP_KERNEL);
  2872. if (!pdata)
  2873. return -ENOMEM;
  2874. msm_set_codec_reg_done(false);
  2875. match = of_match_node(sdm660_asoc_machine_of_match,
  2876. pdev->dev.of_node);
  2877. if (!match)
  2878. goto err;
  2879. ret = of_property_read_u32(pdev->dev.of_node, mclk, &id);
  2880. if (ret) {
  2881. dev_err(&pdev->dev,
  2882. "%s: missing %s in dt node\n", __func__, mclk);
  2883. id = DEFAULT_MCLK_RATE;
  2884. }
  2885. pdata->mclk_freq = id;
  2886. if (!strcmp(match->data, "tasha_codec") ||
  2887. !strcmp(match->data, "tavil_codec")) {
  2888. if (!strcmp(match->data, "tasha_codec"))
  2889. pdata->snd_card_val = EXT_SND_CARD_TASHA;
  2890. else
  2891. pdata->snd_card_val = EXT_SND_CARD_TAVIL;
  2892. ret = msm_ext_cdc_init(pdev, pdata, &card, &mbhc_cfg);
  2893. if (ret)
  2894. goto err;
  2895. } else if (!strcmp(match->data, "internal_codec")) {
  2896. pdata->snd_card_val = INT_SND_CARD;
  2897. ret = msm_int_cdc_init(pdev, pdata, &card, &mbhc_cfg);
  2898. if (ret)
  2899. goto err;
  2900. } else {
  2901. dev_err(&pdev->dev,
  2902. "%s: Not a matching DT sound node\n", __func__);
  2903. goto err;
  2904. }
  2905. if (!card)
  2906. goto err;
  2907. if (pdata->snd_card_val == INT_SND_CARD) {
  2908. /*reading the gpio configurations from dtsi file*/
  2909. pdata->pdm_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2910. "qcom,cdc-pdm-gpios", 0);
  2911. pdata->comp_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2912. "qcom,cdc-comp-gpios", 0);
  2913. pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2914. "qcom,cdc-dmic-gpios", 0);
  2915. pdata->ext_spk_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2916. "qcom,cdc-ext-spk-gpios", 0);
  2917. }
  2918. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2919. "qcom,pri-mi2s-gpios", 0);
  2920. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2921. "qcom,sec-mi2s-gpios", 0);
  2922. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2923. "qcom,tert-mi2s-gpios", 0);
  2924. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2925. "qcom,quat-mi2s-gpios", 0);
  2926. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  2927. "qcom,quin-mi2s-gpios", 0);
  2928. /*
  2929. * Parse US-Euro gpio info from DT. Report no error if us-euro
  2930. * entry is not found in DT file as some targets do not support
  2931. * US-Euro detection
  2932. */
  2933. pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node,
  2934. "qcom,us-euro-gpios", 0);
  2935. if (!gpio_is_valid(pdata->us_euro_gpio))
  2936. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2937. "qcom,us-euro-gpios", 0);
  2938. if (!gpio_is_valid(pdata->us_euro_gpio) && (!pdata->us_euro_gpio_p)) {
  2939. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  2940. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  2941. } else {
  2942. dev_dbg(&pdev->dev, "%s detected",
  2943. "qcom,us-euro-gpios");
  2944. mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  2945. }
  2946. ret = msm_prepare_us_euro(card);
  2947. if (ret)
  2948. dev_dbg(&pdev->dev, "msm_prepare_us_euro failed (%d)\n",
  2949. ret);
  2950. i2s_auxpcm_init(pdev);
  2951. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  2952. if (ret)
  2953. goto err;
  2954. ret = msm_populate_dai_link_component_of_node(pdata, card);
  2955. if (ret) {
  2956. ret = -EPROBE_DEFER;
  2957. goto err;
  2958. }
  2959. if (!of_property_read_bool(pdev->dev.of_node, "qcom,wsa-disable")) {
  2960. ret = msm_init_wsa_dev(pdev, card);
  2961. if (ret)
  2962. goto err;
  2963. }
  2964. ret = devm_snd_soc_register_card(&pdev->dev, card);
  2965. if (ret == -EPROBE_DEFER) {
  2966. if (codec_reg_done) {
  2967. /*
  2968. * return failure as EINVAL since other codec
  2969. * registered sound card successfully.
  2970. * This avoids any further probe calls.
  2971. */
  2972. ret = -EINVAL;
  2973. }
  2974. goto err;
  2975. } else if (ret) {
  2976. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  2977. ret);
  2978. goto err;
  2979. }
  2980. if (pdata->snd_card_val != INT_SND_CARD)
  2981. msm_ext_register_audio_notifier(pdev);
  2982. return 0;
  2983. err:
  2984. if (pdata->us_euro_gpio > 0) {
  2985. dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n",
  2986. __func__, pdata->us_euro_gpio);
  2987. pdata->us_euro_gpio = 0;
  2988. }
  2989. if (pdata->hph_en1_gpio > 0) {
  2990. dev_dbg(&pdev->dev, "%s free hph_en1_gpio %d\n",
  2991. __func__, pdata->hph_en1_gpio);
  2992. gpio_free(pdata->hph_en1_gpio);
  2993. pdata->hph_en1_gpio = 0;
  2994. }
  2995. if (pdata->hph_en0_gpio > 0) {
  2996. dev_dbg(&pdev->dev, "%s free hph_en0_gpio %d\n",
  2997. __func__, pdata->hph_en0_gpio);
  2998. gpio_free(pdata->hph_en0_gpio);
  2999. pdata->hph_en0_gpio = 0;
  3000. }
  3001. devm_kfree(&pdev->dev, pdata);
  3002. return ret;
  3003. }
  3004. static int msm_asoc_machine_remove(struct platform_device *pdev)
  3005. {
  3006. struct snd_soc_card *card = platform_get_drvdata(pdev);
  3007. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3008. if (pdata->snd_card_val == INT_SND_CARD)
  3009. mutex_destroy(&pdata->cdc_int_mclk0_mutex);
  3010. msm_free_auxdev_mem(pdev);
  3011. gpio_free(pdata->us_euro_gpio);
  3012. gpio_free(pdata->hph_en1_gpio);
  3013. gpio_free(pdata->hph_en0_gpio);
  3014. snd_soc_unregister_card(card);
  3015. return 0;
  3016. }
  3017. static struct platform_driver sdm660_asoc_machine_driver = {
  3018. .driver = {
  3019. .name = DRV_NAME,
  3020. .owner = THIS_MODULE,
  3021. .pm = &snd_soc_pm_ops,
  3022. .of_match_table = sdm660_asoc_machine_of_match,
  3023. },
  3024. .probe = msm_asoc_machine_probe,
  3025. .remove = msm_asoc_machine_remove,
  3026. };
  3027. module_platform_driver(sdm660_asoc_machine_driver);
  3028. MODULE_DESCRIPTION("ALSA SoC msm");
  3029. MODULE_LICENSE("GPL v2");
  3030. MODULE_ALIAS("platform:" DRV_NAME);
  3031. MODULE_DEVICE_TABLE(of, sdm660_asoc_machine_of_match);