msm_cvp_platform.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/debugfs.h>
  6. #include <linux/dma-mapping.h>
  7. #include <linux/init.h>
  8. #include <linux/ioctl.h>
  9. #include <linux/list.h>
  10. #include <linux/module.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/types.h>
  15. #include <linux/version.h>
  16. #include <linux/io.h>
  17. #include <linux/of_fdt.h>
  18. #include "msm_cvp_internal.h"
  19. #include "msm_cvp_debug.h"
  20. #include "cvp_hfi_api.h"
  21. #include "cvp_hfi.h"
  22. #define UBWC_CONFIG(mco, mlo, hbo, bslo, bso, rs, mc, ml, hbb, bsl, bsp) \
  23. { \
  24. .override_bit_info.max_channel_override = mco, \
  25. .override_bit_info.mal_length_override = mlo, \
  26. .override_bit_info.hb_override = hbo, \
  27. .override_bit_info.bank_swzl_level_override = bslo, \
  28. .override_bit_info.bank_spreading_override = bso, \
  29. .override_bit_info.reserved = rs, \
  30. .max_channels = mc, \
  31. .mal_length = ml, \
  32. .highest_bank_bit = hbb, \
  33. .bank_swzl_level = bsl, \
  34. .bank_spreading = bsp, \
  35. }
  36. static struct msm_cvp_common_data default_common_data[] = {
  37. {
  38. .key = "qcom,never-unload-fw",
  39. .value = 1,
  40. },
  41. };
  42. static struct msm_cvp_common_data sm8450_common_data[] = {
  43. {
  44. .key = "qcom,auto-pil",
  45. .value = 1,
  46. },
  47. {
  48. .key = "qcom,never-unload-fw",
  49. .value = 1,
  50. },
  51. {
  52. .key = "qcom,sw-power-collapse",
  53. .value = 1,
  54. },
  55. {
  56. .key = "qcom,domain-attr-non-fatal-faults",
  57. .value = 0,
  58. },
  59. {
  60. .key = "qcom,max-secure-instances",
  61. .value = 2, /*
  62. * As per design driver allows 3rd
  63. * instance as well since the secure
  64. * flags were updated later for the
  65. * current instance. Hence total
  66. * secure sessions would be
  67. * max-secure-instances + 1.
  68. */
  69. },
  70. {
  71. .key = "qcom,max-hw-load",
  72. .value = 3916800, /*
  73. * 1920x1088/256 MBs@480fps. It is less
  74. * any other usecases (ex:
  75. * 3840x2160@120fps, 4096x2160@96ps,
  76. * 7680x4320@30fps)
  77. */
  78. },
  79. {
  80. .key = "qcom,power-collapse-delay",
  81. .value = 3000,
  82. },
  83. {
  84. .key = "qcom,hw-resp-timeout",
  85. .value = 2000,
  86. },
  87. {
  88. .key = "qcom,dsp-resp-timeout",
  89. .value = 1000,
  90. },
  91. {
  92. .key = "qcom,debug-timeout",
  93. .value = 0,
  94. },
  95. {
  96. .key = "qcom,dsp-enabled",
  97. .value = 1,
  98. }
  99. };
  100. /* Default UBWC config for LPDDR5 */
  101. static struct msm_cvp_ubwc_config_data kona_ubwc_data[] = {
  102. UBWC_CONFIG(1, 1, 1, 0, 0, 0, 8, 32, 16, 0, 0),
  103. };
  104. static struct msm_cvp_platform_data default_data = {
  105. .common_data = default_common_data,
  106. .common_data_length = ARRAY_SIZE(default_common_data),
  107. .sku_version = 0,
  108. .vpu_ver = VPU_VERSION_5,
  109. .ubwc_config = 0x0,
  110. };
  111. static struct msm_cvp_platform_data sm8450_data = {
  112. .common_data = sm8450_common_data,
  113. .common_data_length = ARRAY_SIZE(sm8450_common_data),
  114. .sku_version = 0,
  115. .vpu_ver = VPU_VERSION_5,
  116. .ubwc_config = kona_ubwc_data,
  117. };
  118. static const struct of_device_id msm_cvp_dt_match[] = {
  119. {
  120. .compatible = "qcom,waipio-cvp",
  121. .data = &sm8450_data,
  122. },
  123. {},
  124. };
  125. const struct msm_cvp_hfi_defs cvp_hfi_defs[] = {
  126. {
  127. .size = HFI_DFS_CONFIG_CMD_SIZE,
  128. .type = HFI_CMD_SESSION_CVP_DFS_CONFIG,
  129. .is_config_pkt = true,
  130. .resp = HAL_NO_RESP,
  131. },
  132. {
  133. .size = HFI_DFS_FRAME_CMD_SIZE,
  134. .type = HFI_CMD_SESSION_CVP_DFS_FRAME,
  135. .is_config_pkt = false,
  136. .resp = HAL_NO_RESP,
  137. },
  138. {
  139. .size = 0xFFFFFFFF,
  140. .type = HFI_CMD_SESSION_CVP_SGM_OF_CONFIG,
  141. .is_config_pkt = true,
  142. .resp = HAL_NO_RESP,
  143. },
  144. {
  145. .size = 0xFFFFFFFF,
  146. .type = HFI_CMD_SESSION_CVP_SGM_OF_FRAME,
  147. .is_config_pkt = false,
  148. .resp = HAL_NO_RESP,
  149. },
  150. {
  151. .size = 0xFFFFFFFF,
  152. .type = HFI_CMD_SESSION_CVP_WARP_NCC_CONFIG,
  153. .is_config_pkt = true,
  154. .resp = HAL_NO_RESP,
  155. },
  156. {
  157. .size = 0xFFFFFFFF,
  158. .type = HFI_CMD_SESSION_CVP_WARP_NCC_FRAME,
  159. .is_config_pkt = false,
  160. .resp = HAL_NO_RESP,
  161. },
  162. {
  163. .size = 0xFFFFFFFF,
  164. .type = HFI_CMD_SESSION_CVP_WARP_CONFIG,
  165. .is_config_pkt = true,
  166. .resp = HAL_NO_RESP,
  167. },
  168. {
  169. .size = 0xFFFFFFFF,
  170. .type = HFI_CMD_SESSION_CVP_WARP_DS_PARAMS,
  171. .is_config_pkt = true,
  172. .resp = HAL_NO_RESP,
  173. },
  174. {
  175. .size = 0xFFFFFFFF,
  176. .type = HFI_CMD_SESSION_CVP_WARP_FRAME,
  177. .is_config_pkt = false,
  178. .resp = HAL_NO_RESP,
  179. },
  180. {
  181. .size = HFI_DMM_CONFIG_CMD_SIZE,
  182. .type = HFI_CMD_SESSION_CVP_DMM_CONFIG,
  183. .is_config_pkt = true,
  184. .resp = HAL_NO_RESP,
  185. },
  186. {
  187. .size = 0xFFFFFFFF,
  188. .type = HFI_CMD_SESSION_CVP_DMM_PARAMS,
  189. .is_config_pkt = true,
  190. .resp = HAL_NO_RESP,
  191. },
  192. {
  193. .size = HFI_DMM_FRAME_CMD_SIZE,
  194. .type = HFI_CMD_SESSION_CVP_DMM_FRAME,
  195. .is_config_pkt = false,
  196. .resp = HAL_NO_RESP,
  197. },
  198. {
  199. .size = HFI_PERSIST_CMD_SIZE,
  200. .type = HFI_CMD_SESSION_CVP_SET_PERSIST_BUFFERS,
  201. .is_config_pkt = true,
  202. .resp = HAL_NO_RESP,
  203. },
  204. {
  205. .size = 0xffffffff,
  206. .type = HFI_CMD_SESSION_CVP_RELEASE_PERSIST_BUFFERS,
  207. .is_config_pkt = true,
  208. .resp = HAL_NO_RESP,
  209. },
  210. {
  211. .size = HFI_DS_CMD_SIZE,
  212. .type = HFI_CMD_SESSION_CVP_DS,
  213. .is_config_pkt = false,
  214. .resp = HAL_NO_RESP,
  215. },
  216. {
  217. .size = HFI_OF_CONFIG_CMD_SIZE,
  218. .type = HFI_CMD_SESSION_CVP_CV_TME_CONFIG,
  219. .is_config_pkt = true,
  220. .resp = HAL_NO_RESP,
  221. },
  222. {
  223. .size = HFI_OF_FRAME_CMD_SIZE,
  224. .type = HFI_CMD_SESSION_CVP_CV_TME_FRAME,
  225. .is_config_pkt = false,
  226. .resp = HAL_NO_RESP,
  227. },
  228. {
  229. .size = HFI_ODT_CONFIG_CMD_SIZE,
  230. .type = HFI_CMD_SESSION_CVP_CV_ODT_CONFIG,
  231. .is_config_pkt = true,
  232. .resp = HAL_NO_RESP,
  233. },
  234. {
  235. .size = HFI_ODT_FRAME_CMD_SIZE,
  236. .type = HFI_CMD_SESSION_CVP_CV_ODT_FRAME,
  237. .is_config_pkt = false,
  238. .resp = HAL_NO_RESP,
  239. },
  240. {
  241. .size = HFI_OD_CONFIG_CMD_SIZE,
  242. .type = HFI_CMD_SESSION_CVP_CV_OD_CONFIG,
  243. .is_config_pkt = true,
  244. .resp = HAL_NO_RESP,
  245. },
  246. {
  247. .size = HFI_OD_FRAME_CMD_SIZE,
  248. .type = HFI_CMD_SESSION_CVP_CV_OD_FRAME,
  249. .is_config_pkt = false,
  250. .resp = HAL_NO_RESP,
  251. },
  252. {
  253. .size = HFI_NCC_CONFIG_CMD_SIZE,
  254. .type = HFI_CMD_SESSION_CVP_NCC_CONFIG,
  255. .is_config_pkt = true,
  256. .resp = HAL_NO_RESP,
  257. },
  258. {
  259. .size = HFI_NCC_FRAME_CMD_SIZE,
  260. .type = HFI_CMD_SESSION_CVP_NCC_FRAME,
  261. .is_config_pkt = false,
  262. .resp = HAL_NO_RESP,
  263. },
  264. {
  265. .size = HFI_ICA_CONFIG_CMD_SIZE,
  266. .type = HFI_CMD_SESSION_CVP_ICA_CONFIG,
  267. .is_config_pkt = true,
  268. .resp = HAL_NO_RESP,
  269. },
  270. {
  271. .size = HFI_ICA_FRAME_CMD_SIZE,
  272. .type = HFI_CMD_SESSION_CVP_ICA_FRAME,
  273. .is_config_pkt = false,
  274. .resp = HAL_NO_RESP,
  275. },
  276. {
  277. .size = HFI_HCD_CONFIG_CMD_SIZE,
  278. .type = HFI_CMD_SESSION_CVP_HCD_CONFIG,
  279. .is_config_pkt = true,
  280. .resp = HAL_NO_RESP,
  281. },
  282. {
  283. .size = HFI_HCD_FRAME_CMD_SIZE,
  284. .type = HFI_CMD_SESSION_CVP_HCD_FRAME,
  285. .is_config_pkt = false,
  286. .resp = HAL_NO_RESP,
  287. },
  288. {
  289. .size = HFI_DCM_CONFIG_CMD_SIZE,
  290. .type = HFI_CMD_SESSION_CVP_DC_CONFIG,
  291. .is_config_pkt = true,
  292. .resp = HAL_NO_RESP,
  293. },
  294. {
  295. .size = HFI_DCM_FRAME_CMD_SIZE,
  296. .type = HFI_CMD_SESSION_CVP_DC_FRAME,
  297. .is_config_pkt = false,
  298. .resp = HAL_NO_RESP,
  299. },
  300. {
  301. .size = HFI_DCM_CONFIG_CMD_SIZE,
  302. .type = HFI_CMD_SESSION_CVP_DCM_CONFIG,
  303. .is_config_pkt = true,
  304. .resp = HAL_NO_RESP,
  305. },
  306. {
  307. .size = HFI_DCM_FRAME_CMD_SIZE,
  308. .type = HFI_CMD_SESSION_CVP_DCM_FRAME,
  309. .is_config_pkt = false,
  310. .resp = HAL_NO_RESP,
  311. },
  312. {
  313. .size = HFI_PYS_HCD_CONFIG_CMD_SIZE,
  314. .type = HFI_CMD_SESSION_CVP_PYS_HCD_CONFIG,
  315. .is_config_pkt = true,
  316. .resp = HAL_NO_RESP,
  317. },
  318. {
  319. .size = HFI_PYS_HCD_FRAME_CMD_SIZE,
  320. .type = HFI_CMD_SESSION_CVP_PYS_HCD_FRAME,
  321. .is_config_pkt = false,
  322. .resp = HAL_NO_RESP,
  323. },
  324. {
  325. .size = 0xFFFFFFFF,
  326. .type = HFI_CMD_SESSION_CVP_SET_MODEL_BUFFERS,
  327. .is_config_pkt = true,
  328. .resp = HAL_NO_RESP,
  329. },
  330. {
  331. .size = 0xFFFFFFFF,
  332. .type = HFI_CMD_SESSION_CVP_FD_CONFIG,
  333. .is_config_pkt = true,
  334. .resp = HAL_NO_RESP,
  335. },
  336. {
  337. .size = 0xFFFFFFFF,
  338. .type = HFI_CMD_SESSION_CVP_FD_FRAME,
  339. .is_config_pkt = false,
  340. .resp = HAL_NO_RESP,
  341. },
  342. };
  343. int get_pkt_index(struct cvp_hal_session_cmd_pkt *hdr)
  344. {
  345. int i, pkt_num = ARRAY_SIZE(cvp_hfi_defs);
  346. for (i = 0; i < pkt_num; i++)
  347. if (cvp_hfi_defs[i].type == hdr->packet_type)
  348. return i;
  349. return -EINVAL;
  350. }
  351. MODULE_DEVICE_TABLE(of, msm_cvp_dt_match);
  352. void *cvp_get_drv_data(struct device *dev)
  353. {
  354. struct msm_cvp_platform_data *driver_data;
  355. const struct of_device_id *match;
  356. uint32_t ddr_type = DDR_TYPE_LPDDR5;
  357. driver_data = &default_data;
  358. if (!IS_ENABLED(CONFIG_OF) || !dev->of_node)
  359. goto exit;
  360. match = of_match_node(msm_cvp_dt_match, dev->of_node);
  361. if (!match)
  362. return NULL;
  363. driver_data = (struct msm_cvp_platform_data *)match->data;
  364. if (!strcmp(match->compatible, "qcom,waipio-cvp")) {
  365. ddr_type = of_fdt_get_ddrtype();
  366. if (ddr_type == -ENOENT) {
  367. dprintk(CVP_ERR,
  368. "Failed to get ddr type, use LPDDR5\n");
  369. }
  370. if (driver_data->ubwc_config &&
  371. (ddr_type == DDR_TYPE_LPDDR4 ||
  372. ddr_type == DDR_TYPE_LPDDR4X))
  373. driver_data->ubwc_config->highest_bank_bit = 15;
  374. dprintk(CVP_CORE, "DDR Type 0x%x hbb 0x%x\n",
  375. ddr_type, driver_data->ubwc_config ?
  376. driver_data->ubwc_config->highest_bank_bit : -1);
  377. }
  378. exit:
  379. return driver_data;
  380. }