hal_api.h 92 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_API_H_
  20. #define _HAL_API_H_
  21. #include "qdf_types.h"
  22. #include "qdf_util.h"
  23. #include "qdf_atomic.h"
  24. #include "hal_internal.h"
  25. #include "hif.h"
  26. #include "hif_io32.h"
  27. #include "qdf_platform.h"
  28. #ifdef DUMP_REO_QUEUE_INFO_IN_DDR
  29. #include "hal_hw_headers.h"
  30. #endif
  31. /* Ring index for WBM2SW2 release ring */
  32. #define HAL_IPA_TX_COMP_RING_IDX 2
  33. /* calculate the register address offset from bar0 of shadow register x */
  34. #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \
  35. defined(QCA_WIFI_KIWI)
  36. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x000008FC
  37. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  38. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  39. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  40. #elif defined(QCA_WIFI_QCA6290) || defined(QCA_WIFI_QCN9000)
  41. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x00003024
  42. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  43. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  44. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  45. #elif defined(QCA_WIFI_QCA6750)
  46. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x00000504
  47. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  48. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  49. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  50. #else
  51. #define SHADOW_REGISTER(x) 0
  52. #endif /* QCA_WIFI_QCA6390 || QCA_WIFI_QCA6490 || QCA_WIFI_QCA6750 */
  53. /*
  54. * BAR + 4K is always accessible, any access outside this
  55. * space requires force wake procedure.
  56. * OFFSET = 4K - 32 bytes = 0xFE0
  57. */
  58. #define MAPPED_REF_OFF 0xFE0
  59. #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET
  60. #ifdef ENABLE_VERBOSE_DEBUG
  61. static inline void
  62. hal_set_verbose_debug(bool flag)
  63. {
  64. is_hal_verbose_debug_enabled = flag;
  65. }
  66. #endif
  67. #ifdef ENABLE_HAL_SOC_STATS
  68. #define HAL_STATS_INC(_handle, _field, _delta) \
  69. { \
  70. if (likely(_handle)) \
  71. _handle->stats._field += _delta; \
  72. }
  73. #else
  74. #define HAL_STATS_INC(_handle, _field, _delta)
  75. #endif
  76. #ifdef ENABLE_HAL_REG_WR_HISTORY
  77. #define HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, wr_val, rd_val) \
  78. hal_reg_wr_fail_history_add(hal_soc, offset, wr_val, rd_val)
  79. void hal_reg_wr_fail_history_add(struct hal_soc *hal_soc,
  80. uint32_t offset,
  81. uint32_t wr_val,
  82. uint32_t rd_val);
  83. static inline int hal_history_get_next_index(qdf_atomic_t *table_index,
  84. int array_size)
  85. {
  86. int record_index = qdf_atomic_inc_return(table_index);
  87. return record_index & (array_size - 1);
  88. }
  89. #else
  90. #define HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, wr_val, rd_val) \
  91. hal_err("write failed at reg offset 0x%x, write 0x%x read 0x%x\n", \
  92. offset, \
  93. wr_val, \
  94. rd_val)
  95. #endif
  96. /**
  97. * hal_reg_write_result_check() - check register writing result
  98. * @hal_soc: HAL soc handle
  99. * @offset: register offset to read
  100. * @exp_val: the expected value of register
  101. * @ret_confirm: result confirm flag
  102. *
  103. * Return: none
  104. */
  105. static inline void hal_reg_write_result_check(struct hal_soc *hal_soc,
  106. uint32_t offset,
  107. uint32_t exp_val)
  108. {
  109. uint32_t value;
  110. value = qdf_ioread32(hal_soc->dev_base_addr + offset);
  111. if (exp_val != value) {
  112. HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, exp_val, value);
  113. HAL_STATS_INC(hal_soc, reg_write_fail, 1);
  114. }
  115. }
  116. #ifdef WINDOW_REG_PLD_LOCK_ENABLE
  117. static inline void hal_lock_reg_access(struct hal_soc *soc,
  118. unsigned long *flags)
  119. {
  120. pld_lock_reg_window(soc->qdf_dev->dev, flags);
  121. }
  122. static inline void hal_unlock_reg_access(struct hal_soc *soc,
  123. unsigned long *flags)
  124. {
  125. pld_unlock_reg_window(soc->qdf_dev->dev, flags);
  126. }
  127. #else
  128. static inline void hal_lock_reg_access(struct hal_soc *soc,
  129. unsigned long *flags)
  130. {
  131. qdf_spin_lock_irqsave(&soc->register_access_lock);
  132. }
  133. static inline void hal_unlock_reg_access(struct hal_soc *soc,
  134. unsigned long *flags)
  135. {
  136. qdf_spin_unlock_irqrestore(&soc->register_access_lock);
  137. }
  138. #endif
  139. #ifdef PCIE_REG_WINDOW_LOCAL_NO_CACHE
  140. /**
  141. * hal_select_window_confirm() - write remap window register and
  142. check writing result
  143. *
  144. */
  145. static inline void hal_select_window_confirm(struct hal_soc *hal_soc,
  146. uint32_t offset)
  147. {
  148. uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
  149. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  150. WINDOW_ENABLE_BIT | window);
  151. hal_soc->register_window = window;
  152. hal_reg_write_result_check(hal_soc, WINDOW_REG_ADDRESS,
  153. WINDOW_ENABLE_BIT | window);
  154. }
  155. #else
  156. static inline void hal_select_window_confirm(struct hal_soc *hal_soc,
  157. uint32_t offset)
  158. {
  159. uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
  160. if (window != hal_soc->register_window) {
  161. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  162. WINDOW_ENABLE_BIT | window);
  163. hal_soc->register_window = window;
  164. hal_reg_write_result_check(
  165. hal_soc,
  166. WINDOW_REG_ADDRESS,
  167. WINDOW_ENABLE_BIT | window);
  168. }
  169. }
  170. #endif
  171. static inline qdf_iomem_t hal_get_window_address(struct hal_soc *hal_soc,
  172. qdf_iomem_t addr)
  173. {
  174. return hal_soc->ops->hal_get_window_address(hal_soc, addr);
  175. }
  176. static inline void hal_tx_init_cmd_credit_ring(hal_soc_handle_t hal_soc_hdl,
  177. hal_ring_handle_t hal_ring_hdl)
  178. {
  179. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  180. return hal_soc->ops->hal_tx_init_cmd_credit_ring(hal_soc_hdl,
  181. hal_ring_hdl);
  182. }
  183. /**
  184. * hal_write32_mb() - Access registers to update configuration
  185. * @hal_soc: hal soc handle
  186. * @offset: offset address from the BAR
  187. * @value: value to write
  188. *
  189. * Return: None
  190. *
  191. * Description: Register address space is split below:
  192. * SHADOW REGION UNWINDOWED REGION WINDOWED REGION
  193. * |--------------------|-------------------|------------------|
  194. * BAR NO FORCE WAKE BAR+4K FORCE WAKE BAR+512K FORCE WAKE
  195. *
  196. * 1. Any access to the shadow region, doesn't need force wake
  197. * and windowing logic to access.
  198. * 2. Any access beyond BAR + 4K:
  199. * If init_phase enabled, no force wake is needed and access
  200. * should be based on windowed or unwindowed access.
  201. * If init_phase disabled, force wake is needed and access
  202. * should be based on windowed or unwindowed access.
  203. *
  204. * note1: WINDOW_RANGE_MASK = (1 << WINDOW_SHIFT) -1
  205. * note2: 1 << WINDOW_SHIFT = MAX_UNWINDOWED_ADDRESS
  206. * note3: WINDOW_VALUE_MASK = big enough that trying to write past
  207. * that window would be a bug
  208. */
  209. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) && \
  210. !defined(QCA_WIFI_QCA6750) && !defined(QCA_WIFI_KIWI)
  211. static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
  212. uint32_t value)
  213. {
  214. unsigned long flags;
  215. qdf_iomem_t new_addr;
  216. if (!hal_soc->use_register_windowing ||
  217. offset < MAX_UNWINDOWED_ADDRESS) {
  218. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  219. } else if (hal_soc->static_window_map) {
  220. new_addr = hal_get_window_address(hal_soc,
  221. hal_soc->dev_base_addr + offset);
  222. qdf_iowrite32(new_addr, value);
  223. } else {
  224. hal_lock_reg_access(hal_soc, &flags);
  225. hal_select_window_confirm(hal_soc, offset);
  226. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  227. (offset & WINDOW_RANGE_MASK), value);
  228. hal_unlock_reg_access(hal_soc, &flags);
  229. }
  230. }
  231. #define hal_write32_mb_confirm(_hal_soc, _offset, _value) \
  232. hal_write32_mb(_hal_soc, _offset, _value)
  233. #define hal_write32_mb_cmem(_hal_soc, _offset, _value)
  234. #else
  235. static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
  236. uint32_t value)
  237. {
  238. int ret;
  239. unsigned long flags;
  240. qdf_iomem_t new_addr;
  241. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  242. hal_soc->hif_handle))) {
  243. hal_err_rl("target access is not allowed");
  244. return;
  245. }
  246. /* Region < BAR + 4K can be directly accessed */
  247. if (offset < MAPPED_REF_OFF) {
  248. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  249. return;
  250. }
  251. /* Region greater than BAR + 4K */
  252. if (!hal_soc->init_phase) {
  253. ret = hif_force_wake_request(hal_soc->hif_handle);
  254. if (ret) {
  255. hal_err_rl("Wake up request failed");
  256. qdf_check_state_before_panic(__func__, __LINE__);
  257. return;
  258. }
  259. }
  260. if (!hal_soc->use_register_windowing ||
  261. offset < MAX_UNWINDOWED_ADDRESS) {
  262. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  263. } else if (hal_soc->static_window_map) {
  264. new_addr = hal_get_window_address(
  265. hal_soc,
  266. hal_soc->dev_base_addr + offset);
  267. qdf_iowrite32(new_addr, value);
  268. } else {
  269. hal_lock_reg_access(hal_soc, &flags);
  270. hal_select_window_confirm(hal_soc, offset);
  271. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  272. (offset & WINDOW_RANGE_MASK), value);
  273. hal_unlock_reg_access(hal_soc, &flags);
  274. }
  275. if (!hal_soc->init_phase) {
  276. ret = hif_force_wake_release(hal_soc->hif_handle);
  277. if (ret) {
  278. hal_err("Wake up release failed");
  279. qdf_check_state_before_panic(__func__, __LINE__);
  280. return;
  281. }
  282. }
  283. }
  284. /**
  285. * hal_write32_mb_confirm() - write register and check writing result
  286. *
  287. */
  288. static inline void hal_write32_mb_confirm(struct hal_soc *hal_soc,
  289. uint32_t offset,
  290. uint32_t value)
  291. {
  292. int ret;
  293. unsigned long flags;
  294. qdf_iomem_t new_addr;
  295. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  296. hal_soc->hif_handle))) {
  297. hal_err_rl("target access is not allowed");
  298. return;
  299. }
  300. /* Region < BAR + 4K can be directly accessed */
  301. if (offset < MAPPED_REF_OFF) {
  302. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  303. return;
  304. }
  305. /* Region greater than BAR + 4K */
  306. if (!hal_soc->init_phase) {
  307. ret = hif_force_wake_request(hal_soc->hif_handle);
  308. if (ret) {
  309. hal_err("Wake up request failed");
  310. qdf_check_state_before_panic(__func__, __LINE__);
  311. return;
  312. }
  313. }
  314. if (!hal_soc->use_register_windowing ||
  315. offset < MAX_UNWINDOWED_ADDRESS) {
  316. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  317. hal_reg_write_result_check(hal_soc, offset,
  318. value);
  319. } else if (hal_soc->static_window_map) {
  320. new_addr = hal_get_window_address(
  321. hal_soc,
  322. hal_soc->dev_base_addr + offset);
  323. qdf_iowrite32(new_addr, value);
  324. hal_reg_write_result_check(hal_soc,
  325. new_addr - hal_soc->dev_base_addr,
  326. value);
  327. } else {
  328. hal_lock_reg_access(hal_soc, &flags);
  329. hal_select_window_confirm(hal_soc, offset);
  330. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  331. (offset & WINDOW_RANGE_MASK), value);
  332. hal_reg_write_result_check(
  333. hal_soc,
  334. WINDOW_START + (offset & WINDOW_RANGE_MASK),
  335. value);
  336. hal_unlock_reg_access(hal_soc, &flags);
  337. }
  338. if (!hal_soc->init_phase) {
  339. ret = hif_force_wake_release(hal_soc->hif_handle);
  340. if (ret) {
  341. hal_err("Wake up release failed");
  342. qdf_check_state_before_panic(__func__, __LINE__);
  343. return;
  344. }
  345. }
  346. }
  347. static inline void hal_write32_mb_cmem(struct hal_soc *hal_soc, uint32_t offset,
  348. uint32_t value)
  349. {
  350. unsigned long flags;
  351. qdf_iomem_t new_addr;
  352. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  353. hal_soc->hif_handle))) {
  354. hal_err_rl("%s: target access is not allowed", __func__);
  355. return;
  356. }
  357. if (!hal_soc->use_register_windowing ||
  358. offset < MAX_UNWINDOWED_ADDRESS) {
  359. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  360. } else if (hal_soc->static_window_map) {
  361. new_addr = hal_get_window_address(
  362. hal_soc,
  363. hal_soc->dev_base_addr + offset);
  364. qdf_iowrite32(new_addr, value);
  365. } else {
  366. hal_lock_reg_access(hal_soc, &flags);
  367. hal_select_window_confirm(hal_soc, offset);
  368. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  369. (offset & WINDOW_RANGE_MASK), value);
  370. hal_unlock_reg_access(hal_soc, &flags);
  371. }
  372. }
  373. #endif
  374. /**
  375. * hal_write_address_32_mb - write a value to a register
  376. *
  377. */
  378. static inline
  379. void hal_write_address_32_mb(struct hal_soc *hal_soc,
  380. qdf_iomem_t addr, uint32_t value, bool wr_confirm)
  381. {
  382. uint32_t offset;
  383. if (!hal_soc->use_register_windowing)
  384. return qdf_iowrite32(addr, value);
  385. offset = addr - hal_soc->dev_base_addr;
  386. if (qdf_unlikely(wr_confirm))
  387. hal_write32_mb_confirm(hal_soc, offset, value);
  388. else
  389. hal_write32_mb(hal_soc, offset, value);
  390. }
  391. #ifdef DP_HAL_MULTIWINDOW_DIRECT_ACCESS
  392. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  393. struct hal_srng *srng,
  394. void __iomem *addr,
  395. uint32_t value)
  396. {
  397. qdf_iowrite32(addr, value);
  398. }
  399. #elif defined(FEATURE_HAL_DELAYED_REG_WRITE)
  400. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  401. struct hal_srng *srng,
  402. void __iomem *addr,
  403. uint32_t value)
  404. {
  405. hal_delayed_reg_write(hal_soc, srng, addr, value);
  406. }
  407. #else
  408. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  409. struct hal_srng *srng,
  410. void __iomem *addr,
  411. uint32_t value)
  412. {
  413. hal_write_address_32_mb(hal_soc, addr, value, false);
  414. }
  415. #endif
  416. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) && \
  417. !defined(QCA_WIFI_QCA6750) && !defined(QCA_WIFI_KIWI)
  418. /**
  419. * hal_read32_mb() - Access registers to read configuration
  420. * @hal_soc: hal soc handle
  421. * @offset: offset address from the BAR
  422. * @value: value to write
  423. *
  424. * Description: Register address space is split below:
  425. * SHADOW REGION UNWINDOWED REGION WINDOWED REGION
  426. * |--------------------|-------------------|------------------|
  427. * BAR NO FORCE WAKE BAR+4K FORCE WAKE BAR+512K FORCE WAKE
  428. *
  429. * 1. Any access to the shadow region, doesn't need force wake
  430. * and windowing logic to access.
  431. * 2. Any access beyond BAR + 4K:
  432. * If init_phase enabled, no force wake is needed and access
  433. * should be based on windowed or unwindowed access.
  434. * If init_phase disabled, force wake is needed and access
  435. * should be based on windowed or unwindowed access.
  436. *
  437. * Return: < 0 for failure/>= 0 for success
  438. */
  439. static inline uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)
  440. {
  441. uint32_t ret;
  442. unsigned long flags;
  443. qdf_iomem_t new_addr;
  444. if (!hal_soc->use_register_windowing ||
  445. offset < MAX_UNWINDOWED_ADDRESS) {
  446. return qdf_ioread32(hal_soc->dev_base_addr + offset);
  447. } else if (hal_soc->static_window_map) {
  448. new_addr = hal_get_window_address(hal_soc, hal_soc->dev_base_addr + offset);
  449. return qdf_ioread32(new_addr);
  450. }
  451. hal_lock_reg_access(hal_soc, &flags);
  452. hal_select_window_confirm(hal_soc, offset);
  453. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  454. (offset & WINDOW_RANGE_MASK));
  455. hal_unlock_reg_access(hal_soc, &flags);
  456. return ret;
  457. }
  458. #define hal_read32_mb_cmem(_hal_soc, _offset)
  459. #else
  460. static
  461. uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)
  462. {
  463. uint32_t ret;
  464. unsigned long flags;
  465. qdf_iomem_t new_addr;
  466. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  467. hal_soc->hif_handle))) {
  468. hal_err_rl("target access is not allowed");
  469. return 0;
  470. }
  471. /* Region < BAR + 4K can be directly accessed */
  472. if (offset < MAPPED_REF_OFF)
  473. return qdf_ioread32(hal_soc->dev_base_addr + offset);
  474. if ((!hal_soc->init_phase) &&
  475. hif_force_wake_request(hal_soc->hif_handle)) {
  476. hal_err("Wake up request failed");
  477. qdf_check_state_before_panic(__func__, __LINE__);
  478. return 0;
  479. }
  480. if (!hal_soc->use_register_windowing ||
  481. offset < MAX_UNWINDOWED_ADDRESS) {
  482. ret = qdf_ioread32(hal_soc->dev_base_addr + offset);
  483. } else if (hal_soc->static_window_map) {
  484. new_addr = hal_get_window_address(
  485. hal_soc,
  486. hal_soc->dev_base_addr + offset);
  487. ret = qdf_ioread32(new_addr);
  488. } else {
  489. hal_lock_reg_access(hal_soc, &flags);
  490. hal_select_window_confirm(hal_soc, offset);
  491. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  492. (offset & WINDOW_RANGE_MASK));
  493. hal_unlock_reg_access(hal_soc, &flags);
  494. }
  495. if ((!hal_soc->init_phase) &&
  496. hif_force_wake_release(hal_soc->hif_handle)) {
  497. hal_err("Wake up release failed");
  498. qdf_check_state_before_panic(__func__, __LINE__);
  499. return 0;
  500. }
  501. return ret;
  502. }
  503. static inline
  504. uint32_t hal_read32_mb_cmem(struct hal_soc *hal_soc, uint32_t offset)
  505. {
  506. uint32_t ret;
  507. unsigned long flags;
  508. qdf_iomem_t new_addr;
  509. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  510. hal_soc->hif_handle))) {
  511. hal_err_rl("%s: target access is not allowed", __func__);
  512. return 0;
  513. }
  514. if (!hal_soc->use_register_windowing ||
  515. offset < MAX_UNWINDOWED_ADDRESS) {
  516. ret = qdf_ioread32(hal_soc->dev_base_addr + offset);
  517. } else if (hal_soc->static_window_map) {
  518. new_addr = hal_get_window_address(
  519. hal_soc,
  520. hal_soc->dev_base_addr + offset);
  521. ret = qdf_ioread32(new_addr);
  522. } else {
  523. hal_lock_reg_access(hal_soc, &flags);
  524. hal_select_window_confirm(hal_soc, offset);
  525. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  526. (offset & WINDOW_RANGE_MASK));
  527. hal_unlock_reg_access(hal_soc, &flags);
  528. }
  529. return ret;
  530. }
  531. #endif
  532. /* Max times allowed for register writing retry */
  533. #define HAL_REG_WRITE_RETRY_MAX 5
  534. /* Delay milliseconds for each time retry */
  535. #define HAL_REG_WRITE_RETRY_DELAY 1
  536. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  537. /* To check shadow config index range between 0..31 */
  538. #define HAL_SHADOW_REG_INDEX_LOW 32
  539. /* To check shadow config index range between 32..39 */
  540. #define HAL_SHADOW_REG_INDEX_HIGH 40
  541. /* Dirty bit reg offsets corresponding to shadow config index */
  542. #define HAL_SHADOW_REG_DIRTY_BIT_DATA_LOW_OFFSET 0x30C8
  543. #define HAL_SHADOW_REG_DIRTY_BIT_DATA_HIGH_OFFSET 0x30C4
  544. /* PCIE_PCIE_TOP base addr offset */
  545. #define HAL_PCIE_PCIE_TOP_WRAPPER 0x01E00000
  546. /* Max retry attempts to read the dirty bit reg */
  547. #ifdef HAL_CONFIG_SLUB_DEBUG_ON
  548. #define HAL_SHADOW_DIRTY_BIT_POLL_MAX 10000
  549. #else
  550. #define HAL_SHADOW_DIRTY_BIT_POLL_MAX 2000
  551. #endif
  552. /* Delay in usecs for polling dirty bit reg */
  553. #define HAL_SHADOW_DIRTY_BIT_POLL_DELAY 5
  554. /**
  555. * hal_poll_dirty_bit_reg() - Poll dirty register bit to confirm
  556. * write was successful
  557. * @hal_soc: hal soc handle
  558. * @shadow_config_index: index of shadow reg used to confirm
  559. * write
  560. *
  561. * Return: QDF_STATUS_SUCCESS on success
  562. */
  563. static inline QDF_STATUS hal_poll_dirty_bit_reg(struct hal_soc *hal,
  564. int shadow_config_index)
  565. {
  566. uint32_t read_value = 0;
  567. int retry_cnt = 0;
  568. uint32_t reg_offset = 0;
  569. if (shadow_config_index > 0 &&
  570. shadow_config_index < HAL_SHADOW_REG_INDEX_LOW) {
  571. reg_offset =
  572. HAL_SHADOW_REG_DIRTY_BIT_DATA_LOW_OFFSET;
  573. } else if (shadow_config_index >= HAL_SHADOW_REG_INDEX_LOW &&
  574. shadow_config_index < HAL_SHADOW_REG_INDEX_HIGH) {
  575. reg_offset =
  576. HAL_SHADOW_REG_DIRTY_BIT_DATA_HIGH_OFFSET;
  577. } else {
  578. hal_err("Invalid shadow_config_index = %d",
  579. shadow_config_index);
  580. return QDF_STATUS_E_INVAL;
  581. }
  582. while (retry_cnt < HAL_SHADOW_DIRTY_BIT_POLL_MAX) {
  583. read_value = hal_read32_mb(
  584. hal, HAL_PCIE_PCIE_TOP_WRAPPER + reg_offset);
  585. /* Check if dirty bit corresponding to shadow_index is set */
  586. if (read_value & BIT(shadow_config_index)) {
  587. /* Dirty reg bit not reset */
  588. qdf_udelay(HAL_SHADOW_DIRTY_BIT_POLL_DELAY);
  589. retry_cnt++;
  590. } else {
  591. hal_debug("Shadow write: offset 0x%x read val 0x%x",
  592. reg_offset, read_value);
  593. return QDF_STATUS_SUCCESS;
  594. }
  595. }
  596. return QDF_STATUS_E_TIMEOUT;
  597. }
  598. /**
  599. * hal_write32_mb_shadow_confirm() - write to shadow reg and
  600. * poll dirty register bit to confirm write
  601. * @hal_soc: hal soc handle
  602. * @reg_offset: target reg offset address from BAR
  603. * @value: value to write
  604. *
  605. * Return: QDF_STATUS_SUCCESS on success
  606. */
  607. static inline QDF_STATUS hal_write32_mb_shadow_confirm(
  608. struct hal_soc *hal,
  609. uint32_t reg_offset,
  610. uint32_t value)
  611. {
  612. int i;
  613. QDF_STATUS ret;
  614. uint32_t shadow_reg_offset;
  615. int shadow_config_index;
  616. bool is_reg_offset_present = false;
  617. for (i = 0; i < MAX_GENERIC_SHADOW_REG; i++) {
  618. /* Found the shadow config for the reg_offset */
  619. struct shadow_reg_config *hal_shadow_reg_list =
  620. &hal->list_shadow_reg_config[i];
  621. if (hal_shadow_reg_list->target_register ==
  622. reg_offset) {
  623. shadow_config_index =
  624. hal_shadow_reg_list->shadow_config_index;
  625. shadow_reg_offset =
  626. SHADOW_REGISTER(shadow_config_index);
  627. hal_write32_mb_confirm(
  628. hal, shadow_reg_offset, value);
  629. is_reg_offset_present = true;
  630. break;
  631. }
  632. ret = QDF_STATUS_E_FAILURE;
  633. }
  634. if (is_reg_offset_present) {
  635. ret = hal_poll_dirty_bit_reg(hal, shadow_config_index);
  636. hal_info("Shadow write:reg 0x%x val 0x%x ret %d",
  637. reg_offset, value, ret);
  638. if (QDF_IS_STATUS_ERROR(ret)) {
  639. HAL_STATS_INC(hal, shadow_reg_write_fail, 1);
  640. return ret;
  641. }
  642. HAL_STATS_INC(hal, shadow_reg_write_succ, 1);
  643. }
  644. return ret;
  645. }
  646. /**
  647. * hal_write32_mb_confirm_retry() - write register with confirming and
  648. do retry/recovery if writing failed
  649. * @hal_soc: hal soc handle
  650. * @offset: offset address from the BAR
  651. * @value: value to write
  652. * @recovery: is recovery needed or not.
  653. *
  654. * Write the register value with confirming and read it back, if
  655. * read back value is not as expected, do retry for writing, if
  656. * retry hit max times allowed but still fail, check if recovery
  657. * needed.
  658. *
  659. * Return: None
  660. */
  661. static inline void hal_write32_mb_confirm_retry(struct hal_soc *hal_soc,
  662. uint32_t offset,
  663. uint32_t value,
  664. bool recovery)
  665. {
  666. QDF_STATUS ret;
  667. ret = hal_write32_mb_shadow_confirm(hal_soc, offset, value);
  668. if (QDF_IS_STATUS_ERROR(ret) && recovery)
  669. qdf_trigger_self_recovery(NULL, QDF_HAL_REG_WRITE_FAILURE);
  670. }
  671. #else /* GENERIC_SHADOW_REGISTER_ACCESS_ENABLE */
  672. static inline void hal_write32_mb_confirm_retry(struct hal_soc *hal_soc,
  673. uint32_t offset,
  674. uint32_t value,
  675. bool recovery)
  676. {
  677. uint8_t retry_cnt = 0;
  678. uint32_t read_value;
  679. while (retry_cnt <= HAL_REG_WRITE_RETRY_MAX) {
  680. hal_write32_mb_confirm(hal_soc, offset, value);
  681. read_value = hal_read32_mb(hal_soc, offset);
  682. if (qdf_likely(read_value == value))
  683. break;
  684. /* write failed, do retry */
  685. hal_warn("Retry reg offset 0x%x, value 0x%x, read value 0x%x",
  686. offset, value, read_value);
  687. qdf_mdelay(HAL_REG_WRITE_RETRY_DELAY);
  688. retry_cnt++;
  689. }
  690. if (retry_cnt > HAL_REG_WRITE_RETRY_MAX && recovery)
  691. qdf_trigger_self_recovery(NULL, QDF_HAL_REG_WRITE_FAILURE);
  692. }
  693. #endif /* GENERIC_SHADOW_REGISTER_ACCESS_ENABLE */
  694. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  695. /**
  696. * hal_dump_reg_write_srng_stats() - dump SRNG reg write stats
  697. * @hal_soc: HAL soc handle
  698. *
  699. * Return: none
  700. */
  701. void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl);
  702. /**
  703. * hal_dump_reg_write_stats() - dump reg write stats
  704. * @hal_soc: HAL soc handle
  705. *
  706. * Return: none
  707. */
  708. void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl);
  709. /**
  710. * hal_get_reg_write_pending_work() - get the number of entries
  711. * pending in the workqueue to be processed.
  712. * @hal_soc: HAL soc handle
  713. *
  714. * Returns: the number of entries pending to be processed
  715. */
  716. int hal_get_reg_write_pending_work(void *hal_soc);
  717. #else
  718. static inline void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
  719. {
  720. }
  721. static inline void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl)
  722. {
  723. }
  724. static inline int hal_get_reg_write_pending_work(void *hal_soc)
  725. {
  726. return 0;
  727. }
  728. #endif
  729. /**
  730. * hal_read_address_32_mb() - Read 32-bit value from the register
  731. * @soc: soc handle
  732. * @addr: register address to read
  733. *
  734. * Return: 32-bit value
  735. */
  736. static inline
  737. uint32_t hal_read_address_32_mb(struct hal_soc *soc,
  738. qdf_iomem_t addr)
  739. {
  740. uint32_t offset;
  741. uint32_t ret;
  742. if (!soc->use_register_windowing)
  743. return qdf_ioread32(addr);
  744. offset = addr - soc->dev_base_addr;
  745. ret = hal_read32_mb(soc, offset);
  746. return ret;
  747. }
  748. /**
  749. * hal_attach - Initialize HAL layer
  750. * @hif_handle: Opaque HIF handle
  751. * @qdf_dev: QDF device
  752. *
  753. * Return: Opaque HAL SOC handle
  754. * NULL on failure (if given ring is not available)
  755. *
  756. * This function should be called as part of HIF initialization (for accessing
  757. * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle()
  758. */
  759. void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev);
  760. /**
  761. * hal_detach - Detach HAL layer
  762. * @hal_soc: HAL SOC handle
  763. *
  764. * This function should be called as part of HIF detach
  765. *
  766. */
  767. extern void hal_detach(void *hal_soc);
  768. #define HAL_SRNG_LMAC_RING 0x80000000
  769. /* SRNG flags passed in hal_srng_params.flags */
  770. #define HAL_SRNG_MSI_SWAP 0x00000008
  771. #define HAL_SRNG_RING_PTR_SWAP 0x00000010
  772. #define HAL_SRNG_DATA_TLV_SWAP 0x00000020
  773. #define HAL_SRNG_LOW_THRES_INTR_ENABLE 0x00010000
  774. #define HAL_SRNG_MSI_INTR 0x00020000
  775. #define HAL_SRNG_CACHED_DESC 0x00040000
  776. #if defined(QCA_WIFI_QCA6490) || defined(QCA_WIFI_KIWI)
  777. #define HAL_SRNG_PREFETCH_TIMER 1
  778. #else
  779. #define HAL_SRNG_PREFETCH_TIMER 0
  780. #endif
  781. #define PN_SIZE_24 0
  782. #define PN_SIZE_48 1
  783. #define PN_SIZE_128 2
  784. #ifdef FORCE_WAKE
  785. /**
  786. * hal_set_init_phase() - Indicate initialization of
  787. * datapath rings
  788. * @soc: hal_soc handle
  789. * @init_phase: flag to indicate datapath rings
  790. * initialization status
  791. *
  792. * Return: None
  793. */
  794. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase);
  795. #else
  796. static inline
  797. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase)
  798. {
  799. }
  800. #endif /* FORCE_WAKE */
  801. /**
  802. * hal_srng_get_entrysize - Returns size of ring entry in bytes. Should be
  803. * used by callers for calculating the size of memory to be allocated before
  804. * calling hal_srng_setup to setup the ring
  805. *
  806. * @hal_soc: Opaque HAL SOC handle
  807. * @ring_type: one of the types from hal_ring_type
  808. *
  809. */
  810. extern uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type);
  811. /**
  812. * hal_srng_max_entries - Returns maximum possible number of ring entries
  813. * @hal_soc: Opaque HAL SOC handle
  814. * @ring_type: one of the types from hal_ring_type
  815. *
  816. * Return: Maximum number of entries for the given ring_type
  817. */
  818. uint32_t hal_srng_max_entries(void *hal_soc, int ring_type);
  819. void hal_set_low_threshold(hal_ring_handle_t hal_ring_hdl,
  820. uint32_t low_threshold);
  821. /**
  822. * hal_srng_dump - Dump ring status
  823. * @srng: hal srng pointer
  824. */
  825. void hal_srng_dump(struct hal_srng *srng);
  826. /**
  827. * hal_srng_get_dir - Returns the direction of the ring
  828. * @hal_soc: Opaque HAL SOC handle
  829. * @ring_type: one of the types from hal_ring_type
  830. *
  831. * Return: Ring direction
  832. */
  833. enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type);
  834. /* HAL memory information */
  835. struct hal_mem_info {
  836. /* dev base virtual addr */
  837. void *dev_base_addr;
  838. /* dev base physical addr */
  839. void *dev_base_paddr;
  840. /* dev base ce virtual addr - applicable only for qca5018 */
  841. /* In qca5018 CE register are outside wcss block */
  842. /* using a separate address space to access CE registers */
  843. void *dev_base_addr_ce;
  844. /* dev base ce physical addr */
  845. void *dev_base_paddr_ce;
  846. /* Remote virtual pointer memory for HW/FW updates */
  847. void *shadow_rdptr_mem_vaddr;
  848. /* Remote physical pointer memory for HW/FW updates */
  849. void *shadow_rdptr_mem_paddr;
  850. /* Shared memory for ring pointer updates from host to FW */
  851. void *shadow_wrptr_mem_vaddr;
  852. /* Shared physical memory for ring pointer updates from host to FW */
  853. void *shadow_wrptr_mem_paddr;
  854. /* lmac srng start id */
  855. uint8_t lmac_srng_start_id;
  856. };
  857. /* SRNG parameters to be passed to hal_srng_setup */
  858. struct hal_srng_params {
  859. /* Physical base address of the ring */
  860. qdf_dma_addr_t ring_base_paddr;
  861. /* Virtual base address of the ring */
  862. void *ring_base_vaddr;
  863. /* Number of entries in ring */
  864. uint32_t num_entries;
  865. /* max transfer length */
  866. uint16_t max_buffer_length;
  867. /* MSI Address */
  868. qdf_dma_addr_t msi_addr;
  869. /* MSI data */
  870. uint32_t msi_data;
  871. /* Interrupt timer threshold – in micro seconds */
  872. uint32_t intr_timer_thres_us;
  873. /* Interrupt batch counter threshold – in number of ring entries */
  874. uint32_t intr_batch_cntr_thres_entries;
  875. /* Low threshold – in number of ring entries
  876. * (valid for src rings only)
  877. */
  878. uint32_t low_threshold;
  879. /* Misc flags */
  880. uint32_t flags;
  881. /* Unique ring id */
  882. uint8_t ring_id;
  883. /* Source or Destination ring */
  884. enum hal_srng_dir ring_dir;
  885. /* Size of ring entry */
  886. uint32_t entry_size;
  887. /* hw register base address */
  888. void *hwreg_base[MAX_SRNG_REG_GROUPS];
  889. /* prefetch timer config - in micro seconds */
  890. uint32_t prefetch_timer;
  891. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  892. /* Near full IRQ support flag */
  893. uint32_t nf_irq_support;
  894. /* MSI2 Address */
  895. qdf_dma_addr_t msi2_addr;
  896. /* MSI2 data */
  897. uint32_t msi2_data;
  898. /* Critical threshold */
  899. uint16_t crit_thresh;
  900. /* High threshold */
  901. uint16_t high_thresh;
  902. /* Safe threshold */
  903. uint16_t safe_thresh;
  904. #endif
  905. };
  906. /* hal_construct_srng_shadow_regs() - initialize the shadow
  907. * registers for srngs
  908. * @hal_soc: hal handle
  909. *
  910. * Return: QDF_STATUS_OK on success
  911. */
  912. QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc);
  913. /* hal_set_one_shadow_config() - add a config for the specified ring
  914. * @hal_soc: hal handle
  915. * @ring_type: ring type
  916. * @ring_num: ring num
  917. *
  918. * The ring type and ring num uniquely specify the ring. After this call,
  919. * the hp/tp will be added as the next entry int the shadow register
  920. * configuration table. The hal code will use the shadow register address
  921. * in place of the hp/tp address.
  922. *
  923. * This function is exposed, so that the CE module can skip configuring shadow
  924. * registers for unused ring and rings assigned to the firmware.
  925. *
  926. * Return: QDF_STATUS_OK on success
  927. */
  928. QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type,
  929. int ring_num);
  930. /**
  931. * hal_get_shadow_config() - retrieve the config table for shadow cfg v2
  932. * @hal_soc: hal handle
  933. * @shadow_config: will point to the table after
  934. * @num_shadow_registers_configured: will contain the number of valid entries
  935. */
  936. extern void
  937. hal_get_shadow_config(void *hal_soc,
  938. struct pld_shadow_reg_v2_cfg **shadow_config,
  939. int *num_shadow_registers_configured);
  940. #ifdef CONFIG_SHADOW_V3
  941. /**
  942. * hal_get_shadow_v3_config() - retrieve the config table for shadow cfg v3
  943. * @hal_soc: hal handle
  944. * @shadow_config: will point to the table after
  945. * @num_shadow_registers_configured: will contain the number of valid entries
  946. */
  947. extern void
  948. hal_get_shadow_v3_config(void *hal_soc,
  949. struct pld_shadow_reg_v3_cfg **shadow_config,
  950. int *num_shadow_registers_configured);
  951. #endif
  952. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  953. /**
  954. * hal_srng_is_near_full_irq_supported() - Check if srng supports near full irq
  955. * @hal_soc: HAL SoC handle [To be validated by caller]
  956. * @ring_type: srng type
  957. * @ring_num: The index of the srng (of the same type)
  958. *
  959. * Return: true, if srng support near full irq trigger
  960. * false, if the srng does not support near full irq support.
  961. */
  962. bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc,
  963. int ring_type, int ring_num);
  964. #else
  965. static inline
  966. bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc,
  967. int ring_type, int ring_num)
  968. {
  969. return false;
  970. }
  971. #endif
  972. /**
  973. * hal_srng_setup - Initialize HW SRNG ring.
  974. *
  975. * @hal_soc: Opaque HAL SOC handle
  976. * @ring_type: one of the types from hal_ring_type
  977. * @ring_num: Ring number if there are multiple rings of
  978. * same type (staring from 0)
  979. * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings
  980. * @ring_params: SRNG ring params in hal_srng_params structure.
  981. * @idle_check: Check if ring is idle
  982. * Callers are expected to allocate contiguous ring memory of size
  983. * 'num_entries * entry_size' bytes and pass the physical and virtual base
  984. * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in hal_srng_params
  985. * structure. Ring base address should be 8 byte aligned and size of each ring
  986. * entry should be queried using the API hal_srng_get_entrysize
  987. *
  988. * Return: Opaque pointer to ring on success
  989. * NULL on failure (if given ring is not available)
  990. */
  991. extern void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
  992. int mac_id, struct hal_srng_params *ring_params, bool idle_check);
  993. /* Remapping ids of REO rings */
  994. #define REO_REMAP_TCL 0
  995. #define REO_REMAP_SW1 1
  996. #define REO_REMAP_SW2 2
  997. #define REO_REMAP_SW3 3
  998. #define REO_REMAP_SW4 4
  999. #define REO_REMAP_RELEASE 5
  1000. #define REO_REMAP_FW 6
  1001. /*
  1002. * In Beryllium: 4 bits REO destination ring value is defined as: 0: TCL
  1003. * 1:SW1 2:SW2 3:SW3 4:SW4 5:Release 6:FW(WIFI) 7:SW5
  1004. * 8:SW6 9:SW7 10:SW8 11: NOT_USED.
  1005. *
  1006. */
  1007. #define REO_REMAP_SW5 7
  1008. #define REO_REMAP_SW6 8
  1009. #define REO_REMAP_SW7 9
  1010. #define REO_REMAP_SW8 10
  1011. /*
  1012. * Macro to access HWIO_REO_R0_ERROR_DESTINATION_RING_CTRL_IX_0
  1013. * to map destination to rings
  1014. */
  1015. #define HAL_REO_ERR_REMAP_IX0(_VALUE, _OFFSET) \
  1016. ((_VALUE) << \
  1017. (HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_ ## \
  1018. DESTINATION_RING_ ## _OFFSET ## _SHFT))
  1019. /*
  1020. * Macro to access HWIO_REO_R0_ERROR_DESTINATION_RING_CTRL_IX_1
  1021. * to map destination to rings
  1022. */
  1023. #define HAL_REO_ERR_REMAP_IX1(_VALUE, _OFFSET) \
  1024. ((_VALUE) << \
  1025. (HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_ ## \
  1026. DESTINATION_RING_ ## _OFFSET ## _SHFT))
  1027. /*
  1028. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0
  1029. * to map destination to rings
  1030. */
  1031. #define HAL_REO_REMAP_IX0(_VALUE, _OFFSET) \
  1032. ((_VALUE) << \
  1033. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_ ## \
  1034. _OFFSET ## _SHFT))
  1035. /*
  1036. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1
  1037. * to map destination to rings
  1038. */
  1039. #define HAL_REO_REMAP_IX2(_VALUE, _OFFSET) \
  1040. ((_VALUE) << \
  1041. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_ ## \
  1042. _OFFSET ## _SHFT))
  1043. /*
  1044. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3
  1045. * to map destination to rings
  1046. */
  1047. #define HAL_REO_REMAP_IX3(_VALUE, _OFFSET) \
  1048. ((_VALUE) << \
  1049. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_ ## \
  1050. _OFFSET ## _SHFT))
  1051. /**
  1052. * hal_reo_read_write_ctrl_ix - Read or write REO_DESTINATION_RING_CTRL_IX
  1053. * @hal_soc_hdl: HAL SOC handle
  1054. * @read: boolean value to indicate if read or write
  1055. * @ix0: pointer to store IX0 reg value
  1056. * @ix1: pointer to store IX1 reg value
  1057. * @ix2: pointer to store IX2 reg value
  1058. * @ix3: pointer to store IX3 reg value
  1059. */
  1060. void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read,
  1061. uint32_t *ix0, uint32_t *ix1,
  1062. uint32_t *ix2, uint32_t *ix3);
  1063. /**
  1064. * hal_srng_set_hp_paddr_confirm() - Set physical address to dest SRNG head
  1065. * pointer and confirm that write went through by reading back the value
  1066. * @sring: sring pointer
  1067. * @paddr: physical address
  1068. *
  1069. * Return: None
  1070. */
  1071. extern void hal_srng_dst_set_hp_paddr_confirm(struct hal_srng *sring,
  1072. uint64_t paddr);
  1073. /**
  1074. * hal_srng_dst_init_hp() - Initilaize head pointer with cached head pointer
  1075. * @hal_soc: hal_soc handle
  1076. * @srng: sring pointer
  1077. * @vaddr: virtual address
  1078. */
  1079. void hal_srng_dst_init_hp(struct hal_soc_handle *hal_soc,
  1080. struct hal_srng *srng,
  1081. uint32_t *vaddr);
  1082. /**
  1083. * hal_srng_cleanup - Deinitialize HW SRNG ring.
  1084. * @hal_soc: Opaque HAL SOC handle
  1085. * @hal_srng: Opaque HAL SRNG pointer
  1086. */
  1087. void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl);
  1088. static inline bool hal_srng_initialized(hal_ring_handle_t hal_ring_hdl)
  1089. {
  1090. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1091. return !!srng->initialized;
  1092. }
  1093. /**
  1094. * hal_srng_dst_peek - Check if there are any entries in the ring (peek)
  1095. * @hal_soc: Opaque HAL SOC handle
  1096. * @hal_ring_hdl: Destination ring pointer
  1097. *
  1098. * Caller takes responsibility for any locking needs.
  1099. *
  1100. * Return: Opaque pointer for next ring entry; NULL on failire
  1101. */
  1102. static inline
  1103. void *hal_srng_dst_peek(hal_soc_handle_t hal_soc_hdl,
  1104. hal_ring_handle_t hal_ring_hdl)
  1105. {
  1106. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1107. if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp)
  1108. return (void *)(&srng->ring_base_vaddr[srng->u.dst_ring.tp]);
  1109. return NULL;
  1110. }
  1111. /**
  1112. * hal_mem_dma_cache_sync - Cache sync the specified virtual address Range
  1113. * @hal_soc: HAL soc handle
  1114. * @desc: desc start address
  1115. * @entry_size: size of memory to sync
  1116. *
  1117. * Return: void
  1118. */
  1119. #if defined(__LINUX_MIPS32_ARCH__) || defined(__LINUX_MIPS64_ARCH__)
  1120. static inline void hal_mem_dma_cache_sync(struct hal_soc *soc, uint32_t *desc,
  1121. uint32_t entry_size)
  1122. {
  1123. qdf_nbuf_dma_inv_range((void *)desc, (void *)(desc + entry_size));
  1124. }
  1125. #else
  1126. static inline void hal_mem_dma_cache_sync(struct hal_soc *soc, uint32_t *desc,
  1127. uint32_t entry_size)
  1128. {
  1129. qdf_mem_dma_cache_sync(soc->qdf_dev, qdf_mem_virt_to_phys(desc),
  1130. QDF_DMA_FROM_DEVICE,
  1131. (entry_size * sizeof(uint32_t)));
  1132. }
  1133. #endif
  1134. /**
  1135. * hal_srng_access_start_unlocked - Start ring access (unlocked). Should use
  1136. * hal_srng_access_start if locked access is required
  1137. *
  1138. * @hal_soc: Opaque HAL SOC handle
  1139. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1140. *
  1141. * This API doesn't implement any byte-order conversion on reading hp/tp.
  1142. * So, Use API only for those srngs for which the target writes hp/tp values to
  1143. * the DDR in the Host order.
  1144. *
  1145. * Return: 0 on success; error on failire
  1146. */
  1147. static inline int
  1148. hal_srng_access_start_unlocked(hal_soc_handle_t hal_soc_hdl,
  1149. hal_ring_handle_t hal_ring_hdl)
  1150. {
  1151. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1152. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  1153. uint32_t *desc;
  1154. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1155. srng->u.src_ring.cached_tp =
  1156. *(volatile uint32_t *)(srng->u.src_ring.tp_addr);
  1157. else {
  1158. srng->u.dst_ring.cached_hp =
  1159. *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1160. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  1161. desc = hal_srng_dst_peek(hal_soc_hdl, hal_ring_hdl);
  1162. if (qdf_likely(desc)) {
  1163. hal_mem_dma_cache_sync(soc, desc,
  1164. srng->entry_size);
  1165. qdf_prefetch(desc);
  1166. }
  1167. }
  1168. }
  1169. return 0;
  1170. }
  1171. /**
  1172. * hal_le_srng_access_start_unlocked_in_cpu_order - Start ring access
  1173. * (unlocked) with endianness correction.
  1174. * @hal_soc: Opaque HAL SOC handle
  1175. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1176. *
  1177. * This API provides same functionally as hal_srng_access_start_unlocked()
  1178. * except that it converts the little-endian formatted hp/tp values to
  1179. * Host order on reading them. So, this API should only be used for those srngs
  1180. * for which the target always writes hp/tp values in little-endian order
  1181. * regardless of Host order.
  1182. *
  1183. * Also, this API doesn't take the lock. For locked access, use
  1184. * hal_srng_access_start/hal_le_srng_access_start_in_cpu_order.
  1185. *
  1186. * Return: 0 on success; error on failire
  1187. */
  1188. static inline int
  1189. hal_le_srng_access_start_unlocked_in_cpu_order(
  1190. hal_soc_handle_t hal_soc_hdl,
  1191. hal_ring_handle_t hal_ring_hdl)
  1192. {
  1193. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1194. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  1195. uint32_t *desc;
  1196. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1197. srng->u.src_ring.cached_tp =
  1198. qdf_le32_to_cpu(*(volatile uint32_t *)
  1199. (srng->u.src_ring.tp_addr));
  1200. else {
  1201. srng->u.dst_ring.cached_hp =
  1202. qdf_le32_to_cpu(*(volatile uint32_t *)
  1203. (srng->u.dst_ring.hp_addr));
  1204. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  1205. desc = hal_srng_dst_peek(hal_soc_hdl, hal_ring_hdl);
  1206. if (qdf_likely(desc)) {
  1207. hal_mem_dma_cache_sync(soc, desc,
  1208. srng->entry_size);
  1209. qdf_prefetch(desc);
  1210. }
  1211. }
  1212. }
  1213. return 0;
  1214. }
  1215. /**
  1216. * hal_srng_try_access_start - Try to start (locked) ring access
  1217. *
  1218. * @hal_soc: Opaque HAL SOC handle
  1219. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1220. *
  1221. * Return: 0 on success; error on failure
  1222. */
  1223. static inline int hal_srng_try_access_start(hal_soc_handle_t hal_soc_hdl,
  1224. hal_ring_handle_t hal_ring_hdl)
  1225. {
  1226. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1227. if (qdf_unlikely(!hal_ring_hdl)) {
  1228. qdf_print("Error: Invalid hal_ring\n");
  1229. return -EINVAL;
  1230. }
  1231. if (!SRNG_TRY_LOCK(&(srng->lock)))
  1232. return -EINVAL;
  1233. return hal_srng_access_start_unlocked(hal_soc_hdl, hal_ring_hdl);
  1234. }
  1235. /**
  1236. * hal_srng_access_start - Start (locked) ring access
  1237. *
  1238. * @hal_soc: Opaque HAL SOC handle
  1239. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1240. *
  1241. * This API doesn't implement any byte-order conversion on reading hp/tp.
  1242. * So, Use API only for those srngs for which the target writes hp/tp values to
  1243. * the DDR in the Host order.
  1244. *
  1245. * Return: 0 on success; error on failire
  1246. */
  1247. static inline int hal_srng_access_start(hal_soc_handle_t hal_soc_hdl,
  1248. hal_ring_handle_t hal_ring_hdl)
  1249. {
  1250. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1251. if (qdf_unlikely(!hal_ring_hdl)) {
  1252. qdf_print("Error: Invalid hal_ring\n");
  1253. return -EINVAL;
  1254. }
  1255. SRNG_LOCK(&(srng->lock));
  1256. return hal_srng_access_start_unlocked(hal_soc_hdl, hal_ring_hdl);
  1257. }
  1258. /**
  1259. * hal_le_srng_access_start_in_cpu_order - Start (locked) ring access with
  1260. * endianness correction
  1261. * @hal_soc: Opaque HAL SOC handle
  1262. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1263. *
  1264. * This API provides same functionally as hal_srng_access_start()
  1265. * except that it converts the little-endian formatted hp/tp values to
  1266. * Host order on reading them. So, this API should only be used for those srngs
  1267. * for which the target always writes hp/tp values in little-endian order
  1268. * regardless of Host order.
  1269. *
  1270. * Return: 0 on success; error on failire
  1271. */
  1272. static inline int
  1273. hal_le_srng_access_start_in_cpu_order(
  1274. hal_soc_handle_t hal_soc_hdl,
  1275. hal_ring_handle_t hal_ring_hdl)
  1276. {
  1277. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1278. if (qdf_unlikely(!hal_ring_hdl)) {
  1279. qdf_print("Error: Invalid hal_ring\n");
  1280. return -EINVAL;
  1281. }
  1282. SRNG_LOCK(&(srng->lock));
  1283. return hal_le_srng_access_start_unlocked_in_cpu_order(
  1284. hal_soc_hdl, hal_ring_hdl);
  1285. }
  1286. /**
  1287. * hal_srng_dst_get_next - Get next entry from a destination ring
  1288. * @hal_soc: Opaque HAL SOC handle
  1289. * @hal_ring_hdl: Destination ring pointer
  1290. *
  1291. * Return: Opaque pointer for next ring entry; NULL on failure
  1292. */
  1293. static inline
  1294. void *hal_srng_dst_get_next(void *hal_soc,
  1295. hal_ring_handle_t hal_ring_hdl)
  1296. {
  1297. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1298. uint32_t *desc;
  1299. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  1300. return NULL;
  1301. desc = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1302. /* TODO: Using % is expensive, but we have to do this since
  1303. * size of some SRNG rings is not power of 2 (due to descriptor
  1304. * sizes). Need to create separate API for rings used
  1305. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1306. * SW2RXDMA and CE rings)
  1307. */
  1308. srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size);
  1309. if (srng->u.dst_ring.tp == srng->ring_size)
  1310. srng->u.dst_ring.tp = 0;
  1311. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  1312. struct hal_soc *soc = (struct hal_soc *)hal_soc;
  1313. uint32_t *desc_next;
  1314. uint32_t tp;
  1315. tp = srng->u.dst_ring.tp;
  1316. desc_next = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1317. hal_mem_dma_cache_sync(soc, desc_next, srng->entry_size);
  1318. qdf_prefetch(desc_next);
  1319. }
  1320. return (void *)desc;
  1321. }
  1322. /**
  1323. * hal_srng_dst_get_next_cached - Get cached next entry
  1324. * @hal_soc: Opaque HAL SOC handle
  1325. * @hal_ring_hdl: Destination ring pointer
  1326. *
  1327. * Get next entry from a destination ring and move cached tail pointer
  1328. *
  1329. * Return: Opaque pointer for next ring entry; NULL on failure
  1330. */
  1331. static inline
  1332. void *hal_srng_dst_get_next_cached(void *hal_soc,
  1333. hal_ring_handle_t hal_ring_hdl)
  1334. {
  1335. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1336. uint32_t *desc;
  1337. uint32_t *desc_next;
  1338. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  1339. return NULL;
  1340. desc = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1341. /* TODO: Using % is expensive, but we have to do this since
  1342. * size of some SRNG rings is not power of 2 (due to descriptor
  1343. * sizes). Need to create separate API for rings used
  1344. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1345. * SW2RXDMA and CE rings)
  1346. */
  1347. srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size);
  1348. if (srng->u.dst_ring.tp == srng->ring_size)
  1349. srng->u.dst_ring.tp = 0;
  1350. desc_next = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1351. qdf_prefetch(desc_next);
  1352. return (void *)desc;
  1353. }
  1354. /**
  1355. * hal_srng_dst_dec_tp - decrement the TP of the Dst ring by one entry
  1356. * @hal_soc: Opaque HAL SOC handle
  1357. * @hal_ring_hdl: Destination ring pointer
  1358. *
  1359. * reset the tail pointer in the destination ring by one entry
  1360. *
  1361. */
  1362. static inline
  1363. void hal_srng_dst_dec_tp(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1364. {
  1365. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1366. if (qdf_unlikely(!srng->u.dst_ring.tp))
  1367. srng->u.dst_ring.tp = (srng->ring_size - srng->entry_size);
  1368. else
  1369. srng->u.dst_ring.tp -= srng->entry_size;
  1370. }
  1371. static inline int hal_srng_lock(hal_ring_handle_t hal_ring_hdl)
  1372. {
  1373. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1374. if (qdf_unlikely(!hal_ring_hdl)) {
  1375. qdf_print("error: invalid hal_ring\n");
  1376. return -EINVAL;
  1377. }
  1378. SRNG_LOCK(&(srng->lock));
  1379. return 0;
  1380. }
  1381. static inline int hal_srng_unlock(hal_ring_handle_t hal_ring_hdl)
  1382. {
  1383. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1384. if (qdf_unlikely(!hal_ring_hdl)) {
  1385. qdf_print("error: invalid hal_ring\n");
  1386. return -EINVAL;
  1387. }
  1388. SRNG_UNLOCK(&(srng->lock));
  1389. return 0;
  1390. }
  1391. /**
  1392. * hal_srng_dst_get_next_hp - Get next entry from a destination ring and move
  1393. * cached head pointer
  1394. *
  1395. * @hal_soc: Opaque HAL SOC handle
  1396. * @hal_ring_hdl: Destination ring pointer
  1397. *
  1398. * Return: Opaque pointer for next ring entry; NULL on failire
  1399. */
  1400. static inline void *
  1401. hal_srng_dst_get_next_hp(hal_soc_handle_t hal_soc_hdl,
  1402. hal_ring_handle_t hal_ring_hdl)
  1403. {
  1404. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1405. uint32_t *desc;
  1406. /* TODO: Using % is expensive, but we have to do this since
  1407. * size of some SRNG rings is not power of 2 (due to descriptor
  1408. * sizes). Need to create separate API for rings used
  1409. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1410. * SW2RXDMA and CE rings)
  1411. */
  1412. uint32_t next_hp = (srng->u.dst_ring.cached_hp + srng->entry_size) %
  1413. srng->ring_size;
  1414. if (next_hp != srng->u.dst_ring.tp) {
  1415. desc = &(srng->ring_base_vaddr[srng->u.dst_ring.cached_hp]);
  1416. srng->u.dst_ring.cached_hp = next_hp;
  1417. return (void *)desc;
  1418. }
  1419. return NULL;
  1420. }
  1421. /**
  1422. * hal_srng_dst_peek_sync - Check if there are any entries in the ring (peek)
  1423. * @hal_soc: Opaque HAL SOC handle
  1424. * @hal_ring_hdl: Destination ring pointer
  1425. *
  1426. * Sync cached head pointer with HW.
  1427. * Caller takes responsibility for any locking needs.
  1428. *
  1429. * Return: Opaque pointer for next ring entry; NULL on failire
  1430. */
  1431. static inline
  1432. void *hal_srng_dst_peek_sync(hal_soc_handle_t hal_soc_hdl,
  1433. hal_ring_handle_t hal_ring_hdl)
  1434. {
  1435. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1436. srng->u.dst_ring.cached_hp =
  1437. *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1438. if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp)
  1439. return (void *)(&(srng->ring_base_vaddr[srng->u.dst_ring.tp]));
  1440. return NULL;
  1441. }
  1442. /**
  1443. * hal_srng_dst_peek_sync_locked - Peek for any entries in the ring
  1444. * @hal_soc: Opaque HAL SOC handle
  1445. * @hal_ring_hdl: Destination ring pointer
  1446. *
  1447. * Sync cached head pointer with HW.
  1448. * This function takes up SRNG_LOCK. Should not be called with SRNG lock held.
  1449. *
  1450. * Return: Opaque pointer for next ring entry; NULL on failire
  1451. */
  1452. static inline
  1453. void *hal_srng_dst_peek_sync_locked(hal_soc_handle_t hal_soc_hdl,
  1454. hal_ring_handle_t hal_ring_hdl)
  1455. {
  1456. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1457. void *ring_desc_ptr = NULL;
  1458. if (qdf_unlikely(!hal_ring_hdl)) {
  1459. qdf_print("Error: Invalid hal_ring\n");
  1460. return NULL;
  1461. }
  1462. SRNG_LOCK(&srng->lock);
  1463. ring_desc_ptr = hal_srng_dst_peek_sync(hal_soc_hdl, hal_ring_hdl);
  1464. SRNG_UNLOCK(&srng->lock);
  1465. return ring_desc_ptr;
  1466. }
  1467. #define hal_srng_dst_num_valid_nolock(hal_soc, hal_ring_hdl, sync_hw_ptr) \
  1468. hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, sync_hw_ptr)
  1469. /**
  1470. * hal_srng_dst_num_valid - Returns number of valid entries (to be processed
  1471. * by SW) in destination ring
  1472. *
  1473. * @hal_soc: Opaque HAL SOC handle
  1474. * @hal_ring_hdl: Destination ring pointer
  1475. * @sync_hw_ptr: Sync cached head pointer with HW
  1476. *
  1477. */
  1478. static inline
  1479. uint32_t hal_srng_dst_num_valid(void *hal_soc,
  1480. hal_ring_handle_t hal_ring_hdl,
  1481. int sync_hw_ptr)
  1482. {
  1483. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1484. uint32_t hp;
  1485. uint32_t tp = srng->u.dst_ring.tp;
  1486. if (sync_hw_ptr) {
  1487. hp = *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1488. srng->u.dst_ring.cached_hp = hp;
  1489. } else {
  1490. hp = srng->u.dst_ring.cached_hp;
  1491. }
  1492. if (hp >= tp)
  1493. return (hp - tp) / srng->entry_size;
  1494. return (srng->ring_size - tp + hp) / srng->entry_size;
  1495. }
  1496. /**
  1497. * hal_srng_dst_inv_cached_descs - API to invalidate descriptors in batch mode
  1498. * @hal_soc: Opaque HAL SOC handle
  1499. * @hal_ring_hdl: Destination ring pointer
  1500. * @entry_count: call invalidate API if valid entries available
  1501. *
  1502. * Invalidates a set of cached descriptors starting from TP to cached_HP
  1503. *
  1504. * Return - None
  1505. */
  1506. static inline void hal_srng_dst_inv_cached_descs(void *hal_soc,
  1507. hal_ring_handle_t hal_ring_hdl,
  1508. uint32_t entry_count)
  1509. {
  1510. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1511. uint32_t *first_desc;
  1512. uint32_t *last_desc;
  1513. uint32_t last_desc_index;
  1514. /*
  1515. * If SRNG does not have cached descriptors this
  1516. * API call should be a no op
  1517. */
  1518. if (!(srng->flags & HAL_SRNG_CACHED_DESC))
  1519. return;
  1520. if (!entry_count)
  1521. return;
  1522. first_desc = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1523. last_desc_index = (srng->u.dst_ring.tp +
  1524. (entry_count * srng->entry_size)) %
  1525. srng->ring_size;
  1526. last_desc = &srng->ring_base_vaddr[last_desc_index];
  1527. if (last_desc > (uint32_t *)first_desc)
  1528. /* invalidate from tp to cached_hp */
  1529. qdf_nbuf_dma_inv_range_no_dsb((void *)first_desc,
  1530. (void *)(last_desc));
  1531. else {
  1532. /* invalidate from tp to end of the ring */
  1533. qdf_nbuf_dma_inv_range_no_dsb((void *)first_desc,
  1534. (void *)srng->ring_vaddr_end);
  1535. /* invalidate from start of ring to cached_hp */
  1536. qdf_nbuf_dma_inv_range_no_dsb((void *)srng->ring_base_vaddr,
  1537. (void *)last_desc);
  1538. }
  1539. qdf_dsb();
  1540. }
  1541. /**
  1542. * hal_srng_dst_num_valid_locked - Returns num valid entries to be processed
  1543. *
  1544. * @hal_soc: Opaque HAL SOC handle
  1545. * @hal_ring_hdl: Destination ring pointer
  1546. * @sync_hw_ptr: Sync cached head pointer with HW
  1547. *
  1548. * Returns number of valid entries to be processed by the host driver. The
  1549. * function takes up SRNG lock.
  1550. *
  1551. * Return: Number of valid destination entries
  1552. */
  1553. static inline uint32_t
  1554. hal_srng_dst_num_valid_locked(hal_soc_handle_t hal_soc,
  1555. hal_ring_handle_t hal_ring_hdl,
  1556. int sync_hw_ptr)
  1557. {
  1558. uint32_t num_valid;
  1559. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1560. SRNG_LOCK(&srng->lock);
  1561. num_valid = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, sync_hw_ptr);
  1562. SRNG_UNLOCK(&srng->lock);
  1563. return num_valid;
  1564. }
  1565. /**
  1566. * hal_srng_sync_cachedhp - sync cachehp pointer from hw hp
  1567. *
  1568. * @hal_soc: Opaque HAL SOC handle
  1569. * @hal_ring_hdl: Destination ring pointer
  1570. *
  1571. */
  1572. static inline
  1573. void hal_srng_sync_cachedhp(void *hal_soc,
  1574. hal_ring_handle_t hal_ring_hdl)
  1575. {
  1576. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1577. uint32_t hp;
  1578. hp = *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1579. srng->u.dst_ring.cached_hp = hp;
  1580. }
  1581. /**
  1582. * hal_srng_src_reap_next - Reap next entry from a source ring and move reap
  1583. * pointer. This can be used to release any buffers associated with completed
  1584. * ring entries. Note that this should not be used for posting new descriptor
  1585. * entries. Posting of new entries should be done only using
  1586. * hal_srng_src_get_next_reaped when this function is used for reaping.
  1587. *
  1588. * @hal_soc: Opaque HAL SOC handle
  1589. * @hal_ring_hdl: Source ring pointer
  1590. *
  1591. * Return: Opaque pointer for next ring entry; NULL on failire
  1592. */
  1593. static inline void *
  1594. hal_srng_src_reap_next(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1595. {
  1596. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1597. uint32_t *desc;
  1598. /* TODO: Using % is expensive, but we have to do this since
  1599. * size of some SRNG rings is not power of 2 (due to descriptor
  1600. * sizes). Need to create separate API for rings used
  1601. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1602. * SW2RXDMA and CE rings)
  1603. */
  1604. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1605. srng->ring_size;
  1606. if (next_reap_hp != srng->u.src_ring.cached_tp) {
  1607. desc = &(srng->ring_base_vaddr[next_reap_hp]);
  1608. srng->u.src_ring.reap_hp = next_reap_hp;
  1609. return (void *)desc;
  1610. }
  1611. return NULL;
  1612. }
  1613. /**
  1614. * hal_srng_src_get_next_reaped - Get next entry from a source ring that is
  1615. * already reaped using hal_srng_src_reap_next, for posting new entries to
  1616. * the ring
  1617. *
  1618. * @hal_soc: Opaque HAL SOC handle
  1619. * @hal_ring_hdl: Source ring pointer
  1620. *
  1621. * Return: Opaque pointer for next (reaped) source ring entry; NULL on failire
  1622. */
  1623. static inline void *
  1624. hal_srng_src_get_next_reaped(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1625. {
  1626. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1627. uint32_t *desc;
  1628. if (srng->u.src_ring.hp != srng->u.src_ring.reap_hp) {
  1629. desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]);
  1630. srng->u.src_ring.hp = (srng->u.src_ring.hp + srng->entry_size) %
  1631. srng->ring_size;
  1632. return (void *)desc;
  1633. }
  1634. return NULL;
  1635. }
  1636. /**
  1637. * hal_srng_src_pending_reap_next - Reap next entry from a source ring and
  1638. * move reap pointer. This API is used in detach path to release any buffers
  1639. * associated with ring entries which are pending reap.
  1640. *
  1641. * @hal_soc: Opaque HAL SOC handle
  1642. * @hal_ring_hdl: Source ring pointer
  1643. *
  1644. * Return: Opaque pointer for next ring entry; NULL on failire
  1645. */
  1646. static inline void *
  1647. hal_srng_src_pending_reap_next(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1648. {
  1649. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1650. uint32_t *desc;
  1651. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1652. srng->ring_size;
  1653. if (next_reap_hp != srng->u.src_ring.hp) {
  1654. desc = &(srng->ring_base_vaddr[next_reap_hp]);
  1655. srng->u.src_ring.reap_hp = next_reap_hp;
  1656. return (void *)desc;
  1657. }
  1658. return NULL;
  1659. }
  1660. /**
  1661. * hal_srng_src_done_val -
  1662. *
  1663. * @hal_soc: Opaque HAL SOC handle
  1664. * @hal_ring_hdl: Source ring pointer
  1665. *
  1666. * Return: Opaque pointer for next ring entry; NULL on failire
  1667. */
  1668. static inline uint32_t
  1669. hal_srng_src_done_val(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1670. {
  1671. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1672. /* TODO: Using % is expensive, but we have to do this since
  1673. * size of some SRNG rings is not power of 2 (due to descriptor
  1674. * sizes). Need to create separate API for rings used
  1675. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1676. * SW2RXDMA and CE rings)
  1677. */
  1678. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1679. srng->ring_size;
  1680. if (next_reap_hp == srng->u.src_ring.cached_tp)
  1681. return 0;
  1682. if (srng->u.src_ring.cached_tp > next_reap_hp)
  1683. return (srng->u.src_ring.cached_tp - next_reap_hp) /
  1684. srng->entry_size;
  1685. else
  1686. return ((srng->ring_size - next_reap_hp) +
  1687. srng->u.src_ring.cached_tp) / srng->entry_size;
  1688. }
  1689. /**
  1690. * hal_get_entrysize_from_srng() - Retrieve ring entry size
  1691. * @hal_ring_hdl: Source ring pointer
  1692. *
  1693. * srng->entry_size value is in 4 byte dwords so left shifting
  1694. * this by 2 to return the value of entry_size in bytes.
  1695. *
  1696. * Return: uint8_t
  1697. */
  1698. static inline
  1699. uint8_t hal_get_entrysize_from_srng(hal_ring_handle_t hal_ring_hdl)
  1700. {
  1701. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1702. return srng->entry_size << 2;
  1703. }
  1704. /**
  1705. * hal_get_sw_hptp - Get SW head and tail pointer location for any ring
  1706. * @hal_soc: Opaque HAL SOC handle
  1707. * @hal_ring_hdl: Source ring pointer
  1708. * @tailp: Tail Pointer
  1709. * @headp: Head Pointer
  1710. *
  1711. * Return: Update tail pointer and head pointer in arguments.
  1712. */
  1713. static inline
  1714. void hal_get_sw_hptp(void *hal_soc, hal_ring_handle_t hal_ring_hdl,
  1715. uint32_t *tailp, uint32_t *headp)
  1716. {
  1717. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1718. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1719. *headp = srng->u.src_ring.hp;
  1720. *tailp = *srng->u.src_ring.tp_addr;
  1721. } else {
  1722. *tailp = srng->u.dst_ring.tp;
  1723. *headp = *srng->u.dst_ring.hp_addr;
  1724. }
  1725. }
  1726. #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
  1727. /**
  1728. * hal_srng_src_get_next_consumed - Get the next desc if consumed by HW
  1729. *
  1730. * @hal_soc: Opaque HAL SOC handle
  1731. * @hal_ring_hdl: Source ring pointer
  1732. *
  1733. * Return: pointer to descriptor if consumed by HW, else NULL
  1734. */
  1735. static inline
  1736. void *hal_srng_src_get_next_consumed(void *hal_soc,
  1737. hal_ring_handle_t hal_ring_hdl)
  1738. {
  1739. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1740. uint32_t *desc = NULL;
  1741. /* TODO: Using % is expensive, but we have to do this since
  1742. * size of some SRNG rings is not power of 2 (due to descriptor
  1743. * sizes). Need to create separate API for rings used
  1744. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1745. * SW2RXDMA and CE rings)
  1746. */
  1747. uint32_t next_entry = (srng->last_desc_cleared + srng->entry_size) %
  1748. srng->ring_size;
  1749. if (next_entry != srng->u.src_ring.cached_tp) {
  1750. desc = &srng->ring_base_vaddr[next_entry];
  1751. srng->last_desc_cleared = next_entry;
  1752. }
  1753. return desc;
  1754. }
  1755. #else
  1756. static inline
  1757. void *hal_srng_src_get_next_consumed(void *hal_soc,
  1758. hal_ring_handle_t hal_ring_hdl)
  1759. {
  1760. return NULL;
  1761. }
  1762. #endif /* CLEAR_SW2TCL_CONSUMED_DESC */
  1763. /**
  1764. * hal_srng_src_get_next - Get next entry from a source ring and move cached tail pointer
  1765. *
  1766. * @hal_soc: Opaque HAL SOC handle
  1767. * @hal_ring_hdl: Source ring pointer
  1768. *
  1769. * Return: Opaque pointer for next ring entry; NULL on failire
  1770. */
  1771. static inline
  1772. void *hal_srng_src_get_next(void *hal_soc,
  1773. hal_ring_handle_t hal_ring_hdl)
  1774. {
  1775. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1776. uint32_t *desc;
  1777. /* TODO: Using % is expensive, but we have to do this since
  1778. * size of some SRNG rings is not power of 2 (due to descriptor
  1779. * sizes). Need to create separate API for rings used
  1780. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1781. * SW2RXDMA and CE rings)
  1782. */
  1783. uint32_t next_hp = (srng->u.src_ring.hp + srng->entry_size) %
  1784. srng->ring_size;
  1785. if (next_hp != srng->u.src_ring.cached_tp) {
  1786. desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]);
  1787. srng->u.src_ring.hp = next_hp;
  1788. /* TODO: Since reap function is not used by all rings, we can
  1789. * remove the following update of reap_hp in this function
  1790. * if we can ensure that only hal_srng_src_get_next_reaped
  1791. * is used for the rings requiring reap functionality
  1792. */
  1793. srng->u.src_ring.reap_hp = next_hp;
  1794. return (void *)desc;
  1795. }
  1796. return NULL;
  1797. }
  1798. /**
  1799. * hal_srng_src_peek_n_get_next - Get next entry from a ring without
  1800. * moving head pointer.
  1801. * hal_srng_src_get_next should be called subsequently to move the head pointer
  1802. *
  1803. * @hal_soc: Opaque HAL SOC handle
  1804. * @hal_ring_hdl: Source ring pointer
  1805. *
  1806. * Return: Opaque pointer for next ring entry; NULL on failire
  1807. */
  1808. static inline
  1809. void *hal_srng_src_peek_n_get_next(hal_soc_handle_t hal_soc_hdl,
  1810. hal_ring_handle_t hal_ring_hdl)
  1811. {
  1812. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1813. uint32_t *desc;
  1814. /* TODO: Using % is expensive, but we have to do this since
  1815. * size of some SRNG rings is not power of 2 (due to descriptor
  1816. * sizes). Need to create separate API for rings used
  1817. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1818. * SW2RXDMA and CE rings)
  1819. */
  1820. if (((srng->u.src_ring.hp + srng->entry_size) %
  1821. srng->ring_size) != srng->u.src_ring.cached_tp) {
  1822. desc = &(srng->ring_base_vaddr[(srng->u.src_ring.hp +
  1823. srng->entry_size) %
  1824. srng->ring_size]);
  1825. return (void *)desc;
  1826. }
  1827. return NULL;
  1828. }
  1829. /**
  1830. * hal_srng_src_peek_n_get_next_next - Get next to next, i.e HP + 2 entry
  1831. * from a ring without moving head pointer.
  1832. *
  1833. * @hal_soc: Opaque HAL SOC handle
  1834. * @hal_ring_hdl: Source ring pointer
  1835. *
  1836. * Return: Opaque pointer for next to next ring entry; NULL on failire
  1837. */
  1838. static inline
  1839. void *hal_srng_src_peek_n_get_next_next(hal_soc_handle_t hal_soc_hdl,
  1840. hal_ring_handle_t hal_ring_hdl)
  1841. {
  1842. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1843. uint32_t *desc;
  1844. /* TODO: Using % is expensive, but we have to do this since
  1845. * size of some SRNG rings is not power of 2 (due to descriptor
  1846. * sizes). Need to create separate API for rings used
  1847. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1848. * SW2RXDMA and CE rings)
  1849. */
  1850. if ((((srng->u.src_ring.hp + (srng->entry_size)) %
  1851. srng->ring_size) != srng->u.src_ring.cached_tp) &&
  1852. (((srng->u.src_ring.hp + (srng->entry_size * 2)) %
  1853. srng->ring_size) != srng->u.src_ring.cached_tp)) {
  1854. desc = &(srng->ring_base_vaddr[(srng->u.src_ring.hp +
  1855. (srng->entry_size * 2)) %
  1856. srng->ring_size]);
  1857. return (void *)desc;
  1858. }
  1859. return NULL;
  1860. }
  1861. /**
  1862. * hal_srng_src_get_cur_hp_n_move_next () - API returns current hp
  1863. * and move hp to next in src ring
  1864. *
  1865. * Usage: This API should only be used at init time replenish.
  1866. *
  1867. * @hal_soc_hdl: HAL soc handle
  1868. * @hal_ring_hdl: Source ring pointer
  1869. *
  1870. */
  1871. static inline void *
  1872. hal_srng_src_get_cur_hp_n_move_next(hal_soc_handle_t hal_soc_hdl,
  1873. hal_ring_handle_t hal_ring_hdl)
  1874. {
  1875. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1876. uint32_t *cur_desc = NULL;
  1877. uint32_t next_hp;
  1878. cur_desc = &srng->ring_base_vaddr[(srng->u.src_ring.hp)];
  1879. next_hp = (srng->u.src_ring.hp + srng->entry_size) %
  1880. srng->ring_size;
  1881. if (next_hp != srng->u.src_ring.cached_tp)
  1882. srng->u.src_ring.hp = next_hp;
  1883. return (void *)cur_desc;
  1884. }
  1885. /**
  1886. * hal_srng_src_num_avail - Returns number of available entries in src ring
  1887. *
  1888. * @hal_soc: Opaque HAL SOC handle
  1889. * @hal_ring_hdl: Source ring pointer
  1890. * @sync_hw_ptr: Sync cached tail pointer with HW
  1891. *
  1892. */
  1893. static inline uint32_t
  1894. hal_srng_src_num_avail(void *hal_soc,
  1895. hal_ring_handle_t hal_ring_hdl, int sync_hw_ptr)
  1896. {
  1897. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1898. uint32_t tp;
  1899. uint32_t hp = srng->u.src_ring.hp;
  1900. if (sync_hw_ptr) {
  1901. tp = *(srng->u.src_ring.tp_addr);
  1902. srng->u.src_ring.cached_tp = tp;
  1903. } else {
  1904. tp = srng->u.src_ring.cached_tp;
  1905. }
  1906. if (tp > hp)
  1907. return ((tp - hp) / srng->entry_size) - 1;
  1908. else
  1909. return ((srng->ring_size - hp + tp) / srng->entry_size) - 1;
  1910. }
  1911. #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING
  1912. /**
  1913. * hal_srng_clear_ring_usage_wm_locked() - Clear SRNG usage watermark stats
  1914. * @hal_soc_hdl: HAL soc handle
  1915. * @hal_ring_hdl: SRNG handle
  1916. *
  1917. * This function tries to acquire SRNG lock, and hence should not be called
  1918. * from a context which has already acquired the SRNG lock.
  1919. *
  1920. * Return: None
  1921. */
  1922. static inline
  1923. void hal_srng_clear_ring_usage_wm_locked(hal_soc_handle_t hal_soc_hdl,
  1924. hal_ring_handle_t hal_ring_hdl)
  1925. {
  1926. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1927. SRNG_LOCK(&srng->lock);
  1928. srng->high_wm.val = 0;
  1929. srng->high_wm.timestamp = 0;
  1930. qdf_mem_zero(&srng->high_wm.bins[0], sizeof(srng->high_wm.bins[0]) *
  1931. HAL_SRNG_HIGH_WM_BIN_MAX);
  1932. SRNG_UNLOCK(&srng->lock);
  1933. }
  1934. /**
  1935. * hal_srng_update_ring_usage_wm_no_lock() - Update the SRNG usage wm stats
  1936. * @hal_soc_hdl: HAL soc handle
  1937. * @hal_ring_hdl: SRNG handle
  1938. *
  1939. * This function should be called with the SRNG lock held.
  1940. *
  1941. * Return: None
  1942. */
  1943. static inline
  1944. void hal_srng_update_ring_usage_wm_no_lock(hal_soc_handle_t hal_soc_hdl,
  1945. hal_ring_handle_t hal_ring_hdl)
  1946. {
  1947. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1948. uint32_t curr_wm_val = 0;
  1949. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1950. curr_wm_val = hal_srng_src_num_avail(hal_soc_hdl, hal_ring_hdl,
  1951. 0);
  1952. else
  1953. curr_wm_val = hal_srng_dst_num_valid(hal_soc_hdl, hal_ring_hdl,
  1954. 0);
  1955. if (curr_wm_val > srng->high_wm.val) {
  1956. srng->high_wm.val = curr_wm_val;
  1957. srng->high_wm.timestamp = qdf_get_system_timestamp();
  1958. }
  1959. if (curr_wm_val >=
  1960. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_90_to_100])
  1961. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_90_to_100]++;
  1962. else if (curr_wm_val >=
  1963. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_80_to_90])
  1964. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_80_to_90]++;
  1965. else if (curr_wm_val >=
  1966. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_70_to_80])
  1967. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_70_to_80]++;
  1968. else if (curr_wm_val >=
  1969. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_60_to_70])
  1970. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_60_to_70]++;
  1971. else if (curr_wm_val >=
  1972. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_50_to_60])
  1973. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_50_to_60]++;
  1974. else
  1975. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT]++;
  1976. }
  1977. static inline
  1978. int hal_dump_srng_high_wm_stats(hal_soc_handle_t hal_soc_hdl,
  1979. hal_ring_handle_t hal_ring_hdl,
  1980. char *buf, int buf_len, int pos)
  1981. {
  1982. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1983. return qdf_scnprintf(buf + pos, buf_len - pos,
  1984. "%8u %7u %12llu %10u %10u %10u %10u %10u %10u",
  1985. srng->ring_id, srng->high_wm.val,
  1986. srng->high_wm.timestamp,
  1987. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT],
  1988. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_50_to_60],
  1989. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_60_to_70],
  1990. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_70_to_80],
  1991. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_80_to_90],
  1992. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_90_to_100]);
  1993. }
  1994. #else
  1995. /**
  1996. * hal_srng_clear_ring_usage_wm_locked() - Clear SRNG usage watermark stats
  1997. * @hal_soc_hdl: HAL soc handle
  1998. * @hal_ring_hdl: SRNG handle
  1999. *
  2000. * This function tries to acquire SRNG lock, and hence should not be called
  2001. * from a context which has already acquired the SRNG lock.
  2002. *
  2003. * Return: None
  2004. */
  2005. static inline
  2006. void hal_srng_clear_ring_usage_wm_locked(hal_soc_handle_t hal_soc_hdl,
  2007. hal_ring_handle_t hal_ring_hdl)
  2008. {
  2009. }
  2010. /**
  2011. * hal_srng_update_ring_usage_wm_no_lock() - Update the SRNG usage wm stats
  2012. * @hal_soc_hdl: HAL soc handle
  2013. * @hal_ring_hdl: SRNG handle
  2014. *
  2015. * This function should be called with the SRNG lock held.
  2016. *
  2017. * Return: None
  2018. */
  2019. static inline
  2020. void hal_srng_update_ring_usage_wm_no_lock(hal_soc_handle_t hal_soc_hdl,
  2021. hal_ring_handle_t hal_ring_hdl)
  2022. {
  2023. }
  2024. static inline
  2025. int hal_dump_srng_high_wm_stats(hal_soc_handle_t hal_soc_hdl,
  2026. hal_ring_handle_t hal_ring_hdl,
  2027. char *buf, int buf_len, int pos)
  2028. {
  2029. return 0;
  2030. }
  2031. #endif
  2032. /**
  2033. * hal_srng_access_end_unlocked - End ring access (unlocked) - update cached
  2034. * ring head/tail pointers to HW.
  2035. *
  2036. * @hal_soc: Opaque HAL SOC handle
  2037. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2038. *
  2039. * The target expects cached head/tail pointer to be updated to the
  2040. * shared location in the little-endian order, This API ensures that.
  2041. * This API should be used only if hal_srng_access_start_unlocked was used to
  2042. * start ring access
  2043. *
  2044. * Return: None
  2045. */
  2046. static inline void
  2047. hal_srng_access_end_unlocked(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  2048. {
  2049. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2050. /* TODO: See if we need a write memory barrier here */
  2051. if (srng->flags & HAL_SRNG_LMAC_RING) {
  2052. /* For LMAC rings, ring pointer updates are done through FW and
  2053. * hence written to a shared memory location that is read by FW
  2054. */
  2055. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  2056. *srng->u.src_ring.hp_addr =
  2057. qdf_cpu_to_le32(srng->u.src_ring.hp);
  2058. } else {
  2059. *srng->u.dst_ring.tp_addr =
  2060. qdf_cpu_to_le32(srng->u.dst_ring.tp);
  2061. }
  2062. } else {
  2063. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  2064. hal_srng_write_address_32_mb(hal_soc,
  2065. srng,
  2066. srng->u.src_ring.hp_addr,
  2067. srng->u.src_ring.hp);
  2068. else
  2069. hal_srng_write_address_32_mb(hal_soc,
  2070. srng,
  2071. srng->u.dst_ring.tp_addr,
  2072. srng->u.dst_ring.tp);
  2073. }
  2074. }
  2075. /* hal_srng_access_end_unlocked already handles endianness conversion,
  2076. * use the same.
  2077. */
  2078. #define hal_le_srng_access_end_unlocked_in_cpu_order \
  2079. hal_srng_access_end_unlocked
  2080. /**
  2081. * hal_srng_access_end - Unlock ring access and update cached ring head/tail
  2082. * pointers to HW
  2083. *
  2084. * @hal_soc: Opaque HAL SOC handle
  2085. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2086. *
  2087. * The target expects cached head/tail pointer to be updated to the
  2088. * shared location in the little-endian order, This API ensures that.
  2089. * This API should be used only if hal_srng_access_start was used to
  2090. * start ring access
  2091. *
  2092. */
  2093. static inline void
  2094. hal_srng_access_end(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  2095. {
  2096. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2097. if (qdf_unlikely(!hal_ring_hdl)) {
  2098. qdf_print("Error: Invalid hal_ring\n");
  2099. return;
  2100. }
  2101. hal_srng_access_end_unlocked(hal_soc, hal_ring_hdl);
  2102. SRNG_UNLOCK(&(srng->lock));
  2103. }
  2104. #ifdef FEATURE_RUNTIME_PM
  2105. #define hal_srng_access_end_v1 hal_srng_rtpm_access_end
  2106. /**
  2107. * hal_srng_rtpm_access_end - RTPM aware, Unlock ring access
  2108. * @hal_soc: Opaque HAL SOC handle
  2109. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2110. * @rtpm_dbgid: RTPM debug id
  2111. * @is_critical_ctx: Whether the calling context is critical
  2112. *
  2113. * Function updates the HP/TP value to the hardware register.
  2114. * The target expects cached head/tail pointer to be updated to the
  2115. * shared location in the little-endian order, This API ensures that.
  2116. * This API should be used only if hal_srng_access_start was used to
  2117. * start ring access
  2118. *
  2119. * Return: None
  2120. */
  2121. void
  2122. hal_srng_rtpm_access_end(hal_soc_handle_t hal_soc_hdl,
  2123. hal_ring_handle_t hal_ring_hdl,
  2124. uint32_t rtpm_id);
  2125. #else
  2126. #define hal_srng_access_end_v1(hal_soc_hdl, hal_ring_hdl, rtpm_id) \
  2127. hal_srng_access_end(hal_soc_hdl, hal_ring_hdl)
  2128. #endif
  2129. /* hal_srng_access_end already handles endianness conversion, so use the same */
  2130. #define hal_le_srng_access_end_in_cpu_order \
  2131. hal_srng_access_end
  2132. /**
  2133. * hal_srng_access_end_reap - Unlock ring access
  2134. * This should be used only if hal_srng_access_start to start ring access
  2135. * and should be used only while reaping SRC ring completions
  2136. *
  2137. * @hal_soc: Opaque HAL SOC handle
  2138. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2139. *
  2140. * Return: 0 on success; error on failire
  2141. */
  2142. static inline void
  2143. hal_srng_access_end_reap(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  2144. {
  2145. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2146. SRNG_UNLOCK(&(srng->lock));
  2147. }
  2148. /* TODO: Check if the following definitions is available in HW headers */
  2149. #define WBM_IDLE_SCATTER_BUF_SIZE 32704
  2150. #define NUM_MPDUS_PER_LINK_DESC 6
  2151. #define NUM_MSDUS_PER_LINK_DESC 7
  2152. #define REO_QUEUE_DESC_ALIGN 128
  2153. #define LINK_DESC_ALIGN 128
  2154. #define ADDRESS_MATCH_TAG_VAL 0x5
  2155. /* Number of mpdu link pointers is 9 in case of TX_MPDU_QUEUE_HEAD and 14 in
  2156. * of TX_MPDU_QUEUE_EXT. We are defining a common average count here
  2157. */
  2158. #define NUM_MPDU_LINKS_PER_QUEUE_DESC 12
  2159. /* TODO: Check with HW team on the scatter buffer size supported. As per WBM
  2160. * MLD, scatter_buffer_size in IDLE_LIST_CONTROL register is 9 bits and size
  2161. * should be specified in 16 word units. But the number of bits defined for
  2162. * this field in HW header files is 5.
  2163. */
  2164. #define WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE 8
  2165. /**
  2166. * hal_idle_list_scatter_buf_size - Get the size of each scatter buffer
  2167. * in an idle list
  2168. *
  2169. * @hal_soc: Opaque HAL SOC handle
  2170. *
  2171. */
  2172. static inline
  2173. uint32_t hal_idle_list_scatter_buf_size(hal_soc_handle_t hal_soc_hdl)
  2174. {
  2175. return WBM_IDLE_SCATTER_BUF_SIZE;
  2176. }
  2177. /**
  2178. * hal_get_link_desc_size - Get the size of each link descriptor
  2179. *
  2180. * @hal_soc: Opaque HAL SOC handle
  2181. *
  2182. */
  2183. static inline uint32_t hal_get_link_desc_size(hal_soc_handle_t hal_soc_hdl)
  2184. {
  2185. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2186. if (!hal_soc || !hal_soc->ops) {
  2187. qdf_print("Error: Invalid ops\n");
  2188. QDF_BUG(0);
  2189. return -EINVAL;
  2190. }
  2191. if (!hal_soc->ops->hal_get_link_desc_size) {
  2192. qdf_print("Error: Invalid function pointer\n");
  2193. QDF_BUG(0);
  2194. return -EINVAL;
  2195. }
  2196. return hal_soc->ops->hal_get_link_desc_size();
  2197. }
  2198. /**
  2199. * hal_get_link_desc_align - Get the required start address alignment for
  2200. * link descriptors
  2201. *
  2202. * @hal_soc: Opaque HAL SOC handle
  2203. *
  2204. */
  2205. static inline
  2206. uint32_t hal_get_link_desc_align(hal_soc_handle_t hal_soc_hdl)
  2207. {
  2208. return LINK_DESC_ALIGN;
  2209. }
  2210. /**
  2211. * hal_num_mpdus_per_link_desc - Get number of mpdus each link desc can hold
  2212. *
  2213. * @hal_soc: Opaque HAL SOC handle
  2214. *
  2215. */
  2216. static inline
  2217. uint32_t hal_num_mpdus_per_link_desc(hal_soc_handle_t hal_soc_hdl)
  2218. {
  2219. return NUM_MPDUS_PER_LINK_DESC;
  2220. }
  2221. /**
  2222. * hal_num_msdus_per_link_desc - Get number of msdus each link desc can hold
  2223. *
  2224. * @hal_soc: Opaque HAL SOC handle
  2225. *
  2226. */
  2227. static inline
  2228. uint32_t hal_num_msdus_per_link_desc(hal_soc_handle_t hal_soc_hdl)
  2229. {
  2230. return NUM_MSDUS_PER_LINK_DESC;
  2231. }
  2232. /**
  2233. * hal_num_mpdu_links_per_queue_desc - Get number of mpdu links each queue
  2234. * descriptor can hold
  2235. *
  2236. * @hal_soc: Opaque HAL SOC handle
  2237. *
  2238. */
  2239. static inline
  2240. uint32_t hal_num_mpdu_links_per_queue_desc(hal_soc_handle_t hal_soc_hdl)
  2241. {
  2242. return NUM_MPDU_LINKS_PER_QUEUE_DESC;
  2243. }
  2244. /**
  2245. * hal_idle_list_scatter_buf_num_entries - Get the number of link desc entries
  2246. * that the given buffer size
  2247. *
  2248. * @hal_soc: Opaque HAL SOC handle
  2249. * @scatter_buf_size: Size of scatter buffer
  2250. *
  2251. */
  2252. static inline
  2253. uint32_t hal_idle_scatter_buf_num_entries(hal_soc_handle_t hal_soc_hdl,
  2254. uint32_t scatter_buf_size)
  2255. {
  2256. return (scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) /
  2257. hal_srng_get_entrysize(hal_soc_hdl, WBM_IDLE_LINK);
  2258. }
  2259. /**
  2260. * hal_idle_list_num_scatter_bufs - Get the number of sctater buffer
  2261. * each given buffer size
  2262. *
  2263. * @hal_soc: Opaque HAL SOC handle
  2264. * @total_mem: size of memory to be scattered
  2265. * @scatter_buf_size: Size of scatter buffer
  2266. *
  2267. */
  2268. static inline
  2269. uint32_t hal_idle_list_num_scatter_bufs(hal_soc_handle_t hal_soc_hdl,
  2270. uint32_t total_mem,
  2271. uint32_t scatter_buf_size)
  2272. {
  2273. uint8_t rem = (total_mem % (scatter_buf_size -
  2274. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)) ? 1 : 0;
  2275. uint32_t num_scatter_bufs = (total_mem / (scatter_buf_size -
  2276. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)) + rem;
  2277. return num_scatter_bufs;
  2278. }
  2279. enum hal_pn_type {
  2280. HAL_PN_NONE,
  2281. HAL_PN_WPA,
  2282. HAL_PN_WAPI_EVEN,
  2283. HAL_PN_WAPI_UNEVEN,
  2284. };
  2285. #define HAL_RX_BA_WINDOW_256 256
  2286. #define HAL_RX_BA_WINDOW_1024 1024
  2287. /**
  2288. * hal_get_reo_qdesc_align - Get start address alignment for reo
  2289. * queue descriptors
  2290. *
  2291. * @hal_soc: Opaque HAL SOC handle
  2292. *
  2293. */
  2294. static inline
  2295. uint32_t hal_get_reo_qdesc_align(hal_soc_handle_t hal_soc_hdl)
  2296. {
  2297. return REO_QUEUE_DESC_ALIGN;
  2298. }
  2299. /**
  2300. * hal_srng_get_hp_addr - Get head pointer physical address
  2301. *
  2302. * @hal_soc: Opaque HAL SOC handle
  2303. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2304. *
  2305. */
  2306. static inline qdf_dma_addr_t
  2307. hal_srng_get_hp_addr(void *hal_soc,
  2308. hal_ring_handle_t hal_ring_hdl)
  2309. {
  2310. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2311. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  2312. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  2313. return hal->shadow_wrptr_mem_paddr +
  2314. ((unsigned long)(srng->u.src_ring.hp_addr) -
  2315. (unsigned long)(hal->shadow_wrptr_mem_vaddr));
  2316. } else {
  2317. return hal->shadow_rdptr_mem_paddr +
  2318. ((unsigned long)(srng->u.dst_ring.hp_addr) -
  2319. (unsigned long)(hal->shadow_rdptr_mem_vaddr));
  2320. }
  2321. }
  2322. /**
  2323. * hal_srng_get_tp_addr - Get tail pointer physical address
  2324. *
  2325. * @hal_soc: Opaque HAL SOC handle
  2326. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2327. *
  2328. */
  2329. static inline qdf_dma_addr_t
  2330. hal_srng_get_tp_addr(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  2331. {
  2332. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2333. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  2334. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  2335. return hal->shadow_rdptr_mem_paddr +
  2336. ((unsigned long)(srng->u.src_ring.tp_addr) -
  2337. (unsigned long)(hal->shadow_rdptr_mem_vaddr));
  2338. } else {
  2339. return hal->shadow_wrptr_mem_paddr +
  2340. ((unsigned long)(srng->u.dst_ring.tp_addr) -
  2341. (unsigned long)(hal->shadow_wrptr_mem_vaddr));
  2342. }
  2343. }
  2344. /**
  2345. * hal_srng_get_num_entries - Get total entries in the HAL Srng
  2346. *
  2347. * @hal_soc: Opaque HAL SOC handle
  2348. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2349. *
  2350. * Return: total number of entries in hal ring
  2351. */
  2352. static inline
  2353. uint32_t hal_srng_get_num_entries(hal_soc_handle_t hal_soc_hdl,
  2354. hal_ring_handle_t hal_ring_hdl)
  2355. {
  2356. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2357. return srng->num_entries;
  2358. }
  2359. /**
  2360. * hal_get_srng_params - Retrieve SRNG parameters for a given ring from HAL
  2361. *
  2362. * @hal_soc: Opaque HAL SOC handle
  2363. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2364. * @ring_params: SRNG parameters will be returned through this structure
  2365. */
  2366. void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl,
  2367. hal_ring_handle_t hal_ring_hdl,
  2368. struct hal_srng_params *ring_params);
  2369. /**
  2370. * hal_mem_info - Retrieve hal memory base address
  2371. *
  2372. * @hal_soc: Opaque HAL SOC handle
  2373. * @mem: pointer to structure to be updated with hal mem info
  2374. */
  2375. void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem);
  2376. /**
  2377. * hal_get_target_type - Return target type
  2378. *
  2379. * @hal_soc: Opaque HAL SOC handle
  2380. */
  2381. uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl);
  2382. /**
  2383. * hal_srng_dst_hw_init - Private function to initialize SRNG
  2384. * destination ring HW
  2385. * @hal_soc: HAL SOC handle
  2386. * @srng: SRNG ring pointer
  2387. * @idle_check: Check if ring is idle
  2388. */
  2389. static inline void hal_srng_dst_hw_init(struct hal_soc *hal,
  2390. struct hal_srng *srng, bool idle_check)
  2391. {
  2392. hal->ops->hal_srng_dst_hw_init(hal, srng, idle_check);
  2393. }
  2394. /**
  2395. * hal_srng_src_hw_init - Private function to initialize SRNG
  2396. * source ring HW
  2397. * @hal_soc: HAL SOC handle
  2398. * @srng: SRNG ring pointer
  2399. * @idle_check: Check if ring is idle
  2400. */
  2401. static inline void hal_srng_src_hw_init(struct hal_soc *hal,
  2402. struct hal_srng *srng, bool idle_check)
  2403. {
  2404. hal->ops->hal_srng_src_hw_init(hal, srng, idle_check);
  2405. }
  2406. /**
  2407. * hal_srng_hw_disable - Private function to disable SRNG
  2408. * source ring HW
  2409. * @hal_soc: HAL SOC handle
  2410. * @srng: SRNG ring pointer
  2411. */
  2412. static inline
  2413. void hal_srng_hw_disable(struct hal_soc *hal_soc, struct hal_srng *srng)
  2414. {
  2415. if (hal_soc->ops->hal_srng_hw_disable)
  2416. hal_soc->ops->hal_srng_hw_disable(hal_soc, srng);
  2417. }
  2418. /**
  2419. * hal_get_hw_hptp() - Get HW head and tail pointer value for any ring
  2420. * @hal_soc: Opaque HAL SOC handle
  2421. * @hal_ring_hdl: Source ring pointer
  2422. * @headp: Head Pointer
  2423. * @tailp: Tail Pointer
  2424. * @ring_type: Ring
  2425. *
  2426. * Return: Update tail pointer and head pointer in arguments.
  2427. */
  2428. static inline
  2429. void hal_get_hw_hptp(hal_soc_handle_t hal_soc_hdl,
  2430. hal_ring_handle_t hal_ring_hdl,
  2431. uint32_t *headp, uint32_t *tailp,
  2432. uint8_t ring_type)
  2433. {
  2434. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2435. hal_soc->ops->hal_get_hw_hptp(hal_soc, hal_ring_hdl,
  2436. headp, tailp, ring_type);
  2437. }
  2438. /**
  2439. * hal_reo_setup - Initialize HW REO block
  2440. *
  2441. * @hal_soc: Opaque HAL SOC handle
  2442. * @reo_params: parameters needed by HAL for REO config
  2443. * @qref_reset: reset qref
  2444. */
  2445. static inline void hal_reo_setup(hal_soc_handle_t hal_soc_hdl,
  2446. void *reoparams, int qref_reset)
  2447. {
  2448. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2449. hal_soc->ops->hal_reo_setup(hal_soc, reoparams, qref_reset);
  2450. }
  2451. static inline
  2452. void hal_compute_reo_remap_ix2_ix3(hal_soc_handle_t hal_soc_hdl,
  2453. uint32_t *ring, uint32_t num_rings,
  2454. uint32_t *remap1, uint32_t *remap2)
  2455. {
  2456. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2457. return hal_soc->ops->hal_compute_reo_remap_ix2_ix3(ring,
  2458. num_rings, remap1, remap2);
  2459. }
  2460. static inline
  2461. void hal_compute_reo_remap_ix0(hal_soc_handle_t hal_soc_hdl, uint32_t *remap0)
  2462. {
  2463. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2464. if (hal_soc->ops->hal_compute_reo_remap_ix0)
  2465. hal_soc->ops->hal_compute_reo_remap_ix0(remap0);
  2466. }
  2467. /**
  2468. * hal_setup_link_idle_list - Setup scattered idle list using the
  2469. * buffer list provided
  2470. *
  2471. * @hal_soc: Opaque HAL SOC handle
  2472. * @scatter_bufs_base_paddr: Array of physical base addresses
  2473. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  2474. * @num_scatter_bufs: Number of scatter buffers in the above lists
  2475. * @scatter_buf_size: Size of each scatter buffer
  2476. * @last_buf_end_offset: Offset to the last entry
  2477. * @num_entries: Total entries of all scatter bufs
  2478. *
  2479. */
  2480. static inline
  2481. void hal_setup_link_idle_list(hal_soc_handle_t hal_soc_hdl,
  2482. qdf_dma_addr_t scatter_bufs_base_paddr[],
  2483. void *scatter_bufs_base_vaddr[],
  2484. uint32_t num_scatter_bufs,
  2485. uint32_t scatter_buf_size,
  2486. uint32_t last_buf_end_offset,
  2487. uint32_t num_entries)
  2488. {
  2489. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2490. hal_soc->ops->hal_setup_link_idle_list(hal_soc, scatter_bufs_base_paddr,
  2491. scatter_bufs_base_vaddr, num_scatter_bufs,
  2492. scatter_buf_size, last_buf_end_offset,
  2493. num_entries);
  2494. }
  2495. #ifdef DUMP_REO_QUEUE_INFO_IN_DDR
  2496. /**
  2497. * hal_dump_rx_reo_queue_desc() - Dump reo queue descriptor fields
  2498. * @hw_qdesc_vaddr_aligned: Pointer to hw reo queue desc virtual addr
  2499. *
  2500. * Use the virtual addr pointer to reo h/w queue desc to read
  2501. * the values from ddr and log them.
  2502. *
  2503. * Return: none
  2504. */
  2505. static inline void hal_dump_rx_reo_queue_desc(
  2506. void *hw_qdesc_vaddr_aligned)
  2507. {
  2508. struct rx_reo_queue *hw_qdesc =
  2509. (struct rx_reo_queue *)hw_qdesc_vaddr_aligned;
  2510. if (!hw_qdesc)
  2511. return;
  2512. hal_info("receive_queue_number %u vld %u window_jump_2k %u"
  2513. " hole_count %u ba_window_size %u ignore_ampdu_flag %u"
  2514. " svld %u ssn %u current_index %u"
  2515. " disable_duplicate_detection %u soft_reorder_enable %u"
  2516. " chk_2k_mode %u oor_mode %u mpdu_frames_processed_count %u"
  2517. " msdu_frames_processed_count %u total_processed_byte_count %u"
  2518. " late_receive_mpdu_count %u seq_2k_error_detected_flag %u"
  2519. " pn_error_detected_flag %u current_mpdu_count %u"
  2520. " current_msdu_count %u timeout_count %u"
  2521. " forward_due_to_bar_count %u duplicate_count %u"
  2522. " frames_in_order_count %u bar_received_count %u"
  2523. " pn_check_needed %u pn_shall_be_even %u"
  2524. " pn_shall_be_uneven %u pn_size %u",
  2525. hw_qdesc->receive_queue_number,
  2526. hw_qdesc->vld,
  2527. hw_qdesc->window_jump_2k,
  2528. hw_qdesc->hole_count,
  2529. hw_qdesc->ba_window_size,
  2530. hw_qdesc->ignore_ampdu_flag,
  2531. hw_qdesc->svld,
  2532. hw_qdesc->ssn,
  2533. hw_qdesc->current_index,
  2534. hw_qdesc->disable_duplicate_detection,
  2535. hw_qdesc->soft_reorder_enable,
  2536. hw_qdesc->chk_2k_mode,
  2537. hw_qdesc->oor_mode,
  2538. hw_qdesc->mpdu_frames_processed_count,
  2539. hw_qdesc->msdu_frames_processed_count,
  2540. hw_qdesc->total_processed_byte_count,
  2541. hw_qdesc->late_receive_mpdu_count,
  2542. hw_qdesc->seq_2k_error_detected_flag,
  2543. hw_qdesc->pn_error_detected_flag,
  2544. hw_qdesc->current_mpdu_count,
  2545. hw_qdesc->current_msdu_count,
  2546. hw_qdesc->timeout_count,
  2547. hw_qdesc->forward_due_to_bar_count,
  2548. hw_qdesc->duplicate_count,
  2549. hw_qdesc->frames_in_order_count,
  2550. hw_qdesc->bar_received_count,
  2551. hw_qdesc->pn_check_needed,
  2552. hw_qdesc->pn_shall_be_even,
  2553. hw_qdesc->pn_shall_be_uneven,
  2554. hw_qdesc->pn_size);
  2555. }
  2556. #else /* DUMP_REO_QUEUE_INFO_IN_DDR */
  2557. static inline void hal_dump_rx_reo_queue_desc(
  2558. void *hw_qdesc_vaddr_aligned)
  2559. {
  2560. }
  2561. #endif /* DUMP_REO_QUEUE_INFO_IN_DDR */
  2562. /**
  2563. * hal_srng_dump_ring_desc() - Dump ring descriptor info
  2564. *
  2565. * @hal_soc: Opaque HAL SOC handle
  2566. * @hal_ring_hdl: Source ring pointer
  2567. * @ring_desc: Opaque ring descriptor handle
  2568. */
  2569. static inline void hal_srng_dump_ring_desc(hal_soc_handle_t hal_soc_hdl,
  2570. hal_ring_handle_t hal_ring_hdl,
  2571. hal_ring_desc_t ring_desc)
  2572. {
  2573. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2574. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2575. ring_desc, (srng->entry_size << 2));
  2576. }
  2577. /**
  2578. * hal_srng_dump_ring() - Dump last 128 descs of the ring
  2579. *
  2580. * @hal_soc: Opaque HAL SOC handle
  2581. * @hal_ring_hdl: Source ring pointer
  2582. */
  2583. static inline void hal_srng_dump_ring(hal_soc_handle_t hal_soc_hdl,
  2584. hal_ring_handle_t hal_ring_hdl)
  2585. {
  2586. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2587. uint32_t *desc;
  2588. uint32_t tp, i;
  2589. tp = srng->u.dst_ring.tp;
  2590. for (i = 0; i < 128; i++) {
  2591. if (!tp)
  2592. tp = srng->ring_size;
  2593. desc = &srng->ring_base_vaddr[tp - srng->entry_size];
  2594. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP,
  2595. QDF_TRACE_LEVEL_DEBUG,
  2596. desc, (srng->entry_size << 2));
  2597. tp -= srng->entry_size;
  2598. }
  2599. }
  2600. /*
  2601. * hal_rxdma_desc_to_hal_ring_desc - API to convert rxdma ring desc
  2602. * to opaque dp_ring desc type
  2603. * @ring_desc - rxdma ring desc
  2604. *
  2605. * Return: hal_rxdma_desc_t type
  2606. */
  2607. static inline
  2608. hal_ring_desc_t hal_rxdma_desc_to_hal_ring_desc(hal_rxdma_desc_t ring_desc)
  2609. {
  2610. return (hal_ring_desc_t)ring_desc;
  2611. }
  2612. /**
  2613. * hal_srng_set_event() - Set hal_srng event
  2614. * @hal_ring_hdl: Source ring pointer
  2615. * @event: SRNG ring event
  2616. *
  2617. * Return: None
  2618. */
  2619. static inline void hal_srng_set_event(hal_ring_handle_t hal_ring_hdl, int event)
  2620. {
  2621. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2622. qdf_atomic_set_bit(event, &srng->srng_event);
  2623. }
  2624. /**
  2625. * hal_srng_clear_event() - Clear hal_srng event
  2626. * @hal_ring_hdl: Source ring pointer
  2627. * @event: SRNG ring event
  2628. *
  2629. * Return: None
  2630. */
  2631. static inline
  2632. void hal_srng_clear_event(hal_ring_handle_t hal_ring_hdl, int event)
  2633. {
  2634. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2635. qdf_atomic_clear_bit(event, &srng->srng_event);
  2636. }
  2637. /**
  2638. * hal_srng_get_clear_event() - Clear srng event and return old value
  2639. * @hal_ring_hdl: Source ring pointer
  2640. * @event: SRNG ring event
  2641. *
  2642. * Return: Return old event value
  2643. */
  2644. static inline
  2645. int hal_srng_get_clear_event(hal_ring_handle_t hal_ring_hdl, int event)
  2646. {
  2647. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2648. return qdf_atomic_test_and_clear_bit(event, &srng->srng_event);
  2649. }
  2650. /**
  2651. * hal_srng_set_flush_last_ts() - Record last flush time stamp
  2652. * @hal_ring_hdl: Source ring pointer
  2653. *
  2654. * Return: None
  2655. */
  2656. static inline void hal_srng_set_flush_last_ts(hal_ring_handle_t hal_ring_hdl)
  2657. {
  2658. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2659. srng->last_flush_ts = qdf_get_log_timestamp();
  2660. }
  2661. /**
  2662. * hal_srng_inc_flush_cnt() - Increment flush counter
  2663. * @hal_ring_hdl: Source ring pointer
  2664. *
  2665. * Return: None
  2666. */
  2667. static inline void hal_srng_inc_flush_cnt(hal_ring_handle_t hal_ring_hdl)
  2668. {
  2669. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2670. srng->flush_count++;
  2671. }
  2672. /**
  2673. * hal_rx_sw_mon_desc_info_get () - Get SW monitor desc info
  2674. *
  2675. * @hal: Core HAL soc handle
  2676. * @ring_desc: Mon dest ring descriptor
  2677. * @desc_info: Desc info to be populated
  2678. *
  2679. * Return void
  2680. */
  2681. static inline void
  2682. hal_rx_sw_mon_desc_info_get(struct hal_soc *hal,
  2683. hal_ring_desc_t ring_desc,
  2684. hal_rx_mon_desc_info_t desc_info)
  2685. {
  2686. return hal->ops->hal_rx_sw_mon_desc_info_get(ring_desc, desc_info);
  2687. }
  2688. /**
  2689. * hal_reo_set_err_dst_remap() - Set REO error destination ring remap
  2690. * register value.
  2691. *
  2692. * @hal_soc_hdl: Opaque HAL soc handle
  2693. *
  2694. * Return: None
  2695. */
  2696. static inline void hal_reo_set_err_dst_remap(hal_soc_handle_t hal_soc_hdl)
  2697. {
  2698. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2699. if (hal_soc->ops->hal_reo_set_err_dst_remap)
  2700. hal_soc->ops->hal_reo_set_err_dst_remap(hal_soc);
  2701. }
  2702. /**
  2703. * hal_reo_enable_pn_in_dest() - Subscribe for previous PN for 2k-jump or
  2704. * OOR error frames
  2705. * @hal_soc_hdl: Opaque HAL soc handle
  2706. *
  2707. * Return: true if feature is enabled,
  2708. * false, otherwise.
  2709. */
  2710. static inline uint8_t
  2711. hal_reo_enable_pn_in_dest(hal_soc_handle_t hal_soc_hdl)
  2712. {
  2713. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2714. if (hal_soc->ops->hal_reo_enable_pn_in_dest)
  2715. return hal_soc->ops->hal_reo_enable_pn_in_dest(hal_soc);
  2716. return 0;
  2717. }
  2718. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  2719. /**
  2720. * hal_set_one_target_reg_config() - Populate the target reg
  2721. * offset in hal_soc for one non srng related register at the
  2722. * given list index
  2723. * @hal_soc: hal handle
  2724. * @target_reg_offset: target register offset
  2725. * @list_index: index in hal list for shadow regs
  2726. *
  2727. * Return: none
  2728. */
  2729. void hal_set_one_target_reg_config(struct hal_soc *hal,
  2730. uint32_t target_reg_offset,
  2731. int list_index);
  2732. /**
  2733. * hal_set_shadow_regs() - Populate register offset for
  2734. * registers that need to be populated in list_shadow_reg_config
  2735. * in order to be sent to FW. These reg offsets will be mapped
  2736. * to shadow registers.
  2737. * @hal_soc: hal handle
  2738. *
  2739. * Return: QDF_STATUS_OK on success
  2740. */
  2741. QDF_STATUS hal_set_shadow_regs(void *hal_soc);
  2742. /**
  2743. * hal_construct_shadow_regs() - initialize the shadow registers
  2744. * for non-srng related register configs
  2745. * @hal_soc: hal handle
  2746. *
  2747. * Return: QDF_STATUS_OK on success
  2748. */
  2749. QDF_STATUS hal_construct_shadow_regs(void *hal_soc);
  2750. #else /* GENERIC_SHADOW_REGISTER_ACCESS_ENABLE */
  2751. static inline void hal_set_one_target_reg_config(
  2752. struct hal_soc *hal,
  2753. uint32_t target_reg_offset,
  2754. int list_index)
  2755. {
  2756. }
  2757. static inline QDF_STATUS hal_set_shadow_regs(void *hal_soc)
  2758. {
  2759. return QDF_STATUS_SUCCESS;
  2760. }
  2761. static inline QDF_STATUS hal_construct_shadow_regs(void *hal_soc)
  2762. {
  2763. return QDF_STATUS_SUCCESS;
  2764. }
  2765. #endif /* GENERIC_SHADOW_REGISTER_ACCESS_ENABLE */
  2766. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  2767. /**
  2768. * hal_flush_reg_write_work() - flush all writes from register write queue
  2769. * @arg: hal_soc pointer
  2770. *
  2771. * Return: None
  2772. */
  2773. void hal_flush_reg_write_work(hal_soc_handle_t hal_handle);
  2774. #else
  2775. static inline void hal_flush_reg_write_work(hal_soc_handle_t hal_handle) { }
  2776. #endif
  2777. /**
  2778. * hal_get_ring_usage - Calculate the ring usage percentage
  2779. * @hal_ring_hdl: Ring pointer
  2780. * @ring_type: Ring type
  2781. * @headp: pointer to head value
  2782. * @tailp: pointer to tail value
  2783. *
  2784. * Calculate the ring usage percentage for src and dest rings
  2785. *
  2786. * Return: Ring usage percentage
  2787. */
  2788. static inline
  2789. uint32_t hal_get_ring_usage(
  2790. hal_ring_handle_t hal_ring_hdl,
  2791. enum hal_ring_type ring_type, uint32_t *headp, uint32_t *tailp)
  2792. {
  2793. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2794. uint32_t num_avail, num_valid = 0;
  2795. uint32_t ring_usage;
  2796. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  2797. if (*tailp > *headp)
  2798. num_avail = ((*tailp - *headp) / srng->entry_size) - 1;
  2799. else
  2800. num_avail = ((srng->ring_size - *headp + *tailp) /
  2801. srng->entry_size) - 1;
  2802. if (ring_type == WBM_IDLE_LINK)
  2803. num_valid = num_avail;
  2804. else
  2805. num_valid = srng->num_entries - num_avail;
  2806. } else {
  2807. if (*headp >= *tailp)
  2808. num_valid = ((*headp - *tailp) / srng->entry_size);
  2809. else
  2810. num_valid = ((srng->ring_size - *tailp + *headp) /
  2811. srng->entry_size);
  2812. }
  2813. ring_usage = (100 * num_valid) / srng->num_entries;
  2814. return ring_usage;
  2815. }
  2816. /**
  2817. * hal_cmem_write() - function for CMEM buffer writing
  2818. * @hal_soc_hdl: HAL SOC handle
  2819. * @offset: CMEM address
  2820. * @value: value to write
  2821. *
  2822. * Return: None.
  2823. */
  2824. static inline void
  2825. hal_cmem_write(hal_soc_handle_t hal_soc_hdl, uint32_t offset,
  2826. uint32_t value)
  2827. {
  2828. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2829. if (hal_soc->ops->hal_cmem_write)
  2830. hal_soc->ops->hal_cmem_write(hal_soc_hdl, offset, value);
  2831. return;
  2832. }
  2833. static inline bool
  2834. hal_dmac_cmn_src_rxbuf_ring_get(hal_soc_handle_t hal_soc_hdl)
  2835. {
  2836. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2837. return hal_soc->dmac_cmn_src_rxbuf_ring;
  2838. }
  2839. /**
  2840. * hal_srng_dst_prefetch() - function to prefetch 4 destination ring descs
  2841. * @hal_soc_hdl: HAL SOC handle
  2842. * @hal_ring_hdl: Destination ring pointer
  2843. * @num_valid: valid entries in the ring
  2844. *
  2845. * return: last prefetched destination ring descriptor
  2846. */
  2847. static inline
  2848. void *hal_srng_dst_prefetch(hal_soc_handle_t hal_soc_hdl,
  2849. hal_ring_handle_t hal_ring_hdl,
  2850. uint16_t num_valid)
  2851. {
  2852. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2853. uint8_t *desc;
  2854. uint32_t cnt;
  2855. /*
  2856. * prefetching 4 HW descriptors will ensure atleast by the time
  2857. * 5th HW descriptor is being processed it is guaranteed that the
  2858. * 5th HW descriptor, its SW Desc, its nbuf and its nbuf's data
  2859. * are in cache line. basically ensuring all the 4 (HW, SW, nbuf
  2860. * & nbuf->data) are prefetched.
  2861. */
  2862. uint32_t max_prefetch = 4;
  2863. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  2864. return NULL;
  2865. desc = (uint8_t *)&srng->ring_base_vaddr[srng->u.dst_ring.tp];
  2866. if (num_valid < max_prefetch)
  2867. max_prefetch = num_valid;
  2868. for (cnt = 0; cnt < max_prefetch; cnt++) {
  2869. desc += srng->entry_size * sizeof(uint32_t);
  2870. if (desc == ((uint8_t *)srng->ring_vaddr_end))
  2871. desc = (uint8_t *)&srng->ring_base_vaddr[0];
  2872. qdf_prefetch(desc);
  2873. }
  2874. return (void *)desc;
  2875. }
  2876. /**
  2877. * hal_srng_dst_prefetch_next_cached_desc() - function to prefetch next desc
  2878. * @hal_soc_hdl: HAL SOC handle
  2879. * @hal_ring_hdl: Destination ring pointer
  2880. * @last_prefetched_hw_desc: last prefetched HW descriptor
  2881. *
  2882. * return: next prefetched destination descriptor
  2883. */
  2884. static inline
  2885. void *hal_srng_dst_prefetch_next_cached_desc(hal_soc_handle_t hal_soc_hdl,
  2886. hal_ring_handle_t hal_ring_hdl,
  2887. uint8_t *last_prefetched_hw_desc)
  2888. {
  2889. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2890. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  2891. return NULL;
  2892. last_prefetched_hw_desc += srng->entry_size * sizeof(uint32_t);
  2893. if (last_prefetched_hw_desc == ((uint8_t *)srng->ring_vaddr_end))
  2894. last_prefetched_hw_desc = (uint8_t *)&srng->ring_base_vaddr[0];
  2895. qdf_prefetch(last_prefetched_hw_desc);
  2896. return (void *)last_prefetched_hw_desc;
  2897. }
  2898. /**
  2899. * hal_srng_dst_prefetch_32_byte_desc() - function to prefetch a desc at
  2900. * 64 byte offset
  2901. * @hal_soc_hdl: HAL SOC handle
  2902. * @hal_ring_hdl: Destination ring pointer
  2903. * @num_valid: valid entries in the ring
  2904. *
  2905. * return: last prefetched destination ring descriptor
  2906. */
  2907. static inline
  2908. void *hal_srng_dst_prefetch_32_byte_desc(hal_soc_handle_t hal_soc_hdl,
  2909. hal_ring_handle_t hal_ring_hdl,
  2910. uint16_t num_valid)
  2911. {
  2912. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2913. uint8_t *desc;
  2914. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  2915. return NULL;
  2916. desc = (uint8_t *)&srng->ring_base_vaddr[srng->u.dst_ring.tp];
  2917. if ((uintptr_t)desc & 0x3f)
  2918. desc += srng->entry_size * sizeof(uint32_t);
  2919. else
  2920. desc += (srng->entry_size * sizeof(uint32_t)) * 2;
  2921. if (desc == ((uint8_t *)srng->ring_vaddr_end))
  2922. desc = (uint8_t *)&srng->ring_base_vaddr[0];
  2923. qdf_prefetch(desc);
  2924. return (void *)(desc + srng->entry_size * sizeof(uint32_t));
  2925. }
  2926. /**
  2927. * hal_srng_dst_prefetch_next_cached_desc() - function to prefetch next desc
  2928. * @hal_soc_hdl: HAL SOC handle
  2929. * @hal_ring_hdl: Destination ring pointer
  2930. * @last_prefetched_hw_desc: last prefetched HW descriptor
  2931. *
  2932. * return: next prefetched destination descriptor
  2933. */
  2934. static inline
  2935. void *hal_srng_dst_get_next_32_byte_desc(hal_soc_handle_t hal_soc_hdl,
  2936. hal_ring_handle_t hal_ring_hdl,
  2937. uint8_t *last_prefetched_hw_desc)
  2938. {
  2939. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2940. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  2941. return NULL;
  2942. last_prefetched_hw_desc += srng->entry_size * sizeof(uint32_t);
  2943. if (last_prefetched_hw_desc == ((uint8_t *)srng->ring_vaddr_end))
  2944. last_prefetched_hw_desc = (uint8_t *)&srng->ring_base_vaddr[0];
  2945. return (void *)last_prefetched_hw_desc;
  2946. }
  2947. #endif /* _HAL_APIH_ */