qcedev.c 72 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * QTI CE device driver.
  4. *
  5. * Copyright (c) 2010-2021, The Linux Foundation. All rights reserved.
  6. */
  7. #include <linux/mman.h>
  8. #include <linux/module.h>
  9. #include <linux/device.h>
  10. #include <linux/types.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/kernel.h>
  14. #include <linux/dmapool.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/init.h>
  18. #include <linux/module.h>
  19. #include <linux/fs.h>
  20. #include <linux/uaccess.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/scatterlist.h>
  23. #include <linux/crypto.h>
  24. #include "linux/platform_data/qcom_crypto_device.h"
  25. #include "linux/qcedev.h"
  26. #include <linux/interconnect.h>
  27. #include <linux/delay.h>
  28. #include <crypto/hash.h>
  29. #include "qcedevi.h"
  30. #include "qce.h"
  31. #include "qcedev_smmu.h"
  32. #include "compat_qcedev.h"
  33. #include <linux/compat.h>
  34. #define CACHE_LINE_SIZE 64
  35. #define CE_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE
  36. #define MAX_CEHW_REQ_TRANSFER_SIZE (128*32*1024)
  37. /*
  38. * Max wait time once a crypto request is done.
  39. * Assuming 5ms per crypto operation, this is calculated for
  40. * the scenario of having 3 offload reqs + 1 tz req + buffer.
  41. */
  42. #define MAX_CRYPTO_WAIT_TIME 25
  43. #define MAX_REQUEST_TIME 5000
  44. enum qcedev_req_status {
  45. QCEDEV_REQ_CURRENT = 0,
  46. QCEDEV_REQ_WAITING = 1,
  47. QCEDEV_REQ_SUBMITTED = 2,
  48. QCEDEV_REQ_DONE = 3,
  49. };
  50. static uint8_t _std_init_vector_sha1_uint8[] = {
  51. 0x67, 0x45, 0x23, 0x01, 0xEF, 0xCD, 0xAB, 0x89,
  52. 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76,
  53. 0xC3, 0xD2, 0xE1, 0xF0
  54. };
  55. /* standard initialization vector for SHA-256, source: FIPS 180-2 */
  56. static uint8_t _std_init_vector_sha256_uint8[] = {
  57. 0x6A, 0x09, 0xE6, 0x67, 0xBB, 0x67, 0xAE, 0x85,
  58. 0x3C, 0x6E, 0xF3, 0x72, 0xA5, 0x4F, 0xF5, 0x3A,
  59. 0x51, 0x0E, 0x52, 0x7F, 0x9B, 0x05, 0x68, 0x8C,
  60. 0x1F, 0x83, 0xD9, 0xAB, 0x5B, 0xE0, 0xCD, 0x19
  61. };
  62. #define QCEDEV_CTX_KEY_MASK 0x000000ff
  63. #define QCEDEV_CTX_USE_HW_KEY 0x00000001
  64. #define QCEDEV_CTX_USE_PIPE_KEY 0x00000002
  65. static DEFINE_MUTEX(send_cmd_lock);
  66. static DEFINE_MUTEX(qcedev_sent_bw_req);
  67. static DEFINE_MUTEX(hash_access_lock);
  68. static dev_t qcedev_device_no;
  69. static struct class *driver_class;
  70. static struct device *class_dev;
  71. static const struct of_device_id qcedev_match[] = {
  72. { .compatible = "qcom,qcedev"},
  73. { .compatible = "qcom,qcedev,context-bank"},
  74. {}
  75. };
  76. MODULE_DEVICE_TABLE(of, qcedev_match);
  77. static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
  78. {
  79. unsigned int control_flag;
  80. int ret = 0;
  81. if (podev->ce_support.req_bw_before_clk) {
  82. if (enable)
  83. control_flag = QCE_BW_REQUEST_FIRST;
  84. else
  85. control_flag = QCE_CLK_DISABLE_FIRST;
  86. } else {
  87. if (enable)
  88. control_flag = QCE_CLK_ENABLE_FIRST;
  89. else
  90. control_flag = QCE_BW_REQUEST_RESET_FIRST;
  91. }
  92. switch (control_flag) {
  93. case QCE_CLK_ENABLE_FIRST:
  94. ret = qce_enable_clk(podev->qce);
  95. if (ret) {
  96. pr_err("%s Unable enable clk\n", __func__);
  97. return ret;
  98. }
  99. ret = icc_set_bw(podev->icc_path,
  100. podev->icc_avg_bw, podev->icc_peak_bw);
  101. if (ret) {
  102. pr_err("%s Unable to set high bw\n", __func__);
  103. ret = qce_disable_clk(podev->qce);
  104. if (ret)
  105. pr_err("%s Unable disable clk\n", __func__);
  106. return ret;
  107. }
  108. break;
  109. case QCE_BW_REQUEST_FIRST:
  110. ret = icc_set_bw(podev->icc_path,
  111. podev->icc_avg_bw, podev->icc_peak_bw);
  112. if (ret) {
  113. pr_err("%s Unable to set high bw\n", __func__);
  114. return ret;
  115. }
  116. ret = qce_enable_clk(podev->qce);
  117. if (ret) {
  118. pr_err("%s Unable enable clk\n", __func__);
  119. ret = icc_set_bw(podev->icc_path, 0, 0);
  120. if (ret)
  121. pr_err("%s Unable to set low bw\n", __func__);
  122. return ret;
  123. }
  124. break;
  125. case QCE_CLK_DISABLE_FIRST:
  126. ret = qce_disable_clk(podev->qce);
  127. if (ret) {
  128. pr_err("%s Unable to disable clk\n", __func__);
  129. return ret;
  130. }
  131. ret = icc_set_bw(podev->icc_path, 0, 0);
  132. if (ret) {
  133. pr_err("%s Unable to set low bw\n", __func__);
  134. ret = qce_enable_clk(podev->qce);
  135. if (ret)
  136. pr_err("%s Unable enable clk\n", __func__);
  137. return ret;
  138. }
  139. break;
  140. case QCE_BW_REQUEST_RESET_FIRST:
  141. ret = icc_set_bw(podev->icc_path, 0, 0);
  142. if (ret) {
  143. pr_err("%s Unable to set low bw\n", __func__);
  144. return ret;
  145. }
  146. ret = qce_disable_clk(podev->qce);
  147. if (ret) {
  148. pr_err("%s Unable to disable clk\n", __func__);
  149. ret = icc_set_bw(podev->icc_path,
  150. podev->icc_avg_bw, podev->icc_peak_bw);
  151. if (ret)
  152. pr_err("%s Unable to set high bw\n", __func__);
  153. return ret;
  154. }
  155. break;
  156. default:
  157. return -ENOENT;
  158. }
  159. return 0;
  160. }
  161. static void qcedev_ce_high_bw_req(struct qcedev_control *podev,
  162. bool high_bw_req)
  163. {
  164. int ret = 0;
  165. mutex_lock(&qcedev_sent_bw_req);
  166. if (high_bw_req) {
  167. if (podev->high_bw_req_count == 0) {
  168. ret = qcedev_control_clocks(podev, true);
  169. if (ret)
  170. goto exit_unlock_mutex;
  171. }
  172. podev->high_bw_req_count++;
  173. } else {
  174. if (podev->high_bw_req_count == 1) {
  175. ret = qcedev_control_clocks(podev, false);
  176. if (ret)
  177. goto exit_unlock_mutex;
  178. }
  179. podev->high_bw_req_count--;
  180. }
  181. exit_unlock_mutex:
  182. mutex_unlock(&qcedev_sent_bw_req);
  183. }
  184. #define QCEDEV_MAGIC 0x56434544 /* "qced" */
  185. static int qcedev_open(struct inode *inode, struct file *file);
  186. static int qcedev_release(struct inode *inode, struct file *file);
  187. static int start_cipher_req(struct qcedev_control *podev,
  188. int *current_req_info);
  189. static int start_offload_cipher_req(struct qcedev_control *podev,
  190. int *current_req_info);
  191. static int start_sha_req(struct qcedev_control *podev,
  192. int *current_req_info);
  193. static const struct file_operations qcedev_fops = {
  194. .owner = THIS_MODULE,
  195. .unlocked_ioctl = qcedev_ioctl,
  196. #ifdef CONFIG_COMPAT
  197. .compat_ioctl = compat_qcedev_ioctl,
  198. #endif
  199. .open = qcedev_open,
  200. .release = qcedev_release,
  201. };
  202. static struct qcedev_control qce_dev[] = {
  203. {
  204. .magic = QCEDEV_MAGIC,
  205. },
  206. };
  207. #define MAX_QCE_DEVICE ARRAY_SIZE(qce_dev)
  208. #define DEBUG_MAX_FNAME 16
  209. #define DEBUG_MAX_RW_BUF 1024
  210. struct qcedev_stat {
  211. u32 qcedev_dec_success;
  212. u32 qcedev_dec_fail;
  213. u32 qcedev_enc_success;
  214. u32 qcedev_enc_fail;
  215. u32 qcedev_sha_success;
  216. u32 qcedev_sha_fail;
  217. };
  218. static struct qcedev_stat _qcedev_stat;
  219. static struct dentry *_debug_dent;
  220. static char _debug_read_buf[DEBUG_MAX_RW_BUF];
  221. static int _debug_qcedev;
  222. static struct qcedev_control *qcedev_minor_to_control(unsigned int n)
  223. {
  224. int i;
  225. for (i = 0; i < MAX_QCE_DEVICE; i++) {
  226. if (qce_dev[i].minor == n)
  227. return &qce_dev[n];
  228. }
  229. return NULL;
  230. }
  231. static int qcedev_open(struct inode *inode, struct file *file)
  232. {
  233. struct qcedev_handle *handle;
  234. struct qcedev_control *podev;
  235. podev = qcedev_minor_to_control(MINOR(inode->i_rdev));
  236. if (podev == NULL) {
  237. pr_err("%s: no such device %d\n", __func__,
  238. MINOR(inode->i_rdev));
  239. return -ENOENT;
  240. }
  241. handle = kzalloc(sizeof(struct qcedev_handle), GFP_KERNEL);
  242. if (handle == NULL)
  243. return -ENOMEM;
  244. handle->cntl = podev;
  245. file->private_data = handle;
  246. qcedev_ce_high_bw_req(podev, true);
  247. mutex_init(&handle->registeredbufs.lock);
  248. INIT_LIST_HEAD(&handle->registeredbufs.list);
  249. return 0;
  250. }
  251. static int qcedev_release(struct inode *inode, struct file *file)
  252. {
  253. struct qcedev_control *podev;
  254. struct qcedev_handle *handle;
  255. handle = file->private_data;
  256. podev = handle->cntl;
  257. if (podev != NULL && podev->magic != QCEDEV_MAGIC) {
  258. pr_err("%s: invalid handle %pK\n",
  259. __func__, podev);
  260. }
  261. qcedev_ce_high_bw_req(podev, false);
  262. if (qcedev_unmap_all_buffers(handle))
  263. pr_err("%s: failed to unmap all ion buffers\n", __func__);
  264. kfree_sensitive(handle);
  265. file->private_data = NULL;
  266. return 0;
  267. }
  268. static void req_done(unsigned long data)
  269. {
  270. struct qcedev_control *podev = (struct qcedev_control *)data;
  271. struct qcedev_async_req *areq;
  272. unsigned long flags = 0;
  273. struct qcedev_async_req *new_req = NULL;
  274. spin_lock_irqsave(&podev->lock, flags);
  275. areq = podev->active_command;
  276. podev->active_command = NULL;
  277. if (areq && !areq->timed_out) {
  278. complete(&areq->complete);
  279. areq->state = QCEDEV_REQ_DONE;
  280. }
  281. /* Look through queued requests and wake up the corresponding thread */
  282. if (!list_empty(&podev->ready_commands)) {
  283. new_req = container_of(podev->ready_commands.next,
  284. struct qcedev_async_req, list);
  285. list_del(&new_req->list);
  286. new_req->state = QCEDEV_REQ_CURRENT;
  287. wake_up_interruptible(&new_req->wait_q);
  288. }
  289. spin_unlock_irqrestore(&podev->lock, flags);
  290. }
  291. void qcedev_sha_req_cb(void *cookie, unsigned char *digest,
  292. unsigned char *authdata, int ret)
  293. {
  294. struct qcedev_sha_req *areq;
  295. struct qcedev_control *pdev;
  296. struct qcedev_handle *handle;
  297. uint32_t *auth32 = (uint32_t *)authdata;
  298. areq = (struct qcedev_sha_req *) cookie;
  299. if (!areq || !areq->cookie)
  300. return;
  301. handle = (struct qcedev_handle *) areq->cookie;
  302. pdev = handle->cntl;
  303. if (!pdev)
  304. return;
  305. if (digest)
  306. memcpy(&handle->sha_ctxt.digest[0], digest, 32);
  307. if (authdata) {
  308. handle->sha_ctxt.auth_data[0] = auth32[0];
  309. handle->sha_ctxt.auth_data[1] = auth32[1];
  310. }
  311. tasklet_schedule(&pdev->done_tasklet);
  312. };
  313. void qcedev_cipher_req_cb(void *cookie, unsigned char *icv,
  314. unsigned char *iv, int ret)
  315. {
  316. struct qcedev_cipher_req *areq;
  317. struct qcedev_handle *handle;
  318. struct qcedev_control *podev;
  319. struct qcedev_async_req *qcedev_areq;
  320. areq = (struct qcedev_cipher_req *) cookie;
  321. if (!areq || !areq->cookie)
  322. return;
  323. handle = (struct qcedev_handle *) areq->cookie;
  324. podev = handle->cntl;
  325. if (!podev)
  326. return;
  327. qcedev_areq = podev->active_command;
  328. if (iv)
  329. memcpy(&qcedev_areq->cipher_op_req.iv[0], iv,
  330. qcedev_areq->cipher_op_req.ivlen);
  331. tasklet_schedule(&podev->done_tasklet);
  332. };
  333. static int start_cipher_req(struct qcedev_control *podev,
  334. int *current_req_info)
  335. {
  336. struct qcedev_async_req *qcedev_areq;
  337. struct qce_req creq;
  338. int ret = 0;
  339. memset(&creq, 0, sizeof(creq));
  340. /* start the command on the podev->active_command */
  341. qcedev_areq = podev->active_command;
  342. qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
  343. if (qcedev_areq->cipher_op_req.use_pmem == QCEDEV_USE_PMEM) {
  344. pr_err("%s: Use of PMEM is not supported\n", __func__);
  345. goto unsupported;
  346. }
  347. creq.pmem = NULL;
  348. switch (qcedev_areq->cipher_op_req.alg) {
  349. case QCEDEV_ALG_DES:
  350. creq.alg = CIPHER_ALG_DES;
  351. break;
  352. case QCEDEV_ALG_3DES:
  353. creq.alg = CIPHER_ALG_3DES;
  354. break;
  355. case QCEDEV_ALG_AES:
  356. creq.alg = CIPHER_ALG_AES;
  357. break;
  358. default:
  359. return -EINVAL;
  360. }
  361. switch (qcedev_areq->cipher_op_req.mode) {
  362. case QCEDEV_AES_MODE_CBC:
  363. case QCEDEV_DES_MODE_CBC:
  364. creq.mode = QCE_MODE_CBC;
  365. break;
  366. case QCEDEV_AES_MODE_ECB:
  367. case QCEDEV_DES_MODE_ECB:
  368. creq.mode = QCE_MODE_ECB;
  369. break;
  370. case QCEDEV_AES_MODE_CTR:
  371. creq.mode = QCE_MODE_CTR;
  372. break;
  373. case QCEDEV_AES_MODE_XTS:
  374. creq.mode = QCE_MODE_XTS;
  375. break;
  376. default:
  377. return -EINVAL;
  378. }
  379. if ((creq.alg == CIPHER_ALG_AES) &&
  380. (creq.mode == QCE_MODE_CTR)) {
  381. creq.dir = QCE_ENCRYPT;
  382. } else {
  383. if (qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC)
  384. creq.dir = QCE_ENCRYPT;
  385. else
  386. creq.dir = QCE_DECRYPT;
  387. }
  388. creq.iv = &qcedev_areq->cipher_op_req.iv[0];
  389. creq.ivsize = qcedev_areq->cipher_op_req.ivlen;
  390. creq.iv_ctr_size = 0;
  391. creq.enckey = &qcedev_areq->cipher_op_req.enckey[0];
  392. creq.encklen = qcedev_areq->cipher_op_req.encklen;
  393. creq.cryptlen = qcedev_areq->cipher_op_req.data_len;
  394. if (qcedev_areq->cipher_op_req.encklen == 0) {
  395. if ((qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC_NO_KEY)
  396. || (qcedev_areq->cipher_op_req.op ==
  397. QCEDEV_OPER_DEC_NO_KEY))
  398. creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
  399. else {
  400. int i;
  401. for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
  402. if (qcedev_areq->cipher_op_req.enckey[i] != 0)
  403. break;
  404. }
  405. if ((podev->platform_support.hw_key_support == 1) &&
  406. (i == QCEDEV_MAX_KEY_SIZE))
  407. creq.op = QCE_REQ_ABLK_CIPHER;
  408. else {
  409. ret = -EINVAL;
  410. goto unsupported;
  411. }
  412. }
  413. } else {
  414. creq.op = QCE_REQ_ABLK_CIPHER;
  415. }
  416. creq.qce_cb = qcedev_cipher_req_cb;
  417. creq.areq = (void *)&qcedev_areq->cipher_req;
  418. creq.flags = 0;
  419. creq.offload_op = QCE_OFFLOAD_NONE;
  420. ret = qce_ablk_cipher_req(podev->qce, &creq);
  421. *current_req_info = creq.current_req_info;
  422. unsupported:
  423. qcedev_areq->err = ret ? -ENXIO : 0;
  424. return ret;
  425. };
  426. void qcedev_offload_cipher_req_cb(void *cookie, unsigned char *icv,
  427. unsigned char *iv, int ret)
  428. {
  429. struct qcedev_cipher_req *areq;
  430. struct qcedev_handle *handle;
  431. struct qcedev_control *podev;
  432. struct qcedev_async_req *qcedev_areq;
  433. areq = (struct qcedev_cipher_req *) cookie;
  434. if (!areq || !areq->cookie)
  435. return;
  436. handle = (struct qcedev_handle *) areq->cookie;
  437. podev = handle->cntl;
  438. if (!podev)
  439. return;
  440. qcedev_areq = podev->active_command;
  441. if (iv)
  442. memcpy(&qcedev_areq->offload_cipher_op_req.iv[0], iv,
  443. qcedev_areq->offload_cipher_op_req.ivlen);
  444. tasklet_schedule(&podev->done_tasklet);
  445. }
  446. static int start_offload_cipher_req(struct qcedev_control *podev,
  447. int *current_req_info)
  448. {
  449. struct qcedev_async_req *qcedev_areq;
  450. struct qce_req creq;
  451. u8 patt_sz = 0, proc_data_sz = 0;
  452. int ret = 0;
  453. memset(&creq, 0, sizeof(creq));
  454. /* Start the command on the podev->active_command */
  455. qcedev_areq = podev->active_command;
  456. qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
  457. switch (qcedev_areq->offload_cipher_op_req.alg) {
  458. case QCEDEV_ALG_AES:
  459. creq.alg = CIPHER_ALG_AES;
  460. break;
  461. default:
  462. return -EINVAL;
  463. }
  464. switch (qcedev_areq->offload_cipher_op_req.mode) {
  465. case QCEDEV_AES_MODE_CBC:
  466. creq.mode = QCE_MODE_CBC;
  467. break;
  468. case QCEDEV_AES_MODE_CTR:
  469. creq.mode = QCE_MODE_CTR;
  470. break;
  471. default:
  472. return -EINVAL;
  473. }
  474. if (qcedev_areq->offload_cipher_op_req.is_copy_op) {
  475. creq.dir = QCE_ENCRYPT;
  476. } else {
  477. switch(qcedev_areq->offload_cipher_op_req.op) {
  478. case QCEDEV_OFFLOAD_HLOS_HLOS:
  479. case QCEDEV_OFFLOAD_HLOS_CPB:
  480. creq.dir = QCE_DECRYPT;
  481. break;
  482. case QCEDEV_OFFLOAD_CPB_HLOS:
  483. creq.dir = QCE_ENCRYPT;
  484. break;
  485. default:
  486. return -EINVAL;
  487. }
  488. }
  489. creq.iv = &qcedev_areq->offload_cipher_op_req.iv[0];
  490. creq.ivsize = qcedev_areq->offload_cipher_op_req.ivlen;
  491. creq.iv_ctr_size = qcedev_areq->offload_cipher_op_req.iv_ctr_size;
  492. creq.encklen = qcedev_areq->offload_cipher_op_req.encklen;
  493. /* OFFLOAD use cases use PIPE keys so no need to set keys */
  494. creq.flags = QCEDEV_CTX_USE_PIPE_KEY;
  495. creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
  496. creq.offload_op = (int)qcedev_areq->offload_cipher_op_req.op;
  497. if (qcedev_areq->offload_cipher_op_req.is_copy_op)
  498. creq.is_copy_op = true;
  499. creq.cryptlen = qcedev_areq->offload_cipher_op_req.data_len;
  500. creq.qce_cb = qcedev_offload_cipher_req_cb;
  501. creq.areq = (void *)&qcedev_areq->cipher_req;
  502. patt_sz = qcedev_areq->offload_cipher_op_req.pattern_info.patt_sz;
  503. proc_data_sz =
  504. qcedev_areq->offload_cipher_op_req.pattern_info.proc_data_sz;
  505. creq.is_pattern_valid =
  506. qcedev_areq->offload_cipher_op_req.is_pattern_valid;
  507. if (creq.is_pattern_valid) {
  508. creq.pattern_info = 0x1;
  509. if (patt_sz)
  510. creq.pattern_info |= (patt_sz - 1) << 4;
  511. if (proc_data_sz)
  512. creq.pattern_info |= (proc_data_sz - 1) << 8;
  513. creq.pattern_info |=
  514. qcedev_areq->offload_cipher_op_req.pattern_info.patt_offset << 12;
  515. }
  516. creq.block_offset = qcedev_areq->offload_cipher_op_req.block_offset;
  517. ret = qce_ablk_cipher_req(podev->qce, &creq);
  518. *current_req_info = creq.current_req_info;
  519. qcedev_areq->err = ret ? -ENXIO : 0;
  520. return ret;
  521. }
  522. static int start_sha_req(struct qcedev_control *podev,
  523. int *current_req_info)
  524. {
  525. struct qcedev_async_req *qcedev_areq;
  526. struct qce_sha_req sreq;
  527. int ret = 0;
  528. struct qcedev_handle *handle;
  529. /* start the command on the podev->active_command */
  530. qcedev_areq = podev->active_command;
  531. handle = qcedev_areq->handle;
  532. switch (qcedev_areq->sha_op_req.alg) {
  533. case QCEDEV_ALG_SHA1:
  534. sreq.alg = QCE_HASH_SHA1;
  535. break;
  536. case QCEDEV_ALG_SHA256:
  537. sreq.alg = QCE_HASH_SHA256;
  538. break;
  539. case QCEDEV_ALG_SHA1_HMAC:
  540. if (podev->ce_support.sha_hmac) {
  541. sreq.alg = QCE_HASH_SHA1_HMAC;
  542. sreq.authkey = &handle->sha_ctxt.authkey[0];
  543. sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
  544. } else {
  545. sreq.alg = QCE_HASH_SHA1;
  546. sreq.authkey = NULL;
  547. }
  548. break;
  549. case QCEDEV_ALG_SHA256_HMAC:
  550. if (podev->ce_support.sha_hmac) {
  551. sreq.alg = QCE_HASH_SHA256_HMAC;
  552. sreq.authkey = &handle->sha_ctxt.authkey[0];
  553. sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
  554. } else {
  555. sreq.alg = QCE_HASH_SHA256;
  556. sreq.authkey = NULL;
  557. }
  558. break;
  559. case QCEDEV_ALG_AES_CMAC:
  560. sreq.alg = QCE_HASH_AES_CMAC;
  561. sreq.authkey = &handle->sha_ctxt.authkey[0];
  562. sreq.authklen = qcedev_areq->sha_op_req.authklen;
  563. break;
  564. default:
  565. pr_err("Algorithm %d not supported, exiting\n",
  566. qcedev_areq->sha_op_req.alg);
  567. return -EINVAL;
  568. }
  569. qcedev_areq->sha_req.cookie = handle;
  570. sreq.qce_cb = qcedev_sha_req_cb;
  571. if (qcedev_areq->sha_op_req.alg != QCEDEV_ALG_AES_CMAC) {
  572. sreq.auth_data[0] = handle->sha_ctxt.auth_data[0];
  573. sreq.auth_data[1] = handle->sha_ctxt.auth_data[1];
  574. sreq.auth_data[2] = handle->sha_ctxt.auth_data[2];
  575. sreq.auth_data[3] = handle->sha_ctxt.auth_data[3];
  576. sreq.digest = &handle->sha_ctxt.digest[0];
  577. sreq.first_blk = handle->sha_ctxt.first_blk;
  578. sreq.last_blk = handle->sha_ctxt.last_blk;
  579. }
  580. sreq.size = qcedev_areq->sha_req.sreq.nbytes;
  581. sreq.src = qcedev_areq->sha_req.sreq.src;
  582. sreq.areq = (void *)&qcedev_areq->sha_req;
  583. sreq.flags = 0;
  584. ret = qce_process_sha_req(podev->qce, &sreq);
  585. *current_req_info = sreq.current_req_info;
  586. qcedev_areq->err = ret ? -ENXIO : 0;
  587. return ret;
  588. };
  589. static void qcedev_check_crypto_status(
  590. struct qcedev_async_req *qcedev_areq, void *handle)
  591. {
  592. struct qce_error error = {0};
  593. qcedev_areq->offload_cipher_op_req.err = QCEDEV_OFFLOAD_NO_ERROR;
  594. qce_get_crypto_status(handle, &error);
  595. if (error.timer_error) {
  596. qcedev_areq->offload_cipher_op_req.err =
  597. QCEDEV_OFFLOAD_KEY_TIMER_EXPIRED_ERROR;
  598. } else if (error.key_paused) {
  599. qcedev_areq->offload_cipher_op_req.err =
  600. QCEDEV_OFFLOAD_KEY_PAUSE_ERROR;
  601. } else if (error.generic_error) {
  602. qcedev_areq->offload_cipher_op_req.err =
  603. QCEDEV_OFFLOAD_GENERIC_ERROR;
  604. }
  605. return;
  606. }
  607. #define MAX_RETRIES 333
  608. static int submit_req(struct qcedev_async_req *qcedev_areq,
  609. struct qcedev_handle *handle)
  610. {
  611. struct qcedev_control *podev;
  612. unsigned long flags = 0;
  613. int ret = 0;
  614. struct qcedev_stat *pstat;
  615. int current_req_info = 0;
  616. int wait = MAX_CRYPTO_WAIT_TIME;
  617. struct qcedev_async_req *new_req = NULL;
  618. int retries = 0;
  619. qcedev_areq->err = 0;
  620. podev = handle->cntl;
  621. init_waitqueue_head(&qcedev_areq->wait_q);
  622. spin_lock_irqsave(&podev->lock, flags);
  623. /*
  624. * Service only one crypto request at a time.
  625. * Any other new requests are queued in ready_commands and woken up
  626. * only when the active command has finished successfully or when the
  627. * request times out or when the command failed when setting up.
  628. */
  629. do {
  630. if (podev->active_command == NULL) {
  631. podev->active_command = qcedev_areq;
  632. qcedev_areq->state = QCEDEV_REQ_SUBMITTED;
  633. switch (qcedev_areq->op_type) {
  634. case QCEDEV_CRYPTO_OPER_CIPHER:
  635. ret = start_cipher_req(podev,
  636. &current_req_info);
  637. break;
  638. case QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER:
  639. ret = start_offload_cipher_req(podev,
  640. &current_req_info);
  641. break;
  642. default:
  643. ret = start_sha_req(podev,
  644. &current_req_info);
  645. break;
  646. }
  647. } else {
  648. list_add_tail(&qcedev_areq->list,
  649. &podev->ready_commands);
  650. qcedev_areq->state = QCEDEV_REQ_WAITING;
  651. if (wait_event_interruptible_lock_irq_timeout(
  652. qcedev_areq->wait_q,
  653. (qcedev_areq->state == QCEDEV_REQ_CURRENT),
  654. podev->lock,
  655. msecs_to_jiffies(MAX_REQUEST_TIME)) == 0) {
  656. pr_err("%s: request timed out\n", __func__);
  657. spin_unlock_irqrestore(&podev->lock, flags);
  658. return qcedev_areq->err;
  659. }
  660. }
  661. } while (qcedev_areq->state != QCEDEV_REQ_SUBMITTED);
  662. if (ret != 0) {
  663. podev->active_command = NULL;
  664. /*
  665. * Look through queued requests and wake up the corresponding
  666. * thread.
  667. */
  668. if (!list_empty(&podev->ready_commands)) {
  669. new_req = container_of(podev->ready_commands.next,
  670. struct qcedev_async_req, list);
  671. list_del(&new_req->list);
  672. new_req->state = QCEDEV_REQ_CURRENT;
  673. wake_up_interruptible(&new_req->wait_q);
  674. }
  675. }
  676. spin_unlock_irqrestore(&podev->lock, flags);
  677. qcedev_areq->timed_out = false;
  678. if (ret == 0)
  679. wait = wait_for_completion_timeout(&qcedev_areq->complete,
  680. msecs_to_jiffies(MAX_CRYPTO_WAIT_TIME));
  681. if (!wait) {
  682. /*
  683. * This means wait timed out, and the callback routine was not
  684. * exercised. The callback sequence does some housekeeping which
  685. * would be missed here, hence having a call to qce here to do
  686. * that.
  687. */
  688. pr_err("%s: wait timed out, req info = %d\n", __func__,
  689. current_req_info);
  690. qcedev_check_crypto_status(qcedev_areq, podev->qce);
  691. if (qcedev_areq->offload_cipher_op_req.err ==
  692. QCEDEV_OFFLOAD_NO_ERROR) {
  693. pr_err("%s: no error, wait for request to be done", __func__);
  694. while (qcedev_areq->state != QCEDEV_REQ_DONE &&
  695. retries < MAX_RETRIES) {
  696. usleep_range(3000, 5000);
  697. retries++;
  698. pr_err("%s: waiting for req state to be done, retries = %d",
  699. __func__, retries);
  700. }
  701. return 0;
  702. }
  703. spin_lock_irqsave(&podev->lock, flags);
  704. qcedev_areq->timed_out = true;
  705. ret = qce_manage_timeout(podev->qce, current_req_info);
  706. if (ret)
  707. pr_err("%s: error during manage timeout", __func__);
  708. spin_unlock_irqrestore(&podev->lock, flags);
  709. tasklet_schedule(&podev->done_tasklet);
  710. if (qcedev_areq->offload_cipher_op_req.err !=
  711. QCEDEV_OFFLOAD_NO_ERROR)
  712. return 0;
  713. }
  714. if (ret)
  715. qcedev_areq->err = -EIO;
  716. pstat = &_qcedev_stat;
  717. if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER) {
  718. switch (qcedev_areq->cipher_op_req.op) {
  719. case QCEDEV_OPER_DEC:
  720. if (qcedev_areq->err)
  721. pstat->qcedev_dec_fail++;
  722. else
  723. pstat->qcedev_dec_success++;
  724. break;
  725. case QCEDEV_OPER_ENC:
  726. if (qcedev_areq->err)
  727. pstat->qcedev_enc_fail++;
  728. else
  729. pstat->qcedev_enc_success++;
  730. break;
  731. default:
  732. break;
  733. }
  734. } else if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER) {
  735. //Do nothing
  736. } else {
  737. if (qcedev_areq->err)
  738. pstat->qcedev_sha_fail++;
  739. else
  740. pstat->qcedev_sha_success++;
  741. }
  742. return qcedev_areq->err;
  743. }
  744. static int qcedev_sha_init(struct qcedev_async_req *areq,
  745. struct qcedev_handle *handle)
  746. {
  747. struct qcedev_sha_ctxt *sha_ctxt = &handle->sha_ctxt;
  748. memset(sha_ctxt, 0, sizeof(struct qcedev_sha_ctxt));
  749. sha_ctxt->first_blk = 1;
  750. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  751. (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)) {
  752. memcpy(&sha_ctxt->digest[0],
  753. &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
  754. sha_ctxt->diglen = SHA1_DIGEST_SIZE;
  755. } else {
  756. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA256) ||
  757. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)) {
  758. memcpy(&sha_ctxt->digest[0],
  759. &_std_init_vector_sha256_uint8[0],
  760. SHA256_DIGEST_SIZE);
  761. sha_ctxt->diglen = SHA256_DIGEST_SIZE;
  762. }
  763. }
  764. sha_ctxt->init_done = true;
  765. return 0;
  766. }
  767. static int qcedev_sha_update_max_xfer(struct qcedev_async_req *qcedev_areq,
  768. struct qcedev_handle *handle,
  769. struct scatterlist *sg_src)
  770. {
  771. int err = 0;
  772. int i = 0;
  773. uint32_t total;
  774. uint8_t *user_src = NULL;
  775. uint8_t *k_src = NULL;
  776. uint8_t *k_buf_src = NULL;
  777. uint32_t buf_size = 0;
  778. uint8_t *k_align_src = NULL;
  779. uint32_t sha_pad_len = 0;
  780. uint32_t trailing_buf_len = 0;
  781. uint32_t t_buf = handle->sha_ctxt.trailing_buf_len;
  782. uint32_t sha_block_size;
  783. total = qcedev_areq->sha_op_req.data_len + t_buf;
  784. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1)
  785. sha_block_size = SHA1_BLOCK_SIZE;
  786. else
  787. sha_block_size = SHA256_BLOCK_SIZE;
  788. if (total <= sha_block_size) {
  789. uint32_t len = qcedev_areq->sha_op_req.data_len;
  790. i = 0;
  791. k_src = &handle->sha_ctxt.trailing_buf[t_buf];
  792. /* Copy data from user src(s) */
  793. while (len > 0) {
  794. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  795. if (user_src && copy_from_user(k_src,
  796. (void __user *)user_src,
  797. qcedev_areq->sha_op_req.data[i].len))
  798. return -EFAULT;
  799. len -= qcedev_areq->sha_op_req.data[i].len;
  800. k_src += qcedev_areq->sha_op_req.data[i].len;
  801. i++;
  802. }
  803. handle->sha_ctxt.trailing_buf_len = total;
  804. return 0;
  805. }
  806. buf_size = total + CACHE_LINE_SIZE * 2;
  807. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  808. if (k_buf_src == NULL)
  809. return -ENOMEM;
  810. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  811. CACHE_LINE_SIZE);
  812. k_src = k_align_src;
  813. /* check for trailing buffer from previous updates and append it */
  814. if (t_buf > 0) {
  815. memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
  816. t_buf);
  817. k_src += t_buf;
  818. }
  819. /* Copy data from user src(s) */
  820. user_src = qcedev_areq->sha_op_req.data[0].vaddr;
  821. if (user_src && copy_from_user(k_src,
  822. (void __user *)user_src,
  823. qcedev_areq->sha_op_req.data[0].len)) {
  824. memset(k_buf_src, 0, buf_size);
  825. kfree(k_buf_src);
  826. return -EFAULT;
  827. }
  828. k_src += qcedev_areq->sha_op_req.data[0].len;
  829. for (i = 1; i < qcedev_areq->sha_op_req.entries; i++) {
  830. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  831. if (user_src && copy_from_user(k_src,
  832. (void __user *)user_src,
  833. qcedev_areq->sha_op_req.data[i].len)) {
  834. memset(k_buf_src, 0, buf_size);
  835. kfree(k_buf_src);
  836. return -EFAULT;
  837. }
  838. k_src += qcedev_areq->sha_op_req.data[i].len;
  839. }
  840. /* get new trailing buffer */
  841. sha_pad_len = ALIGN(total, CE_SHA_BLOCK_SIZE) - total;
  842. trailing_buf_len = CE_SHA_BLOCK_SIZE - sha_pad_len;
  843. qcedev_areq->sha_req.sreq.src = sg_src;
  844. sg_init_one(qcedev_areq->sha_req.sreq.src, k_align_src,
  845. total-trailing_buf_len);
  846. qcedev_areq->sha_req.sreq.nbytes = total - trailing_buf_len;
  847. /* update sha_ctxt trailing buf content to new trailing buf */
  848. if (trailing_buf_len > 0) {
  849. memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
  850. memcpy(&handle->sha_ctxt.trailing_buf[0],
  851. (k_src - trailing_buf_len),
  852. trailing_buf_len);
  853. }
  854. handle->sha_ctxt.trailing_buf_len = trailing_buf_len;
  855. err = submit_req(qcedev_areq, handle);
  856. handle->sha_ctxt.last_blk = 0;
  857. handle->sha_ctxt.first_blk = 0;
  858. memset(k_buf_src, 0, buf_size);
  859. kfree(k_buf_src);
  860. return err;
  861. }
  862. static int qcedev_sha_update(struct qcedev_async_req *qcedev_areq,
  863. struct qcedev_handle *handle,
  864. struct scatterlist *sg_src)
  865. {
  866. int err = 0;
  867. int i = 0;
  868. int j = 0;
  869. int k = 0;
  870. int num_entries = 0;
  871. uint32_t total = 0;
  872. if (!handle->sha_ctxt.init_done) {
  873. pr_err("%s Init was not called\n", __func__);
  874. return -EINVAL;
  875. }
  876. if (qcedev_areq->sha_op_req.data_len > QCE_MAX_OPER_DATA) {
  877. struct qcedev_sha_op_req *saved_req;
  878. struct qcedev_sha_op_req req;
  879. struct qcedev_sha_op_req *sreq = &qcedev_areq->sha_op_req;
  880. uint32_t req_size = 0;
  881. req_size = sizeof(struct qcedev_sha_op_req);
  882. /* save the original req structure */
  883. saved_req =
  884. kmalloc(req_size, GFP_KERNEL);
  885. if (saved_req == NULL) {
  886. pr_err("%s:Can't Allocate mem:saved_req 0x%lx\n",
  887. __func__, (uintptr_t)saved_req);
  888. return -ENOMEM;
  889. }
  890. memcpy(&req, sreq, sizeof(*sreq));
  891. memcpy(saved_req, sreq, sizeof(*sreq));
  892. i = 0;
  893. /* Address 32 KB at a time */
  894. while ((i < req.entries) && (err == 0)) {
  895. if (sreq->data[i].len > QCE_MAX_OPER_DATA) {
  896. sreq->data[0].len = QCE_MAX_OPER_DATA;
  897. if (i > 0) {
  898. sreq->data[0].vaddr =
  899. sreq->data[i].vaddr;
  900. }
  901. sreq->data_len = QCE_MAX_OPER_DATA;
  902. sreq->entries = 1;
  903. err = qcedev_sha_update_max_xfer(qcedev_areq,
  904. handle, sg_src);
  905. sreq->data[i].len = req.data[i].len -
  906. QCE_MAX_OPER_DATA;
  907. sreq->data[i].vaddr = req.data[i].vaddr +
  908. QCE_MAX_OPER_DATA;
  909. req.data[i].vaddr = sreq->data[i].vaddr;
  910. req.data[i].len = sreq->data[i].len;
  911. } else {
  912. total = 0;
  913. for (j = i; j < req.entries; j++) {
  914. num_entries++;
  915. if ((total + sreq->data[j].len) >=
  916. QCE_MAX_OPER_DATA) {
  917. sreq->data[j].len =
  918. (QCE_MAX_OPER_DATA - total);
  919. total = QCE_MAX_OPER_DATA;
  920. break;
  921. }
  922. total += sreq->data[j].len;
  923. }
  924. sreq->data_len = total;
  925. if (i > 0)
  926. for (k = 0; k < num_entries; k++) {
  927. sreq->data[k].len =
  928. sreq->data[i+k].len;
  929. sreq->data[k].vaddr =
  930. sreq->data[i+k].vaddr;
  931. }
  932. sreq->entries = num_entries;
  933. i = j;
  934. err = qcedev_sha_update_max_xfer(qcedev_areq,
  935. handle, sg_src);
  936. num_entries = 0;
  937. sreq->data[i].vaddr = req.data[i].vaddr +
  938. sreq->data[i].len;
  939. sreq->data[i].len = req.data[i].len -
  940. sreq->data[i].len;
  941. req.data[i].vaddr = sreq->data[i].vaddr;
  942. req.data[i].len = sreq->data[i].len;
  943. if (sreq->data[i].len == 0)
  944. i++;
  945. }
  946. } /* end of while ((i < req.entries) && (err == 0)) */
  947. /* Restore the original req structure */
  948. for (i = 0; i < saved_req->entries; i++) {
  949. sreq->data[i].len = saved_req->data[i].len;
  950. sreq->data[i].vaddr = saved_req->data[i].vaddr;
  951. }
  952. sreq->entries = saved_req->entries;
  953. sreq->data_len = saved_req->data_len;
  954. memset(saved_req, 0, req_size);
  955. kfree(saved_req);
  956. } else
  957. err = qcedev_sha_update_max_xfer(qcedev_areq, handle, sg_src);
  958. return err;
  959. }
  960. static int qcedev_sha_final(struct qcedev_async_req *qcedev_areq,
  961. struct qcedev_handle *handle)
  962. {
  963. int err = 0;
  964. struct scatterlist sg_src;
  965. uint32_t total;
  966. uint8_t *k_buf_src = NULL;
  967. uint32_t buf_size = 0;
  968. uint8_t *k_align_src = NULL;
  969. if (!handle->sha_ctxt.init_done) {
  970. pr_err("%s Init was not called\n", __func__);
  971. return -EINVAL;
  972. }
  973. handle->sha_ctxt.last_blk = 1;
  974. total = handle->sha_ctxt.trailing_buf_len;
  975. buf_size = total + CACHE_LINE_SIZE * 2;
  976. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  977. if (k_buf_src == NULL)
  978. return -ENOMEM;
  979. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  980. CACHE_LINE_SIZE);
  981. memcpy(k_align_src, &handle->sha_ctxt.trailing_buf[0], total);
  982. qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
  983. sg_init_one(qcedev_areq->sha_req.sreq.src, k_align_src, total);
  984. qcedev_areq->sha_req.sreq.nbytes = total;
  985. err = submit_req(qcedev_areq, handle);
  986. handle->sha_ctxt.first_blk = 0;
  987. handle->sha_ctxt.last_blk = 0;
  988. handle->sha_ctxt.auth_data[0] = 0;
  989. handle->sha_ctxt.auth_data[1] = 0;
  990. handle->sha_ctxt.trailing_buf_len = 0;
  991. handle->sha_ctxt.init_done = false;
  992. memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
  993. memset(k_buf_src, 0, buf_size);
  994. kfree(k_buf_src);
  995. qcedev_areq->sha_req.sreq.src = NULL;
  996. return err;
  997. }
  998. static int qcedev_hash_cmac(struct qcedev_async_req *qcedev_areq,
  999. struct qcedev_handle *handle,
  1000. struct scatterlist *sg_src)
  1001. {
  1002. int err = 0;
  1003. int i = 0;
  1004. uint32_t total;
  1005. uint8_t *user_src = NULL;
  1006. uint8_t *k_src = NULL;
  1007. uint8_t *k_buf_src = NULL;
  1008. uint32_t buf_size = 0;
  1009. total = qcedev_areq->sha_op_req.data_len;
  1010. if ((qcedev_areq->sha_op_req.authklen != QCEDEV_AES_KEY_128) &&
  1011. (qcedev_areq->sha_op_req.authklen != QCEDEV_AES_KEY_256)) {
  1012. pr_err("%s: unsupported key length\n", __func__);
  1013. return -EINVAL;
  1014. }
  1015. if (copy_from_user(&handle->sha_ctxt.authkey[0],
  1016. (void __user *)qcedev_areq->sha_op_req.authkey,
  1017. qcedev_areq->sha_op_req.authklen))
  1018. return -EFAULT;
  1019. if (total > U32_MAX - CACHE_LINE_SIZE * 2)
  1020. return -EINVAL;
  1021. buf_size = total + CACHE_LINE_SIZE * 2;
  1022. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  1023. if (k_buf_src == NULL)
  1024. return -ENOMEM;
  1025. k_src = k_buf_src;
  1026. /* Copy data from user src(s) */
  1027. user_src = qcedev_areq->sha_op_req.data[0].vaddr;
  1028. for (i = 0; i < qcedev_areq->sha_op_req.entries; i++) {
  1029. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  1030. if (user_src && copy_from_user(k_src, (void __user *)user_src,
  1031. qcedev_areq->sha_op_req.data[i].len)) {
  1032. memset(k_buf_src, 0, buf_size);
  1033. kfree(k_buf_src);
  1034. return -EFAULT;
  1035. }
  1036. k_src += qcedev_areq->sha_op_req.data[i].len;
  1037. }
  1038. qcedev_areq->sha_req.sreq.src = sg_src;
  1039. sg_init_one(qcedev_areq->sha_req.sreq.src, k_buf_src, total);
  1040. qcedev_areq->sha_req.sreq.nbytes = total;
  1041. handle->sha_ctxt.diglen = qcedev_areq->sha_op_req.diglen;
  1042. err = submit_req(qcedev_areq, handle);
  1043. memset(k_buf_src, 0, buf_size);
  1044. kfree(k_buf_src);
  1045. return err;
  1046. }
  1047. static int qcedev_set_hmac_auth_key(struct qcedev_async_req *areq,
  1048. struct qcedev_handle *handle,
  1049. struct scatterlist *sg_src)
  1050. {
  1051. int err = 0;
  1052. if (areq->sha_op_req.authklen <= QCEDEV_MAX_KEY_SIZE) {
  1053. qcedev_sha_init(areq, handle);
  1054. if (copy_from_user(&handle->sha_ctxt.authkey[0],
  1055. (void __user *)areq->sha_op_req.authkey,
  1056. areq->sha_op_req.authklen))
  1057. return -EFAULT;
  1058. } else {
  1059. struct qcedev_async_req authkey_areq;
  1060. uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE];
  1061. init_completion(&authkey_areq.complete);
  1062. authkey_areq.sha_op_req.entries = 1;
  1063. authkey_areq.sha_op_req.data[0].vaddr =
  1064. areq->sha_op_req.authkey;
  1065. authkey_areq.sha_op_req.data[0].len = areq->sha_op_req.authklen;
  1066. authkey_areq.sha_op_req.data_len = areq->sha_op_req.authklen;
  1067. authkey_areq.sha_op_req.diglen = 0;
  1068. authkey_areq.handle = handle;
  1069. memset(&authkey_areq.sha_op_req.digest[0], 0,
  1070. QCEDEV_MAX_SHA_DIGEST);
  1071. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
  1072. authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA1;
  1073. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)
  1074. authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA256;
  1075. authkey_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
  1076. qcedev_sha_init(&authkey_areq, handle);
  1077. err = qcedev_sha_update(&authkey_areq, handle, sg_src);
  1078. if (!err)
  1079. err = qcedev_sha_final(&authkey_areq, handle);
  1080. else
  1081. return err;
  1082. memcpy(&authkey[0], &handle->sha_ctxt.digest[0],
  1083. handle->sha_ctxt.diglen);
  1084. qcedev_sha_init(areq, handle);
  1085. memcpy(&handle->sha_ctxt.authkey[0], &authkey[0],
  1086. handle->sha_ctxt.diglen);
  1087. }
  1088. return err;
  1089. }
  1090. static int qcedev_hmac_get_ohash(struct qcedev_async_req *qcedev_areq,
  1091. struct qcedev_handle *handle)
  1092. {
  1093. int err = 0;
  1094. struct scatterlist sg_src;
  1095. uint8_t *k_src = NULL;
  1096. uint32_t sha_block_size = 0;
  1097. uint32_t sha_digest_size = 0;
  1098. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
  1099. sha_digest_size = SHA1_DIGEST_SIZE;
  1100. sha_block_size = SHA1_BLOCK_SIZE;
  1101. } else {
  1102. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
  1103. sha_digest_size = SHA256_DIGEST_SIZE;
  1104. sha_block_size = SHA256_BLOCK_SIZE;
  1105. }
  1106. }
  1107. k_src = kmalloc(sha_block_size, GFP_KERNEL);
  1108. if (k_src == NULL)
  1109. return -ENOMEM;
  1110. /* check for trailing buffer from previous updates and append it */
  1111. memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
  1112. handle->sha_ctxt.trailing_buf_len);
  1113. qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
  1114. sg_init_one(qcedev_areq->sha_req.sreq.src, k_src, sha_block_size);
  1115. qcedev_areq->sha_req.sreq.nbytes = sha_block_size;
  1116. memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
  1117. memcpy(&handle->sha_ctxt.trailing_buf[0], &handle->sha_ctxt.digest[0],
  1118. sha_digest_size);
  1119. handle->sha_ctxt.trailing_buf_len = sha_digest_size;
  1120. handle->sha_ctxt.first_blk = 1;
  1121. handle->sha_ctxt.last_blk = 0;
  1122. handle->sha_ctxt.auth_data[0] = 0;
  1123. handle->sha_ctxt.auth_data[1] = 0;
  1124. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
  1125. memcpy(&handle->sha_ctxt.digest[0],
  1126. &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
  1127. handle->sha_ctxt.diglen = SHA1_DIGEST_SIZE;
  1128. }
  1129. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
  1130. memcpy(&handle->sha_ctxt.digest[0],
  1131. &_std_init_vector_sha256_uint8[0], SHA256_DIGEST_SIZE);
  1132. handle->sha_ctxt.diglen = SHA256_DIGEST_SIZE;
  1133. }
  1134. err = submit_req(qcedev_areq, handle);
  1135. handle->sha_ctxt.last_blk = 0;
  1136. handle->sha_ctxt.first_blk = 0;
  1137. memset(k_src, 0, sha_block_size);
  1138. kfree(k_src);
  1139. qcedev_areq->sha_req.sreq.src = NULL;
  1140. return err;
  1141. }
  1142. static int qcedev_hmac_update_iokey(struct qcedev_async_req *areq,
  1143. struct qcedev_handle *handle, bool ikey)
  1144. {
  1145. int i;
  1146. uint32_t constant;
  1147. uint32_t sha_block_size;
  1148. if (ikey)
  1149. constant = 0x36;
  1150. else
  1151. constant = 0x5c;
  1152. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
  1153. sha_block_size = SHA1_BLOCK_SIZE;
  1154. else
  1155. sha_block_size = SHA256_BLOCK_SIZE;
  1156. memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
  1157. for (i = 0; i < sha_block_size; i++)
  1158. handle->sha_ctxt.trailing_buf[i] =
  1159. (handle->sha_ctxt.authkey[i] ^ constant);
  1160. handle->sha_ctxt.trailing_buf_len = sha_block_size;
  1161. return 0;
  1162. }
  1163. static int qcedev_hmac_init(struct qcedev_async_req *areq,
  1164. struct qcedev_handle *handle,
  1165. struct scatterlist *sg_src)
  1166. {
  1167. int err;
  1168. struct qcedev_control *podev = handle->cntl;
  1169. err = qcedev_set_hmac_auth_key(areq, handle, sg_src);
  1170. if (err)
  1171. return err;
  1172. if (!podev->ce_support.sha_hmac)
  1173. qcedev_hmac_update_iokey(areq, handle, true);
  1174. return 0;
  1175. }
  1176. static int qcedev_hmac_final(struct qcedev_async_req *areq,
  1177. struct qcedev_handle *handle)
  1178. {
  1179. int err;
  1180. struct qcedev_control *podev = handle->cntl;
  1181. err = qcedev_sha_final(areq, handle);
  1182. if (podev->ce_support.sha_hmac)
  1183. return err;
  1184. qcedev_hmac_update_iokey(areq, handle, false);
  1185. err = qcedev_hmac_get_ohash(areq, handle);
  1186. if (err)
  1187. return err;
  1188. err = qcedev_sha_final(areq, handle);
  1189. return err;
  1190. }
  1191. static int qcedev_hash_init(struct qcedev_async_req *areq,
  1192. struct qcedev_handle *handle,
  1193. struct scatterlist *sg_src)
  1194. {
  1195. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  1196. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
  1197. return qcedev_sha_init(areq, handle);
  1198. else
  1199. return qcedev_hmac_init(areq, handle, sg_src);
  1200. }
  1201. static int qcedev_hash_update(struct qcedev_async_req *qcedev_areq,
  1202. struct qcedev_handle *handle,
  1203. struct scatterlist *sg_src)
  1204. {
  1205. return qcedev_sha_update(qcedev_areq, handle, sg_src);
  1206. }
  1207. static int qcedev_hash_final(struct qcedev_async_req *areq,
  1208. struct qcedev_handle *handle)
  1209. {
  1210. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  1211. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
  1212. return qcedev_sha_final(areq, handle);
  1213. else
  1214. return qcedev_hmac_final(areq, handle);
  1215. }
  1216. static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
  1217. int *di, struct qcedev_handle *handle,
  1218. uint8_t *k_align_src)
  1219. {
  1220. int err = 0;
  1221. int i = 0;
  1222. int dst_i = *di;
  1223. struct scatterlist sg_src;
  1224. uint32_t byteoffset = 0;
  1225. uint8_t *user_src = NULL;
  1226. uint8_t *k_align_dst = k_align_src;
  1227. struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
  1228. if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1229. byteoffset = areq->cipher_op_req.byteoffset;
  1230. user_src = areq->cipher_op_req.vbuf.src[0].vaddr;
  1231. if (user_src && copy_from_user((k_align_src + byteoffset),
  1232. (void __user *)user_src,
  1233. areq->cipher_op_req.vbuf.src[0].len))
  1234. return -EFAULT;
  1235. k_align_src += byteoffset + areq->cipher_op_req.vbuf.src[0].len;
  1236. for (i = 1; i < areq->cipher_op_req.entries; i++) {
  1237. user_src = areq->cipher_op_req.vbuf.src[i].vaddr;
  1238. if (user_src && copy_from_user(k_align_src,
  1239. (void __user *)user_src,
  1240. areq->cipher_op_req.vbuf.src[i].len)) {
  1241. return -EFAULT;
  1242. }
  1243. k_align_src += areq->cipher_op_req.vbuf.src[i].len;
  1244. }
  1245. /* restore src beginning */
  1246. k_align_src = k_align_dst;
  1247. areq->cipher_op_req.data_len += byteoffset;
  1248. areq->cipher_req.creq.src = (struct scatterlist *) &sg_src;
  1249. areq->cipher_req.creq.dst = (struct scatterlist *) &sg_src;
  1250. /* In place encryption/decryption */
  1251. sg_init_one(areq->cipher_req.creq.src,
  1252. k_align_dst,
  1253. areq->cipher_op_req.data_len);
  1254. areq->cipher_req.creq.cryptlen = areq->cipher_op_req.data_len;
  1255. areq->cipher_req.creq.iv = areq->cipher_op_req.iv;
  1256. areq->cipher_op_req.entries = 1;
  1257. err = submit_req(areq, handle);
  1258. /* copy data to destination buffer*/
  1259. creq->data_len -= byteoffset;
  1260. while (creq->data_len > 0) {
  1261. if (creq->vbuf.dst[dst_i].len <= creq->data_len) {
  1262. if (err == 0 && copy_to_user(
  1263. (void __user *)creq->vbuf.dst[dst_i].vaddr,
  1264. (k_align_dst + byteoffset),
  1265. creq->vbuf.dst[dst_i].len)) {
  1266. err = -EFAULT;
  1267. goto exit;
  1268. }
  1269. k_align_dst += creq->vbuf.dst[dst_i].len;
  1270. creq->data_len -= creq->vbuf.dst[dst_i].len;
  1271. dst_i++;
  1272. } else {
  1273. if (err == 0 && copy_to_user(
  1274. (void __user *)creq->vbuf.dst[dst_i].vaddr,
  1275. (k_align_dst + byteoffset),
  1276. creq->data_len)) {
  1277. err = -EFAULT;
  1278. goto exit;
  1279. }
  1280. k_align_dst += creq->data_len;
  1281. creq->vbuf.dst[dst_i].len -= creq->data_len;
  1282. creq->vbuf.dst[dst_i].vaddr += creq->data_len;
  1283. creq->data_len = 0;
  1284. }
  1285. }
  1286. *di = dst_i;
  1287. exit:
  1288. areq->cipher_req.creq.src = NULL;
  1289. areq->cipher_req.creq.dst = NULL;
  1290. return err;
  1291. };
  1292. static int qcedev_vbuf_ablk_cipher(struct qcedev_async_req *areq,
  1293. struct qcedev_handle *handle)
  1294. {
  1295. int err = 0;
  1296. int di = 0;
  1297. int i = 0;
  1298. int j = 0;
  1299. int k = 0;
  1300. uint32_t byteoffset = 0;
  1301. int num_entries = 0;
  1302. uint32_t total = 0;
  1303. uint32_t len;
  1304. uint8_t *k_buf_src = NULL;
  1305. uint32_t buf_size = 0;
  1306. uint8_t *k_align_src = NULL;
  1307. uint32_t max_data_xfer;
  1308. struct qcedev_cipher_op_req *saved_req;
  1309. uint32_t req_size = 0;
  1310. struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
  1311. total = 0;
  1312. if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1313. byteoffset = areq->cipher_op_req.byteoffset;
  1314. buf_size = QCE_MAX_OPER_DATA + CACHE_LINE_SIZE * 2;
  1315. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  1316. if (k_buf_src == NULL)
  1317. return -ENOMEM;
  1318. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  1319. CACHE_LINE_SIZE);
  1320. max_data_xfer = QCE_MAX_OPER_DATA - byteoffset;
  1321. req_size = sizeof(struct qcedev_cipher_op_req);
  1322. saved_req = kmemdup(creq, req_size, GFP_KERNEL);
  1323. if (saved_req == NULL) {
  1324. memset(k_buf_src, 0, buf_size);
  1325. kfree(k_buf_src);
  1326. return -ENOMEM;
  1327. }
  1328. if (areq->cipher_op_req.data_len > max_data_xfer) {
  1329. struct qcedev_cipher_op_req req;
  1330. /* save the original req structure */
  1331. memcpy(&req, creq, sizeof(struct qcedev_cipher_op_req));
  1332. i = 0;
  1333. /* Address 32 KB at a time */
  1334. while ((i < req.entries) && (err == 0)) {
  1335. if (creq->vbuf.src[i].len > max_data_xfer) {
  1336. creq->vbuf.src[0].len = max_data_xfer;
  1337. if (i > 0) {
  1338. creq->vbuf.src[0].vaddr =
  1339. creq->vbuf.src[i].vaddr;
  1340. }
  1341. creq->data_len = max_data_xfer;
  1342. creq->entries = 1;
  1343. err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
  1344. &di, handle, k_align_src);
  1345. if (err < 0) {
  1346. memset(saved_req, 0, req_size);
  1347. memset(k_buf_src, 0, buf_size);
  1348. kfree(k_buf_src);
  1349. kfree(saved_req);
  1350. return err;
  1351. }
  1352. creq->vbuf.src[i].len = req.vbuf.src[i].len -
  1353. max_data_xfer;
  1354. creq->vbuf.src[i].vaddr =
  1355. req.vbuf.src[i].vaddr +
  1356. max_data_xfer;
  1357. req.vbuf.src[i].vaddr =
  1358. creq->vbuf.src[i].vaddr;
  1359. req.vbuf.src[i].len = creq->vbuf.src[i].len;
  1360. } else {
  1361. total = areq->cipher_op_req.byteoffset;
  1362. for (j = i; j < req.entries; j++) {
  1363. num_entries++;
  1364. if ((total + creq->vbuf.src[j].len)
  1365. >= max_data_xfer) {
  1366. creq->vbuf.src[j].len =
  1367. max_data_xfer - total;
  1368. total = max_data_xfer;
  1369. break;
  1370. }
  1371. total += creq->vbuf.src[j].len;
  1372. }
  1373. creq->data_len = total;
  1374. if (i > 0)
  1375. for (k = 0; k < num_entries; k++) {
  1376. creq->vbuf.src[k].len =
  1377. creq->vbuf.src[i+k].len;
  1378. creq->vbuf.src[k].vaddr =
  1379. creq->vbuf.src[i+k].vaddr;
  1380. }
  1381. creq->entries = num_entries;
  1382. i = j;
  1383. err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
  1384. &di, handle, k_align_src);
  1385. if (err < 0) {
  1386. memset(saved_req, 0, req_size);
  1387. memset(k_buf_src, 0, buf_size);
  1388. kfree(k_buf_src);
  1389. kfree(saved_req);
  1390. return err;
  1391. }
  1392. num_entries = 0;
  1393. areq->cipher_op_req.byteoffset = 0;
  1394. creq->vbuf.src[i].vaddr = req.vbuf.src[i].vaddr
  1395. + creq->vbuf.src[i].len;
  1396. creq->vbuf.src[i].len = req.vbuf.src[i].len -
  1397. creq->vbuf.src[i].len;
  1398. req.vbuf.src[i].vaddr =
  1399. creq->vbuf.src[i].vaddr;
  1400. req.vbuf.src[i].len = creq->vbuf.src[i].len;
  1401. if (creq->vbuf.src[i].len == 0)
  1402. i++;
  1403. }
  1404. areq->cipher_op_req.byteoffset = 0;
  1405. max_data_xfer = QCE_MAX_OPER_DATA;
  1406. byteoffset = 0;
  1407. } /* end of while ((i < req.entries) && (err == 0)) */
  1408. } else
  1409. err = qcedev_vbuf_ablk_cipher_max_xfer(areq, &di, handle,
  1410. k_align_src);
  1411. /* Restore the original req structure */
  1412. for (i = 0; i < saved_req->entries; i++) {
  1413. creq->vbuf.src[i].len = saved_req->vbuf.src[i].len;
  1414. creq->vbuf.src[i].vaddr = saved_req->vbuf.src[i].vaddr;
  1415. }
  1416. for (len = 0, i = 0; len < saved_req->data_len; i++) {
  1417. creq->vbuf.dst[i].len = saved_req->vbuf.dst[i].len;
  1418. creq->vbuf.dst[i].vaddr = saved_req->vbuf.dst[i].vaddr;
  1419. len += saved_req->vbuf.dst[i].len;
  1420. }
  1421. creq->entries = saved_req->entries;
  1422. creq->data_len = saved_req->data_len;
  1423. creq->byteoffset = saved_req->byteoffset;
  1424. memset(saved_req, 0, req_size);
  1425. memset(k_buf_src, 0, buf_size);
  1426. kfree(saved_req);
  1427. kfree(k_buf_src);
  1428. return err;
  1429. }
  1430. static int qcedev_smmu_ablk_offload_cipher(struct qcedev_async_req *areq,
  1431. struct qcedev_handle *handle)
  1432. {
  1433. int i = 0;
  1434. int err = 0;
  1435. size_t byteoffset = 0;
  1436. size_t transfer_data_len = 0;
  1437. size_t pending_data_len = 0;
  1438. size_t max_data_xfer = MAX_CEHW_REQ_TRANSFER_SIZE - byteoffset;
  1439. uint8_t *user_src = NULL;
  1440. uint8_t *user_dst = NULL;
  1441. struct scatterlist sg_src;
  1442. struct scatterlist sg_dst;
  1443. if (areq->offload_cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1444. byteoffset = areq->offload_cipher_op_req.byteoffset;
  1445. /*
  1446. * areq has two components:
  1447. * a) Request that comes from userspace i.e. offload_cipher_op_req
  1448. * b) Request that QCE understands - skcipher i.e. cipher_req.creq
  1449. * skcipher has sglist pointers src and dest that would carry
  1450. * data to/from CE.
  1451. */
  1452. areq->cipher_req.creq.src = &sg_src;
  1453. areq->cipher_req.creq.dst = &sg_dst;
  1454. sg_init_table(&sg_src, 1);
  1455. sg_init_table(&sg_dst, 1);
  1456. for (i = 0; i < areq->offload_cipher_op_req.entries; i++) {
  1457. transfer_data_len = 0;
  1458. pending_data_len = areq->offload_cipher_op_req.vbuf.src[i].len;
  1459. user_src = areq->offload_cipher_op_req.vbuf.src[i].vaddr;
  1460. user_src += byteoffset;
  1461. user_dst = areq->offload_cipher_op_req.vbuf.dst[i].vaddr;
  1462. user_dst += byteoffset;
  1463. areq->cipher_req.creq.iv = areq->offload_cipher_op_req.iv;
  1464. while (pending_data_len) {
  1465. transfer_data_len = min(max_data_xfer,
  1466. pending_data_len);
  1467. sg_src.dma_address = (dma_addr_t)user_src;
  1468. sg_dst.dma_address = (dma_addr_t)user_dst;
  1469. areq->cipher_req.creq.cryptlen = transfer_data_len;
  1470. sg_src.length = transfer_data_len;
  1471. sg_dst.length = transfer_data_len;
  1472. err = submit_req(areq, handle);
  1473. if (err) {
  1474. pr_err("%s: Error processing req, err = %d\n",
  1475. __func__, err);
  1476. goto exit;
  1477. }
  1478. /* update data len to be processed */
  1479. pending_data_len -= transfer_data_len;
  1480. user_src += transfer_data_len;
  1481. user_dst += transfer_data_len;
  1482. }
  1483. }
  1484. exit:
  1485. return err;
  1486. }
  1487. static int qcedev_check_cipher_key(struct qcedev_cipher_op_req *req,
  1488. struct qcedev_control *podev)
  1489. {
  1490. /* if intending to use HW key make sure key fields are set
  1491. * correctly and HW key is indeed supported in target
  1492. */
  1493. if (req->encklen == 0) {
  1494. int i;
  1495. for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
  1496. if (req->enckey[i]) {
  1497. pr_err("%s: Invalid key: non-zero key input\n",
  1498. __func__);
  1499. goto error;
  1500. }
  1501. }
  1502. if ((req->op != QCEDEV_OPER_ENC_NO_KEY) &&
  1503. (req->op != QCEDEV_OPER_DEC_NO_KEY))
  1504. if (!podev->platform_support.hw_key_support) {
  1505. pr_err("%s: Invalid op %d\n", __func__,
  1506. (uint32_t)req->op);
  1507. goto error;
  1508. }
  1509. } else {
  1510. if (req->encklen == QCEDEV_AES_KEY_192) {
  1511. if (!podev->ce_support.aes_key_192) {
  1512. pr_err("%s: AES-192 not supported\n", __func__);
  1513. goto error;
  1514. }
  1515. } else {
  1516. /* if not using HW key make sure key
  1517. * length is valid
  1518. */
  1519. if (req->mode == QCEDEV_AES_MODE_XTS) {
  1520. if ((req->encklen != QCEDEV_AES_KEY_128*2) &&
  1521. (req->encklen != QCEDEV_AES_KEY_256*2)) {
  1522. pr_err("%s: unsupported key size: %d\n",
  1523. __func__, req->encklen);
  1524. goto error;
  1525. }
  1526. } else {
  1527. if ((req->encklen != QCEDEV_AES_KEY_128) &&
  1528. (req->encklen != QCEDEV_AES_KEY_256)) {
  1529. pr_err("%s: unsupported key size %d\n",
  1530. __func__, req->encklen);
  1531. goto error;
  1532. }
  1533. }
  1534. }
  1535. }
  1536. return 0;
  1537. error:
  1538. return -EINVAL;
  1539. }
  1540. static int qcedev_check_cipher_params(struct qcedev_cipher_op_req *req,
  1541. struct qcedev_control *podev)
  1542. {
  1543. uint32_t total = 0;
  1544. uint32_t i;
  1545. if (req->use_pmem) {
  1546. pr_err("%s: Use of PMEM is not supported\n", __func__);
  1547. goto error;
  1548. }
  1549. if ((req->entries == 0) || (req->data_len == 0) ||
  1550. (req->entries > QCEDEV_MAX_BUFFERS)) {
  1551. pr_err("%s: Invalid cipher length/entries\n", __func__);
  1552. goto error;
  1553. }
  1554. if ((req->alg >= QCEDEV_ALG_LAST) ||
  1555. (req->mode >= QCEDEV_AES_DES_MODE_LAST)) {
  1556. pr_err("%s: Invalid algorithm %d\n", __func__,
  1557. (uint32_t)req->alg);
  1558. goto error;
  1559. }
  1560. if ((req->mode == QCEDEV_AES_MODE_XTS) &&
  1561. (!podev->ce_support.aes_xts)) {
  1562. pr_err("%s: XTS algorithm is not supported\n", __func__);
  1563. goto error;
  1564. }
  1565. if (req->alg == QCEDEV_ALG_AES) {
  1566. if (qcedev_check_cipher_key(req, podev))
  1567. goto error;
  1568. }
  1569. /* if using a byteoffset, make sure it is CTR mode using vbuf */
  1570. if (req->byteoffset) {
  1571. if (req->mode != QCEDEV_AES_MODE_CTR) {
  1572. pr_err("%s: Operation on byte offset not supported\n",
  1573. __func__);
  1574. goto error;
  1575. }
  1576. if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
  1577. pr_err("%s: Invalid byte offset\n", __func__);
  1578. goto error;
  1579. }
  1580. total = req->byteoffset;
  1581. for (i = 0; i < req->entries; i++) {
  1582. if (total > U32_MAX - req->vbuf.src[i].len) {
  1583. pr_err("%s:Integer overflow on total src len\n",
  1584. __func__);
  1585. goto error;
  1586. }
  1587. total += req->vbuf.src[i].len;
  1588. }
  1589. }
  1590. if (req->data_len < req->byteoffset) {
  1591. pr_err("%s: req data length %u is less than byteoffset %u\n",
  1592. __func__, req->data_len, req->byteoffset);
  1593. goto error;
  1594. }
  1595. /* Ensure IV size */
  1596. if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
  1597. pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
  1598. goto error;
  1599. }
  1600. /* Ensure Key size */
  1601. if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
  1602. pr_err("%s: Klen is not correct: %u\n", __func__, req->encklen);
  1603. goto error;
  1604. }
  1605. /* Ensure zer ivlen for ECB mode */
  1606. if (req->ivlen > 0) {
  1607. if ((req->mode == QCEDEV_AES_MODE_ECB) ||
  1608. (req->mode == QCEDEV_DES_MODE_ECB)) {
  1609. pr_err("%s: Expecting a zero length IV\n", __func__);
  1610. goto error;
  1611. }
  1612. } else {
  1613. if ((req->mode != QCEDEV_AES_MODE_ECB) &&
  1614. (req->mode != QCEDEV_DES_MODE_ECB)) {
  1615. pr_err("%s: Expecting a non-zero ength IV\n", __func__);
  1616. goto error;
  1617. }
  1618. }
  1619. /* Check for sum of all dst length is equal to data_len */
  1620. for (i = 0, total = 0; i < req->entries; i++) {
  1621. if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) {
  1622. pr_err("%s: NULL req dst vbuf[%d] with length %d\n",
  1623. __func__, i, req->vbuf.dst[i].len);
  1624. goto error;
  1625. }
  1626. if (req->vbuf.dst[i].len >= U32_MAX - total) {
  1627. pr_err("%s: Integer overflow on total req dst vbuf length\n",
  1628. __func__);
  1629. goto error;
  1630. }
  1631. total += req->vbuf.dst[i].len;
  1632. }
  1633. if (total != req->data_len) {
  1634. pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
  1635. __func__, i, total, req->data_len);
  1636. goto error;
  1637. }
  1638. /* Check for sum of all src length is equal to data_len */
  1639. for (i = 0, total = 0; i < req->entries; i++) {
  1640. if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) {
  1641. pr_err("%s: NULL req src vbuf[%d] with length %d\n",
  1642. __func__, i, req->vbuf.src[i].len);
  1643. goto error;
  1644. }
  1645. if (req->vbuf.src[i].len > U32_MAX - total) {
  1646. pr_err("%s: Integer overflow on total req src vbuf length\n",
  1647. __func__);
  1648. goto error;
  1649. }
  1650. total += req->vbuf.src[i].len;
  1651. }
  1652. if (total != req->data_len) {
  1653. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1654. __func__, total, req->data_len);
  1655. goto error;
  1656. }
  1657. return 0;
  1658. error:
  1659. return -EINVAL;
  1660. }
  1661. static int qcedev_check_sha_params(struct qcedev_sha_op_req *req,
  1662. struct qcedev_control *podev)
  1663. {
  1664. uint32_t total = 0;
  1665. uint32_t i;
  1666. if ((req->alg == QCEDEV_ALG_AES_CMAC) &&
  1667. (!podev->ce_support.cmac)) {
  1668. pr_err("%s: CMAC not supported\n", __func__);
  1669. goto sha_error;
  1670. }
  1671. if ((!req->entries) || (req->entries > QCEDEV_MAX_BUFFERS)) {
  1672. pr_err("%s: Invalid num entries (%d)\n",
  1673. __func__, req->entries);
  1674. goto sha_error;
  1675. }
  1676. if (req->alg >= QCEDEV_ALG_SHA_ALG_LAST) {
  1677. pr_err("%s: Invalid algorithm (%d)\n", __func__, req->alg);
  1678. goto sha_error;
  1679. }
  1680. if ((req->alg == QCEDEV_ALG_SHA1_HMAC) ||
  1681. (req->alg == QCEDEV_ALG_SHA256_HMAC)) {
  1682. if (req->authkey == NULL) {
  1683. pr_err("%s: Invalid authkey pointer\n", __func__);
  1684. goto sha_error;
  1685. }
  1686. if (req->authklen <= 0) {
  1687. pr_err("%s: Invalid authkey length (%d)\n",
  1688. __func__, req->authklen);
  1689. goto sha_error;
  1690. }
  1691. }
  1692. if (req->alg == QCEDEV_ALG_AES_CMAC) {
  1693. if ((req->authklen != QCEDEV_AES_KEY_128) &&
  1694. (req->authklen != QCEDEV_AES_KEY_256)) {
  1695. pr_err("%s: unsupported key length\n", __func__);
  1696. goto sha_error;
  1697. }
  1698. }
  1699. /* Check for sum of all src length is equal to data_len */
  1700. for (i = 0, total = 0; i < req->entries; i++) {
  1701. if (req->data[i].len > U32_MAX - total) {
  1702. pr_err("%s: Integer overflow on total req buf length\n",
  1703. __func__);
  1704. goto sha_error;
  1705. }
  1706. total += req->data[i].len;
  1707. }
  1708. if (total != req->data_len) {
  1709. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1710. __func__, total, req->data_len);
  1711. goto sha_error;
  1712. }
  1713. return 0;
  1714. sha_error:
  1715. return -EINVAL;
  1716. }
  1717. static int qcedev_check_offload_cipher_key(struct qcedev_offload_cipher_op_req *req,
  1718. struct qcedev_control *podev)
  1719. {
  1720. if (req->encklen == 0)
  1721. return -EINVAL;
  1722. /* AES-192 is not a valid option for OFFLOAD use case */
  1723. if ((req->encklen != QCEDEV_AES_KEY_128) &&
  1724. (req->encklen != QCEDEV_AES_KEY_256)) {
  1725. pr_err("%s: unsupported key size %d\n",
  1726. __func__, req->encklen);
  1727. goto error;
  1728. }
  1729. return 0;
  1730. error:
  1731. return -EINVAL;
  1732. }
  1733. static int qcedev_check_offload_cipher_params(struct qcedev_offload_cipher_op_req *req,
  1734. struct qcedev_control *podev)
  1735. {
  1736. uint32_t total = 0;
  1737. int i = 0;
  1738. if ((req->entries == 0) || (req->data_len == 0) ||
  1739. (req->entries > QCEDEV_MAX_BUFFERS)) {
  1740. pr_err("%s: Invalid cipher length/entries\n", __func__);
  1741. goto error;
  1742. }
  1743. if ((req->alg != QCEDEV_ALG_AES) ||
  1744. (req->mode > QCEDEV_AES_MODE_CTR)) {
  1745. pr_err("%s: Invalid algorithm %d\n", __func__,
  1746. (uint32_t)req->alg);
  1747. goto error;
  1748. }
  1749. if (qcedev_check_offload_cipher_key(req, podev))
  1750. goto error;
  1751. if (req->block_offset >= AES_CE_BLOCK_SIZE)
  1752. goto error;
  1753. /* if using a byteoffset, make sure it is CTR mode using vbuf */
  1754. if (req->byteoffset) {
  1755. if (req->mode != QCEDEV_AES_MODE_CTR) {
  1756. pr_err("%s: Operation on byte offset not supported\n",
  1757. __func__);
  1758. goto error;
  1759. }
  1760. if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
  1761. pr_err("%s: Invalid byte offset\n", __func__);
  1762. goto error;
  1763. }
  1764. total = req->byteoffset;
  1765. for (i = 0; i < req->entries; i++) {
  1766. if (total > U32_MAX - req->vbuf.src[i].len) {
  1767. pr_err("%s:Int overflow on total src len\n",
  1768. __func__);
  1769. goto error;
  1770. }
  1771. total += req->vbuf.src[i].len;
  1772. }
  1773. }
  1774. if (req->data_len < req->byteoffset) {
  1775. pr_err("%s: req data length %u is less than byteoffset %u\n",
  1776. __func__, req->data_len, req->byteoffset);
  1777. goto error;
  1778. }
  1779. /* Ensure IV size */
  1780. if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
  1781. pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
  1782. goto error;
  1783. }
  1784. /* Ensure Key size */
  1785. if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
  1786. pr_err("%s: Klen is not correct: %u\n", __func__,
  1787. req->encklen);
  1788. goto error;
  1789. }
  1790. /* Check for sum of all dst length is equal to data_len */
  1791. for (i = 0, total = 0; i < req->entries; i++) {
  1792. if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) {
  1793. pr_err("%s: NULL req dst vbuf[%d] with length %d\n",
  1794. __func__, i, req->vbuf.dst[i].len);
  1795. goto error;
  1796. }
  1797. if (req->vbuf.dst[i].len >= U32_MAX - total) {
  1798. pr_err("%s: Int overflow on total req dst vbuf len\n",
  1799. __func__);
  1800. goto error;
  1801. }
  1802. total += req->vbuf.dst[i].len;
  1803. }
  1804. if (total != req->data_len) {
  1805. pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
  1806. __func__, i, total, req->data_len);
  1807. goto error;
  1808. }
  1809. /* Check for sum of all src length is equal to data_len */
  1810. for (i = 0, total = 0; i < req->entries; i++) {
  1811. if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) {
  1812. pr_err("%s: NULL req src vbuf[%d] with length %d\n",
  1813. __func__, i, req->vbuf.src[i].len);
  1814. goto error;
  1815. }
  1816. if (req->vbuf.src[i].len > U32_MAX - total) {
  1817. pr_err("%s: Int overflow on total req src vbuf len\n",
  1818. __func__);
  1819. goto error;
  1820. }
  1821. total += req->vbuf.src[i].len;
  1822. }
  1823. if (total != req->data_len) {
  1824. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1825. __func__, total, req->data_len);
  1826. goto error;
  1827. }
  1828. return 0;
  1829. error:
  1830. return -EINVAL;
  1831. }
  1832. long qcedev_ioctl(struct file *file,
  1833. unsigned int cmd, unsigned long arg)
  1834. {
  1835. int err = 0;
  1836. struct qcedev_handle *handle;
  1837. struct qcedev_control *podev;
  1838. struct qcedev_async_req *qcedev_areq;
  1839. struct qcedev_stat *pstat;
  1840. qcedev_areq = kzalloc(sizeof(struct qcedev_async_req), GFP_KERNEL);
  1841. if (!qcedev_areq)
  1842. return -ENOMEM;
  1843. handle = file->private_data;
  1844. podev = handle->cntl;
  1845. qcedev_areq->handle = handle;
  1846. if (podev == NULL || podev->magic != QCEDEV_MAGIC) {
  1847. pr_err("%s: invalid handle %pK\n",
  1848. __func__, podev);
  1849. err = -ENOENT;
  1850. goto exit_free_qcedev_areq;
  1851. }
  1852. /* Verify user arguments. */
  1853. if (_IOC_TYPE(cmd) != QCEDEV_IOC_MAGIC) {
  1854. err = -ENOTTY;
  1855. goto exit_free_qcedev_areq;
  1856. }
  1857. init_completion(&qcedev_areq->complete);
  1858. pstat = &_qcedev_stat;
  1859. switch (cmd) {
  1860. case QCEDEV_IOCTL_ENC_REQ:
  1861. case QCEDEV_IOCTL_DEC_REQ:
  1862. if (copy_from_user(&qcedev_areq->cipher_op_req,
  1863. (void __user *)arg,
  1864. sizeof(struct qcedev_cipher_op_req))) {
  1865. err = -EFAULT;
  1866. goto exit_free_qcedev_areq;
  1867. }
  1868. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_CIPHER;
  1869. if (qcedev_check_cipher_params(&qcedev_areq->cipher_op_req,
  1870. podev)) {
  1871. err = -EINVAL;
  1872. goto exit_free_qcedev_areq;
  1873. }
  1874. err = qcedev_vbuf_ablk_cipher(qcedev_areq, handle);
  1875. if (err)
  1876. goto exit_free_qcedev_areq;
  1877. if (copy_to_user((void __user *)arg,
  1878. &qcedev_areq->cipher_op_req,
  1879. sizeof(struct qcedev_cipher_op_req))) {
  1880. err = -EFAULT;
  1881. goto exit_free_qcedev_areq;
  1882. }
  1883. break;
  1884. case QCEDEV_IOCTL_OFFLOAD_OP_REQ:
  1885. if (copy_from_user(&qcedev_areq->offload_cipher_op_req,
  1886. (void __user *)arg,
  1887. sizeof(struct qcedev_offload_cipher_op_req))) {
  1888. err = -EFAULT;
  1889. goto exit_free_qcedev_areq;
  1890. }
  1891. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER;
  1892. if (qcedev_check_offload_cipher_params(
  1893. &qcedev_areq->offload_cipher_op_req, podev)) {
  1894. err = -EINVAL;
  1895. goto exit_free_qcedev_areq;
  1896. }
  1897. qcedev_areq->offload_cipher_op_req.err = QCEDEV_OFFLOAD_NO_ERROR;
  1898. err = qcedev_smmu_ablk_offload_cipher(qcedev_areq, handle);
  1899. if (err)
  1900. goto exit_free_qcedev_areq;
  1901. if (copy_to_user((void __user *)arg,
  1902. &qcedev_areq->offload_cipher_op_req,
  1903. sizeof(struct qcedev_offload_cipher_op_req))) {
  1904. err = -EFAULT;
  1905. goto exit_free_qcedev_areq;
  1906. }
  1907. break;
  1908. case QCEDEV_IOCTL_SHA_INIT_REQ:
  1909. {
  1910. struct scatterlist sg_src;
  1911. if (copy_from_user(&qcedev_areq->sha_op_req,
  1912. (void __user *)arg,
  1913. sizeof(struct qcedev_sha_op_req))) {
  1914. err = -EFAULT;
  1915. goto exit_free_qcedev_areq;
  1916. }
  1917. mutex_lock(&hash_access_lock);
  1918. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  1919. mutex_unlock(&hash_access_lock);
  1920. err = -EINVAL;
  1921. goto exit_free_qcedev_areq;
  1922. }
  1923. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  1924. err = qcedev_hash_init(qcedev_areq, handle, &sg_src);
  1925. if (err) {
  1926. mutex_unlock(&hash_access_lock);
  1927. goto exit_free_qcedev_areq;
  1928. }
  1929. mutex_unlock(&hash_access_lock);
  1930. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  1931. sizeof(struct qcedev_sha_op_req))) {
  1932. err = -EFAULT;
  1933. goto exit_free_qcedev_areq;
  1934. }
  1935. handle->sha_ctxt.init_done = true;
  1936. }
  1937. break;
  1938. case QCEDEV_IOCTL_GET_CMAC_REQ:
  1939. if (!podev->ce_support.cmac) {
  1940. err = -ENOTTY;
  1941. goto exit_free_qcedev_areq;
  1942. }
  1943. fallthrough;
  1944. case QCEDEV_IOCTL_SHA_UPDATE_REQ:
  1945. {
  1946. struct scatterlist sg_src;
  1947. if (copy_from_user(&qcedev_areq->sha_op_req,
  1948. (void __user *)arg,
  1949. sizeof(struct qcedev_sha_op_req))) {
  1950. err = -EFAULT;
  1951. goto exit_free_qcedev_areq;
  1952. }
  1953. mutex_lock(&hash_access_lock);
  1954. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  1955. mutex_unlock(&hash_access_lock);
  1956. err = -EINVAL;
  1957. goto exit_free_qcedev_areq;
  1958. }
  1959. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  1960. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_AES_CMAC) {
  1961. err = qcedev_hash_cmac(qcedev_areq, handle, &sg_src);
  1962. if (err) {
  1963. mutex_unlock(&hash_access_lock);
  1964. goto exit_free_qcedev_areq;
  1965. }
  1966. } else {
  1967. if (!handle->sha_ctxt.init_done) {
  1968. pr_err("%s Init was not called\n", __func__);
  1969. mutex_unlock(&hash_access_lock);
  1970. err = -EINVAL;
  1971. goto exit_free_qcedev_areq;
  1972. }
  1973. err = qcedev_hash_update(qcedev_areq, handle, &sg_src);
  1974. if (err) {
  1975. mutex_unlock(&hash_access_lock);
  1976. goto exit_free_qcedev_areq;
  1977. }
  1978. }
  1979. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  1980. pr_err("Invalid sha_ctxt.diglen %d\n",
  1981. handle->sha_ctxt.diglen);
  1982. mutex_unlock(&hash_access_lock);
  1983. err = -EINVAL;
  1984. goto exit_free_qcedev_areq;
  1985. }
  1986. memcpy(&qcedev_areq->sha_op_req.digest[0],
  1987. &handle->sha_ctxt.digest[0],
  1988. handle->sha_ctxt.diglen);
  1989. mutex_unlock(&hash_access_lock);
  1990. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  1991. sizeof(struct qcedev_sha_op_req))) {
  1992. err = -EFAULT;
  1993. goto exit_free_qcedev_areq;
  1994. }
  1995. }
  1996. break;
  1997. case QCEDEV_IOCTL_SHA_FINAL_REQ:
  1998. if (!handle->sha_ctxt.init_done) {
  1999. pr_err("%s Init was not called\n", __func__);
  2000. err = -EINVAL;
  2001. goto exit_free_qcedev_areq;
  2002. }
  2003. if (copy_from_user(&qcedev_areq->sha_op_req,
  2004. (void __user *)arg,
  2005. sizeof(struct qcedev_sha_op_req))) {
  2006. err = -EFAULT;
  2007. goto exit_free_qcedev_areq;
  2008. }
  2009. mutex_lock(&hash_access_lock);
  2010. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  2011. mutex_unlock(&hash_access_lock);
  2012. err = -EINVAL;
  2013. goto exit_free_qcedev_areq;
  2014. }
  2015. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  2016. err = qcedev_hash_final(qcedev_areq, handle);
  2017. if (err) {
  2018. mutex_unlock(&hash_access_lock);
  2019. goto exit_free_qcedev_areq;
  2020. }
  2021. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2022. pr_err("Invalid sha_ctxt.diglen %d\n",
  2023. handle->sha_ctxt.diglen);
  2024. mutex_unlock(&hash_access_lock);
  2025. err = -EINVAL;
  2026. goto exit_free_qcedev_areq;
  2027. }
  2028. qcedev_areq->sha_op_req.diglen = handle->sha_ctxt.diglen;
  2029. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2030. &handle->sha_ctxt.digest[0],
  2031. handle->sha_ctxt.diglen);
  2032. mutex_unlock(&hash_access_lock);
  2033. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2034. sizeof(struct qcedev_sha_op_req))) {
  2035. err = -EFAULT;
  2036. goto exit_free_qcedev_areq;
  2037. }
  2038. handle->sha_ctxt.init_done = false;
  2039. break;
  2040. case QCEDEV_IOCTL_GET_SHA_REQ:
  2041. {
  2042. struct scatterlist sg_src;
  2043. if (copy_from_user(&qcedev_areq->sha_op_req,
  2044. (void __user *)arg,
  2045. sizeof(struct qcedev_sha_op_req))) {
  2046. err = -EFAULT;
  2047. goto exit_free_qcedev_areq;
  2048. }
  2049. mutex_lock(&hash_access_lock);
  2050. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  2051. mutex_unlock(&hash_access_lock);
  2052. err = -EINVAL;
  2053. goto exit_free_qcedev_areq;
  2054. }
  2055. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  2056. qcedev_hash_init(qcedev_areq, handle, &sg_src);
  2057. err = qcedev_hash_update(qcedev_areq, handle, &sg_src);
  2058. if (err) {
  2059. mutex_unlock(&hash_access_lock);
  2060. goto exit_free_qcedev_areq;
  2061. }
  2062. err = qcedev_hash_final(qcedev_areq, handle);
  2063. if (err) {
  2064. mutex_unlock(&hash_access_lock);
  2065. goto exit_free_qcedev_areq;
  2066. }
  2067. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2068. pr_err("Invalid sha_ctxt.diglen %d\n",
  2069. handle->sha_ctxt.diglen);
  2070. mutex_unlock(&hash_access_lock);
  2071. err = -EINVAL;
  2072. goto exit_free_qcedev_areq;
  2073. }
  2074. qcedev_areq->sha_op_req.diglen = handle->sha_ctxt.diglen;
  2075. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2076. &handle->sha_ctxt.digest[0],
  2077. handle->sha_ctxt.diglen);
  2078. mutex_unlock(&hash_access_lock);
  2079. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2080. sizeof(struct qcedev_sha_op_req))) {
  2081. err = -EFAULT;
  2082. goto exit_free_qcedev_areq;
  2083. }
  2084. }
  2085. break;
  2086. case QCEDEV_IOCTL_MAP_BUF_REQ:
  2087. {
  2088. unsigned long long vaddr = 0;
  2089. struct qcedev_map_buf_req map_buf = { {0} };
  2090. int i = 0;
  2091. if (copy_from_user(&map_buf,
  2092. (void __user *)arg, sizeof(map_buf))) {
  2093. err = -EFAULT;
  2094. goto exit_free_qcedev_areq;
  2095. }
  2096. if (map_buf.num_fds > ARRAY_SIZE(map_buf.fd)) {
  2097. pr_err("%s: err: num_fds = %d exceeds max value\n",
  2098. __func__, map_buf.num_fds);
  2099. err = -EINVAL;
  2100. goto exit_free_qcedev_areq;
  2101. }
  2102. for (i = 0; i < map_buf.num_fds; i++) {
  2103. err = qcedev_check_and_map_buffer(handle,
  2104. map_buf.fd[i],
  2105. map_buf.fd_offset[i],
  2106. map_buf.fd_size[i],
  2107. &vaddr);
  2108. if (err) {
  2109. pr_err(
  2110. "%s: err: failed to map fd(%d) - %d\n",
  2111. __func__, map_buf.fd[i], err);
  2112. goto exit_free_qcedev_areq;
  2113. }
  2114. map_buf.buf_vaddr[i] = vaddr;
  2115. pr_info("%s: info: vaddr = %llx\n, fd = %d",
  2116. __func__, vaddr, map_buf.fd[i]);
  2117. }
  2118. if (copy_to_user((void __user *)arg, &map_buf,
  2119. sizeof(map_buf))) {
  2120. err = -EFAULT;
  2121. goto exit_free_qcedev_areq;
  2122. }
  2123. break;
  2124. }
  2125. case QCEDEV_IOCTL_UNMAP_BUF_REQ:
  2126. {
  2127. struct qcedev_unmap_buf_req unmap_buf = { { 0 } };
  2128. int i = 0;
  2129. if (copy_from_user(&unmap_buf,
  2130. (void __user *)arg, sizeof(unmap_buf))) {
  2131. err = -EFAULT;
  2132. goto exit_free_qcedev_areq;
  2133. }
  2134. if (unmap_buf.num_fds > ARRAY_SIZE(unmap_buf.fd)) {
  2135. pr_err("%s: err: num_fds = %d exceeds max value\n",
  2136. __func__, unmap_buf.num_fds);
  2137. err = -EINVAL;
  2138. goto exit_free_qcedev_areq;
  2139. }
  2140. for (i = 0; i < unmap_buf.num_fds; i++) {
  2141. err = qcedev_check_and_unmap_buffer(handle,
  2142. unmap_buf.fd[i]);
  2143. if (err) {
  2144. pr_err(
  2145. "%s: err: failed to unmap fd(%d) - %d\n",
  2146. __func__,
  2147. unmap_buf.fd[i], err);
  2148. goto exit_free_qcedev_areq;
  2149. }
  2150. }
  2151. break;
  2152. }
  2153. default:
  2154. err = -ENOTTY;
  2155. goto exit_free_qcedev_areq;
  2156. }
  2157. exit_free_qcedev_areq:
  2158. kfree(qcedev_areq);
  2159. return err;
  2160. }
  2161. static int qcedev_probe_device(struct platform_device *pdev)
  2162. {
  2163. void *handle = NULL;
  2164. int rc = 0;
  2165. struct qcedev_control *podev;
  2166. struct msm_ce_hw_support *platform_support;
  2167. podev = &qce_dev[0];
  2168. rc = alloc_chrdev_region(&qcedev_device_no, 0, 1, QCEDEV_DEV);
  2169. if (rc < 0) {
  2170. pr_err("alloc_chrdev_region failed %d\n", rc);
  2171. return rc;
  2172. }
  2173. driver_class = class_create(THIS_MODULE, QCEDEV_DEV);
  2174. if (IS_ERR(driver_class)) {
  2175. rc = -ENOMEM;
  2176. pr_err("class_create failed %d\n", rc);
  2177. goto exit_unreg_chrdev_region;
  2178. }
  2179. class_dev = device_create(driver_class, NULL, qcedev_device_no, NULL,
  2180. QCEDEV_DEV);
  2181. if (IS_ERR(class_dev)) {
  2182. pr_err("class_device_create failed %d\n", rc);
  2183. rc = -ENOMEM;
  2184. goto exit_destroy_class;
  2185. }
  2186. cdev_init(&podev->cdev, &qcedev_fops);
  2187. podev->cdev.owner = THIS_MODULE;
  2188. rc = cdev_add(&podev->cdev, MKDEV(MAJOR(qcedev_device_no), 0), 1);
  2189. if (rc < 0) {
  2190. pr_err("cdev_add failed %d\n", rc);
  2191. goto exit_destroy_device;
  2192. }
  2193. podev->minor = 0;
  2194. podev->high_bw_req_count = 0;
  2195. INIT_LIST_HEAD(&podev->ready_commands);
  2196. podev->active_command = NULL;
  2197. INIT_LIST_HEAD(&podev->context_banks);
  2198. spin_lock_init(&podev->lock);
  2199. tasklet_init(&podev->done_tasklet, req_done, (unsigned long)podev);
  2200. podev->icc_path = of_icc_get(&pdev->dev, "data_path");
  2201. if (IS_ERR(podev->icc_path)) {
  2202. rc = PTR_ERR(podev->icc_path);
  2203. pr_err("%s Failed to get icc path with error %d\n",
  2204. __func__, rc);
  2205. goto exit_del_cdev;
  2206. }
  2207. /*
  2208. * HLOS crypto vote values from DTSI. If no values specified, use
  2209. * nominal values.
  2210. */
  2211. if (of_property_read_u32((&pdev->dev)->of_node,
  2212. "qcom,icc_avg_bw",
  2213. &podev->icc_avg_bw)) {
  2214. pr_warn("%s: No icc avg BW set, using default\n", __func__);
  2215. podev->icc_avg_bw = CRYPTO_AVG_BW;
  2216. }
  2217. if (of_property_read_u32((&pdev->dev)->of_node,
  2218. "qcom,icc_peak_bw",
  2219. &podev->icc_peak_bw)) {
  2220. pr_warn("%s: No icc peak BW set, using default\n", __func__);
  2221. podev->icc_peak_bw = CRYPTO_PEAK_BW;
  2222. }
  2223. rc = icc_set_bw(podev->icc_path, podev->icc_avg_bw,
  2224. podev->icc_peak_bw);
  2225. if (rc) {
  2226. pr_err("%s Unable to set high bandwidth\n", __func__);
  2227. goto exit_unregister_bus_scale;
  2228. }
  2229. handle = qce_open(pdev, &rc);
  2230. if (handle == NULL) {
  2231. rc = -ENODEV;
  2232. goto exit_scale_busbandwidth;
  2233. }
  2234. rc = icc_set_bw(podev->icc_path, 0, 0);
  2235. if (rc) {
  2236. pr_err("%s Unable to set to low bandwidth\n", __func__);
  2237. goto exit_qce_close;
  2238. }
  2239. podev->qce = handle;
  2240. podev->pdev = pdev;
  2241. platform_set_drvdata(pdev, podev);
  2242. qce_hw_support(podev->qce, &podev->ce_support);
  2243. if (podev->ce_support.bam) {
  2244. podev->platform_support.ce_shared = 0;
  2245. podev->platform_support.shared_ce_resource = 0;
  2246. podev->platform_support.hw_key_support =
  2247. podev->ce_support.hw_key;
  2248. podev->platform_support.sha_hmac = 1;
  2249. } else {
  2250. platform_support =
  2251. (struct msm_ce_hw_support *)pdev->dev.platform_data;
  2252. podev->platform_support.ce_shared = platform_support->ce_shared;
  2253. podev->platform_support.shared_ce_resource =
  2254. platform_support->shared_ce_resource;
  2255. podev->platform_support.hw_key_support =
  2256. platform_support->hw_key_support;
  2257. podev->platform_support.sha_hmac = platform_support->sha_hmac;
  2258. }
  2259. podev->mem_client = qcedev_mem_new_client(MEM_ION);
  2260. if (!podev->mem_client) {
  2261. pr_err("%s: err: qcedev_mem_new_client failed\n", __func__);
  2262. goto exit_qce_close;
  2263. }
  2264. rc = of_platform_populate(pdev->dev.of_node, qcedev_match,
  2265. NULL, &pdev->dev);
  2266. if (rc) {
  2267. pr_err("%s: err: of_platform_populate failed: %d\n",
  2268. __func__, rc);
  2269. goto exit_mem_new_client;
  2270. }
  2271. return 0;
  2272. exit_mem_new_client:
  2273. if (podev->mem_client)
  2274. qcedev_mem_delete_client(podev->mem_client);
  2275. podev->mem_client = NULL;
  2276. exit_qce_close:
  2277. if (handle)
  2278. qce_close(handle);
  2279. exit_scale_busbandwidth:
  2280. icc_set_bw(podev->icc_path, 0, 0);
  2281. exit_unregister_bus_scale:
  2282. if (podev->icc_path)
  2283. icc_put(podev->icc_path);
  2284. exit_del_cdev:
  2285. cdev_del(&podev->cdev);
  2286. exit_destroy_device:
  2287. device_destroy(driver_class, qcedev_device_no);
  2288. exit_destroy_class:
  2289. class_destroy(driver_class);
  2290. exit_unreg_chrdev_region:
  2291. unregister_chrdev_region(qcedev_device_no, 1);
  2292. podev->icc_path = NULL;
  2293. platform_set_drvdata(pdev, NULL);
  2294. podev->pdev = NULL;
  2295. podev->qce = NULL;
  2296. return rc;
  2297. }
  2298. static int qcedev_probe(struct platform_device *pdev)
  2299. {
  2300. if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcedev"))
  2301. return qcedev_probe_device(pdev);
  2302. else if (of_device_is_compatible(pdev->dev.of_node,
  2303. "qcom,qcedev,context-bank"))
  2304. return qcedev_parse_context_bank(pdev);
  2305. return -EINVAL;
  2306. };
  2307. static int qcedev_remove(struct platform_device *pdev)
  2308. {
  2309. struct qcedev_control *podev;
  2310. podev = platform_get_drvdata(pdev);
  2311. if (!podev)
  2312. return 0;
  2313. if (podev->qce)
  2314. qce_close(podev->qce);
  2315. if (podev->icc_path)
  2316. icc_put(podev->icc_path);
  2317. tasklet_kill(&podev->done_tasklet);
  2318. cdev_del(&podev->cdev);
  2319. device_destroy(driver_class, qcedev_device_no);
  2320. class_destroy(driver_class);
  2321. unregister_chrdev_region(qcedev_device_no, 1);
  2322. return 0;
  2323. };
  2324. static int qcedev_suspend(struct platform_device *pdev, pm_message_t state)
  2325. {
  2326. struct qcedev_control *podev;
  2327. int ret;
  2328. podev = platform_get_drvdata(pdev);
  2329. if (!podev)
  2330. return 0;
  2331. mutex_lock(&qcedev_sent_bw_req);
  2332. if (podev->high_bw_req_count) {
  2333. ret = qcedev_control_clocks(podev, false);
  2334. if (ret)
  2335. goto suspend_exit;
  2336. }
  2337. suspend_exit:
  2338. mutex_unlock(&qcedev_sent_bw_req);
  2339. return 0;
  2340. }
  2341. static int qcedev_resume(struct platform_device *pdev)
  2342. {
  2343. struct qcedev_control *podev;
  2344. int ret;
  2345. podev = platform_get_drvdata(pdev);
  2346. if (!podev)
  2347. return 0;
  2348. mutex_lock(&qcedev_sent_bw_req);
  2349. if (podev->high_bw_req_count) {
  2350. ret = qcedev_control_clocks(podev, true);
  2351. if (ret)
  2352. goto resume_exit;
  2353. }
  2354. resume_exit:
  2355. mutex_unlock(&qcedev_sent_bw_req);
  2356. return 0;
  2357. }
  2358. static struct platform_driver qcedev_plat_driver = {
  2359. .probe = qcedev_probe,
  2360. .remove = qcedev_remove,
  2361. .suspend = qcedev_suspend,
  2362. .resume = qcedev_resume,
  2363. .driver = {
  2364. .name = "qce",
  2365. .of_match_table = qcedev_match,
  2366. },
  2367. };
  2368. static int _disp_stats(int id)
  2369. {
  2370. struct qcedev_stat *pstat;
  2371. int len = 0;
  2372. pstat = &_qcedev_stat;
  2373. len = scnprintf(_debug_read_buf, DEBUG_MAX_RW_BUF - 1,
  2374. "\nQTI QCE dev driver %d Statistics:\n",
  2375. id + 1);
  2376. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2377. " Encryption operation success : %d\n",
  2378. pstat->qcedev_enc_success);
  2379. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2380. " Encryption operation fail : %d\n",
  2381. pstat->qcedev_enc_fail);
  2382. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2383. " Decryption operation success : %d\n",
  2384. pstat->qcedev_dec_success);
  2385. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2386. " Encryption operation fail : %d\n",
  2387. pstat->qcedev_dec_fail);
  2388. return len;
  2389. }
  2390. static ssize_t _debug_stats_read(struct file *file, char __user *buf,
  2391. size_t count, loff_t *ppos)
  2392. {
  2393. ssize_t rc = -EINVAL;
  2394. int qcedev = *((int *) file->private_data);
  2395. int len;
  2396. len = _disp_stats(qcedev);
  2397. if (len <= count)
  2398. rc = simple_read_from_buffer((void __user *) buf, len,
  2399. ppos, (void *) _debug_read_buf, len);
  2400. return rc;
  2401. }
  2402. static ssize_t _debug_stats_write(struct file *file, const char __user *buf,
  2403. size_t count, loff_t *ppos)
  2404. {
  2405. memset((char *)&_qcedev_stat, 0, sizeof(struct qcedev_stat));
  2406. return count;
  2407. };
  2408. static const struct file_operations _debug_stats_ops = {
  2409. .open = simple_open,
  2410. .read = _debug_stats_read,
  2411. .write = _debug_stats_write,
  2412. };
  2413. static int _qcedev_debug_init(void)
  2414. {
  2415. int rc;
  2416. char name[DEBUG_MAX_FNAME];
  2417. struct dentry *dent;
  2418. _debug_dent = debugfs_create_dir("qcedev", NULL);
  2419. if (IS_ERR(_debug_dent)) {
  2420. pr_debug("qcedev debugfs_create_dir fail, error %ld\n",
  2421. PTR_ERR(_debug_dent));
  2422. return PTR_ERR(_debug_dent);
  2423. }
  2424. snprintf(name, DEBUG_MAX_FNAME-1, "stats-%d", 1);
  2425. _debug_qcedev = 0;
  2426. dent = debugfs_create_file(name, 0644, _debug_dent,
  2427. &_debug_qcedev, &_debug_stats_ops);
  2428. if (dent == NULL) {
  2429. pr_debug("qcedev debugfs_create_file fail, error %ld\n",
  2430. PTR_ERR(dent));
  2431. rc = PTR_ERR(dent);
  2432. goto err;
  2433. }
  2434. return 0;
  2435. err:
  2436. debugfs_remove_recursive(_debug_dent);
  2437. return rc;
  2438. }
  2439. static int qcedev_init(void)
  2440. {
  2441. _qcedev_debug_init();
  2442. return platform_driver_register(&qcedev_plat_driver);
  2443. }
  2444. static void qcedev_exit(void)
  2445. {
  2446. debugfs_remove_recursive(_debug_dent);
  2447. platform_driver_unregister(&qcedev_plat_driver);
  2448. }
  2449. MODULE_LICENSE("GPL v2");
  2450. MODULE_DESCRIPTION("QTI DEV Crypto driver");
  2451. MODULE_IMPORT_NS(DMA_BUF);
  2452. module_init(qcedev_init);
  2453. module_exit(qcedev_exit);