dp_tx.c 128 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814
  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. /* TODO Add support in TSO */
  44. #define DP_DESC_NUM_FRAG(x) 0
  45. /* disable TQM_BYPASS */
  46. #define TQM_BYPASS_WAR 0
  47. /* invalid peer id for reinject*/
  48. #define DP_INVALID_PEER 0XFFFE
  49. /*mapping between hal encrypt type and cdp_sec_type*/
  50. #define MAX_CDP_SEC_TYPE 12
  51. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  52. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  53. HAL_TX_ENCRYPT_TYPE_WEP_128,
  54. HAL_TX_ENCRYPT_TYPE_WEP_104,
  55. HAL_TX_ENCRYPT_TYPE_WEP_40,
  56. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  57. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  59. HAL_TX_ENCRYPT_TYPE_WAPI,
  60. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  62. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  63. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  64. #ifdef QCA_TX_LIMIT_CHECK
  65. /**
  66. * dp_tx_limit_check - Check if allocated tx descriptors reached
  67. * soc max limit and pdev max limit
  68. * @vdev: DP vdev handle
  69. *
  70. * Return: true if allocated tx descriptors reached max configured value, else
  71. * false
  72. */
  73. static inline bool
  74. dp_tx_limit_check(struct dp_vdev *vdev)
  75. {
  76. struct dp_pdev *pdev = vdev->pdev;
  77. struct dp_soc *soc = pdev->soc;
  78. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  79. soc->num_tx_allowed) {
  80. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  81. "%s: queued packets are more than max tx, drop the frame",
  82. __func__);
  83. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  84. return true;
  85. }
  86. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  87. pdev->num_tx_allowed) {
  88. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  89. "%s: queued packets are more than max tx, drop the frame",
  90. __func__);
  91. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  92. return true;
  93. }
  94. return false;
  95. }
  96. /**
  97. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  98. * reached soc max limit
  99. * @vdev: DP vdev handle
  100. *
  101. * Return: true if allocated tx descriptors reached max configured value, else
  102. * false
  103. */
  104. static inline bool
  105. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  106. {
  107. struct dp_pdev *pdev = vdev->pdev;
  108. struct dp_soc *soc = pdev->soc;
  109. if (qdf_atomic_read(&soc->num_tx_exception) >=
  110. soc->num_msdu_exception_desc) {
  111. dp_info("exc packets are more than max drop the exc pkt");
  112. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  113. return true;
  114. }
  115. return false;
  116. }
  117. /**
  118. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  119. * @vdev: DP pdev handle
  120. *
  121. * Return: void
  122. */
  123. static inline void
  124. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  125. {
  126. struct dp_soc *soc = pdev->soc;
  127. qdf_atomic_inc(&pdev->num_tx_outstanding);
  128. qdf_atomic_inc(&soc->num_tx_outstanding);
  129. }
  130. /**
  131. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  132. * @vdev: DP pdev handle
  133. *
  134. * Return: void
  135. */
  136. static inline void
  137. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  138. {
  139. struct dp_soc *soc = pdev->soc;
  140. qdf_atomic_dec(&pdev->num_tx_outstanding);
  141. qdf_atomic_dec(&soc->num_tx_outstanding);
  142. }
  143. #else //QCA_TX_LIMIT_CHECK
  144. static inline bool
  145. dp_tx_limit_check(struct dp_vdev *vdev)
  146. {
  147. return false;
  148. }
  149. static inline bool
  150. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  151. {
  152. return false;
  153. }
  154. static inline void
  155. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  156. {
  157. qdf_atomic_inc(&pdev->num_tx_outstanding);
  158. }
  159. static inline void
  160. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  161. {
  162. qdf_atomic_dec(&pdev->num_tx_outstanding);
  163. }
  164. #endif //QCA_TX_LIMIT_CHECK
  165. #if defined(FEATURE_TSO)
  166. /**
  167. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  168. *
  169. * @soc - core txrx main context
  170. * @seg_desc - tso segment descriptor
  171. * @num_seg_desc - tso number segment descriptor
  172. */
  173. static void dp_tx_tso_unmap_segment(
  174. struct dp_soc *soc,
  175. struct qdf_tso_seg_elem_t *seg_desc,
  176. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  177. {
  178. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  179. if (qdf_unlikely(!seg_desc)) {
  180. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  181. __func__, __LINE__);
  182. qdf_assert(0);
  183. } else if (qdf_unlikely(!num_seg_desc)) {
  184. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  185. __func__, __LINE__);
  186. qdf_assert(0);
  187. } else {
  188. bool is_last_seg;
  189. /* no tso segment left to do dma unmap */
  190. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  191. return;
  192. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  193. true : false;
  194. qdf_nbuf_unmap_tso_segment(soc->osdev,
  195. seg_desc, is_last_seg);
  196. num_seg_desc->num_seg.tso_cmn_num_seg--;
  197. }
  198. }
  199. /**
  200. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  201. * back to the freelist
  202. *
  203. * @soc - soc device handle
  204. * @tx_desc - Tx software descriptor
  205. */
  206. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  207. struct dp_tx_desc_s *tx_desc)
  208. {
  209. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  210. if (qdf_unlikely(!tx_desc->tso_desc)) {
  211. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  212. "%s %d TSO desc is NULL!",
  213. __func__, __LINE__);
  214. qdf_assert(0);
  215. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  216. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  217. "%s %d TSO num desc is NULL!",
  218. __func__, __LINE__);
  219. qdf_assert(0);
  220. } else {
  221. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  222. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  223. /* Add the tso num segment into the free list */
  224. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  225. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  226. tx_desc->tso_num_desc);
  227. tx_desc->tso_num_desc = NULL;
  228. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  229. }
  230. /* Add the tso segment into the free list*/
  231. dp_tx_tso_desc_free(soc,
  232. tx_desc->pool_id, tx_desc->tso_desc);
  233. tx_desc->tso_desc = NULL;
  234. }
  235. }
  236. #else
  237. static void dp_tx_tso_unmap_segment(
  238. struct dp_soc *soc,
  239. struct qdf_tso_seg_elem_t *seg_desc,
  240. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  241. {
  242. }
  243. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  244. struct dp_tx_desc_s *tx_desc)
  245. {
  246. }
  247. #endif
  248. /**
  249. * dp_tx_desc_release() - Release Tx Descriptor
  250. * @tx_desc : Tx Descriptor
  251. * @desc_pool_id: Descriptor Pool ID
  252. *
  253. * Deallocate all resources attached to Tx descriptor and free the Tx
  254. * descriptor.
  255. *
  256. * Return:
  257. */
  258. static void
  259. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  260. {
  261. struct dp_pdev *pdev = tx_desc->pdev;
  262. struct dp_soc *soc;
  263. uint8_t comp_status = 0;
  264. qdf_assert(pdev);
  265. soc = pdev->soc;
  266. dp_tx_outstanding_dec(pdev);
  267. if (tx_desc->frm_type == dp_tx_frm_tso)
  268. dp_tx_tso_desc_release(soc, tx_desc);
  269. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  270. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  271. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  272. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  273. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  274. qdf_atomic_dec(&soc->num_tx_exception);
  275. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  276. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  277. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  278. soc->hal_soc);
  279. else
  280. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  281. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  282. "Tx Completion Release desc %d status %d outstanding %d",
  283. tx_desc->id, comp_status,
  284. qdf_atomic_read(&pdev->num_tx_outstanding));
  285. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  286. return;
  287. }
  288. /**
  289. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  290. * @vdev: DP vdev Handle
  291. * @nbuf: skb
  292. * @msdu_info: msdu_info required to create HTT metadata
  293. *
  294. * Prepares and fills HTT metadata in the frame pre-header for special frames
  295. * that should be transmitted using varying transmit parameters.
  296. * There are 2 VDEV modes that currently needs this special metadata -
  297. * 1) Mesh Mode
  298. * 2) DSRC Mode
  299. *
  300. * Return: HTT metadata size
  301. *
  302. */
  303. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  304. struct dp_tx_msdu_info_s *msdu_info)
  305. {
  306. uint32_t *meta_data = msdu_info->meta_data;
  307. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  308. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  309. uint8_t htt_desc_size;
  310. /* Size rounded of multiple of 8 bytes */
  311. uint8_t htt_desc_size_aligned;
  312. uint8_t *hdr = NULL;
  313. /*
  314. * Metadata - HTT MSDU Extension header
  315. */
  316. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  317. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  318. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  319. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  320. meta_data[0])) {
  321. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  322. htt_desc_size_aligned)) {
  323. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  324. htt_desc_size_aligned);
  325. if (!nbuf) {
  326. /*
  327. * qdf_nbuf_realloc_headroom won't do skb_clone
  328. * as skb_realloc_headroom does. so, no free is
  329. * needed here.
  330. */
  331. DP_STATS_INC(vdev,
  332. tx_i.dropped.headroom_insufficient,
  333. 1);
  334. qdf_print(" %s[%d] skb_realloc_headroom failed",
  335. __func__, __LINE__);
  336. return 0;
  337. }
  338. }
  339. /* Fill and add HTT metaheader */
  340. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  341. if (!hdr) {
  342. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  343. "Error in filling HTT metadata");
  344. return 0;
  345. }
  346. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  347. } else if (vdev->opmode == wlan_op_mode_ocb) {
  348. /* Todo - Add support for DSRC */
  349. }
  350. return htt_desc_size_aligned;
  351. }
  352. /**
  353. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  354. * @tso_seg: TSO segment to process
  355. * @ext_desc: Pointer to MSDU extension descriptor
  356. *
  357. * Return: void
  358. */
  359. #if defined(FEATURE_TSO)
  360. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  361. void *ext_desc)
  362. {
  363. uint8_t num_frag;
  364. uint32_t tso_flags;
  365. /*
  366. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  367. * tcp_flag_mask
  368. *
  369. * Checksum enable flags are set in TCL descriptor and not in Extension
  370. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  371. */
  372. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  373. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  374. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  375. tso_seg->tso_flags.ip_len);
  376. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  377. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  378. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  379. uint32_t lo = 0;
  380. uint32_t hi = 0;
  381. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  382. (tso_seg->tso_frags[num_frag].length));
  383. qdf_dmaaddr_to_32s(
  384. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  385. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  386. tso_seg->tso_frags[num_frag].length);
  387. }
  388. return;
  389. }
  390. #else
  391. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  392. void *ext_desc)
  393. {
  394. return;
  395. }
  396. #endif
  397. #if defined(FEATURE_TSO)
  398. /**
  399. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  400. * allocated and free them
  401. *
  402. * @soc: soc handle
  403. * @free_seg: list of tso segments
  404. * @msdu_info: msdu descriptor
  405. *
  406. * Return - void
  407. */
  408. static void dp_tx_free_tso_seg_list(
  409. struct dp_soc *soc,
  410. struct qdf_tso_seg_elem_t *free_seg,
  411. struct dp_tx_msdu_info_s *msdu_info)
  412. {
  413. struct qdf_tso_seg_elem_t *next_seg;
  414. while (free_seg) {
  415. next_seg = free_seg->next;
  416. dp_tx_tso_desc_free(soc,
  417. msdu_info->tx_queue.desc_pool_id,
  418. free_seg);
  419. free_seg = next_seg;
  420. }
  421. }
  422. /**
  423. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  424. * allocated and free them
  425. *
  426. * @soc: soc handle
  427. * @free_num_seg: list of tso number segments
  428. * @msdu_info: msdu descriptor
  429. * Return - void
  430. */
  431. static void dp_tx_free_tso_num_seg_list(
  432. struct dp_soc *soc,
  433. struct qdf_tso_num_seg_elem_t *free_num_seg,
  434. struct dp_tx_msdu_info_s *msdu_info)
  435. {
  436. struct qdf_tso_num_seg_elem_t *next_num_seg;
  437. while (free_num_seg) {
  438. next_num_seg = free_num_seg->next;
  439. dp_tso_num_seg_free(soc,
  440. msdu_info->tx_queue.desc_pool_id,
  441. free_num_seg);
  442. free_num_seg = next_num_seg;
  443. }
  444. }
  445. /**
  446. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  447. * do dma unmap for each segment
  448. *
  449. * @soc: soc handle
  450. * @free_seg: list of tso segments
  451. * @num_seg_desc: tso number segment descriptor
  452. *
  453. * Return - void
  454. */
  455. static void dp_tx_unmap_tso_seg_list(
  456. struct dp_soc *soc,
  457. struct qdf_tso_seg_elem_t *free_seg,
  458. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  459. {
  460. struct qdf_tso_seg_elem_t *next_seg;
  461. if (qdf_unlikely(!num_seg_desc)) {
  462. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  463. return;
  464. }
  465. while (free_seg) {
  466. next_seg = free_seg->next;
  467. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  468. free_seg = next_seg;
  469. }
  470. }
  471. #ifdef FEATURE_TSO_STATS
  472. /**
  473. * dp_tso_get_stats_idx: Retrieve the tso packet id
  474. * @pdev - pdev handle
  475. *
  476. * Return: id
  477. */
  478. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  479. {
  480. uint32_t stats_idx;
  481. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  482. % CDP_MAX_TSO_PACKETS);
  483. return stats_idx;
  484. }
  485. #else
  486. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  487. {
  488. return 0;
  489. }
  490. #endif /* FEATURE_TSO_STATS */
  491. /**
  492. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  493. * free the tso segments descriptor and
  494. * tso num segments descriptor
  495. *
  496. * @soc: soc handle
  497. * @msdu_info: msdu descriptor
  498. * @tso_seg_unmap: flag to show if dma unmap is necessary
  499. *
  500. * Return - void
  501. */
  502. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  503. struct dp_tx_msdu_info_s *msdu_info,
  504. bool tso_seg_unmap)
  505. {
  506. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  507. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  508. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  509. tso_info->tso_num_seg_list;
  510. /* do dma unmap for each segment */
  511. if (tso_seg_unmap)
  512. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  513. /* free all tso number segment descriptor though looks only have 1 */
  514. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  515. /* free all tso segment descriptor */
  516. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  517. }
  518. /**
  519. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  520. * @vdev: virtual device handle
  521. * @msdu: network buffer
  522. * @msdu_info: meta data associated with the msdu
  523. *
  524. * Return: QDF_STATUS_SUCCESS success
  525. */
  526. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  527. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  528. {
  529. struct qdf_tso_seg_elem_t *tso_seg;
  530. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  531. struct dp_soc *soc = vdev->pdev->soc;
  532. struct dp_pdev *pdev = vdev->pdev;
  533. struct qdf_tso_info_t *tso_info;
  534. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  535. tso_info = &msdu_info->u.tso_info;
  536. tso_info->curr_seg = NULL;
  537. tso_info->tso_seg_list = NULL;
  538. tso_info->num_segs = num_seg;
  539. msdu_info->frm_type = dp_tx_frm_tso;
  540. tso_info->tso_num_seg_list = NULL;
  541. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  542. while (num_seg) {
  543. tso_seg = dp_tx_tso_desc_alloc(
  544. soc, msdu_info->tx_queue.desc_pool_id);
  545. if (tso_seg) {
  546. tso_seg->next = tso_info->tso_seg_list;
  547. tso_info->tso_seg_list = tso_seg;
  548. num_seg--;
  549. } else {
  550. dp_err_rl("Failed to alloc tso seg desc");
  551. DP_STATS_INC_PKT(vdev->pdev,
  552. tso_stats.tso_no_mem_dropped, 1,
  553. qdf_nbuf_len(msdu));
  554. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  555. return QDF_STATUS_E_NOMEM;
  556. }
  557. }
  558. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  559. tso_num_seg = dp_tso_num_seg_alloc(soc,
  560. msdu_info->tx_queue.desc_pool_id);
  561. if (tso_num_seg) {
  562. tso_num_seg->next = tso_info->tso_num_seg_list;
  563. tso_info->tso_num_seg_list = tso_num_seg;
  564. } else {
  565. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  566. __func__);
  567. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  568. return QDF_STATUS_E_NOMEM;
  569. }
  570. msdu_info->num_seg =
  571. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  572. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  573. msdu_info->num_seg);
  574. if (!(msdu_info->num_seg)) {
  575. /*
  576. * Free allocated TSO seg desc and number seg desc,
  577. * do unmap for segments if dma map has done.
  578. */
  579. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  580. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  581. return QDF_STATUS_E_INVAL;
  582. }
  583. tso_info->curr_seg = tso_info->tso_seg_list;
  584. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  585. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  586. msdu, msdu_info->num_seg);
  587. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  588. tso_info->msdu_stats_idx);
  589. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  590. return QDF_STATUS_SUCCESS;
  591. }
  592. #else
  593. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  594. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  595. {
  596. return QDF_STATUS_E_NOMEM;
  597. }
  598. #endif
  599. /**
  600. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  601. * @vdev: DP Vdev handle
  602. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  603. * @desc_pool_id: Descriptor Pool ID
  604. *
  605. * Return:
  606. */
  607. static
  608. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  609. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  610. {
  611. uint8_t i;
  612. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  613. struct dp_tx_seg_info_s *seg_info;
  614. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  615. struct dp_soc *soc = vdev->pdev->soc;
  616. /* Allocate an extension descriptor */
  617. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  618. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  619. if (!msdu_ext_desc) {
  620. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  621. return NULL;
  622. }
  623. if (msdu_info->exception_fw &&
  624. qdf_unlikely(vdev->mesh_vdev)) {
  625. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  626. &msdu_info->meta_data[0],
  627. sizeof(struct htt_tx_msdu_desc_ext2_t));
  628. qdf_atomic_inc(&soc->num_tx_exception);
  629. }
  630. switch (msdu_info->frm_type) {
  631. case dp_tx_frm_sg:
  632. case dp_tx_frm_me:
  633. case dp_tx_frm_raw:
  634. seg_info = msdu_info->u.sg_info.curr_seg;
  635. /* Update the buffer pointers in MSDU Extension Descriptor */
  636. for (i = 0; i < seg_info->frag_cnt; i++) {
  637. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  638. seg_info->frags[i].paddr_lo,
  639. seg_info->frags[i].paddr_hi,
  640. seg_info->frags[i].len);
  641. }
  642. break;
  643. case dp_tx_frm_tso:
  644. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  645. &cached_ext_desc[0]);
  646. break;
  647. default:
  648. break;
  649. }
  650. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  651. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  652. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  653. msdu_ext_desc->vaddr);
  654. return msdu_ext_desc;
  655. }
  656. /**
  657. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  658. *
  659. * @skb: skb to be traced
  660. * @msdu_id: msdu_id of the packet
  661. * @vdev_id: vdev_id of the packet
  662. *
  663. * Return: None
  664. */
  665. #ifdef DP_DISABLE_TX_PKT_TRACE
  666. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  667. uint8_t vdev_id)
  668. {
  669. }
  670. #else
  671. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  672. uint8_t vdev_id)
  673. {
  674. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  675. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  676. DPTRACE(qdf_dp_trace_ptr(skb,
  677. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  678. QDF_TRACE_DEFAULT_PDEV_ID,
  679. qdf_nbuf_data_addr(skb),
  680. sizeof(qdf_nbuf_data(skb)),
  681. msdu_id, vdev_id));
  682. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  683. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  684. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  685. msdu_id, QDF_TX));
  686. }
  687. #endif
  688. /**
  689. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  690. * @vdev: DP vdev handle
  691. * @nbuf: skb
  692. * @desc_pool_id: Descriptor pool ID
  693. * @meta_data: Metadata to the fw
  694. * @tx_exc_metadata: Handle that holds exception path metadata
  695. * Allocate and prepare Tx descriptor with msdu information.
  696. *
  697. * Return: Pointer to Tx Descriptor on success,
  698. * NULL on failure
  699. */
  700. static
  701. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  702. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  703. struct dp_tx_msdu_info_s *msdu_info,
  704. struct cdp_tx_exception_metadata *tx_exc_metadata)
  705. {
  706. uint8_t align_pad;
  707. uint8_t is_exception = 0;
  708. uint8_t htt_hdr_size;
  709. struct dp_tx_desc_s *tx_desc;
  710. struct dp_pdev *pdev = vdev->pdev;
  711. struct dp_soc *soc = pdev->soc;
  712. if (dp_tx_limit_check(vdev))
  713. return NULL;
  714. /* Allocate software Tx descriptor */
  715. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  716. if (qdf_unlikely(!tx_desc)) {
  717. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  718. return NULL;
  719. }
  720. dp_tx_outstanding_inc(pdev);
  721. /* Initialize the SW tx descriptor */
  722. tx_desc->nbuf = nbuf;
  723. tx_desc->frm_type = dp_tx_frm_std;
  724. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  725. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  726. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  727. tx_desc->vdev = vdev;
  728. tx_desc->pdev = pdev;
  729. tx_desc->msdu_ext_desc = NULL;
  730. tx_desc->pkt_offset = 0;
  731. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  732. if (qdf_unlikely(vdev->multipass_en)) {
  733. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  734. goto failure;
  735. }
  736. /*
  737. * For special modes (vdev_type == ocb or mesh), data frames should be
  738. * transmitted using varying transmit parameters (tx spec) which include
  739. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  740. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  741. * These frames are sent as exception packets to firmware.
  742. *
  743. * HW requirement is that metadata should always point to a
  744. * 8-byte aligned address. So we add alignment pad to start of buffer.
  745. * HTT Metadata should be ensured to be multiple of 8-bytes,
  746. * to get 8-byte aligned start address along with align_pad added
  747. *
  748. * |-----------------------------|
  749. * | |
  750. * |-----------------------------| <-----Buffer Pointer Address given
  751. * | | ^ in HW descriptor (aligned)
  752. * | HTT Metadata | |
  753. * | | |
  754. * | | | Packet Offset given in descriptor
  755. * | | |
  756. * |-----------------------------| |
  757. * | Alignment Pad | v
  758. * |-----------------------------| <----- Actual buffer start address
  759. * | SKB Data | (Unaligned)
  760. * | |
  761. * | |
  762. * | |
  763. * | |
  764. * | |
  765. * |-----------------------------|
  766. */
  767. if (qdf_unlikely((msdu_info->exception_fw)) ||
  768. (vdev->opmode == wlan_op_mode_ocb) ||
  769. (tx_exc_metadata &&
  770. tx_exc_metadata->is_tx_sniffer)) {
  771. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  772. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  773. DP_STATS_INC(vdev,
  774. tx_i.dropped.headroom_insufficient, 1);
  775. goto failure;
  776. }
  777. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  779. "qdf_nbuf_push_head failed");
  780. goto failure;
  781. }
  782. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  783. msdu_info);
  784. if (htt_hdr_size == 0)
  785. goto failure;
  786. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  787. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  788. is_exception = 1;
  789. }
  790. #if !TQM_BYPASS_WAR
  791. if (is_exception || tx_exc_metadata)
  792. #endif
  793. {
  794. /* Temporary WAR due to TQM VP issues */
  795. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  796. qdf_atomic_inc(&soc->num_tx_exception);
  797. }
  798. return tx_desc;
  799. failure:
  800. dp_tx_desc_release(tx_desc, desc_pool_id);
  801. return NULL;
  802. }
  803. /**
  804. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  805. * @vdev: DP vdev handle
  806. * @nbuf: skb
  807. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  808. * @desc_pool_id : Descriptor Pool ID
  809. *
  810. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  811. * information. For frames wth fragments, allocate and prepare
  812. * an MSDU extension descriptor
  813. *
  814. * Return: Pointer to Tx Descriptor on success,
  815. * NULL on failure
  816. */
  817. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  818. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  819. uint8_t desc_pool_id)
  820. {
  821. struct dp_tx_desc_s *tx_desc;
  822. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  823. struct dp_pdev *pdev = vdev->pdev;
  824. struct dp_soc *soc = pdev->soc;
  825. if (dp_tx_limit_check(vdev))
  826. return NULL;
  827. /* Allocate software Tx descriptor */
  828. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  829. if (!tx_desc) {
  830. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  831. return NULL;
  832. }
  833. dp_tx_outstanding_inc(pdev);
  834. /* Initialize the SW tx descriptor */
  835. tx_desc->nbuf = nbuf;
  836. tx_desc->frm_type = msdu_info->frm_type;
  837. tx_desc->tx_encap_type = vdev->tx_encap_type;
  838. tx_desc->vdev = vdev;
  839. tx_desc->pdev = pdev;
  840. tx_desc->pkt_offset = 0;
  841. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  842. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  843. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  844. /* Handle scattered frames - TSO/SG/ME */
  845. /* Allocate and prepare an extension descriptor for scattered frames */
  846. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  847. if (!msdu_ext_desc) {
  848. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  849. "%s Tx Extension Descriptor Alloc Fail",
  850. __func__);
  851. goto failure;
  852. }
  853. #if TQM_BYPASS_WAR
  854. /* Temporary WAR due to TQM VP issues */
  855. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  856. qdf_atomic_inc(&soc->num_tx_exception);
  857. #endif
  858. if (qdf_unlikely(msdu_info->exception_fw))
  859. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  860. tx_desc->msdu_ext_desc = msdu_ext_desc;
  861. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  862. return tx_desc;
  863. failure:
  864. dp_tx_desc_release(tx_desc, desc_pool_id);
  865. return NULL;
  866. }
  867. /**
  868. * dp_tx_prepare_raw() - Prepare RAW packet TX
  869. * @vdev: DP vdev handle
  870. * @nbuf: buffer pointer
  871. * @seg_info: Pointer to Segment info Descriptor to be prepared
  872. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  873. * descriptor
  874. *
  875. * Return:
  876. */
  877. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  878. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  879. {
  880. qdf_nbuf_t curr_nbuf = NULL;
  881. uint16_t total_len = 0;
  882. qdf_dma_addr_t paddr;
  883. int32_t i;
  884. int32_t mapped_buf_num = 0;
  885. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  886. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  887. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  888. /* Continue only if frames are of DATA type */
  889. if (!DP_FRAME_IS_DATA(qos_wh)) {
  890. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  891. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  892. "Pkt. recd is of not data type");
  893. goto error;
  894. }
  895. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  896. if (vdev->raw_mode_war &&
  897. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  898. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  899. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  900. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  901. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  902. if (QDF_STATUS_SUCCESS !=
  903. qdf_nbuf_map_nbytes_single(vdev->osdev,
  904. curr_nbuf,
  905. QDF_DMA_TO_DEVICE,
  906. curr_nbuf->len)) {
  907. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  908. "%s dma map error ", __func__);
  909. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  910. mapped_buf_num = i;
  911. goto error;
  912. }
  913. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  914. seg_info->frags[i].paddr_lo = paddr;
  915. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  916. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  917. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  918. total_len += qdf_nbuf_len(curr_nbuf);
  919. }
  920. seg_info->frag_cnt = i;
  921. seg_info->total_len = total_len;
  922. seg_info->next = NULL;
  923. sg_info->curr_seg = seg_info;
  924. msdu_info->frm_type = dp_tx_frm_raw;
  925. msdu_info->num_seg = 1;
  926. return nbuf;
  927. error:
  928. i = 0;
  929. while (nbuf) {
  930. curr_nbuf = nbuf;
  931. if (i < mapped_buf_num) {
  932. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  933. QDF_DMA_TO_DEVICE,
  934. curr_nbuf->len);
  935. i++;
  936. }
  937. nbuf = qdf_nbuf_next(nbuf);
  938. qdf_nbuf_free(curr_nbuf);
  939. }
  940. return NULL;
  941. }
  942. /**
  943. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  944. * @soc: DP soc handle
  945. * @nbuf: Buffer pointer
  946. *
  947. * unmap the chain of nbufs that belong to this RAW frame.
  948. *
  949. * Return: None
  950. */
  951. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  952. qdf_nbuf_t nbuf)
  953. {
  954. qdf_nbuf_t cur_nbuf = nbuf;
  955. do {
  956. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  957. QDF_DMA_TO_DEVICE,
  958. cur_nbuf->len);
  959. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  960. } while (cur_nbuf);
  961. }
  962. #ifdef VDEV_PEER_PROTOCOL_COUNT
  963. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  964. { \
  965. qdf_nbuf_t nbuf_local; \
  966. struct dp_vdev *vdev_local = vdev_hdl; \
  967. do { \
  968. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  969. break; \
  970. nbuf_local = nbuf; \
  971. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  972. htt_cmn_pkt_type_raw)) \
  973. break; \
  974. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  975. break; \
  976. else if (qdf_nbuf_is_tso((nbuf_local))) \
  977. break; \
  978. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  979. (nbuf_local), \
  980. NULL, 1, 0); \
  981. } while (0); \
  982. }
  983. #else
  984. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  985. #endif
  986. /**
  987. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  988. * @soc: DP Soc Handle
  989. * @vdev: DP vdev handle
  990. * @tx_desc: Tx Descriptor Handle
  991. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  992. * @fw_metadata: Metadata to send to Target Firmware along with frame
  993. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  994. * @tx_exc_metadata: Handle that holds exception path meta data
  995. *
  996. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  997. * from software Tx descriptor
  998. *
  999. * Return: QDF_STATUS_SUCCESS: success
  1000. * QDF_STATUS_E_RESOURCES: Error return
  1001. */
  1002. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1003. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  1004. uint16_t fw_metadata, uint8_t ring_id,
  1005. struct cdp_tx_exception_metadata
  1006. *tx_exc_metadata)
  1007. {
  1008. uint8_t type;
  1009. void *hal_tx_desc;
  1010. uint32_t *hal_tx_desc_cached;
  1011. /*
  1012. * Setting it initialization statically here to avoid
  1013. * a memset call jump with qdf_mem_set call
  1014. */
  1015. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1016. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1017. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1018. tx_exc_metadata->sec_type : vdev->sec_type);
  1019. /* Return Buffer Manager ID */
  1020. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1021. hal_ring_handle_t hal_ring_hdl = NULL;
  1022. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1023. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1024. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1025. return QDF_STATUS_E_RESOURCES;
  1026. }
  1027. hal_tx_desc_cached = (void *) cached_desc;
  1028. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1029. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1030. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1031. tx_desc->dma_addr = tx_desc->msdu_ext_desc->paddr;
  1032. } else {
  1033. tx_desc->length = qdf_nbuf_len(tx_desc->nbuf) -
  1034. tx_desc->pkt_offset;
  1035. type = HAL_TX_BUF_TYPE_BUFFER;
  1036. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1037. }
  1038. qdf_assert_always(tx_desc->dma_addr);
  1039. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1040. tx_desc->dma_addr, bm_id, tx_desc->id,
  1041. type);
  1042. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1043. vdev->lmac_id);
  1044. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1045. vdev->search_type);
  1046. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1047. vdev->bss_ast_idx);
  1048. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1049. vdev->dscp_tid_map_id);
  1050. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1051. sec_type_map[sec_type]);
  1052. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1053. (vdev->bss_ast_hash & 0xF));
  1054. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1055. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1056. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1057. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1058. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1059. vdev->hal_desc_addr_search_flags);
  1060. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1061. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1062. /* verify checksum offload configuration*/
  1063. if (vdev->csum_enabled &&
  1064. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1065. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1066. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1067. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1068. }
  1069. if (tid != HTT_TX_EXT_TID_INVALID)
  1070. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1071. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1072. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1073. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1074. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1075. soc->wlan_cfg_ctx)))
  1076. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1077. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1078. tx_desc->length, type, (uint64_t)tx_desc->dma_addr,
  1079. tx_desc->pkt_offset, tx_desc->id);
  1080. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1081. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1082. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1083. "%s %d : HAL RING Access Failed -- %pK",
  1084. __func__, __LINE__, hal_ring_hdl);
  1085. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1086. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1087. return status;
  1088. }
  1089. /* Sync cached descriptor with HW */
  1090. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1091. if (qdf_unlikely(!hal_tx_desc)) {
  1092. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1093. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1094. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1095. goto ring_access_fail;
  1096. }
  1097. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1098. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1099. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1100. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1101. status = QDF_STATUS_SUCCESS;
  1102. ring_access_fail:
  1103. if (hif_pm_runtime_get(soc->hif_handle,
  1104. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1105. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1106. hif_pm_runtime_put(soc->hif_handle,
  1107. RTPM_ID_DW_TX_HW_ENQUEUE);
  1108. } else {
  1109. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1110. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1111. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1112. }
  1113. return status;
  1114. }
  1115. /**
  1116. * dp_cce_classify() - Classify the frame based on CCE rules
  1117. * @vdev: DP vdev handle
  1118. * @nbuf: skb
  1119. *
  1120. * Classify frames based on CCE rules
  1121. * Return: bool( true if classified,
  1122. * else false)
  1123. */
  1124. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1125. {
  1126. qdf_ether_header_t *eh = NULL;
  1127. uint16_t ether_type;
  1128. qdf_llc_t *llcHdr;
  1129. qdf_nbuf_t nbuf_clone = NULL;
  1130. qdf_dot3_qosframe_t *qos_wh = NULL;
  1131. /* for mesh packets don't do any classification */
  1132. if (qdf_unlikely(vdev->mesh_vdev))
  1133. return false;
  1134. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1135. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1136. ether_type = eh->ether_type;
  1137. llcHdr = (qdf_llc_t *)(nbuf->data +
  1138. sizeof(qdf_ether_header_t));
  1139. } else {
  1140. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1141. /* For encrypted packets don't do any classification */
  1142. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1143. return false;
  1144. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1145. if (qdf_unlikely(
  1146. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1147. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1148. ether_type = *(uint16_t *)(nbuf->data
  1149. + QDF_IEEE80211_4ADDR_HDR_LEN
  1150. + sizeof(qdf_llc_t)
  1151. - sizeof(ether_type));
  1152. llcHdr = (qdf_llc_t *)(nbuf->data +
  1153. QDF_IEEE80211_4ADDR_HDR_LEN);
  1154. } else {
  1155. ether_type = *(uint16_t *)(nbuf->data
  1156. + QDF_IEEE80211_3ADDR_HDR_LEN
  1157. + sizeof(qdf_llc_t)
  1158. - sizeof(ether_type));
  1159. llcHdr = (qdf_llc_t *)(nbuf->data +
  1160. QDF_IEEE80211_3ADDR_HDR_LEN);
  1161. }
  1162. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1163. && (ether_type ==
  1164. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1165. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1166. return true;
  1167. }
  1168. }
  1169. return false;
  1170. }
  1171. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1172. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1173. sizeof(*llcHdr));
  1174. nbuf_clone = qdf_nbuf_clone(nbuf);
  1175. if (qdf_unlikely(nbuf_clone)) {
  1176. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1177. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1178. qdf_nbuf_pull_head(nbuf_clone,
  1179. sizeof(qdf_net_vlanhdr_t));
  1180. }
  1181. }
  1182. } else {
  1183. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1184. nbuf_clone = qdf_nbuf_clone(nbuf);
  1185. if (qdf_unlikely(nbuf_clone)) {
  1186. qdf_nbuf_pull_head(nbuf_clone,
  1187. sizeof(qdf_net_vlanhdr_t));
  1188. }
  1189. }
  1190. }
  1191. if (qdf_unlikely(nbuf_clone))
  1192. nbuf = nbuf_clone;
  1193. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1194. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1195. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1196. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1197. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1198. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1199. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1200. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1201. if (qdf_unlikely(nbuf_clone))
  1202. qdf_nbuf_free(nbuf_clone);
  1203. return true;
  1204. }
  1205. if (qdf_unlikely(nbuf_clone))
  1206. qdf_nbuf_free(nbuf_clone);
  1207. return false;
  1208. }
  1209. /**
  1210. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1211. * @vdev: DP vdev handle
  1212. * @nbuf: skb
  1213. *
  1214. * Extract the DSCP or PCP information from frame and map into TID value.
  1215. *
  1216. * Return: void
  1217. */
  1218. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1219. struct dp_tx_msdu_info_s *msdu_info)
  1220. {
  1221. uint8_t tos = 0, dscp_tid_override = 0;
  1222. uint8_t *hdr_ptr, *L3datap;
  1223. uint8_t is_mcast = 0;
  1224. qdf_ether_header_t *eh = NULL;
  1225. qdf_ethervlan_header_t *evh = NULL;
  1226. uint16_t ether_type;
  1227. qdf_llc_t *llcHdr;
  1228. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1229. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1230. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1231. eh = (qdf_ether_header_t *)nbuf->data;
  1232. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1233. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1234. } else {
  1235. qdf_dot3_qosframe_t *qos_wh =
  1236. (qdf_dot3_qosframe_t *) nbuf->data;
  1237. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1238. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1239. return;
  1240. }
  1241. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1242. ether_type = eh->ether_type;
  1243. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1244. /*
  1245. * Check if packet is dot3 or eth2 type.
  1246. */
  1247. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1248. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1249. sizeof(*llcHdr));
  1250. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1251. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1252. sizeof(*llcHdr);
  1253. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1254. + sizeof(*llcHdr) +
  1255. sizeof(qdf_net_vlanhdr_t));
  1256. } else {
  1257. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1258. sizeof(*llcHdr);
  1259. }
  1260. } else {
  1261. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1262. evh = (qdf_ethervlan_header_t *) eh;
  1263. ether_type = evh->ether_type;
  1264. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1265. }
  1266. }
  1267. /*
  1268. * Find priority from IP TOS DSCP field
  1269. */
  1270. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1271. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1272. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1273. /* Only for unicast frames */
  1274. if (!is_mcast) {
  1275. /* send it on VO queue */
  1276. msdu_info->tid = DP_VO_TID;
  1277. }
  1278. } else {
  1279. /*
  1280. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1281. * from TOS byte.
  1282. */
  1283. tos = ip->ip_tos;
  1284. dscp_tid_override = 1;
  1285. }
  1286. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1287. /* TODO
  1288. * use flowlabel
  1289. *igmpmld cases to be handled in phase 2
  1290. */
  1291. unsigned long ver_pri_flowlabel;
  1292. unsigned long pri;
  1293. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1294. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1295. DP_IPV6_PRIORITY_SHIFT;
  1296. tos = pri;
  1297. dscp_tid_override = 1;
  1298. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1299. msdu_info->tid = DP_VO_TID;
  1300. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1301. /* Only for unicast frames */
  1302. if (!is_mcast) {
  1303. /* send ucast arp on VO queue */
  1304. msdu_info->tid = DP_VO_TID;
  1305. }
  1306. }
  1307. /*
  1308. * Assign all MCAST packets to BE
  1309. */
  1310. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1311. if (is_mcast) {
  1312. tos = 0;
  1313. dscp_tid_override = 1;
  1314. }
  1315. }
  1316. if (dscp_tid_override == 1) {
  1317. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1318. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1319. }
  1320. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1321. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1322. return;
  1323. }
  1324. /**
  1325. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1326. * @vdev: DP vdev handle
  1327. * @nbuf: skb
  1328. *
  1329. * Software based TID classification is required when more than 2 DSCP-TID
  1330. * mapping tables are needed.
  1331. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1332. *
  1333. * Return: void
  1334. */
  1335. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1336. struct dp_tx_msdu_info_s *msdu_info)
  1337. {
  1338. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1339. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1340. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1341. return;
  1342. /* for mesh packets don't do any classification */
  1343. if (qdf_unlikely(vdev->mesh_vdev))
  1344. return;
  1345. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1346. }
  1347. #ifdef FEATURE_WLAN_TDLS
  1348. /**
  1349. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1350. * @tx_desc: TX descriptor
  1351. *
  1352. * Return: None
  1353. */
  1354. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1355. {
  1356. if (tx_desc->vdev) {
  1357. if (tx_desc->vdev->is_tdls_frame) {
  1358. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1359. tx_desc->vdev->is_tdls_frame = false;
  1360. }
  1361. }
  1362. }
  1363. /**
  1364. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1365. * @soc: dp_soc handle
  1366. * @tx_desc: TX descriptor
  1367. * @vdev: datapath vdev handle
  1368. *
  1369. * Return: None
  1370. */
  1371. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1372. struct dp_tx_desc_s *tx_desc,
  1373. struct dp_vdev *vdev)
  1374. {
  1375. struct hal_tx_completion_status ts = {0};
  1376. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1377. if (qdf_unlikely(!vdev)) {
  1378. dp_err_rl("vdev is null!");
  1379. goto error;
  1380. }
  1381. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1382. if (vdev->tx_non_std_data_callback.func) {
  1383. qdf_nbuf_set_next(nbuf, NULL);
  1384. vdev->tx_non_std_data_callback.func(
  1385. vdev->tx_non_std_data_callback.ctxt,
  1386. nbuf, ts.status);
  1387. return;
  1388. } else {
  1389. dp_err_rl("callback func is null");
  1390. }
  1391. error:
  1392. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1393. qdf_nbuf_free(nbuf);
  1394. }
  1395. /**
  1396. * dp_tx_msdu_single_map() - do nbuf map
  1397. * @vdev: DP vdev handle
  1398. * @tx_desc: DP TX descriptor pointer
  1399. * @nbuf: skb pointer
  1400. *
  1401. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1402. * operation done in other component.
  1403. *
  1404. * Return: QDF_STATUS
  1405. */
  1406. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1407. struct dp_tx_desc_s *tx_desc,
  1408. qdf_nbuf_t nbuf)
  1409. {
  1410. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1411. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1412. nbuf,
  1413. QDF_DMA_TO_DEVICE,
  1414. nbuf->len);
  1415. else
  1416. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1417. QDF_DMA_TO_DEVICE);
  1418. }
  1419. #else
  1420. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1421. {
  1422. }
  1423. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1424. struct dp_tx_desc_s *tx_desc,
  1425. struct dp_vdev *vdev)
  1426. {
  1427. }
  1428. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1429. struct dp_tx_desc_s *tx_desc,
  1430. qdf_nbuf_t nbuf)
  1431. {
  1432. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1433. nbuf,
  1434. QDF_DMA_TO_DEVICE,
  1435. nbuf->len);
  1436. }
  1437. #endif
  1438. /**
  1439. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1440. * @vdev: DP vdev handle
  1441. * @nbuf: skb
  1442. *
  1443. * Return: 1 if frame needs to be dropped else 0
  1444. */
  1445. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1446. {
  1447. struct dp_pdev *pdev = NULL;
  1448. struct dp_ast_entry *src_ast_entry = NULL;
  1449. struct dp_ast_entry *dst_ast_entry = NULL;
  1450. struct dp_soc *soc = NULL;
  1451. qdf_assert(vdev);
  1452. pdev = vdev->pdev;
  1453. qdf_assert(pdev);
  1454. soc = pdev->soc;
  1455. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1456. (soc, dstmac, vdev->pdev->pdev_id);
  1457. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1458. (soc, srcmac, vdev->pdev->pdev_id);
  1459. if (dst_ast_entry && src_ast_entry) {
  1460. if (dst_ast_entry->peer->peer_id ==
  1461. src_ast_entry->peer->peer_id)
  1462. return 1;
  1463. }
  1464. return 0;
  1465. }
  1466. /**
  1467. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1468. * @vdev: DP vdev handle
  1469. * @nbuf: skb
  1470. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1471. * @meta_data: Metadata to the fw
  1472. * @tx_q: Tx queue to be used for this Tx frame
  1473. * @peer_id: peer_id of the peer in case of NAWDS frames
  1474. * @tx_exc_metadata: Handle that holds exception path metadata
  1475. *
  1476. * Return: NULL on success,
  1477. * nbuf when it fails to send
  1478. */
  1479. qdf_nbuf_t
  1480. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1481. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1482. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1483. {
  1484. struct dp_pdev *pdev = vdev->pdev;
  1485. struct dp_soc *soc = pdev->soc;
  1486. struct dp_tx_desc_s *tx_desc;
  1487. QDF_STATUS status;
  1488. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1489. uint16_t htt_tcl_metadata = 0;
  1490. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1491. uint8_t tid = msdu_info->tid;
  1492. struct cdp_tid_tx_stats *tid_stats = NULL;
  1493. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1494. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1495. msdu_info, tx_exc_metadata);
  1496. if (!tx_desc) {
  1497. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1498. vdev, tx_q->desc_pool_id);
  1499. drop_code = TX_DESC_ERR;
  1500. goto fail_return;
  1501. }
  1502. if (qdf_unlikely(soc->cce_disable)) {
  1503. if (dp_cce_classify(vdev, nbuf) == true) {
  1504. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1505. tid = DP_VO_TID;
  1506. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1507. }
  1508. }
  1509. dp_tx_update_tdls_flags(tx_desc);
  1510. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1511. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1512. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1513. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1514. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1515. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1516. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1517. peer_id);
  1518. } else
  1519. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1520. if (msdu_info->exception_fw)
  1521. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1522. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1523. !pdev->enhanced_stats_en);
  1524. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1525. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1526. /* Handle failure */
  1527. dp_err("qdf_nbuf_map failed");
  1528. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1529. drop_code = TX_DMA_MAP_ERR;
  1530. goto release_desc;
  1531. }
  1532. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1533. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1534. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1535. if (status != QDF_STATUS_SUCCESS) {
  1536. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1537. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1538. __func__, tx_desc, tx_q->ring_id);
  1539. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1540. QDF_DMA_TO_DEVICE,
  1541. nbuf->len);
  1542. drop_code = TX_HW_ENQUEUE;
  1543. goto release_desc;
  1544. }
  1545. return NULL;
  1546. release_desc:
  1547. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1548. fail_return:
  1549. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1550. tid_stats = &pdev->stats.tid_stats.
  1551. tid_tx_stats[tx_q->ring_id][tid];
  1552. tid_stats->swdrop_cnt[drop_code]++;
  1553. return nbuf;
  1554. }
  1555. /**
  1556. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1557. * @vdev: DP vdev handle
  1558. * @nbuf: skb
  1559. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1560. *
  1561. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1562. *
  1563. * Return: NULL on success,
  1564. * nbuf when it fails to send
  1565. */
  1566. #if QDF_LOCK_STATS
  1567. noinline
  1568. #else
  1569. #endif
  1570. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1571. struct dp_tx_msdu_info_s *msdu_info)
  1572. {
  1573. uint32_t i;
  1574. struct dp_pdev *pdev = vdev->pdev;
  1575. struct dp_soc *soc = pdev->soc;
  1576. struct dp_tx_desc_s *tx_desc;
  1577. bool is_cce_classified = false;
  1578. QDF_STATUS status;
  1579. uint16_t htt_tcl_metadata = 0;
  1580. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1581. struct cdp_tid_tx_stats *tid_stats = NULL;
  1582. if (qdf_unlikely(soc->cce_disable)) {
  1583. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1584. if (is_cce_classified) {
  1585. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1586. msdu_info->tid = DP_VO_TID;
  1587. }
  1588. }
  1589. if (msdu_info->frm_type == dp_tx_frm_me)
  1590. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1591. i = 0;
  1592. /* Print statement to track i and num_seg */
  1593. /*
  1594. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1595. * descriptors using information in msdu_info
  1596. */
  1597. while (i < msdu_info->num_seg) {
  1598. /*
  1599. * Setup Tx descriptor for an MSDU, and MSDU extension
  1600. * descriptor
  1601. */
  1602. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1603. tx_q->desc_pool_id);
  1604. if (!tx_desc) {
  1605. if (msdu_info->frm_type == dp_tx_frm_me) {
  1606. dp_tx_me_free_buf(pdev,
  1607. (void *)(msdu_info->u.sg_info
  1608. .curr_seg->frags[0].vaddr));
  1609. i++;
  1610. continue;
  1611. }
  1612. goto done;
  1613. }
  1614. if (msdu_info->frm_type == dp_tx_frm_me) {
  1615. tx_desc->me_buffer =
  1616. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1617. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1618. }
  1619. if (is_cce_classified)
  1620. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1621. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1622. if (msdu_info->exception_fw) {
  1623. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1624. }
  1625. /*
  1626. * Enqueue the Tx MSDU descriptor to HW for transmit
  1627. */
  1628. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1629. htt_tcl_metadata, tx_q->ring_id, NULL);
  1630. if (status != QDF_STATUS_SUCCESS) {
  1631. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1632. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1633. __func__, tx_desc, tx_q->ring_id);
  1634. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1635. tid_stats = &pdev->stats.tid_stats.
  1636. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1637. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1638. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1639. if (msdu_info->frm_type == dp_tx_frm_me) {
  1640. i++;
  1641. continue;
  1642. }
  1643. goto done;
  1644. }
  1645. /*
  1646. * TODO
  1647. * if tso_info structure can be modified to have curr_seg
  1648. * as first element, following 2 blocks of code (for TSO and SG)
  1649. * can be combined into 1
  1650. */
  1651. /*
  1652. * For frames with multiple segments (TSO, ME), jump to next
  1653. * segment.
  1654. */
  1655. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1656. if (msdu_info->u.tso_info.curr_seg->next) {
  1657. msdu_info->u.tso_info.curr_seg =
  1658. msdu_info->u.tso_info.curr_seg->next;
  1659. /*
  1660. * If this is a jumbo nbuf, then increment the number of
  1661. * nbuf users for each additional segment of the msdu.
  1662. * This will ensure that the skb is freed only after
  1663. * receiving tx completion for all segments of an nbuf
  1664. */
  1665. qdf_nbuf_inc_users(nbuf);
  1666. /* Check with MCL if this is needed */
  1667. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1668. }
  1669. }
  1670. /*
  1671. * For Multicast-Unicast converted packets,
  1672. * each converted frame (for a client) is represented as
  1673. * 1 segment
  1674. */
  1675. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1676. (msdu_info->frm_type == dp_tx_frm_me)) {
  1677. if (msdu_info->u.sg_info.curr_seg->next) {
  1678. msdu_info->u.sg_info.curr_seg =
  1679. msdu_info->u.sg_info.curr_seg->next;
  1680. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1681. }
  1682. }
  1683. i++;
  1684. }
  1685. nbuf = NULL;
  1686. done:
  1687. return nbuf;
  1688. }
  1689. /**
  1690. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1691. * for SG frames
  1692. * @vdev: DP vdev handle
  1693. * @nbuf: skb
  1694. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1695. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1696. *
  1697. * Return: NULL on success,
  1698. * nbuf when it fails to send
  1699. */
  1700. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1701. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1702. {
  1703. uint32_t cur_frag, nr_frags;
  1704. qdf_dma_addr_t paddr;
  1705. struct dp_tx_sg_info_s *sg_info;
  1706. sg_info = &msdu_info->u.sg_info;
  1707. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1708. if (QDF_STATUS_SUCCESS !=
  1709. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  1710. QDF_DMA_TO_DEVICE, nbuf->len)) {
  1711. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1712. "dma map error");
  1713. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1714. qdf_nbuf_free(nbuf);
  1715. return NULL;
  1716. }
  1717. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  1718. seg_info->frags[0].paddr_lo = paddr;
  1719. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1720. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1721. seg_info->frags[0].vaddr = (void *) nbuf;
  1722. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1723. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1724. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1725. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1726. "frag dma map error");
  1727. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1728. qdf_nbuf_free(nbuf);
  1729. return NULL;
  1730. }
  1731. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  1732. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1733. seg_info->frags[cur_frag + 1].paddr_hi =
  1734. ((uint64_t) paddr) >> 32;
  1735. seg_info->frags[cur_frag + 1].len =
  1736. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1737. }
  1738. seg_info->frag_cnt = (cur_frag + 1);
  1739. seg_info->total_len = qdf_nbuf_len(nbuf);
  1740. seg_info->next = NULL;
  1741. sg_info->curr_seg = seg_info;
  1742. msdu_info->frm_type = dp_tx_frm_sg;
  1743. msdu_info->num_seg = 1;
  1744. return nbuf;
  1745. }
  1746. /**
  1747. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1748. * @vdev: DP vdev handle
  1749. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1750. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1751. *
  1752. * Return: NULL on failure,
  1753. * nbuf when extracted successfully
  1754. */
  1755. static
  1756. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1757. struct dp_tx_msdu_info_s *msdu_info,
  1758. uint16_t ppdu_cookie)
  1759. {
  1760. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1761. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1762. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1763. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1764. (msdu_info->meta_data[5], 1);
  1765. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1766. (msdu_info->meta_data[5], 1);
  1767. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1768. (msdu_info->meta_data[6], ppdu_cookie);
  1769. msdu_info->exception_fw = 1;
  1770. msdu_info->is_tx_sniffer = 1;
  1771. }
  1772. #ifdef MESH_MODE_SUPPORT
  1773. /**
  1774. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1775. and prepare msdu_info for mesh frames.
  1776. * @vdev: DP vdev handle
  1777. * @nbuf: skb
  1778. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1779. *
  1780. * Return: NULL on failure,
  1781. * nbuf when extracted successfully
  1782. */
  1783. static
  1784. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1785. struct dp_tx_msdu_info_s *msdu_info)
  1786. {
  1787. struct meta_hdr_s *mhdr;
  1788. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1789. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1790. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1791. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1792. msdu_info->exception_fw = 0;
  1793. goto remove_meta_hdr;
  1794. }
  1795. msdu_info->exception_fw = 1;
  1796. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1797. meta_data->host_tx_desc_pool = 1;
  1798. meta_data->update_peer_cache = 1;
  1799. meta_data->learning_frame = 1;
  1800. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1801. meta_data->power = mhdr->power;
  1802. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1803. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1804. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1805. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1806. meta_data->dyn_bw = 1;
  1807. meta_data->valid_pwr = 1;
  1808. meta_data->valid_mcs_mask = 1;
  1809. meta_data->valid_nss_mask = 1;
  1810. meta_data->valid_preamble_type = 1;
  1811. meta_data->valid_retries = 1;
  1812. meta_data->valid_bw_info = 1;
  1813. }
  1814. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1815. meta_data->encrypt_type = 0;
  1816. meta_data->valid_encrypt_type = 1;
  1817. meta_data->learning_frame = 0;
  1818. }
  1819. meta_data->valid_key_flags = 1;
  1820. meta_data->key_flags = (mhdr->keyix & 0x3);
  1821. remove_meta_hdr:
  1822. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1823. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1824. "qdf_nbuf_pull_head failed");
  1825. qdf_nbuf_free(nbuf);
  1826. return NULL;
  1827. }
  1828. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1829. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1830. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1831. " tid %d to_fw %d",
  1832. __func__, msdu_info->meta_data[0],
  1833. msdu_info->meta_data[1],
  1834. msdu_info->meta_data[2],
  1835. msdu_info->meta_data[3],
  1836. msdu_info->meta_data[4],
  1837. msdu_info->meta_data[5],
  1838. msdu_info->tid, msdu_info->exception_fw);
  1839. return nbuf;
  1840. }
  1841. #else
  1842. static
  1843. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1844. struct dp_tx_msdu_info_s *msdu_info)
  1845. {
  1846. return nbuf;
  1847. }
  1848. #endif
  1849. /**
  1850. * dp_check_exc_metadata() - Checks if parameters are valid
  1851. * @tx_exc - holds all exception path parameters
  1852. *
  1853. * Returns true when all the parameters are valid else false
  1854. *
  1855. */
  1856. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1857. {
  1858. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1859. HTT_INVALID_TID);
  1860. bool invalid_encap_type =
  1861. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1862. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1863. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1864. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1865. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1866. tx_exc->ppdu_cookie == 0);
  1867. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1868. invalid_cookie) {
  1869. return false;
  1870. }
  1871. return true;
  1872. }
  1873. /**
  1874. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1875. * @soc: DP soc handle
  1876. * @vdev_id: id of DP vdev handle
  1877. * @nbuf: skb
  1878. * @tx_exc_metadata: Handle that holds exception path meta data
  1879. *
  1880. * Entry point for Core Tx layer (DP_TX) invoked from
  1881. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1882. *
  1883. * Return: NULL on success,
  1884. * nbuf when it fails to send
  1885. */
  1886. qdf_nbuf_t
  1887. dp_tx_send_exception(struct cdp_soc_t *soc, uint8_t vdev_id, qdf_nbuf_t nbuf,
  1888. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1889. {
  1890. qdf_ether_header_t *eh = NULL;
  1891. struct dp_tx_msdu_info_s msdu_info;
  1892. struct dp_vdev *vdev =
  1893. dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  1894. vdev_id);
  1895. if (qdf_unlikely(!vdev))
  1896. goto fail;
  1897. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1898. if (!tx_exc_metadata)
  1899. goto fail;
  1900. msdu_info.tid = tx_exc_metadata->tid;
  1901. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1902. dp_verbose_debug("skb %pM", nbuf->data);
  1903. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1904. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1905. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1906. "Invalid parameters in exception path");
  1907. goto fail;
  1908. }
  1909. /* Basic sanity checks for unsupported packets */
  1910. /* MESH mode */
  1911. if (qdf_unlikely(vdev->mesh_vdev)) {
  1912. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1913. "Mesh mode is not supported in exception path");
  1914. goto fail;
  1915. }
  1916. /* TSO or SG */
  1917. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1918. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1919. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1920. "TSO and SG are not supported in exception path");
  1921. goto fail;
  1922. }
  1923. /* RAW */
  1924. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1925. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1926. "Raw frame is not supported in exception path");
  1927. goto fail;
  1928. }
  1929. /* Mcast enhancement*/
  1930. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1931. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1932. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1933. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1934. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1935. }
  1936. }
  1937. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1938. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1939. qdf_nbuf_len(nbuf));
  1940. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1941. tx_exc_metadata->ppdu_cookie);
  1942. }
  1943. /*
  1944. * Get HW Queue to use for this frame.
  1945. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1946. * dedicated for data and 1 for command.
  1947. * "queue_id" maps to one hardware ring.
  1948. * With each ring, we also associate a unique Tx descriptor pool
  1949. * to minimize lock contention for these resources.
  1950. */
  1951. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1952. /*
  1953. * Check exception descriptors
  1954. */
  1955. if (dp_tx_exception_limit_check(vdev))
  1956. goto fail;
  1957. /* Single linear frame */
  1958. /*
  1959. * If nbuf is a simple linear frame, use send_single function to
  1960. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1961. * SRNG. There is no need to setup a MSDU extension descriptor.
  1962. */
  1963. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1964. tx_exc_metadata->peer_id, tx_exc_metadata);
  1965. return nbuf;
  1966. fail:
  1967. dp_verbose_debug("pkt send failed");
  1968. return nbuf;
  1969. }
  1970. /**
  1971. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1972. * @soc: DP soc handle
  1973. * @vdev_id: DP vdev handle
  1974. * @nbuf: skb
  1975. *
  1976. * Entry point for Core Tx layer (DP_TX) invoked from
  1977. * hard_start_xmit in OSIF/HDD
  1978. *
  1979. * Return: NULL on success,
  1980. * nbuf when it fails to send
  1981. */
  1982. #ifdef MESH_MODE_SUPPORT
  1983. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  1984. qdf_nbuf_t nbuf)
  1985. {
  1986. struct meta_hdr_s *mhdr;
  1987. qdf_nbuf_t nbuf_mesh = NULL;
  1988. qdf_nbuf_t nbuf_clone = NULL;
  1989. struct dp_vdev *vdev;
  1990. uint8_t no_enc_frame = 0;
  1991. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1992. if (!nbuf_mesh) {
  1993. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1994. "qdf_nbuf_unshare failed");
  1995. return nbuf;
  1996. }
  1997. vdev = dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  1998. vdev_id);
  1999. if (!vdev) {
  2000. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2001. "vdev is NULL for vdev_id %d", vdev_id);
  2002. return nbuf;
  2003. }
  2004. nbuf = nbuf_mesh;
  2005. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2006. if ((vdev->sec_type != cdp_sec_type_none) &&
  2007. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2008. no_enc_frame = 1;
  2009. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2010. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2011. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2012. !no_enc_frame) {
  2013. nbuf_clone = qdf_nbuf_clone(nbuf);
  2014. if (!nbuf_clone) {
  2015. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2016. "qdf_nbuf_clone failed");
  2017. return nbuf;
  2018. }
  2019. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2020. }
  2021. if (nbuf_clone) {
  2022. if (!dp_tx_send(soc, vdev_id, nbuf_clone)) {
  2023. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2024. } else {
  2025. qdf_nbuf_free(nbuf_clone);
  2026. }
  2027. }
  2028. if (no_enc_frame)
  2029. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2030. else
  2031. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2032. nbuf = dp_tx_send(soc, vdev_id, nbuf);
  2033. if ((!nbuf) && no_enc_frame) {
  2034. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2035. }
  2036. return nbuf;
  2037. }
  2038. #else
  2039. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2040. qdf_nbuf_t nbuf)
  2041. {
  2042. return dp_tx_send(soc, vdev_id, nbuf);
  2043. }
  2044. #endif
  2045. /**
  2046. * dp_tx_nawds_handler() - NAWDS handler
  2047. *
  2048. * @soc: DP soc handle
  2049. * @vdev_id: id of DP vdev handle
  2050. * @msdu_info: msdu_info required to create HTT metadata
  2051. * @nbuf: skb
  2052. *
  2053. * This API transfers the multicast frames with the peer id
  2054. * on NAWDS enabled peer.
  2055. * Return: none
  2056. */
  2057. static inline
  2058. void dp_tx_nawds_handler(struct cdp_soc_t *soc, struct dp_vdev *vdev,
  2059. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2060. {
  2061. struct dp_peer *peer = NULL;
  2062. qdf_nbuf_t nbuf_clone = NULL;
  2063. struct dp_soc *dp_soc = (struct dp_soc *)soc;
  2064. uint16_t peer_id = DP_INVALID_PEER;
  2065. struct dp_peer *sa_peer = NULL;
  2066. struct dp_ast_entry *ast_entry = NULL;
  2067. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2068. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2069. qdf_spin_lock_bh(&dp_soc->ast_lock);
  2070. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2071. (dp_soc,
  2072. (uint8_t *)(eh->ether_shost),
  2073. vdev->pdev->pdev_id);
  2074. if (ast_entry)
  2075. sa_peer = ast_entry->peer;
  2076. qdf_spin_unlock_bh(&dp_soc->ast_lock);
  2077. }
  2078. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2079. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2080. if (!peer->bss_peer && peer->nawds_enabled) {
  2081. peer_id = peer->peer_id;
  2082. /* Multicast packets needs to be
  2083. * dropped in case of intra bss forwarding
  2084. */
  2085. if (sa_peer == peer) {
  2086. QDF_TRACE(QDF_MODULE_ID_DP,
  2087. QDF_TRACE_LEVEL_DEBUG,
  2088. " %s: multicast packet", __func__);
  2089. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2090. continue;
  2091. }
  2092. nbuf_clone = qdf_nbuf_clone(nbuf);
  2093. if (!nbuf_clone) {
  2094. QDF_TRACE(QDF_MODULE_ID_DP,
  2095. QDF_TRACE_LEVEL_ERROR,
  2096. FL("nbuf clone failed"));
  2097. break;
  2098. }
  2099. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2100. msdu_info, peer_id,
  2101. NULL);
  2102. if (nbuf_clone) {
  2103. QDF_TRACE(QDF_MODULE_ID_DP,
  2104. QDF_TRACE_LEVEL_DEBUG,
  2105. FL("pkt send failed"));
  2106. qdf_nbuf_free(nbuf_clone);
  2107. } else {
  2108. if (peer_id != DP_INVALID_PEER)
  2109. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2110. 1, qdf_nbuf_len(nbuf));
  2111. }
  2112. }
  2113. }
  2114. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2115. }
  2116. /**
  2117. * dp_tx_send() - Transmit a frame on a given VAP
  2118. * @soc: DP soc handle
  2119. * @vdev_id: id of DP vdev handle
  2120. * @nbuf: skb
  2121. *
  2122. * Entry point for Core Tx layer (DP_TX) invoked from
  2123. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2124. * cases
  2125. *
  2126. * Return: NULL on success,
  2127. * nbuf when it fails to send
  2128. */
  2129. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc, uint8_t vdev_id, qdf_nbuf_t nbuf)
  2130. {
  2131. uint16_t peer_id = HTT_INVALID_PEER;
  2132. /*
  2133. * doing a memzero is causing additional function call overhead
  2134. * so doing static stack clearing
  2135. */
  2136. struct dp_tx_msdu_info_s msdu_info = {0};
  2137. struct dp_vdev *vdev =
  2138. dp_get_vdev_from_soc_vdev_id_wifi3((struct dp_soc *)soc,
  2139. vdev_id);
  2140. if (qdf_unlikely(!vdev))
  2141. return nbuf;
  2142. dp_verbose_debug("skb %pM", nbuf->data);
  2143. /*
  2144. * Set Default Host TID value to invalid TID
  2145. * (TID override disabled)
  2146. */
  2147. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2148. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2149. if (qdf_unlikely(vdev->mesh_vdev)) {
  2150. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2151. &msdu_info);
  2152. if (!nbuf_mesh) {
  2153. dp_verbose_debug("Extracting mesh metadata failed");
  2154. return nbuf;
  2155. }
  2156. nbuf = nbuf_mesh;
  2157. }
  2158. /*
  2159. * Get HW Queue to use for this frame.
  2160. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2161. * dedicated for data and 1 for command.
  2162. * "queue_id" maps to one hardware ring.
  2163. * With each ring, we also associate a unique Tx descriptor pool
  2164. * to minimize lock contention for these resources.
  2165. */
  2166. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2167. /*
  2168. * TCL H/W supports 2 DSCP-TID mapping tables.
  2169. * Table 1 - Default DSCP-TID mapping table
  2170. * Table 2 - 1 DSCP-TID override table
  2171. *
  2172. * If we need a different DSCP-TID mapping for this vap,
  2173. * call tid_classify to extract DSCP/ToS from frame and
  2174. * map to a TID and store in msdu_info. This is later used
  2175. * to fill in TCL Input descriptor (per-packet TID override).
  2176. */
  2177. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2178. /*
  2179. * Classify the frame and call corresponding
  2180. * "prepare" function which extracts the segment (TSO)
  2181. * and fragmentation information (for TSO , SG, ME, or Raw)
  2182. * into MSDU_INFO structure which is later used to fill
  2183. * SW and HW descriptors.
  2184. */
  2185. if (qdf_nbuf_is_tso(nbuf)) {
  2186. dp_verbose_debug("TSO frame %pK", vdev);
  2187. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2188. qdf_nbuf_len(nbuf));
  2189. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2190. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2191. qdf_nbuf_len(nbuf));
  2192. return nbuf;
  2193. }
  2194. goto send_multiple;
  2195. }
  2196. /* SG */
  2197. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2198. struct dp_tx_seg_info_s seg_info = {0};
  2199. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2200. if (!nbuf)
  2201. return NULL;
  2202. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2203. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2204. qdf_nbuf_len(nbuf));
  2205. goto send_multiple;
  2206. }
  2207. #ifdef ATH_SUPPORT_IQUE
  2208. /* Mcast to Ucast Conversion*/
  2209. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2210. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2211. qdf_nbuf_data(nbuf);
  2212. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2213. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2214. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2215. DP_STATS_INC_PKT(vdev,
  2216. tx_i.mcast_en.mcast_pkt, 1,
  2217. qdf_nbuf_len(nbuf));
  2218. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2219. QDF_STATUS_SUCCESS) {
  2220. return NULL;
  2221. }
  2222. }
  2223. }
  2224. #endif
  2225. /* RAW */
  2226. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2227. struct dp_tx_seg_info_s seg_info = {0};
  2228. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2229. if (!nbuf)
  2230. return NULL;
  2231. dp_verbose_debug("Raw frame %pK", vdev);
  2232. goto send_multiple;
  2233. }
  2234. if (qdf_unlikely(vdev->nawds_enabled)) {
  2235. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2236. qdf_nbuf_data(nbuf);
  2237. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2238. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2239. peer_id = DP_INVALID_PEER;
  2240. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2241. 1, qdf_nbuf_len(nbuf));
  2242. }
  2243. /* Single linear frame */
  2244. /*
  2245. * If nbuf is a simple linear frame, use send_single function to
  2246. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2247. * SRNG. There is no need to setup a MSDU extension descriptor.
  2248. */
  2249. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2250. return nbuf;
  2251. send_multiple:
  2252. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2253. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2254. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2255. return nbuf;
  2256. }
  2257. /**
  2258. * dp_tx_reinject_handler() - Tx Reinject Handler
  2259. * @tx_desc: software descriptor head pointer
  2260. * @status : Tx completion status from HTT descriptor
  2261. *
  2262. * This function reinjects frames back to Target.
  2263. * Todo - Host queue needs to be added
  2264. *
  2265. * Return: none
  2266. */
  2267. static
  2268. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2269. {
  2270. struct dp_vdev *vdev;
  2271. struct dp_peer *peer = NULL;
  2272. uint32_t peer_id = HTT_INVALID_PEER;
  2273. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2274. qdf_nbuf_t nbuf_copy = NULL;
  2275. struct dp_tx_msdu_info_s msdu_info;
  2276. struct dp_soc *soc = NULL;
  2277. #ifdef WDS_VENDOR_EXTENSION
  2278. int is_mcast = 0, is_ucast = 0;
  2279. int num_peers_3addr = 0;
  2280. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2281. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2282. #endif
  2283. vdev = tx_desc->vdev;
  2284. soc = vdev->pdev->soc;
  2285. qdf_assert(vdev);
  2286. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2287. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2288. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2289. "%s Tx reinject path", __func__);
  2290. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2291. qdf_nbuf_len(tx_desc->nbuf));
  2292. #ifdef WDS_VENDOR_EXTENSION
  2293. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2294. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2295. } else {
  2296. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2297. }
  2298. is_ucast = !is_mcast;
  2299. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2300. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2301. if (peer->bss_peer)
  2302. continue;
  2303. /* Detect wds peers that use 3-addr framing for mcast.
  2304. * if there are any, the bss_peer is used to send the
  2305. * the mcast frame using 3-addr format. all wds enabled
  2306. * peers that use 4-addr framing for mcast frames will
  2307. * be duplicated and sent as 4-addr frames below.
  2308. */
  2309. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2310. num_peers_3addr = 1;
  2311. break;
  2312. }
  2313. }
  2314. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2315. #endif
  2316. if (qdf_unlikely(vdev->mesh_vdev)) {
  2317. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2318. } else {
  2319. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2320. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2321. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2322. #ifdef WDS_VENDOR_EXTENSION
  2323. /*
  2324. * . if 3-addr STA, then send on BSS Peer
  2325. * . if Peer WDS enabled and accept 4-addr mcast,
  2326. * send mcast on that peer only
  2327. * . if Peer WDS enabled and accept 4-addr ucast,
  2328. * send ucast on that peer only
  2329. */
  2330. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2331. (peer->wds_enabled &&
  2332. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2333. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2334. #else
  2335. ((peer->bss_peer &&
  2336. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2337. #endif
  2338. peer_id = DP_INVALID_PEER;
  2339. nbuf_copy = qdf_nbuf_copy(nbuf);
  2340. if (!nbuf_copy) {
  2341. QDF_TRACE(QDF_MODULE_ID_DP,
  2342. QDF_TRACE_LEVEL_DEBUG,
  2343. FL("nbuf copy failed"));
  2344. break;
  2345. }
  2346. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2347. nbuf_copy,
  2348. &msdu_info,
  2349. peer_id,
  2350. NULL);
  2351. if (nbuf_copy) {
  2352. QDF_TRACE(QDF_MODULE_ID_DP,
  2353. QDF_TRACE_LEVEL_DEBUG,
  2354. FL("pkt send failed"));
  2355. qdf_nbuf_free(nbuf_copy);
  2356. } else {
  2357. if (peer_id != DP_INVALID_PEER)
  2358. DP_STATS_INC_PKT(peer,
  2359. tx.nawds_mcast,
  2360. 1, qdf_nbuf_len(nbuf));
  2361. }
  2362. }
  2363. }
  2364. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2365. }
  2366. qdf_nbuf_free(nbuf);
  2367. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2368. }
  2369. /**
  2370. * dp_tx_inspect_handler() - Tx Inspect Handler
  2371. * @tx_desc: software descriptor head pointer
  2372. * @status : Tx completion status from HTT descriptor
  2373. *
  2374. * Handles Tx frames sent back to Host for inspection
  2375. * (ProxyARP)
  2376. *
  2377. * Return: none
  2378. */
  2379. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2380. {
  2381. struct dp_soc *soc;
  2382. struct dp_pdev *pdev = tx_desc->pdev;
  2383. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2384. "%s Tx inspect path",
  2385. __func__);
  2386. qdf_assert(pdev);
  2387. soc = pdev->soc;
  2388. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2389. qdf_nbuf_len(tx_desc->nbuf));
  2390. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2391. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2392. }
  2393. #ifdef FEATURE_PERPKT_INFO
  2394. /**
  2395. * dp_get_completion_indication_for_stack() - send completion to stack
  2396. * @soc : dp_soc handle
  2397. * @pdev: dp_pdev handle
  2398. * @peer: dp peer handle
  2399. * @ts: transmit completion status structure
  2400. * @netbuf: Buffer pointer for free
  2401. *
  2402. * This function is used for indication whether buffer needs to be
  2403. * sent to stack for freeing or not
  2404. */
  2405. QDF_STATUS
  2406. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2407. struct dp_pdev *pdev,
  2408. struct dp_peer *peer,
  2409. struct hal_tx_completion_status *ts,
  2410. qdf_nbuf_t netbuf,
  2411. uint64_t time_latency)
  2412. {
  2413. struct tx_capture_hdr *ppdu_hdr;
  2414. uint16_t peer_id = ts->peer_id;
  2415. uint32_t ppdu_id = ts->ppdu_id;
  2416. uint8_t first_msdu = ts->first_msdu;
  2417. uint8_t last_msdu = ts->last_msdu;
  2418. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  2419. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2420. !pdev->latency_capture_enable))
  2421. return QDF_STATUS_E_NOSUPPORT;
  2422. if (!peer) {
  2423. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2424. FL("Peer Invalid"));
  2425. return QDF_STATUS_E_INVAL;
  2426. }
  2427. if (pdev->mcopy_mode) {
  2428. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  2429. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  2430. * for each MPDU
  2431. */
  2432. if (pdev->mcopy_mode == M_COPY) {
  2433. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2434. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2435. return QDF_STATUS_E_INVAL;
  2436. }
  2437. }
  2438. if (!first_msdu)
  2439. return QDF_STATUS_E_INVAL;
  2440. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2441. pdev->m_copy_id.tx_peer_id = peer_id;
  2442. }
  2443. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  2444. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  2445. if (!netbuf) {
  2446. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2447. FL("No headroom"));
  2448. return QDF_STATUS_E_NOMEM;
  2449. }
  2450. }
  2451. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  2452. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2453. FL("No headroom"));
  2454. return QDF_STATUS_E_NOMEM;
  2455. }
  2456. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2457. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2458. QDF_MAC_ADDR_SIZE);
  2459. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2460. QDF_MAC_ADDR_SIZE);
  2461. ppdu_hdr->ppdu_id = ppdu_id;
  2462. ppdu_hdr->peer_id = peer_id;
  2463. ppdu_hdr->first_msdu = first_msdu;
  2464. ppdu_hdr->last_msdu = last_msdu;
  2465. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2466. ppdu_hdr->tsf = ts->tsf;
  2467. ppdu_hdr->time_latency = time_latency;
  2468. }
  2469. return QDF_STATUS_SUCCESS;
  2470. }
  2471. /**
  2472. * dp_send_completion_to_stack() - send completion to stack
  2473. * @soc : dp_soc handle
  2474. * @pdev: dp_pdev handle
  2475. * @peer_id: peer_id of the peer for which completion came
  2476. * @ppdu_id: ppdu_id
  2477. * @netbuf: Buffer pointer for free
  2478. *
  2479. * This function is used to send completion to stack
  2480. * to free buffer
  2481. */
  2482. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2483. uint16_t peer_id, uint32_t ppdu_id,
  2484. qdf_nbuf_t netbuf)
  2485. {
  2486. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2487. netbuf, peer_id,
  2488. WDI_NO_VAL, pdev->pdev_id);
  2489. }
  2490. #else
  2491. static QDF_STATUS
  2492. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2493. struct dp_pdev *pdev,
  2494. struct dp_peer *peer,
  2495. struct hal_tx_completion_status *ts,
  2496. qdf_nbuf_t netbuf,
  2497. uint64_t time_latency)
  2498. {
  2499. return QDF_STATUS_E_NOSUPPORT;
  2500. }
  2501. static void
  2502. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2503. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2504. {
  2505. }
  2506. #endif
  2507. /**
  2508. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2509. * @soc: Soc handle
  2510. * @desc: software Tx descriptor to be processed
  2511. *
  2512. * Return: none
  2513. */
  2514. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2515. struct dp_tx_desc_s *desc)
  2516. {
  2517. struct dp_vdev *vdev = desc->vdev;
  2518. qdf_nbuf_t nbuf = desc->nbuf;
  2519. /* nbuf already freed in vdev detach path */
  2520. if (!nbuf)
  2521. return;
  2522. /* If it is TDLS mgmt, don't unmap or free the frame */
  2523. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2524. return dp_non_std_tx_comp_free_buff(soc, desc, vdev);
  2525. /* 0 : MSDU buffer, 1 : MLE */
  2526. if (desc->msdu_ext_desc) {
  2527. /* TSO free */
  2528. if (hal_tx_ext_desc_get_tso_enable(
  2529. desc->msdu_ext_desc->vaddr)) {
  2530. /* unmap eash TSO seg before free the nbuf */
  2531. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2532. desc->tso_num_desc);
  2533. qdf_nbuf_free(nbuf);
  2534. return;
  2535. }
  2536. }
  2537. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2538. QDF_DMA_TO_DEVICE, nbuf->len);
  2539. if (qdf_unlikely(!vdev)) {
  2540. qdf_nbuf_free(nbuf);
  2541. return;
  2542. }
  2543. if (qdf_likely(!vdev->mesh_vdev))
  2544. qdf_nbuf_free(nbuf);
  2545. else {
  2546. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2547. qdf_nbuf_free(nbuf);
  2548. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2549. } else
  2550. vdev->osif_tx_free_ext((nbuf));
  2551. }
  2552. }
  2553. #ifdef MESH_MODE_SUPPORT
  2554. /**
  2555. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2556. * in mesh meta header
  2557. * @tx_desc: software descriptor head pointer
  2558. * @ts: pointer to tx completion stats
  2559. * Return: none
  2560. */
  2561. static
  2562. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2563. struct hal_tx_completion_status *ts)
  2564. {
  2565. struct meta_hdr_s *mhdr;
  2566. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2567. if (!tx_desc->msdu_ext_desc) {
  2568. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2569. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2570. "netbuf %pK offset %d",
  2571. netbuf, tx_desc->pkt_offset);
  2572. return;
  2573. }
  2574. }
  2575. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2576. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2577. "netbuf %pK offset %lu", netbuf,
  2578. sizeof(struct meta_hdr_s));
  2579. return;
  2580. }
  2581. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2582. mhdr->rssi = ts->ack_frame_rssi;
  2583. mhdr->band = tx_desc->pdev->operating_channel.band;
  2584. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2585. }
  2586. #else
  2587. static
  2588. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2589. struct hal_tx_completion_status *ts)
  2590. {
  2591. }
  2592. #endif
  2593. #ifdef QCA_PEER_EXT_STATS
  2594. /*
  2595. * dp_tx_compute_tid_delay() - Compute per TID delay
  2596. * @stats: Per TID delay stats
  2597. * @tx_desc: Software Tx descriptor
  2598. *
  2599. * Compute the software enqueue and hw enqueue delays and
  2600. * update the respective histograms
  2601. *
  2602. * Return: void
  2603. */
  2604. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  2605. struct dp_tx_desc_s *tx_desc)
  2606. {
  2607. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  2608. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2609. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  2610. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2611. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2612. timestamp_hw_enqueue = tx_desc->timestamp;
  2613. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2614. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2615. timestamp_hw_enqueue);
  2616. /*
  2617. * Update the Tx software enqueue delay and HW enque-Completion delay.
  2618. */
  2619. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  2620. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  2621. }
  2622. /*
  2623. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  2624. * @peer: DP peer context
  2625. * @tx_desc: Tx software descriptor
  2626. * @tid: Transmission ID
  2627. * @ring_id: Rx CPU context ID/CPU_ID
  2628. *
  2629. * Update the peer extended stats. These are enhanced other
  2630. * delay stats per msdu level.
  2631. *
  2632. * Return: void
  2633. */
  2634. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2635. struct dp_tx_desc_s *tx_desc,
  2636. uint8_t tid, uint8_t ring_id)
  2637. {
  2638. struct dp_pdev *pdev = peer->vdev->pdev;
  2639. struct dp_soc *soc = NULL;
  2640. struct cdp_peer_ext_stats *pext_stats = NULL;
  2641. soc = pdev->soc;
  2642. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  2643. return;
  2644. pext_stats = peer->pext_stats;
  2645. qdf_assert(pext_stats);
  2646. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  2647. /*
  2648. * For non-TID packets use the TID 9
  2649. */
  2650. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2651. tid = CDP_MAX_DATA_TIDS - 1;
  2652. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  2653. tx_desc);
  2654. }
  2655. #else
  2656. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2657. struct dp_tx_desc_s *tx_desc,
  2658. uint8_t tid, uint8_t ring_id)
  2659. {
  2660. }
  2661. #endif
  2662. /**
  2663. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2664. * to pass in correct fields
  2665. *
  2666. * @vdev: pdev handle
  2667. * @tx_desc: tx descriptor
  2668. * @tid: tid value
  2669. * @ring_id: TCL or WBM ring number for transmit path
  2670. * Return: none
  2671. */
  2672. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2673. struct dp_tx_desc_s *tx_desc,
  2674. uint8_t tid, uint8_t ring_id)
  2675. {
  2676. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2677. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2678. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2679. return;
  2680. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2681. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2682. timestamp_hw_enqueue = tx_desc->timestamp;
  2683. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2684. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2685. timestamp_hw_enqueue);
  2686. interframe_delay = (uint32_t)(timestamp_ingress -
  2687. vdev->prev_tx_enq_tstamp);
  2688. /*
  2689. * Delay in software enqueue
  2690. */
  2691. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2692. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2693. /*
  2694. * Delay between packet enqueued to HW and Tx completion
  2695. */
  2696. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2697. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2698. /*
  2699. * Update interframe delay stats calculated at hardstart receive point.
  2700. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2701. * interframe delay will not be calculate correctly for 1st frame.
  2702. * On the other side, this will help in avoiding extra per packet check
  2703. * of !vdev->prev_tx_enq_tstamp.
  2704. */
  2705. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2706. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2707. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2708. }
  2709. #ifdef DISABLE_DP_STATS
  2710. static
  2711. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2712. {
  2713. }
  2714. #else
  2715. static
  2716. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2717. {
  2718. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  2719. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  2720. if (subtype != QDF_PROTO_INVALID)
  2721. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  2722. }
  2723. #endif
  2724. /**
  2725. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2726. * per wbm ring
  2727. *
  2728. * @tx_desc: software descriptor head pointer
  2729. * @ts: Tx completion status
  2730. * @peer: peer handle
  2731. * @ring_id: ring number
  2732. *
  2733. * Return: None
  2734. */
  2735. static inline void
  2736. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2737. struct hal_tx_completion_status *ts,
  2738. struct dp_peer *peer, uint8_t ring_id)
  2739. {
  2740. struct dp_pdev *pdev = peer->vdev->pdev;
  2741. struct dp_soc *soc = NULL;
  2742. uint8_t mcs, pkt_type;
  2743. uint8_t tid = ts->tid;
  2744. uint32_t length;
  2745. struct cdp_tid_tx_stats *tid_stats;
  2746. if (!pdev)
  2747. return;
  2748. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2749. tid = CDP_MAX_DATA_TIDS - 1;
  2750. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2751. soc = pdev->soc;
  2752. mcs = ts->mcs;
  2753. pkt_type = ts->pkt_type;
  2754. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2755. dp_err("Release source is not from TQM");
  2756. return;
  2757. }
  2758. length = qdf_nbuf_len(tx_desc->nbuf);
  2759. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2760. if (qdf_unlikely(pdev->delay_stats_flag))
  2761. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2762. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2763. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2764. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2765. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2766. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2767. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2768. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2769. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2770. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2771. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2772. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2773. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2774. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2775. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2776. /*
  2777. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2778. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2779. * are no completions for failed cases. Hence updating tx_failed from
  2780. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2781. * then this has to be removed
  2782. */
  2783. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2784. peer->stats.tx.dropped.fw_rem_notx +
  2785. peer->stats.tx.dropped.fw_rem_tx +
  2786. peer->stats.tx.dropped.age_out +
  2787. peer->stats.tx.dropped.fw_reason1 +
  2788. peer->stats.tx.dropped.fw_reason2 +
  2789. peer->stats.tx.dropped.fw_reason3;
  2790. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2791. tid_stats->tqm_status_cnt[ts->status]++;
  2792. }
  2793. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2794. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  2795. return;
  2796. }
  2797. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2798. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2799. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2800. /*
  2801. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2802. * Return from here if HTT PPDU events are enabled.
  2803. */
  2804. if (!(soc->process_tx_status))
  2805. return;
  2806. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2807. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2808. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2809. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2810. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2811. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2812. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2813. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2814. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2815. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2816. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2817. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2818. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2819. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2820. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2821. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2822. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2823. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2824. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2825. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2826. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2827. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2828. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2829. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2830. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2831. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2832. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2833. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2834. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2835. &peer->stats, ts->peer_id,
  2836. UPDATE_PEER_STATS, pdev->pdev_id);
  2837. #endif
  2838. }
  2839. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2840. /**
  2841. * dp_tx_flow_pool_lock() - take flow pool lock
  2842. * @soc: core txrx main context
  2843. * @tx_desc: tx desc
  2844. *
  2845. * Return: None
  2846. */
  2847. static inline
  2848. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2849. struct dp_tx_desc_s *tx_desc)
  2850. {
  2851. struct dp_tx_desc_pool_s *pool;
  2852. uint8_t desc_pool_id;
  2853. desc_pool_id = tx_desc->pool_id;
  2854. pool = &soc->tx_desc[desc_pool_id];
  2855. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2856. }
  2857. /**
  2858. * dp_tx_flow_pool_unlock() - release flow pool lock
  2859. * @soc: core txrx main context
  2860. * @tx_desc: tx desc
  2861. *
  2862. * Return: None
  2863. */
  2864. static inline
  2865. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2866. struct dp_tx_desc_s *tx_desc)
  2867. {
  2868. struct dp_tx_desc_pool_s *pool;
  2869. uint8_t desc_pool_id;
  2870. desc_pool_id = tx_desc->pool_id;
  2871. pool = &soc->tx_desc[desc_pool_id];
  2872. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2873. }
  2874. #else
  2875. static inline
  2876. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2877. {
  2878. }
  2879. static inline
  2880. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2881. {
  2882. }
  2883. #endif
  2884. /**
  2885. * dp_tx_notify_completion() - Notify tx completion for this desc
  2886. * @soc: core txrx main context
  2887. * @tx_desc: tx desc
  2888. * @netbuf: buffer
  2889. * @status: tx status
  2890. *
  2891. * Return: none
  2892. */
  2893. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2894. struct dp_tx_desc_s *tx_desc,
  2895. qdf_nbuf_t netbuf,
  2896. uint8_t status)
  2897. {
  2898. void *osif_dev;
  2899. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2900. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  2901. qdf_assert(tx_desc);
  2902. dp_tx_flow_pool_lock(soc, tx_desc);
  2903. if (!tx_desc->vdev ||
  2904. !tx_desc->vdev->osif_vdev) {
  2905. dp_tx_flow_pool_unlock(soc, tx_desc);
  2906. return;
  2907. }
  2908. osif_dev = tx_desc->vdev->osif_vdev;
  2909. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2910. dp_tx_flow_pool_unlock(soc, tx_desc);
  2911. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  2912. flag |= BIT(QDF_TX_RX_STATUS_OK);
  2913. if (tx_compl_cbk)
  2914. tx_compl_cbk(netbuf, osif_dev, flag);
  2915. }
  2916. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2917. * @pdev: pdev handle
  2918. * @tid: tid value
  2919. * @txdesc_ts: timestamp from txdesc
  2920. * @ppdu_id: ppdu id
  2921. *
  2922. * Return: none
  2923. */
  2924. #ifdef FEATURE_PERPKT_INFO
  2925. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2926. struct dp_peer *peer,
  2927. uint8_t tid,
  2928. uint64_t txdesc_ts,
  2929. uint32_t ppdu_id)
  2930. {
  2931. uint64_t delta_ms;
  2932. struct cdp_tx_sojourn_stats *sojourn_stats;
  2933. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2934. return;
  2935. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2936. tid >= CDP_DATA_TID_MAX))
  2937. return;
  2938. if (qdf_unlikely(!pdev->sojourn_buf))
  2939. return;
  2940. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2941. qdf_nbuf_data(pdev->sojourn_buf);
  2942. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2943. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2944. txdesc_ts;
  2945. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2946. delta_ms);
  2947. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2948. sojourn_stats->num_msdus[tid] = 1;
  2949. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2950. peer->avg_sojourn_msdu[tid].internal;
  2951. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2952. pdev->sojourn_buf, HTT_INVALID_PEER,
  2953. WDI_NO_VAL, pdev->pdev_id);
  2954. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2955. sojourn_stats->num_msdus[tid] = 0;
  2956. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2957. }
  2958. #else
  2959. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2960. struct dp_peer *peer,
  2961. uint8_t tid,
  2962. uint64_t txdesc_ts,
  2963. uint32_t ppdu_id)
  2964. {
  2965. }
  2966. #endif
  2967. /**
  2968. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2969. * @soc: DP Soc handle
  2970. * @tx_desc: software Tx descriptor
  2971. * @ts : Tx completion status from HAL/HTT descriptor
  2972. *
  2973. * Return: none
  2974. */
  2975. static inline void
  2976. dp_tx_comp_process_desc(struct dp_soc *soc,
  2977. struct dp_tx_desc_s *desc,
  2978. struct hal_tx_completion_status *ts,
  2979. struct dp_peer *peer)
  2980. {
  2981. uint64_t time_latency = 0;
  2982. /*
  2983. * m_copy/tx_capture modes are not supported for
  2984. * scatter gather packets
  2985. */
  2986. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2987. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  2988. desc->timestamp);
  2989. }
  2990. if (!(desc->msdu_ext_desc)) {
  2991. if (QDF_STATUS_SUCCESS ==
  2992. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2993. return;
  2994. }
  2995. if (QDF_STATUS_SUCCESS ==
  2996. dp_get_completion_indication_for_stack(soc,
  2997. desc->pdev,
  2998. peer, ts,
  2999. desc->nbuf,
  3000. time_latency)) {
  3001. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3002. QDF_DMA_TO_DEVICE,
  3003. desc->nbuf->len);
  3004. dp_send_completion_to_stack(soc,
  3005. desc->pdev,
  3006. ts->peer_id,
  3007. ts->ppdu_id,
  3008. desc->nbuf);
  3009. return;
  3010. }
  3011. }
  3012. dp_tx_comp_free_buf(soc, desc);
  3013. }
  3014. #ifdef DISABLE_DP_STATS
  3015. /**
  3016. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3017. * @soc: core txrx main context
  3018. * @tx_desc: tx desc
  3019. * @status: tx status
  3020. *
  3021. * Return: none
  3022. */
  3023. static inline
  3024. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3025. struct dp_tx_desc_s *tx_desc,
  3026. uint8_t status)
  3027. {
  3028. }
  3029. #else
  3030. static inline
  3031. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3032. struct dp_tx_desc_s *tx_desc,
  3033. uint8_t status)
  3034. {
  3035. void *osif_dev;
  3036. ol_txrx_stats_rx_fp stats_cbk;
  3037. uint8_t pkt_type;
  3038. qdf_assert(tx_desc);
  3039. if (!tx_desc->vdev ||
  3040. !tx_desc->vdev->osif_vdev ||
  3041. !tx_desc->vdev->stats_cb)
  3042. return;
  3043. osif_dev = tx_desc->vdev->osif_vdev;
  3044. stats_cbk = tx_desc->vdev->stats_cb;
  3045. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3046. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3047. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3048. &pkt_type);
  3049. }
  3050. #endif
  3051. /**
  3052. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3053. * @soc: DP soc handle
  3054. * @tx_desc: software descriptor head pointer
  3055. * @ts: Tx completion status
  3056. * @peer: peer handle
  3057. * @ring_id: ring number
  3058. *
  3059. * Return: none
  3060. */
  3061. static inline
  3062. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3063. struct dp_tx_desc_s *tx_desc,
  3064. struct hal_tx_completion_status *ts,
  3065. struct dp_peer *peer, uint8_t ring_id)
  3066. {
  3067. uint32_t length;
  3068. qdf_ether_header_t *eh;
  3069. struct dp_vdev *vdev = tx_desc->vdev;
  3070. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3071. uint8_t dp_status;
  3072. if (!vdev || !nbuf) {
  3073. dp_info_rl("invalid tx descriptor. vdev or nbuf NULL");
  3074. goto out;
  3075. }
  3076. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3077. length = qdf_nbuf_len(nbuf);
  3078. dp_status = qdf_dp_get_status_from_htt(ts->status);
  3079. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3080. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3081. QDF_TRACE_DEFAULT_PDEV_ID,
  3082. qdf_nbuf_data_addr(nbuf),
  3083. sizeof(qdf_nbuf_data(nbuf)),
  3084. tx_desc->id,
  3085. dp_status));
  3086. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3087. "-------------------- \n"
  3088. "Tx Completion Stats: \n"
  3089. "-------------------- \n"
  3090. "ack_frame_rssi = %d \n"
  3091. "first_msdu = %d \n"
  3092. "last_msdu = %d \n"
  3093. "msdu_part_of_amsdu = %d \n"
  3094. "rate_stats valid = %d \n"
  3095. "bw = %d \n"
  3096. "pkt_type = %d \n"
  3097. "stbc = %d \n"
  3098. "ldpc = %d \n"
  3099. "sgi = %d \n"
  3100. "mcs = %d \n"
  3101. "ofdma = %d \n"
  3102. "tones_in_ru = %d \n"
  3103. "tsf = %d \n"
  3104. "ppdu_id = %d \n"
  3105. "transmit_cnt = %d \n"
  3106. "tid = %d \n"
  3107. "peer_id = %d\n",
  3108. ts->ack_frame_rssi, ts->first_msdu,
  3109. ts->last_msdu, ts->msdu_part_of_amsdu,
  3110. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3111. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3112. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3113. ts->transmit_cnt, ts->tid, ts->peer_id);
  3114. /* Update SoC level stats */
  3115. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3116. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3117. if (!peer) {
  3118. dp_err_rl("peer is null or deletion in progress");
  3119. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3120. goto out;
  3121. }
  3122. dp_tx_update_connectivity_stats(soc, tx_desc, ts->status);
  3123. /* Update per-packet stats for mesh mode */
  3124. if (qdf_unlikely(vdev->mesh_vdev) &&
  3125. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3126. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3127. /* Update peer level stats */
  3128. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3129. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3130. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3131. if ((peer->vdev->tx_encap_type ==
  3132. htt_cmn_pkt_type_ethernet) &&
  3133. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3134. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3135. }
  3136. }
  3137. } else {
  3138. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3139. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3140. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3141. if (qdf_unlikely(peer->in_twt)) {
  3142. DP_STATS_INC_PKT(peer,
  3143. tx.tx_success_twt,
  3144. 1, length);
  3145. }
  3146. }
  3147. }
  3148. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3149. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3150. #ifdef QCA_SUPPORT_RDK_STATS
  3151. if (soc->wlanstats_enabled)
  3152. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3153. tx_desc->timestamp,
  3154. ts->ppdu_id);
  3155. #endif
  3156. out:
  3157. return;
  3158. }
  3159. /**
  3160. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3161. * @soc: core txrx main context
  3162. * @comp_head: software descriptor head pointer
  3163. * @ring_id: ring number
  3164. *
  3165. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3166. * and release the software descriptors after processing is complete
  3167. *
  3168. * Return: none
  3169. */
  3170. static void
  3171. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3172. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3173. {
  3174. struct dp_tx_desc_s *desc;
  3175. struct dp_tx_desc_s *next;
  3176. struct hal_tx_completion_status ts;
  3177. struct dp_peer *peer;
  3178. qdf_nbuf_t netbuf;
  3179. desc = comp_head;
  3180. while (desc) {
  3181. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3182. struct dp_pdev *pdev = desc->pdev;
  3183. peer = dp_peer_find_by_id(soc, desc->peer_id);
  3184. if (qdf_likely(peer)) {
  3185. /*
  3186. * Increment peer statistics
  3187. * Minimal statistics update done here
  3188. */
  3189. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3190. desc->length);
  3191. if (desc->tx_status !=
  3192. HAL_TX_TQM_RR_FRAME_ACKED)
  3193. peer->stats.tx.tx_failed++;
  3194. dp_peer_unref_delete(peer);
  3195. }
  3196. qdf_assert(pdev);
  3197. dp_tx_outstanding_dec(pdev);
  3198. /*
  3199. * Calling a QDF WRAPPER here is creating signifcant
  3200. * performance impact so avoided the wrapper call here
  3201. */
  3202. next = desc->next;
  3203. qdf_mem_unmap_nbytes_single(soc->osdev,
  3204. desc->dma_addr,
  3205. QDF_DMA_TO_DEVICE,
  3206. desc->length);
  3207. qdf_nbuf_free(desc->nbuf);
  3208. dp_tx_desc_free(soc, desc, desc->pool_id);
  3209. desc = next;
  3210. continue;
  3211. }
  3212. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3213. peer = dp_peer_find_by_id(soc, ts.peer_id);
  3214. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3215. netbuf = desc->nbuf;
  3216. /* check tx complete notification */
  3217. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  3218. dp_tx_notify_completion(soc, desc, netbuf, ts.status);
  3219. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3220. if (peer)
  3221. dp_peer_unref_delete(peer);
  3222. next = desc->next;
  3223. dp_tx_desc_release(desc, desc->pool_id);
  3224. desc = next;
  3225. }
  3226. }
  3227. /**
  3228. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3229. * @tx_desc: software descriptor head pointer
  3230. * @status : Tx completion status from HTT descriptor
  3231. * @ring_id: ring number
  3232. *
  3233. * This function will process HTT Tx indication messages from Target
  3234. *
  3235. * Return: none
  3236. */
  3237. static
  3238. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3239. uint8_t ring_id)
  3240. {
  3241. uint8_t tx_status;
  3242. struct dp_pdev *pdev;
  3243. struct dp_vdev *vdev;
  3244. struct dp_soc *soc;
  3245. struct hal_tx_completion_status ts = {0};
  3246. uint32_t *htt_desc = (uint32_t *)status;
  3247. struct dp_peer *peer;
  3248. struct cdp_tid_tx_stats *tid_stats = NULL;
  3249. struct htt_soc *htt_handle;
  3250. /*
  3251. * If the descriptor is already freed in vdev_detach,
  3252. * continue to next descriptor
  3253. */
  3254. if (!tx_desc->vdev && !tx_desc->flags) {
  3255. QDF_TRACE(QDF_MODULE_ID_DP,
  3256. QDF_TRACE_LEVEL_INFO,
  3257. "Descriptor freed in vdev_detach %d",
  3258. tx_desc->id);
  3259. return;
  3260. }
  3261. pdev = tx_desc->pdev;
  3262. soc = pdev->soc;
  3263. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3264. QDF_TRACE(QDF_MODULE_ID_DP,
  3265. QDF_TRACE_LEVEL_INFO,
  3266. "pdev in down state %d",
  3267. tx_desc->id);
  3268. dp_tx_comp_free_buf(soc, tx_desc);
  3269. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3270. return;
  3271. }
  3272. qdf_assert(tx_desc->pdev);
  3273. vdev = tx_desc->vdev;
  3274. if (!vdev)
  3275. return;
  3276. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3277. htt_handle = (struct htt_soc *)soc->htt_handle;
  3278. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3279. switch (tx_status) {
  3280. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3281. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3282. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3283. {
  3284. uint8_t tid;
  3285. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3286. ts.peer_id =
  3287. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3288. htt_desc[2]);
  3289. ts.tid =
  3290. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3291. htt_desc[2]);
  3292. } else {
  3293. ts.peer_id = HTT_INVALID_PEER;
  3294. ts.tid = HTT_INVALID_TID;
  3295. }
  3296. ts.ppdu_id =
  3297. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3298. htt_desc[1]);
  3299. ts.ack_frame_rssi =
  3300. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3301. htt_desc[1]);
  3302. ts.tsf = htt_desc[3];
  3303. ts.first_msdu = 1;
  3304. ts.last_msdu = 1;
  3305. tid = ts.tid;
  3306. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3307. tid = CDP_MAX_DATA_TIDS - 1;
  3308. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3309. if (qdf_unlikely(pdev->delay_stats_flag))
  3310. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3311. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3312. tid_stats->htt_status_cnt[tx_status]++;
  3313. }
  3314. peer = dp_peer_find_by_id(soc, ts.peer_id);
  3315. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3316. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3317. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3318. if (qdf_likely(peer))
  3319. dp_peer_unref_delete(peer);
  3320. break;
  3321. }
  3322. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3323. {
  3324. dp_tx_reinject_handler(tx_desc, status);
  3325. break;
  3326. }
  3327. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3328. {
  3329. dp_tx_inspect_handler(tx_desc, status);
  3330. break;
  3331. }
  3332. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3333. {
  3334. dp_tx_mec_handler(vdev, status);
  3335. break;
  3336. }
  3337. default:
  3338. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3339. "%s Invalid HTT tx_status %d\n",
  3340. __func__, tx_status);
  3341. break;
  3342. }
  3343. }
  3344. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3345. static inline
  3346. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3347. {
  3348. bool limit_hit = false;
  3349. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3350. limit_hit =
  3351. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3352. if (limit_hit)
  3353. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3354. return limit_hit;
  3355. }
  3356. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3357. {
  3358. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3359. }
  3360. #else
  3361. static inline
  3362. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3363. {
  3364. return false;
  3365. }
  3366. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3367. {
  3368. return false;
  3369. }
  3370. #endif
  3371. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3372. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3373. uint32_t quota)
  3374. {
  3375. void *tx_comp_hal_desc;
  3376. uint8_t buffer_src;
  3377. uint8_t pool_id;
  3378. uint32_t tx_desc_id;
  3379. struct dp_tx_desc_s *tx_desc = NULL;
  3380. struct dp_tx_desc_s *head_desc = NULL;
  3381. struct dp_tx_desc_s *tail_desc = NULL;
  3382. uint32_t num_processed = 0;
  3383. uint32_t count;
  3384. uint32_t num_avail_for_reap = 0;
  3385. bool force_break = false;
  3386. DP_HIST_INIT();
  3387. more_data:
  3388. /* Re-initialize local variables to be re-used */
  3389. head_desc = NULL;
  3390. tail_desc = NULL;
  3391. count = 0;
  3392. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3393. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3394. return 0;
  3395. }
  3396. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3397. if (num_avail_for_reap >= quota)
  3398. num_avail_for_reap = quota;
  3399. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3400. /* Find head descriptor from completion ring */
  3401. while (qdf_likely(num_avail_for_reap)) {
  3402. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3403. if (qdf_unlikely(!tx_comp_hal_desc))
  3404. break;
  3405. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3406. /* If this buffer was not released by TQM or FW, then it is not
  3407. * Tx completion indication, assert */
  3408. if (qdf_unlikely(buffer_src !=
  3409. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3410. (qdf_unlikely(buffer_src !=
  3411. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3412. uint8_t wbm_internal_error;
  3413. dp_err_rl(
  3414. "Tx comp release_src != TQM | FW but from %d",
  3415. buffer_src);
  3416. hal_dump_comp_desc(tx_comp_hal_desc);
  3417. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3418. /* When WBM sees NULL buffer_addr_info in any of
  3419. * ingress rings it sends an error indication,
  3420. * with wbm_internal_error=1, to a specific ring.
  3421. * The WBM2SW ring used to indicate these errors is
  3422. * fixed in HW, and that ring is being used as Tx
  3423. * completion ring. These errors are not related to
  3424. * Tx completions, and should just be ignored
  3425. */
  3426. wbm_internal_error = hal_get_wbm_internal_error(
  3427. soc->hal_soc,
  3428. tx_comp_hal_desc);
  3429. if (wbm_internal_error) {
  3430. dp_err_rl("Tx comp wbm_internal_error!!");
  3431. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3432. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3433. buffer_src)
  3434. dp_handle_wbm_internal_error(
  3435. soc,
  3436. tx_comp_hal_desc,
  3437. hal_tx_comp_get_buffer_type(
  3438. tx_comp_hal_desc));
  3439. } else {
  3440. dp_err_rl("Tx comp wbm_internal_error false");
  3441. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3442. }
  3443. continue;
  3444. }
  3445. /* Get descriptor id */
  3446. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3447. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3448. DP_TX_DESC_ID_POOL_OS;
  3449. /* Find Tx descriptor */
  3450. tx_desc = dp_tx_desc_find(soc, pool_id,
  3451. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3452. DP_TX_DESC_ID_PAGE_OS,
  3453. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3454. DP_TX_DESC_ID_OFFSET_OS);
  3455. /*
  3456. * If the release source is FW, process the HTT status
  3457. */
  3458. if (qdf_unlikely(buffer_src ==
  3459. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3460. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3461. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3462. htt_tx_status);
  3463. dp_tx_process_htt_completion(tx_desc,
  3464. htt_tx_status, ring_id);
  3465. } else {
  3466. /*
  3467. * If the fast completion mode is enabled extended
  3468. * metadata from descriptor is not copied
  3469. */
  3470. if (qdf_likely(tx_desc->flags &
  3471. DP_TX_DESC_FLAG_SIMPLE)) {
  3472. tx_desc->peer_id =
  3473. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3474. tx_desc->tx_status =
  3475. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3476. goto add_to_pool;
  3477. }
  3478. /*
  3479. * If the descriptor is already freed in vdev_detach,
  3480. * continue to next descriptor
  3481. */
  3482. if (qdf_unlikely(!tx_desc->vdev) &&
  3483. qdf_unlikely(!tx_desc->flags)) {
  3484. QDF_TRACE(QDF_MODULE_ID_DP,
  3485. QDF_TRACE_LEVEL_INFO,
  3486. "Descriptor freed in vdev_detach %d",
  3487. tx_desc_id);
  3488. continue;
  3489. }
  3490. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3491. QDF_TRACE(QDF_MODULE_ID_DP,
  3492. QDF_TRACE_LEVEL_INFO,
  3493. "pdev in down state %d",
  3494. tx_desc_id);
  3495. dp_tx_comp_free_buf(soc, tx_desc);
  3496. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3497. goto next_desc;
  3498. }
  3499. /* Pool id is not matching. Error */
  3500. if (tx_desc->pool_id != pool_id) {
  3501. QDF_TRACE(QDF_MODULE_ID_DP,
  3502. QDF_TRACE_LEVEL_FATAL,
  3503. "Tx Comp pool id %d not matched %d",
  3504. pool_id, tx_desc->pool_id);
  3505. qdf_assert_always(0);
  3506. }
  3507. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3508. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3509. QDF_TRACE(QDF_MODULE_ID_DP,
  3510. QDF_TRACE_LEVEL_FATAL,
  3511. "Txdesc invalid, flgs = %x,id = %d",
  3512. tx_desc->flags, tx_desc_id);
  3513. qdf_assert_always(0);
  3514. }
  3515. /* Collect hw completion contents */
  3516. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3517. &tx_desc->comp, 1);
  3518. add_to_pool:
  3519. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3520. /* First ring descriptor on the cycle */
  3521. if (!head_desc) {
  3522. head_desc = tx_desc;
  3523. tail_desc = tx_desc;
  3524. }
  3525. tail_desc->next = tx_desc;
  3526. tx_desc->next = NULL;
  3527. tail_desc = tx_desc;
  3528. }
  3529. next_desc:
  3530. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3531. /*
  3532. * Processed packet count is more than given quota
  3533. * stop to processing
  3534. */
  3535. count++;
  3536. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3537. break;
  3538. }
  3539. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3540. /* Process the reaped descriptors */
  3541. if (head_desc)
  3542. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3543. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3544. if (num_processed >= quota)
  3545. force_break = true;
  3546. if (!force_break &&
  3547. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3548. hal_ring_hdl)) {
  3549. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3550. if (!hif_exec_should_yield(soc->hif_handle,
  3551. int_ctx->dp_intr_id))
  3552. goto more_data;
  3553. }
  3554. }
  3555. DP_TX_HIST_STATS_PER_PDEV();
  3556. return num_processed;
  3557. }
  3558. #ifdef FEATURE_WLAN_TDLS
  3559. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3560. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3561. {
  3562. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3563. struct dp_vdev *vdev = dp_get_vdev_from_soc_vdev_id_wifi3(soc, vdev_id);
  3564. if (!vdev) {
  3565. dp_err("vdev handle for id %d is NULL", vdev_id);
  3566. return NULL;
  3567. }
  3568. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3569. vdev->is_tdls_frame = true;
  3570. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3571. }
  3572. #endif
  3573. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  3574. {
  3575. struct wlan_cfg_dp_soc_ctxt *cfg;
  3576. struct dp_soc *soc;
  3577. soc = vdev->pdev->soc;
  3578. if (!soc)
  3579. return;
  3580. cfg = soc->wlan_cfg_ctx;
  3581. if (!cfg)
  3582. return;
  3583. if (vdev->opmode == wlan_op_mode_ndi)
  3584. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  3585. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  3586. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  3587. (vdev->subtype == wlan_op_subtype_p2p_go))
  3588. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  3589. else
  3590. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  3591. }
  3592. /**
  3593. * dp_tx_vdev_attach() - attach vdev to dp tx
  3594. * @vdev: virtual device instance
  3595. *
  3596. * Return: QDF_STATUS_SUCCESS: success
  3597. * QDF_STATUS_E_RESOURCES: Error return
  3598. */
  3599. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3600. {
  3601. int pdev_id;
  3602. /*
  3603. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3604. */
  3605. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3606. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3607. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3608. vdev->vdev_id);
  3609. pdev_id =
  3610. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  3611. vdev->pdev->pdev_id);
  3612. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  3613. /*
  3614. * Set HTT Extension Valid bit to 0 by default
  3615. */
  3616. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3617. dp_tx_vdev_update_search_flags(vdev);
  3618. dp_tx_vdev_update_feature_flags(vdev);
  3619. return QDF_STATUS_SUCCESS;
  3620. }
  3621. #ifndef FEATURE_WDS
  3622. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3623. {
  3624. return false;
  3625. }
  3626. #endif
  3627. /**
  3628. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3629. * @vdev: virtual device instance
  3630. *
  3631. * Return: void
  3632. *
  3633. */
  3634. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3635. {
  3636. struct dp_soc *soc = vdev->pdev->soc;
  3637. /*
  3638. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3639. * for TDLS link
  3640. *
  3641. * Enable AddrY (SA based search) only for non-WDS STA and
  3642. * ProxySTA VAP (in HKv1) modes.
  3643. *
  3644. * In all other VAP modes, only DA based search should be
  3645. * enabled
  3646. */
  3647. if (vdev->opmode == wlan_op_mode_sta &&
  3648. vdev->tdls_link_connected)
  3649. vdev->hal_desc_addr_search_flags =
  3650. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3651. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3652. !dp_tx_da_search_override(vdev))
  3653. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3654. else
  3655. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3656. /* Set search type only when peer map v2 messaging is enabled
  3657. * as we will have the search index (AST hash) only when v2 is
  3658. * enabled
  3659. */
  3660. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3661. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3662. else
  3663. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3664. }
  3665. static inline bool
  3666. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3667. struct dp_vdev *vdev,
  3668. struct dp_tx_desc_s *tx_desc)
  3669. {
  3670. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3671. return false;
  3672. /*
  3673. * if vdev is given, then only check whether desc
  3674. * vdev match. if vdev is NULL, then check whether
  3675. * desc pdev match.
  3676. */
  3677. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3678. }
  3679. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3680. /**
  3681. * dp_tx_desc_flush() - release resources associated
  3682. * to TX Desc
  3683. *
  3684. * @dp_pdev: Handle to DP pdev structure
  3685. * @vdev: virtual device instance
  3686. * NULL: no specific Vdev is required and check all allcated TX desc
  3687. * on this pdev.
  3688. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3689. *
  3690. * @force_free:
  3691. * true: flush the TX desc.
  3692. * false: only reset the Vdev in each allocated TX desc
  3693. * that associated to current Vdev.
  3694. *
  3695. * This function will go through the TX desc pool to flush
  3696. * the outstanding TX data or reset Vdev to NULL in associated TX
  3697. * Desc.
  3698. */
  3699. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3700. bool force_free)
  3701. {
  3702. uint8_t i;
  3703. uint32_t j;
  3704. uint32_t num_desc, page_id, offset;
  3705. uint16_t num_desc_per_page;
  3706. struct dp_soc *soc = pdev->soc;
  3707. struct dp_tx_desc_s *tx_desc = NULL;
  3708. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3709. if (!vdev && !force_free) {
  3710. dp_err("Reset TX desc vdev, Vdev param is required!");
  3711. return;
  3712. }
  3713. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3714. tx_desc_pool = &soc->tx_desc[i];
  3715. if (!(tx_desc_pool->pool_size) ||
  3716. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3717. !(tx_desc_pool->desc_pages.cacheable_pages))
  3718. continue;
  3719. /*
  3720. * Add flow pool lock protection in case pool is freed
  3721. * due to all tx_desc is recycled when handle TX completion.
  3722. * this is not necessary when do force flush as:
  3723. * a. double lock will happen if dp_tx_desc_release is
  3724. * also trying to acquire it.
  3725. * b. dp interrupt has been disabled before do force TX desc
  3726. * flush in dp_pdev_deinit().
  3727. */
  3728. if (!force_free)
  3729. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  3730. num_desc = tx_desc_pool->pool_size;
  3731. num_desc_per_page =
  3732. tx_desc_pool->desc_pages.num_element_per_page;
  3733. for (j = 0; j < num_desc; j++) {
  3734. page_id = j / num_desc_per_page;
  3735. offset = j % num_desc_per_page;
  3736. if (qdf_unlikely(!(tx_desc_pool->
  3737. desc_pages.cacheable_pages)))
  3738. break;
  3739. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3740. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3741. /*
  3742. * Free TX desc if force free is
  3743. * required, otherwise only reset vdev
  3744. * in this TX desc.
  3745. */
  3746. if (force_free) {
  3747. dp_tx_comp_free_buf(soc, tx_desc);
  3748. dp_tx_desc_release(tx_desc, i);
  3749. } else {
  3750. tx_desc->vdev = NULL;
  3751. }
  3752. }
  3753. }
  3754. if (!force_free)
  3755. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  3756. }
  3757. }
  3758. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3759. /**
  3760. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3761. *
  3762. * @soc: Handle to DP soc structure
  3763. * @tx_desc: pointer of one TX desc
  3764. * @desc_pool_id: TX Desc pool id
  3765. */
  3766. static inline void
  3767. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3768. uint8_t desc_pool_id)
  3769. {
  3770. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3771. tx_desc->vdev = NULL;
  3772. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3773. }
  3774. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3775. bool force_free)
  3776. {
  3777. uint8_t i, num_pool;
  3778. uint32_t j;
  3779. uint32_t num_desc, page_id, offset;
  3780. uint16_t num_desc_per_page;
  3781. struct dp_soc *soc = pdev->soc;
  3782. struct dp_tx_desc_s *tx_desc = NULL;
  3783. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3784. if (!vdev && !force_free) {
  3785. dp_err("Reset TX desc vdev, Vdev param is required!");
  3786. return;
  3787. }
  3788. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3789. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3790. for (i = 0; i < num_pool; i++) {
  3791. tx_desc_pool = &soc->tx_desc[i];
  3792. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3793. continue;
  3794. num_desc_per_page =
  3795. tx_desc_pool->desc_pages.num_element_per_page;
  3796. for (j = 0; j < num_desc; j++) {
  3797. page_id = j / num_desc_per_page;
  3798. offset = j % num_desc_per_page;
  3799. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3800. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3801. if (force_free) {
  3802. dp_tx_comp_free_buf(soc, tx_desc);
  3803. dp_tx_desc_release(tx_desc, i);
  3804. } else {
  3805. dp_tx_desc_reset_vdev(soc, tx_desc,
  3806. i);
  3807. }
  3808. }
  3809. }
  3810. }
  3811. }
  3812. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3813. /**
  3814. * dp_tx_vdev_detach() - detach vdev from dp tx
  3815. * @vdev: virtual device instance
  3816. *
  3817. * Return: QDF_STATUS_SUCCESS: success
  3818. * QDF_STATUS_E_RESOURCES: Error return
  3819. */
  3820. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3821. {
  3822. struct dp_pdev *pdev = vdev->pdev;
  3823. /* Reset TX desc associated to this Vdev as NULL */
  3824. dp_tx_desc_flush(pdev, vdev, false);
  3825. dp_tx_vdev_multipass_deinit(vdev);
  3826. return QDF_STATUS_SUCCESS;
  3827. }
  3828. /**
  3829. * dp_tx_pdev_attach() - attach pdev to dp tx
  3830. * @pdev: physical device instance
  3831. *
  3832. * Return: QDF_STATUS_SUCCESS: success
  3833. * QDF_STATUS_E_RESOURCES: Error return
  3834. */
  3835. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  3836. {
  3837. struct dp_soc *soc = pdev->soc;
  3838. /* Initialize Flow control counters */
  3839. qdf_atomic_init(&pdev->num_tx_outstanding);
  3840. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3841. /* Initialize descriptors in TCL Ring */
  3842. hal_tx_init_data_ring(soc->hal_soc,
  3843. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3844. }
  3845. return QDF_STATUS_SUCCESS;
  3846. }
  3847. /**
  3848. * dp_tx_pdev_detach() - detach pdev from dp tx
  3849. * @pdev: physical device instance
  3850. *
  3851. * Return: QDF_STATUS_SUCCESS: success
  3852. * QDF_STATUS_E_RESOURCES: Error return
  3853. */
  3854. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3855. {
  3856. /* flush TX outstanding data per pdev */
  3857. dp_tx_desc_flush(pdev, NULL, true);
  3858. dp_tx_me_exit(pdev);
  3859. return QDF_STATUS_SUCCESS;
  3860. }
  3861. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3862. /* Pools will be allocated dynamically */
  3863. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3864. int num_desc)
  3865. {
  3866. uint8_t i;
  3867. for (i = 0; i < num_pool; i++) {
  3868. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3869. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3870. }
  3871. return QDF_STATUS_SUCCESS;
  3872. }
  3873. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  3874. int num_desc)
  3875. {
  3876. return QDF_STATUS_SUCCESS;
  3877. }
  3878. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  3879. {
  3880. }
  3881. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3882. {
  3883. uint8_t i;
  3884. for (i = 0; i < num_pool; i++)
  3885. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3886. }
  3887. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3888. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3889. int num_desc)
  3890. {
  3891. uint8_t i, count;
  3892. /* Allocate software Tx descriptor pools */
  3893. for (i = 0; i < num_pool; i++) {
  3894. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3895. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3896. FL("Tx Desc Pool alloc %d failed %pK"),
  3897. i, soc);
  3898. goto fail;
  3899. }
  3900. }
  3901. return QDF_STATUS_SUCCESS;
  3902. fail:
  3903. for (count = 0; count < i; count++)
  3904. dp_tx_desc_pool_free(soc, count);
  3905. return QDF_STATUS_E_NOMEM;
  3906. }
  3907. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  3908. int num_desc)
  3909. {
  3910. uint8_t i;
  3911. for (i = 0; i < num_pool; i++) {
  3912. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  3913. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3914. FL("Tx Desc Pool init %d failed %pK"),
  3915. i, soc);
  3916. return QDF_STATUS_E_NOMEM;
  3917. }
  3918. }
  3919. return QDF_STATUS_SUCCESS;
  3920. }
  3921. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  3922. {
  3923. uint8_t i;
  3924. for (i = 0; i < num_pool; i++)
  3925. dp_tx_desc_pool_deinit(soc, i);
  3926. }
  3927. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3928. {
  3929. uint8_t i;
  3930. for (i = 0; i < num_pool; i++)
  3931. dp_tx_desc_pool_free(soc, i);
  3932. }
  3933. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3934. /**
  3935. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  3936. * @soc: core txrx main context
  3937. * @num_pool: number of pools
  3938. *
  3939. */
  3940. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  3941. {
  3942. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  3943. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  3944. }
  3945. /**
  3946. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  3947. * @soc: core txrx main context
  3948. * @num_pool: number of pools
  3949. *
  3950. */
  3951. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  3952. {
  3953. dp_tx_tso_desc_pool_free(soc, num_pool);
  3954. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  3955. }
  3956. /**
  3957. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  3958. * @soc: core txrx main context
  3959. *
  3960. * This function frees all tx related descriptors as below
  3961. * 1. Regular TX descriptors (static pools)
  3962. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  3963. * 3. TSO descriptors
  3964. *
  3965. */
  3966. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  3967. {
  3968. uint8_t num_pool;
  3969. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3970. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  3971. dp_tx_ext_desc_pool_free(soc, num_pool);
  3972. dp_tx_delete_static_pools(soc, num_pool);
  3973. }
  3974. /**
  3975. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  3976. * @soc: core txrx main context
  3977. *
  3978. * This function de-initializes all tx related descriptors as below
  3979. * 1. Regular TX descriptors (static pools)
  3980. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  3981. * 3. TSO descriptors
  3982. *
  3983. */
  3984. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  3985. {
  3986. uint8_t num_pool;
  3987. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3988. dp_tx_flow_control_deinit(soc);
  3989. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  3990. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  3991. dp_tx_deinit_static_pools(soc, num_pool);
  3992. }
  3993. /**
  3994. * dp_tso_attach() - TSO attach handler
  3995. * @txrx_soc: Opaque Dp handle
  3996. *
  3997. * Reserve TSO descriptor buffers
  3998. *
  3999. * Return: QDF_STATUS_E_FAILURE on failure or
  4000. * QDF_STATUS_SUCCESS on success
  4001. */
  4002. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4003. uint8_t num_pool,
  4004. uint16_t num_desc)
  4005. {
  4006. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4007. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4008. return QDF_STATUS_E_FAILURE;
  4009. }
  4010. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4011. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4012. num_pool, soc);
  4013. return QDF_STATUS_E_FAILURE;
  4014. }
  4015. return QDF_STATUS_SUCCESS;
  4016. }
  4017. /**
  4018. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4019. * @soc: DP soc handle
  4020. * @num_pool: Number of pools
  4021. * @num_desc: Number of descriptors
  4022. *
  4023. * Initialize TSO descriptor pools
  4024. *
  4025. * Return: QDF_STATUS_E_FAILURE on failure or
  4026. * QDF_STATUS_SUCCESS on success
  4027. */
  4028. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4029. uint8_t num_pool,
  4030. uint16_t num_desc)
  4031. {
  4032. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4033. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4034. return QDF_STATUS_E_FAILURE;
  4035. }
  4036. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4037. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4038. num_pool, soc);
  4039. return QDF_STATUS_E_FAILURE;
  4040. }
  4041. return QDF_STATUS_SUCCESS;
  4042. }
  4043. /**
  4044. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4045. * @soc: core txrx main context
  4046. *
  4047. * This function allocates memory for following descriptor pools
  4048. * 1. regular sw tx descriptor pools (static pools)
  4049. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4050. * 3. TSO descriptor pools
  4051. *
  4052. * Return: QDF_STATUS_SUCCESS: success
  4053. * QDF_STATUS_E_RESOURCES: Error return
  4054. */
  4055. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4056. {
  4057. uint8_t num_pool;
  4058. uint32_t num_desc;
  4059. uint32_t num_ext_desc;
  4060. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4061. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4062. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4063. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4064. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4065. __func__, num_pool, num_desc);
  4066. if ((num_pool > MAX_TXDESC_POOLS) ||
  4067. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4068. goto fail1;
  4069. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4070. goto fail1;
  4071. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4072. goto fail2;
  4073. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4074. return QDF_STATUS_SUCCESS;
  4075. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4076. goto fail3;
  4077. return QDF_STATUS_SUCCESS;
  4078. fail3:
  4079. dp_tx_ext_desc_pool_free(soc, num_pool);
  4080. fail2:
  4081. dp_tx_delete_static_pools(soc, num_pool);
  4082. fail1:
  4083. return QDF_STATUS_E_RESOURCES;
  4084. }
  4085. /**
  4086. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4087. * @soc: core txrx main context
  4088. *
  4089. * This function initializes the following TX descriptor pools
  4090. * 1. regular sw tx descriptor pools (static pools)
  4091. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4092. * 3. TSO descriptor pools
  4093. *
  4094. * Return: QDF_STATUS_SUCCESS: success
  4095. * QDF_STATUS_E_RESOURCES: Error return
  4096. */
  4097. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4098. {
  4099. uint8_t num_pool;
  4100. uint32_t num_desc;
  4101. uint32_t num_ext_desc;
  4102. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4103. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4104. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4105. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4106. goto fail1;
  4107. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4108. goto fail2;
  4109. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4110. return QDF_STATUS_SUCCESS;
  4111. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4112. goto fail3;
  4113. dp_tx_flow_control_init(soc);
  4114. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4115. return QDF_STATUS_SUCCESS;
  4116. fail3:
  4117. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4118. fail2:
  4119. dp_tx_deinit_static_pools(soc, num_pool);
  4120. fail1:
  4121. return QDF_STATUS_E_RESOURCES;
  4122. }
  4123. /**
  4124. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4125. * @txrx_soc: dp soc handle
  4126. *
  4127. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4128. * QDF_STATUS_E_FAILURE
  4129. */
  4130. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4131. {
  4132. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4133. uint8_t num_pool;
  4134. uint32_t num_desc;
  4135. uint32_t num_ext_desc;
  4136. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4137. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4138. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4139. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4140. return QDF_STATUS_E_FAILURE;
  4141. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4142. return QDF_STATUS_E_FAILURE;
  4143. return QDF_STATUS_SUCCESS;
  4144. }
  4145. /**
  4146. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4147. * @txrx_soc: dp soc handle
  4148. *
  4149. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4150. */
  4151. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4152. {
  4153. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4154. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4155. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4156. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4157. return QDF_STATUS_SUCCESS;
  4158. }