msm_smem.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/dma-buf.h>
  6. #include <linux/dma-direction.h>
  7. #include <linux/iommu.h>
  8. #include <linux/msm_dma_iommu_mapping.h>
  9. #include <linux/ion.h>
  10. #include <linux/msm_ion.h>
  11. #include <linux/slab.h>
  12. #include <linux/types.h>
  13. #include "msm_cvp_core.h"
  14. #include "msm_cvp_debug.h"
  15. #include "msm_cvp_resources.h"
  16. #include "cvp_core_hfi.h"
  17. static int msm_dma_get_device_address(struct dma_buf *dbuf, u32 align,
  18. dma_addr_t *iova, u32 flags, unsigned long ion_flags,
  19. struct msm_cvp_platform_resources *res,
  20. struct cvp_dma_mapping_info *mapping_info)
  21. {
  22. int rc = 0;
  23. struct dma_buf_attachment *attach;
  24. struct sg_table *table = NULL;
  25. struct context_bank_info *cb = NULL;
  26. if (!dbuf || !iova || !mapping_info) {
  27. dprintk(CVP_ERR, "Invalid params: %pK, %pK, %pK\n",
  28. dbuf, iova, mapping_info);
  29. return -EINVAL;
  30. }
  31. if (is_iommu_present(res)) {
  32. cb = msm_cvp_smem_get_context_bank((flags & SMEM_SECURE),
  33. res, ion_flags);
  34. if (!cb) {
  35. dprintk(CVP_ERR,
  36. "%s: Failed to get context bank device\n",
  37. __func__);
  38. rc = -EIO;
  39. goto mem_map_failed;
  40. }
  41. /* Prepare a dma buf for dma on the given device */
  42. attach = dma_buf_attach(dbuf, cb->dev);
  43. if (IS_ERR_OR_NULL(attach)) {
  44. rc = PTR_ERR(attach) ?: -ENOMEM;
  45. dprintk(CVP_ERR, "Failed to attach dmabuf\n");
  46. goto mem_buf_attach_failed;
  47. }
  48. /*
  49. * Get the scatterlist for the given attachment
  50. * Mapping of sg is taken care by map attachment
  51. */
  52. attach->dma_map_attrs = DMA_ATTR_DELAYED_UNMAP;
  53. /*
  54. * We do not need dma_map function to perform cache operations
  55. * on the whole buffer size and hence pass skip sync flag.
  56. * We do the required cache operations separately for the
  57. * required buffer size
  58. */
  59. attach->dma_map_attrs |= DMA_ATTR_SKIP_CPU_SYNC;
  60. if (res->sys_cache_present)
  61. attach->dma_map_attrs |=
  62. DMA_ATTR_IOMMU_USE_UPSTREAM_HINT;
  63. table = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
  64. if (IS_ERR_OR_NULL(table)) {
  65. rc = PTR_ERR(table) ?: -ENOMEM;
  66. dprintk(CVP_ERR, "Failed to map table\n");
  67. goto mem_map_table_failed;
  68. }
  69. if (table->sgl) {
  70. *iova = table->sgl->dma_address;
  71. } else {
  72. dprintk(CVP_ERR, "sgl is NULL\n");
  73. rc = -ENOMEM;
  74. goto mem_map_sg_failed;
  75. }
  76. mapping_info->dev = cb->dev;
  77. mapping_info->domain = cb->domain;
  78. mapping_info->table = table;
  79. mapping_info->attach = attach;
  80. mapping_info->buf = dbuf;
  81. mapping_info->cb_info = (void *)cb;
  82. } else {
  83. dprintk(CVP_MEM, "iommu not present, use phys mem addr\n");
  84. }
  85. return 0;
  86. mem_map_sg_failed:
  87. dma_buf_unmap_attachment(attach, table, DMA_BIDIRECTIONAL);
  88. mem_map_table_failed:
  89. dma_buf_detach(dbuf, attach);
  90. mem_buf_attach_failed:
  91. mem_map_failed:
  92. return rc;
  93. }
  94. static int msm_dma_put_device_address(u32 flags,
  95. struct cvp_dma_mapping_info *mapping_info)
  96. {
  97. int rc = 0;
  98. if (!mapping_info) {
  99. dprintk(CVP_WARN, "Invalid mapping_info\n");
  100. return -EINVAL;
  101. }
  102. if (!mapping_info->dev || !mapping_info->table ||
  103. !mapping_info->buf || !mapping_info->attach ||
  104. !mapping_info->cb_info) {
  105. dprintk(CVP_WARN, "Invalid params\n");
  106. return -EINVAL;
  107. }
  108. dma_buf_unmap_attachment(mapping_info->attach,
  109. mapping_info->table, DMA_BIDIRECTIONAL);
  110. dma_buf_detach(mapping_info->buf, mapping_info->attach);
  111. mapping_info->dev = NULL;
  112. mapping_info->domain = NULL;
  113. mapping_info->table = NULL;
  114. mapping_info->attach = NULL;
  115. mapping_info->buf = NULL;
  116. mapping_info->cb_info = NULL;
  117. return rc;
  118. }
  119. struct dma_buf *msm_cvp_smem_get_dma_buf(int fd)
  120. {
  121. struct dma_buf *dma_buf;
  122. dma_buf = dma_buf_get(fd);
  123. if (IS_ERR_OR_NULL(dma_buf)) {
  124. dprintk(CVP_ERR, "Failed to get dma_buf for %d, error %ld\n",
  125. fd, PTR_ERR(dma_buf));
  126. dma_buf = NULL;
  127. }
  128. return dma_buf;
  129. }
  130. void msm_cvp_smem_put_dma_buf(void *dma_buf)
  131. {
  132. if (!dma_buf) {
  133. dprintk(CVP_ERR, "%s: NULL dma_buf\n", __func__);
  134. return;
  135. }
  136. dma_buf_put((struct dma_buf *)dma_buf);
  137. }
  138. int msm_cvp_map_smem(struct msm_cvp_inst *inst,
  139. struct msm_cvp_smem *smem,
  140. const char *str)
  141. {
  142. int rc = 0;
  143. dma_addr_t iova = 0;
  144. u32 temp = 0;
  145. u32 align = SZ_4K;
  146. struct dma_buf *dma_buf;
  147. unsigned long ion_flags = 0;
  148. if (!inst || !smem) {
  149. dprintk(CVP_ERR, "%s: Invalid params: %pK %pK\n",
  150. __func__, inst, smem);
  151. return -EINVAL;
  152. }
  153. dma_buf = smem->dma_buf;
  154. rc = dma_buf_get_flags(dma_buf, &ion_flags);
  155. if (rc) {
  156. dprintk(CVP_ERR, "Failed to get dma buf flags: %d\n", rc);
  157. goto exit;
  158. }
  159. if (ion_flags & ION_FLAG_CACHED)
  160. smem->flags |= SMEM_CACHED;
  161. if (ion_flags & ION_FLAG_SECURE)
  162. smem->flags |= SMEM_SECURE;
  163. rc = msm_dma_get_device_address(dma_buf, align, &iova, smem->flags,
  164. ion_flags, &(inst->core->resources),
  165. &smem->mapping_info);
  166. if (rc) {
  167. dprintk(CVP_ERR, "Failed to get device address: %d\n", rc);
  168. goto exit;
  169. }
  170. temp = (u32)iova;
  171. if ((dma_addr_t)temp != iova) {
  172. dprintk(CVP_ERR, "iova(%pa) truncated to %#x", &iova, temp);
  173. rc = -EINVAL;
  174. goto exit;
  175. }
  176. smem->size = dma_buf->size;
  177. smem->device_addr = (u32)iova;
  178. print_smem(CVP_MEM, str, inst, smem);
  179. return rc;
  180. exit:
  181. smem->device_addr = 0x0;
  182. return rc;
  183. }
  184. int msm_cvp_unmap_smem(struct msm_cvp_inst *inst,
  185. struct msm_cvp_smem *smem,
  186. const char *str)
  187. {
  188. int rc = 0;
  189. if (!smem) {
  190. dprintk(CVP_ERR, "%s: Invalid params: %pK\n", __func__, smem);
  191. rc = -EINVAL;
  192. goto exit;
  193. }
  194. print_smem(CVP_MEM, str, inst, smem);
  195. rc = msm_dma_put_device_address(smem->flags, &smem->mapping_info);
  196. if (rc) {
  197. dprintk(CVP_ERR, "Failed to put device address: %d\n", rc);
  198. goto exit;
  199. }
  200. smem->device_addr = 0x0;
  201. exit:
  202. return rc;
  203. }
  204. static int alloc_dma_mem(size_t size, u32 align, u32 flags, int map_kernel,
  205. struct msm_cvp_platform_resources *res, struct msm_cvp_smem *mem)
  206. {
  207. dma_addr_t iova = 0;
  208. unsigned long heap_mask = 0;
  209. int rc = 0;
  210. int ion_flags = 0;
  211. struct dma_buf *dbuf = NULL;
  212. if (!res) {
  213. dprintk(CVP_ERR, "%s: NULL res\n", __func__);
  214. return -EINVAL;
  215. }
  216. align = ALIGN(align, SZ_4K);
  217. size = ALIGN(size, SZ_4K);
  218. if (is_iommu_present(res)) {
  219. if (flags & SMEM_ADSP) {
  220. dprintk(CVP_MEM, "Allocating from ADSP heap\n");
  221. heap_mask = ION_HEAP(ION_ADSP_HEAP_ID);
  222. } else {
  223. heap_mask = ION_HEAP(ION_SYSTEM_HEAP_ID);
  224. }
  225. } else {
  226. dprintk(CVP_MEM,
  227. "allocate shared memory from adsp heap size %zx align %d\n",
  228. size, align);
  229. heap_mask = ION_HEAP(ION_ADSP_HEAP_ID);
  230. }
  231. if (flags & SMEM_CACHED)
  232. ion_flags |= ION_FLAG_CACHED;
  233. if (flags & SMEM_NON_PIXEL)
  234. ion_flags |= ION_FLAG_CP_NON_PIXEL;
  235. if (flags & SMEM_SECURE) {
  236. ion_flags |= ION_FLAG_SECURE;
  237. heap_mask = ION_HEAP(ION_SECURE_HEAP_ID);
  238. }
  239. dbuf = ion_alloc(size, heap_mask, ion_flags);
  240. if (IS_ERR_OR_NULL(dbuf)) {
  241. dprintk(CVP_ERR,
  242. "Failed to allocate shared memory = %x bytes, %llx, %x %x\n",
  243. size, heap_mask, ion_flags, PTR_ERR(dbuf));
  244. rc = -ENOMEM;
  245. goto fail_shared_mem_alloc;
  246. }
  247. mem->flags = flags;
  248. mem->ion_flags = ion_flags;
  249. mem->size = size;
  250. mem->dma_buf = dbuf;
  251. mem->kvaddr = NULL;
  252. rc = msm_dma_get_device_address(dbuf, align, &iova, flags,
  253. ion_flags, res, &mem->mapping_info);
  254. if (rc) {
  255. dprintk(CVP_ERR, "Failed to get device address: %d\n",
  256. rc);
  257. goto fail_device_address;
  258. }
  259. mem->device_addr = (u32)iova;
  260. if ((dma_addr_t)mem->device_addr != iova) {
  261. dprintk(CVP_ERR, "iova(%pa) truncated to %#x",
  262. &iova, mem->device_addr);
  263. goto fail_device_address;
  264. }
  265. if (map_kernel) {
  266. dma_buf_begin_cpu_access(dbuf, DMA_BIDIRECTIONAL);
  267. mem->kvaddr = dma_buf_vmap(dbuf);
  268. if (!mem->kvaddr) {
  269. dprintk(CVP_ERR,
  270. "Failed to map shared mem in kernel\n");
  271. rc = -EIO;
  272. goto fail_map;
  273. }
  274. }
  275. dprintk(CVP_MEM,
  276. "%s: dma_buf = %pK, device_addr = %x, size = %d, kvaddr = %pK, ion_flags = %#x, flags = %#lx\n",
  277. __func__, mem->dma_buf, mem->device_addr, mem->size,
  278. mem->kvaddr, mem->ion_flags, mem->flags);
  279. return rc;
  280. fail_map:
  281. if (map_kernel)
  282. dma_buf_end_cpu_access(dbuf, DMA_BIDIRECTIONAL);
  283. fail_device_address:
  284. dma_buf_put(dbuf);
  285. fail_shared_mem_alloc:
  286. return rc;
  287. }
  288. static int free_dma_mem(struct msm_cvp_smem *mem)
  289. {
  290. dprintk(CVP_MEM,
  291. "%s: dma_buf = %pK, device_addr = %x, size = %d, kvaddr = %pK, ion_flags = %#x\n",
  292. __func__, mem->dma_buf, mem->device_addr, mem->size,
  293. mem->kvaddr, mem->ion_flags);
  294. if (mem->device_addr) {
  295. msm_dma_put_device_address(mem->flags, &mem->mapping_info);
  296. mem->device_addr = 0x0;
  297. }
  298. if (mem->kvaddr) {
  299. dma_buf_vunmap(mem->dma_buf, mem->kvaddr);
  300. mem->kvaddr = NULL;
  301. dma_buf_end_cpu_access(mem->dma_buf, DMA_BIDIRECTIONAL);
  302. }
  303. if (mem->dma_buf) {
  304. dma_buf_put(mem->dma_buf);
  305. mem->dma_buf = NULL;
  306. }
  307. return 0;
  308. }
  309. int msm_cvp_smem_alloc(size_t size, u32 align, u32 flags, int map_kernel,
  310. void *res, struct msm_cvp_smem *smem)
  311. {
  312. int rc = 0;
  313. if (!smem || !size) {
  314. dprintk(CVP_ERR, "%s: NULL smem or %d size\n",
  315. __func__, (u32)size);
  316. return -EINVAL;
  317. }
  318. rc = alloc_dma_mem(size, align, flags, map_kernel,
  319. (struct msm_cvp_platform_resources *)res,
  320. smem);
  321. return rc;
  322. }
  323. int msm_cvp_smem_free(struct msm_cvp_smem *smem)
  324. {
  325. int rc = 0;
  326. if (!smem) {
  327. dprintk(CVP_ERR, "NULL smem passed\n");
  328. return -EINVAL;
  329. }
  330. rc = free_dma_mem(smem);
  331. return rc;
  332. };
  333. int msm_cvp_smem_cache_operations(struct dma_buf *dbuf,
  334. enum smem_cache_ops cache_op, unsigned long offset, unsigned long size)
  335. {
  336. int rc = 0;
  337. unsigned long flags = 0;
  338. if (!dbuf) {
  339. dprintk(CVP_ERR, "%s: Invalid params\n", __func__);
  340. return -EINVAL;
  341. }
  342. /* Return if buffer doesn't support caching */
  343. rc = dma_buf_get_flags(dbuf, &flags);
  344. if (rc) {
  345. dprintk(CVP_ERR, "%s: dma_buf_get_flags failed, err %d\n",
  346. __func__, rc);
  347. return rc;
  348. } else if (!(flags & ION_FLAG_CACHED)) {
  349. return rc;
  350. }
  351. switch (cache_op) {
  352. case SMEM_CACHE_CLEAN:
  353. case SMEM_CACHE_CLEAN_INVALIDATE:
  354. rc = dma_buf_begin_cpu_access_partial(dbuf, DMA_BIDIRECTIONAL,
  355. offset, size);
  356. if (rc)
  357. break;
  358. rc = dma_buf_end_cpu_access_partial(dbuf, DMA_BIDIRECTIONAL,
  359. offset, size);
  360. break;
  361. case SMEM_CACHE_INVALIDATE:
  362. rc = dma_buf_begin_cpu_access_partial(dbuf, DMA_TO_DEVICE,
  363. offset, size);
  364. if (rc)
  365. break;
  366. rc = dma_buf_end_cpu_access_partial(dbuf, DMA_FROM_DEVICE,
  367. offset, size);
  368. break;
  369. default:
  370. dprintk(CVP_ERR, "%s: cache (%d) operation not supported\n",
  371. __func__, cache_op);
  372. rc = -EINVAL;
  373. break;
  374. }
  375. return rc;
  376. }
  377. struct context_bank_info *msm_cvp_smem_get_context_bank(bool is_secure,
  378. struct msm_cvp_platform_resources *res, unsigned long ion_flags)
  379. {
  380. struct context_bank_info *cb = NULL, *match = NULL;
  381. char *search_str;
  382. char *non_secure_cb = "cvp_hlos";
  383. char *secure_nonpixel_cb = "cvp_sec_nonpixel";
  384. char *secure_pixel_cb = "cvp_sec_pixel";
  385. if (ion_flags & ION_FLAG_CP_PIXEL)
  386. search_str = secure_pixel_cb;
  387. else if (ion_flags & ION_FLAG_CP_NON_PIXEL)
  388. search_str = secure_nonpixel_cb;
  389. else
  390. search_str = non_secure_cb;
  391. list_for_each_entry(cb, &res->context_banks, list) {
  392. if (cb->is_secure == is_secure &&
  393. !strcmp(search_str, cb->name)) {
  394. match = cb;
  395. break;
  396. }
  397. }
  398. if (!match)
  399. dprintk(CVP_ERR,
  400. "%s: cb not found for ion_flags %x, is_secure %d\n",
  401. __func__, ion_flags, is_secure);
  402. return match;
  403. }
  404. int msm_cvp_map_ipcc_regs(u32 *iova)
  405. {
  406. struct context_bank_info *cb;
  407. struct msm_cvp_core *core;
  408. struct cvp_hfi_device *hfi_ops;
  409. struct iris_hfi_device *dev = NULL;
  410. phys_addr_t paddr;
  411. u32 size;
  412. core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
  413. if (core) {
  414. hfi_ops = core->device;
  415. if (hfi_ops)
  416. dev = hfi_ops->hfi_device_data;
  417. }
  418. if (!dev)
  419. return -EINVAL;
  420. paddr = dev->res->ipcc_reg_base;
  421. size = dev->res->ipcc_reg_size;
  422. if (!paddr || !size)
  423. return -EINVAL;
  424. cb = msm_cvp_smem_get_context_bank(false, dev->res, 0);
  425. if (!cb) {
  426. dprintk(CVP_ERR, "%s: fail to get context bank\n", __func__);
  427. return -EINVAL;
  428. }
  429. *iova = dma_map_resource(cb->dev, paddr, size, DMA_BIDIRECTIONAL, 0);
  430. if (*iova == DMA_MAPPING_ERROR) {
  431. dprintk(CVP_WARN, "%s: fail to map IPCC regs\n", __func__);
  432. return -EFAULT;
  433. }
  434. return 0;
  435. }