dp_tx.c 158 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef QCA_DP_TX_FW_METADATA_V2
  66. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  67. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  68. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  69. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  78. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  79. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  80. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  81. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  82. #else
  83. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  84. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  85. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  86. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  95. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  96. HTT_TCL_METADATA_TYPE_PEER_BASED
  97. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  98. HTT_TCL_METADATA_TYPE_VDEV_BASED
  99. #endif
  100. /*mapping between hal encrypt type and cdp_sec_type*/
  101. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  102. HAL_TX_ENCRYPT_TYPE_WEP_128,
  103. HAL_TX_ENCRYPT_TYPE_WEP_104,
  104. HAL_TX_ENCRYPT_TYPE_WEP_40,
  105. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  106. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  107. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  108. HAL_TX_ENCRYPT_TYPE_WAPI,
  109. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  110. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  111. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  112. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  113. qdf_export_symbol(sec_type_map);
  114. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  115. /**
  116. * dp_update_tx_desc_stats - Update the increase or decrease in
  117. * outstanding tx desc count
  118. * values on pdev and soc
  119. * @vdev: DP pdev handle
  120. *
  121. * Return: void
  122. */
  123. static inline void
  124. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  125. {
  126. int32_t tx_descs_cnt =
  127. qdf_atomic_read(&pdev->num_tx_outstanding);
  128. if (pdev->tx_descs_max < tx_descs_cnt)
  129. pdev->tx_descs_max = tx_descs_cnt;
  130. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  131. pdev->tx_descs_max);
  132. }
  133. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  134. static inline void
  135. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  136. {
  137. }
  138. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  139. #ifdef QCA_TX_LIMIT_CHECK
  140. /**
  141. * dp_tx_limit_check - Check if allocated tx descriptors reached
  142. * soc max limit and pdev max limit
  143. * @vdev: DP vdev handle
  144. *
  145. * Return: true if allocated tx descriptors reached max configured value, else
  146. * false
  147. */
  148. static inline bool
  149. dp_tx_limit_check(struct dp_vdev *vdev)
  150. {
  151. struct dp_pdev *pdev = vdev->pdev;
  152. struct dp_soc *soc = pdev->soc;
  153. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  154. soc->num_tx_allowed) {
  155. dp_tx_info("queued packets are more than max tx, drop the frame");
  156. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  157. return true;
  158. }
  159. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  160. pdev->num_tx_allowed) {
  161. dp_tx_info("queued packets are more than max tx, drop the frame");
  162. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  163. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  164. return true;
  165. }
  166. return false;
  167. }
  168. /**
  169. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  170. * reached soc max limit
  171. * @vdev: DP vdev handle
  172. *
  173. * Return: true if allocated tx descriptors reached max configured value, else
  174. * false
  175. */
  176. static inline bool
  177. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  178. {
  179. struct dp_pdev *pdev = vdev->pdev;
  180. struct dp_soc *soc = pdev->soc;
  181. if (qdf_atomic_read(&soc->num_tx_exception) >=
  182. soc->num_msdu_exception_desc) {
  183. dp_info("exc packets are more than max drop the exc pkt");
  184. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  185. return true;
  186. }
  187. return false;
  188. }
  189. /**
  190. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  191. * @vdev: DP pdev handle
  192. *
  193. * Return: void
  194. */
  195. static inline void
  196. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  197. {
  198. struct dp_soc *soc = pdev->soc;
  199. qdf_atomic_inc(&pdev->num_tx_outstanding);
  200. qdf_atomic_inc(&soc->num_tx_outstanding);
  201. dp_update_tx_desc_stats(pdev);
  202. }
  203. /**
  204. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  205. * @vdev: DP pdev handle
  206. *
  207. * Return: void
  208. */
  209. static inline void
  210. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  211. {
  212. struct dp_soc *soc = pdev->soc;
  213. qdf_atomic_dec(&pdev->num_tx_outstanding);
  214. qdf_atomic_dec(&soc->num_tx_outstanding);
  215. dp_update_tx_desc_stats(pdev);
  216. }
  217. #else //QCA_TX_LIMIT_CHECK
  218. static inline bool
  219. dp_tx_limit_check(struct dp_vdev *vdev)
  220. {
  221. return false;
  222. }
  223. static inline bool
  224. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  225. {
  226. return false;
  227. }
  228. static inline void
  229. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  230. {
  231. qdf_atomic_inc(&pdev->num_tx_outstanding);
  232. dp_update_tx_desc_stats(pdev);
  233. }
  234. static inline void
  235. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  236. {
  237. qdf_atomic_dec(&pdev->num_tx_outstanding);
  238. dp_update_tx_desc_stats(pdev);
  239. }
  240. #endif //QCA_TX_LIMIT_CHECK
  241. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  242. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  243. {
  244. enum dp_tx_event_type type;
  245. if (flags & DP_TX_DESC_FLAG_FLUSH)
  246. type = DP_TX_DESC_FLUSH;
  247. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  248. type = DP_TX_COMP_UNMAP_ERR;
  249. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  250. type = DP_TX_COMP_UNMAP;
  251. else
  252. type = DP_TX_DESC_UNMAP;
  253. return type;
  254. }
  255. static inline void
  256. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  257. qdf_nbuf_t skb, uint32_t sw_cookie,
  258. enum dp_tx_event_type type)
  259. {
  260. struct dp_tx_desc_event *entry;
  261. uint32_t idx;
  262. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  263. return;
  264. switch (type) {
  265. case DP_TX_COMP_UNMAP:
  266. case DP_TX_COMP_UNMAP_ERR:
  267. case DP_TX_COMP_MSDU_EXT:
  268. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  269. DP_TX_COMP_HISTORY_SIZE);
  270. entry = &soc->tx_comp_history->entry[idx];
  271. break;
  272. case DP_TX_DESC_MAP:
  273. case DP_TX_DESC_UNMAP:
  274. case DP_TX_DESC_COOKIE:
  275. case DP_TX_DESC_FLUSH:
  276. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  277. DP_TX_TCL_HISTORY_SIZE);
  278. entry = &soc->tx_tcl_history->entry[idx];
  279. break;
  280. default:
  281. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  282. return;
  283. }
  284. entry->skb = skb;
  285. entry->paddr = paddr;
  286. entry->sw_cookie = sw_cookie;
  287. entry->type = type;
  288. entry->ts = qdf_get_log_timestamp();
  289. }
  290. static inline void
  291. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  292. struct qdf_tso_seg_elem_t *tso_seg,
  293. qdf_nbuf_t skb, uint32_t sw_cookie,
  294. enum dp_tx_event_type type)
  295. {
  296. int i;
  297. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  298. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  299. skb, sw_cookie, type);
  300. }
  301. if (!tso_seg->next)
  302. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  303. skb, 0xFFFFFFFF, type);
  304. }
  305. static inline void
  306. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  307. qdf_nbuf_t skb, uint32_t sw_cookie,
  308. enum dp_tx_event_type type)
  309. {
  310. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  311. uint32_t num_segs = tso_info.num_segs;
  312. while (num_segs) {
  313. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  314. curr_seg = curr_seg->next;
  315. num_segs--;
  316. }
  317. }
  318. #else
  319. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  320. {
  321. return DP_TX_DESC_INVAL_EVT;
  322. }
  323. static inline void
  324. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  325. qdf_nbuf_t skb, uint32_t sw_cookie,
  326. enum dp_tx_event_type type)
  327. {
  328. }
  329. static inline void
  330. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  331. struct qdf_tso_seg_elem_t *tso_seg,
  332. qdf_nbuf_t skb, uint32_t sw_cookie,
  333. enum dp_tx_event_type type)
  334. {
  335. }
  336. static inline void
  337. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  338. qdf_nbuf_t skb, uint32_t sw_cookie,
  339. enum dp_tx_event_type type)
  340. {
  341. }
  342. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  343. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  344. /**
  345. * dp_is_tput_high() - Check if throughput is high
  346. *
  347. * @soc - core txrx main context
  348. *
  349. * The current function is based of the RTPM tput policy variable where RTPM is
  350. * avoided based on throughput.
  351. */
  352. static inline int dp_is_tput_high(struct dp_soc *soc)
  353. {
  354. return dp_get_rtpm_tput_policy_requirement(soc);
  355. }
  356. #if defined(FEATURE_TSO)
  357. /**
  358. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  359. *
  360. * @soc - core txrx main context
  361. * @seg_desc - tso segment descriptor
  362. * @num_seg_desc - tso number segment descriptor
  363. */
  364. static void dp_tx_tso_unmap_segment(
  365. struct dp_soc *soc,
  366. struct qdf_tso_seg_elem_t *seg_desc,
  367. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  368. {
  369. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  370. if (qdf_unlikely(!seg_desc)) {
  371. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  372. __func__, __LINE__);
  373. qdf_assert(0);
  374. } else if (qdf_unlikely(!num_seg_desc)) {
  375. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  376. __func__, __LINE__);
  377. qdf_assert(0);
  378. } else {
  379. bool is_last_seg;
  380. /* no tso segment left to do dma unmap */
  381. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  382. return;
  383. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  384. true : false;
  385. qdf_nbuf_unmap_tso_segment(soc->osdev,
  386. seg_desc, is_last_seg);
  387. num_seg_desc->num_seg.tso_cmn_num_seg--;
  388. }
  389. }
  390. /**
  391. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  392. * back to the freelist
  393. *
  394. * @soc - soc device handle
  395. * @tx_desc - Tx software descriptor
  396. */
  397. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  398. struct dp_tx_desc_s *tx_desc)
  399. {
  400. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  401. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  402. dp_tx_err("SO desc is NULL!");
  403. qdf_assert(0);
  404. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  405. dp_tx_err("TSO num desc is NULL!");
  406. qdf_assert(0);
  407. } else {
  408. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  409. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  410. msdu_ext_desc->tso_num_desc;
  411. /* Add the tso num segment into the free list */
  412. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  413. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  414. tx_desc->msdu_ext_desc->
  415. tso_num_desc);
  416. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  417. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  418. }
  419. /* Add the tso segment into the free list*/
  420. dp_tx_tso_desc_free(soc,
  421. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  422. tso_desc);
  423. tx_desc->msdu_ext_desc->tso_desc = NULL;
  424. }
  425. }
  426. #else
  427. static void dp_tx_tso_unmap_segment(
  428. struct dp_soc *soc,
  429. struct qdf_tso_seg_elem_t *seg_desc,
  430. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  431. {
  432. }
  433. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  434. struct dp_tx_desc_s *tx_desc)
  435. {
  436. }
  437. #endif
  438. /**
  439. * dp_tx_desc_release() - Release Tx Descriptor
  440. * @tx_desc : Tx Descriptor
  441. * @desc_pool_id: Descriptor Pool ID
  442. *
  443. * Deallocate all resources attached to Tx descriptor and free the Tx
  444. * descriptor.
  445. *
  446. * Return:
  447. */
  448. void
  449. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  450. {
  451. struct dp_pdev *pdev = tx_desc->pdev;
  452. struct dp_soc *soc;
  453. uint8_t comp_status = 0;
  454. qdf_assert(pdev);
  455. soc = pdev->soc;
  456. dp_tx_outstanding_dec(pdev);
  457. if (tx_desc->msdu_ext_desc) {
  458. if (tx_desc->frm_type == dp_tx_frm_tso)
  459. dp_tx_tso_desc_release(soc, tx_desc);
  460. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  461. dp_tx_me_free_buf(tx_desc->pdev,
  462. tx_desc->msdu_ext_desc->me_buffer);
  463. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  464. }
  465. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  466. qdf_atomic_dec(&soc->num_tx_exception);
  467. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  468. tx_desc->buffer_src)
  469. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  470. soc->hal_soc);
  471. else
  472. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  473. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  474. tx_desc->id, comp_status,
  475. qdf_atomic_read(&pdev->num_tx_outstanding));
  476. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  477. return;
  478. }
  479. /**
  480. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  481. * @vdev: DP vdev Handle
  482. * @nbuf: skb
  483. * @msdu_info: msdu_info required to create HTT metadata
  484. *
  485. * Prepares and fills HTT metadata in the frame pre-header for special frames
  486. * that should be transmitted using varying transmit parameters.
  487. * There are 2 VDEV modes that currently needs this special metadata -
  488. * 1) Mesh Mode
  489. * 2) DSRC Mode
  490. *
  491. * Return: HTT metadata size
  492. *
  493. */
  494. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  495. struct dp_tx_msdu_info_s *msdu_info)
  496. {
  497. uint32_t *meta_data = msdu_info->meta_data;
  498. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  499. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  500. uint8_t htt_desc_size;
  501. /* Size rounded of multiple of 8 bytes */
  502. uint8_t htt_desc_size_aligned;
  503. uint8_t *hdr = NULL;
  504. /*
  505. * Metadata - HTT MSDU Extension header
  506. */
  507. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  508. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  509. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  510. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  511. meta_data[0])) {
  512. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  513. htt_desc_size_aligned)) {
  514. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  515. htt_desc_size_aligned);
  516. if (!nbuf) {
  517. /*
  518. * qdf_nbuf_realloc_headroom won't do skb_clone
  519. * as skb_realloc_headroom does. so, no free is
  520. * needed here.
  521. */
  522. DP_STATS_INC(vdev,
  523. tx_i.dropped.headroom_insufficient,
  524. 1);
  525. qdf_print(" %s[%d] skb_realloc_headroom failed",
  526. __func__, __LINE__);
  527. return 0;
  528. }
  529. }
  530. /* Fill and add HTT metaheader */
  531. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  532. if (!hdr) {
  533. dp_tx_err("Error in filling HTT metadata");
  534. return 0;
  535. }
  536. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  537. } else if (vdev->opmode == wlan_op_mode_ocb) {
  538. /* Todo - Add support for DSRC */
  539. }
  540. return htt_desc_size_aligned;
  541. }
  542. /**
  543. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  544. * @tso_seg: TSO segment to process
  545. * @ext_desc: Pointer to MSDU extension descriptor
  546. *
  547. * Return: void
  548. */
  549. #if defined(FEATURE_TSO)
  550. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  551. void *ext_desc)
  552. {
  553. uint8_t num_frag;
  554. uint32_t tso_flags;
  555. /*
  556. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  557. * tcp_flag_mask
  558. *
  559. * Checksum enable flags are set in TCL descriptor and not in Extension
  560. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  561. */
  562. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  563. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  564. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  565. tso_seg->tso_flags.ip_len);
  566. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  567. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  568. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  569. uint32_t lo = 0;
  570. uint32_t hi = 0;
  571. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  572. (tso_seg->tso_frags[num_frag].length));
  573. qdf_dmaaddr_to_32s(
  574. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  575. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  576. tso_seg->tso_frags[num_frag].length);
  577. }
  578. return;
  579. }
  580. #else
  581. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  582. void *ext_desc)
  583. {
  584. return;
  585. }
  586. #endif
  587. #if defined(FEATURE_TSO)
  588. /**
  589. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  590. * allocated and free them
  591. *
  592. * @soc: soc handle
  593. * @free_seg: list of tso segments
  594. * @msdu_info: msdu descriptor
  595. *
  596. * Return - void
  597. */
  598. static void dp_tx_free_tso_seg_list(
  599. struct dp_soc *soc,
  600. struct qdf_tso_seg_elem_t *free_seg,
  601. struct dp_tx_msdu_info_s *msdu_info)
  602. {
  603. struct qdf_tso_seg_elem_t *next_seg;
  604. while (free_seg) {
  605. next_seg = free_seg->next;
  606. dp_tx_tso_desc_free(soc,
  607. msdu_info->tx_queue.desc_pool_id,
  608. free_seg);
  609. free_seg = next_seg;
  610. }
  611. }
  612. /**
  613. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  614. * allocated and free them
  615. *
  616. * @soc: soc handle
  617. * @free_num_seg: list of tso number segments
  618. * @msdu_info: msdu descriptor
  619. * Return - void
  620. */
  621. static void dp_tx_free_tso_num_seg_list(
  622. struct dp_soc *soc,
  623. struct qdf_tso_num_seg_elem_t *free_num_seg,
  624. struct dp_tx_msdu_info_s *msdu_info)
  625. {
  626. struct qdf_tso_num_seg_elem_t *next_num_seg;
  627. while (free_num_seg) {
  628. next_num_seg = free_num_seg->next;
  629. dp_tso_num_seg_free(soc,
  630. msdu_info->tx_queue.desc_pool_id,
  631. free_num_seg);
  632. free_num_seg = next_num_seg;
  633. }
  634. }
  635. /**
  636. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  637. * do dma unmap for each segment
  638. *
  639. * @soc: soc handle
  640. * @free_seg: list of tso segments
  641. * @num_seg_desc: tso number segment descriptor
  642. *
  643. * Return - void
  644. */
  645. static void dp_tx_unmap_tso_seg_list(
  646. struct dp_soc *soc,
  647. struct qdf_tso_seg_elem_t *free_seg,
  648. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  649. {
  650. struct qdf_tso_seg_elem_t *next_seg;
  651. if (qdf_unlikely(!num_seg_desc)) {
  652. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  653. return;
  654. }
  655. while (free_seg) {
  656. next_seg = free_seg->next;
  657. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  658. free_seg = next_seg;
  659. }
  660. }
  661. #ifdef FEATURE_TSO_STATS
  662. /**
  663. * dp_tso_get_stats_idx: Retrieve the tso packet id
  664. * @pdev - pdev handle
  665. *
  666. * Return: id
  667. */
  668. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  669. {
  670. uint32_t stats_idx;
  671. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  672. % CDP_MAX_TSO_PACKETS);
  673. return stats_idx;
  674. }
  675. #else
  676. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  677. {
  678. return 0;
  679. }
  680. #endif /* FEATURE_TSO_STATS */
  681. /**
  682. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  683. * free the tso segments descriptor and
  684. * tso num segments descriptor
  685. *
  686. * @soc: soc handle
  687. * @msdu_info: msdu descriptor
  688. * @tso_seg_unmap: flag to show if dma unmap is necessary
  689. *
  690. * Return - void
  691. */
  692. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  693. struct dp_tx_msdu_info_s *msdu_info,
  694. bool tso_seg_unmap)
  695. {
  696. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  697. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  698. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  699. tso_info->tso_num_seg_list;
  700. /* do dma unmap for each segment */
  701. if (tso_seg_unmap)
  702. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  703. /* free all tso number segment descriptor though looks only have 1 */
  704. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  705. /* free all tso segment descriptor */
  706. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  707. }
  708. /**
  709. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  710. * @vdev: virtual device handle
  711. * @msdu: network buffer
  712. * @msdu_info: meta data associated with the msdu
  713. *
  714. * Return: QDF_STATUS_SUCCESS success
  715. */
  716. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  717. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  718. {
  719. struct qdf_tso_seg_elem_t *tso_seg;
  720. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  721. struct dp_soc *soc = vdev->pdev->soc;
  722. struct dp_pdev *pdev = vdev->pdev;
  723. struct qdf_tso_info_t *tso_info;
  724. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  725. tso_info = &msdu_info->u.tso_info;
  726. tso_info->curr_seg = NULL;
  727. tso_info->tso_seg_list = NULL;
  728. tso_info->num_segs = num_seg;
  729. msdu_info->frm_type = dp_tx_frm_tso;
  730. tso_info->tso_num_seg_list = NULL;
  731. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  732. while (num_seg) {
  733. tso_seg = dp_tx_tso_desc_alloc(
  734. soc, msdu_info->tx_queue.desc_pool_id);
  735. if (tso_seg) {
  736. tso_seg->next = tso_info->tso_seg_list;
  737. tso_info->tso_seg_list = tso_seg;
  738. num_seg--;
  739. } else {
  740. dp_err_rl("Failed to alloc tso seg desc");
  741. DP_STATS_INC_PKT(vdev->pdev,
  742. tso_stats.tso_no_mem_dropped, 1,
  743. qdf_nbuf_len(msdu));
  744. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  745. return QDF_STATUS_E_NOMEM;
  746. }
  747. }
  748. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  749. tso_num_seg = dp_tso_num_seg_alloc(soc,
  750. msdu_info->tx_queue.desc_pool_id);
  751. if (tso_num_seg) {
  752. tso_num_seg->next = tso_info->tso_num_seg_list;
  753. tso_info->tso_num_seg_list = tso_num_seg;
  754. } else {
  755. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  756. __func__);
  757. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  758. return QDF_STATUS_E_NOMEM;
  759. }
  760. msdu_info->num_seg =
  761. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  762. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  763. msdu_info->num_seg);
  764. if (!(msdu_info->num_seg)) {
  765. /*
  766. * Free allocated TSO seg desc and number seg desc,
  767. * do unmap for segments if dma map has done.
  768. */
  769. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  770. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  771. return QDF_STATUS_E_INVAL;
  772. }
  773. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  774. msdu, 0, DP_TX_DESC_MAP);
  775. tso_info->curr_seg = tso_info->tso_seg_list;
  776. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  777. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  778. msdu, msdu_info->num_seg);
  779. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  780. tso_info->msdu_stats_idx);
  781. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  782. return QDF_STATUS_SUCCESS;
  783. }
  784. #else
  785. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  786. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  787. {
  788. return QDF_STATUS_E_NOMEM;
  789. }
  790. #endif
  791. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  792. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  793. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  794. /**
  795. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  796. * @vdev: DP Vdev handle
  797. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  798. * @desc_pool_id: Descriptor Pool ID
  799. *
  800. * Return:
  801. */
  802. static
  803. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  804. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  805. {
  806. uint8_t i;
  807. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  808. struct dp_tx_seg_info_s *seg_info;
  809. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  810. struct dp_soc *soc = vdev->pdev->soc;
  811. /* Allocate an extension descriptor */
  812. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  813. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  814. if (!msdu_ext_desc) {
  815. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  816. return NULL;
  817. }
  818. if (msdu_info->exception_fw &&
  819. qdf_unlikely(vdev->mesh_vdev)) {
  820. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  821. &msdu_info->meta_data[0],
  822. sizeof(struct htt_tx_msdu_desc_ext2_t));
  823. qdf_atomic_inc(&soc->num_tx_exception);
  824. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  825. }
  826. switch (msdu_info->frm_type) {
  827. case dp_tx_frm_sg:
  828. case dp_tx_frm_me:
  829. case dp_tx_frm_raw:
  830. seg_info = msdu_info->u.sg_info.curr_seg;
  831. /* Update the buffer pointers in MSDU Extension Descriptor */
  832. for (i = 0; i < seg_info->frag_cnt; i++) {
  833. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  834. seg_info->frags[i].paddr_lo,
  835. seg_info->frags[i].paddr_hi,
  836. seg_info->frags[i].len);
  837. }
  838. break;
  839. case dp_tx_frm_tso:
  840. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  841. &cached_ext_desc[0]);
  842. break;
  843. default:
  844. break;
  845. }
  846. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  847. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  848. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  849. msdu_ext_desc->vaddr);
  850. return msdu_ext_desc;
  851. }
  852. /**
  853. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  854. *
  855. * @skb: skb to be traced
  856. * @msdu_id: msdu_id of the packet
  857. * @vdev_id: vdev_id of the packet
  858. *
  859. * Return: None
  860. */
  861. #ifdef DP_DISABLE_TX_PKT_TRACE
  862. static void dp_tx_trace_pkt(struct dp_soc *soc,
  863. qdf_nbuf_t skb, uint16_t msdu_id,
  864. uint8_t vdev_id)
  865. {
  866. }
  867. #else
  868. static void dp_tx_trace_pkt(struct dp_soc *soc,
  869. qdf_nbuf_t skb, uint16_t msdu_id,
  870. uint8_t vdev_id)
  871. {
  872. if (dp_is_tput_high(soc))
  873. return;
  874. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  875. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  876. DPTRACE(qdf_dp_trace_ptr(skb,
  877. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  878. QDF_TRACE_DEFAULT_PDEV_ID,
  879. qdf_nbuf_data_addr(skb),
  880. sizeof(qdf_nbuf_data(skb)),
  881. msdu_id, vdev_id, 0));
  882. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  883. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  884. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  885. msdu_id, QDF_TX));
  886. }
  887. #endif
  888. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  889. /**
  890. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  891. * exception by the upper layer (OS_IF)
  892. * @soc: DP soc handle
  893. * @nbuf: packet to be transmitted
  894. *
  895. * Returns: 1 if the packet is marked as exception,
  896. * 0, if the packet is not marked as exception.
  897. */
  898. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  899. qdf_nbuf_t nbuf)
  900. {
  901. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  902. }
  903. #else
  904. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  905. qdf_nbuf_t nbuf)
  906. {
  907. return 0;
  908. }
  909. #endif
  910. /**
  911. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  912. * @vdev: DP vdev handle
  913. * @nbuf: skb
  914. * @desc_pool_id: Descriptor pool ID
  915. * @meta_data: Metadata to the fw
  916. * @tx_exc_metadata: Handle that holds exception path metadata
  917. * Allocate and prepare Tx descriptor with msdu information.
  918. *
  919. * Return: Pointer to Tx Descriptor on success,
  920. * NULL on failure
  921. */
  922. static
  923. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  924. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  925. struct dp_tx_msdu_info_s *msdu_info,
  926. struct cdp_tx_exception_metadata *tx_exc_metadata)
  927. {
  928. uint8_t align_pad;
  929. uint8_t is_exception = 0;
  930. uint8_t htt_hdr_size;
  931. struct dp_tx_desc_s *tx_desc;
  932. struct dp_pdev *pdev = vdev->pdev;
  933. struct dp_soc *soc = pdev->soc;
  934. if (dp_tx_limit_check(vdev))
  935. return NULL;
  936. /* Allocate software Tx descriptor */
  937. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  938. if (qdf_unlikely(!tx_desc)) {
  939. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  940. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  941. return NULL;
  942. }
  943. dp_tx_outstanding_inc(pdev);
  944. /* Initialize the SW tx descriptor */
  945. tx_desc->nbuf = nbuf;
  946. tx_desc->frm_type = dp_tx_frm_std;
  947. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  948. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  949. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  950. tx_desc->vdev_id = vdev->vdev_id;
  951. tx_desc->pdev = pdev;
  952. tx_desc->msdu_ext_desc = NULL;
  953. tx_desc->pkt_offset = 0;
  954. tx_desc->length = qdf_nbuf_headlen(nbuf);
  955. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  956. if (qdf_unlikely(vdev->multipass_en)) {
  957. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  958. goto failure;
  959. }
  960. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  961. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  962. is_exception = 1;
  963. /*
  964. * For special modes (vdev_type == ocb or mesh), data frames should be
  965. * transmitted using varying transmit parameters (tx spec) which include
  966. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  967. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  968. * These frames are sent as exception packets to firmware.
  969. *
  970. * HW requirement is that metadata should always point to a
  971. * 8-byte aligned address. So we add alignment pad to start of buffer.
  972. * HTT Metadata should be ensured to be multiple of 8-bytes,
  973. * to get 8-byte aligned start address along with align_pad added
  974. *
  975. * |-----------------------------|
  976. * | |
  977. * |-----------------------------| <-----Buffer Pointer Address given
  978. * | | ^ in HW descriptor (aligned)
  979. * | HTT Metadata | |
  980. * | | |
  981. * | | | Packet Offset given in descriptor
  982. * | | |
  983. * |-----------------------------| |
  984. * | Alignment Pad | v
  985. * |-----------------------------| <----- Actual buffer start address
  986. * | SKB Data | (Unaligned)
  987. * | |
  988. * | |
  989. * | |
  990. * | |
  991. * | |
  992. * |-----------------------------|
  993. */
  994. if (qdf_unlikely((msdu_info->exception_fw)) ||
  995. (vdev->opmode == wlan_op_mode_ocb) ||
  996. (tx_exc_metadata &&
  997. tx_exc_metadata->is_tx_sniffer)) {
  998. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  999. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1000. DP_STATS_INC(vdev,
  1001. tx_i.dropped.headroom_insufficient, 1);
  1002. goto failure;
  1003. }
  1004. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1005. dp_tx_err("qdf_nbuf_push_head failed");
  1006. goto failure;
  1007. }
  1008. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1009. msdu_info);
  1010. if (htt_hdr_size == 0)
  1011. goto failure;
  1012. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1013. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1014. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1015. is_exception = 1;
  1016. tx_desc->length -= tx_desc->pkt_offset;
  1017. }
  1018. #if !TQM_BYPASS_WAR
  1019. if (is_exception || tx_exc_metadata)
  1020. #endif
  1021. {
  1022. /* Temporary WAR due to TQM VP issues */
  1023. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1024. qdf_atomic_inc(&soc->num_tx_exception);
  1025. }
  1026. return tx_desc;
  1027. failure:
  1028. dp_tx_desc_release(tx_desc, desc_pool_id);
  1029. return NULL;
  1030. }
  1031. /**
  1032. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1033. * @vdev: DP vdev handle
  1034. * @nbuf: skb
  1035. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1036. * @desc_pool_id : Descriptor Pool ID
  1037. *
  1038. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1039. * information. For frames wth fragments, allocate and prepare
  1040. * an MSDU extension descriptor
  1041. *
  1042. * Return: Pointer to Tx Descriptor on success,
  1043. * NULL on failure
  1044. */
  1045. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1046. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1047. uint8_t desc_pool_id)
  1048. {
  1049. struct dp_tx_desc_s *tx_desc;
  1050. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1051. struct dp_pdev *pdev = vdev->pdev;
  1052. struct dp_soc *soc = pdev->soc;
  1053. if (dp_tx_limit_check(vdev))
  1054. return NULL;
  1055. /* Allocate software Tx descriptor */
  1056. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1057. if (!tx_desc) {
  1058. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1059. return NULL;
  1060. }
  1061. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1062. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1063. dp_tx_outstanding_inc(pdev);
  1064. /* Initialize the SW tx descriptor */
  1065. tx_desc->nbuf = nbuf;
  1066. tx_desc->frm_type = msdu_info->frm_type;
  1067. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1068. tx_desc->vdev_id = vdev->vdev_id;
  1069. tx_desc->pdev = pdev;
  1070. tx_desc->pkt_offset = 0;
  1071. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1072. /* Handle scattered frames - TSO/SG/ME */
  1073. /* Allocate and prepare an extension descriptor for scattered frames */
  1074. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1075. if (!msdu_ext_desc) {
  1076. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1077. goto failure;
  1078. }
  1079. #if TQM_BYPASS_WAR
  1080. /* Temporary WAR due to TQM VP issues */
  1081. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1082. qdf_atomic_inc(&soc->num_tx_exception);
  1083. #endif
  1084. if (qdf_unlikely(msdu_info->exception_fw))
  1085. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1086. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1087. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1088. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1089. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1090. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1091. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1092. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1093. else
  1094. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1095. return tx_desc;
  1096. failure:
  1097. dp_tx_desc_release(tx_desc, desc_pool_id);
  1098. return NULL;
  1099. }
  1100. /**
  1101. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1102. * @vdev: DP vdev handle
  1103. * @nbuf: buffer pointer
  1104. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1105. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1106. * descriptor
  1107. *
  1108. * Return:
  1109. */
  1110. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1111. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1112. {
  1113. qdf_nbuf_t curr_nbuf = NULL;
  1114. uint16_t total_len = 0;
  1115. qdf_dma_addr_t paddr;
  1116. int32_t i;
  1117. int32_t mapped_buf_num = 0;
  1118. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1119. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1120. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1121. /* Continue only if frames are of DATA type */
  1122. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1123. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1124. dp_tx_debug("Pkt. recd is of not data type");
  1125. goto error;
  1126. }
  1127. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1128. if (vdev->raw_mode_war &&
  1129. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1130. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1131. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1132. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1133. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1134. /*
  1135. * Number of nbuf's must not exceed the size of the frags
  1136. * array in seg_info.
  1137. */
  1138. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1139. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1140. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1141. goto error;
  1142. }
  1143. if (QDF_STATUS_SUCCESS !=
  1144. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1145. curr_nbuf,
  1146. QDF_DMA_TO_DEVICE,
  1147. curr_nbuf->len)) {
  1148. dp_tx_err("%s dma map error ", __func__);
  1149. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1150. goto error;
  1151. }
  1152. /* Update the count of mapped nbuf's */
  1153. mapped_buf_num++;
  1154. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1155. seg_info->frags[i].paddr_lo = paddr;
  1156. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1157. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1158. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1159. total_len += qdf_nbuf_len(curr_nbuf);
  1160. }
  1161. seg_info->frag_cnt = i;
  1162. seg_info->total_len = total_len;
  1163. seg_info->next = NULL;
  1164. sg_info->curr_seg = seg_info;
  1165. msdu_info->frm_type = dp_tx_frm_raw;
  1166. msdu_info->num_seg = 1;
  1167. return nbuf;
  1168. error:
  1169. i = 0;
  1170. while (nbuf) {
  1171. curr_nbuf = nbuf;
  1172. if (i < mapped_buf_num) {
  1173. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1174. QDF_DMA_TO_DEVICE,
  1175. curr_nbuf->len);
  1176. i++;
  1177. }
  1178. nbuf = qdf_nbuf_next(nbuf);
  1179. qdf_nbuf_free(curr_nbuf);
  1180. }
  1181. return NULL;
  1182. }
  1183. /**
  1184. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1185. * @soc: DP soc handle
  1186. * @nbuf: Buffer pointer
  1187. *
  1188. * unmap the chain of nbufs that belong to this RAW frame.
  1189. *
  1190. * Return: None
  1191. */
  1192. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1193. qdf_nbuf_t nbuf)
  1194. {
  1195. qdf_nbuf_t cur_nbuf = nbuf;
  1196. do {
  1197. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1198. QDF_DMA_TO_DEVICE,
  1199. cur_nbuf->len);
  1200. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1201. } while (cur_nbuf);
  1202. }
  1203. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1204. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1205. qdf_nbuf_t nbuf)
  1206. {
  1207. qdf_nbuf_t nbuf_local;
  1208. struct dp_vdev *vdev_local = vdev_hdl;
  1209. do {
  1210. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1211. break;
  1212. nbuf_local = nbuf;
  1213. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1214. htt_cmn_pkt_type_raw))
  1215. break;
  1216. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1217. break;
  1218. else if (qdf_nbuf_is_tso((nbuf_local)))
  1219. break;
  1220. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1221. (nbuf_local),
  1222. NULL, 1, 0);
  1223. } while (0);
  1224. }
  1225. #endif
  1226. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1227. /**
  1228. * dp_tx_update_stats() - Update soc level tx stats
  1229. * @soc: DP soc handle
  1230. * @tx_desc: TX descriptor reference
  1231. * @ring_id: TCL ring id
  1232. *
  1233. * Returns: none
  1234. */
  1235. void dp_tx_update_stats(struct dp_soc *soc,
  1236. struct dp_tx_desc_s *tx_desc,
  1237. uint8_t ring_id)
  1238. {
  1239. uint32_t stats_len = 0;
  1240. if (tx_desc->frm_type == dp_tx_frm_tso)
  1241. stats_len = tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1242. else
  1243. stats_len = qdf_nbuf_len(tx_desc->nbuf);
  1244. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1245. }
  1246. int
  1247. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1248. struct dp_tx_desc_s *tx_desc,
  1249. uint8_t tid,
  1250. struct dp_tx_msdu_info_s *msdu_info,
  1251. uint8_t ring_id)
  1252. {
  1253. struct dp_swlm *swlm = &soc->swlm;
  1254. union swlm_data swlm_query_data;
  1255. struct dp_swlm_tcl_data tcl_data;
  1256. QDF_STATUS status;
  1257. int ret;
  1258. if (!swlm->is_enabled)
  1259. return msdu_info->skip_hp_update;
  1260. tcl_data.nbuf = tx_desc->nbuf;
  1261. tcl_data.tid = tid;
  1262. tcl_data.ring_id = ring_id;
  1263. if (tx_desc->frm_type == dp_tx_frm_tso) {
  1264. tcl_data.pkt_len =
  1265. tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1266. } else {
  1267. tcl_data.pkt_len = qdf_nbuf_len(tx_desc->nbuf);
  1268. }
  1269. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1270. swlm_query_data.tcl_data = &tcl_data;
  1271. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1272. if (QDF_IS_STATUS_ERROR(status)) {
  1273. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1274. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1275. return 0;
  1276. }
  1277. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1278. if (ret) {
  1279. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1280. } else {
  1281. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1282. }
  1283. return ret;
  1284. }
  1285. void
  1286. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1287. int coalesce)
  1288. {
  1289. if (coalesce)
  1290. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1291. else
  1292. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1293. }
  1294. static inline void
  1295. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1296. {
  1297. if (((i + 1) < msdu_info->num_seg))
  1298. msdu_info->skip_hp_update = 1;
  1299. else
  1300. msdu_info->skip_hp_update = 0;
  1301. }
  1302. static inline void
  1303. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1304. {
  1305. hal_ring_handle_t hal_ring_hdl =
  1306. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1307. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1308. dp_err("Fillmore: SRNG access start failed");
  1309. return;
  1310. }
  1311. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1312. }
  1313. static inline void
  1314. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1315. QDF_STATUS status,
  1316. struct dp_tx_msdu_info_s *msdu_info)
  1317. {
  1318. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1319. dp_flush_tcp_hp(soc,
  1320. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1321. }
  1322. }
  1323. #else
  1324. static inline void
  1325. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1326. {
  1327. }
  1328. static inline void
  1329. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1330. QDF_STATUS status,
  1331. struct dp_tx_msdu_info_s *msdu_info)
  1332. {
  1333. }
  1334. #endif
  1335. #ifdef FEATURE_RUNTIME_PM
  1336. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1337. {
  1338. return qdf_atomic_read(&soc->rtpm_high_tput_flag);
  1339. }
  1340. /**
  1341. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1342. * @soc: Datapath soc handle
  1343. * @hal_ring_hdl: HAL ring handle
  1344. * @coalesce: Coalesce the current write or not
  1345. *
  1346. * Wrapper for HAL ring access end for data transmission for
  1347. * FEATURE_RUNTIME_PM
  1348. *
  1349. * Returns: none
  1350. */
  1351. void
  1352. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1353. hal_ring_handle_t hal_ring_hdl,
  1354. int coalesce)
  1355. {
  1356. int ret;
  1357. /*
  1358. * Avoid runtime get and put APIs under high throughput scenarios.
  1359. */
  1360. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1361. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1362. return;
  1363. }
  1364. ret = hif_pm_runtime_get(soc->hif_handle,
  1365. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1366. switch (ret) {
  1367. case 0:
  1368. if (hif_system_pm_state_check(soc->hif_handle)) {
  1369. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1370. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1371. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1372. } else {
  1373. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1374. }
  1375. hif_pm_runtime_put(soc->hif_handle,
  1376. RTPM_ID_DW_TX_HW_ENQUEUE);
  1377. break;
  1378. /*
  1379. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1380. * take the dp runtime refcount using dp_runtime_get,
  1381. * check link state,if up, write TX ring HP, else just set flush event.
  1382. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1383. * zero or time out, then flush pending tx.
  1384. */
  1385. case -EBUSY:
  1386. case -EINPROGRESS:
  1387. dp_runtime_get(soc);
  1388. if (hif_pm_get_link_state(soc->hif_handle) ==
  1389. HIF_PM_LINK_STATE_UP) {
  1390. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1391. } else {
  1392. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1393. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1394. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1395. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1396. }
  1397. dp_runtime_put(soc);
  1398. break;
  1399. default:
  1400. dp_runtime_get(soc);
  1401. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1402. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1403. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1404. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1405. dp_runtime_put(soc);
  1406. }
  1407. }
  1408. #else
  1409. #ifdef DP_POWER_SAVE
  1410. void
  1411. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1412. hal_ring_handle_t hal_ring_hdl,
  1413. int coalesce)
  1414. {
  1415. if (hif_system_pm_state_check(soc->hif_handle)) {
  1416. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1417. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1418. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1419. } else {
  1420. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1421. }
  1422. }
  1423. #endif
  1424. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1425. {
  1426. return 0;
  1427. }
  1428. #endif
  1429. /**
  1430. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1431. * @vdev: DP vdev handle
  1432. * @nbuf: skb
  1433. *
  1434. * Extract the DSCP or PCP information from frame and map into TID value.
  1435. *
  1436. * Return: void
  1437. */
  1438. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1439. struct dp_tx_msdu_info_s *msdu_info)
  1440. {
  1441. uint8_t tos = 0, dscp_tid_override = 0;
  1442. uint8_t *hdr_ptr, *L3datap;
  1443. uint8_t is_mcast = 0;
  1444. qdf_ether_header_t *eh = NULL;
  1445. qdf_ethervlan_header_t *evh = NULL;
  1446. uint16_t ether_type;
  1447. qdf_llc_t *llcHdr;
  1448. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1449. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1450. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1451. eh = (qdf_ether_header_t *)nbuf->data;
  1452. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1453. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1454. } else {
  1455. qdf_dot3_qosframe_t *qos_wh =
  1456. (qdf_dot3_qosframe_t *) nbuf->data;
  1457. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1458. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1459. return;
  1460. }
  1461. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1462. ether_type = eh->ether_type;
  1463. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1464. /*
  1465. * Check if packet is dot3 or eth2 type.
  1466. */
  1467. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1468. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1469. sizeof(*llcHdr));
  1470. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1471. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1472. sizeof(*llcHdr);
  1473. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1474. + sizeof(*llcHdr) +
  1475. sizeof(qdf_net_vlanhdr_t));
  1476. } else {
  1477. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1478. sizeof(*llcHdr);
  1479. }
  1480. } else {
  1481. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1482. evh = (qdf_ethervlan_header_t *) eh;
  1483. ether_type = evh->ether_type;
  1484. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1485. }
  1486. }
  1487. /*
  1488. * Find priority from IP TOS DSCP field
  1489. */
  1490. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1491. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1492. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1493. /* Only for unicast frames */
  1494. if (!is_mcast) {
  1495. /* send it on VO queue */
  1496. msdu_info->tid = DP_VO_TID;
  1497. }
  1498. } else {
  1499. /*
  1500. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1501. * from TOS byte.
  1502. */
  1503. tos = ip->ip_tos;
  1504. dscp_tid_override = 1;
  1505. }
  1506. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1507. /* TODO
  1508. * use flowlabel
  1509. *igmpmld cases to be handled in phase 2
  1510. */
  1511. unsigned long ver_pri_flowlabel;
  1512. unsigned long pri;
  1513. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1514. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1515. DP_IPV6_PRIORITY_SHIFT;
  1516. tos = pri;
  1517. dscp_tid_override = 1;
  1518. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1519. msdu_info->tid = DP_VO_TID;
  1520. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1521. /* Only for unicast frames */
  1522. if (!is_mcast) {
  1523. /* send ucast arp on VO queue */
  1524. msdu_info->tid = DP_VO_TID;
  1525. }
  1526. }
  1527. /*
  1528. * Assign all MCAST packets to BE
  1529. */
  1530. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1531. if (is_mcast) {
  1532. tos = 0;
  1533. dscp_tid_override = 1;
  1534. }
  1535. }
  1536. if (dscp_tid_override == 1) {
  1537. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1538. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1539. }
  1540. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1541. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1542. return;
  1543. }
  1544. /**
  1545. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1546. * @vdev: DP vdev handle
  1547. * @nbuf: skb
  1548. *
  1549. * Software based TID classification is required when more than 2 DSCP-TID
  1550. * mapping tables are needed.
  1551. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1552. *
  1553. * Return: void
  1554. */
  1555. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1556. struct dp_tx_msdu_info_s *msdu_info)
  1557. {
  1558. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1559. /*
  1560. * skip_sw_tid_classification flag will set in below cases-
  1561. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1562. * 2. hlos_tid_override enabled for vdev
  1563. * 3. mesh mode enabled for vdev
  1564. */
  1565. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1566. /* Update tid in msdu_info from skb priority */
  1567. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1568. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1569. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1570. if (tid == DP_TX_INVALID_QOS_TAG)
  1571. return;
  1572. msdu_info->tid = tid;
  1573. return;
  1574. }
  1575. return;
  1576. }
  1577. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1578. }
  1579. #ifdef FEATURE_WLAN_TDLS
  1580. /**
  1581. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1582. * @soc: datapath SOC
  1583. * @vdev: datapath vdev
  1584. * @tx_desc: TX descriptor
  1585. *
  1586. * Return: None
  1587. */
  1588. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1589. struct dp_vdev *vdev,
  1590. struct dp_tx_desc_s *tx_desc)
  1591. {
  1592. if (vdev) {
  1593. if (vdev->is_tdls_frame) {
  1594. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1595. vdev->is_tdls_frame = false;
  1596. }
  1597. }
  1598. }
  1599. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1600. {
  1601. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1602. switch (soc->arch_id) {
  1603. case CDP_ARCH_TYPE_LI:
  1604. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1605. break;
  1606. case CDP_ARCH_TYPE_BE:
  1607. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1608. break;
  1609. default:
  1610. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1611. QDF_BUG(0);
  1612. }
  1613. return tx_status;
  1614. }
  1615. /**
  1616. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1617. * @soc: dp_soc handle
  1618. * @tx_desc: TX descriptor
  1619. * @vdev: datapath vdev handle
  1620. *
  1621. * Return: None
  1622. */
  1623. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1624. struct dp_tx_desc_s *tx_desc)
  1625. {
  1626. uint8_t tx_status = 0;
  1627. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1628. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1629. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1630. DP_MOD_ID_TDLS);
  1631. if (qdf_unlikely(!vdev)) {
  1632. dp_err_rl("vdev is null!");
  1633. goto error;
  1634. }
  1635. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1636. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1637. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1638. if (vdev->tx_non_std_data_callback.func) {
  1639. qdf_nbuf_set_next(nbuf, NULL);
  1640. vdev->tx_non_std_data_callback.func(
  1641. vdev->tx_non_std_data_callback.ctxt,
  1642. nbuf, tx_status);
  1643. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1644. return;
  1645. } else {
  1646. dp_err_rl("callback func is null");
  1647. }
  1648. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1649. error:
  1650. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1651. qdf_nbuf_free(nbuf);
  1652. }
  1653. /**
  1654. * dp_tx_msdu_single_map() - do nbuf map
  1655. * @vdev: DP vdev handle
  1656. * @tx_desc: DP TX descriptor pointer
  1657. * @nbuf: skb pointer
  1658. *
  1659. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1660. * operation done in other component.
  1661. *
  1662. * Return: QDF_STATUS
  1663. */
  1664. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1665. struct dp_tx_desc_s *tx_desc,
  1666. qdf_nbuf_t nbuf)
  1667. {
  1668. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1669. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1670. nbuf,
  1671. QDF_DMA_TO_DEVICE,
  1672. nbuf->len);
  1673. else
  1674. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1675. QDF_DMA_TO_DEVICE);
  1676. }
  1677. #else
  1678. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1679. struct dp_vdev *vdev,
  1680. struct dp_tx_desc_s *tx_desc)
  1681. {
  1682. }
  1683. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1684. struct dp_tx_desc_s *tx_desc)
  1685. {
  1686. }
  1687. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1688. struct dp_tx_desc_s *tx_desc,
  1689. qdf_nbuf_t nbuf)
  1690. {
  1691. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1692. nbuf,
  1693. QDF_DMA_TO_DEVICE,
  1694. nbuf->len);
  1695. }
  1696. #endif
  1697. static inline
  1698. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1699. struct dp_tx_desc_s *tx_desc,
  1700. qdf_nbuf_t nbuf)
  1701. {
  1702. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1703. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1704. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1705. return 0;
  1706. return qdf_nbuf_mapped_paddr_get(nbuf);
  1707. }
  1708. static inline
  1709. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1710. {
  1711. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1712. desc->nbuf,
  1713. desc->dma_addr,
  1714. QDF_DMA_TO_DEVICE,
  1715. desc->length);
  1716. }
  1717. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1718. static inline
  1719. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1720. struct dp_tx_desc_s *tx_desc,
  1721. qdf_nbuf_t nbuf)
  1722. {
  1723. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1724. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1725. (void *)(nbuf->data + nbuf->len));
  1726. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1727. } else {
  1728. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1729. }
  1730. }
  1731. static inline
  1732. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1733. struct dp_tx_desc_s *desc)
  1734. {
  1735. if (qdf_unlikely(!(desc->flags & DP_TX_DESC_FLAG_SIMPLE)))
  1736. return dp_tx_nbuf_unmap_regular(soc, desc);
  1737. }
  1738. #else
  1739. static inline
  1740. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1741. struct dp_tx_desc_s *tx_desc,
  1742. qdf_nbuf_t nbuf)
  1743. {
  1744. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1745. }
  1746. static inline
  1747. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1748. struct dp_tx_desc_s *desc)
  1749. {
  1750. return dp_tx_nbuf_unmap_regular(soc, desc);
  1751. }
  1752. #endif
  1753. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1754. static inline
  1755. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1756. {
  1757. dp_tx_nbuf_unmap(soc, desc);
  1758. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1759. }
  1760. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1761. {
  1762. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1763. dp_tx_nbuf_unmap(soc, desc);
  1764. }
  1765. #else
  1766. static inline
  1767. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1768. {
  1769. }
  1770. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1771. {
  1772. dp_tx_nbuf_unmap(soc, desc);
  1773. }
  1774. #endif
  1775. #ifdef MESH_MODE_SUPPORT
  1776. /**
  1777. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1778. * @soc: datapath SOC
  1779. * @vdev: datapath vdev
  1780. * @tx_desc: TX descriptor
  1781. *
  1782. * Return: None
  1783. */
  1784. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1785. struct dp_vdev *vdev,
  1786. struct dp_tx_desc_s *tx_desc)
  1787. {
  1788. if (qdf_unlikely(vdev->mesh_vdev))
  1789. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1790. }
  1791. /**
  1792. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1793. * @soc: dp_soc handle
  1794. * @tx_desc: TX descriptor
  1795. * @vdev: datapath vdev handle
  1796. *
  1797. * Return: None
  1798. */
  1799. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1800. struct dp_tx_desc_s *tx_desc)
  1801. {
  1802. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1803. struct dp_vdev *vdev = NULL;
  1804. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1805. qdf_nbuf_free(nbuf);
  1806. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1807. } else {
  1808. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1809. DP_MOD_ID_MESH);
  1810. if (vdev && vdev->osif_tx_free_ext)
  1811. vdev->osif_tx_free_ext((nbuf));
  1812. else
  1813. qdf_nbuf_free(nbuf);
  1814. if (vdev)
  1815. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1816. }
  1817. }
  1818. #else
  1819. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1820. struct dp_vdev *vdev,
  1821. struct dp_tx_desc_s *tx_desc)
  1822. {
  1823. }
  1824. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1825. struct dp_tx_desc_s *tx_desc)
  1826. {
  1827. }
  1828. #endif
  1829. /**
  1830. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1831. * @vdev: DP vdev handle
  1832. * @nbuf: skb
  1833. *
  1834. * Return: 1 if frame needs to be dropped else 0
  1835. */
  1836. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1837. {
  1838. struct dp_pdev *pdev = NULL;
  1839. struct dp_ast_entry *src_ast_entry = NULL;
  1840. struct dp_ast_entry *dst_ast_entry = NULL;
  1841. struct dp_soc *soc = NULL;
  1842. qdf_assert(vdev);
  1843. pdev = vdev->pdev;
  1844. qdf_assert(pdev);
  1845. soc = pdev->soc;
  1846. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1847. (soc, dstmac, vdev->pdev->pdev_id);
  1848. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1849. (soc, srcmac, vdev->pdev->pdev_id);
  1850. if (dst_ast_entry && src_ast_entry) {
  1851. if (dst_ast_entry->peer_id ==
  1852. src_ast_entry->peer_id)
  1853. return 1;
  1854. }
  1855. return 0;
  1856. }
  1857. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1858. defined(WLAN_MCAST_MLO)
  1859. /* MLO peer id for reinject*/
  1860. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1861. /* MLO vdev id inc offset */
  1862. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1863. static inline void
  1864. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1865. {
  1866. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1867. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1868. qdf_atomic_inc(&soc->num_tx_exception);
  1869. }
  1870. }
  1871. static inline void
  1872. dp_tx_update_mcast_param(uint16_t peer_id,
  1873. uint16_t *htt_tcl_metadata,
  1874. struct dp_vdev *vdev,
  1875. struct dp_tx_msdu_info_s *msdu_info)
  1876. {
  1877. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1878. *htt_tcl_metadata = 0;
  1879. DP_TX_TCL_METADATA_TYPE_SET(
  1880. *htt_tcl_metadata,
  1881. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1882. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1883. msdu_info->gsn);
  1884. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  1885. if (qdf_unlikely(vdev->nawds_enabled))
  1886. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  1887. *htt_tcl_metadata, 1);
  1888. } else {
  1889. msdu_info->vdev_id = vdev->vdev_id;
  1890. }
  1891. }
  1892. #else
  1893. static inline void
  1894. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1895. {
  1896. }
  1897. static inline void
  1898. dp_tx_update_mcast_param(uint16_t peer_id,
  1899. uint16_t *htt_tcl_metadata,
  1900. struct dp_vdev *vdev,
  1901. struct dp_tx_msdu_info_s *msdu_info)
  1902. {
  1903. }
  1904. #endif
  1905. /**
  1906. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1907. * @vdev: DP vdev handle
  1908. * @nbuf: skb
  1909. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1910. * @meta_data: Metadata to the fw
  1911. * @tx_q: Tx queue to be used for this Tx frame
  1912. * @peer_id: peer_id of the peer in case of NAWDS frames
  1913. * @tx_exc_metadata: Handle that holds exception path metadata
  1914. *
  1915. * Return: NULL on success,
  1916. * nbuf when it fails to send
  1917. */
  1918. qdf_nbuf_t
  1919. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1920. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1921. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1922. {
  1923. struct dp_pdev *pdev = vdev->pdev;
  1924. struct dp_soc *soc = pdev->soc;
  1925. struct dp_tx_desc_s *tx_desc;
  1926. QDF_STATUS status;
  1927. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1928. uint16_t htt_tcl_metadata = 0;
  1929. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1930. uint8_t tid = msdu_info->tid;
  1931. struct cdp_tid_tx_stats *tid_stats = NULL;
  1932. qdf_dma_addr_t paddr;
  1933. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1934. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1935. msdu_info, tx_exc_metadata);
  1936. if (!tx_desc) {
  1937. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1938. vdev, tx_q->desc_pool_id);
  1939. drop_code = TX_DESC_ERR;
  1940. goto fail_return;
  1941. }
  1942. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1943. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1944. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1945. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1946. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1947. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1948. DP_TCL_METADATA_TYPE_PEER_BASED);
  1949. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1950. peer_id);
  1951. dp_tx_bypass_reinjection(soc, tx_desc);
  1952. } else
  1953. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1954. if (msdu_info->exception_fw)
  1955. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1956. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1957. !pdev->enhanced_stats_en);
  1958. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1959. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  1960. if (!paddr) {
  1961. /* Handle failure */
  1962. dp_err("qdf_nbuf_map failed");
  1963. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1964. drop_code = TX_DMA_MAP_ERR;
  1965. goto release_desc;
  1966. }
  1967. tx_desc->dma_addr = paddr;
  1968. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1969. tx_desc->id, DP_TX_DESC_MAP);
  1970. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  1971. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1972. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1973. htt_tcl_metadata,
  1974. tx_exc_metadata, msdu_info);
  1975. if (status != QDF_STATUS_SUCCESS) {
  1976. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1977. tx_desc, tx_q->ring_id);
  1978. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1979. tx_desc->id, DP_TX_DESC_UNMAP);
  1980. dp_tx_nbuf_unmap(soc, tx_desc);
  1981. drop_code = TX_HW_ENQUEUE;
  1982. goto release_desc;
  1983. }
  1984. return NULL;
  1985. release_desc:
  1986. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1987. fail_return:
  1988. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1989. tid_stats = &pdev->stats.tid_stats.
  1990. tid_tx_stats[tx_q->ring_id][tid];
  1991. tid_stats->swdrop_cnt[drop_code]++;
  1992. return nbuf;
  1993. }
  1994. /**
  1995. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1996. * @soc: Soc handle
  1997. * @desc: software Tx descriptor to be processed
  1998. *
  1999. * Return: none
  2000. */
  2001. void dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2002. {
  2003. qdf_nbuf_t nbuf = desc->nbuf;
  2004. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2005. /* nbuf already freed in vdev detach path */
  2006. if (!nbuf)
  2007. return;
  2008. /* If it is TDLS mgmt, don't unmap or free the frame */
  2009. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2010. return dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2011. /* 0 : MSDU buffer, 1 : MLE */
  2012. if (desc->msdu_ext_desc) {
  2013. /* TSO free */
  2014. if (hal_tx_ext_desc_get_tso_enable(
  2015. desc->msdu_ext_desc->vaddr)) {
  2016. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2017. desc->id, DP_TX_COMP_MSDU_EXT);
  2018. dp_tx_tso_seg_history_add(soc,
  2019. desc->msdu_ext_desc->tso_desc,
  2020. desc->nbuf, desc->id, type);
  2021. /* unmap eash TSO seg before free the nbuf */
  2022. dp_tx_tso_unmap_segment(soc,
  2023. desc->msdu_ext_desc->tso_desc,
  2024. desc->msdu_ext_desc->
  2025. tso_num_desc);
  2026. qdf_nbuf_free(nbuf);
  2027. return;
  2028. }
  2029. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2030. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2031. qdf_dma_addr_t iova;
  2032. uint32_t frag_len;
  2033. uint32_t i;
  2034. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2035. QDF_DMA_TO_DEVICE,
  2036. qdf_nbuf_headlen(nbuf));
  2037. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2038. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2039. &iova,
  2040. &frag_len);
  2041. if (!iova || !frag_len)
  2042. break;
  2043. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2044. QDF_DMA_TO_DEVICE);
  2045. }
  2046. qdf_nbuf_free(nbuf);
  2047. return;
  2048. }
  2049. }
  2050. /* If it's ME frame, dont unmap the cloned nbuf's */
  2051. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2052. goto nbuf_free;
  2053. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2054. dp_tx_unmap(soc, desc);
  2055. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2056. return dp_mesh_tx_comp_free_buff(soc, desc);
  2057. nbuf_free:
  2058. qdf_nbuf_free(nbuf);
  2059. }
  2060. /**
  2061. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2062. * @soc: DP soc handle
  2063. * @nbuf: skb
  2064. * @msdu_info: MSDU info
  2065. *
  2066. * Return: None
  2067. */
  2068. static inline void
  2069. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2070. struct dp_tx_msdu_info_s *msdu_info)
  2071. {
  2072. uint32_t cur_idx;
  2073. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2074. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2075. qdf_nbuf_headlen(nbuf));
  2076. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2077. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2078. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2079. seg->frags[cur_idx].paddr_hi) << 32),
  2080. seg->frags[cur_idx].len,
  2081. QDF_DMA_TO_DEVICE);
  2082. }
  2083. /**
  2084. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2085. * @vdev: DP vdev handle
  2086. * @nbuf: skb
  2087. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2088. *
  2089. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2090. *
  2091. * Return: NULL on success,
  2092. * nbuf when it fails to send
  2093. */
  2094. #if QDF_LOCK_STATS
  2095. noinline
  2096. #else
  2097. #endif
  2098. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2099. struct dp_tx_msdu_info_s *msdu_info)
  2100. {
  2101. uint32_t i;
  2102. struct dp_pdev *pdev = vdev->pdev;
  2103. struct dp_soc *soc = pdev->soc;
  2104. struct dp_tx_desc_s *tx_desc;
  2105. bool is_cce_classified = false;
  2106. QDF_STATUS status;
  2107. uint16_t htt_tcl_metadata = 0;
  2108. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2109. struct cdp_tid_tx_stats *tid_stats = NULL;
  2110. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2111. if (msdu_info->frm_type == dp_tx_frm_me)
  2112. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2113. i = 0;
  2114. /* Print statement to track i and num_seg */
  2115. /*
  2116. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2117. * descriptors using information in msdu_info
  2118. */
  2119. while (i < msdu_info->num_seg) {
  2120. /*
  2121. * Setup Tx descriptor for an MSDU, and MSDU extension
  2122. * descriptor
  2123. */
  2124. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2125. tx_q->desc_pool_id);
  2126. if (!tx_desc) {
  2127. if (msdu_info->frm_type == dp_tx_frm_me) {
  2128. prep_desc_fail++;
  2129. dp_tx_me_free_buf(pdev,
  2130. (void *)(msdu_info->u.sg_info
  2131. .curr_seg->frags[0].vaddr));
  2132. if (prep_desc_fail == msdu_info->num_seg) {
  2133. /*
  2134. * Unmap is needed only if descriptor
  2135. * preparation failed for all segments.
  2136. */
  2137. qdf_nbuf_unmap(soc->osdev,
  2138. msdu_info->u.sg_info.
  2139. curr_seg->nbuf,
  2140. QDF_DMA_TO_DEVICE);
  2141. }
  2142. /*
  2143. * Free the nbuf for the current segment
  2144. * and make it point to the next in the list.
  2145. * For me, there are as many segments as there
  2146. * are no of clients.
  2147. */
  2148. qdf_nbuf_free(msdu_info->u.sg_info
  2149. .curr_seg->nbuf);
  2150. if (msdu_info->u.sg_info.curr_seg->next) {
  2151. msdu_info->u.sg_info.curr_seg =
  2152. msdu_info->u.sg_info
  2153. .curr_seg->next;
  2154. nbuf = msdu_info->u.sg_info
  2155. .curr_seg->nbuf;
  2156. }
  2157. i++;
  2158. continue;
  2159. }
  2160. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2161. dp_tx_tso_seg_history_add(
  2162. soc,
  2163. msdu_info->u.tso_info.curr_seg,
  2164. nbuf, 0, DP_TX_DESC_UNMAP);
  2165. dp_tx_tso_unmap_segment(soc,
  2166. msdu_info->u.tso_info.
  2167. curr_seg,
  2168. msdu_info->u.tso_info.
  2169. tso_num_seg_list);
  2170. if (msdu_info->u.tso_info.curr_seg->next) {
  2171. msdu_info->u.tso_info.curr_seg =
  2172. msdu_info->u.tso_info.curr_seg->next;
  2173. i++;
  2174. continue;
  2175. }
  2176. }
  2177. if (msdu_info->frm_type == dp_tx_frm_sg)
  2178. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2179. goto done;
  2180. }
  2181. if (msdu_info->frm_type == dp_tx_frm_me) {
  2182. tx_desc->msdu_ext_desc->me_buffer =
  2183. (struct dp_tx_me_buf_t *)msdu_info->
  2184. u.sg_info.curr_seg->frags[0].vaddr;
  2185. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2186. }
  2187. if (is_cce_classified)
  2188. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2189. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2190. if (msdu_info->exception_fw) {
  2191. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2192. }
  2193. dp_tx_is_hp_update_required(i, msdu_info);
  2194. /*
  2195. * For frames with multiple segments (TSO, ME), jump to next
  2196. * segment.
  2197. */
  2198. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2199. if (msdu_info->u.tso_info.curr_seg->next) {
  2200. msdu_info->u.tso_info.curr_seg =
  2201. msdu_info->u.tso_info.curr_seg->next;
  2202. /*
  2203. * If this is a jumbo nbuf, then increment the
  2204. * number of nbuf users for each additional
  2205. * segment of the msdu. This will ensure that
  2206. * the skb is freed only after receiving tx
  2207. * completion for all segments of an nbuf
  2208. */
  2209. qdf_nbuf_inc_users(nbuf);
  2210. /* Check with MCL if this is needed */
  2211. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2212. */
  2213. }
  2214. }
  2215. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2216. &htt_tcl_metadata,
  2217. vdev,
  2218. msdu_info);
  2219. /*
  2220. * Enqueue the Tx MSDU descriptor to HW for transmit
  2221. */
  2222. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2223. htt_tcl_metadata,
  2224. NULL, msdu_info);
  2225. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2226. if (status != QDF_STATUS_SUCCESS) {
  2227. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2228. tx_desc, tx_q->ring_id);
  2229. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2230. tid_stats = &pdev->stats.tid_stats.
  2231. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2232. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2233. if (msdu_info->frm_type == dp_tx_frm_me) {
  2234. hw_enq_fail++;
  2235. if (hw_enq_fail == msdu_info->num_seg) {
  2236. /*
  2237. * Unmap is needed only if enqueue
  2238. * failed for all segments.
  2239. */
  2240. qdf_nbuf_unmap(soc->osdev,
  2241. msdu_info->u.sg_info.
  2242. curr_seg->nbuf,
  2243. QDF_DMA_TO_DEVICE);
  2244. }
  2245. /*
  2246. * Free the nbuf for the current segment
  2247. * and make it point to the next in the list.
  2248. * For me, there are as many segments as there
  2249. * are no of clients.
  2250. */
  2251. qdf_nbuf_free(msdu_info->u.sg_info
  2252. .curr_seg->nbuf);
  2253. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2254. if (msdu_info->u.sg_info.curr_seg->next) {
  2255. msdu_info->u.sg_info.curr_seg =
  2256. msdu_info->u.sg_info
  2257. .curr_seg->next;
  2258. nbuf = msdu_info->u.sg_info
  2259. .curr_seg->nbuf;
  2260. } else
  2261. break;
  2262. i++;
  2263. continue;
  2264. }
  2265. /*
  2266. * For TSO frames, the nbuf users increment done for
  2267. * the current segment has to be reverted, since the
  2268. * hw enqueue for this segment failed
  2269. */
  2270. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2271. msdu_info->u.tso_info.curr_seg) {
  2272. /*
  2273. * unmap and free current,
  2274. * retransmit remaining segments
  2275. */
  2276. dp_tx_comp_free_buf(soc, tx_desc);
  2277. i++;
  2278. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2279. continue;
  2280. }
  2281. if (msdu_info->frm_type == dp_tx_frm_sg)
  2282. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2283. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2284. goto done;
  2285. }
  2286. /*
  2287. * TODO
  2288. * if tso_info structure can be modified to have curr_seg
  2289. * as first element, following 2 blocks of code (for TSO and SG)
  2290. * can be combined into 1
  2291. */
  2292. /*
  2293. * For Multicast-Unicast converted packets,
  2294. * each converted frame (for a client) is represented as
  2295. * 1 segment
  2296. */
  2297. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2298. (msdu_info->frm_type == dp_tx_frm_me)) {
  2299. if (msdu_info->u.sg_info.curr_seg->next) {
  2300. msdu_info->u.sg_info.curr_seg =
  2301. msdu_info->u.sg_info.curr_seg->next;
  2302. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2303. } else
  2304. break;
  2305. }
  2306. i++;
  2307. }
  2308. nbuf = NULL;
  2309. done:
  2310. return nbuf;
  2311. }
  2312. /**
  2313. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2314. * for SG frames
  2315. * @vdev: DP vdev handle
  2316. * @nbuf: skb
  2317. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2318. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2319. *
  2320. * Return: NULL on success,
  2321. * nbuf when it fails to send
  2322. */
  2323. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2324. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2325. {
  2326. uint32_t cur_frag, nr_frags, i;
  2327. qdf_dma_addr_t paddr;
  2328. struct dp_tx_sg_info_s *sg_info;
  2329. sg_info = &msdu_info->u.sg_info;
  2330. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2331. if (QDF_STATUS_SUCCESS !=
  2332. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2333. QDF_DMA_TO_DEVICE,
  2334. qdf_nbuf_headlen(nbuf))) {
  2335. dp_tx_err("dma map error");
  2336. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2337. qdf_nbuf_free(nbuf);
  2338. return NULL;
  2339. }
  2340. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2341. seg_info->frags[0].paddr_lo = paddr;
  2342. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2343. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2344. seg_info->frags[0].vaddr = (void *) nbuf;
  2345. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2346. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2347. nbuf, 0,
  2348. QDF_DMA_TO_DEVICE,
  2349. cur_frag)) {
  2350. dp_tx_err("frag dma map error");
  2351. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2352. goto map_err;
  2353. }
  2354. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2355. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2356. seg_info->frags[cur_frag + 1].paddr_hi =
  2357. ((uint64_t) paddr) >> 32;
  2358. seg_info->frags[cur_frag + 1].len =
  2359. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2360. }
  2361. seg_info->frag_cnt = (cur_frag + 1);
  2362. seg_info->total_len = qdf_nbuf_len(nbuf);
  2363. seg_info->next = NULL;
  2364. sg_info->curr_seg = seg_info;
  2365. msdu_info->frm_type = dp_tx_frm_sg;
  2366. msdu_info->num_seg = 1;
  2367. return nbuf;
  2368. map_err:
  2369. /* restore paddr into nbuf before calling unmap */
  2370. qdf_nbuf_mapped_paddr_set(nbuf,
  2371. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2372. ((uint64_t)
  2373. seg_info->frags[0].paddr_hi) << 32));
  2374. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2375. QDF_DMA_TO_DEVICE,
  2376. seg_info->frags[0].len);
  2377. for (i = 1; i <= cur_frag; i++) {
  2378. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2379. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2380. seg_info->frags[i].paddr_hi) << 32),
  2381. seg_info->frags[i].len,
  2382. QDF_DMA_TO_DEVICE);
  2383. }
  2384. qdf_nbuf_free(nbuf);
  2385. return NULL;
  2386. }
  2387. /**
  2388. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2389. * @vdev: DP vdev handle
  2390. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2391. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2392. *
  2393. * Return: NULL on failure,
  2394. * nbuf when extracted successfully
  2395. */
  2396. static
  2397. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2398. struct dp_tx_msdu_info_s *msdu_info,
  2399. uint16_t ppdu_cookie)
  2400. {
  2401. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2402. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2403. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2404. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2405. (msdu_info->meta_data[5], 1);
  2406. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2407. (msdu_info->meta_data[5], 1);
  2408. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2409. (msdu_info->meta_data[6], ppdu_cookie);
  2410. msdu_info->exception_fw = 1;
  2411. msdu_info->is_tx_sniffer = 1;
  2412. }
  2413. #ifdef MESH_MODE_SUPPORT
  2414. /**
  2415. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2416. and prepare msdu_info for mesh frames.
  2417. * @vdev: DP vdev handle
  2418. * @nbuf: skb
  2419. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2420. *
  2421. * Return: NULL on failure,
  2422. * nbuf when extracted successfully
  2423. */
  2424. static
  2425. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2426. struct dp_tx_msdu_info_s *msdu_info)
  2427. {
  2428. struct meta_hdr_s *mhdr;
  2429. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2430. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2431. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2432. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2433. msdu_info->exception_fw = 0;
  2434. goto remove_meta_hdr;
  2435. }
  2436. msdu_info->exception_fw = 1;
  2437. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2438. meta_data->host_tx_desc_pool = 1;
  2439. meta_data->update_peer_cache = 1;
  2440. meta_data->learning_frame = 1;
  2441. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2442. meta_data->power = mhdr->power;
  2443. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2444. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2445. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2446. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2447. meta_data->dyn_bw = 1;
  2448. meta_data->valid_pwr = 1;
  2449. meta_data->valid_mcs_mask = 1;
  2450. meta_data->valid_nss_mask = 1;
  2451. meta_data->valid_preamble_type = 1;
  2452. meta_data->valid_retries = 1;
  2453. meta_data->valid_bw_info = 1;
  2454. }
  2455. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2456. meta_data->encrypt_type = 0;
  2457. meta_data->valid_encrypt_type = 1;
  2458. meta_data->learning_frame = 0;
  2459. }
  2460. meta_data->valid_key_flags = 1;
  2461. meta_data->key_flags = (mhdr->keyix & 0x3);
  2462. remove_meta_hdr:
  2463. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2464. dp_tx_err("qdf_nbuf_pull_head failed");
  2465. qdf_nbuf_free(nbuf);
  2466. return NULL;
  2467. }
  2468. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2469. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2470. " tid %d to_fw %d",
  2471. msdu_info->meta_data[0],
  2472. msdu_info->meta_data[1],
  2473. msdu_info->meta_data[2],
  2474. msdu_info->meta_data[3],
  2475. msdu_info->meta_data[4],
  2476. msdu_info->meta_data[5],
  2477. msdu_info->tid, msdu_info->exception_fw);
  2478. return nbuf;
  2479. }
  2480. #else
  2481. static
  2482. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2483. struct dp_tx_msdu_info_s *msdu_info)
  2484. {
  2485. return nbuf;
  2486. }
  2487. #endif
  2488. /**
  2489. * dp_check_exc_metadata() - Checks if parameters are valid
  2490. * @tx_exc - holds all exception path parameters
  2491. *
  2492. * Returns true when all the parameters are valid else false
  2493. *
  2494. */
  2495. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2496. {
  2497. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2498. HTT_INVALID_TID);
  2499. bool invalid_encap_type =
  2500. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2501. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2502. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2503. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2504. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2505. tx_exc->ppdu_cookie == 0);
  2506. if (tx_exc->is_intrabss_fwd)
  2507. return true;
  2508. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2509. invalid_cookie) {
  2510. return false;
  2511. }
  2512. return true;
  2513. }
  2514. #ifdef ATH_SUPPORT_IQUE
  2515. /**
  2516. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2517. * @vdev: vdev handle
  2518. * @nbuf: skb
  2519. *
  2520. * Return: true on success,
  2521. * false on failure
  2522. */
  2523. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2524. {
  2525. qdf_ether_header_t *eh;
  2526. /* Mcast to Ucast Conversion*/
  2527. if (qdf_likely(!vdev->mcast_enhancement_en))
  2528. return true;
  2529. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2530. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2531. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2532. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2533. qdf_nbuf_set_next(nbuf, NULL);
  2534. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2535. qdf_nbuf_len(nbuf));
  2536. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2537. QDF_STATUS_SUCCESS) {
  2538. return false;
  2539. }
  2540. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2541. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2542. QDF_STATUS_SUCCESS) {
  2543. return false;
  2544. }
  2545. }
  2546. }
  2547. return true;
  2548. }
  2549. #else
  2550. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2551. {
  2552. return true;
  2553. }
  2554. #endif
  2555. /**
  2556. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2557. * @nbuf: qdf_nbuf_t
  2558. * @vdev: struct dp_vdev *
  2559. *
  2560. * Allow packet for processing only if it is for peer client which is
  2561. * connected with same vap. Drop packet if client is connected to
  2562. * different vap.
  2563. *
  2564. * Return: QDF_STATUS
  2565. */
  2566. static inline QDF_STATUS
  2567. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2568. {
  2569. struct dp_ast_entry *dst_ast_entry = NULL;
  2570. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2571. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2572. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2573. return QDF_STATUS_SUCCESS;
  2574. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2575. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2576. eh->ether_dhost,
  2577. vdev->vdev_id);
  2578. /* If there is no ast entry, return failure */
  2579. if (qdf_unlikely(!dst_ast_entry)) {
  2580. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2581. return QDF_STATUS_E_FAILURE;
  2582. }
  2583. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2584. return QDF_STATUS_SUCCESS;
  2585. }
  2586. /**
  2587. * dp_tx_nawds_handler() - NAWDS handler
  2588. *
  2589. * @soc: DP soc handle
  2590. * @vdev_id: id of DP vdev handle
  2591. * @msdu_info: msdu_info required to create HTT metadata
  2592. * @nbuf: skb
  2593. *
  2594. * This API transfers the multicast frames with the peer id
  2595. * on NAWDS enabled peer.
  2596. * Return: none
  2597. */
  2598. static inline
  2599. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2600. struct dp_tx_msdu_info_s *msdu_info,
  2601. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2602. {
  2603. struct dp_peer *peer = NULL;
  2604. qdf_nbuf_t nbuf_clone = NULL;
  2605. uint16_t peer_id = DP_INVALID_PEER;
  2606. struct dp_txrx_peer *txrx_peer;
  2607. /* This check avoids pkt forwarding which is entered
  2608. * in the ast table but still doesn't have valid peerid.
  2609. */
  2610. if (sa_peer_id == HTT_INVALID_PEER)
  2611. return;
  2612. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2613. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2614. txrx_peer = dp_get_txrx_peer(peer);
  2615. if (!txrx_peer)
  2616. continue;
  2617. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2618. peer_id = peer->peer_id;
  2619. if (!dp_peer_is_primary_link_peer(peer))
  2620. continue;
  2621. /* Multicast packets needs to be
  2622. * dropped in case of intra bss forwarding
  2623. */
  2624. if (sa_peer_id == txrx_peer->peer_id) {
  2625. dp_tx_debug("multicast packet");
  2626. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2627. tx.nawds_mcast_drop,
  2628. 1);
  2629. continue;
  2630. }
  2631. nbuf_clone = qdf_nbuf_clone(nbuf);
  2632. if (!nbuf_clone) {
  2633. QDF_TRACE(QDF_MODULE_ID_DP,
  2634. QDF_TRACE_LEVEL_ERROR,
  2635. FL("nbuf clone failed"));
  2636. break;
  2637. }
  2638. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2639. msdu_info, peer_id,
  2640. NULL);
  2641. if (nbuf_clone) {
  2642. dp_tx_debug("pkt send failed");
  2643. qdf_nbuf_free(nbuf_clone);
  2644. } else {
  2645. if (peer_id != DP_INVALID_PEER)
  2646. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2647. tx.nawds_mcast,
  2648. 1, qdf_nbuf_len(nbuf));
  2649. }
  2650. }
  2651. }
  2652. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2653. }
  2654. /**
  2655. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2656. * @soc: DP soc handle
  2657. * @vdev_id: id of DP vdev handle
  2658. * @nbuf: skb
  2659. * @tx_exc_metadata: Handle that holds exception path meta data
  2660. *
  2661. * Entry point for Core Tx layer (DP_TX) invoked from
  2662. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2663. *
  2664. * Return: NULL on success,
  2665. * nbuf when it fails to send
  2666. */
  2667. qdf_nbuf_t
  2668. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2669. qdf_nbuf_t nbuf,
  2670. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2671. {
  2672. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2673. qdf_ether_header_t *eh = NULL;
  2674. struct dp_tx_msdu_info_s msdu_info;
  2675. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2676. DP_MOD_ID_TX_EXCEPTION);
  2677. if (qdf_unlikely(!vdev))
  2678. goto fail;
  2679. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2680. if (!tx_exc_metadata)
  2681. goto fail;
  2682. msdu_info.tid = tx_exc_metadata->tid;
  2683. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2684. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2685. QDF_MAC_ADDR_REF(nbuf->data));
  2686. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2687. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2688. dp_tx_err("Invalid parameters in exception path");
  2689. goto fail;
  2690. }
  2691. /* Basic sanity checks for unsupported packets */
  2692. /* MESH mode */
  2693. if (qdf_unlikely(vdev->mesh_vdev)) {
  2694. dp_tx_err("Mesh mode is not supported in exception path");
  2695. goto fail;
  2696. }
  2697. /*
  2698. * Classify the frame and call corresponding
  2699. * "prepare" function which extracts the segment (TSO)
  2700. * and fragmentation information (for TSO , SG, ME, or Raw)
  2701. * into MSDU_INFO structure which is later used to fill
  2702. * SW and HW descriptors.
  2703. */
  2704. if (qdf_nbuf_is_tso(nbuf)) {
  2705. dp_verbose_debug("TSO frame %pK", vdev);
  2706. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2707. qdf_nbuf_len(nbuf));
  2708. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2709. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2710. qdf_nbuf_len(nbuf));
  2711. goto fail;
  2712. }
  2713. goto send_multiple;
  2714. }
  2715. /* SG */
  2716. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2717. struct dp_tx_seg_info_s seg_info = {0};
  2718. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2719. if (!nbuf)
  2720. goto fail;
  2721. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2722. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2723. qdf_nbuf_len(nbuf));
  2724. goto send_multiple;
  2725. }
  2726. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2727. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2728. qdf_nbuf_len(nbuf));
  2729. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2730. tx_exc_metadata->ppdu_cookie);
  2731. }
  2732. /*
  2733. * Get HW Queue to use for this frame.
  2734. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2735. * dedicated for data and 1 for command.
  2736. * "queue_id" maps to one hardware ring.
  2737. * With each ring, we also associate a unique Tx descriptor pool
  2738. * to minimize lock contention for these resources.
  2739. */
  2740. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2741. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2742. if (qdf_unlikely(vdev->nawds_enabled)) {
  2743. /*
  2744. * This is a multicast packet
  2745. */
  2746. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2747. tx_exc_metadata->peer_id);
  2748. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2749. 1, qdf_nbuf_len(nbuf));
  2750. }
  2751. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2752. DP_INVALID_PEER, NULL);
  2753. } else {
  2754. /*
  2755. * Check exception descriptors
  2756. */
  2757. if (dp_tx_exception_limit_check(vdev))
  2758. goto fail;
  2759. /* Single linear frame */
  2760. /*
  2761. * If nbuf is a simple linear frame, use send_single function to
  2762. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2763. * SRNG. There is no need to setup a MSDU extension descriptor.
  2764. */
  2765. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2766. tx_exc_metadata->peer_id,
  2767. tx_exc_metadata);
  2768. }
  2769. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2770. return nbuf;
  2771. send_multiple:
  2772. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2773. fail:
  2774. if (vdev)
  2775. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2776. dp_verbose_debug("pkt send failed");
  2777. return nbuf;
  2778. }
  2779. /**
  2780. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2781. * in exception path in special case to avoid regular exception path chk.
  2782. * @soc: DP soc handle
  2783. * @vdev_id: id of DP vdev handle
  2784. * @nbuf: skb
  2785. * @tx_exc_metadata: Handle that holds exception path meta data
  2786. *
  2787. * Entry point for Core Tx layer (DP_TX) invoked from
  2788. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2789. *
  2790. * Return: NULL on success,
  2791. * nbuf when it fails to send
  2792. */
  2793. qdf_nbuf_t
  2794. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2795. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2796. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2797. {
  2798. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2799. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2800. DP_MOD_ID_TX_EXCEPTION);
  2801. if (qdf_unlikely(!vdev))
  2802. goto fail;
  2803. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2804. == QDF_STATUS_E_FAILURE)) {
  2805. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2806. goto fail;
  2807. }
  2808. /* Unref count as it will agin be taken inside dp_tx_exception */
  2809. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2810. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2811. fail:
  2812. if (vdev)
  2813. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2814. dp_verbose_debug("pkt send failed");
  2815. return nbuf;
  2816. }
  2817. /**
  2818. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2819. * @soc: DP soc handle
  2820. * @vdev_id: DP vdev handle
  2821. * @nbuf: skb
  2822. *
  2823. * Entry point for Core Tx layer (DP_TX) invoked from
  2824. * hard_start_xmit in OSIF/HDD
  2825. *
  2826. * Return: NULL on success,
  2827. * nbuf when it fails to send
  2828. */
  2829. #ifdef MESH_MODE_SUPPORT
  2830. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2831. qdf_nbuf_t nbuf)
  2832. {
  2833. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2834. struct meta_hdr_s *mhdr;
  2835. qdf_nbuf_t nbuf_mesh = NULL;
  2836. qdf_nbuf_t nbuf_clone = NULL;
  2837. struct dp_vdev *vdev;
  2838. uint8_t no_enc_frame = 0;
  2839. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2840. if (!nbuf_mesh) {
  2841. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2842. "qdf_nbuf_unshare failed");
  2843. return nbuf;
  2844. }
  2845. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2846. if (!vdev) {
  2847. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2848. "vdev is NULL for vdev_id %d", vdev_id);
  2849. return nbuf;
  2850. }
  2851. nbuf = nbuf_mesh;
  2852. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2853. if ((vdev->sec_type != cdp_sec_type_none) &&
  2854. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2855. no_enc_frame = 1;
  2856. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2857. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2858. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2859. !no_enc_frame) {
  2860. nbuf_clone = qdf_nbuf_clone(nbuf);
  2861. if (!nbuf_clone) {
  2862. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2863. "qdf_nbuf_clone failed");
  2864. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2865. return nbuf;
  2866. }
  2867. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2868. }
  2869. if (nbuf_clone) {
  2870. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2871. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2872. } else {
  2873. qdf_nbuf_free(nbuf_clone);
  2874. }
  2875. }
  2876. if (no_enc_frame)
  2877. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2878. else
  2879. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2880. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2881. if ((!nbuf) && no_enc_frame) {
  2882. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2883. }
  2884. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2885. return nbuf;
  2886. }
  2887. #else
  2888. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2889. qdf_nbuf_t nbuf)
  2890. {
  2891. return dp_tx_send(soc, vdev_id, nbuf);
  2892. }
  2893. #endif
  2894. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  2895. static inline
  2896. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2897. {
  2898. if (nbuf) {
  2899. qdf_prefetch(&nbuf->len);
  2900. qdf_prefetch(&nbuf->data);
  2901. }
  2902. }
  2903. #else
  2904. static inline
  2905. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2906. {
  2907. }
  2908. #endif
  2909. /**
  2910. * dp_tx_send() - Transmit a frame on a given VAP
  2911. * @soc: DP soc handle
  2912. * @vdev_id: id of DP vdev handle
  2913. * @nbuf: skb
  2914. *
  2915. * Entry point for Core Tx layer (DP_TX) invoked from
  2916. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2917. * cases
  2918. *
  2919. * Return: NULL on success,
  2920. * nbuf when it fails to send
  2921. */
  2922. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2923. qdf_nbuf_t nbuf)
  2924. {
  2925. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2926. uint16_t peer_id = HTT_INVALID_PEER;
  2927. /*
  2928. * doing a memzero is causing additional function call overhead
  2929. * so doing static stack clearing
  2930. */
  2931. struct dp_tx_msdu_info_s msdu_info = {0};
  2932. struct dp_vdev *vdev = NULL;
  2933. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2934. return nbuf;
  2935. /*
  2936. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2937. * this in per packet path.
  2938. *
  2939. * As in this path vdev memory is already protected with netdev
  2940. * tx lock
  2941. */
  2942. vdev = soc->vdev_id_map[vdev_id];
  2943. if (qdf_unlikely(!vdev))
  2944. return nbuf;
  2945. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2946. QDF_MAC_ADDR_REF(nbuf->data));
  2947. /*
  2948. * Set Default Host TID value to invalid TID
  2949. * (TID override disabled)
  2950. */
  2951. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2952. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2953. if (qdf_unlikely(vdev->mesh_vdev)) {
  2954. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2955. &msdu_info);
  2956. if (!nbuf_mesh) {
  2957. dp_verbose_debug("Extracting mesh metadata failed");
  2958. return nbuf;
  2959. }
  2960. nbuf = nbuf_mesh;
  2961. }
  2962. /*
  2963. * Get HW Queue to use for this frame.
  2964. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2965. * dedicated for data and 1 for command.
  2966. * "queue_id" maps to one hardware ring.
  2967. * With each ring, we also associate a unique Tx descriptor pool
  2968. * to minimize lock contention for these resources.
  2969. */
  2970. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2971. /*
  2972. * TCL H/W supports 2 DSCP-TID mapping tables.
  2973. * Table 1 - Default DSCP-TID mapping table
  2974. * Table 2 - 1 DSCP-TID override table
  2975. *
  2976. * If we need a different DSCP-TID mapping for this vap,
  2977. * call tid_classify to extract DSCP/ToS from frame and
  2978. * map to a TID and store in msdu_info. This is later used
  2979. * to fill in TCL Input descriptor (per-packet TID override).
  2980. */
  2981. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2982. /*
  2983. * Classify the frame and call corresponding
  2984. * "prepare" function which extracts the segment (TSO)
  2985. * and fragmentation information (for TSO , SG, ME, or Raw)
  2986. * into MSDU_INFO structure which is later used to fill
  2987. * SW and HW descriptors.
  2988. */
  2989. if (qdf_nbuf_is_tso(nbuf)) {
  2990. dp_verbose_debug("TSO frame %pK", vdev);
  2991. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2992. qdf_nbuf_len(nbuf));
  2993. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2994. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2995. qdf_nbuf_len(nbuf));
  2996. return nbuf;
  2997. }
  2998. goto send_multiple;
  2999. }
  3000. /* SG */
  3001. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3002. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3003. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3004. return nbuf;
  3005. } else {
  3006. struct dp_tx_seg_info_s seg_info = {0};
  3007. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3008. &msdu_info);
  3009. if (!nbuf)
  3010. return NULL;
  3011. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3012. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3013. qdf_nbuf_len(nbuf));
  3014. goto send_multiple;
  3015. }
  3016. }
  3017. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3018. return NULL;
  3019. /* RAW */
  3020. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3021. struct dp_tx_seg_info_s seg_info = {0};
  3022. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3023. if (!nbuf)
  3024. return NULL;
  3025. dp_verbose_debug("Raw frame %pK", vdev);
  3026. goto send_multiple;
  3027. }
  3028. if (qdf_unlikely(vdev->nawds_enabled)) {
  3029. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3030. qdf_nbuf_data(nbuf);
  3031. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3032. uint16_t sa_peer_id = DP_INVALID_PEER;
  3033. if (!soc->ast_offload_support) {
  3034. struct dp_ast_entry *ast_entry = NULL;
  3035. qdf_spin_lock_bh(&soc->ast_lock);
  3036. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3037. (soc,
  3038. (uint8_t *)(eh->ether_shost),
  3039. vdev->pdev->pdev_id);
  3040. if (ast_entry)
  3041. sa_peer_id = ast_entry->peer_id;
  3042. qdf_spin_unlock_bh(&soc->ast_lock);
  3043. }
  3044. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3045. sa_peer_id);
  3046. }
  3047. peer_id = DP_INVALID_PEER;
  3048. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3049. 1, qdf_nbuf_len(nbuf));
  3050. }
  3051. /* Single linear frame */
  3052. /*
  3053. * If nbuf is a simple linear frame, use send_single function to
  3054. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3055. * SRNG. There is no need to setup a MSDU extension descriptor.
  3056. */
  3057. dp_tx_prefetch_nbuf_data(nbuf);
  3058. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  3059. return nbuf;
  3060. send_multiple:
  3061. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3062. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3063. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3064. return nbuf;
  3065. }
  3066. /**
  3067. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3068. * case to vaoid check in perpkt path.
  3069. * @soc: DP soc handle
  3070. * @vdev_id: id of DP vdev handle
  3071. * @nbuf: skb
  3072. *
  3073. * Entry point for Core Tx layer (DP_TX) invoked from
  3074. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3075. * with special condition to avoid per pkt check in dp_tx_send
  3076. *
  3077. * Return: NULL on success,
  3078. * nbuf when it fails to send
  3079. */
  3080. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3081. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3082. {
  3083. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3084. struct dp_vdev *vdev = NULL;
  3085. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3086. return nbuf;
  3087. /*
  3088. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3089. * this in per packet path.
  3090. *
  3091. * As in this path vdev memory is already protected with netdev
  3092. * tx lock
  3093. */
  3094. vdev = soc->vdev_id_map[vdev_id];
  3095. if (qdf_unlikely(!vdev))
  3096. return nbuf;
  3097. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3098. == QDF_STATUS_E_FAILURE)) {
  3099. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3100. return nbuf;
  3101. }
  3102. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3103. }
  3104. #ifdef UMAC_SUPPORT_PROXY_ARP
  3105. /**
  3106. * dp_tx_proxy_arp() - Tx proxy arp handler
  3107. * @vdev: datapath vdev handle
  3108. * @buf: sk buffer
  3109. *
  3110. * Return: status
  3111. */
  3112. static inline
  3113. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3114. {
  3115. if (vdev->osif_proxy_arp)
  3116. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3117. /*
  3118. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3119. * osif_proxy_arp has a valid function pointer assigned
  3120. * to it
  3121. */
  3122. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3123. return QDF_STATUS_NOT_INITIALIZED;
  3124. }
  3125. #else
  3126. /**
  3127. * dp_tx_proxy_arp() - Tx proxy arp handler
  3128. * @vdev: datapath vdev handle
  3129. * @buf: sk buffer
  3130. *
  3131. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3132. * is not defined.
  3133. *
  3134. * Return: status
  3135. */
  3136. static inline
  3137. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3138. {
  3139. return QDF_STATUS_SUCCESS;
  3140. }
  3141. #endif
  3142. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3143. #ifdef WLAN_MCAST_MLO
  3144. static bool
  3145. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3146. struct dp_tx_desc_s *tx_desc,
  3147. qdf_nbuf_t nbuf,
  3148. uint8_t reinject_reason)
  3149. {
  3150. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3151. if (soc->arch_ops.dp_tx_mcast_handler)
  3152. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3153. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3154. return true;
  3155. }
  3156. return false;
  3157. }
  3158. #else /* WLAN_MCAST_MLO */
  3159. static inline bool
  3160. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3161. struct dp_tx_desc_s *tx_desc,
  3162. qdf_nbuf_t nbuf,
  3163. uint8_t reinject_reason)
  3164. {
  3165. return false;
  3166. }
  3167. #endif /* WLAN_MCAST_MLO */
  3168. #else
  3169. static inline bool
  3170. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3171. struct dp_tx_desc_s *tx_desc,
  3172. qdf_nbuf_t nbuf,
  3173. uint8_t reinject_reason)
  3174. {
  3175. return false;
  3176. }
  3177. #endif
  3178. /**
  3179. * dp_tx_reinject_handler() - Tx Reinject Handler
  3180. * @soc: datapath soc handle
  3181. * @vdev: datapath vdev handle
  3182. * @tx_desc: software descriptor head pointer
  3183. * @status : Tx completion status from HTT descriptor
  3184. * @reinject_reason : reinject reason from HTT descriptor
  3185. *
  3186. * This function reinjects frames back to Target.
  3187. * Todo - Host queue needs to be added
  3188. *
  3189. * Return: none
  3190. */
  3191. void dp_tx_reinject_handler(struct dp_soc *soc,
  3192. struct dp_vdev *vdev,
  3193. struct dp_tx_desc_s *tx_desc,
  3194. uint8_t *status,
  3195. uint8_t reinject_reason)
  3196. {
  3197. struct dp_peer *peer = NULL;
  3198. uint32_t peer_id = HTT_INVALID_PEER;
  3199. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3200. qdf_nbuf_t nbuf_copy = NULL;
  3201. struct dp_tx_msdu_info_s msdu_info;
  3202. #ifdef WDS_VENDOR_EXTENSION
  3203. int is_mcast = 0, is_ucast = 0;
  3204. int num_peers_3addr = 0;
  3205. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3206. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3207. #endif
  3208. struct dp_txrx_peer *txrx_peer;
  3209. qdf_assert(vdev);
  3210. dp_tx_debug("Tx reinject path");
  3211. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3212. qdf_nbuf_len(tx_desc->nbuf));
  3213. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3214. return;
  3215. #ifdef WDS_VENDOR_EXTENSION
  3216. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3217. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3218. } else {
  3219. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3220. }
  3221. is_ucast = !is_mcast;
  3222. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3223. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3224. txrx_peer = dp_get_txrx_peer(peer);
  3225. if (!txrx_peer || txrx_peer->bss_peer)
  3226. continue;
  3227. /* Detect wds peers that use 3-addr framing for mcast.
  3228. * if there are any, the bss_peer is used to send the
  3229. * the mcast frame using 3-addr format. all wds enabled
  3230. * peers that use 4-addr framing for mcast frames will
  3231. * be duplicated and sent as 4-addr frames below.
  3232. */
  3233. if (!txrx_peer->wds_enabled ||
  3234. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3235. num_peers_3addr = 1;
  3236. break;
  3237. }
  3238. }
  3239. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3240. #endif
  3241. if (qdf_unlikely(vdev->mesh_vdev)) {
  3242. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3243. } else {
  3244. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3245. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3246. txrx_peer = dp_get_txrx_peer(peer);
  3247. if (!txrx_peer)
  3248. continue;
  3249. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3250. #ifdef WDS_VENDOR_EXTENSION
  3251. /*
  3252. * . if 3-addr STA, then send on BSS Peer
  3253. * . if Peer WDS enabled and accept 4-addr mcast,
  3254. * send mcast on that peer only
  3255. * . if Peer WDS enabled and accept 4-addr ucast,
  3256. * send ucast on that peer only
  3257. */
  3258. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3259. (txrx_peer->wds_enabled &&
  3260. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3261. (is_ucast &&
  3262. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3263. #else
  3264. (txrx_peer->bss_peer &&
  3265. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3266. #endif
  3267. peer_id = DP_INVALID_PEER;
  3268. nbuf_copy = qdf_nbuf_copy(nbuf);
  3269. if (!nbuf_copy) {
  3270. dp_tx_debug("nbuf copy failed");
  3271. break;
  3272. }
  3273. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3274. dp_tx_get_queue(vdev, nbuf,
  3275. &msdu_info.tx_queue);
  3276. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3277. nbuf_copy,
  3278. &msdu_info,
  3279. peer_id,
  3280. NULL);
  3281. if (nbuf_copy) {
  3282. dp_tx_debug("pkt send failed");
  3283. qdf_nbuf_free(nbuf_copy);
  3284. }
  3285. }
  3286. }
  3287. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3288. }
  3289. qdf_nbuf_free(nbuf);
  3290. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3291. }
  3292. /**
  3293. * dp_tx_inspect_handler() - Tx Inspect Handler
  3294. * @soc: datapath soc handle
  3295. * @vdev: datapath vdev handle
  3296. * @tx_desc: software descriptor head pointer
  3297. * @status : Tx completion status from HTT descriptor
  3298. *
  3299. * Handles Tx frames sent back to Host for inspection
  3300. * (ProxyARP)
  3301. *
  3302. * Return: none
  3303. */
  3304. void dp_tx_inspect_handler(struct dp_soc *soc,
  3305. struct dp_vdev *vdev,
  3306. struct dp_tx_desc_s *tx_desc,
  3307. uint8_t *status)
  3308. {
  3309. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3310. "%s Tx inspect path",
  3311. __func__);
  3312. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3313. qdf_nbuf_len(tx_desc->nbuf));
  3314. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3315. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3316. }
  3317. #ifdef MESH_MODE_SUPPORT
  3318. /**
  3319. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3320. * in mesh meta header
  3321. * @tx_desc: software descriptor head pointer
  3322. * @ts: pointer to tx completion stats
  3323. * Return: none
  3324. */
  3325. static
  3326. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3327. struct hal_tx_completion_status *ts)
  3328. {
  3329. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3330. if (!tx_desc->msdu_ext_desc) {
  3331. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3332. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3333. "netbuf %pK offset %d",
  3334. netbuf, tx_desc->pkt_offset);
  3335. return;
  3336. }
  3337. }
  3338. }
  3339. #else
  3340. static
  3341. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3342. struct hal_tx_completion_status *ts)
  3343. {
  3344. }
  3345. #endif
  3346. #ifdef CONFIG_SAWF
  3347. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3348. struct dp_vdev *vdev,
  3349. struct dp_txrx_peer *txrx_peer,
  3350. struct dp_tx_desc_s *tx_desc,
  3351. struct hal_tx_completion_status *ts,
  3352. uint8_t tid)
  3353. {
  3354. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3355. ts, tid);
  3356. }
  3357. #else
  3358. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3359. struct dp_vdev *vdev,
  3360. struct dp_txrx_peer *txrx_peer,
  3361. struct dp_tx_desc_s *tx_desc,
  3362. struct hal_tx_completion_status *ts,
  3363. uint8_t tid)
  3364. {
  3365. }
  3366. #endif
  3367. #ifdef QCA_PEER_EXT_STATS
  3368. /*
  3369. * dp_tx_compute_tid_delay() - Compute per TID delay
  3370. * @stats: Per TID delay stats
  3371. * @tx_desc: Software Tx descriptor
  3372. *
  3373. * Compute the software enqueue and hw enqueue delays and
  3374. * update the respective histograms
  3375. *
  3376. * Return: void
  3377. */
  3378. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3379. struct dp_tx_desc_s *tx_desc)
  3380. {
  3381. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3382. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3383. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3384. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3385. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3386. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3387. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3388. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3389. timestamp_hw_enqueue);
  3390. /*
  3391. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3392. */
  3393. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3394. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3395. }
  3396. /*
  3397. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3398. * @txrx_peer: DP peer context
  3399. * @tx_desc: Tx software descriptor
  3400. * @tid: Transmission ID
  3401. * @ring_id: Rx CPU context ID/CPU_ID
  3402. *
  3403. * Update the peer extended stats. These are enhanced other
  3404. * delay stats per msdu level.
  3405. *
  3406. * Return: void
  3407. */
  3408. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3409. struct dp_tx_desc_s *tx_desc,
  3410. uint8_t tid, uint8_t ring_id)
  3411. {
  3412. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3413. struct dp_soc *soc = NULL;
  3414. struct dp_peer_delay_stats *delay_stats = NULL;
  3415. soc = pdev->soc;
  3416. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3417. return;
  3418. delay_stats = txrx_peer->delay_stats;
  3419. qdf_assert(delay_stats);
  3420. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3421. /*
  3422. * For non-TID packets use the TID 9
  3423. */
  3424. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3425. tid = CDP_MAX_DATA_TIDS - 1;
  3426. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3427. tx_desc);
  3428. }
  3429. #else
  3430. static inline void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3431. struct dp_tx_desc_s *tx_desc,
  3432. uint8_t tid, uint8_t ring_id)
  3433. {
  3434. }
  3435. #endif
  3436. #ifdef HW_TX_DELAY_STATS_ENABLE
  3437. /**
  3438. * dp_update_tx_delay_stats() - update the delay stats
  3439. * @vdev: vdev handle
  3440. * @delay: delay in ms or us based on the flag delay_in_us
  3441. * @tid: tid value
  3442. * @mode: type of tx delay mode
  3443. * @ring id: ring number
  3444. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3445. *
  3446. * Return: none
  3447. */
  3448. static inline
  3449. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3450. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3451. {
  3452. struct cdp_tid_tx_stats *tstats =
  3453. &vdev->stats.tid_tx_stats[ring_id][tid];
  3454. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3455. delay_in_us);
  3456. }
  3457. #else
  3458. static inline
  3459. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3460. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3461. {
  3462. struct cdp_tid_tx_stats *tstats =
  3463. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3464. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3465. delay_in_us);
  3466. }
  3467. #endif
  3468. /**
  3469. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3470. * to pass in correct fields
  3471. *
  3472. * @vdev: pdev handle
  3473. * @tx_desc: tx descriptor
  3474. * @tid: tid value
  3475. * @ring_id: TCL or WBM ring number for transmit path
  3476. * Return: none
  3477. */
  3478. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3479. uint8_t tid, uint8_t ring_id)
  3480. {
  3481. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3482. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3483. uint32_t fwhw_transmit_delay_us;
  3484. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3485. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3486. return;
  3487. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3488. fwhw_transmit_delay_us =
  3489. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3490. qdf_ktime_to_us(tx_desc->timestamp);
  3491. /*
  3492. * Delay between packet enqueued to HW and Tx completion in us
  3493. */
  3494. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3495. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3496. ring_id, true);
  3497. /*
  3498. * For MCL, only enqueue to completion delay is required
  3499. * so return if the vdev flag is enabled.
  3500. */
  3501. return;
  3502. }
  3503. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3504. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3505. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3506. timestamp_hw_enqueue);
  3507. /*
  3508. * Delay between packet enqueued to HW and Tx completion in ms
  3509. */
  3510. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3511. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3512. false);
  3513. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3514. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3515. interframe_delay = (uint32_t)(timestamp_ingress -
  3516. vdev->prev_tx_enq_tstamp);
  3517. /*
  3518. * Delay in software enqueue
  3519. */
  3520. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3521. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3522. false);
  3523. /*
  3524. * Update interframe delay stats calculated at hardstart receive point.
  3525. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3526. * interframe delay will not be calculate correctly for 1st frame.
  3527. * On the other side, this will help in avoiding extra per packet check
  3528. * of !vdev->prev_tx_enq_tstamp.
  3529. */
  3530. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3531. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3532. false);
  3533. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3534. }
  3535. #ifdef DISABLE_DP_STATS
  3536. static
  3537. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3538. struct dp_txrx_peer *txrx_peer)
  3539. {
  3540. }
  3541. #else
  3542. static inline void
  3543. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3544. {
  3545. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3546. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3547. if (subtype != QDF_PROTO_INVALID)
  3548. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3549. 1);
  3550. }
  3551. #endif
  3552. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3553. /**
  3554. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3555. *
  3556. * @ts: Tx compltion status
  3557. * @txrx_peer: datapath txrx_peer handle
  3558. *
  3559. * Return: void
  3560. */
  3561. static inline void
  3562. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3563. struct dp_txrx_peer *txrx_peer)
  3564. {
  3565. uint8_t mcs, pkt_type, retry_threshold;
  3566. mcs = ts->mcs;
  3567. pkt_type = ts->pkt_type;
  3568. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3569. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3570. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3571. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3572. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3573. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3574. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3575. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3576. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3577. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3578. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3579. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3580. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3581. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3582. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3583. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3584. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3585. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3586. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3587. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3588. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3589. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3590. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3591. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3592. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3593. tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3594. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3595. DP_PEER_EXTD_STATS_INCC(txrx_peer,
  3596. tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3597. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3598. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  3599. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  3600. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3601. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3602. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3603. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  3604. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  3605. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  3606. if (ts->first_msdu) {
  3607. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3608. ts->transmit_cnt > 1);
  3609. switch (ts->bw) {
  3610. case 0: /* 20Mhz */
  3611. case 1: /* 40Mhz */
  3612. case 2: /* 80Mhz */
  3613. retry_threshold = txrx_peer->mpdu_retry_threshold_1;
  3614. break;
  3615. default: /* 160Mhz */
  3616. retry_threshold = txrx_peer->mpdu_retry_threshold_2;
  3617. break;
  3618. }
  3619. if (!retry_threshold)
  3620. return;
  3621. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3622. qdf_do_div(ts->transmit_cnt,
  3623. retry_threshold),
  3624. ts->transmit_cnt > retry_threshold);
  3625. }
  3626. }
  3627. #else
  3628. static inline void
  3629. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3630. struct dp_txrx_peer *txrx_peer)
  3631. {
  3632. }
  3633. #endif
  3634. /**
  3635. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3636. * per wbm ring
  3637. *
  3638. * @tx_desc: software descriptor head pointer
  3639. * @ts: Tx completion status
  3640. * @peer: peer handle
  3641. * @ring_id: ring number
  3642. *
  3643. * Return: None
  3644. */
  3645. static inline void
  3646. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3647. struct hal_tx_completion_status *ts,
  3648. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  3649. {
  3650. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3651. uint8_t tid = ts->tid;
  3652. uint32_t length;
  3653. struct cdp_tid_tx_stats *tid_stats;
  3654. if (!pdev)
  3655. return;
  3656. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3657. tid = CDP_MAX_DATA_TIDS - 1;
  3658. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3659. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3660. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  3661. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  3662. return;
  3663. }
  3664. length = qdf_nbuf_len(tx_desc->nbuf);
  3665. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  3666. if (qdf_unlikely(pdev->delay_stats_flag) ||
  3667. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  3668. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  3669. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3670. tid_stats->tqm_status_cnt[ts->status]++;
  3671. }
  3672. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  3673. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  3674. ts->transmit_cnt > 1);
  3675. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  3676. 1, ts->transmit_cnt > 2);
  3677. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  3678. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  3679. ts->msdu_part_of_amsdu);
  3680. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  3681. !ts->msdu_part_of_amsdu);
  3682. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  3683. qdf_system_ticks();
  3684. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  3685. return;
  3686. }
  3687. /*
  3688. * tx_failed is ideally supposed to be updated from HTT ppdu
  3689. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  3690. * hw limitation there are no completions for failed cases.
  3691. * Hence updating tx_failed from data path. Please note that
  3692. * if tx_failed is fixed to be from ppdu, then this has to be
  3693. * removed
  3694. */
  3695. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  3696. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  3697. ts->transmit_cnt > DP_RETRY_COUNT);
  3698. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  3699. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  3700. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  3701. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  3702. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  3703. length);
  3704. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  3705. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  3706. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  3707. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  3708. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  3709. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  3710. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  3711. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  3712. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  3713. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  3714. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  3715. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3716. tx.dropped.fw_rem_queue_disable, 1);
  3717. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  3718. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3719. tx.dropped.fw_rem_no_match, 1);
  3720. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  3721. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3722. tx.dropped.drop_threshold, 1);
  3723. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  3724. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3725. tx.dropped.drop_link_desc_na, 1);
  3726. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  3727. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3728. tx.dropped.invalid_drop, 1);
  3729. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  3730. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3731. tx.dropped.mcast_vdev_drop, 1);
  3732. } else {
  3733. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  3734. }
  3735. }
  3736. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3737. /**
  3738. * dp_tx_flow_pool_lock() - take flow pool lock
  3739. * @soc: core txrx main context
  3740. * @tx_desc: tx desc
  3741. *
  3742. * Return: None
  3743. */
  3744. static inline
  3745. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3746. struct dp_tx_desc_s *tx_desc)
  3747. {
  3748. struct dp_tx_desc_pool_s *pool;
  3749. uint8_t desc_pool_id;
  3750. desc_pool_id = tx_desc->pool_id;
  3751. pool = &soc->tx_desc[desc_pool_id];
  3752. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3753. }
  3754. /**
  3755. * dp_tx_flow_pool_unlock() - release flow pool lock
  3756. * @soc: core txrx main context
  3757. * @tx_desc: tx desc
  3758. *
  3759. * Return: None
  3760. */
  3761. static inline
  3762. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3763. struct dp_tx_desc_s *tx_desc)
  3764. {
  3765. struct dp_tx_desc_pool_s *pool;
  3766. uint8_t desc_pool_id;
  3767. desc_pool_id = tx_desc->pool_id;
  3768. pool = &soc->tx_desc[desc_pool_id];
  3769. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3770. }
  3771. #else
  3772. static inline
  3773. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3774. {
  3775. }
  3776. static inline
  3777. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3778. {
  3779. }
  3780. #endif
  3781. /**
  3782. * dp_tx_notify_completion() - Notify tx completion for this desc
  3783. * @soc: core txrx main context
  3784. * @vdev: datapath vdev handle
  3785. * @tx_desc: tx desc
  3786. * @netbuf: buffer
  3787. * @status: tx status
  3788. *
  3789. * Return: none
  3790. */
  3791. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3792. struct dp_vdev *vdev,
  3793. struct dp_tx_desc_s *tx_desc,
  3794. qdf_nbuf_t netbuf,
  3795. uint8_t status)
  3796. {
  3797. void *osif_dev;
  3798. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3799. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3800. qdf_assert(tx_desc);
  3801. if (!vdev ||
  3802. !vdev->osif_vdev) {
  3803. return;
  3804. }
  3805. osif_dev = vdev->osif_vdev;
  3806. tx_compl_cbk = vdev->tx_comp;
  3807. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3808. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3809. if (tx_compl_cbk)
  3810. tx_compl_cbk(netbuf, osif_dev, flag);
  3811. }
  3812. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3813. * @pdev: pdev handle
  3814. * @tid: tid value
  3815. * @txdesc_ts: timestamp from txdesc
  3816. * @ppdu_id: ppdu id
  3817. *
  3818. * Return: none
  3819. */
  3820. #ifdef FEATURE_PERPKT_INFO
  3821. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3822. struct dp_txrx_peer *txrx_peer,
  3823. uint8_t tid,
  3824. uint64_t txdesc_ts,
  3825. uint32_t ppdu_id)
  3826. {
  3827. uint64_t delta_ms;
  3828. struct cdp_tx_sojourn_stats *sojourn_stats;
  3829. struct dp_peer *primary_link_peer = NULL;
  3830. struct dp_soc *link_peer_soc = NULL;
  3831. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3832. return;
  3833. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3834. tid >= CDP_DATA_TID_MAX))
  3835. return;
  3836. if (qdf_unlikely(!pdev->sojourn_buf))
  3837. return;
  3838. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  3839. txrx_peer->peer_id,
  3840. DP_MOD_ID_TX_COMP);
  3841. if (qdf_unlikely(!primary_link_peer))
  3842. return;
  3843. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3844. qdf_nbuf_data(pdev->sojourn_buf);
  3845. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  3846. sojourn_stats->cookie = (void *)
  3847. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  3848. primary_link_peer);
  3849. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3850. txdesc_ts;
  3851. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  3852. delta_ms);
  3853. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3854. sojourn_stats->num_msdus[tid] = 1;
  3855. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3856. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  3857. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3858. pdev->sojourn_buf, HTT_INVALID_PEER,
  3859. WDI_NO_VAL, pdev->pdev_id);
  3860. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3861. sojourn_stats->num_msdus[tid] = 0;
  3862. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3863. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  3864. }
  3865. #else
  3866. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3867. struct dp_txrx_peer *txrx_peer,
  3868. uint8_t tid,
  3869. uint64_t txdesc_ts,
  3870. uint32_t ppdu_id)
  3871. {
  3872. }
  3873. #endif
  3874. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3875. /**
  3876. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3877. * @soc: dp_soc handle
  3878. * @desc: Tx Descriptor
  3879. * @ts: HAL Tx completion descriptor contents
  3880. *
  3881. * This function is used to send tx completion to packet capture
  3882. */
  3883. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3884. struct dp_tx_desc_s *desc,
  3885. struct hal_tx_completion_status *ts)
  3886. {
  3887. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3888. desc, ts->peer_id,
  3889. WDI_NO_VAL, desc->pdev->pdev_id);
  3890. }
  3891. #endif
  3892. /**
  3893. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3894. * @soc: DP Soc handle
  3895. * @tx_desc: software Tx descriptor
  3896. * @ts : Tx completion status from HAL/HTT descriptor
  3897. *
  3898. * Return: none
  3899. */
  3900. void
  3901. dp_tx_comp_process_desc(struct dp_soc *soc,
  3902. struct dp_tx_desc_s *desc,
  3903. struct hal_tx_completion_status *ts,
  3904. struct dp_txrx_peer *txrx_peer)
  3905. {
  3906. uint64_t time_latency = 0;
  3907. uint16_t peer_id = DP_INVALID_PEER_ID;
  3908. /*
  3909. * m_copy/tx_capture modes are not supported for
  3910. * scatter gather packets
  3911. */
  3912. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3913. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3914. qdf_ktime_to_ms(desc->timestamp));
  3915. }
  3916. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3917. if (dp_tx_pkt_tracepoints_enabled())
  3918. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  3919. desc->msdu_ext_desc ?
  3920. desc->msdu_ext_desc->tso_desc : NULL,
  3921. qdf_ktime_to_ms(desc->timestamp));
  3922. if (!(desc->msdu_ext_desc)) {
  3923. dp_tx_enh_unmap(soc, desc);
  3924. if (txrx_peer)
  3925. peer_id = txrx_peer->peer_id;
  3926. if (QDF_STATUS_SUCCESS ==
  3927. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  3928. return;
  3929. }
  3930. if (QDF_STATUS_SUCCESS ==
  3931. dp_get_completion_indication_for_stack(soc,
  3932. desc->pdev,
  3933. txrx_peer, ts,
  3934. desc->nbuf,
  3935. time_latency)) {
  3936. dp_send_completion_to_stack(soc,
  3937. desc->pdev,
  3938. ts->peer_id,
  3939. ts->ppdu_id,
  3940. desc->nbuf);
  3941. return;
  3942. }
  3943. }
  3944. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  3945. dp_tx_comp_free_buf(soc, desc);
  3946. }
  3947. #ifdef DISABLE_DP_STATS
  3948. /**
  3949. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3950. * @soc: core txrx main context
  3951. * @tx_desc: tx desc
  3952. * @status: tx status
  3953. *
  3954. * Return: none
  3955. */
  3956. static inline
  3957. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3958. struct dp_vdev *vdev,
  3959. struct dp_tx_desc_s *tx_desc,
  3960. uint8_t status)
  3961. {
  3962. }
  3963. #else
  3964. static inline
  3965. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3966. struct dp_vdev *vdev,
  3967. struct dp_tx_desc_s *tx_desc,
  3968. uint8_t status)
  3969. {
  3970. void *osif_dev;
  3971. ol_txrx_stats_rx_fp stats_cbk;
  3972. uint8_t pkt_type;
  3973. qdf_assert(tx_desc);
  3974. if (!vdev ||
  3975. !vdev->osif_vdev ||
  3976. !vdev->stats_cb)
  3977. return;
  3978. osif_dev = vdev->osif_vdev;
  3979. stats_cbk = vdev->stats_cb;
  3980. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3981. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3982. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3983. &pkt_type);
  3984. }
  3985. #endif
  3986. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(CONFIG_SAWF)
  3987. QDF_STATUS
  3988. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  3989. uint32_t delta_tsf,
  3990. uint32_t *delay_us)
  3991. {
  3992. uint32_t buffer_ts;
  3993. uint32_t delay;
  3994. if (!delay_us)
  3995. return QDF_STATUS_E_INVAL;
  3996. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  3997. if (!ts->valid)
  3998. return QDF_STATUS_E_INVAL;
  3999. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4000. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4001. * valid up to 29 bits.
  4002. */
  4003. buffer_ts = ts->buffer_timestamp << 10;
  4004. delay = ts->tsf - buffer_ts - delta_tsf;
  4005. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4006. if (delay > 0x1000000) {
  4007. dp_info_rl("----------------------\n"
  4008. "Tx completion status:\n"
  4009. "----------------------\n"
  4010. "release_src = %d\n"
  4011. "ppdu_id = 0x%x\n"
  4012. "release_reason = %d\n"
  4013. "tsf = %u (0x%x)\n"
  4014. "buffer_timestamp = %u (0x%x)\n"
  4015. "delta_tsf = %u (0x%x)\n",
  4016. ts->release_src, ts->ppdu_id, ts->status,
  4017. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4018. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4019. return QDF_STATUS_E_FAILURE;
  4020. }
  4021. *delay_us = delay;
  4022. return QDF_STATUS_SUCCESS;
  4023. }
  4024. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4025. uint32_t delta_tsf)
  4026. {
  4027. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4028. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4029. DP_MOD_ID_CDP);
  4030. if (!vdev) {
  4031. dp_err_rl("vdev %d does not exist", vdev_id);
  4032. return;
  4033. }
  4034. vdev->delta_tsf = delta_tsf;
  4035. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4036. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4037. }
  4038. #endif
  4039. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4040. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4041. uint8_t vdev_id, bool enable)
  4042. {
  4043. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4044. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4045. DP_MOD_ID_CDP);
  4046. if (!vdev) {
  4047. dp_err_rl("vdev %d does not exist", vdev_id);
  4048. return QDF_STATUS_E_FAILURE;
  4049. }
  4050. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4051. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4052. return QDF_STATUS_SUCCESS;
  4053. }
  4054. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4055. uint32_t *val)
  4056. {
  4057. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4058. struct dp_vdev *vdev;
  4059. uint32_t delay_accum;
  4060. uint32_t pkts_accum;
  4061. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4062. if (!vdev) {
  4063. dp_err_rl("vdev %d does not exist", vdev_id);
  4064. return QDF_STATUS_E_FAILURE;
  4065. }
  4066. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4067. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4068. return QDF_STATUS_E_FAILURE;
  4069. }
  4070. /* Average uplink delay based on current accumulated values */
  4071. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4072. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4073. *val = delay_accum / pkts_accum;
  4074. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4075. delay_accum, pkts_accum);
  4076. /* Reset accumulated values to 0 */
  4077. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4078. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4079. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4080. return QDF_STATUS_SUCCESS;
  4081. }
  4082. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4083. struct hal_tx_completion_status *ts)
  4084. {
  4085. uint32_t ul_delay;
  4086. if (qdf_unlikely(!vdev)) {
  4087. dp_info_rl("vdev is null or delete in progrss");
  4088. return;
  4089. }
  4090. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4091. return;
  4092. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4093. vdev->delta_tsf,
  4094. &ul_delay)))
  4095. return;
  4096. ul_delay /= 1000; /* in unit of ms */
  4097. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4098. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4099. }
  4100. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4101. static inline
  4102. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4103. struct hal_tx_completion_status *ts)
  4104. {
  4105. }
  4106. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4107. /**
  4108. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4109. * @soc: DP soc handle
  4110. * @tx_desc: software descriptor head pointer
  4111. * @ts: Tx completion status
  4112. * @txrx_peer: txrx peer handle
  4113. * @ring_id: ring number
  4114. *
  4115. * Return: none
  4116. */
  4117. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4118. struct dp_tx_desc_s *tx_desc,
  4119. struct hal_tx_completion_status *ts,
  4120. struct dp_txrx_peer *txrx_peer,
  4121. uint8_t ring_id)
  4122. {
  4123. uint32_t length;
  4124. qdf_ether_header_t *eh;
  4125. struct dp_vdev *vdev = NULL;
  4126. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4127. enum qdf_dp_tx_rx_status dp_status;
  4128. if (!nbuf) {
  4129. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4130. goto out;
  4131. }
  4132. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4133. length = qdf_nbuf_len(nbuf);
  4134. dp_status = dp_tx_hw_to_qdf(ts->status);
  4135. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4136. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4137. QDF_TRACE_DEFAULT_PDEV_ID,
  4138. qdf_nbuf_data_addr(nbuf),
  4139. sizeof(qdf_nbuf_data(nbuf)),
  4140. tx_desc->id, ts->status, dp_status));
  4141. dp_tx_comp_debug("-------------------- \n"
  4142. "Tx Completion Stats: \n"
  4143. "-------------------- \n"
  4144. "ack_frame_rssi = %d \n"
  4145. "first_msdu = %d \n"
  4146. "last_msdu = %d \n"
  4147. "msdu_part_of_amsdu = %d \n"
  4148. "rate_stats valid = %d \n"
  4149. "bw = %d \n"
  4150. "pkt_type = %d \n"
  4151. "stbc = %d \n"
  4152. "ldpc = %d \n"
  4153. "sgi = %d \n"
  4154. "mcs = %d \n"
  4155. "ofdma = %d \n"
  4156. "tones_in_ru = %d \n"
  4157. "tsf = %d \n"
  4158. "ppdu_id = %d \n"
  4159. "transmit_cnt = %d \n"
  4160. "tid = %d \n"
  4161. "peer_id = %d\n"
  4162. "tx_status = %d\n",
  4163. ts->ack_frame_rssi, ts->first_msdu,
  4164. ts->last_msdu, ts->msdu_part_of_amsdu,
  4165. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4166. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4167. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4168. ts->transmit_cnt, ts->tid, ts->peer_id,
  4169. ts->status);
  4170. /* Update SoC level stats */
  4171. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4172. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4173. if (!txrx_peer) {
  4174. dp_info_rl("peer is null or deletion in progress");
  4175. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4176. goto out;
  4177. }
  4178. vdev = txrx_peer->vdev;
  4179. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4180. dp_tx_update_uplink_delay(soc, vdev, ts);
  4181. /* check tx complete notification */
  4182. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4183. dp_tx_notify_completion(soc, vdev, tx_desc,
  4184. nbuf, ts->status);
  4185. /* Update per-packet stats for mesh mode */
  4186. if (qdf_unlikely(vdev->mesh_vdev) &&
  4187. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4188. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4189. /* Update peer level stats */
  4190. if (qdf_unlikely(txrx_peer->bss_peer &&
  4191. vdev->opmode == wlan_op_mode_ap)) {
  4192. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4193. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4194. length);
  4195. if (txrx_peer->vdev->tx_encap_type ==
  4196. htt_cmn_pkt_type_ethernet &&
  4197. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4198. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4199. tx.bcast, 1,
  4200. length);
  4201. }
  4202. }
  4203. } else {
  4204. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4205. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4206. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4207. 1, length);
  4208. if (qdf_unlikely(txrx_peer->in_twt)) {
  4209. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4210. tx.tx_success_twt,
  4211. 1, length);
  4212. }
  4213. }
  4214. }
  4215. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4216. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts->tid, ring_id);
  4217. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4218. ts, ts->tid);
  4219. #ifdef QCA_SUPPORT_RDK_STATS
  4220. if (soc->peerstats_enabled)
  4221. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4222. qdf_ktime_to_ms(tx_desc->timestamp),
  4223. ts->ppdu_id);
  4224. #endif
  4225. out:
  4226. return;
  4227. }
  4228. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4229. defined(QCA_ENHANCED_STATS_SUPPORT)
  4230. /*
  4231. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4232. * @txrx_peer: Datapath txrx_peer handle
  4233. * @length: Length of the packet
  4234. * @tx_status: Tx status from TQM/FW
  4235. * @update: enhanced flag value present in dp_pdev
  4236. *
  4237. * Return: none
  4238. */
  4239. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4240. uint32_t length, uint8_t tx_status,
  4241. bool update)
  4242. {
  4243. if ((!txrx_peer->hw_txrx_stats_en) || update) {
  4244. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4245. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4246. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4247. }
  4248. }
  4249. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4250. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4251. uint32_t length, uint8_t tx_status,
  4252. bool update)
  4253. {
  4254. if (!peer->hw_txrx_stats_en) {
  4255. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4256. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4257. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4258. }
  4259. }
  4260. #else
  4261. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4262. uint32_t length, uint8_t tx_status,
  4263. bool update)
  4264. {
  4265. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4266. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4267. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4268. }
  4269. #endif
  4270. /*
  4271. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4272. * @nbuf: skb buffer
  4273. *
  4274. * Return: none
  4275. */
  4276. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4277. static inline
  4278. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4279. {
  4280. qdf_nbuf_t nbuf = NULL;
  4281. if (next)
  4282. nbuf = next->nbuf;
  4283. if (nbuf) {
  4284. /* prefetch skb->next and first few bytes of skb->cb */
  4285. qdf_prefetch(nbuf);
  4286. /* prefetch skb fields present in different cachelines */
  4287. qdf_prefetch(&nbuf->len);
  4288. qdf_prefetch(&nbuf->users);
  4289. }
  4290. }
  4291. #else
  4292. static inline
  4293. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4294. {
  4295. }
  4296. #endif
  4297. /**
  4298. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4299. * @soc: core txrx main context
  4300. * @desc: software descriptor
  4301. *
  4302. * Return: true when packet is reinjected
  4303. */
  4304. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4305. defined(WLAN_MCAST_MLO)
  4306. static inline bool
  4307. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4308. {
  4309. struct dp_vdev *vdev = NULL;
  4310. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4311. if (!soc->arch_ops.dp_tx_mcast_handler)
  4312. return false;
  4313. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4314. DP_MOD_ID_REINJECT);
  4315. if (qdf_unlikely(!vdev)) {
  4316. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4317. desc->id);
  4318. return false;
  4319. }
  4320. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4321. qdf_nbuf_len(desc->nbuf));
  4322. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4323. dp_tx_desc_release(desc, desc->pool_id);
  4324. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4325. return true;
  4326. }
  4327. return false;
  4328. }
  4329. #else
  4330. static inline bool
  4331. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4332. {
  4333. return false;
  4334. }
  4335. #endif
  4336. /**
  4337. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4338. * @soc: core txrx main context
  4339. * @comp_head: software descriptor head pointer
  4340. * @ring_id: ring number
  4341. *
  4342. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4343. * and release the software descriptors after processing is complete
  4344. *
  4345. * Return: none
  4346. */
  4347. static void
  4348. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4349. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4350. {
  4351. struct dp_tx_desc_s *desc;
  4352. struct dp_tx_desc_s *next;
  4353. struct hal_tx_completion_status ts;
  4354. struct dp_txrx_peer *txrx_peer = NULL;
  4355. uint16_t peer_id = DP_INVALID_PEER;
  4356. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4357. desc = comp_head;
  4358. while (desc) {
  4359. next = desc->next;
  4360. dp_tx_prefetch_next_nbuf_data(next);
  4361. if (peer_id != desc->peer_id) {
  4362. if (txrx_peer)
  4363. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4364. DP_MOD_ID_TX_COMP);
  4365. peer_id = desc->peer_id;
  4366. txrx_peer =
  4367. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4368. &txrx_ref_handle,
  4369. DP_MOD_ID_TX_COMP);
  4370. }
  4371. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4372. desc = next;
  4373. continue;
  4374. }
  4375. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4376. struct dp_pdev *pdev = desc->pdev;
  4377. if (qdf_likely(txrx_peer))
  4378. dp_tx_update_peer_basic_stats(txrx_peer,
  4379. desc->length,
  4380. desc->tx_status,
  4381. false);
  4382. qdf_assert(pdev);
  4383. dp_tx_outstanding_dec(pdev);
  4384. /*
  4385. * Calling a QDF WRAPPER here is creating signifcant
  4386. * performance impact so avoided the wrapper call here
  4387. */
  4388. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4389. desc->id, DP_TX_COMP_UNMAP);
  4390. dp_tx_nbuf_unmap(soc, desc);
  4391. qdf_nbuf_free(desc->nbuf);
  4392. dp_tx_desc_free(soc, desc, desc->pool_id);
  4393. desc = next;
  4394. continue;
  4395. }
  4396. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4397. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4398. ring_id);
  4399. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4400. dp_tx_desc_release(desc, desc->pool_id);
  4401. desc = next;
  4402. }
  4403. if (txrx_peer)
  4404. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4405. }
  4406. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4407. static inline
  4408. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4409. int max_reap_limit)
  4410. {
  4411. bool limit_hit = false;
  4412. limit_hit =
  4413. (num_reaped >= max_reap_limit) ? true : false;
  4414. if (limit_hit)
  4415. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4416. return limit_hit;
  4417. }
  4418. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4419. {
  4420. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4421. }
  4422. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4423. {
  4424. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4425. return cfg->tx_comp_loop_pkt_limit;
  4426. }
  4427. #else
  4428. static inline
  4429. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4430. int max_reap_limit)
  4431. {
  4432. return false;
  4433. }
  4434. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4435. {
  4436. return false;
  4437. }
  4438. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4439. {
  4440. return 0;
  4441. }
  4442. #endif
  4443. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4444. static inline int
  4445. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4446. int *max_reap_limit)
  4447. {
  4448. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4449. max_reap_limit);
  4450. }
  4451. #else
  4452. static inline int
  4453. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4454. int *max_reap_limit)
  4455. {
  4456. return 0;
  4457. }
  4458. #endif
  4459. #ifdef DP_TX_TRACKING
  4460. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4461. {
  4462. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4463. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4464. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4465. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4466. }
  4467. }
  4468. #endif
  4469. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4470. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4471. uint32_t quota)
  4472. {
  4473. void *tx_comp_hal_desc;
  4474. void *last_prefetched_hw_desc = NULL;
  4475. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4476. hal_soc_handle_t hal_soc;
  4477. uint8_t buffer_src;
  4478. struct dp_tx_desc_s *tx_desc = NULL;
  4479. struct dp_tx_desc_s *head_desc = NULL;
  4480. struct dp_tx_desc_s *tail_desc = NULL;
  4481. uint32_t num_processed = 0;
  4482. uint32_t count;
  4483. uint32_t num_avail_for_reap = 0;
  4484. bool force_break = false;
  4485. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4486. int max_reap_limit, ring_near_full;
  4487. DP_HIST_INIT();
  4488. more_data:
  4489. hal_soc = soc->hal_soc;
  4490. /* Re-initialize local variables to be re-used */
  4491. head_desc = NULL;
  4492. tail_desc = NULL;
  4493. count = 0;
  4494. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4495. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4496. &max_reap_limit);
  4497. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4498. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4499. return 0;
  4500. }
  4501. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  4502. if (num_avail_for_reap >= quota)
  4503. num_avail_for_reap = quota;
  4504. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4505. last_prefetched_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  4506. num_avail_for_reap);
  4507. /* Find head descriptor from completion ring */
  4508. while (qdf_likely(num_avail_for_reap--)) {
  4509. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4510. if (qdf_unlikely(!tx_comp_hal_desc))
  4511. break;
  4512. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4513. tx_comp_hal_desc);
  4514. /* If this buffer was not released by TQM or FW, then it is not
  4515. * Tx completion indication, assert */
  4516. if (qdf_unlikely(buffer_src !=
  4517. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4518. (qdf_unlikely(buffer_src !=
  4519. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4520. uint8_t wbm_internal_error;
  4521. dp_err_rl(
  4522. "Tx comp release_src != TQM | FW but from %d",
  4523. buffer_src);
  4524. hal_dump_comp_desc(tx_comp_hal_desc);
  4525. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4526. /* When WBM sees NULL buffer_addr_info in any of
  4527. * ingress rings it sends an error indication,
  4528. * with wbm_internal_error=1, to a specific ring.
  4529. * The WBM2SW ring used to indicate these errors is
  4530. * fixed in HW, and that ring is being used as Tx
  4531. * completion ring. These errors are not related to
  4532. * Tx completions, and should just be ignored
  4533. */
  4534. wbm_internal_error = hal_get_wbm_internal_error(
  4535. hal_soc,
  4536. tx_comp_hal_desc);
  4537. if (wbm_internal_error) {
  4538. dp_err_rl("Tx comp wbm_internal_error!!");
  4539. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4540. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4541. buffer_src)
  4542. dp_handle_wbm_internal_error(
  4543. soc,
  4544. tx_comp_hal_desc,
  4545. hal_tx_comp_get_buffer_type(
  4546. tx_comp_hal_desc));
  4547. } else {
  4548. dp_err_rl("Tx comp wbm_internal_error false");
  4549. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4550. }
  4551. continue;
  4552. }
  4553. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4554. tx_comp_hal_desc,
  4555. &tx_desc);
  4556. if (!tx_desc) {
  4557. dp_err("unable to retrieve tx_desc!");
  4558. QDF_BUG(0);
  4559. continue;
  4560. }
  4561. tx_desc->buffer_src = buffer_src;
  4562. /*
  4563. * If the release source is FW, process the HTT status
  4564. */
  4565. if (qdf_unlikely(buffer_src ==
  4566. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4567. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4568. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4569. htt_tx_status);
  4570. /* Collect hw completion contents */
  4571. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4572. &tx_desc->comp, 1);
  4573. soc->arch_ops.dp_tx_process_htt_completion(
  4574. soc,
  4575. tx_desc,
  4576. htt_tx_status,
  4577. ring_id);
  4578. } else {
  4579. tx_desc->tx_status =
  4580. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4581. tx_desc->buffer_src = buffer_src;
  4582. /*
  4583. * If the fast completion mode is enabled extended
  4584. * metadata from descriptor is not copied
  4585. */
  4586. if (qdf_likely(tx_desc->flags &
  4587. DP_TX_DESC_FLAG_SIMPLE))
  4588. goto add_to_pool;
  4589. /*
  4590. * If the descriptor is already freed in vdev_detach,
  4591. * continue to next descriptor
  4592. */
  4593. if (qdf_unlikely
  4594. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4595. !tx_desc->flags)) {
  4596. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4597. tx_desc->id);
  4598. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4599. dp_tx_desc_check_corruption(tx_desc);
  4600. continue;
  4601. }
  4602. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4603. dp_tx_comp_info_rl("pdev in down state %d",
  4604. tx_desc->id);
  4605. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4606. dp_tx_comp_free_buf(soc, tx_desc);
  4607. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4608. goto next_desc;
  4609. }
  4610. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4611. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4612. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4613. tx_desc->flags, tx_desc->id);
  4614. qdf_assert_always(0);
  4615. }
  4616. /* Collect hw completion contents */
  4617. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4618. &tx_desc->comp, 1);
  4619. add_to_pool:
  4620. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4621. /* First ring descriptor on the cycle */
  4622. if (!head_desc) {
  4623. head_desc = tx_desc;
  4624. tail_desc = tx_desc;
  4625. }
  4626. tail_desc->next = tx_desc;
  4627. tx_desc->next = NULL;
  4628. tail_desc = tx_desc;
  4629. }
  4630. next_desc:
  4631. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4632. /*
  4633. * Processed packet count is more than given quota
  4634. * stop to processing
  4635. */
  4636. count++;
  4637. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  4638. num_avail_for_reap,
  4639. hal_ring_hdl,
  4640. &last_prefetched_hw_desc,
  4641. &last_prefetched_sw_desc);
  4642. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4643. break;
  4644. }
  4645. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4646. /* Process the reaped descriptors */
  4647. if (head_desc)
  4648. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4649. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  4650. /*
  4651. * If we are processing in near-full condition, there are 3 scenario
  4652. * 1) Ring entries has reached critical state
  4653. * 2) Ring entries are still near high threshold
  4654. * 3) Ring entries are below the safe level
  4655. *
  4656. * One more loop will move te state to normal processing and yield
  4657. */
  4658. if (ring_near_full)
  4659. goto more_data;
  4660. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4661. if (num_processed >= quota)
  4662. force_break = true;
  4663. if (!force_break &&
  4664. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4665. hal_ring_hdl)) {
  4666. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4667. if (!hif_exec_should_yield(soc->hif_handle,
  4668. int_ctx->dp_intr_id))
  4669. goto more_data;
  4670. }
  4671. }
  4672. DP_TX_HIST_STATS_PER_PDEV();
  4673. return num_processed;
  4674. }
  4675. #ifdef FEATURE_WLAN_TDLS
  4676. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4677. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4678. {
  4679. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4680. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4681. DP_MOD_ID_TDLS);
  4682. if (!vdev) {
  4683. dp_err("vdev handle for id %d is NULL", vdev_id);
  4684. return NULL;
  4685. }
  4686. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4687. vdev->is_tdls_frame = true;
  4688. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4689. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4690. }
  4691. #endif
  4692. /**
  4693. * dp_tx_vdev_attach() - attach vdev to dp tx
  4694. * @vdev: virtual device instance
  4695. *
  4696. * Return: QDF_STATUS_SUCCESS: success
  4697. * QDF_STATUS_E_RESOURCES: Error return
  4698. */
  4699. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4700. {
  4701. int pdev_id;
  4702. /*
  4703. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4704. */
  4705. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4706. DP_TCL_METADATA_TYPE_VDEV_BASED);
  4707. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4708. vdev->vdev_id);
  4709. pdev_id =
  4710. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4711. vdev->pdev->pdev_id);
  4712. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4713. /*
  4714. * Set HTT Extension Valid bit to 0 by default
  4715. */
  4716. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4717. dp_tx_vdev_update_search_flags(vdev);
  4718. return QDF_STATUS_SUCCESS;
  4719. }
  4720. #ifndef FEATURE_WDS
  4721. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4722. {
  4723. return false;
  4724. }
  4725. #endif
  4726. /**
  4727. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4728. * @vdev: virtual device instance
  4729. *
  4730. * Return: void
  4731. *
  4732. */
  4733. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4734. {
  4735. struct dp_soc *soc = vdev->pdev->soc;
  4736. /*
  4737. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4738. * for TDLS link
  4739. *
  4740. * Enable AddrY (SA based search) only for non-WDS STA and
  4741. * ProxySTA VAP (in HKv1) modes.
  4742. *
  4743. * In all other VAP modes, only DA based search should be
  4744. * enabled
  4745. */
  4746. if (vdev->opmode == wlan_op_mode_sta &&
  4747. vdev->tdls_link_connected)
  4748. vdev->hal_desc_addr_search_flags =
  4749. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4750. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4751. !dp_tx_da_search_override(vdev))
  4752. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4753. else
  4754. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4755. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  4756. vdev->search_type = soc->sta_mode_search_policy;
  4757. else
  4758. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4759. }
  4760. static inline bool
  4761. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4762. struct dp_vdev *vdev,
  4763. struct dp_tx_desc_s *tx_desc)
  4764. {
  4765. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4766. return false;
  4767. /*
  4768. * if vdev is given, then only check whether desc
  4769. * vdev match. if vdev is NULL, then check whether
  4770. * desc pdev match.
  4771. */
  4772. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4773. (tx_desc->pdev == pdev);
  4774. }
  4775. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4776. /**
  4777. * dp_tx_desc_flush() - release resources associated
  4778. * to TX Desc
  4779. *
  4780. * @dp_pdev: Handle to DP pdev structure
  4781. * @vdev: virtual device instance
  4782. * NULL: no specific Vdev is required and check all allcated TX desc
  4783. * on this pdev.
  4784. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4785. *
  4786. * @force_free:
  4787. * true: flush the TX desc.
  4788. * false: only reset the Vdev in each allocated TX desc
  4789. * that associated to current Vdev.
  4790. *
  4791. * This function will go through the TX desc pool to flush
  4792. * the outstanding TX data or reset Vdev to NULL in associated TX
  4793. * Desc.
  4794. */
  4795. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4796. bool force_free)
  4797. {
  4798. uint8_t i;
  4799. uint32_t j;
  4800. uint32_t num_desc, page_id, offset;
  4801. uint16_t num_desc_per_page;
  4802. struct dp_soc *soc = pdev->soc;
  4803. struct dp_tx_desc_s *tx_desc = NULL;
  4804. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4805. if (!vdev && !force_free) {
  4806. dp_err("Reset TX desc vdev, Vdev param is required!");
  4807. return;
  4808. }
  4809. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4810. tx_desc_pool = &soc->tx_desc[i];
  4811. if (!(tx_desc_pool->pool_size) ||
  4812. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4813. !(tx_desc_pool->desc_pages.cacheable_pages))
  4814. continue;
  4815. /*
  4816. * Add flow pool lock protection in case pool is freed
  4817. * due to all tx_desc is recycled when handle TX completion.
  4818. * this is not necessary when do force flush as:
  4819. * a. double lock will happen if dp_tx_desc_release is
  4820. * also trying to acquire it.
  4821. * b. dp interrupt has been disabled before do force TX desc
  4822. * flush in dp_pdev_deinit().
  4823. */
  4824. if (!force_free)
  4825. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4826. num_desc = tx_desc_pool->pool_size;
  4827. num_desc_per_page =
  4828. tx_desc_pool->desc_pages.num_element_per_page;
  4829. for (j = 0; j < num_desc; j++) {
  4830. page_id = j / num_desc_per_page;
  4831. offset = j % num_desc_per_page;
  4832. if (qdf_unlikely(!(tx_desc_pool->
  4833. desc_pages.cacheable_pages)))
  4834. break;
  4835. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4836. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4837. /*
  4838. * Free TX desc if force free is
  4839. * required, otherwise only reset vdev
  4840. * in this TX desc.
  4841. */
  4842. if (force_free) {
  4843. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4844. dp_tx_comp_free_buf(soc, tx_desc);
  4845. dp_tx_desc_release(tx_desc, i);
  4846. } else {
  4847. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4848. }
  4849. }
  4850. }
  4851. if (!force_free)
  4852. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4853. }
  4854. }
  4855. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4856. /**
  4857. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4858. *
  4859. * @soc: Handle to DP soc structure
  4860. * @tx_desc: pointer of one TX desc
  4861. * @desc_pool_id: TX Desc pool id
  4862. */
  4863. static inline void
  4864. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4865. uint8_t desc_pool_id)
  4866. {
  4867. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4868. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4869. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4870. }
  4871. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4872. bool force_free)
  4873. {
  4874. uint8_t i, num_pool;
  4875. uint32_t j;
  4876. uint32_t num_desc, page_id, offset;
  4877. uint16_t num_desc_per_page;
  4878. struct dp_soc *soc = pdev->soc;
  4879. struct dp_tx_desc_s *tx_desc = NULL;
  4880. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4881. if (!vdev && !force_free) {
  4882. dp_err("Reset TX desc vdev, Vdev param is required!");
  4883. return;
  4884. }
  4885. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4886. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4887. for (i = 0; i < num_pool; i++) {
  4888. tx_desc_pool = &soc->tx_desc[i];
  4889. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4890. continue;
  4891. num_desc_per_page =
  4892. tx_desc_pool->desc_pages.num_element_per_page;
  4893. for (j = 0; j < num_desc; j++) {
  4894. page_id = j / num_desc_per_page;
  4895. offset = j % num_desc_per_page;
  4896. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4897. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4898. if (force_free) {
  4899. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4900. dp_tx_comp_free_buf(soc, tx_desc);
  4901. dp_tx_desc_release(tx_desc, i);
  4902. } else {
  4903. dp_tx_desc_reset_vdev(soc, tx_desc,
  4904. i);
  4905. }
  4906. }
  4907. }
  4908. }
  4909. }
  4910. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4911. /**
  4912. * dp_tx_vdev_detach() - detach vdev from dp tx
  4913. * @vdev: virtual device instance
  4914. *
  4915. * Return: QDF_STATUS_SUCCESS: success
  4916. * QDF_STATUS_E_RESOURCES: Error return
  4917. */
  4918. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4919. {
  4920. struct dp_pdev *pdev = vdev->pdev;
  4921. /* Reset TX desc associated to this Vdev as NULL */
  4922. dp_tx_desc_flush(pdev, vdev, false);
  4923. return QDF_STATUS_SUCCESS;
  4924. }
  4925. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4926. /* Pools will be allocated dynamically */
  4927. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4928. int num_desc)
  4929. {
  4930. uint8_t i;
  4931. for (i = 0; i < num_pool; i++) {
  4932. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4933. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4934. }
  4935. return QDF_STATUS_SUCCESS;
  4936. }
  4937. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4938. uint32_t num_desc)
  4939. {
  4940. return QDF_STATUS_SUCCESS;
  4941. }
  4942. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4943. {
  4944. }
  4945. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4946. {
  4947. uint8_t i;
  4948. for (i = 0; i < num_pool; i++)
  4949. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4950. }
  4951. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4952. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4953. uint32_t num_desc)
  4954. {
  4955. uint8_t i, count;
  4956. /* Allocate software Tx descriptor pools */
  4957. for (i = 0; i < num_pool; i++) {
  4958. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4959. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4960. FL("Tx Desc Pool alloc %d failed %pK"),
  4961. i, soc);
  4962. goto fail;
  4963. }
  4964. }
  4965. return QDF_STATUS_SUCCESS;
  4966. fail:
  4967. for (count = 0; count < i; count++)
  4968. dp_tx_desc_pool_free(soc, count);
  4969. return QDF_STATUS_E_NOMEM;
  4970. }
  4971. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4972. uint32_t num_desc)
  4973. {
  4974. uint8_t i;
  4975. for (i = 0; i < num_pool; i++) {
  4976. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4977. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4978. FL("Tx Desc Pool init %d failed %pK"),
  4979. i, soc);
  4980. return QDF_STATUS_E_NOMEM;
  4981. }
  4982. }
  4983. return QDF_STATUS_SUCCESS;
  4984. }
  4985. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4986. {
  4987. uint8_t i;
  4988. for (i = 0; i < num_pool; i++)
  4989. dp_tx_desc_pool_deinit(soc, i);
  4990. }
  4991. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4992. {
  4993. uint8_t i;
  4994. for (i = 0; i < num_pool; i++)
  4995. dp_tx_desc_pool_free(soc, i);
  4996. }
  4997. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4998. /**
  4999. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5000. * @soc: core txrx main context
  5001. * @num_pool: number of pools
  5002. *
  5003. */
  5004. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5005. {
  5006. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5007. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5008. }
  5009. /**
  5010. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5011. * @soc: core txrx main context
  5012. * @num_pool: number of pools
  5013. *
  5014. */
  5015. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5016. {
  5017. dp_tx_tso_desc_pool_free(soc, num_pool);
  5018. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5019. }
  5020. /**
  5021. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5022. * @soc: core txrx main context
  5023. *
  5024. * This function frees all tx related descriptors as below
  5025. * 1. Regular TX descriptors (static pools)
  5026. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5027. * 3. TSO descriptors
  5028. *
  5029. */
  5030. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5031. {
  5032. uint8_t num_pool;
  5033. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5034. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5035. dp_tx_ext_desc_pool_free(soc, num_pool);
  5036. dp_tx_delete_static_pools(soc, num_pool);
  5037. }
  5038. /**
  5039. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5040. * @soc: core txrx main context
  5041. *
  5042. * This function de-initializes all tx related descriptors as below
  5043. * 1. Regular TX descriptors (static pools)
  5044. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5045. * 3. TSO descriptors
  5046. *
  5047. */
  5048. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5049. {
  5050. uint8_t num_pool;
  5051. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5052. dp_tx_flow_control_deinit(soc);
  5053. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5054. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5055. dp_tx_deinit_static_pools(soc, num_pool);
  5056. }
  5057. /**
  5058. * dp_tso_attach() - TSO attach handler
  5059. * @txrx_soc: Opaque Dp handle
  5060. *
  5061. * Reserve TSO descriptor buffers
  5062. *
  5063. * Return: QDF_STATUS_E_FAILURE on failure or
  5064. * QDF_STATUS_SUCCESS on success
  5065. */
  5066. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5067. uint8_t num_pool,
  5068. uint32_t num_desc)
  5069. {
  5070. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5071. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5072. return QDF_STATUS_E_FAILURE;
  5073. }
  5074. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5075. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5076. num_pool, soc);
  5077. return QDF_STATUS_E_FAILURE;
  5078. }
  5079. return QDF_STATUS_SUCCESS;
  5080. }
  5081. /**
  5082. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5083. * @soc: DP soc handle
  5084. * @num_pool: Number of pools
  5085. * @num_desc: Number of descriptors
  5086. *
  5087. * Initialize TSO descriptor pools
  5088. *
  5089. * Return: QDF_STATUS_E_FAILURE on failure or
  5090. * QDF_STATUS_SUCCESS on success
  5091. */
  5092. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5093. uint8_t num_pool,
  5094. uint32_t num_desc)
  5095. {
  5096. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5097. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5098. return QDF_STATUS_E_FAILURE;
  5099. }
  5100. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5101. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5102. num_pool, soc);
  5103. return QDF_STATUS_E_FAILURE;
  5104. }
  5105. return QDF_STATUS_SUCCESS;
  5106. }
  5107. /**
  5108. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5109. * @soc: core txrx main context
  5110. *
  5111. * This function allocates memory for following descriptor pools
  5112. * 1. regular sw tx descriptor pools (static pools)
  5113. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5114. * 3. TSO descriptor pools
  5115. *
  5116. * Return: QDF_STATUS_SUCCESS: success
  5117. * QDF_STATUS_E_RESOURCES: Error return
  5118. */
  5119. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5120. {
  5121. uint8_t num_pool;
  5122. uint32_t num_desc;
  5123. uint32_t num_ext_desc;
  5124. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5125. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5126. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5127. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5128. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5129. __func__, num_pool, num_desc);
  5130. if ((num_pool > MAX_TXDESC_POOLS) ||
  5131. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5132. goto fail1;
  5133. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5134. goto fail1;
  5135. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5136. goto fail2;
  5137. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5138. return QDF_STATUS_SUCCESS;
  5139. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5140. goto fail3;
  5141. return QDF_STATUS_SUCCESS;
  5142. fail3:
  5143. dp_tx_ext_desc_pool_free(soc, num_pool);
  5144. fail2:
  5145. dp_tx_delete_static_pools(soc, num_pool);
  5146. fail1:
  5147. return QDF_STATUS_E_RESOURCES;
  5148. }
  5149. /**
  5150. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5151. * @soc: core txrx main context
  5152. *
  5153. * This function initializes the following TX descriptor pools
  5154. * 1. regular sw tx descriptor pools (static pools)
  5155. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5156. * 3. TSO descriptor pools
  5157. *
  5158. * Return: QDF_STATUS_SUCCESS: success
  5159. * QDF_STATUS_E_RESOURCES: Error return
  5160. */
  5161. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5162. {
  5163. uint8_t num_pool;
  5164. uint32_t num_desc;
  5165. uint32_t num_ext_desc;
  5166. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5167. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5168. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5169. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5170. goto fail1;
  5171. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5172. goto fail2;
  5173. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5174. return QDF_STATUS_SUCCESS;
  5175. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5176. goto fail3;
  5177. dp_tx_flow_control_init(soc);
  5178. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5179. return QDF_STATUS_SUCCESS;
  5180. fail3:
  5181. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5182. fail2:
  5183. dp_tx_deinit_static_pools(soc, num_pool);
  5184. fail1:
  5185. return QDF_STATUS_E_RESOURCES;
  5186. }
  5187. /**
  5188. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5189. * @txrx_soc: dp soc handle
  5190. *
  5191. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5192. * QDF_STATUS_E_FAILURE
  5193. */
  5194. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5195. {
  5196. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5197. uint8_t num_pool;
  5198. uint32_t num_desc;
  5199. uint32_t num_ext_desc;
  5200. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5201. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5202. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5203. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5204. return QDF_STATUS_E_FAILURE;
  5205. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5206. return QDF_STATUS_E_FAILURE;
  5207. return QDF_STATUS_SUCCESS;
  5208. }
  5209. /**
  5210. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5211. * @txrx_soc: dp soc handle
  5212. *
  5213. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5214. */
  5215. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5216. {
  5217. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5218. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5219. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5220. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5221. return QDF_STATUS_SUCCESS;
  5222. }