wcd9378.c 130 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/msm-cdc-pinctrl.h>
  19. #include <asoc/msm-cdc-supply.h>
  20. #include <bindings/audio-codec-port-types.h>
  21. #include <linux/qti-regmap-debugfs.h>
  22. #include "wcd9378-reg-masks.h"
  23. #include "wcd9378.h"
  24. #include "internal.h"
  25. #include "asoc/bolero-slave-internal.h"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD9378_MOBILE_MODE 0x01
  28. #define WCD9378_VERSION_1_0 1
  29. #define WCD9378_VERSION_ENTRY_SIZE 32
  30. #define SWR_BASECLK_19P2MHZ (0x01)
  31. #define SWR_BASECLK_24P576MHZ (0x03)
  32. #define SWR_BASECLK_22P5792MHZ (0x04)
  33. #define SWR_CLKSCALE_DIV2 (0x02)
  34. #define ADC_MODE_VAL_HIFI 0x01
  35. #define ADC_MODE_VAL_NORMAL 0x03
  36. #define ADC_MODE_VAL_LP 0x05
  37. #define PWR_LEVEL_LOHIFI_VAL 0x00
  38. #define PWR_LEVEL_LP_VAL 0x01
  39. #define PWR_LEVEL_HIFI_VAL 0x02
  40. #define PWR_LEVEL_ULP_VAL 0x03
  41. #define WCD9378_MBQ_ENABLE_MASK 0x2000
  42. #define MICB_USAGE_VAL_DISABLE 0x00
  43. #define MICB_USAGE_VAL_PULL_DOWN 0x01
  44. #define MICB_USAGE_VAL_1P2V 0x02
  45. #define MICB_USAGE_VAL_1P8VORPULLUP 0x03
  46. #define MICB_USAGE_VAL_2P5V 0x04
  47. #define MICB_USAGE_VAL_2P75V 0x05
  48. #define MICB_USAGE_VAL_2P2V 0xF0
  49. #define MICB_USAGE_VAL_2P7V 0xF1
  50. #define MICB_USAGE_VAL_2P8V 0xF2
  51. #define MICB_USAGE_VAL_MICB1_TABLE_VAL 0xF3
  52. #define MICB_USAGE_VAL_MICB2_TABLE_VAL 0xF4
  53. #define MICB_USAGE_VAL_MICB3_TABLE_VAL 0xF5
  54. #define MICB_NUM_MAX 3
  55. #define NUM_ATTEMPTS 20
  56. #define WCD9378_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  57. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  58. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  59. SNDRV_PCM_RATE_384000)
  60. /* Fractional Rates */
  61. #define WCD9378_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  62. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  63. #define WCD9378_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  64. SNDRV_PCM_FMTBIT_S24_LE |\
  65. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  66. #define WCD9378_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  67. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  68. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  69. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  70. .tlv.p = (tlv_array), \
  71. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  72. .put = wcd9378_ear_pa_put_gain, \
  73. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  74. #define WCD9378_AUX_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  75. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  76. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  77. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  78. .tlv.p = (tlv_array), \
  79. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  80. .put = wcd9378_aux_pa_put_gain, \
  81. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  82. enum {
  83. CODEC_TX = 0,
  84. CODEC_RX,
  85. };
  86. enum {
  87. RX2_HP_MODE,
  88. RX2_NORMAL_MODE,
  89. };
  90. enum {
  91. CLASS_AB_EN = 0,
  92. TX1_FOR_JACK,
  93. TX2_AMIC4_EN,
  94. TX2_AMIC1_EN,
  95. TX1_AMIC3_EN,
  96. TX1_AMIC2_EN,
  97. TX0_AMIC2_EN,
  98. TX0_AMIC1_EN,
  99. RX2_EAR_EN,
  100. RX2_AUX_EN,
  101. RX1_AUX_EN,
  102. RX0_EAR_EN,
  103. RX0_RX1_HPH_EN,
  104. };
  105. enum {
  106. WCD_ADC1 = 0,
  107. WCD_ADC2,
  108. WCD_ADC3,
  109. WCD_ADC4,
  110. ALLOW_BUCK_DISABLE,
  111. HPH_COMP_DELAY,
  112. HPH_PA_DELAY,
  113. AMIC2_BCS_ENABLE,
  114. WCD_SUPPLIES_LPM_MODE,
  115. WCD_ADC1_MODE,
  116. WCD_ADC2_MODE,
  117. WCD_ADC3_MODE,
  118. WCD_ADC4_MODE,
  119. WCD_AUX_EN,
  120. WCD_EAR_EN,
  121. };
  122. enum {
  123. SYS_USAGE_0,
  124. SYS_USAGE_1,
  125. SYS_USAGE_2,
  126. SYS_USAGE_3,
  127. SYS_USAGE_4,
  128. SYS_USAGE_5,
  129. SYS_USAGE_6,
  130. SYS_USAGE_7,
  131. SYS_USAGE_8,
  132. SYS_USAGE_9,
  133. SYS_USAGE_10,
  134. SYS_USAGE_11,
  135. SYS_USAGE_12,
  136. SYS_USAGE_NUM,
  137. };
  138. enum {
  139. NO_MICB_USED,
  140. MICB1,
  141. MICB2,
  142. MICB3,
  143. MICB_NUM,
  144. };
  145. enum {
  146. ADC_MODE_INVALID = 0,
  147. ADC_MODE_HIFI,
  148. ADC_MODE_NORMAL,
  149. ADC_MODE_LP,
  150. };
  151. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
  152. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(aux_pa_gain, 600, -600);
  153. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
  154. static int wcd9378_reset(struct device *dev);
  155. static int wcd9378_reset_low(struct device *dev);
  156. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable);
  157. static void wcd9378_class_load(struct snd_soc_component *component);
  158. /* sys_usage:
  159. * rx0_rx1_hph_en,
  160. * rx0_ear_en, rx1_aux_en, rx2_aux_en, rx2_ear_en,
  161. * tx0_amic1_en, tx0_amic2_en, tx1_amic2_en, tx1_amic3_en,
  162. * tx2_amic1_en, tx2_amic4_en, tx1_for_jack, class_ab_en;
  163. */
  164. static const int sys_usage[SYS_USAGE_NUM] = {
  165. [SYS_USAGE_0] = 0x0c95, /*0b0 1100 1001 0101*/
  166. [SYS_USAGE_1] = 0x12a7, /*0b1 0010 1010 0111*/
  167. [SYS_USAGE_2] = 0x0c99, /*0b0 1100 1001 1001*/
  168. [SYS_USAGE_3] = 0x1aab, /*0b1 1010 1010 1011*/
  169. [SYS_USAGE_4] = 0x0894, /*0b0 1000 1001 0100*/
  170. [SYS_USAGE_5] = 0x11a6, /*0b1 0001 1010 0110*/
  171. [SYS_USAGE_6] = 0x0898, /*0b0 1000 1001 1000*/
  172. [SYS_USAGE_7] = 0x11ab, /*0b1 0001 1010 1011*/
  173. [SYS_USAGE_8] = 0x126a, /*0b1 0010 0110 1010*/
  174. [SYS_USAGE_9] = 0x116b, /*0b1 0001 0110 1011*/
  175. [SYS_USAGE_10] = 0x1ca7, /*0b1 1100 1010 0111*/
  176. [SYS_USAGE_11] = 0x1195, /*0b1 0001 1001 0101*/
  177. [SYS_USAGE_12] = 0x1296, /*0b1 0010 1001 0101*/
  178. };
  179. static const struct regmap_irq wcd9378_regmap_irqs[WCD9378_NUM_IRQS] = {
  180. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  181. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  182. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  183. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  184. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_SW_DET, 0, 0x10),
  185. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_OCP_INT, 0, 0x20),
  186. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_CNP_INT, 0, 0x40),
  187. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_OCP_INT, 0, 0x80),
  188. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_CNP_INT, 1, 0x01),
  189. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_CNP_INT, 1, 0x02),
  190. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_SCD_INT, 1, 0x04),
  191. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_CNP_INT, 1, 0x08),
  192. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_SCD_INT, 1, 0x10),
  193. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  194. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  195. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  196. REGMAP_IRQ_REG(WCD9378_IRQ_LDORT_SCD_INT, 2, 0x01),
  197. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  198. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  199. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  200. REGMAP_IRQ_REG(WCD9378_IRQ_SAPU_PROT_MODE_CHG, 2, 0x40),
  201. };
  202. static int wcd9378_handle_post_irq(void *data)
  203. {
  204. struct wcd9378_priv *wcd9378 = data;
  205. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  206. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_1, &sts1);
  207. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_2, &sts2);
  208. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_3, &sts3);
  209. wcd9378->tx_swr_dev->slave_irq_pending =
  210. ((sts1 || sts2 || !sts3) ? true : false);
  211. return IRQ_HANDLED;
  212. }
  213. static struct regmap_irq_chip wcd9378_regmap_irq_chip = {
  214. .name = "wcd9378",
  215. .irqs = wcd9378_regmap_irqs,
  216. .num_irqs = ARRAY_SIZE(wcd9378_regmap_irqs),
  217. .num_regs = 3,
  218. .status_base = SWRS_SCP_SDCA_INTSTAT_1,
  219. .unmask_base = SWRS_SCP_SDCA_INTMASK_1,
  220. .type_base = SWRS_SCP_SDCA_INTRTYPE_1,
  221. .ack_base = SWRS_SCP_SDCA_INTSTAT_1,
  222. .use_ack = 1,
  223. .runtime_pm = false,
  224. .handle_post_irq = wcd9378_handle_post_irq,
  225. .irq_drv_data = NULL,
  226. };
  227. static int wcd9378_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  228. {
  229. int ret = 0;
  230. int bank = 0;
  231. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  232. if (ret)
  233. return -EINVAL;
  234. return ((bank & 0x40) ? 1 : 0);
  235. }
  236. static int wcd9378_init_reg(struct snd_soc_component *component)
  237. {
  238. struct wcd9378_priv *wcd9378 =
  239. snd_soc_component_get_drvdata(component);
  240. u32 val = 0;
  241. val = snd_soc_component_read(component, WCD9378_EFUSE_REG_16);
  242. if (!val)
  243. snd_soc_component_update_bits(component, WCD9378_MBHC_CTL_SPARE_1,
  244. WCD9378_MBHC_CTL_SPARE_1_BIASGEN_RES_CTRL_MASK,
  245. 0x03);
  246. else
  247. snd_soc_component_update_bits(component, WCD9378_MBHC_CTL_SPARE_1,
  248. WCD9378_MBHC_CTL_SPARE_1_BIASGEN_RES_CTRL_MASK,
  249. 0x01);
  250. /*0.9 Volts*/
  251. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  252. WCD9378_SLEEP_CTL_BG_CTL_MASK, 0x0E);
  253. /*BG_EN ENABLE*/
  254. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  255. WCD9378_SLEEP_CTL_BG_EN_MASK, 0x80);
  256. usleep_range(1000, 1010);
  257. /*LDOL_BG_SEL SLEEP_BG*/
  258. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  259. WCD9378_SLEEP_CTL_LDOL_BG_SEL_MASK, 0x40);
  260. usleep_range(1000, 1010);
  261. /*Start up analog master bias. Sequence cannot change*/
  262. /*VBG_FINE_ADJ 0.005 Volts*/
  263. snd_soc_component_update_bits(component, WCD9378_BIAS_VBG_FINE_ADJ,
  264. WCD9378_BIAS_VBG_FINE_ADJ_VBG_FINE_ADJ_MASK, 0xB0);
  265. /*ANALOG_BIAS_EN ENABLE*/
  266. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  267. WCD9378_ANA_BIAS_ANALOG_BIAS_EN_MASK, 0x80);
  268. /*PRECHRG_EN ENABLE*/
  269. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  270. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x40);
  271. usleep_range(10000, 10010);
  272. /*PRECHRG_EN DISABLE*/
  273. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  274. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x00);
  275. /*End Analog Master Bias enable*/
  276. /*ANA_TXSCBIAS_CLK_EN ENABLE*/
  277. snd_soc_component_update_bits(component, WCD9378_CDC_ANA_TX_CLK_CTL,
  278. WCD9378_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN_MASK, 0x01);
  279. /*SEQ_BYPASS ENABLE*/
  280. snd_soc_component_update_bits(component, WCD9378_TX_COM_TXFE_DIV_CTL,
  281. WCD9378_TX_COM_TXFE_DIV_CTL_SEQ_BYPASS_MASK, 0x80);
  282. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  283. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL0,
  284. WCD9378_PDM_WD_CTL0_TIME_OUT_SEL_PCM_MASK, 0x10);
  285. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  286. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL1,
  287. WCD9378_PDM_WD_CTL1_TIME_OUT_SEL_PCM_MASK, 0x10);
  288. /*IBIAS_LDO_DRIVER 5e-06*/
  289. snd_soc_component_update_bits(component, WCD9378_MICB1_TEST_CTL_2,
  290. WCD9378_MICB1_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  291. /*IBIAS_LDO_DRIVER 5e-06*/
  292. snd_soc_component_update_bits(component, WCD9378_MICB2_TEST_CTL_2,
  293. WCD9378_MICB2_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  294. /*IBIAS_LDO_DRIVER 5e-06*/
  295. snd_soc_component_update_bits(component, WCD9378_MICB3_TEST_CTL_2,
  296. WCD9378_MICB3_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  297. /*HD2_RES_DIV_CTL_L 82.77*/
  298. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L,
  299. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L_MASK, 0x04);
  300. /*HD2_RES_DIV_CTL_R 82.77*/
  301. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R,
  302. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R_MASK, 0x04);
  303. /*RDAC_GAINCTL 0.55*/
  304. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL,
  305. WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL_RDAC_GAINCTL_MASK, 0x50);
  306. /*HPH_UP_T0: 0.002*/
  307. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T0,
  308. WCD9378_HPH_UP_T0_HPH_UP_T0_MASK, 0x05);
  309. /*HPH_UP_T9: 0.002*/
  310. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T9,
  311. WCD9378_HPH_UP_T9_HPH_UP_T9_MASK, 0x05);
  312. /*HPH_DN_T0: 0.007*/
  313. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T0,
  314. WCD9378_HPH_DN_T0_HPH_DN_T0_MASK, 0x06);
  315. /*SM0 MB SEL:MB1*/
  316. snd_soc_component_update_bits(component, WCD9378_SM0_MB_SEL,
  317. WCD9378_SM0_MB_SEL_SM0_MB_SEL_MASK, 0x01);
  318. /*SM1 MB SEL:MB2*/
  319. snd_soc_component_update_bits(component, WCD9378_SM1_MB_SEL,
  320. WCD9378_SM1_MB_SEL_SM1_MB_SEL_MASK, 0x02);
  321. /*SM2 MB SEL:MB3*/
  322. snd_soc_component_update_bits(component, WCD9378_SM2_MB_SEL,
  323. WCD9378_SM2_MB_SEL_SM2_MB_SEL_MASK, 0x03);
  324. /*INIT SYS_USAGE*/
  325. snd_soc_component_update_bits(component,
  326. WCD9378_SYS_USAGE_CTRL,
  327. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  328. 0);
  329. wcd9378->sys_usage = 0;
  330. wcd9378_class_load(component);
  331. return 0;
  332. }
  333. static int wcd9378_set_port_params(struct snd_soc_component *component,
  334. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  335. u8 *ch_mask, u32 *ch_rate,
  336. u8 *port_type, u8 path)
  337. {
  338. int i, j;
  339. u8 num_ports = 0;
  340. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  341. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  342. switch (path) {
  343. case CODEC_RX:
  344. map = &wcd9378->rx_port_mapping;
  345. num_ports = wcd9378->num_rx_ports;
  346. break;
  347. case CODEC_TX:
  348. map = &wcd9378->tx_port_mapping;
  349. num_ports = wcd9378->num_tx_ports;
  350. break;
  351. default:
  352. dev_err(component->dev, "%s Invalid path selected %u\n",
  353. __func__, path);
  354. return -EINVAL;
  355. }
  356. for (i = 0; i <= num_ports; i++) {
  357. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  358. if ((*map)[i][j].slave_port_type == slv_prt_type)
  359. goto found;
  360. }
  361. }
  362. found:
  363. if (i > num_ports || j == MAX_CH_PER_PORT) {
  364. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  365. __func__, slv_prt_type);
  366. return -EINVAL;
  367. }
  368. *port_id = i;
  369. *num_ch = (*map)[i][j].num_ch;
  370. *ch_mask = (*map)[i][j].ch_mask;
  371. *ch_rate = (*map)[i][j].ch_rate;
  372. *port_type = (*map)[i][j].master_port_type;
  373. return 0;
  374. }
  375. static int wcd9378_parse_port_params(struct device *dev,
  376. char *prop, u8 path)
  377. {
  378. u32 *dt_array, map_size, max_uc;
  379. int ret = 0;
  380. u32 cnt = 0;
  381. u32 i, j;
  382. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  383. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  384. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  385. switch (path) {
  386. case CODEC_TX:
  387. map = &wcd9378->tx_port_params;
  388. map_uc = &wcd9378->swr_tx_port_params;
  389. break;
  390. default:
  391. ret = -EINVAL;
  392. goto err_port_map;
  393. }
  394. if (!of_find_property(dev->of_node, prop,
  395. &map_size)) {
  396. dev_err(dev, "missing port mapping prop %s\n", prop);
  397. ret = -EINVAL;
  398. goto err_port_map;
  399. }
  400. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  401. if (max_uc != SWR_UC_MAX) {
  402. dev_err(dev, "%s: port params not provided for all usecases\n",
  403. __func__);
  404. ret = -EINVAL;
  405. goto err_port_map;
  406. }
  407. dt_array = kzalloc(map_size, GFP_KERNEL);
  408. if (!dt_array) {
  409. ret = -ENOMEM;
  410. goto err_alloc;
  411. }
  412. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  413. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  414. if (ret) {
  415. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  416. __func__, prop);
  417. goto err_pdata_fail;
  418. }
  419. for (i = 0; i < max_uc; i++) {
  420. for (j = 0; j < SWR_NUM_PORTS; j++) {
  421. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  422. (*map)[i][j].offset1 = dt_array[cnt];
  423. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  424. }
  425. (*map_uc)[i].pp = &(*map)[i][0];
  426. }
  427. kfree(dt_array);
  428. return 0;
  429. err_pdata_fail:
  430. kfree(dt_array);
  431. err_alloc:
  432. err_port_map:
  433. return ret;
  434. }
  435. static int wcd9378_parse_port_mapping(struct device *dev,
  436. char *prop, u8 path)
  437. {
  438. u32 *dt_array, map_size, map_length;
  439. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  440. u32 slave_port_type, master_port_type;
  441. u32 i, ch_iter = 0;
  442. int ret = 0;
  443. u8 *num_ports = NULL;
  444. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  445. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  446. switch (path) {
  447. case CODEC_RX:
  448. map = &wcd9378->rx_port_mapping;
  449. num_ports = &wcd9378->num_rx_ports;
  450. break;
  451. case CODEC_TX:
  452. map = &wcd9378->tx_port_mapping;
  453. num_ports = &wcd9378->num_tx_ports;
  454. break;
  455. default:
  456. dev_err(dev, "%s Invalid path selected %u\n",
  457. __func__, path);
  458. return -EINVAL;
  459. }
  460. if (!of_find_property(dev->of_node, prop,
  461. &map_size)) {
  462. dev_err(dev, "missing port mapping prop %s\n", prop);
  463. ret = -EINVAL;
  464. goto err_port_map;
  465. }
  466. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  467. dt_array = kzalloc(map_size, GFP_KERNEL);
  468. if (!dt_array) {
  469. ret = -ENOMEM;
  470. goto err_alloc;
  471. }
  472. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  473. NUM_SWRS_DT_PARAMS * map_length);
  474. if (ret) {
  475. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  476. __func__, prop);
  477. goto err_pdata_fail;
  478. }
  479. for (i = 0; i < map_length; i++) {
  480. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  481. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  482. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  483. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  484. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  485. if (port_num != old_port_num)
  486. ch_iter = 0;
  487. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  488. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  489. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  490. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  491. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  492. old_port_num = port_num;
  493. }
  494. *num_ports = port_num;
  495. kfree(dt_array);
  496. return 0;
  497. err_pdata_fail:
  498. kfree(dt_array);
  499. err_alloc:
  500. err_port_map:
  501. return ret;
  502. }
  503. static int wcd9378_tx_connect_port(struct snd_soc_component *component,
  504. u8 slv_port_type, int clk_rate,
  505. u8 enable)
  506. {
  507. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  508. u8 port_id, num_ch, ch_mask;
  509. u8 ch_type = 0;
  510. u32 ch_rate;
  511. int slave_ch_idx;
  512. u8 num_port = 1;
  513. int ret = 0;
  514. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  515. &num_ch, &ch_mask, &ch_rate,
  516. &ch_type, CODEC_TX);
  517. if (ret)
  518. return ret;
  519. if (clk_rate)
  520. ch_rate = clk_rate;
  521. slave_ch_idx = wcd9378_slave_get_slave_ch_val(slv_port_type);
  522. if (slave_ch_idx != -EINVAL)
  523. ch_type = wcd9378->tx_master_ch_map[slave_ch_idx];
  524. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  525. __func__, slave_ch_idx, ch_type);
  526. if (enable)
  527. ret = swr_connect_port(wcd9378->tx_swr_dev, &port_id,
  528. num_port, &ch_mask, &ch_rate,
  529. &num_ch, &ch_type);
  530. else
  531. ret = swr_disconnect_port(wcd9378->tx_swr_dev, &port_id,
  532. num_port, &ch_mask, &ch_type);
  533. return ret;
  534. }
  535. static int wcd9378_rx_connect_port(struct snd_soc_component *component,
  536. u8 slv_port_type, u8 enable)
  537. {
  538. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  539. u8 port_id, num_ch, ch_mask, port_type;
  540. u32 ch_rate;
  541. u8 num_port = 1;
  542. int ret = 0;
  543. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  544. &num_ch, &ch_mask, &ch_rate,
  545. &port_type, CODEC_RX);
  546. if (ret)
  547. return ret;
  548. if (enable)
  549. ret = swr_connect_port(wcd9378->rx_swr_dev, &port_id,
  550. num_port, &ch_mask, &ch_rate,
  551. &num_ch, &port_type);
  552. else
  553. ret = swr_disconnect_port(wcd9378->rx_swr_dev, &port_id,
  554. num_port, &ch_mask, &port_type);
  555. return ret;
  556. }
  557. static int wcd9378_enable_clsh(struct snd_soc_dapm_widget *w,
  558. struct snd_kcontrol *kcontrol,
  559. int event)
  560. {
  561. struct snd_soc_component *component =
  562. snd_soc_dapm_to_component(w->dapm);
  563. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  564. int mode = wcd9378->hph_mode;
  565. int ret = 0;
  566. int bank = 0;
  567. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  568. w->name, event);
  569. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  570. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  571. wcd9378_rx_connect_port(component, CLSH,
  572. SND_SOC_DAPM_EVENT_ON(event));
  573. }
  574. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  575. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  576. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  577. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, false);
  578. ret = swr_slvdev_datapath_control(
  579. wcd9378->rx_swr_dev,
  580. wcd9378->rx_swr_dev->dev_num,
  581. false);
  582. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, false);
  583. }
  584. return ret;
  585. }
  586. static int wcd9378_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  587. struct snd_kcontrol *kcontrol,
  588. int event)
  589. {
  590. struct snd_soc_component *component =
  591. snd_soc_dapm_to_component(w->dapm);
  592. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  593. u32 dmic_clk_reg, dmic_clk_en_reg;
  594. s32 *dmic_clk_cnt;
  595. u8 dmic_ctl_shift = 0;
  596. u8 dmic_clk_shift = 0;
  597. u8 dmic_clk_mask = 0;
  598. u32 dmic2_left_en = 0;
  599. int ret = 0;
  600. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  601. w->name, event);
  602. switch (w->shift) {
  603. case 0:
  604. case 1:
  605. dmic_clk_cnt = &(wcd9378->dmic_0_1_clk_cnt);
  606. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  607. dmic_clk_en_reg = WCD9378_CDC_DMIC1_CTL;
  608. dmic_clk_mask = 0x0F;
  609. dmic_clk_shift = 0x00;
  610. dmic_ctl_shift = 0x00;
  611. break;
  612. case 2:
  613. dmic2_left_en = WCD9378_CDC_DMIC2_CTL;
  614. fallthrough;
  615. case 3:
  616. dmic_clk_cnt = &(wcd9378->dmic_2_3_clk_cnt);
  617. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  618. dmic_clk_en_reg = WCD9378_CDC_DMIC2_CTL;
  619. dmic_clk_mask = 0xF0;
  620. dmic_clk_shift = 0x04;
  621. dmic_ctl_shift = 0x01;
  622. break;
  623. case 4:
  624. case 5:
  625. dmic_clk_cnt = &(wcd9378->dmic_4_5_clk_cnt);
  626. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_3_4;
  627. dmic_clk_en_reg = WCD9378_CDC_DMIC3_CTL;
  628. dmic_clk_mask = 0x0F;
  629. dmic_clk_shift = 0x00;
  630. dmic_ctl_shift = 0x02;
  631. break;
  632. default:
  633. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  634. __func__);
  635. return -EINVAL;
  636. };
  637. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  638. __func__, event, (w->shift + 1), *dmic_clk_cnt);
  639. switch (event) {
  640. case SND_SOC_DAPM_PRE_PMU:
  641. snd_soc_component_update_bits(component,
  642. WCD9378_CDC_AMIC_CTL,
  643. (0x01 << dmic_ctl_shift), 0x00);
  644. /* 250us sleep as per HW requirement */
  645. usleep_range(250, 260);
  646. if (dmic2_left_en)
  647. snd_soc_component_update_bits(component,
  648. dmic2_left_en, 0x80, 0x80);
  649. /* Setting DMIC clock rate to 2.4MHz */
  650. snd_soc_component_update_bits(component,
  651. dmic_clk_reg, dmic_clk_mask,
  652. (0x03 << dmic_clk_shift));
  653. snd_soc_component_update_bits(component,
  654. dmic_clk_en_reg, 0x08, 0x08);
  655. /* enable clock scaling */
  656. snd_soc_component_update_bits(component,
  657. WCD9378_CDC_DMIC_CTL, 0x06, 0x06);
  658. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  659. wcd9378->tx_swr_dev->dev_num,
  660. true);
  661. break;
  662. case SND_SOC_DAPM_POST_PMD:
  663. wcd9378_tx_connect_port(component, DMIC0 + (w->shift), 0,
  664. false);
  665. snd_soc_component_update_bits(component,
  666. WCD9378_CDC_AMIC_CTL,
  667. (0x01 << dmic_ctl_shift),
  668. (0x01 << dmic_ctl_shift));
  669. if (dmic2_left_en)
  670. snd_soc_component_update_bits(component,
  671. dmic2_left_en, 0x80, 0x00);
  672. snd_soc_component_update_bits(component,
  673. dmic_clk_en_reg, 0x08, 0x00);
  674. break;
  675. };
  676. return ret;
  677. }
  678. /*
  679. * wcd9378_get_micb_vout_ctl_val: converts micbias from volts to register value
  680. * @micb_mv: micbias in mv
  681. *
  682. * return register value converted
  683. */
  684. int wcd9378_get_micb_vout_ctl_val(u32 micb_mv)
  685. {
  686. /* min micbias voltage is 1V and maximum is 2.85V */
  687. if (micb_mv < 1000 || micb_mv > 2850) {
  688. pr_err("%s: unsupported micbias voltage\n", __func__);
  689. return -EINVAL;
  690. }
  691. return (micb_mv - 1000) / 50;
  692. }
  693. EXPORT_SYMBOL_GPL(wcd9378_get_micb_vout_ctl_val);
  694. /*
  695. * wcd9378_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  696. * @component: handle to snd_soc_component *
  697. * @req_volt: micbias voltage to be set
  698. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  699. *
  700. * return 0 if adjustment is success or error code in case of failure
  701. */
  702. static int wcd9378_micb_table_value_set(struct snd_soc_component *component,
  703. u32 micb_mv, int micb_num)
  704. {
  705. int vcout_ctl;
  706. switch (micb_mv) {
  707. case 2200:
  708. return MICB_USAGE_VAL_2P2V;
  709. case 2700:
  710. return MICB_USAGE_VAL_2P7V;
  711. case 2800:
  712. return MICB_USAGE_VAL_2P8V;
  713. default:
  714. vcout_ctl = wcd9378_get_micb_vout_ctl_val(micb_mv);
  715. if (micb_num == MIC_BIAS_1) {
  716. snd_soc_component_update_bits(component,
  717. WCD9378_MICB_REMAP_TABLE_VAL_3,
  718. WCD9378_MICB_REMAP_TABLE_VAL_3_MICB_REMAP_TABLE_VAL_3_MASK,
  719. vcout_ctl);
  720. return MICB_USAGE_VAL_MICB1_TABLE_VAL;
  721. } else if (micb_num == MIC_BIAS_2) {
  722. snd_soc_component_update_bits(component,
  723. WCD9378_MICB_REMAP_TABLE_VAL_4,
  724. WCD9378_MICB_REMAP_TABLE_VAL_4_MICB_REMAP_TABLE_VAL_4_MASK,
  725. vcout_ctl);
  726. return MICB_USAGE_VAL_MICB2_TABLE_VAL;
  727. } else if (micb_num == MIC_BIAS_3) {
  728. snd_soc_component_update_bits(component,
  729. WCD9378_MICB_REMAP_TABLE_VAL_5,
  730. WCD9378_MICB_REMAP_TABLE_VAL_5_MICB_REMAP_TABLE_VAL_5_MASK,
  731. vcout_ctl);
  732. return MICB_USAGE_VAL_MICB3_TABLE_VAL;
  733. }
  734. }
  735. return 0;
  736. }
  737. static int wcd9378_micb_usage_value_convert(struct snd_soc_component *component,
  738. u32 micb_mv, int micb_num)
  739. {
  740. switch (micb_mv) {
  741. case 0:
  742. return MICB_USAGE_VAL_PULL_DOWN;
  743. case 1200:
  744. return MICB_USAGE_VAL_1P2V;
  745. case 1800:
  746. return MICB_USAGE_VAL_1P8VORPULLUP;
  747. case 2500:
  748. return MICB_USAGE_VAL_2P5V;
  749. case 2750:
  750. return MICB_USAGE_VAL_2P75V;
  751. default:
  752. return wcd9378_micb_table_value_set(component, micb_mv, micb_num);
  753. }
  754. return MICB_USAGE_VAL_DISABLE;
  755. }
  756. int wcd9378_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  757. int req_volt, int micb_num)
  758. {
  759. struct wcd9378_priv *wcd9378 =
  760. snd_soc_component_get_drvdata(component);
  761. int micb_usage = 0, micb_mask = 0, req_vout_ctl = 0;
  762. if (wcd9378 == NULL) {
  763. dev_err(component->dev,
  764. "%s: wcd9378 private data is NULL\n", __func__);
  765. return -EINVAL;
  766. }
  767. switch (micb_num) {
  768. case MIC_BIAS_1:
  769. micb_usage = WCD9378_IT11_USAGE;
  770. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  771. break;
  772. case MIC_BIAS_2:
  773. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  774. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  775. break;
  776. case MIC_BIAS_3:
  777. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  778. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  779. break;
  780. default:
  781. dev_err(component->dev,
  782. "%s: wcd9378 private data is NULL\n", __func__);
  783. break;
  784. }
  785. mutex_lock(&wcd9378->micb_lock);
  786. req_vout_ctl =
  787. wcd9378_micb_usage_value_convert(component, req_volt, micb_num);
  788. snd_soc_component_update_bits(component,
  789. micb_usage, micb_mask, req_vout_ctl);
  790. if (micb_num == MIC_BIAS_2) {
  791. dev_err(component->dev,
  792. "%s: sj micbias set\n", __func__);
  793. snd_soc_component_update_bits(component,
  794. WCD9378_IT31_MICB,
  795. WCD9378_IT31_MICB_IT31_MICB_MASK,
  796. req_vout_ctl);
  797. wcd9378->curr_micbias2 = req_volt;
  798. }
  799. mutex_unlock(&wcd9378->micb_lock);
  800. return 0;
  801. }
  802. EXPORT_SYMBOL_GPL(wcd9378_mbhc_micb_adjust_voltage);
  803. void wcd9378_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  804. bool bcs_disable)
  805. {
  806. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  807. if (wcd9378->update_wcd_event) {
  808. if (bcs_disable)
  809. wcd9378->update_wcd_event(wcd9378->handle,
  810. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  811. else
  812. wcd9378->update_wcd_event(wcd9378->handle,
  813. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  814. }
  815. }
  816. static int wcd9378_get_clk_rate(int mode)
  817. {
  818. int rate;
  819. switch (mode) {
  820. case ADC_MODE_LP:
  821. rate = SWR_CLK_RATE_4P8MHZ;
  822. break;
  823. case ADC_MODE_INVALID:
  824. case ADC_MODE_NORMAL:
  825. case ADC_MODE_HIFI:
  826. default:
  827. rate = SWR_CLK_RATE_9P6MHZ;
  828. break;
  829. }
  830. pr_debug("%s: mode: %d, rate: %d\n", __func__, mode, rate);
  831. return rate;
  832. }
  833. static int wcd9378_get_adc_mode_val(int mode)
  834. {
  835. int ret = 0;
  836. switch (mode) {
  837. case ADC_MODE_INVALID:
  838. case ADC_MODE_NORMAL:
  839. ret = ADC_MODE_VAL_NORMAL;
  840. break;
  841. case ADC_MODE_HIFI:
  842. ret = ADC_MODE_VAL_HIFI;
  843. break;
  844. case ADC_MODE_LP:
  845. ret = ADC_MODE_VAL_LP;
  846. break;
  847. default:
  848. ret = -EINVAL;
  849. pr_err("%s: invalid ADC mode value %d\n", __func__, mode);
  850. break;
  851. }
  852. return ret;
  853. }
  854. static int wcd9378_sys_usage_auto_udpate(struct snd_soc_component *component,
  855. int sys_usage_bit, bool set_enable)
  856. {
  857. struct wcd9378_priv *wcd9378 =
  858. snd_soc_component_get_drvdata(component);
  859. int i = 0;
  860. dev_dbg(component->dev,
  861. "%s: enter, current sys_usage: %d, sys_usage_status: 0x%x, sys_usage_bit: %d, set_enable: %d\n",
  862. __func__, wcd9378->sys_usage,
  863. wcd9378->sys_usage_status,
  864. sys_usage_bit, set_enable);
  865. mutex_lock(&wcd9378->sys_usage_lock);
  866. if (set_enable) {
  867. set_bit(sys_usage_bit, &wcd9378->sys_usage_status);
  868. if ((sys_usage[wcd9378->sys_usage] &
  869. wcd9378->sys_usage_status) == wcd9378->sys_usage_status)
  870. goto exit;
  871. for (i = 0; i < SYS_USAGE_NUM; i++) {
  872. if ((sys_usage[i] & wcd9378->sys_usage_status)
  873. == wcd9378->sys_usage_status) {
  874. snd_soc_component_update_bits(component,
  875. WCD9378_SYS_USAGE_CTRL,
  876. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  877. i);
  878. wcd9378->sys_usage = i;
  879. dev_dbg(component->dev, "%s: update sys_usage: %d\n",
  880. __func__, wcd9378->sys_usage);
  881. goto exit;
  882. }
  883. }
  884. dev_dbg(component->dev, "%s: cannot find sys_usage\n",
  885. __func__);
  886. } else {
  887. clear_bit(sys_usage_bit, &wcd9378->sys_usage_status);
  888. }
  889. exit:
  890. mutex_unlock(&wcd9378->sys_usage_lock);
  891. return 0;
  892. }
  893. static int wcd9378_sys_usage_bit_get(
  894. struct snd_soc_component *component, u32 w_shift,
  895. int *sys_usage_bit, int event)
  896. {
  897. struct wcd9378_priv *wcd9378 =
  898. snd_soc_component_get_drvdata(component);
  899. dev_dbg(component->dev, "%s: wshift: %d event: %d\n", __func__,
  900. w_shift, event);
  901. switch (event) {
  902. case SND_SOC_DAPM_PRE_PMU:
  903. switch (w_shift) {
  904. case ADC1:
  905. if ((snd_soc_component_read(component,
  906. WCD9378_TX_NEW_TX_CH12_MUX) &
  907. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_MASK) == 0x01) {
  908. *sys_usage_bit = TX0_AMIC1_EN;
  909. } else if ((snd_soc_component_read(component,
  910. WCD9378_TX_NEW_TX_CH12_MUX) &
  911. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_MASK) == 0x02) {
  912. *sys_usage_bit = TX0_AMIC2_EN;
  913. } else {
  914. dev_err(component->dev, "%s: unsupport usecase, pls check\n",
  915. __func__);
  916. return -EINVAL;
  917. }
  918. break;
  919. case ADC2:
  920. if ((snd_soc_component_read(component,
  921. WCD9378_TX_NEW_TX_CH12_MUX) &
  922. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10) {
  923. *sys_usage_bit = TX1_AMIC2_EN;
  924. } else if ((snd_soc_component_read(component,
  925. WCD9378_TX_NEW_TX_CH12_MUX) &
  926. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x18) {
  927. *sys_usage_bit = TX1_AMIC3_EN;
  928. } else {
  929. dev_err(component->dev, "%s: unsupport usecase, pls check\n",
  930. __func__);
  931. return -EINVAL;
  932. }
  933. break;
  934. case ADC3:
  935. if ((snd_soc_component_read(component,
  936. WCD9378_TX_NEW_TX_CH34_MUX) &
  937. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT) == 0x01) {
  938. *sys_usage_bit = TX2_AMIC1_EN;
  939. } else if ((snd_soc_component_read(component,
  940. WCD9378_TX_NEW_TX_CH34_MUX) &
  941. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT) == 0x03) {
  942. *sys_usage_bit = TX2_AMIC4_EN;
  943. } else {
  944. dev_err(component->dev, "%s: unsupport usecase, pls check\n",
  945. __func__);
  946. return -EINVAL;
  947. }
  948. break;
  949. default:
  950. break;
  951. }
  952. break;
  953. case SND_SOC_DAPM_POST_PMD:
  954. switch (w_shift) {
  955. case ADC1:
  956. if (test_bit(TX0_AMIC1_EN, &wcd9378->sys_usage_status))
  957. *sys_usage_bit = TX0_AMIC1_EN;
  958. if (test_bit(TX0_AMIC2_EN, &wcd9378->sys_usage_status))
  959. *sys_usage_bit = TX0_AMIC2_EN;
  960. break;
  961. case ADC2:
  962. if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
  963. *sys_usage_bit = TX1_AMIC2_EN;
  964. if (test_bit(TX1_AMIC3_EN, &wcd9378->sys_usage_status))
  965. *sys_usage_bit = TX1_AMIC3_EN;
  966. break;
  967. case ADC3:
  968. if (test_bit(TX2_AMIC1_EN, &wcd9378->sys_usage_status))
  969. *sys_usage_bit = TX2_AMIC1_EN;
  970. if (test_bit(TX2_AMIC4_EN, &wcd9378->sys_usage_status))
  971. *sys_usage_bit = TX2_AMIC4_EN;
  972. break;
  973. default:
  974. break;
  975. }
  976. break;
  977. default:
  978. break;
  979. }
  980. dev_dbg(component->dev, "%s: done, event: %d, sys_usage_bit: %d\n",
  981. __func__, event, *sys_usage_bit);
  982. return 0;
  983. }
  984. static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
  985. struct snd_kcontrol *kcontrol, int event)
  986. {
  987. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  988. struct wcd9378_priv *wcd9378 =
  989. snd_soc_component_get_drvdata(component);
  990. int mode_val = 0, bank = 0, ret = 0, rate = 0;
  991. int act_ps = 0, sys_usage_bit = 0;
  992. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->tx_swr_dev,
  993. wcd9378->tx_swr_dev->dev_num) ? 0 : 1);
  994. dev_dbg(component->dev, "%s wname: %s wshift: %d event: %d\n", __func__,
  995. w->name, w->shift, event);
  996. ret = wcd9378_sys_usage_bit_get(component, w->shift, &sys_usage_bit, event);
  997. if (ret < 0)
  998. return ret;
  999. switch (event) {
  1000. case SND_SOC_DAPM_PRE_PMU:
  1001. /*Update sys_usage*/
  1002. wcd9378_sys_usage_auto_udpate(component, sys_usage_bit, true);
  1003. mode_val = wcd9378_get_adc_mode_val(wcd9378->tx_mode[w->shift - ADC1]);
  1004. if (mode_val < 0) {
  1005. dev_dbg(component->dev,
  1006. "%s: invalid mode, setting to normal mode\n",
  1007. __func__);
  1008. mode_val = ADC_MODE_VAL_NORMAL;
  1009. }
  1010. rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
  1011. if (w->shift == ADC2 && !((snd_soc_component_read(component,
  1012. WCD9378_TX_NEW_TX_CH12_MUX) &
  1013. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10)) {
  1014. if (!wcd9378->bcs_dis) {
  1015. wcd9378_tx_connect_port(component, MBHC,
  1016. SWR_CLK_RATE_4P8MHZ, true);
  1017. set_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  1018. }
  1019. }
  1020. set_bit(w->shift - ADC1, &wcd9378->status_mask);
  1021. wcd9378_tx_connect_port(component, w->shift, rate,
  1022. true);
  1023. switch (w->shift) {
  1024. case ADC1:
  1025. /*SMP MIC0 IT11 USAGE SET*/
  1026. snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
  1027. WCD9378_IT11_USAGE_IT11_USAGE_MASK, mode_val);
  1028. /*Hold TXFE in Initialization During Startup*/
  1029. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1030. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x40);
  1031. /*Power up TX0 sequencer*/
  1032. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1033. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  1034. break;
  1035. case ADC2:
  1036. /*Check if amic2 is connected to ADC2 MUX*/
  1037. if ((snd_soc_component_read(component,
  1038. WCD9378_TX_NEW_TX_CH12_MUX) &
  1039. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10) {
  1040. /*SMP JACK IT31 USAGE SET*/
  1041. snd_soc_component_update_bits(component,
  1042. WCD9378_IT31_USAGE,
  1043. WCD9378_IT31_USAGE_IT31_USAGE_MASK, mode_val);
  1044. /*Power up TX1 sequencer*/
  1045. snd_soc_component_update_bits(component,
  1046. WCD9378_PDE34_REQ_PS,
  1047. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x00);
  1048. } else {
  1049. snd_soc_component_update_bits(component,
  1050. WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
  1051. WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK,
  1052. mode_val);
  1053. /*Hold TXFE in Initialization During Startup*/
  1054. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1055. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x20);
  1056. /*Power up TX1 sequencer*/
  1057. snd_soc_component_update_bits(component,
  1058. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS,
  1059. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS_PDE11_REQ_PS_MASK,
  1060. 0x00);
  1061. }
  1062. break;
  1063. case ADC3:
  1064. /*SMP MIC2 IT11 USAGE SET*/
  1065. snd_soc_component_update_bits(component,
  1066. WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
  1067. WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK,
  1068. mode_val);
  1069. /*Hold TXFE in Initialization During Startup*/
  1070. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1071. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x40);
  1072. /*Power up TX2 sequencer*/
  1073. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS,
  1074. WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  1075. break;
  1076. default:
  1077. break;
  1078. }
  1079. /*default delay 800us*/
  1080. usleep_range(800, 810);
  1081. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, true);
  1082. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1083. wcd9378->tx_swr_dev->dev_num,
  1084. true);
  1085. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, true);
  1086. switch (w->shift) {
  1087. case ADC1:
  1088. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1089. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1090. act_ps = snd_soc_component_read(component, WCD9378_PDE11_ACT_PS);
  1091. if (act_ps)
  1092. dev_dbg(component->dev, "%s: tx0 sequencer didnot power on, act_ps: 0x%0x\n",
  1093. __func__, act_ps);
  1094. else
  1095. dev_dbg(component->dev, "%s: tx0 sequencer power on successful, act_ps: 0x%0x\n",
  1096. __func__, act_ps);
  1097. break;
  1098. case ADC2:
  1099. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1100. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x00);
  1101. if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
  1102. act_ps = snd_soc_component_read(component,
  1103. WCD9378_PDE34_ACT_PS);
  1104. else
  1105. act_ps = snd_soc_component_read(component,
  1106. WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS);
  1107. if (act_ps)
  1108. dev_dbg(component->dev, "%s: tx1 sequencer didnot power on, act_ps: 0x%0x\n",
  1109. __func__, act_ps);
  1110. else
  1111. dev_dbg(component->dev, "%s: tx1 sequencer power on successful, act_ps: 0x%0x\n",
  1112. __func__, act_ps);
  1113. break;
  1114. case ADC3:
  1115. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1116. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  1117. act_ps = snd_soc_component_read(component,
  1118. WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS);
  1119. if (act_ps)
  1120. dev_dbg(component->dev, "%s: tx2 sequencer didnot power on, act_ps: 0x%0x\n",
  1121. __func__, act_ps);
  1122. else
  1123. dev_dbg(component->dev, "%s: tx2 sequencer power on successful, act_ps: 0x%0x\n",
  1124. __func__, act_ps);
  1125. break;
  1126. };
  1127. break;
  1128. case SND_SOC_DAPM_POST_PMD:
  1129. wcd9378_tx_connect_port(component, w->shift, 0, false);
  1130. if (w->shift == ADC2 &&
  1131. test_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask)) {
  1132. wcd9378_tx_connect_port(component, MBHC, 0,
  1133. false);
  1134. clear_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  1135. }
  1136. switch (w->shift) {
  1137. case ADC1:
  1138. /*Normal TXFE Startup*/
  1139. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1140. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1141. /*tear down TX0 sequencer*/
  1142. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1143. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1144. break;
  1145. case ADC2:
  1146. if (test_bit(TX1_AMIC2_EN, &wcd9378->sys_usage_status))
  1147. /*tear down TX1 sequencer*/
  1148. snd_soc_component_update_bits(component, WCD9378_PDE34_REQ_PS,
  1149. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x03);
  1150. if (test_bit(TX1_AMIC3_EN, &wcd9378->sys_usage_status)) {
  1151. /*Normal TXFE Startup*/
  1152. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1153. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1154. /*tear down TX1 sequencer*/
  1155. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1156. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1157. }
  1158. break;
  1159. case ADC3:
  1160. /*Normal TXFE Startup*/
  1161. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1162. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  1163. /*tear down TX2 sequencer*/
  1164. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1165. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1166. break;
  1167. default:
  1168. break;
  1169. }
  1170. /*default delay 800us*/
  1171. usleep_range(800, 810);
  1172. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, false);
  1173. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1174. wcd9378->tx_swr_dev->dev_num,
  1175. false);
  1176. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, false);
  1177. /*Disable sys_usage_status*/
  1178. wcd9378_sys_usage_auto_udpate(component, sys_usage_bit, false);
  1179. break;
  1180. default:
  1181. break;
  1182. }
  1183. return ret;
  1184. }
  1185. static int wcd9378_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1186. struct snd_kcontrol *kcontrol,
  1187. int event)
  1188. {
  1189. struct snd_soc_component *component =
  1190. snd_soc_dapm_to_component(w->dapm);
  1191. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1192. int ret = 0;
  1193. switch (event) {
  1194. case SND_SOC_DAPM_PRE_PMU:
  1195. wcd9378_tx_connect_port(component, w->shift,
  1196. SWR_CLK_RATE_2P4MHZ, true);
  1197. break;
  1198. case SND_SOC_DAPM_POST_PMD:
  1199. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1200. wcd9378->tx_swr_dev->dev_num,
  1201. false);
  1202. break;
  1203. };
  1204. return ret;
  1205. }
  1206. static int wcd9378_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1207. struct snd_kcontrol *kcontrol,
  1208. int event)
  1209. {
  1210. struct snd_soc_component *component =
  1211. snd_soc_dapm_to_component(w->dapm);
  1212. int micb_num = 0;
  1213. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1214. __func__, w->name, event);
  1215. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1216. micb_num = MIC_BIAS_1;
  1217. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1218. micb_num = MIC_BIAS_2;
  1219. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1220. micb_num = MIC_BIAS_3;
  1221. else
  1222. return -EINVAL;
  1223. switch (event) {
  1224. case SND_SOC_DAPM_PRE_PMU:
  1225. wcd9378_micbias_control(component, micb_num,
  1226. MICB_ENABLE, true);
  1227. break;
  1228. case SND_SOC_DAPM_POST_PMU:
  1229. usleep_range(1000, 1100);
  1230. break;
  1231. case SND_SOC_DAPM_POST_PMD:
  1232. wcd9378_micbias_control(component, micb_num,
  1233. MICB_DISABLE, true);
  1234. break;
  1235. };
  1236. return 0;
  1237. }
  1238. static int wcd9378_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1239. struct snd_kcontrol *kcontrol,
  1240. int event)
  1241. {
  1242. struct snd_soc_component *component =
  1243. snd_soc_dapm_to_component(w->dapm);
  1244. int micb_num = 0;
  1245. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1246. __func__, w->name, event);
  1247. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1248. micb_num = MIC_BIAS_1;
  1249. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1250. micb_num = MIC_BIAS_2;
  1251. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1252. micb_num = MIC_BIAS_3;
  1253. else
  1254. return -EINVAL;
  1255. switch (event) {
  1256. case SND_SOC_DAPM_PRE_PMU:
  1257. wcd9378_micbias_control(component, micb_num,
  1258. MICB_PULLUP_ENABLE, true);
  1259. break;
  1260. case SND_SOC_DAPM_POST_PMU:
  1261. usleep_range(1000, 1100);
  1262. break;
  1263. case SND_SOC_DAPM_POST_PMD:
  1264. wcd9378_micbias_control(component, micb_num,
  1265. MICB_PULLUP_DISABLE, true);
  1266. break;
  1267. };
  1268. return 0;
  1269. }
  1270. /*
  1271. * wcd9378_soc_get_mbhc: get wcd9378_mbhc handle of corresponding component
  1272. * @component: handle to snd_soc_component *
  1273. *
  1274. * return wcd9378_mbhc handle or error code in case of failure
  1275. */
  1276. struct wcd9378_mbhc *wcd9378_soc_get_mbhc(struct snd_soc_component *component)
  1277. {
  1278. struct wcd9378_priv *wcd9378;
  1279. if (!component) {
  1280. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  1281. return NULL;
  1282. }
  1283. wcd9378 = snd_soc_component_get_drvdata(component);
  1284. if (!wcd9378) {
  1285. pr_err_ratelimited("%s: wcd9378 is NULL\n", __func__);
  1286. return NULL;
  1287. }
  1288. return wcd9378->mbhc;
  1289. }
  1290. EXPORT_SYMBOL_GPL(wcd9378_soc_get_mbhc);
  1291. static int wcd9378_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  1292. struct snd_kcontrol *kcontrol,
  1293. int event)
  1294. {
  1295. struct snd_soc_component *component =
  1296. snd_soc_dapm_to_component(w->dapm);
  1297. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1298. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1299. w->name, event);
  1300. switch (event) {
  1301. case SND_SOC_DAPM_PRE_PMU:
  1302. /*OCP FSM EN*/
  1303. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1304. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x10);
  1305. /*SCD OP EN*/
  1306. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1307. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x02);
  1308. /*HPHL ENABLE*/
  1309. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1310. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
  1311. /*OPAMP_CHOP_CLK DISABLE*/
  1312. snd_soc_component_update_bits(component, WCD9378_HPH_RDAC_CLK_CTL1,
  1313. WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK, 0x00);
  1314. wcd9378_rx_connect_port(component, HPH_L, true);
  1315. if (wcd9378->comp1_enable) {
  1316. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1317. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x02);
  1318. wcd9378_rx_connect_port(component, COMP_L, true);
  1319. }
  1320. if (wcd9378->update_wcd_event)
  1321. wcd9378->update_wcd_event(wcd9378->handle,
  1322. SLV_BOLERO_EVT_RX_MUTE,
  1323. (WCD_RX1 << 0x10));
  1324. break;
  1325. case SND_SOC_DAPM_POST_PMD:
  1326. /*OCP FSM DISABLE*/
  1327. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1328. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x00);
  1329. /*SCD OP DISABLE*/
  1330. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1331. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x00);
  1332. /*HPHL DISABLE*/
  1333. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1334. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1335. wcd9378_rx_connect_port(component, HPH_L, false);
  1336. if (wcd9378->comp1_enable) {
  1337. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1338. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x00);
  1339. wcd9378_rx_connect_port(component, COMP_R, false);
  1340. }
  1341. break;
  1342. default:
  1343. break;
  1344. };
  1345. return 0;
  1346. }
  1347. static int wcd9378_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  1348. struct snd_kcontrol *kcontrol,
  1349. int event)
  1350. {
  1351. struct snd_soc_component *component =
  1352. snd_soc_dapm_to_component(w->dapm);
  1353. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1354. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1355. w->name, event);
  1356. switch (event) {
  1357. case SND_SOC_DAPM_PRE_PMU:
  1358. /*OCP FSM EN*/
  1359. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1360. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x10);
  1361. /*SCD OP EN*/
  1362. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1363. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x02);
  1364. /*HPHR ENABLE*/
  1365. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1366. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
  1367. /*OPAMP_CHOP_CLK DISABLE*/
  1368. snd_soc_component_update_bits(component, WCD9378_HPH_RDAC_CLK_CTL1,
  1369. WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK, 0x00);
  1370. wcd9378_rx_connect_port(component, HPH_R, true);
  1371. if (wcd9378->comp2_enable) {
  1372. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1373. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x01);
  1374. wcd9378_rx_connect_port(component, COMP_R, true);
  1375. }
  1376. break;
  1377. case SND_SOC_DAPM_POST_PMD:
  1378. /*OCP FSM DISABLE*/
  1379. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1380. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x00);
  1381. /*SCD OP DISABLE*/
  1382. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  1383. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x00);
  1384. /*HPHR DISABLE*/
  1385. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1386. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x00);
  1387. wcd9378_rx_connect_port(component, HPH_R, false);
  1388. if (wcd9378->comp2_enable) {
  1389. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1390. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x00);
  1391. wcd9378_rx_connect_port(component, COMP_R, false);
  1392. }
  1393. break;
  1394. default:
  1395. break;
  1396. };
  1397. return 0;
  1398. }
  1399. static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  1400. struct snd_kcontrol *kcontrol,
  1401. int event)
  1402. {
  1403. struct snd_soc_component *component =
  1404. snd_soc_dapm_to_component(w->dapm);
  1405. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1406. int bank = 0;
  1407. int act_ps = 0;
  1408. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1409. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1410. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1411. w->name, event);
  1412. switch (event) {
  1413. case SND_SOC_DAPM_PRE_PMU:
  1414. if (wcd9378->update_wcd_event)
  1415. wcd9378->update_wcd_event(wcd9378->handle,
  1416. SLV_BOLERO_EVT_RX_MUTE,
  1417. (WCD_RX1 << 0x10 | 0x01));
  1418. if (wcd9378->update_wcd_event)
  1419. wcd9378->update_wcd_event(wcd9378->handle,
  1420. SLV_BOLERO_EVT_RX_MUTE,
  1421. (WCD_RX1 << 0x10));
  1422. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1423. if (act_ps)
  1424. dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1425. __func__, act_ps);
  1426. else
  1427. dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1428. __func__, act_ps);
  1429. break;
  1430. case SND_SOC_DAPM_POST_PMD:
  1431. if (wcd9378->update_wcd_event)
  1432. wcd9378->update_wcd_event(wcd9378->handle,
  1433. SLV_BOLERO_EVT_RX_MUTE,
  1434. (WCD_RX1 << 0x10 | 0x1));
  1435. if (wcd9378->update_wcd_event && wcd9378->comp1_enable)
  1436. wcd9378->update_wcd_event(wcd9378->handle,
  1437. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1438. (WCD_RX1 << 0x10));
  1439. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1440. WCD_EVENT_POST_HPHL_PA_OFF,
  1441. &wcd9378->mbhc->wcd_mbhc);
  1442. break;
  1443. default:
  1444. break;
  1445. };
  1446. return 0;
  1447. }
  1448. static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  1449. struct snd_kcontrol *kcontrol,
  1450. int event)
  1451. {
  1452. struct snd_soc_component *component =
  1453. snd_soc_dapm_to_component(w->dapm);
  1454. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1455. int act_ps = 0;
  1456. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1457. w->name, event);
  1458. switch (event) {
  1459. case SND_SOC_DAPM_PRE_PMU:
  1460. if (wcd9378->update_wcd_event)
  1461. wcd9378->update_wcd_event(wcd9378->handle,
  1462. SLV_BOLERO_EVT_RX_MUTE,
  1463. (WCD_RX2 << 0x10 | 0x1));
  1464. if (wcd9378->update_wcd_event)
  1465. wcd9378->update_wcd_event(wcd9378->handle,
  1466. SLV_BOLERO_EVT_RX_MUTE,
  1467. (WCD_RX2 << 0x10));
  1468. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1469. if (act_ps)
  1470. dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1471. __func__, act_ps);
  1472. else
  1473. dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1474. __func__, act_ps);
  1475. break;
  1476. case SND_SOC_DAPM_POST_PMD:
  1477. if (wcd9378->update_wcd_event)
  1478. wcd9378->update_wcd_event(wcd9378->handle,
  1479. SLV_BOLERO_EVT_RX_MUTE,
  1480. (WCD_RX2 << 0x10 | 0x1));
  1481. if (wcd9378->update_wcd_event && wcd9378->comp2_enable)
  1482. wcd9378->update_wcd_event(wcd9378->handle,
  1483. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1484. (WCD_RX2 << 0x10));
  1485. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1486. WCD_EVENT_POST_HPHR_PA_OFF,
  1487. &wcd9378->mbhc->wcd_mbhc);
  1488. break;
  1489. default:
  1490. break;
  1491. };
  1492. return 0;
  1493. }
  1494. static int wcd9378_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1495. struct snd_kcontrol *kcontrol,
  1496. int event)
  1497. {
  1498. struct snd_soc_component *component =
  1499. snd_soc_dapm_to_component(w->dapm);
  1500. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1501. int ret = 0;
  1502. int bank = 0;
  1503. int act_ps = 0;
  1504. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1505. w->name, event);
  1506. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1507. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1508. switch (event) {
  1509. case SND_SOC_DAPM_PRE_PMU:
  1510. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1511. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1512. wcd9378->rx_swr_dev->dev_num,
  1513. true);
  1514. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1515. if (test_bit(RX1_AUX_EN, &wcd9378->sys_usage_status)) {
  1516. if (wcd9378->update_wcd_event)
  1517. wcd9378->update_wcd_event(wcd9378->handle,
  1518. SLV_BOLERO_EVT_RX_MUTE,
  1519. (WCD_RX2 << 0x10));
  1520. } else {
  1521. if (wcd9378->update_wcd_event)
  1522. wcd9378->update_wcd_event(wcd9378->handle,
  1523. SLV_BOLERO_EVT_RX_MUTE,
  1524. (WCD_RX3 << 0x10));
  1525. }
  1526. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1527. if (act_ps)
  1528. dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1529. __func__, act_ps);
  1530. else
  1531. dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1532. __func__, act_ps);
  1533. break;
  1534. case SND_SOC_DAPM_POST_PMD:
  1535. if (test_bit(RX1_AUX_EN, &wcd9378->sys_usage_status)) {
  1536. if (wcd9378->update_wcd_event)
  1537. wcd9378->update_wcd_event(wcd9378->handle,
  1538. SLV_BOLERO_EVT_RX_MUTE,
  1539. (WCD_RX2 << 0x10 | 0x1));
  1540. } else {
  1541. if (wcd9378->update_wcd_event)
  1542. wcd9378->update_wcd_event(wcd9378->handle,
  1543. SLV_BOLERO_EVT_RX_MUTE,
  1544. (WCD_RX3 << 0x10 | 0x1));
  1545. }
  1546. break;
  1547. };
  1548. return ret;
  1549. }
  1550. static int wcd9378_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1551. struct snd_kcontrol *kcontrol,
  1552. int event)
  1553. {
  1554. struct snd_soc_component *component =
  1555. snd_soc_dapm_to_component(w->dapm);
  1556. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1557. int ret = 0, bank = 0;
  1558. int act_ps = 0;
  1559. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1560. w->name, event);
  1561. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1562. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1563. switch (event) {
  1564. case SND_SOC_DAPM_PRE_PMU:
  1565. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1566. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1567. wcd9378->rx_swr_dev->dev_num,
  1568. true);
  1569. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1570. if (test_bit(RX0_EAR_EN, &wcd9378->sys_usage_status)) {
  1571. if (wcd9378->update_wcd_event)
  1572. wcd9378->update_wcd_event(wcd9378->handle,
  1573. SLV_BOLERO_EVT_RX_MUTE,
  1574. (WCD_RX1 << 0x10));
  1575. } else {
  1576. if (wcd9378->update_wcd_event)
  1577. wcd9378->update_wcd_event(wcd9378->handle,
  1578. SLV_BOLERO_EVT_RX_MUTE,
  1579. (WCD_RX3 << 0x10));
  1580. }
  1581. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1582. if (act_ps)
  1583. dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1584. __func__, act_ps);
  1585. else
  1586. dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1587. __func__, act_ps);
  1588. break;
  1589. case SND_SOC_DAPM_POST_PMD:
  1590. if (test_bit(RX0_EAR_EN, &wcd9378->sys_usage_status)) {
  1591. if (wcd9378->update_wcd_event)
  1592. wcd9378->update_wcd_event(wcd9378->handle,
  1593. SLV_BOLERO_EVT_RX_MUTE,
  1594. (WCD_RX1 << 0x10 | 0x1));
  1595. } else {
  1596. if (wcd9378->update_wcd_event)
  1597. wcd9378->update_wcd_event(wcd9378->handle,
  1598. SLV_BOLERO_EVT_RX_MUTE,
  1599. (WCD_RX3 << 0x10 | 0x1));
  1600. }
  1601. break;
  1602. };
  1603. return ret;
  1604. }
  1605. static int wcd9378_get_hph_pwr_level(int hph_mode)
  1606. {
  1607. switch (hph_mode) {
  1608. case CLS_H_LOHIFI:
  1609. case CLS_AB_LOHIFI:
  1610. return PWR_LEVEL_LOHIFI_VAL;
  1611. case CLS_H_LP:
  1612. case CLS_AB_LP:
  1613. return PWR_LEVEL_LP_VAL;
  1614. case CLS_H_HIFI:
  1615. case CLS_AB_HIFI:
  1616. return PWR_LEVEL_HIFI_VAL;
  1617. case CLS_H_ULP:
  1618. case CLS_AB:
  1619. case CLS_H_NORMAL:
  1620. default:
  1621. return PWR_LEVEL_ULP_VAL;
  1622. }
  1623. return PWR_LEVEL_ULP_VAL;
  1624. }
  1625. static void wcd9378_hph_set_channel_volume(struct snd_soc_component *component)
  1626. {
  1627. struct wcd9378_priv *wcd9378 =
  1628. snd_soc_component_get_drvdata(component);
  1629. if ((!wcd9378->comp1_enable) &&
  1630. (!wcd9378->comp2_enable)) {
  1631. dev_err(component->dev, "%s hph gainis 0x%0xd\n", __func__, wcd9378->hph_gain);
  1632. snd_soc_component_update_bits(component,
  1633. (WCD9378_FU42_CH_VOL_CH1 | WCD9378_MBQ_ENABLE_MASK),
  1634. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1635. wcd9378->hph_gain >> 8);
  1636. snd_soc_component_update_bits(component,
  1637. WCD9378_FU42_CH_VOL_CH1,
  1638. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1639. wcd9378->hph_gain & 0x00ff);
  1640. snd_soc_component_update_bits(component,
  1641. (WCD9378_FU42_CH_VOL_CH2 | WCD9378_MBQ_ENABLE_MASK),
  1642. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1643. wcd9378->hph_gain >> 8);
  1644. snd_soc_component_update_bits(component,
  1645. WCD9378_FU42_CH_VOL_CH2,
  1646. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1647. wcd9378->hph_gain & 0x00ff);
  1648. }
  1649. }
  1650. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable)
  1651. {
  1652. u16 clk_scale_reg = 0;
  1653. u8 clk_rst = 0x00, scale_rst = 0x00;
  1654. u8 swr_base_clk = 0, swr_clk_scale = 0;
  1655. struct wcd9378_priv *wcd9378 = NULL;
  1656. struct swr_device *swr_dev = NULL;
  1657. wcd9378 = dev_get_drvdata(dev);
  1658. if (!wcd9378)
  1659. return -EINVAL;
  1660. if (path == RX_PATH) {
  1661. swr_dev = wcd9378->rx_swr_dev;
  1662. swr_base_clk = wcd9378->swr_base_clk;
  1663. swr_clk_scale = wcd9378->swr_clk_scale;
  1664. } else {
  1665. swr_dev = wcd9378->tx_swr_dev;
  1666. swr_base_clk = SWR_BASECLK_19P2MHZ;
  1667. swr_clk_scale = SWR_CLKSCALE_DIV2;
  1668. }
  1669. clk_scale_reg = (bank ? SWRS_SCP_BUSCLOCK_SCALE_BANK1 :
  1670. SWRS_SCP_BUSCLOCK_SCALE_BANK0);
  1671. if (enable) {
  1672. swr_write(swr_dev, swr_dev->dev_num,
  1673. SWRS_SCP_BASE_CLK_BASE, &swr_base_clk);
  1674. swr_write(swr_dev, swr_dev->dev_num,
  1675. clk_scale_reg, &swr_clk_scale);
  1676. } else {
  1677. swr_write(swr_dev, swr_dev->dev_num,
  1678. SWRS_SCP_BASE_CLK_BASE, &clk_rst);
  1679. swr_write(swr_dev, swr_dev->dev_num,
  1680. clk_scale_reg, &scale_rst);
  1681. }
  1682. return 0;
  1683. }
  1684. static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
  1685. struct snd_kcontrol *kcontrol, int event)
  1686. {
  1687. struct snd_soc_component *component =
  1688. snd_soc_dapm_to_component(w->dapm);
  1689. struct wcd9378_priv *wcd9378 =
  1690. snd_soc_component_get_drvdata(component);
  1691. int power_level, bank = 0;
  1692. int ret = 0;
  1693. struct swr_device *swr_dev = wcd9378->tx_swr_dev;
  1694. u8 scp_commit_val = 0x2;
  1695. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1696. w->name, event);
  1697. switch (event) {
  1698. case SND_SOC_DAPM_PRE_PMU:
  1699. wcd9378_sys_usage_auto_udpate(component, RX0_RX1_HPH_EN, true);
  1700. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable)) {
  1701. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T7,
  1702. WCD9378_HPH_UP_T7_HPH_UP_T7_MASK, 0x07);
  1703. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T1,
  1704. WCD9378_HPH_DN_T1_HPH_DN_T1_MASK, 0x07);
  1705. }
  1706. if ((wcd9378->hph_mode == CLS_AB) ||
  1707. (wcd9378->hph_mode == CLS_AB_HIFI) ||
  1708. (wcd9378->hph_mode == CLS_AB_LP) ||
  1709. (wcd9378->hph_mode == CLS_AB_LOHIFI))
  1710. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1711. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1712. /*GET HPH_MODE*/
  1713. power_level = wcd9378_get_hph_pwr_level(wcd9378->hph_mode);
  1714. /*SET HPH_MODE*/
  1715. snd_soc_component_update_bits(component, WCD9378_IT41_USAGE,
  1716. WCD9378_IT41_USAGE_IT41_USAGE_MASK, power_level);
  1717. /*TURN ON HPH SEQUENCER*/
  1718. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1719. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x00);
  1720. /*TBD: SET SDCA GAIN, NEED CHECK THE LOGIC*/
  1721. wcd9378_hph_set_channel_volume(component);
  1722. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable))
  1723. /*PA delay is 22400us*/
  1724. usleep_range(22500, 22510);
  1725. else
  1726. /*COMP delay is 9400us*/
  1727. usleep_range(9500, 9510);
  1728. /*RX0 unmute*/
  1729. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1730. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x00);
  1731. /*RX1 unmute*/
  1732. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1733. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x00);
  1734. if (wcd9378->sys_usage == SYS_USAGE_10)
  1735. /*FU23 UNMUTE*/
  1736. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1737. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
  1738. swr_write(swr_dev, swr_dev->dev_num, 0x004c, &scp_commit_val);
  1739. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1740. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1741. wcd9378->rx_swr_dev->dev_num,
  1742. true);
  1743. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1744. break;
  1745. case SND_SOC_DAPM_POST_PMD:
  1746. /*RX0 mute*/
  1747. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1748. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x01);
  1749. /*RX1 mute*/
  1750. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1751. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x01);
  1752. /*TEAR DOWN HPH SEQUENCER*/
  1753. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1754. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x03);
  1755. if (!wcd9378->comp1_enable || !wcd9378->comp2_enable)
  1756. /*PA delay is 24250us*/
  1757. usleep_range(24300, 24310);
  1758. else
  1759. /*COMP delay is 11250us*/
  1760. usleep_range(11300, 11310);
  1761. wcd9378_sys_usage_auto_udpate(component, RX0_RX1_HPH_EN, false);
  1762. break;
  1763. default:
  1764. break;
  1765. };
  1766. return ret;
  1767. }
  1768. static int wcd9378_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  1769. struct snd_kcontrol *kcontrol,
  1770. int event)
  1771. {
  1772. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1773. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1774. int ear_rx2 = 0;
  1775. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1776. w->name, event);
  1777. ear_rx2 = snd_soc_component_read(component, WCD9378_CDC_AUX_GAIN_CTL) &
  1778. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK;
  1779. switch (event) {
  1780. case SND_SOC_DAPM_PRE_PMU:
  1781. /*SHORT_PROT_EN ENABLE*/
  1782. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  1783. WCD9378_ANA_EAR_SHORT_PROT_EN_MASK, 0x40);
  1784. if (!ear_rx2) {
  1785. /*RX0 ENABLE*/
  1786. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1787. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
  1788. wcd9378_sys_usage_auto_udpate(component, RX0_EAR_EN, true);
  1789. if (wcd9378->comp1_enable) {
  1790. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1791. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x04);
  1792. wcd9378_rx_connect_port(component, COMP_L, true);
  1793. }
  1794. wcd9378_rx_connect_port(component, HPH_L, true);
  1795. } else {
  1796. wcd9378_sys_usage_auto_udpate(component, RX2_EAR_EN, true);
  1797. /*FORCE CLASS_AB EN*/
  1798. snd_soc_component_update_bits(component, WCD9378_SEQ_OVRRIDE_CTL0,
  1799. WCD9378_SEQ_OVRRIDE_CTL0_CLASSAB_EN_OVR_MASK, 0x20);
  1800. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1801. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1802. if (wcd9378->rx2_clk_mode)
  1803. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1804. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1805. wcd9378_rx_connect_port(component, LO, true);
  1806. }
  1807. break;
  1808. case SND_SOC_DAPM_POST_PMD:
  1809. /*SHORT_PROT_EN DISABLE*/
  1810. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  1811. WCD9378_ANA_EAR_SHORT_PROT_EN_MASK, 0x00);
  1812. if (test_bit(RX0_EAR_EN, &wcd9378->sys_usage_status)) {
  1813. /*RX0 DISABLE*/
  1814. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1815. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1816. wcd9378_rx_connect_port(component, HPH_L, false);
  1817. if (wcd9378->comp1_enable) {
  1818. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1819. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x00);
  1820. wcd9378_rx_connect_port(component, COMP_L, false);
  1821. }
  1822. wcd9378_sys_usage_auto_udpate(component, RX0_EAR_EN, false);
  1823. } else {
  1824. wcd9378_rx_connect_port(component, LO, false);
  1825. wcd9378_sys_usage_auto_udpate(component, RX2_EAR_EN, false);
  1826. }
  1827. break;
  1828. };
  1829. return 0;
  1830. }
  1831. static int wcd9378_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  1832. struct snd_kcontrol *kcontrol,
  1833. int event)
  1834. {
  1835. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1836. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1837. int aux_rx2 = 0;
  1838. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1839. w->name, event);
  1840. aux_rx2 = snd_soc_component_read(component, WCD9378_CDC_AUX_GAIN_CTL) &
  1841. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK;
  1842. switch (event) {
  1843. case SND_SOC_DAPM_PRE_PMU:
  1844. /*AUXPA SHORT PROT ENABLE*/
  1845. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  1846. WCD9378_AUX_AUXPA_AUX_PA_SHORT_PROT_EN_MASK, 0x40);
  1847. if (!aux_rx2) {
  1848. /*RX1 ENABLE*/
  1849. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1850. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
  1851. wcd9378_sys_usage_auto_udpate(component, RX1_AUX_EN, true);
  1852. wcd9378_rx_connect_port(component, HPH_R, true);
  1853. } else {
  1854. wcd9378_sys_usage_auto_udpate(component, RX2_AUX_EN, true);
  1855. if (wcd9378->rx2_clk_mode)
  1856. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1857. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1858. wcd9378_rx_connect_port(component, LO, true);
  1859. }
  1860. break;
  1861. case SND_SOC_DAPM_POST_PMD:
  1862. /*AUXPA SHORT PROT DISABLE*/
  1863. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  1864. WCD9378_AUX_AUXPA_AUX_PA_SHORT_PROT_EN_MASK, 0x00);
  1865. if (test_bit(RX1_AUX_EN, &wcd9378->sys_usage_status)) {
  1866. wcd9378_rx_connect_port(component, HPH_R, false);
  1867. wcd9378_sys_usage_auto_udpate(component, RX1_AUX_EN, false);
  1868. } else {
  1869. wcd9378_rx_connect_port(component, LO, true);
  1870. wcd9378_sys_usage_auto_udpate(component, RX2_AUX_EN, false);
  1871. }
  1872. break;
  1873. };
  1874. return 0;
  1875. }
  1876. static int wcd9378_sa_sequencer_enable(struct snd_soc_dapm_widget *w,
  1877. struct snd_kcontrol *kcontrol, int event)
  1878. {
  1879. struct snd_soc_component *component =
  1880. snd_soc_dapm_to_component(w->dapm);
  1881. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1882. w->name, event);
  1883. switch (event) {
  1884. case SND_SOC_DAPM_PRE_PMU:
  1885. /*TURN ON AMP SEQUENCER*/
  1886. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1887. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x00);
  1888. /*default delay 8550us*/
  1889. usleep_range(8600, 8610);
  1890. /*FU23 UNMUTE*/
  1891. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1892. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
  1893. break;
  1894. case SND_SOC_DAPM_POST_PMD:
  1895. /*FU23 MUTE*/
  1896. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1897. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x01);
  1898. /*TEAR DOWN AMP SEQUENCER*/
  1899. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1900. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x03);
  1901. /*default delay 1530us*/
  1902. usleep_range(15400, 15410);
  1903. break;
  1904. default:
  1905. break;
  1906. };
  1907. return 0;
  1908. }
  1909. int wcd9378_micbias_control(struct snd_soc_component *component,
  1910. int micb_num, int req, bool is_dapm)
  1911. {
  1912. struct wcd9378_priv *wcd9378 =
  1913. snd_soc_component_get_drvdata(component);
  1914. struct wcd9378_pdata *pdata =
  1915. dev_get_platdata(wcd9378->dev);
  1916. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  1917. int micb_usage = 0, micb_mask = 0, micb_usage_val = 0;
  1918. int pre_off_event = 0, post_off_event = 0;
  1919. int post_on_event = 0, post_dapm_off = 0;
  1920. int post_dapm_on = 0;
  1921. int pull_up_mask = 0, pull_up_en = 0;
  1922. int micb_index = 0, ret = 0;
  1923. switch (micb_num) {
  1924. case MIC_BIAS_1:
  1925. pull_up_mask = WCD9378_MB_PULLUP_EN_MB1_1P8V_OR_PULLUP_SEL_MASK;
  1926. pull_up_en = 0x01;
  1927. micb_usage = WCD9378_IT11_MICB;
  1928. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  1929. micb_usage_val = mb->micb1_usage_val;
  1930. break;
  1931. case MIC_BIAS_2:
  1932. pull_up_mask = WCD9378_MB_PULLUP_EN_MB2_1P8V_OR_PULLUP_SEL_MASK;
  1933. pull_up_en = 0x02;
  1934. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  1935. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  1936. micb_usage_val = mb->micb2_usage_val;
  1937. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1938. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1939. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1940. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1941. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1942. break;
  1943. case MIC_BIAS_3:
  1944. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  1945. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  1946. pull_up_mask = WCD9378_MB_PULLUP_EN_MB3_1P8V_OR_PULLUP_SEL_MASK;
  1947. pull_up_en = 0x04;
  1948. micb_usage_val = mb->micb3_usage_val;
  1949. break;
  1950. default:
  1951. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1952. __func__, micb_num);
  1953. return -EINVAL;
  1954. }
  1955. mutex_lock(&wcd9378->micb_lock);
  1956. micb_index = micb_num - 1;
  1957. switch (req) {
  1958. case MICB_PULLUP_ENABLE:
  1959. wcd9378->pullup_ref[micb_index]++;
  1960. if ((wcd9378->pullup_ref[micb_index] == 1) &&
  1961. (wcd9378->micb_ref[micb_index] == 0)) {
  1962. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  1963. pull_up_mask, pull_up_en);
  1964. snd_soc_component_update_bits(component,
  1965. micb_usage, micb_mask, 0x03);
  1966. if (micb_num == MIC_BIAS_2) {
  1967. dev_dbg(component->dev, "%s: pull up sj micbias\n",
  1968. __func__);
  1969. snd_soc_component_update_bits(component,
  1970. WCD9378_IT31_MICB,
  1971. WCD9378_IT31_MICB_IT31_MICB_MASK,
  1972. 0x03);
  1973. wcd9378->curr_micbias2 = 1800;
  1974. }
  1975. }
  1976. break;
  1977. case MICB_PULLUP_DISABLE:
  1978. if (wcd9378->pullup_ref[micb_index] > 0)
  1979. wcd9378->pullup_ref[micb_index]--;
  1980. if ((wcd9378->pullup_ref[micb_index] == 0) &&
  1981. (wcd9378->micb_ref[micb_index] == 0)) {
  1982. snd_soc_component_update_bits(component, micb_usage, micb_mask, 0x01);
  1983. if (micb_num == MIC_BIAS_2) {
  1984. dev_dbg(component->dev, "%s: pull down sj micbias\n",
  1985. __func__);
  1986. snd_soc_component_update_bits(component,
  1987. WCD9378_IT31_MICB,
  1988. WCD9378_IT31_MICB_IT31_MICB_MASK,
  1989. 0x01);
  1990. wcd9378->curr_micbias2 = 0;
  1991. }
  1992. }
  1993. break;
  1994. case MICB_ENABLE:
  1995. dev_dbg(component->dev, "%s: micbias enable enter\n",
  1996. __func__);
  1997. if (!wcd9378->dev_up) {
  1998. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1999. __func__, req);
  2000. ret = -ENODEV;
  2001. goto done;
  2002. }
  2003. wcd9378->micb_ref[micb_index]++;
  2004. if (wcd9378->micb_ref[micb_index] == 1) {
  2005. dev_dbg(component->dev, "%s: enable micbias, micb_usage:0x%0x, val:0x%0x\n",
  2006. __func__, micb_usage, micb_usage_val);
  2007. snd_soc_component_update_bits(component,
  2008. micb_usage, micb_mask, micb_usage_val);
  2009. if (micb_num == MIC_BIAS_2) {
  2010. dev_dbg(component->dev, "%s: enable sj micbias\n",
  2011. __func__);
  2012. snd_soc_component_update_bits(component,
  2013. WCD9378_IT31_MICB,
  2014. WCD9378_IT31_MICB_IT31_MICB_MASK,
  2015. micb_usage_val);
  2016. wcd9378->curr_micbias2 = 1800;
  2017. }
  2018. if (post_on_event)
  2019. blocking_notifier_call_chain(
  2020. &wcd9378->mbhc->notifier,
  2021. post_on_event,
  2022. &wcd9378->mbhc->wcd_mbhc);
  2023. }
  2024. if (is_dapm && post_dapm_on && wcd9378->mbhc)
  2025. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  2026. post_dapm_on,
  2027. &wcd9378->mbhc->wcd_mbhc);
  2028. break;
  2029. case MICB_DISABLE:
  2030. dev_dbg(component->dev, "%s: micbias disable enter\n",
  2031. __func__);
  2032. if (wcd9378->micb_ref[micb_index] > 0)
  2033. wcd9378->micb_ref[micb_index]--;
  2034. if ((wcd9378->micb_ref[micb_index] == 0) &&
  2035. (wcd9378->pullup_ref[micb_index] > 0)) {
  2036. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  2037. pull_up_mask, pull_up_en);
  2038. if (micb_num == MIC_BIAS_2)
  2039. wcd9378->curr_micbias2 = 1800;
  2040. } else if ((wcd9378->micb_ref[micb_index] == 0) &&
  2041. (wcd9378->pullup_ref[micb_index] == 0)) {
  2042. if (pre_off_event && wcd9378->mbhc)
  2043. blocking_notifier_call_chain(
  2044. &wcd9378->mbhc->notifier,
  2045. pre_off_event,
  2046. &wcd9378->mbhc->wcd_mbhc);
  2047. snd_soc_component_update_bits(component, micb_usage,
  2048. micb_mask, 0x00);
  2049. if (micb_num == MIC_BIAS_2) {
  2050. snd_soc_component_update_bits(component,
  2051. WCD9378_IT31_MICB,
  2052. WCD9378_IT31_MICB_IT31_MICB_MASK,
  2053. 0x00);
  2054. wcd9378->curr_micbias2 = 0;
  2055. }
  2056. if (post_off_event && wcd9378->mbhc)
  2057. blocking_notifier_call_chain(
  2058. &wcd9378->mbhc->notifier,
  2059. post_off_event,
  2060. &wcd9378->mbhc->wcd_mbhc);
  2061. }
  2062. if (is_dapm && post_dapm_off && wcd9378->mbhc)
  2063. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  2064. post_dapm_off,
  2065. &wcd9378->mbhc->wcd_mbhc);
  2066. break;
  2067. default:
  2068. dev_err(component->dev, "%s: Invalid req event: %d\n",
  2069. __func__, req);
  2070. return -EINVAL;
  2071. }
  2072. dev_dbg(component->dev,
  2073. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  2074. __func__, micb_num, wcd9378->micb_ref[micb_index],
  2075. wcd9378->pullup_ref[micb_index]);
  2076. done:
  2077. mutex_unlock(&wcd9378->micb_lock);
  2078. return ret;
  2079. }
  2080. EXPORT_SYMBOL_GPL(wcd9378_micbias_control);
  2081. static int wcd9378_get_logical_addr(struct swr_device *swr_dev)
  2082. {
  2083. int ret = 0;
  2084. uint8_t devnum = 0;
  2085. int num_retry = NUM_ATTEMPTS;
  2086. do {
  2087. /* retry after 4ms */
  2088. usleep_range(4000, 4010);
  2089. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  2090. } while (ret && --num_retry);
  2091. if (ret)
  2092. dev_err(&swr_dev->dev,
  2093. "%s get devnum %d for dev addr %llx failed\n",
  2094. __func__, devnum, swr_dev->addr);
  2095. swr_dev->dev_num = devnum;
  2096. return 0;
  2097. }
  2098. static bool get_usbc_hs_status(struct snd_soc_component *component,
  2099. struct wcd_mbhc_config *mbhc_cfg)
  2100. {
  2101. if (mbhc_cfg->enable_usbc_analog) {
  2102. if (!(snd_soc_component_read(component, WCD9378_ANA_MBHC_MECH)
  2103. & 0x20))
  2104. return true;
  2105. }
  2106. return false;
  2107. }
  2108. int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *component,
  2109. struct notifier_block *nblock,
  2110. bool enable)
  2111. {
  2112. struct wcd9378_priv *wcd9378_priv = NULL;
  2113. if (component == NULL) {
  2114. pr_err_ratelimited("%s: wcd9378 component is NULL\n", __func__);
  2115. return -EINVAL;
  2116. }
  2117. wcd9378_priv = snd_soc_component_get_drvdata(component);
  2118. wcd9378_priv->notify_swr_dmic = enable;
  2119. if (enable)
  2120. return blocking_notifier_chain_register(&wcd9378_priv->notifier,
  2121. nblock);
  2122. else
  2123. return blocking_notifier_chain_unregister(
  2124. &wcd9378_priv->notifier, nblock);
  2125. }
  2126. EXPORT_SYMBOL_GPL(wcd9378_swr_dmic_register_notifier);
  2127. static int wcd9378_event_notify(struct notifier_block *block,
  2128. unsigned long val,
  2129. void *data)
  2130. {
  2131. u16 event = (val & 0xffff);
  2132. int ret = 0;
  2133. struct wcd9378_priv *wcd9378 = dev_get_drvdata((struct device *)data);
  2134. struct snd_soc_component *component = wcd9378->component;
  2135. struct wcd_mbhc *mbhc;
  2136. int rx_clk_type;
  2137. switch (event) {
  2138. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2139. if (test_bit(WCD_ADC1, &wcd9378->status_mask)) {
  2140. snd_soc_component_update_bits(component,
  2141. WCD9378_ANA_TX_CH2, 0x40, 0x00);
  2142. set_bit(WCD_ADC1_MODE, &wcd9378->status_mask);
  2143. clear_bit(WCD_ADC1, &wcd9378->status_mask);
  2144. }
  2145. if (test_bit(WCD_ADC2, &wcd9378->status_mask)) {
  2146. snd_soc_component_update_bits(component,
  2147. WCD9378_ANA_TX_CH2, 0x20, 0x00);
  2148. set_bit(WCD_ADC2_MODE, &wcd9378->status_mask);
  2149. clear_bit(WCD_ADC2, &wcd9378->status_mask);
  2150. }
  2151. if (test_bit(WCD_ADC3, &wcd9378->status_mask)) {
  2152. snd_soc_component_update_bits(component,
  2153. WCD9378_ANA_TX_CH3_HPF, 0x40, 0x00);
  2154. set_bit(WCD_ADC3_MODE, &wcd9378->status_mask);
  2155. clear_bit(WCD_ADC3, &wcd9378->status_mask);
  2156. }
  2157. break;
  2158. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2159. snd_soc_component_update_bits(component, WCD9378_ANA_HPH,
  2160. 0xC0, 0x00);
  2161. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  2162. 0x80, 0x00);
  2163. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  2164. 0x80, 0x00);
  2165. break;
  2166. case BOLERO_SLV_EVT_SSR_DOWN:
  2167. wcd9378->dev_up = false;
  2168. if (wcd9378->notify_swr_dmic)
  2169. blocking_notifier_call_chain(&wcd9378->notifier,
  2170. WCD9378_EVT_SSR_DOWN,
  2171. NULL);
  2172. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = true;
  2173. mbhc = &wcd9378->mbhc->wcd_mbhc;
  2174. wcd9378->usbc_hs_status = get_usbc_hs_status(component,
  2175. mbhc->mbhc_cfg);
  2176. wcd9378_mbhc_ssr_down(wcd9378->mbhc, component);
  2177. wcd9378_reset_low(wcd9378->dev);
  2178. break;
  2179. case BOLERO_SLV_EVT_SSR_UP:
  2180. wcd9378_reset(wcd9378->dev);
  2181. /* allow reset to take effect */
  2182. usleep_range(10000, 10010);
  2183. wcd9378_get_logical_addr(wcd9378->tx_swr_dev);
  2184. wcd9378_get_logical_addr(wcd9378->rx_swr_dev);
  2185. wcd9378->tx_swr_dev->scp1_val = 0;
  2186. wcd9378->tx_swr_dev->scp2_val = 0;
  2187. wcd9378->rx_swr_dev->scp1_val = 0;
  2188. wcd9378->rx_swr_dev->scp2_val = 0;
  2189. wcd9378_init_reg(component);
  2190. regcache_mark_dirty(wcd9378->regmap);
  2191. regcache_sync(wcd9378->regmap);
  2192. /* Initialize MBHC module */
  2193. mbhc = &wcd9378->mbhc->wcd_mbhc;
  2194. ret = wcd9378_mbhc_post_ssr_init(wcd9378->mbhc, component);
  2195. if (ret) {
  2196. dev_err(component->dev, "%s: mbhc initialization failed\n",
  2197. __func__);
  2198. } else {
  2199. wcd9378_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2200. }
  2201. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = false;
  2202. wcd9378->dev_up = true;
  2203. if (wcd9378->notify_swr_dmic)
  2204. blocking_notifier_call_chain(&wcd9378->notifier,
  2205. WCD9378_EVT_SSR_UP,
  2206. NULL);
  2207. if (wcd9378->usbc_hs_status)
  2208. mdelay(500);
  2209. break;
  2210. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2211. snd_soc_component_update_bits(component,
  2212. WCD9378_TOP_CLK_CFG, 0x06,
  2213. ((val >> 0x10) << 0x01));
  2214. rx_clk_type = (val >> 0x10);
  2215. switch (rx_clk_type) {
  2216. case RX_CLK_12P288MHZ:
  2217. wcd9378->swr_base_clk = SWR_BASECLK_24P576MHZ;
  2218. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2219. break;
  2220. case RX_CLK_11P2896MHZ:
  2221. wcd9378->swr_base_clk = SWR_BASECLK_22P5792MHZ;
  2222. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2223. break;
  2224. default:
  2225. wcd9378->swr_base_clk = SWR_BASECLK_19P2MHZ;
  2226. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2227. break;
  2228. }
  2229. dev_dbg(component->dev, "%s: base_clk:0x%0x, clk_scale:0x%x\n",
  2230. __func__, wcd9378->swr_base_clk, wcd9378->swr_clk_scale);
  2231. break;
  2232. default:
  2233. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2234. break;
  2235. }
  2236. return 0;
  2237. }
  2238. static int wcd9378_wakeup(void *handle, bool enable)
  2239. {
  2240. struct wcd9378_priv *priv;
  2241. int ret = 0;
  2242. if (!handle) {
  2243. pr_err("%s: NULL handle\n", __func__);
  2244. return -EINVAL;
  2245. }
  2246. priv = (struct wcd9378_priv *)handle;
  2247. if (!priv->tx_swr_dev) {
  2248. pr_err("%s: tx swr dev is NULL\n", __func__);
  2249. return -EINVAL;
  2250. }
  2251. mutex_lock(&priv->wakeup_lock);
  2252. if (enable)
  2253. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2254. else
  2255. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2256. mutex_unlock(&priv->wakeup_lock);
  2257. return ret;
  2258. }
  2259. static inline int wcd9378_tx_path_get(const char *wname,
  2260. unsigned int *path_num)
  2261. {
  2262. int ret = 0;
  2263. char *widget_name = NULL;
  2264. char *w_name = NULL;
  2265. char *path_num_char = NULL;
  2266. char *path_name = NULL;
  2267. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2268. if (!widget_name)
  2269. return -EINVAL;
  2270. w_name = widget_name;
  2271. path_name = strsep(&widget_name, " ");
  2272. if (!path_name) {
  2273. pr_err("%s: Invalid widget name = %s\n",
  2274. __func__, widget_name);
  2275. ret = -EINVAL;
  2276. goto err;
  2277. }
  2278. path_num_char = strpbrk(path_name, "0123");
  2279. if (!path_num_char) {
  2280. pr_err("%s: tx path index not found\n",
  2281. __func__);
  2282. ret = -EINVAL;
  2283. goto err;
  2284. }
  2285. ret = kstrtouint(path_num_char, 10, path_num);
  2286. if (ret < 0)
  2287. pr_err("%s: Invalid tx path = %s\n",
  2288. __func__, w_name);
  2289. err:
  2290. kfree(w_name);
  2291. return ret;
  2292. }
  2293. static int wcd9378_tx_mode_get(struct snd_kcontrol *kcontrol,
  2294. struct snd_ctl_elem_value *ucontrol)
  2295. {
  2296. struct snd_soc_component *component =
  2297. snd_soc_kcontrol_component(kcontrol);
  2298. struct wcd9378_priv *wcd9378 = NULL;
  2299. int ret = 0;
  2300. unsigned int path = 0;
  2301. if (!component)
  2302. return -EINVAL;
  2303. wcd9378 = snd_soc_component_get_drvdata(component);
  2304. if (!wcd9378)
  2305. return -EINVAL;
  2306. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2307. if (ret < 0)
  2308. return ret;
  2309. ucontrol->value.integer.value[0] = wcd9378->tx_mode[path];
  2310. return 0;
  2311. }
  2312. static int wcd9378_tx_mode_put(struct snd_kcontrol *kcontrol,
  2313. struct snd_ctl_elem_value *ucontrol)
  2314. {
  2315. struct snd_soc_component *component =
  2316. snd_soc_kcontrol_component(kcontrol);
  2317. struct wcd9378_priv *wcd9378 = NULL;
  2318. u32 mode_val;
  2319. unsigned int path = 0;
  2320. int ret = 0;
  2321. if (!component)
  2322. return -EINVAL;
  2323. wcd9378 = snd_soc_component_get_drvdata(component);
  2324. if (!wcd9378)
  2325. return -EINVAL;
  2326. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2327. if (ret)
  2328. return ret;
  2329. mode_val = ucontrol->value.enumerated.item[0];
  2330. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2331. wcd9378->tx_mode[path] = mode_val;
  2332. return 0;
  2333. }
  2334. static int wcd9378_loopback_mode_get(struct snd_kcontrol *kcontrol,
  2335. struct snd_ctl_elem_value *ucontrol)
  2336. {
  2337. struct snd_soc_component *component =
  2338. snd_soc_kcontrol_component(kcontrol);
  2339. u32 loopback_mode = 0;
  2340. if (!component)
  2341. return -EINVAL;
  2342. loopback_mode = (snd_soc_component_read(component, WCD9378_LOOP_BACK_MODE) &
  2343. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK);
  2344. ucontrol->value.integer.value[0] = loopback_mode;
  2345. return 0;
  2346. }
  2347. static int wcd9378_loopback_mode_put(struct snd_kcontrol *kcontrol,
  2348. struct snd_ctl_elem_value *ucontrol)
  2349. {
  2350. struct snd_soc_component *component =
  2351. snd_soc_kcontrol_component(kcontrol);
  2352. u32 loopback_mode = 0;
  2353. if (!component)
  2354. return -EINVAL;
  2355. loopback_mode = ucontrol->value.enumerated.item[0];
  2356. snd_soc_component_update_bits(component,
  2357. WCD9378_LOOP_BACK_MODE,
  2358. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK,
  2359. loopback_mode);
  2360. dev_dbg(component->dev, "%s: loopback_mode: %d\n",
  2361. __func__, loopback_mode);
  2362. return 0;
  2363. }
  2364. static int wcd9378_aux_dsm_get(struct snd_kcontrol *kcontrol,
  2365. struct snd_ctl_elem_value *ucontrol)
  2366. {
  2367. struct snd_soc_component *component =
  2368. snd_soc_kcontrol_component(kcontrol);
  2369. u32 aux_dsm_in = 0;
  2370. if (!component)
  2371. return -EINVAL;
  2372. aux_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2373. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK);
  2374. ucontrol->value.integer.value[0] = aux_dsm_in;
  2375. return 0;
  2376. }
  2377. static int wcd9378_aux_dsm_put(struct snd_kcontrol *kcontrol,
  2378. struct snd_ctl_elem_value *ucontrol)
  2379. {
  2380. struct snd_soc_component *component =
  2381. snd_soc_kcontrol_component(kcontrol);
  2382. u32 aux_dsm_in = 0;
  2383. if (!component)
  2384. return -EINVAL;
  2385. aux_dsm_in = ucontrol->value.enumerated.item[0];
  2386. snd_soc_component_update_bits(component,
  2387. WCD9378_LB_IN_SEL_CTL,
  2388. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK,
  2389. aux_dsm_in);
  2390. dev_dbg(component->dev, "%s: aux_dsm input: %d\n",
  2391. __func__, aux_dsm_in);
  2392. return 0;
  2393. }
  2394. static int wcd9378_hph_dsm_get(struct snd_kcontrol *kcontrol,
  2395. struct snd_ctl_elem_value *ucontrol)
  2396. {
  2397. struct snd_soc_component *component =
  2398. snd_soc_kcontrol_component(kcontrol);
  2399. u32 hph_dsm_in = 0;
  2400. if (!component)
  2401. return -EINVAL;
  2402. hph_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2403. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK);
  2404. ucontrol->value.integer.value[0] = hph_dsm_in;
  2405. return 0;
  2406. }
  2407. static int wcd9378_hph_dsm_put(struct snd_kcontrol *kcontrol,
  2408. struct snd_ctl_elem_value *ucontrol)
  2409. {
  2410. struct snd_soc_component *component =
  2411. snd_soc_kcontrol_component(kcontrol);
  2412. u32 hph_dsm_in = 0;
  2413. if (!component)
  2414. return -EINVAL;
  2415. hph_dsm_in = ucontrol->value.enumerated.item[0];
  2416. snd_soc_component_update_bits(component,
  2417. WCD9378_LB_IN_SEL_CTL,
  2418. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK,
  2419. hph_dsm_in);
  2420. dev_dbg(component->dev, "%s: hph_dsm input: %d\n",
  2421. __func__, hph_dsm_in);
  2422. return 0;
  2423. }
  2424. static int wcd9378_hph_put_gain(struct snd_kcontrol *kcontrol,
  2425. struct snd_ctl_elem_value *ucontrol)
  2426. {
  2427. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2428. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2429. u16 offset = ucontrol->value.enumerated.item[0];
  2430. u32 temp = 0;
  2431. temp = 0x00 - offset * 0x180;
  2432. wcd9378->hph_gain = (u16)(temp & 0xffff);
  2433. dev_dbg(component->dev, "%s: hph gain is 0x%0x\n", __func__, wcd9378->hph_gain);
  2434. return 0;
  2435. }
  2436. static int wcd9378_hph_get_gain(struct snd_kcontrol *kcontrol,
  2437. struct snd_ctl_elem_value *ucontrol)
  2438. {
  2439. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2440. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2441. u32 temp = 0;
  2442. u16 offset = 0;
  2443. temp = 0 - wcd9378->hph_gain;
  2444. offset = (u16)(temp & 0xffff);
  2445. offset /= 0x180;
  2446. ucontrol->value.enumerated.item[0] = offset;
  2447. dev_dbg(component->dev, "%s: offset is 0x%0x\n", __func__, offset);
  2448. return 0;
  2449. }
  2450. static int wcd9378_rx2_mode_put(struct snd_kcontrol *kcontrol,
  2451. struct snd_ctl_elem_value *ucontrol)
  2452. {
  2453. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2454. struct wcd9378_priv *wcd9378 =
  2455. snd_soc_component_get_drvdata(component);
  2456. if (ucontrol->value.enumerated.item[0])
  2457. wcd9378->rx2_clk_mode = RX2_NORMAL_MODE;
  2458. else
  2459. wcd9378->rx2_clk_mode = RX2_HP_MODE;
  2460. return 1;
  2461. }
  2462. static int wcd9378_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2463. struct snd_ctl_elem_value *ucontrol)
  2464. {
  2465. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2466. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2467. ucontrol->value.enumerated.item[0] = wcd9378->hph_mode;
  2468. return 0;
  2469. }
  2470. static int wcd9378_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2471. struct snd_ctl_elem_value *ucontrol)
  2472. {
  2473. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2474. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2475. if (wcd9378->hph_mode == ucontrol->value.enumerated.item[0])
  2476. return 0;
  2477. wcd9378->hph_mode = ucontrol->value.enumerated.item[0];
  2478. return 1;
  2479. }
  2480. /* wcd9378_codec_get_dev_num - returns swr device number
  2481. * @component: Codec instance
  2482. *
  2483. * Return: swr device number on success or negative error
  2484. * code on failure.
  2485. */
  2486. int wcd9378_codec_get_dev_num(struct snd_soc_component *component)
  2487. {
  2488. struct wcd9378_priv *wcd9378;
  2489. if (!component)
  2490. return -EINVAL;
  2491. wcd9378 = snd_soc_component_get_drvdata(component);
  2492. if (!wcd9378 || !wcd9378->rx_swr_dev) {
  2493. pr_err("%s: wcd9378 component is NULL\n", __func__);
  2494. return -EINVAL;
  2495. }
  2496. return wcd9378->rx_swr_dev->dev_num;
  2497. }
  2498. EXPORT_SYMBOL_GPL(wcd9378_codec_get_dev_num);
  2499. static int wcd9378_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
  2500. struct snd_ctl_elem_value *ucontrol)
  2501. {
  2502. struct snd_soc_component *component =
  2503. snd_soc_kcontrol_component(kcontrol);
  2504. struct wcd9378_priv *wcd9378 =
  2505. snd_soc_component_get_drvdata(component);
  2506. if (wcd9378->comp1_enable) {
  2507. dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
  2508. return -EINVAL;
  2509. }
  2510. snd_soc_component_update_bits(component, WCD9378_AUX_INT_MISC,
  2511. WCD9378_ANA_EAR_COMPANDER_CTL_EAR_GAIN_MASK,
  2512. ucontrol->value.integer.value[0]);
  2513. return 1;
  2514. }
  2515. static int wcd9378_aux_pa_put_gain(struct snd_kcontrol *kcontrol,
  2516. struct snd_ctl_elem_value *ucontrol)
  2517. {
  2518. struct snd_soc_component *component =
  2519. snd_soc_kcontrol_component(kcontrol);
  2520. struct wcd9378_priv *wcd9378 =
  2521. snd_soc_component_get_drvdata(component);
  2522. if (wcd9378->comp1_enable) {
  2523. dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
  2524. return -EINVAL;
  2525. }
  2526. snd_soc_component_update_bits(component, WCD9378_ANA_EAR_COMPANDER_CTL,
  2527. WCD9378_AUX_INT_MISC_PA_GAIN_MASK,
  2528. ucontrol->value.integer.value[0]);
  2529. return 1;
  2530. }
  2531. static int wcd9378_get_compander(struct snd_kcontrol *kcontrol,
  2532. struct snd_ctl_elem_value *ucontrol)
  2533. {
  2534. struct snd_soc_component *component =
  2535. snd_soc_kcontrol_component(kcontrol);
  2536. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2537. bool hphr;
  2538. struct soc_multi_mixer_control *mc;
  2539. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2540. hphr = mc->shift;
  2541. ucontrol->value.integer.value[0] = hphr ? wcd9378->comp2_enable :
  2542. wcd9378->comp1_enable;
  2543. return 0;
  2544. }
  2545. static int wcd9378_set_compander(struct snd_kcontrol *kcontrol,
  2546. struct snd_ctl_elem_value *ucontrol)
  2547. {
  2548. struct snd_soc_component *component =
  2549. snd_soc_kcontrol_component(kcontrol);
  2550. struct wcd9378_priv *wcd9378 =
  2551. snd_soc_component_get_drvdata(component);
  2552. int value = ucontrol->value.integer.value[0];
  2553. bool hphr;
  2554. struct soc_multi_mixer_control *mc;
  2555. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2556. hphr = mc->shift;
  2557. if (hphr)
  2558. wcd9378->comp2_enable = value;
  2559. else
  2560. wcd9378->comp1_enable = value;
  2561. dev_dbg(component->dev, "%s: set compander: %d\n", __func__, value);
  2562. return 0;
  2563. }
  2564. static int wcd9378_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2565. struct snd_kcontrol *kcontrol,
  2566. int event)
  2567. {
  2568. struct snd_soc_component *component =
  2569. snd_soc_dapm_to_component(w->dapm);
  2570. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2571. struct wcd9378_pdata *pdata = NULL;
  2572. int ret = 0;
  2573. pdata = dev_get_platdata(wcd9378->dev);
  2574. if (!pdata) {
  2575. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2576. return -EINVAL;
  2577. }
  2578. if (!msm_cdc_is_ondemand_supply(wcd9378->dev,
  2579. wcd9378->supplies,
  2580. pdata->regulator,
  2581. pdata->num_supplies,
  2582. "cdc-vdd-buck"))
  2583. return 0;
  2584. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2585. w->name, event);
  2586. switch (event) {
  2587. case SND_SOC_DAPM_PRE_PMU:
  2588. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  2589. dev_dbg(component->dev,
  2590. "%s: buck already in enabled state\n",
  2591. __func__);
  2592. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2593. return 0;
  2594. }
  2595. ret = msm_cdc_enable_ondemand_supply(wcd9378->dev,
  2596. wcd9378->supplies,
  2597. pdata->regulator,
  2598. pdata->num_supplies,
  2599. "cdc-vdd-buck");
  2600. if (ret == -EINVAL) {
  2601. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2602. __func__);
  2603. return ret;
  2604. }
  2605. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2606. /*
  2607. * 200us sleep is required after LDO is enabled as per
  2608. * HW requirement
  2609. */
  2610. usleep_range(200, 250);
  2611. break;
  2612. case SND_SOC_DAPM_POST_PMD:
  2613. set_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2614. break;
  2615. }
  2616. return 0;
  2617. }
  2618. const char * const tx_master_ch_text[] = {
  2619. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2620. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2621. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2622. "SWRM_PCM_IN",
  2623. };
  2624. const struct soc_enum tx_master_ch_enum =
  2625. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2626. tx_master_ch_text);
  2627. static void wcd9378_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2628. {
  2629. u8 ch_type = 0;
  2630. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2631. ch_type = ADC1;
  2632. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2633. ch_type = ADC2;
  2634. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2635. ch_type = ADC3;
  2636. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2637. ch_type = ADC4;
  2638. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2639. ch_type = DMIC0;
  2640. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2641. ch_type = DMIC1;
  2642. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2643. ch_type = MBHC;
  2644. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2645. ch_type = DMIC2;
  2646. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2647. ch_type = DMIC3;
  2648. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2649. ch_type = DMIC4;
  2650. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2651. ch_type = DMIC5;
  2652. else
  2653. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2654. if (ch_type)
  2655. *ch_idx = wcd9378_slave_get_slave_ch_val(ch_type);
  2656. else
  2657. *ch_idx = -EINVAL;
  2658. }
  2659. static int wcd9378_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2660. struct snd_ctl_elem_value *ucontrol)
  2661. {
  2662. struct snd_soc_component *component =
  2663. snd_soc_kcontrol_component(kcontrol);
  2664. struct wcd9378_priv *wcd9378 = NULL;
  2665. int slave_ch_idx = -EINVAL;
  2666. if (component == NULL)
  2667. return -EINVAL;
  2668. wcd9378 = snd_soc_component_get_drvdata(component);
  2669. if (wcd9378 == NULL)
  2670. return -EINVAL;
  2671. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2672. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2673. return -EINVAL;
  2674. ucontrol->value.integer.value[0] = wcd9378_slave_get_master_ch_val(
  2675. wcd9378->tx_master_ch_map[slave_ch_idx]);
  2676. return 0;
  2677. }
  2678. static int wcd9378_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2679. struct snd_ctl_elem_value *ucontrol)
  2680. {
  2681. struct snd_soc_component *component =
  2682. snd_soc_kcontrol_component(kcontrol);
  2683. struct wcd9378_priv *wcd9378 = NULL;
  2684. int slave_ch_idx = -EINVAL, idx = 0;
  2685. if (component == NULL)
  2686. return -EINVAL;
  2687. wcd9378 = snd_soc_component_get_drvdata(component);
  2688. if (wcd9378 == NULL)
  2689. return -EINVAL;
  2690. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2691. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2692. return -EINVAL;
  2693. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2694. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2695. __func__, ucontrol->value.enumerated.item[0]);
  2696. idx = ucontrol->value.enumerated.item[0];
  2697. if (idx < 0 || idx >= ARRAY_SIZE(wcd9378_swr_master_ch_map))
  2698. return -EINVAL;
  2699. wcd9378->tx_master_ch_map[slave_ch_idx] = wcd9378_slave_get_master_ch(idx);
  2700. return 0;
  2701. }
  2702. static int wcd9378_bcs_get(struct snd_kcontrol *kcontrol,
  2703. struct snd_ctl_elem_value *ucontrol)
  2704. {
  2705. struct snd_soc_component *component =
  2706. snd_soc_kcontrol_component(kcontrol);
  2707. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2708. ucontrol->value.integer.value[0] = wcd9378->bcs_dis;
  2709. return 0;
  2710. }
  2711. static int wcd9378_bcs_put(struct snd_kcontrol *kcontrol,
  2712. struct snd_ctl_elem_value *ucontrol)
  2713. {
  2714. struct snd_soc_component *component =
  2715. snd_soc_kcontrol_component(kcontrol);
  2716. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2717. wcd9378->bcs_dis = ucontrol->value.integer.value[0];
  2718. return 0;
  2719. }
  2720. static const char * const loopback_mode_text[] = {
  2721. "NO_LP", "SWR_LP1", "SWR_LP2", "SWR_LP3",
  2722. };
  2723. static const struct soc_enum loopback_mode_enum =
  2724. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(loopback_mode_text),
  2725. loopback_mode_text);
  2726. static const char * const aux_dsm_text[] = {
  2727. "TX2->AUX", "TX3->AUX", "TX0->AUX", "TX1->AUX",
  2728. };
  2729. static const struct soc_enum aux_dsm_enum =
  2730. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aux_dsm_text),
  2731. aux_dsm_text);
  2732. static const char * const hph_dsm_text[] = {
  2733. "HPH_DSM_IN0", "HPH_DSM_IN1", "HPH_DSM_IN2", "HPH_DSM_IN3",
  2734. };
  2735. static const struct soc_enum hph_dsm_enum =
  2736. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(hph_dsm_text),
  2737. hph_dsm_text);
  2738. static const char * const tx_mode_mux_text[] = {
  2739. "ADC_INVALID", "ADC_HIFI", "ADC_NORMAL", "ADC_LP",
  2740. };
  2741. static const struct soc_enum tx_mode_mux_enum =
  2742. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2743. tx_mode_mux_text);
  2744. static const char * const rx2_mode_text[] = {
  2745. "HP", "NORMAL",
  2746. };
  2747. static const struct soc_enum rx2_mode_enum =
  2748. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx2_mode_text),
  2749. rx2_mode_text);
  2750. static const char * const rx_hph_mode_mux_text[] = {
  2751. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2752. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2753. };
  2754. static const struct soc_enum rx_hph_mode_mux_enum =
  2755. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2756. rx_hph_mode_mux_text);
  2757. static const struct snd_kcontrol_new wcd9378_snd_controls[] = {
  2758. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2759. wcd9378_get_compander, wcd9378_set_compander),
  2760. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2761. wcd9378_get_compander, wcd9378_set_compander),
  2762. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2763. wcd9378_bcs_get, wcd9378_bcs_put),
  2764. SOC_ENUM_EXT("LOOPBACK Mode", loopback_mode_enum,
  2765. wcd9378_loopback_mode_get, wcd9378_loopback_mode_put),
  2766. SOC_ENUM_EXT("AUX_LB_IN SEL", aux_dsm_enum,
  2767. wcd9378_aux_dsm_get, wcd9378_aux_dsm_put),
  2768. SOC_ENUM_EXT("HPH_LB_IN SEL", hph_dsm_enum,
  2769. wcd9378_hph_dsm_get, wcd9378_hph_dsm_put),
  2770. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2771. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2772. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2773. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2774. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2775. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2776. SOC_ENUM_EXT("RX2 Mode", rx2_mode_enum,
  2777. NULL, wcd9378_rx2_mode_put),
  2778. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2779. wcd9378_rx_hph_mode_get, wcd9378_rx_hph_mode_put),
  2780. SOC_SINGLE_EXT("HPH Volume", SND_SOC_NOPM, 0, 0x14, 0,
  2781. wcd9378_hph_get_gain, wcd9378_hph_put_gain),
  2782. WCD9378_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD9378_ANA_EAR_COMPANDER_CTL,
  2783. 2, 0x10, 0, ear_pa_gain),
  2784. WCD9378_AUX_PA_GAIN_TLV("AUX_PA Volume", WCD9378_AUX_INT_MISC,
  2785. 0, 0x8, 0, aux_pa_gain),
  2786. SOC_SINGLE_TLV("ADC1 Volume", WCD9378_ANA_TX_CH1, 0, 20, 0,
  2787. analog_gain),
  2788. SOC_SINGLE_TLV("ADC2 Volume", WCD9378_ANA_TX_CH2, 0, 20, 0,
  2789. analog_gain),
  2790. SOC_SINGLE_TLV("ADC3 Volume", WCD9378_ANA_TX_CH3, 0, 20, 0,
  2791. analog_gain),
  2792. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2793. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2794. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2795. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2796. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2797. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2798. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2799. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2800. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2801. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2802. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2803. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2804. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2805. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2806. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2807. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2808. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2809. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2810. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2811. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2812. };
  2813. static const struct snd_kcontrol_new amic1_switch[] = {
  2814. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2815. };
  2816. static const struct snd_kcontrol_new amic2_switch[] = {
  2817. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2818. };
  2819. static const struct snd_kcontrol_new amic3_switch[] = {
  2820. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2821. };
  2822. static const struct snd_kcontrol_new amic4_switch[] = {
  2823. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2824. };
  2825. static const struct snd_kcontrol_new va_amic1_switch[] = {
  2826. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2827. };
  2828. static const struct snd_kcontrol_new va_amic2_switch[] = {
  2829. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2830. };
  2831. static const struct snd_kcontrol_new va_amic3_switch[] = {
  2832. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2833. };
  2834. static const struct snd_kcontrol_new va_amic4_switch[] = {
  2835. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2836. };
  2837. static const struct snd_kcontrol_new dmic1_switch[] = {
  2838. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2839. };
  2840. static const struct snd_kcontrol_new dmic2_switch[] = {
  2841. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2842. };
  2843. static const struct snd_kcontrol_new dmic3_switch[] = {
  2844. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2845. };
  2846. static const struct snd_kcontrol_new dmic4_switch[] = {
  2847. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2848. };
  2849. static const struct snd_kcontrol_new dmic5_switch[] = {
  2850. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2851. };
  2852. static const struct snd_kcontrol_new dmic6_switch[] = {
  2853. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2854. };
  2855. static const char * const adc1_mux_text[] = {
  2856. "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4"
  2857. };
  2858. static const char * const adc2_mux_text[] = {
  2859. "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4"
  2860. };
  2861. static const char * const adc3_mux_text[] = {
  2862. "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4"
  2863. };
  2864. static const char * const ear_mux_text[] = {
  2865. "RX0", "RX2"
  2866. };
  2867. static const char * const aux_mux_text[] = {
  2868. "RX1", "RX2"
  2869. };
  2870. static const struct soc_enum adc1_enum =
  2871. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2872. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT,
  2873. ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
  2874. static const struct soc_enum adc2_enum =
  2875. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2876. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT,
  2877. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2878. static const struct soc_enum adc3_enum =
  2879. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH34_MUX,
  2880. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT,
  2881. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2882. static const struct soc_enum ear_enum =
  2883. SOC_ENUM_SINGLE(WCD9378_CDC_AUX_GAIN_CTL,
  2884. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_SHIFT,
  2885. ARRAY_SIZE(ear_mux_text), ear_mux_text);
  2886. static const struct soc_enum aux_enum =
  2887. SOC_ENUM_SINGLE(WCD9378_CDC_AUX_GAIN_CTL,
  2888. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_SHIFT,
  2889. ARRAY_SIZE(aux_mux_text), aux_mux_text);
  2890. static const struct snd_kcontrol_new tx_adc1_mux =
  2891. SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
  2892. static const struct snd_kcontrol_new tx_adc2_mux =
  2893. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2894. static const struct snd_kcontrol_new tx_adc3_mux =
  2895. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2896. static const struct snd_kcontrol_new ear_mux =
  2897. SOC_DAPM_ENUM("EAR Mux", ear_enum);
  2898. static const struct snd_kcontrol_new aux_mux =
  2899. SOC_DAPM_ENUM("AUX Mux", aux_enum);
  2900. static const struct snd_kcontrol_new dac1_switch[] = {
  2901. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2902. };
  2903. static const struct snd_kcontrol_new dac2_switch[] = {
  2904. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2905. };
  2906. static const struct snd_kcontrol_new ear_mixer_switch[] = {
  2907. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2908. };
  2909. static const struct snd_kcontrol_new aux_mixer_switch[] = {
  2910. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2911. };
  2912. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2913. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2914. };
  2915. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2916. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2917. };
  2918. static const struct snd_kcontrol_new rx0_switch[] = {
  2919. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2920. };
  2921. static const struct snd_kcontrol_new rx1_switch[] = {
  2922. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2923. };
  2924. static const struct snd_soc_dapm_widget wcd9378_dapm_widgets[] = {
  2925. /*input widgets*/
  2926. SND_SOC_DAPM_INPUT("AMIC1"),
  2927. SND_SOC_DAPM_INPUT("AMIC2"),
  2928. SND_SOC_DAPM_INPUT("AMIC3"),
  2929. SND_SOC_DAPM_INPUT("AMIC4"),
  2930. SND_SOC_DAPM_INPUT("VA AMIC1"),
  2931. SND_SOC_DAPM_INPUT("VA AMIC2"),
  2932. SND_SOC_DAPM_INPUT("VA AMIC3"),
  2933. SND_SOC_DAPM_INPUT("VA AMIC4"),
  2934. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2935. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2936. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2937. /*tx widgets*/
  2938. SND_SOC_DAPM_MIXER_E("TX0 SEQUENCER", SND_SOC_NOPM, ADC1, 0,
  2939. NULL, 0, wcd9378_tx_sequencer_enable,
  2940. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2941. SND_SOC_DAPM_MIXER_E("TX1 SEQUENCER", SND_SOC_NOPM, ADC2, 0,
  2942. NULL, 0, wcd9378_tx_sequencer_enable,
  2943. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2944. SND_SOC_DAPM_MIXER_E("TX2 SEQUENCER", SND_SOC_NOPM, ADC3, 0,
  2945. NULL, 0, wcd9378_tx_sequencer_enable,
  2946. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2947. SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
  2948. &tx_adc1_mux),
  2949. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2950. &tx_adc2_mux),
  2951. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2952. &tx_adc3_mux),
  2953. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2954. wcd9378_codec_enable_dmic,
  2955. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2956. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2957. wcd9378_codec_enable_dmic,
  2958. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2959. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2960. wcd9378_codec_enable_dmic,
  2961. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2962. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2963. wcd9378_codec_enable_dmic,
  2964. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2965. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2966. wcd9378_codec_enable_dmic,
  2967. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2968. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2969. wcd9378_codec_enable_dmic,
  2970. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2971. /*rx widgets*/
  2972. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2973. wcd9378_codec_hphl_dac_event,
  2974. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2975. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2976. wcd9378_codec_hphr_dac_event,
  2977. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2978. SND_SOC_DAPM_MIXER_E("HPH SEQUENCER", SND_SOC_NOPM, 0, 0, NULL, 0,
  2979. wcd9378_hph_sequencer_enable,
  2980. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2981. SND_SOC_DAPM_PGA_E("HPHL PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2982. wcd9378_codec_enable_hphl_pa,
  2983. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2984. SND_SOC_DAPM_PGA_E("HPHR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2985. wcd9378_codec_enable_hphr_pa,
  2986. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2987. SND_SOC_DAPM_MIXER_E("SA SEQUENCER", SND_SOC_NOPM, 0, 0,
  2988. NULL, 0, wcd9378_sa_sequencer_enable,
  2989. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2990. SND_SOC_DAPM_DAC_E("EAR_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  2991. wcd9378_codec_ear_dac_event,
  2992. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2993. SND_SOC_DAPM_DAC_E("AUX_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  2994. wcd9378_codec_aux_dac_event,
  2995. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2996. SND_SOC_DAPM_PGA_E("EAR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2997. wcd9378_codec_enable_ear_pa,
  2998. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2999. SND_SOC_DAPM_PGA_E("AUX PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  3000. wcd9378_codec_enable_aux_pa,
  3001. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3002. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  3003. wcd9378_codec_enable_vdd_buck,
  3004. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3005. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  3006. wcd9378_enable_clsh,
  3007. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3008. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3009. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  3010. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3011. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3012. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  3013. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3014. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3015. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  3016. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3017. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3018. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  3019. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3020. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3021. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  3022. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3023. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3024. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  3025. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3026. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3027. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  3028. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3029. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3030. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3031. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3032. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3033. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3034. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3035. SND_SOC_DAPM_POST_PMD),
  3036. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3037. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3038. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3039. SND_SOC_DAPM_POST_PMD),
  3040. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3041. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3042. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3043. SND_SOC_DAPM_POST_PMD),
  3044. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3045. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3046. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3047. SND_SOC_DAPM_POST_PMD),
  3048. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3049. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3050. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3051. SND_SOC_DAPM_POST_PMD),
  3052. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3053. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3054. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3055. SND_SOC_DAPM_POST_PMD),
  3056. /* micbias widgets*/
  3057. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3058. wcd9378_codec_enable_micbias,
  3059. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3060. SND_SOC_DAPM_POST_PMD),
  3061. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3062. wcd9378_codec_enable_micbias,
  3063. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3064. SND_SOC_DAPM_POST_PMD),
  3065. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3066. wcd9378_codec_enable_micbias,
  3067. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3068. SND_SOC_DAPM_POST_PMD),
  3069. /* micbias pull up widgets*/
  3070. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3071. wcd9378_codec_enable_micbias_pullup,
  3072. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3073. SND_SOC_DAPM_POST_PMD),
  3074. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3075. wcd9378_codec_enable_micbias_pullup,
  3076. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3077. SND_SOC_DAPM_POST_PMD),
  3078. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3079. wcd9378_codec_enable_micbias_pullup,
  3080. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3081. SND_SOC_DAPM_POST_PMD),
  3082. /* rx mixer widgets*/
  3083. SND_SOC_DAPM_MUX("EAR_MUX", SND_SOC_NOPM, 0, 0, &ear_mux),
  3084. SND_SOC_DAPM_MUX("AUX_MUX", SND_SOC_NOPM, 0, 0, &aux_mux),
  3085. SND_SOC_DAPM_MIXER("EAR_MIXER", SND_SOC_NOPM, 0, 0,
  3086. ear_mixer_switch, ARRAY_SIZE(ear_mixer_switch)),
  3087. SND_SOC_DAPM_MIXER("AUX_MIXER", SND_SOC_NOPM, 0, 0,
  3088. aux_mixer_switch, ARRAY_SIZE(aux_mixer_switch)),
  3089. SND_SOC_DAPM_MIXER("DAC1", SND_SOC_NOPM, 0, 0,
  3090. dac1_switch, ARRAY_SIZE(dac1_switch)),
  3091. SND_SOC_DAPM_MIXER("DAC2", SND_SOC_NOPM, 0, 0,
  3092. dac2_switch, ARRAY_SIZE(dac2_switch)),
  3093. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3094. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3095. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3096. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3097. /*output widgets tx*/
  3098. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  3099. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  3100. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  3101. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  3102. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  3103. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  3104. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  3105. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  3106. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  3107. /*output widgets rx*/
  3108. SND_SOC_DAPM_OUTPUT("EAR"),
  3109. SND_SOC_DAPM_OUTPUT("AUX"),
  3110. SND_SOC_DAPM_OUTPUT("HPHL"),
  3111. SND_SOC_DAPM_OUTPUT("HPHR"),
  3112. };
  3113. static const struct snd_soc_dapm_route wcd9378_audio_map[] = {
  3114. /*ADC-1 (channel-1)*/
  3115. {"ADC1_OUTPUT", NULL, "TX0 SEQUENCER"},
  3116. {"TX0 SEQUENCER", NULL, "ADC1 MUX"},
  3117. {"ADC1 MUX", "CH1_AMIC1", "AMIC1_MIXER"},
  3118. {"ADC1 MUX", "CH1_AMIC2", "AMIC2_MIXER"},
  3119. {"ADC1 MUX", "CH1_AMIC3", "AMIC3_MIXER"},
  3120. {"ADC1 MUX", "CH1_AMIC4", "AMIC4_MIXER"},
  3121. /*ADC-2 (channel-2)*/
  3122. {"ADC2_OUTPUT", NULL, "TX1 SEQUENCER"},
  3123. {"TX1 SEQUENCER", NULL, "ADC2 MUX"},
  3124. {"ADC2 MUX", "CH2_AMIC1", "AMIC1_MIXER"},
  3125. {"ADC2 MUX", "CH2_AMIC2", "AMIC2_MIXER"},
  3126. {"ADC2 MUX", "CH2_AMIC3", "AMIC3_MIXER"},
  3127. {"ADC2 MUX", "CH2_AMIC4", "AMIC4_MIXER"},
  3128. /*ADC-3 (channel-3)*/
  3129. {"ADC3_OUTPUT", NULL, "TX2 SEQUENCER"},
  3130. {"TX2 SEQUENCER", NULL, "ADC3 MUX"},
  3131. {"ADC3 MUX", "CH3_AMIC1", "AMIC1_MIXER"},
  3132. {"ADC3 MUX", "CH3_AMIC3", "AMIC3_MIXER"},
  3133. {"ADC3 MUX", "CH3_AMIC4", "AMIC4_MIXER"},
  3134. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3135. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3136. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3137. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3138. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3139. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3140. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3141. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3142. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3143. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3144. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3145. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3146. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  3147. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3148. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  3149. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3150. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  3151. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3152. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  3153. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3154. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  3155. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3156. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  3157. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3158. /*Headphone playback*/
  3159. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3160. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3161. {"HPH SEQUENCER", NULL, "IN1_HPHL"},
  3162. {"RDAC1", NULL, "HPH SEQUENCER"},
  3163. {"HPHL_RDAC", "Switch", "RDAC1"},
  3164. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3165. {"HPHL", NULL, "HPHL PGA"},
  3166. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3167. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3168. {"HPH SEQUENCER", NULL, "IN2_HPHR"},
  3169. {"RDAC2", NULL, "HPH SEQUENCER"},
  3170. {"HPHR_RDAC", "Switch", "RDAC2"},
  3171. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3172. {"HPHR", NULL, "HPHR PGA"},
  3173. /*Amplier playback*/
  3174. {"IN3_AUX", NULL, "VDD_BUCK"},
  3175. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3176. {"EAR_MUX", "RX0", "IN1_HPHL"},
  3177. {"EAR_MUX", "RX2", "IN3_AUX"},
  3178. {"DAC1", "Switch", "EAR_MUX"},
  3179. {"EAR_RDAC", NULL, "DAC1"},
  3180. {"SA SEQUENCER", NULL, "EAR_RDAC"},
  3181. {"EAR_MIXER", "Switch", "SA SEQUENCER"},
  3182. {"EAR PGA", NULL, "EAR_MIXER"},
  3183. {"EAR", NULL, "EAR PGA"},
  3184. {"AUX_MUX", "RX1", "IN2_HPHR"},
  3185. {"AUX_MUX", "RX2", "IN3_AUX"},
  3186. {"DAC2", "Switch", "AUX_MUX"},
  3187. {"AUX_RDAC", NULL, "DAC2"},
  3188. {"SA SEQUENCER", NULL, "AUX_RDAC"},
  3189. {"AUX_MIXER", "Switch", "SA SEQUENCER",},
  3190. {"AUX PGA", NULL, "AUX_MIXER"},
  3191. {"AUX", NULL, "AUX PGA"},
  3192. };
  3193. static ssize_t wcd9378_version_read(struct snd_info_entry *entry,
  3194. void *file_private_data,
  3195. struct file *file,
  3196. char __user *buf, size_t count,
  3197. loff_t pos)
  3198. {
  3199. struct wcd9378_priv *priv;
  3200. char buffer[WCD9378_VERSION_ENTRY_SIZE];
  3201. int len = 0;
  3202. priv = (struct wcd9378_priv *) entry->private_data;
  3203. if (!priv) {
  3204. pr_err("%s: wcd9378 priv is null\n", __func__);
  3205. return -EINVAL;
  3206. }
  3207. switch (priv->version) {
  3208. case WCD9378_VERSION_1_0:
  3209. len = scnprintf(buffer, sizeof(buffer), "WCD9378_1_0\n");
  3210. break;
  3211. default:
  3212. len = scnprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3213. }
  3214. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3215. }
  3216. static struct snd_info_entry_ops wcd9378_info_ops = {
  3217. .read = wcd9378_version_read,
  3218. };
  3219. /*
  3220. * wcd9378_info_create_codec_entry - creates wcd9378 module
  3221. * @codec_root: The parent directory
  3222. * @component: component instance
  3223. *
  3224. * Creates wcd9378 module, version entry under the given
  3225. * parent directory.
  3226. *
  3227. * Return: 0 on success or negative error code on failure.
  3228. */
  3229. int wcd9378_info_create_codec_entry(struct snd_info_entry *codec_root,
  3230. struct snd_soc_component *component)
  3231. {
  3232. struct snd_info_entry *version_entry;
  3233. struct wcd9378_priv *priv;
  3234. struct snd_soc_card *card;
  3235. if (!codec_root || !component)
  3236. return -EINVAL;
  3237. priv = snd_soc_component_get_drvdata(component);
  3238. if (priv->entry) {
  3239. dev_dbg(priv->dev,
  3240. "%s:wcd9378 module already created\n", __func__);
  3241. return 0;
  3242. }
  3243. card = component->card;
  3244. priv->entry = snd_info_create_module_entry(codec_root->module,
  3245. "wcd9378", codec_root);
  3246. if (!priv->entry) {
  3247. dev_dbg(component->dev, "%s: failed to create wcd9378 entry\n",
  3248. __func__);
  3249. return -ENOMEM;
  3250. }
  3251. priv->entry->mode = S_IFDIR | 0555;
  3252. if (snd_info_register(priv->entry) < 0) {
  3253. snd_info_free_entry(priv->entry);
  3254. return -ENOMEM;
  3255. }
  3256. version_entry = snd_info_create_card_entry(card->snd_card,
  3257. "version",
  3258. priv->entry);
  3259. if (!version_entry) {
  3260. dev_dbg(component->dev, "%s: failed to create wcd9378 version entry\n",
  3261. __func__);
  3262. snd_info_free_entry(priv->entry);
  3263. return -ENOMEM;
  3264. }
  3265. version_entry->private_data = priv;
  3266. version_entry->size = WCD9378_VERSION_ENTRY_SIZE;
  3267. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3268. version_entry->c.ops = &wcd9378_info_ops;
  3269. if (snd_info_register(version_entry) < 0) {
  3270. snd_info_free_entry(version_entry);
  3271. snd_info_free_entry(priv->entry);
  3272. return -ENOMEM;
  3273. }
  3274. priv->version_entry = version_entry;
  3275. return 0;
  3276. }
  3277. EXPORT_SYMBOL_GPL(wcd9378_info_create_codec_entry);
  3278. static void wcd9378_class_load(struct snd_soc_component *component)
  3279. {
  3280. /*SMP AMP CLASS LOADING*/
  3281. snd_soc_component_update_bits(component, WCD9378_FUNC_ACT,
  3282. WCD9378_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3283. usleep_range(20000, 20010);
  3284. snd_soc_component_update_bits(component, WCD9378_SMP_AMP_FUNC_STAT,
  3285. WCD9378_SMP_AMP_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3286. /*SMP JACK CLASS LOADING*/
  3287. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_ACT,
  3288. WCD9378_SMP_JACK_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3289. usleep_range(30000, 30010);
  3290. snd_soc_component_update_bits(component, WCD9378_CMT_GRP_MASK,
  3291. WCD9378_CMT_GRP_MASK_CMT_GRP_MASK_MASK, 0x02);
  3292. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_STAT,
  3293. WCD9378_SMP_JACK_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3294. /*SMP MIC0 CLASS LOADING*/
  3295. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_ACT,
  3296. WCD9378_SMP_MIC_CTRL0_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3297. usleep_range(5000, 5010);
  3298. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_STAT,
  3299. WCD9378_SMP_MIC_CTRL0_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3300. /*SMP MIC1 CLASS LOADING*/
  3301. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_ACT,
  3302. WCD9378_SMP_MIC_CTRL1_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3303. usleep_range(5000, 5010);
  3304. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_STAT,
  3305. WCD9378_SMP_MIC_CTRL1_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3306. /*SMP MIC2 CLASS LOADING*/
  3307. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_ACT,
  3308. WCD9378_SMP_MIC_CTRL2_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3309. usleep_range(5000, 5010);
  3310. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_STAT,
  3311. WCD9378_SMP_MIC_CTRL2_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3312. }
  3313. static void wcd9378_micb_value_convert(struct snd_soc_component *component)
  3314. {
  3315. struct wcd9378_priv *wcd9378 =
  3316. snd_soc_component_get_drvdata(component);
  3317. struct wcd9378_pdata *pdata =
  3318. dev_get_platdata(wcd9378->dev);
  3319. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  3320. mb->micb1_usage_val = wcd9378_micb_usage_value_convert(component,
  3321. mb->micb1_mv, MIC_BIAS_1);
  3322. mb->micb2_usage_val = wcd9378_micb_usage_value_convert(component,
  3323. mb->micb2_mv, MIC_BIAS_2);
  3324. mb->micb3_usage_val = wcd9378_micb_usage_value_convert(component,
  3325. mb->micb3_mv, MIC_BIAS_3);
  3326. pr_debug("%s: micb1_usage: 0x%x, micb2_usage: 0x%x, micb3_usage: 0x%x\n", __func__,
  3327. mb->micb1_usage_val, mb->micb2_usage_val, mb->micb3_usage_val);
  3328. }
  3329. static int wcd9378_wcd_mode_check(struct snd_soc_component *component)
  3330. {
  3331. struct wcd9378_priv *wcd9378 =
  3332. snd_soc_component_get_drvdata(component);
  3333. if (snd_soc_component_read(component,
  3334. WCD9378_EFUSE_REG_29)
  3335. & WCD9378_EFUSE_REG_29_PLATFORM_BLOWN_MASK) {
  3336. if (((snd_soc_component_read(component,
  3337. WCD9378_EFUSE_REG_29) &
  3338. WCD9378_EFUSE_REG_29_PLATFORM_MASK) >> 1) == wcd9378->wcd_mode)
  3339. return true;
  3340. else
  3341. return false;
  3342. } else {
  3343. if ((snd_soc_component_read(component, WCD9378_PLATFORM_CTL)
  3344. & WCD9378_PLATFORM_CTL_MODE_MASK) == wcd9378->wcd_mode)
  3345. return true;
  3346. else
  3347. return false;
  3348. }
  3349. return 0;
  3350. }
  3351. static int wcd9378_soc_codec_probe(struct snd_soc_component *component)
  3352. {
  3353. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3354. struct snd_soc_dapm_context *dapm =
  3355. snd_soc_component_get_dapm(component);
  3356. int ret = -EINVAL;
  3357. wcd9378 = snd_soc_component_get_drvdata(component);
  3358. if (!wcd9378)
  3359. return -EINVAL;
  3360. wcd9378->component = component;
  3361. snd_soc_component_init_regmap(component, wcd9378->regmap);
  3362. devm_regmap_qti_debugfs_register(&wcd9378->tx_swr_dev->dev, wcd9378->regmap);
  3363. ret = wcd9378_wcd_mode_check(component);
  3364. if (!ret) {
  3365. dev_err(component->dev, "wcd mode check failed\n");
  3366. ret = -EINVAL;
  3367. goto exit;
  3368. }
  3369. ret = wcd9378_mbhc_init(&wcd9378->mbhc, component);
  3370. if (ret) {
  3371. pr_err("%s: mbhc initialization failed\n", __func__);
  3372. ret = -EINVAL;
  3373. goto exit;
  3374. }
  3375. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3376. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3377. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3378. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3379. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3380. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3381. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3382. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3383. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3384. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3385. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3386. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  3387. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  3388. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  3389. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3390. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3391. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3392. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3393. snd_soc_dapm_sync(dapm);
  3394. wcd_cls_h_init(&wcd9378->clsh_info);
  3395. wcd9378_init_reg(component);
  3396. wcd9378_micb_value_convert(component);
  3397. wcd9378->version = WCD9378_VERSION_1_0;
  3398. /* Register event notifier */
  3399. wcd9378->nblock.notifier_call = wcd9378_event_notify;
  3400. if (wcd9378->register_notifier) {
  3401. ret = wcd9378->register_notifier(wcd9378->handle,
  3402. &wcd9378->nblock,
  3403. true);
  3404. if (ret) {
  3405. dev_err(component->dev,
  3406. "%s: Failed to register notifier %d\n",
  3407. __func__, ret);
  3408. return ret;
  3409. }
  3410. }
  3411. exit:
  3412. return ret;
  3413. }
  3414. static void wcd9378_soc_codec_remove(struct snd_soc_component *component)
  3415. {
  3416. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3417. if (!wcd9378) {
  3418. dev_err(component->dev, "%s: wcd9378 is already NULL\n",
  3419. __func__);
  3420. return;
  3421. }
  3422. if (wcd9378->register_notifier)
  3423. wcd9378->register_notifier(wcd9378->handle,
  3424. &wcd9378->nblock,
  3425. false);
  3426. }
  3427. static int wcd9378_soc_codec_suspend(struct snd_soc_component *component)
  3428. {
  3429. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3430. if (!wcd9378)
  3431. return 0;
  3432. wcd9378->dapm_bias_off = true;
  3433. return 0;
  3434. }
  3435. static int wcd9378_soc_codec_resume(struct snd_soc_component *component)
  3436. {
  3437. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3438. if (!wcd9378)
  3439. return 0;
  3440. wcd9378->dapm_bias_off = false;
  3441. return 0;
  3442. }
  3443. static const struct snd_soc_component_driver soc_codec_dev_wcd9378 = {
  3444. .name = WCD9378_DRV_NAME,
  3445. .probe = wcd9378_soc_codec_probe,
  3446. .remove = wcd9378_soc_codec_remove,
  3447. .controls = wcd9378_snd_controls,
  3448. .num_controls = ARRAY_SIZE(wcd9378_snd_controls),
  3449. .dapm_widgets = wcd9378_dapm_widgets,
  3450. .num_dapm_widgets = ARRAY_SIZE(wcd9378_dapm_widgets),
  3451. .dapm_routes = wcd9378_audio_map,
  3452. .num_dapm_routes = ARRAY_SIZE(wcd9378_audio_map),
  3453. .suspend = wcd9378_soc_codec_suspend,
  3454. .resume = wcd9378_soc_codec_resume,
  3455. };
  3456. static int wcd9378_reset(struct device *dev)
  3457. {
  3458. struct wcd9378_priv *wcd9378 = NULL;
  3459. int rc = 0;
  3460. int value = 0;
  3461. if (!dev)
  3462. return -ENODEV;
  3463. wcd9378 = dev_get_drvdata(dev);
  3464. if (!wcd9378)
  3465. return -EINVAL;
  3466. if (!wcd9378->rst_np) {
  3467. dev_err(dev, "%s: reset gpio device node not specified\n",
  3468. __func__);
  3469. return -EINVAL;
  3470. }
  3471. value = msm_cdc_pinctrl_get_state(wcd9378->rst_np);
  3472. if (value > 0)
  3473. return 0;
  3474. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3475. if (rc) {
  3476. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3477. __func__);
  3478. return -EPROBE_DEFER;
  3479. }
  3480. /* 20us sleep required after pulling the reset gpio to LOW */
  3481. usleep_range(20, 30);
  3482. rc = msm_cdc_pinctrl_select_active_state(wcd9378->rst_np);
  3483. if (rc) {
  3484. dev_err(dev, "%s: wcd active state request fail!\n",
  3485. __func__);
  3486. return -EPROBE_DEFER;
  3487. }
  3488. /* 20us sleep required after pulling the reset gpio to HIGH */
  3489. usleep_range(20, 30);
  3490. return rc;
  3491. }
  3492. static int wcd9378_read_of_property_u32(struct device *dev, const char *name,
  3493. u32 *val)
  3494. {
  3495. int rc = 0;
  3496. rc = of_property_read_u32(dev->of_node, name, val);
  3497. if (rc)
  3498. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3499. __func__, name, dev->of_node->full_name);
  3500. return rc;
  3501. }
  3502. static void wcd9378_dt_parse_micbias_info(struct device *dev,
  3503. struct wcd9378_micbias_setting *mb)
  3504. {
  3505. u32 prop_val = 0;
  3506. int rc = 0;
  3507. /* MB1 */
  3508. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3509. NULL)) {
  3510. rc = wcd9378_read_of_property_u32(dev,
  3511. "qcom,cdc-micbias1-mv",
  3512. &prop_val);
  3513. if (!rc)
  3514. mb->micb1_mv = prop_val;
  3515. } else {
  3516. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3517. __func__);
  3518. }
  3519. /* MB2 */
  3520. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3521. NULL)) {
  3522. rc = wcd9378_read_of_property_u32(dev,
  3523. "qcom,cdc-micbias2-mv",
  3524. &prop_val);
  3525. if (!rc)
  3526. mb->micb2_mv = prop_val;
  3527. } else {
  3528. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3529. __func__);
  3530. }
  3531. /* MB3 */
  3532. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3533. NULL)) {
  3534. rc = wcd9378_read_of_property_u32(dev,
  3535. "qcom,cdc-micbias3-mv",
  3536. &prop_val);
  3537. if (!rc)
  3538. mb->micb3_mv = prop_val;
  3539. } else {
  3540. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3541. __func__);
  3542. }
  3543. }
  3544. static int wcd9378_reset_low(struct device *dev)
  3545. {
  3546. struct wcd9378_priv *wcd9378 = NULL;
  3547. int rc = 0;
  3548. if (!dev)
  3549. return -ENODEV;
  3550. wcd9378 = dev_get_drvdata(dev);
  3551. if (!wcd9378)
  3552. return -EINVAL;
  3553. if (!wcd9378->rst_np) {
  3554. dev_err(dev, "%s: reset gpio device node not specified\n",
  3555. __func__);
  3556. return -EINVAL;
  3557. }
  3558. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3559. if (rc) {
  3560. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3561. __func__);
  3562. return rc;
  3563. }
  3564. /* 20us sleep required after pulling the reset gpio to LOW */
  3565. usleep_range(20, 30);
  3566. return rc;
  3567. }
  3568. struct wcd9378_pdata *wcd9378_populate_dt_data(struct device *dev)
  3569. {
  3570. struct wcd9378_pdata *pdata = NULL;
  3571. pdata = devm_kzalloc(dev, sizeof(struct wcd9378_pdata),
  3572. GFP_KERNEL);
  3573. if (!pdata)
  3574. return NULL;
  3575. pdata->rst_np = of_parse_phandle(dev->of_node,
  3576. "qcom,wcd-rst-gpio-node", 0);
  3577. if (!pdata->rst_np) {
  3578. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3579. __func__, "qcom,wcd-rst-gpio-node",
  3580. dev->of_node->full_name);
  3581. return NULL;
  3582. }
  3583. /* Parse power supplies */
  3584. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3585. &pdata->num_supplies);
  3586. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3587. dev_err(dev, "%s: no power supplies defined for codec\n",
  3588. __func__);
  3589. return NULL;
  3590. }
  3591. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3592. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3593. wcd9378_dt_parse_micbias_info(dev, &pdata->micbias);
  3594. return pdata;
  3595. }
  3596. static struct snd_soc_dai_driver wcd9378_dai[] = {
  3597. {
  3598. .name = "wcd9378_cdc",
  3599. .playback = {
  3600. .stream_name = "WCD9378_AIF Playback",
  3601. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3602. .formats = WCD9378_FORMATS,
  3603. .rate_max = 384000,
  3604. .rate_min = 8000,
  3605. .channels_min = 1,
  3606. .channels_max = 4,
  3607. },
  3608. .capture = {
  3609. .stream_name = "WCD9378_AIF Capture",
  3610. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3611. .formats = WCD9378_FORMATS,
  3612. .rate_max = 384000,
  3613. .rate_min = 8000,
  3614. .channels_min = 1,
  3615. .channels_max = 4,
  3616. },
  3617. },
  3618. };
  3619. static int wcd9378_bind(struct device *dev)
  3620. {
  3621. int ret = 0;
  3622. struct wcd9378_pdata *pdata = dev_get_platdata(dev);
  3623. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3624. /*
  3625. * Add 5msec delay to provide sufficient time for
  3626. * soundwire auto enumeration of slave devices as
  3627. * per HW requirement.
  3628. */
  3629. usleep_range(5000, 5010);
  3630. ret = component_bind_all(dev, wcd9378);
  3631. if (ret) {
  3632. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3633. __func__, ret);
  3634. return ret;
  3635. }
  3636. wcd9378->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3637. if (!wcd9378->rx_swr_dev) {
  3638. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3639. __func__);
  3640. ret = -ENODEV;
  3641. goto err;
  3642. }
  3643. wcd9378->rx_swr_dev->paging_support = true;
  3644. wcd9378->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3645. if (!wcd9378->tx_swr_dev) {
  3646. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3647. __func__);
  3648. ret = -ENODEV;
  3649. goto err;
  3650. }
  3651. wcd9378->tx_swr_dev->paging_support = true;
  3652. swr_init_port_params(wcd9378->tx_swr_dev, SWR_NUM_PORTS,
  3653. wcd9378->swr_tx_port_params);
  3654. wcd9378->regmap = devm_regmap_init_swr(wcd9378->tx_swr_dev,
  3655. &wcd9378_regmap_config);
  3656. if (!wcd9378->regmap) {
  3657. dev_err(dev, "%s: Regmap init failed\n",
  3658. __func__);
  3659. goto err;
  3660. }
  3661. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_1, 0xff);
  3662. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_2, 0x0b);
  3663. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_3, 0xff);
  3664. wcd9378_regmap_irq_chip.irq_drv_data = wcd9378;
  3665. wcd9378->irq_info.wcd_regmap_irq_chip = &wcd9378_regmap_irq_chip;
  3666. wcd9378->irq_info.codec_name = "WCD9378";
  3667. wcd9378->irq_info.regmap = wcd9378->regmap;
  3668. wcd9378->irq_info.dev = dev;
  3669. ret = wcd_irq_init(&wcd9378->irq_info, &wcd9378->virq);
  3670. if (ret) {
  3671. dev_err(wcd9378->dev, "%s: IRQ init failed: %d\n",
  3672. __func__, ret);
  3673. goto err;
  3674. }
  3675. dev_err(wcd9378->dev, "%s: wcd irq init done\n",
  3676. __func__);
  3677. wcd9378->tx_swr_dev->slave_irq = wcd9378->virq;
  3678. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd9378,
  3679. wcd9378_dai, ARRAY_SIZE(wcd9378_dai));
  3680. if (ret) {
  3681. dev_err(dev, "%s: Codec registration failed\n",
  3682. __func__);
  3683. goto err_irq;
  3684. }
  3685. wcd9378->dev_up = true;
  3686. return ret;
  3687. err_irq:
  3688. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3689. err:
  3690. component_unbind_all(dev, wcd9378);
  3691. return ret;
  3692. }
  3693. static void wcd9378_unbind(struct device *dev)
  3694. {
  3695. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3696. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3697. snd_soc_unregister_component(dev);
  3698. component_unbind_all(dev, wcd9378);
  3699. }
  3700. static const struct of_device_id wcd9378_dt_match[] = {
  3701. { .compatible = "qcom,wcd9378-codec", .data = "wcd9378"},
  3702. {}
  3703. };
  3704. static const struct component_master_ops wcd9378_comp_ops = {
  3705. .bind = wcd9378_bind,
  3706. .unbind = wcd9378_unbind,
  3707. };
  3708. static int wcd9378_compare_of(struct device *dev, void *data)
  3709. {
  3710. return dev->of_node == data;
  3711. }
  3712. static void wcd9378_release_of(struct device *dev, void *data)
  3713. {
  3714. of_node_put(data);
  3715. }
  3716. static int wcd9378_add_slave_components(struct device *dev,
  3717. struct component_match **matchptr)
  3718. {
  3719. struct device_node *np, *rx_node, *tx_node;
  3720. np = dev->of_node;
  3721. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3722. if (!rx_node) {
  3723. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3724. return -ENODEV;
  3725. }
  3726. of_node_get(rx_node);
  3727. component_match_add_release(dev, matchptr,
  3728. wcd9378_release_of,
  3729. wcd9378_compare_of,
  3730. rx_node);
  3731. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3732. if (!tx_node) {
  3733. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3734. return -ENODEV;
  3735. }
  3736. of_node_get(tx_node);
  3737. component_match_add_release(dev, matchptr,
  3738. wcd9378_release_of,
  3739. wcd9378_compare_of,
  3740. tx_node);
  3741. return 0;
  3742. }
  3743. static int wcd9378_probe(struct platform_device *pdev)
  3744. {
  3745. struct component_match *match = NULL;
  3746. struct wcd9378_priv *wcd9378 = NULL;
  3747. struct wcd9378_pdata *pdata = NULL;
  3748. struct wcd_ctrl_platform_data *plat_data = NULL;
  3749. struct device *dev = &pdev->dev;
  3750. int ret;
  3751. wcd9378 = devm_kzalloc(dev, sizeof(struct wcd9378_priv),
  3752. GFP_KERNEL);
  3753. if (!wcd9378)
  3754. return -ENOMEM;
  3755. dev_set_drvdata(dev, wcd9378);
  3756. wcd9378->dev = dev;
  3757. pdata = wcd9378_populate_dt_data(dev);
  3758. if (!pdata) {
  3759. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3760. return -EINVAL;
  3761. }
  3762. dev->platform_data = pdata;
  3763. wcd9378->rst_np = pdata->rst_np;
  3764. ret = msm_cdc_init_supplies(dev, &wcd9378->supplies,
  3765. pdata->regulator, pdata->num_supplies);
  3766. if (!wcd9378->supplies) {
  3767. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3768. __func__);
  3769. return ret;
  3770. }
  3771. plat_data = dev_get_platdata(dev->parent);
  3772. if (!plat_data) {
  3773. dev_err(dev, "%s: platform data from parent is NULL\n",
  3774. __func__);
  3775. return -EINVAL;
  3776. }
  3777. wcd9378->handle = (void *)plat_data->handle;
  3778. if (!wcd9378->handle) {
  3779. dev_err(dev, "%s: handle is NULL\n", __func__);
  3780. return -EINVAL;
  3781. }
  3782. wcd9378->update_wcd_event = plat_data->update_wcd_event;
  3783. if (!wcd9378->update_wcd_event) {
  3784. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3785. __func__);
  3786. return -EINVAL;
  3787. }
  3788. wcd9378->register_notifier = plat_data->register_notifier;
  3789. if (!wcd9378->register_notifier) {
  3790. dev_err(dev, "%s: register_notifier api is null!\n",
  3791. __func__);
  3792. return -EINVAL;
  3793. }
  3794. ret = of_property_read_u32(dev->of_node, "qcom,wcd-mode",
  3795. &wcd9378->wcd_mode);
  3796. if (ret) {
  3797. dev_dbg(dev, "%s: wcd-mode read failed, use mobile mode\n",
  3798. __func__);
  3799. wcd9378->wcd_mode = WCD9378_MOBILE_MODE;
  3800. }
  3801. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd9378->supplies,
  3802. pdata->regulator,
  3803. pdata->num_supplies);
  3804. if (ret) {
  3805. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3806. __func__);
  3807. return ret;
  3808. }
  3809. ret = wcd9378_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3810. CODEC_RX);
  3811. ret |= wcd9378_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3812. CODEC_TX);
  3813. if (ret) {
  3814. dev_err(dev, "Failed to read port mapping\n");
  3815. goto err;
  3816. }
  3817. ret = wcd9378_parse_port_params(dev, "qcom,swr-tx-port-params",
  3818. CODEC_TX);
  3819. if (ret) {
  3820. dev_err(dev, "Failed to read port params\n");
  3821. goto err;
  3822. }
  3823. mutex_init(&wcd9378->wakeup_lock);
  3824. mutex_init(&wcd9378->micb_lock);
  3825. mutex_init(&wcd9378->sys_usage_lock);
  3826. ret = wcd9378_add_slave_components(dev, &match);
  3827. if (ret)
  3828. goto err_lock_init;
  3829. ret = wcd9378_reset(dev);
  3830. if (ret == -EPROBE_DEFER) {
  3831. dev_err(dev, "%s: wcd reset failed!\n", __func__);
  3832. goto err_lock_init;
  3833. }
  3834. wcd9378->wakeup = wcd9378_wakeup;
  3835. return component_master_add_with_match(dev,
  3836. &wcd9378_comp_ops, match);
  3837. err_lock_init:
  3838. mutex_destroy(&wcd9378->micb_lock);
  3839. mutex_destroy(&wcd9378->wakeup_lock);
  3840. mutex_destroy(&wcd9378->sys_usage_lock);
  3841. err:
  3842. return ret;
  3843. }
  3844. static int wcd9378_remove(struct platform_device *pdev)
  3845. {
  3846. struct wcd9378_priv *wcd9378 = NULL;
  3847. wcd9378 = platform_get_drvdata(pdev);
  3848. component_master_del(&pdev->dev, &wcd9378_comp_ops);
  3849. mutex_destroy(&wcd9378->micb_lock);
  3850. mutex_destroy(&wcd9378->wakeup_lock);
  3851. mutex_destroy(&wcd9378->sys_usage_lock);
  3852. dev_set_drvdata(&pdev->dev, NULL);
  3853. return 0;
  3854. }
  3855. #ifdef CONFIG_PM_SLEEP
  3856. static int wcd9378_suspend(struct device *dev)
  3857. {
  3858. struct wcd9378_priv *wcd9378 = NULL;
  3859. int ret = 0;
  3860. struct wcd9378_pdata *pdata = NULL;
  3861. if (!dev)
  3862. return -ENODEV;
  3863. wcd9378 = dev_get_drvdata(dev);
  3864. if (!wcd9378)
  3865. return -EINVAL;
  3866. pdata = dev_get_platdata(wcd9378->dev);
  3867. if (!pdata) {
  3868. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3869. return -EINVAL;
  3870. }
  3871. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  3872. ret = msm_cdc_disable_ondemand_supply(wcd9378->dev,
  3873. wcd9378->supplies,
  3874. pdata->regulator,
  3875. pdata->num_supplies,
  3876. "cdc-vdd-buck");
  3877. if (ret == -EINVAL) {
  3878. dev_err(dev, "%s: vdd buck is not disabled\n",
  3879. __func__);
  3880. return 0;
  3881. }
  3882. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  3883. }
  3884. if (wcd9378->dapm_bias_off) {
  3885. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3886. wcd9378->supplies,
  3887. pdata->regulator,
  3888. pdata->num_supplies,
  3889. true);
  3890. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3891. }
  3892. return 0;
  3893. }
  3894. static int wcd9378_resume(struct device *dev)
  3895. {
  3896. struct wcd9378_priv *wcd9378 = NULL;
  3897. struct wcd9378_pdata *pdata = NULL;
  3898. if (!dev)
  3899. return -ENODEV;
  3900. wcd9378 = dev_get_drvdata(dev);
  3901. if (!wcd9378)
  3902. return -EINVAL;
  3903. pdata = dev_get_platdata(wcd9378->dev);
  3904. if (!pdata) {
  3905. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3906. return -EINVAL;
  3907. }
  3908. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask)) {
  3909. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3910. wcd9378->supplies,
  3911. pdata->regulator,
  3912. pdata->num_supplies,
  3913. false);
  3914. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3915. }
  3916. return 0;
  3917. }
  3918. static const struct dev_pm_ops wcd9378_dev_pm_ops = {
  3919. .suspend_late = wcd9378_suspend,
  3920. .resume_early = wcd9378_resume,
  3921. };
  3922. #endif
  3923. static struct platform_driver wcd9378_codec_driver = {
  3924. .probe = wcd9378_probe,
  3925. .remove = wcd9378_remove,
  3926. .driver = {
  3927. .name = "wcd9378_codec",
  3928. .of_match_table = of_match_ptr(wcd9378_dt_match),
  3929. #ifdef CONFIG_PM_SLEEP
  3930. .pm = &wcd9378_dev_pm_ops,
  3931. #endif
  3932. .suppress_bind_attrs = true,
  3933. },
  3934. };
  3935. module_platform_driver(wcd9378_codec_driver);
  3936. MODULE_DESCRIPTION("WCD9378 Codec driver");
  3937. MODULE_LICENSE("GPL");