sde_kms.c 134 KB

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  1. /*
  2. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <drm/drm_crtc.h>
  21. #include <drm/drm_fixed.h>
  22. #include <drm/drm_panel.h>
  23. #include <linux/debugfs.h>
  24. #include <linux/of_address.h>
  25. #include <linux/of_irq.h>
  26. #include <linux/dma-buf.h>
  27. #include <linux/memblock.h>
  28. #include <linux/soc/qcom/panel_event_notifier.h>
  29. #include <drm/drm_atomic_uapi.h>
  30. #include <drm/drm_probe_helper.h>
  31. #include "msm_drv.h"
  32. #include "msm_mmu.h"
  33. #include "msm_gem.h"
  34. #include "dsi_display.h"
  35. #include "dsi_drm.h"
  36. #include "sde_wb.h"
  37. #include "dp_display.h"
  38. #include "dp_drm.h"
  39. #include "dp_mst_drm.h"
  40. #include "sde_kms.h"
  41. #include "sde_core_irq.h"
  42. #include "sde_formats.h"
  43. #include "sde_hw_vbif.h"
  44. #include "sde_vbif.h"
  45. #include "sde_encoder.h"
  46. #include "sde_plane.h"
  47. #include "sde_crtc.h"
  48. #include "sde_color_processing.h"
  49. #include "sde_reg_dma.h"
  50. #include "sde_connector.h"
  51. #include "sde_vm.h"
  52. #include "sde_fence.h"
  53. #include <linux/qcom_scm.h>
  54. #include <linux/qcom-iommu-util.h>
  55. #include "soc/qcom/secure_buffer.h"
  56. #include <linux/qtee_shmbridge.h>
  57. #ifdef CONFIG_DRM_SDE_VM
  58. #include <linux/gunyah/gh_irq_lend.h>
  59. #endif
  60. #define CREATE_TRACE_POINTS
  61. #include "sde_trace.h"
  62. /* defines for secure channel call */
  63. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  64. #define MDP_DEVICE_ID 0x1A
  65. #define DEMURA_REGION_NAME_MAX 32
  66. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  67. static const char * const iommu_ports[] = {
  68. "mdp_0",
  69. };
  70. /**
  71. * Controls size of event log buffer. Specified as a power of 2.
  72. */
  73. #define SDE_EVTLOG_SIZE 1024
  74. /*
  75. * To enable overall DRM driver logging
  76. * # echo 0x2 > /sys/module/drm/parameters/debug
  77. *
  78. * To enable DRM driver h/w logging
  79. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  80. *
  81. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  82. */
  83. #define SDE_DEBUGFS_DIR "msm_sde"
  84. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  85. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  86. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  87. /**
  88. * sdecustom - enable certain driver customizations for sde clients
  89. * Enabling this modifies the standard DRM behavior slightly and assumes
  90. * that the clients have specific knowledge about the modifications that
  91. * are involved, so don't enable this unless you know what you're doing.
  92. *
  93. * Parts of the driver that are affected by this setting may be located by
  94. * searching for invocations of the 'sde_is_custom_client()' function.
  95. *
  96. * This is disabled by default.
  97. */
  98. static bool sdecustom = true;
  99. module_param(sdecustom, bool, 0400);
  100. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  101. static int sde_kms_hw_init(struct msm_kms *kms);
  102. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  103. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  104. static int _sde_kms_register_events(struct msm_kms *kms,
  105. struct drm_mode_object *obj, u32 event, bool en);
  106. static void sde_kms_handle_power_event(u32 event_type, void *usr);
  107. bool sde_is_custom_client(void)
  108. {
  109. return sdecustom;
  110. }
  111. #if IS_ENABLED(CONFIG_DEBUG_FS)
  112. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  113. {
  114. struct msm_drm_private *priv;
  115. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  116. return NULL;
  117. priv = sde_kms->dev->dev_private;
  118. return priv->debug_root;
  119. }
  120. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  121. {
  122. void *p;
  123. int rc;
  124. void *debugfs_root;
  125. p = sde_hw_util_get_log_mask_ptr();
  126. if (!sde_kms || !p)
  127. return -EINVAL;
  128. debugfs_root = sde_debugfs_get_root(sde_kms);
  129. if (!debugfs_root)
  130. return -EINVAL;
  131. /* allow debugfs_root to be NULL */
  132. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  133. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  134. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  135. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  136. if (rc) {
  137. SDE_ERROR("failed to init perf %d\n", rc);
  138. return rc;
  139. }
  140. sde_rm_debugfs_init(&sde_kms->rm, debugfs_root);
  141. if (sde_kms->catalog->qdss_count)
  142. debugfs_create_u32("qdss", 0600, debugfs_root,
  143. (u32 *)&sde_kms->qdss_enabled);
  144. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  145. (u32 *)&sde_kms->pm_suspend_clk_dump);
  146. return 0;
  147. }
  148. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  149. {
  150. struct sde_kms *sde_kms = to_sde_kms(kms);
  151. /* don't need to NULL check debugfs_root */
  152. if (sde_kms) {
  153. sde_debugfs_vbif_destroy(sde_kms);
  154. sde_debugfs_core_irq_destroy(sde_kms);
  155. }
  156. }
  157. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  158. {
  159. int i;
  160. struct device *dev = sde_kms->dev->dev;
  161. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  162. for (i = 0; i < sde_kms->dsi_display_count; i++)
  163. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  164. return 0;
  165. }
  166. #else
  167. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  168. {
  169. return 0;
  170. }
  171. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  172. {
  173. }
  174. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  175. {
  176. return 0;
  177. }
  178. #endif /* CONFIG_DEBUG_FS */
  179. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  180. struct drm_crtc *crtc)
  181. {
  182. struct drm_encoder *encoder;
  183. struct drm_device *dev;
  184. int ret;
  185. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  186. SDE_ERROR("invalid params\n");
  187. return;
  188. }
  189. if (!crtc->state->enable) {
  190. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  191. return;
  192. }
  193. if (!crtc->state->active) {
  194. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  195. return;
  196. }
  197. dev = crtc->dev;
  198. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  199. if (encoder->crtc != crtc)
  200. continue;
  201. /*
  202. * Video Mode - Wait for VSYNC
  203. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  204. * complete
  205. */
  206. SDE_EVT32_VERBOSE(DRMID(crtc));
  207. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  208. if (ret && ret != -EWOULDBLOCK) {
  209. SDE_ERROR(
  210. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  211. crtc->base.id, encoder->base.id, ret);
  212. break;
  213. }
  214. }
  215. }
  216. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  217. struct drm_crtc *crtc, bool enable)
  218. {
  219. struct drm_device *dev;
  220. struct msm_drm_private *priv;
  221. struct sde_mdss_cfg *sde_cfg;
  222. struct drm_plane *plane;
  223. int i, ret;
  224. dev = sde_kms->dev;
  225. priv = dev->dev_private;
  226. sde_cfg = sde_kms->catalog;
  227. ret = sde_vbif_halt_xin_mask(sde_kms,
  228. sde_cfg->sui_block_xin_mask, enable);
  229. if (ret) {
  230. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  231. return ret;
  232. }
  233. if (enable) {
  234. for (i = 0; i < priv->num_planes; i++) {
  235. plane = priv->planes[i];
  236. sde_plane_secure_ctrl_xin_client(plane, crtc);
  237. }
  238. }
  239. return 0;
  240. }
  241. /**
  242. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  243. * @sde_kms: Pointer to sde_kms struct
  244. * @vimd: switch the stage 2 translation to this VMID
  245. */
  246. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  247. {
  248. struct device dummy = {};
  249. dma_addr_t dma_handle;
  250. uint32_t num_sids;
  251. uint32_t *sec_sid;
  252. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  253. int ret = 0, i;
  254. struct qtee_shm shm;
  255. bool qtee_en = qtee_shmbridge_is_enabled();
  256. phys_addr_t mem_addr;
  257. u64 mem_size;
  258. num_sids = sde_cfg->sec_sid_mask_count;
  259. if (!num_sids) {
  260. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  261. return -EINVAL;
  262. }
  263. if (qtee_en) {
  264. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  265. &shm);
  266. if (ret)
  267. return -ENOMEM;
  268. sec_sid = (uint32_t *) shm.vaddr;
  269. mem_addr = shm.paddr;
  270. /**
  271. * SMMUSecureModeSwitch requires the size to be number of SID's
  272. * but shm allocates size in pages. Modify the args as per
  273. * client requirement.
  274. */
  275. mem_size = sizeof(uint32_t) * num_sids;
  276. } else {
  277. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  278. if (!sec_sid)
  279. return -ENOMEM;
  280. mem_addr = virt_to_phys(sec_sid);
  281. mem_size = sizeof(uint32_t) * num_sids;
  282. }
  283. for (i = 0; i < num_sids; i++) {
  284. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  285. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  286. }
  287. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  288. if (ret) {
  289. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  290. goto map_error;
  291. }
  292. set_dma_ops(&dummy, NULL);
  293. dma_handle = dma_map_single(&dummy, sec_sid,
  294. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  295. if (dma_mapping_error(&dummy, dma_handle)) {
  296. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  297. vmid);
  298. goto map_error;
  299. }
  300. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  301. vmid, num_sids, qtee_en);
  302. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  303. mem_size, vmid);
  304. if (ret)
  305. SDE_ERROR("Error:scm_call2, vmid %d, ret%d\n",
  306. vmid, ret);
  307. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  308. vmid, qtee_en, num_sids, ret);
  309. dma_unmap_single(&dummy, dma_handle,
  310. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  311. map_error:
  312. if (qtee_en)
  313. qtee_shmbridge_free_shm(&shm);
  314. else
  315. kfree(sec_sid);
  316. return ret;
  317. }
  318. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  319. {
  320. u32 ret;
  321. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  322. return 0;
  323. /* detach_all_contexts */
  324. ret = sde_kms_mmu_detach(sde_kms, false);
  325. if (ret) {
  326. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  327. goto mmu_error;
  328. }
  329. ret = _sde_kms_scm_call(sde_kms, vmid);
  330. if (ret) {
  331. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  332. goto scm_error;
  333. }
  334. return 0;
  335. scm_error:
  336. sde_kms_mmu_attach(sde_kms, false);
  337. mmu_error:
  338. atomic_dec(&sde_kms->detach_all_cb);
  339. return ret;
  340. }
  341. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  342. u32 old_vmid)
  343. {
  344. u32 ret;
  345. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  346. return 0;
  347. ret = _sde_kms_scm_call(sde_kms, vmid);
  348. if (ret) {
  349. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  350. goto scm_error;
  351. }
  352. /* attach_all_contexts */
  353. ret = sde_kms_mmu_attach(sde_kms, false);
  354. if (ret) {
  355. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  356. goto mmu_error;
  357. }
  358. return 0;
  359. mmu_error:
  360. _sde_kms_scm_call(sde_kms, old_vmid);
  361. scm_error:
  362. atomic_inc(&sde_kms->detach_all_cb);
  363. return ret;
  364. }
  365. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  366. {
  367. u32 ret;
  368. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  369. return 0;
  370. /* detach secure_context */
  371. ret = sde_kms_mmu_detach(sde_kms, true);
  372. if (ret) {
  373. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  374. goto mmu_error;
  375. }
  376. ret = _sde_kms_scm_call(sde_kms, vmid);
  377. if (ret) {
  378. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  379. goto scm_error;
  380. }
  381. return 0;
  382. scm_error:
  383. sde_kms_mmu_attach(sde_kms, true);
  384. mmu_error:
  385. atomic_dec(&sde_kms->detach_sec_cb);
  386. return ret;
  387. }
  388. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  389. u32 old_vmid)
  390. {
  391. u32 ret;
  392. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  393. return 0;
  394. ret = _sde_kms_scm_call(sde_kms, vmid);
  395. if (ret) {
  396. goto scm_error;
  397. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  398. }
  399. ret = sde_kms_mmu_attach(sde_kms, true);
  400. if (ret) {
  401. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  402. goto mmu_error;
  403. }
  404. return 0;
  405. mmu_error:
  406. _sde_kms_scm_call(sde_kms, old_vmid);
  407. scm_error:
  408. atomic_inc(&sde_kms->detach_sec_cb);
  409. return ret;
  410. }
  411. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  412. struct drm_crtc *crtc, bool enable)
  413. {
  414. int ret;
  415. if (enable) {
  416. ret = pm_runtime_resume_and_get(sde_kms->dev->dev);
  417. if (ret < 0) {
  418. SDE_ERROR("failed to enable power resource %d\n", ret);
  419. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  420. return ret;
  421. }
  422. sde_crtc_misr_setup(crtc, true, 1);
  423. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  424. if (ret) {
  425. sde_crtc_misr_setup(crtc, false, 0);
  426. pm_runtime_put_sync(sde_kms->dev->dev);
  427. return ret;
  428. }
  429. } else {
  430. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  431. sde_crtc_misr_setup(crtc, false, 0);
  432. pm_runtime_put_sync(sde_kms->dev->dev);
  433. }
  434. return 0;
  435. }
  436. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  437. bool post_commit)
  438. {
  439. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  440. int old_smmu_state = smmu_state->state;
  441. int ret = 0;
  442. u32 vmid;
  443. if (!sde_kms || !crtc) {
  444. SDE_ERROR("invalid argument(s)\n");
  445. return -EINVAL;
  446. }
  447. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  448. post_commit, smmu_state->sui_misr_state,
  449. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  450. if ((!smmu_state->transition_type) ||
  451. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  452. /* Bail out */
  453. return 0;
  454. /* enable sui misr if requested, before the transition */
  455. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  456. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  457. if (ret) {
  458. smmu_state->sui_misr_state = NONE;
  459. goto end;
  460. }
  461. }
  462. mutex_lock(&sde_kms->secure_transition_lock);
  463. switch (smmu_state->state) {
  464. case DETACH_ALL_REQ:
  465. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  466. if (!ret)
  467. smmu_state->state = DETACHED;
  468. break;
  469. case ATTACH_ALL_REQ:
  470. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  471. VMID_CP_SEC_DISPLAY);
  472. if (!ret) {
  473. smmu_state->state = ATTACHED;
  474. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  475. }
  476. break;
  477. case DETACH_SEC_REQ:
  478. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  479. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  480. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  481. if (!ret)
  482. smmu_state->state = DETACHED_SEC;
  483. break;
  484. case ATTACH_SEC_REQ:
  485. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  486. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  487. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  488. if (!ret) {
  489. smmu_state->state = ATTACHED;
  490. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  491. }
  492. break;
  493. default:
  494. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  495. DRMID(crtc), smmu_state->state,
  496. smmu_state->transition_type);
  497. ret = -EINVAL;
  498. break;
  499. }
  500. mutex_unlock(&sde_kms->secure_transition_lock);
  501. /* disable sui misr if requested, after the transition */
  502. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  503. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  504. if (ret)
  505. goto end;
  506. }
  507. end:
  508. smmu_state->transition_error = false;
  509. if (ret) {
  510. smmu_state->transition_error = true;
  511. SDE_ERROR(
  512. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  513. DRMID(crtc), old_smmu_state, smmu_state->state,
  514. smmu_state->secure_level, ret);
  515. smmu_state->state = smmu_state->prev_state;
  516. smmu_state->secure_level = smmu_state->prev_secure_level;
  517. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  518. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  519. }
  520. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  521. DRMID(crtc), old_smmu_state, smmu_state->state,
  522. smmu_state->secure_level, ret);
  523. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  524. smmu_state->transition_type,
  525. smmu_state->transition_error,
  526. smmu_state->secure_level, smmu_state->prev_secure_level,
  527. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  528. smmu_state->sui_misr_state = NONE;
  529. smmu_state->transition_type = NONE;
  530. return ret;
  531. }
  532. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  533. struct drm_atomic_state *state)
  534. {
  535. struct drm_crtc *crtc;
  536. struct drm_crtc_state *old_crtc_state;
  537. struct drm_plane_state *old_plane_state, *new_plane_state;
  538. struct drm_plane *plane;
  539. struct drm_plane_state *plane_state;
  540. struct sde_kms *sde_kms = to_sde_kms(kms);
  541. struct drm_device *dev = sde_kms->dev;
  542. int i, ops = 0, ret = 0;
  543. bool old_valid_fb = false;
  544. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  545. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  546. if (!crtc->state || !crtc->state->active)
  547. continue;
  548. /*
  549. * It is safe to assume only one active crtc,
  550. * and compatible translation modes on the
  551. * planes staged on this crtc.
  552. * otherwise validation would have failed.
  553. * For this CRTC,
  554. */
  555. /*
  556. * 1. Check if old state on the CRTC has planes
  557. * staged with valid fbs
  558. */
  559. for_each_old_plane_in_state(state, plane, plane_state, i) {
  560. if (!plane_state->crtc)
  561. continue;
  562. if (plane_state->fb) {
  563. old_valid_fb = true;
  564. break;
  565. }
  566. }
  567. /*
  568. * 2.Get the operations needed to be performed before
  569. * secure transition can be initiated.
  570. */
  571. ops = sde_crtc_get_secure_transition_ops(crtc,
  572. old_crtc_state, old_valid_fb);
  573. if (ops < 0) {
  574. SDE_ERROR("invalid secure operations %x\n", ops);
  575. return ops;
  576. }
  577. if (!ops) {
  578. smmu_state->transition_error = false;
  579. goto no_ops;
  580. }
  581. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  582. crtc->base.id, ops, crtc->state);
  583. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  584. /* 3. Perform operations needed for secure transition */
  585. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  586. SDE_DEBUG("wait_for_transfer_done\n");
  587. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  588. }
  589. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  590. SDE_DEBUG("cleanup planes\n");
  591. drm_atomic_helper_cleanup_planes(dev, state);
  592. for_each_oldnew_plane_in_state(state, plane,
  593. old_plane_state, new_plane_state, i)
  594. sde_plane_destroy_fb(old_plane_state);
  595. }
  596. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  597. SDE_DEBUG("secure ctrl\n");
  598. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  599. }
  600. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  601. SDE_DEBUG("prepare planes %d",
  602. crtc->state->plane_mask);
  603. drm_atomic_crtc_for_each_plane(plane,
  604. crtc) {
  605. const struct drm_plane_helper_funcs *funcs;
  606. plane_state = plane->state;
  607. funcs = plane->helper_private;
  608. SDE_DEBUG("psde:%d FB[%u]\n",
  609. plane->base.id,
  610. plane->fb->base.id);
  611. if (!funcs)
  612. continue;
  613. if (funcs->prepare_fb(plane, plane_state)) {
  614. ret = funcs->prepare_fb(plane,
  615. plane_state);
  616. if (ret)
  617. return ret;
  618. }
  619. }
  620. }
  621. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  622. SDE_DEBUG("secure operations completed\n");
  623. }
  624. no_ops:
  625. return 0;
  626. }
  627. static int _sde_kms_release_shared_buffer(unsigned int mem_addr,
  628. unsigned int splash_buffer_size,
  629. unsigned int ramdump_base,
  630. unsigned int ramdump_buffer_size)
  631. {
  632. unsigned long pfn_start, pfn_end, pfn_idx;
  633. int ret = 0;
  634. if (!mem_addr || !splash_buffer_size) {
  635. SDE_ERROR("invalid params\n");
  636. return -EINVAL;
  637. }
  638. /* leave ramdump memory only if base address matches */
  639. if (ramdump_base == mem_addr &&
  640. ramdump_buffer_size <= splash_buffer_size) {
  641. mem_addr += ramdump_buffer_size;
  642. splash_buffer_size -= ramdump_buffer_size;
  643. }
  644. pfn_start = mem_addr >> PAGE_SHIFT;
  645. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  646. ret = memblock_free(mem_addr, splash_buffer_size);
  647. if (ret) {
  648. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  649. return ret;
  650. }
  651. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  652. free_reserved_page(pfn_to_page(pfn_idx));
  653. return ret;
  654. }
  655. static int _sde_kms_one2one_mem_map_ipcc_reg(struct sde_kms *sde_kms, u32 buf_size,
  656. unsigned long buf_base)
  657. {
  658. struct msm_mmu *mmu = NULL;
  659. int ret = 0;
  660. if (!sde_kms->aspace[MSM_SMMU_DOMAIN_UNSECURE]
  661. || !sde_kms->aspace[MSM_SMMU_DOMAIN_UNSECURE]->mmu) {
  662. SDE_ERROR("aspace not found for sde kms node\n");
  663. return -EINVAL;
  664. }
  665. mmu = sde_kms->aspace[MSM_SMMU_DOMAIN_UNSECURE]->mmu;
  666. if (!mmu) {
  667. SDE_ERROR("mmu not found for aspace\n");
  668. return -EINVAL;
  669. }
  670. if (!mmu->funcs || !mmu->funcs->one_to_one_map) {
  671. SDE_ERROR("invalid input params for map\n");
  672. return -EINVAL;
  673. }
  674. ret = mmu->funcs->one_to_one_map(mmu, buf_base, buf_base, buf_size,
  675. IOMMU_READ | IOMMU_WRITE);
  676. if (ret)
  677. SDE_ERROR("one2one memory smmu map failed:%d\n", ret);
  678. return ret;
  679. }
  680. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  681. struct sde_splash_mem *splash)
  682. {
  683. struct msm_mmu *mmu = NULL;
  684. int ret = 0;
  685. if (!sde_kms->aspace[0]) {
  686. SDE_ERROR("aspace not found for sde kms node\n");
  687. return -EINVAL;
  688. }
  689. mmu = sde_kms->aspace[0]->mmu;
  690. if (!mmu) {
  691. SDE_ERROR("mmu not found for aspace\n");
  692. return -EINVAL;
  693. }
  694. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  695. SDE_ERROR("invalid input params for map\n");
  696. return -EINVAL;
  697. }
  698. if (!splash->ref_cnt) {
  699. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  700. splash->splash_buf_base,
  701. splash->splash_buf_size,
  702. IOMMU_READ | IOMMU_NOEXEC);
  703. if (ret)
  704. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  705. }
  706. splash->ref_cnt++;
  707. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  708. splash->splash_buf_base,
  709. splash->splash_buf_size,
  710. splash->ref_cnt);
  711. return ret;
  712. }
  713. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  714. {
  715. int i = 0;
  716. int ret = 0;
  717. struct sde_splash_mem *region;
  718. if (!sde_kms)
  719. return -EINVAL;
  720. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  721. region = sde_kms->splash_data.splash_display[i].splash;
  722. ret = _sde_kms_splash_mem_get(sde_kms, region);
  723. if (ret)
  724. return ret;
  725. /* Demura is optional and need not exist */
  726. region = sde_kms->splash_data.splash_display[i].demura;
  727. if (region) {
  728. ret = _sde_kms_splash_mem_get(sde_kms, region);
  729. if (ret)
  730. return ret;
  731. }
  732. }
  733. return ret;
  734. }
  735. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  736. struct sde_splash_mem *splash)
  737. {
  738. struct msm_mmu *mmu = NULL;
  739. int rc = 0;
  740. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  741. SDE_ERROR("invalid params\n");
  742. return -EINVAL;
  743. }
  744. mmu = sde_kms->aspace[0]->mmu;
  745. if (!splash || !splash->ref_cnt ||
  746. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  747. return -EINVAL;
  748. splash->ref_cnt--;
  749. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  750. splash->splash_buf_base, splash->ref_cnt);
  751. if (!splash->ref_cnt) {
  752. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  753. splash->splash_buf_size);
  754. rc = _sde_kms_release_shared_buffer(splash->splash_buf_base,
  755. splash->splash_buf_size, splash->ramdump_base,
  756. splash->ramdump_size);
  757. splash->splash_buf_base = 0;
  758. splash->splash_buf_size = 0;
  759. }
  760. return rc;
  761. }
  762. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  763. {
  764. int i = 0;
  765. int ret = 0, failure = 0;
  766. struct sde_splash_mem *region;
  767. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  768. return -EINVAL;
  769. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  770. region = sde_kms->splash_data.splash_display[i].splash;
  771. ret = _sde_kms_splash_mem_put(sde_kms, region);
  772. if (ret) {
  773. failure = 1;
  774. pr_err("Error unmapping splash mem for display %d\n",
  775. i);
  776. }
  777. /* Demura is optional and need not exist */
  778. region = sde_kms->splash_data.splash_display[i].demura;
  779. if (region) {
  780. ret = _sde_kms_splash_mem_put(sde_kms, region);
  781. if (ret) {
  782. failure = 1;
  783. pr_err("Error unmapping demura mem for display %d\n",
  784. i);
  785. }
  786. }
  787. }
  788. if (failure)
  789. ret = -EINVAL;
  790. return ret;
  791. }
  792. static int _sde_kms_get_blank(struct drm_crtc_state *crtc_state,
  793. struct drm_connector_state *conn_state)
  794. {
  795. int lp_mode, blank;
  796. if (crtc_state->active)
  797. lp_mode = sde_connector_get_property(conn_state,
  798. CONNECTOR_PROP_LP);
  799. else
  800. lp_mode = SDE_MODE_DPMS_OFF;
  801. switch (lp_mode) {
  802. case SDE_MODE_DPMS_ON:
  803. blank = DRM_PANEL_EVENT_UNBLANK;
  804. break;
  805. case SDE_MODE_DPMS_LP1:
  806. case SDE_MODE_DPMS_LP2:
  807. blank = DRM_PANEL_EVENT_BLANK_LP;
  808. break;
  809. case SDE_MODE_DPMS_OFF:
  810. default:
  811. blank = DRM_PANEL_EVENT_BLANK;
  812. break;
  813. }
  814. return blank;
  815. }
  816. static void _sde_kms_drm_check_dpms(struct drm_atomic_state *old_state,
  817. bool is_pre_commit)
  818. {
  819. struct panel_event_notification notification;
  820. struct drm_connector *connector;
  821. struct drm_connector_state *old_conn_state;
  822. struct drm_crtc_state *old_crtc_state;
  823. struct drm_crtc *crtc;
  824. struct sde_connector *c_conn;
  825. int i, old_mode, new_mode, old_fps, new_fps;
  826. enum panel_event_notifier_tag panel_type;
  827. for_each_old_connector_in_state(old_state, connector,
  828. old_conn_state, i) {
  829. crtc = connector->state->crtc ? connector->state->crtc :
  830. old_conn_state->crtc;
  831. if (!crtc)
  832. continue;
  833. new_fps = drm_mode_vrefresh(&crtc->state->mode);
  834. new_mode = _sde_kms_get_blank(crtc->state, connector->state);
  835. if (old_conn_state->crtc) {
  836. old_crtc_state = drm_atomic_get_existing_crtc_state(
  837. old_state, old_conn_state->crtc);
  838. old_fps = drm_mode_vrefresh(&old_crtc_state->mode);
  839. old_mode = _sde_kms_get_blank(old_crtc_state,
  840. old_conn_state);
  841. } else {
  842. old_fps = 0;
  843. old_mode = DRM_PANEL_EVENT_BLANK;
  844. }
  845. if ((old_mode != new_mode) || (old_fps != new_fps)) {
  846. c_conn = to_sde_connector(connector);
  847. SDE_EVT32(old_mode, new_mode, old_fps, new_fps,
  848. c_conn->panel, crtc->state->active,
  849. old_conn_state->crtc);
  850. pr_debug("change detected for connector:%s (power mode %d->%d, fps %d->%d)\n",
  851. c_conn->name, old_mode, new_mode, old_fps, new_fps);
  852. /* If suspend resume and fps change are happening
  853. * at the same time, give preference to power mode
  854. * changes rather than fps change.
  855. */
  856. if ((old_mode == new_mode) && (old_fps != new_fps))
  857. new_mode = DRM_PANEL_EVENT_FPS_CHANGE;
  858. if (!c_conn->panel)
  859. continue;
  860. panel_type = sde_encoder_is_primary_display(
  861. connector->encoder) ?
  862. PANEL_EVENT_NOTIFICATION_PRIMARY :
  863. PANEL_EVENT_NOTIFICATION_SECONDARY;
  864. notification.notif_type = new_mode;
  865. notification.panel = c_conn->panel;
  866. notification.notif_data.old_fps = old_fps;
  867. notification.notif_data.new_fps = new_fps;
  868. notification.notif_data.early_trigger = is_pre_commit;
  869. panel_event_notification_trigger(panel_type,
  870. &notification);
  871. }
  872. }
  873. }
  874. static struct drm_crtc *sde_kms_vm_get_vm_crtc(
  875. struct drm_atomic_state *state)
  876. {
  877. int i;
  878. enum sde_crtc_vm_req vm_req = VM_REQ_NONE;
  879. struct drm_crtc *crtc, *vm_crtc = NULL;
  880. struct drm_crtc_state *new_cstate, *old_cstate;
  881. struct sde_crtc_state *vm_cstate;
  882. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  883. if (!new_cstate->active && !old_cstate->active)
  884. continue;
  885. vm_cstate = to_sde_crtc_state(new_cstate);
  886. vm_req = sde_crtc_get_property(vm_cstate,
  887. CRTC_PROP_VM_REQ_STATE);
  888. if (vm_req != VM_REQ_NONE) {
  889. SDE_DEBUG("valid vm request:%d found on crtc-%d\n",
  890. vm_req, crtc->base.id);
  891. vm_crtc = crtc;
  892. break;
  893. }
  894. }
  895. return vm_crtc;
  896. }
  897. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  898. struct drm_atomic_state *state)
  899. {
  900. struct drm_device *ddev;
  901. struct drm_crtc *crtc;
  902. struct drm_crtc_state *new_cstate;
  903. struct drm_encoder *encoder;
  904. struct drm_connector *connector;
  905. struct sde_vm_ops *vm_ops;
  906. struct sde_crtc_state *cstate;
  907. struct drm_connector_list_iter iter;
  908. enum sde_crtc_vm_req vm_req;
  909. int rc = 0;
  910. ddev = sde_kms->dev;
  911. vm_ops = sde_vm_get_ops(sde_kms);
  912. if (!vm_ops)
  913. return -EINVAL;
  914. crtc = sde_kms_vm_get_vm_crtc(state);
  915. if (!crtc)
  916. return 0;
  917. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  918. cstate = to_sde_crtc_state(new_cstate);
  919. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  920. if (vm_req != VM_REQ_ACQUIRE)
  921. return 0;
  922. /* enable MDSS irq line */
  923. sde_irq_update(&sde_kms->base, true);
  924. /* clear the stale IRQ status bits */
  925. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  926. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  927. /* enable the display path IRQ's */
  928. drm_for_each_encoder_mask(encoder, crtc->dev,
  929. crtc->state->encoder_mask) {
  930. if (sde_encoder_in_clone_mode(encoder))
  931. continue;
  932. sde_encoder_irq_control(encoder, true);
  933. }
  934. /* Schedule ESD work */
  935. drm_connector_list_iter_begin(ddev, &iter);
  936. drm_for_each_connector_iter(connector, &iter)
  937. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  938. sde_connector_schedule_status_work(connector, true);
  939. drm_connector_list_iter_end(&iter);
  940. /* enable vblank events */
  941. drm_crtc_vblank_on(crtc);
  942. sde_dbg_set_hw_ownership_status(true);
  943. /* handle non-SDE pre_acquire */
  944. if (vm_ops->vm_client_post_acquire)
  945. rc = vm_ops->vm_client_post_acquire(sde_kms);
  946. return rc;
  947. }
  948. void sde_kms_vm_set_sid(struct sde_kms *sde_kms, u32 vm)
  949. {
  950. struct drm_plane *plane;
  951. struct drm_device *ddev;
  952. struct sde_mdss_cfg *sde_cfg;
  953. ddev = sde_kms->dev;
  954. sde_cfg = sde_kms->catalog;
  955. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  956. sde_plane_set_sid(plane, vm);
  957. if (sde_kms->hw_sid && sde_kms->hw_sid->ops.set_vm_sid)
  958. sde_kms->hw_sid->ops.set_vm_sid(sde_kms->hw_sid, vm, sde_kms->catalog);
  959. }
  960. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  961. struct drm_atomic_state *state)
  962. {
  963. struct drm_crtc *crtc;
  964. struct drm_crtc_state *new_cstate;
  965. struct sde_crtc_state *cstate;
  966. enum sde_crtc_vm_req vm_req;
  967. crtc = sde_kms_vm_get_vm_crtc(state);
  968. if (!crtc)
  969. return 0;
  970. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  971. cstate = to_sde_crtc_state(new_cstate);
  972. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  973. if (vm_req != VM_REQ_ACQUIRE)
  974. return 0;
  975. /* Clear the stale IRQ status bits */
  976. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  977. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  978. /* Program the SID's for the trusted VM */
  979. sde_kms_vm_set_sid(sde_kms, 1);
  980. sde_dbg_set_hw_ownership_status(true);
  981. return 0;
  982. }
  983. static void sde_kms_prepare_commit(struct msm_kms *kms,
  984. struct drm_atomic_state *state)
  985. {
  986. struct sde_kms *sde_kms;
  987. struct msm_drm_private *priv;
  988. struct drm_device *dev;
  989. struct drm_encoder *encoder;
  990. struct drm_crtc *crtc;
  991. struct drm_crtc_state *cstate;
  992. struct sde_vm_ops *vm_ops;
  993. int i, rc;
  994. if (!kms)
  995. return;
  996. sde_kms = to_sde_kms(kms);
  997. dev = sde_kms->dev;
  998. if (!dev || !dev->dev_private)
  999. return;
  1000. priv = dev->dev_private;
  1001. SDE_ATRACE_BEGIN("prepare_commit");
  1002. rc = pm_runtime_resume_and_get(sde_kms->dev->dev);
  1003. if (rc < 0) {
  1004. SDE_ERROR("failed to enable power resources %d\n", rc);
  1005. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  1006. goto end;
  1007. }
  1008. if (sde_kms->first_kickoff) {
  1009. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  1010. sde_kms->first_kickoff = false;
  1011. }
  1012. for_each_new_crtc_in_state(state, crtc, cstate, i) {
  1013. drm_for_each_encoder_mask(encoder, dev, cstate->encoder_mask) {
  1014. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  1015. SDE_ERROR("crtc:%d, initiating hw reset\n",
  1016. DRMID(crtc));
  1017. sde_encoder_needs_hw_reset(encoder);
  1018. sde_crtc_set_needs_hw_reset(crtc);
  1019. }
  1020. }
  1021. }
  1022. /*
  1023. * NOTE: for secure use cases we want to apply the new HW
  1024. * configuration only after completing preparation for secure
  1025. * transitions prepare below if any transtions is required.
  1026. */
  1027. sde_kms_prepare_secure_transition(kms, state);
  1028. vm_ops = sde_vm_get_ops(sde_kms);
  1029. if (!vm_ops)
  1030. goto end_vm;
  1031. if (vm_ops->vm_prepare_commit)
  1032. vm_ops->vm_prepare_commit(sde_kms, state);
  1033. end_vm:
  1034. _sde_kms_drm_check_dpms(state, true);
  1035. end:
  1036. SDE_ATRACE_END("prepare_commit");
  1037. }
  1038. static void sde_kms_commit(struct msm_kms *kms,
  1039. struct drm_atomic_state *old_state)
  1040. {
  1041. struct sde_kms *sde_kms;
  1042. struct drm_crtc *crtc;
  1043. struct drm_crtc_state *old_crtc_state;
  1044. int i;
  1045. if (!kms || !old_state)
  1046. return;
  1047. sde_kms = to_sde_kms(kms);
  1048. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  1049. SDE_ERROR("power resource is not enabled\n");
  1050. return;
  1051. }
  1052. SDE_ATRACE_BEGIN("sde_kms_commit");
  1053. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1054. if (crtc->state->active) {
  1055. SDE_EVT32(DRMID(crtc), old_state);
  1056. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  1057. }
  1058. }
  1059. SDE_ATRACE_END("sde_kms_commit");
  1060. }
  1061. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  1062. struct sde_splash_display *splash_display)
  1063. {
  1064. if (!sde_kms || !splash_display ||
  1065. !sde_kms->splash_data.num_splash_displays)
  1066. return;
  1067. if (sde_kms->splash_data.num_splash_regions) {
  1068. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  1069. if (splash_display->demura)
  1070. _sde_kms_splash_mem_put(sde_kms,
  1071. splash_display->demura);
  1072. }
  1073. sde_kms->splash_data.num_splash_displays--;
  1074. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  1075. sde_kms->splash_data.num_splash_displays);
  1076. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  1077. }
  1078. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  1079. struct drm_crtc *crtc)
  1080. {
  1081. struct msm_drm_private *priv;
  1082. struct sde_splash_display *splash_display;
  1083. int i;
  1084. if (!sde_kms || !crtc)
  1085. return;
  1086. priv = sde_kms->dev->dev_private;
  1087. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  1088. return;
  1089. SDE_EVT32(DRMID(crtc), crtc->state->active,
  1090. sde_kms->splash_data.num_splash_displays);
  1091. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1092. splash_display = &sde_kms->splash_data.splash_display[i];
  1093. if (splash_display->encoder &&
  1094. crtc == splash_display->encoder->crtc)
  1095. break;
  1096. }
  1097. if (i >= MAX_DSI_DISPLAYS)
  1098. return;
  1099. if (splash_display->cont_splash_enabled) {
  1100. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  1101. splash_display, false);
  1102. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  1103. }
  1104. /* remove the votes if all displays are done with splash */
  1105. if (!sde_kms->splash_data.num_splash_displays) {
  1106. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1107. sde_power_data_bus_set_quota(&priv->phandle, i,
  1108. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1109. priv->phandle.ib_quota[i] ? priv->phandle.ib_quota[i] :
  1110. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1111. pm_runtime_put_sync(sde_kms->dev->dev);
  1112. }
  1113. }
  1114. static void sde_kms_cancel_delayed_work(struct drm_crtc *crtc)
  1115. {
  1116. struct drm_connector *connector;
  1117. struct drm_connector_list_iter iter;
  1118. struct drm_encoder *encoder;
  1119. /* Cancel CRTC work */
  1120. sde_crtc_cancel_delayed_work(crtc);
  1121. /* Cancel ESD work */
  1122. drm_connector_list_iter_begin(crtc->dev, &iter);
  1123. drm_for_each_connector_iter(connector, &iter)
  1124. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1125. sde_connector_schedule_status_work(connector, false);
  1126. drm_connector_list_iter_end(&iter);
  1127. /* Cancel Idle-PC work */
  1128. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
  1129. if (sde_encoder_in_clone_mode(encoder))
  1130. continue;
  1131. sde_encoder_cancel_delayed_work(encoder);
  1132. }
  1133. }
  1134. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1135. struct drm_atomic_state *state, bool is_primary)
  1136. {
  1137. struct drm_crtc *crtc;
  1138. struct drm_encoder *encoder;
  1139. int rc = 0;
  1140. crtc = sde_kms_vm_get_vm_crtc(state);
  1141. if (!crtc)
  1142. return 0;
  1143. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1144. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1145. sde_dbg_set_hw_ownership_status(false);
  1146. sde_kms_cancel_delayed_work(crtc);
  1147. /* disable SDE encoder irq's */
  1148. drm_for_each_encoder_mask(encoder, crtc->dev,
  1149. crtc->state->encoder_mask) {
  1150. if (sde_encoder_in_clone_mode(encoder))
  1151. continue;
  1152. sde_encoder_irq_control(encoder, false);
  1153. }
  1154. if (is_primary) {
  1155. /* disable vblank events */
  1156. drm_crtc_vblank_off(crtc);
  1157. /* reset sw state */
  1158. sde_crtc_reset_sw_state(crtc);
  1159. }
  1160. return rc;
  1161. }
  1162. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1163. struct drm_atomic_state *state)
  1164. {
  1165. struct sde_vm_ops *vm_ops;
  1166. struct drm_crtc *crtc;
  1167. struct sde_crtc_state *cstate;
  1168. struct drm_crtc_state *new_cstate;
  1169. enum sde_crtc_vm_req vm_req;
  1170. int rc = 0;
  1171. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1172. return -EINVAL;
  1173. vm_ops = sde_vm_get_ops(sde_kms);
  1174. crtc = sde_kms_vm_get_vm_crtc(state);
  1175. if (!crtc)
  1176. return 0;
  1177. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1178. cstate = to_sde_crtc_state(new_cstate);
  1179. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1180. if (vm_req != VM_REQ_RELEASE)
  1181. return 0;
  1182. sde_kms_vm_pre_release(sde_kms, state, false);
  1183. sde_kms_vm_set_sid(sde_kms, 0);
  1184. sde_vm_lock(sde_kms);
  1185. if (vm_ops->vm_release)
  1186. rc = vm_ops->vm_release(sde_kms);
  1187. sde_vm_unlock(sde_kms);
  1188. return rc;
  1189. }
  1190. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1191. struct drm_atomic_state *state)
  1192. {
  1193. struct sde_vm_ops *vm_ops;
  1194. struct sde_crtc_state *cstate;
  1195. struct drm_crtc *crtc;
  1196. struct drm_crtc_state *new_cstate;
  1197. enum sde_crtc_vm_req vm_req;
  1198. int rc = 0;
  1199. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1200. return -EINVAL;
  1201. vm_ops = sde_vm_get_ops(sde_kms);
  1202. crtc = sde_kms_vm_get_vm_crtc(state);
  1203. if (!crtc)
  1204. return 0;
  1205. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1206. cstate = to_sde_crtc_state(new_cstate);
  1207. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1208. if (vm_req != VM_REQ_RELEASE)
  1209. return 0;
  1210. /* handle SDE pre-release */
  1211. rc = sde_kms_vm_pre_release(sde_kms, state, true);
  1212. if (rc) {
  1213. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1214. goto exit;
  1215. }
  1216. /* properly handoff color processing features */
  1217. sde_cp_crtc_vm_primary_handoff(crtc);
  1218. sde_vm_lock(sde_kms);
  1219. /* handle non-SDE clients pre-release */
  1220. if (vm_ops->vm_client_pre_release) {
  1221. rc = vm_ops->vm_client_pre_release(sde_kms);
  1222. if (rc) {
  1223. SDE_ERROR("sde vm client pre_release failed, rc=%d\n",
  1224. rc);
  1225. sde_vm_unlock(sde_kms);
  1226. goto exit;
  1227. }
  1228. }
  1229. /* disable IRQ line */
  1230. sde_irq_update(&sde_kms->base, false);
  1231. /* release HW */
  1232. if (vm_ops->vm_release) {
  1233. rc = vm_ops->vm_release(sde_kms);
  1234. if (rc)
  1235. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1236. }
  1237. sde_vm_unlock(sde_kms);
  1238. _sde_crtc_vm_release_notify(crtc);
  1239. exit:
  1240. return rc;
  1241. }
  1242. static void sde_kms_complete_commit(struct msm_kms *kms,
  1243. struct drm_atomic_state *old_state)
  1244. {
  1245. struct sde_kms *sde_kms;
  1246. struct msm_drm_private *priv;
  1247. struct drm_crtc *crtc;
  1248. struct drm_crtc_state *old_crtc_state;
  1249. struct drm_connector *connector;
  1250. struct drm_connector_state *old_conn_state;
  1251. struct msm_display_conn_params params;
  1252. struct sde_vm_ops *vm_ops;
  1253. int i, rc = 0;
  1254. if (!kms || !old_state)
  1255. return;
  1256. sde_kms = to_sde_kms(kms);
  1257. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1258. return;
  1259. priv = sde_kms->dev->dev_private;
  1260. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  1261. SDE_ERROR("power resource is not enabled\n");
  1262. return;
  1263. }
  1264. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1265. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1266. sde_crtc_complete_commit(crtc, old_crtc_state);
  1267. /* complete secure transitions if any */
  1268. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1269. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1270. }
  1271. for_each_old_connector_in_state(old_state, connector,
  1272. old_conn_state, i) {
  1273. struct sde_connector *c_conn;
  1274. c_conn = to_sde_connector(connector);
  1275. if (!c_conn->ops.post_kickoff)
  1276. continue;
  1277. memset(&params, 0, sizeof(params));
  1278. sde_connector_complete_qsync_commit(connector, &params);
  1279. rc = c_conn->ops.post_kickoff(connector, &params);
  1280. if (rc) {
  1281. pr_err("Connector Post kickoff failed rc=%d\n",
  1282. rc);
  1283. }
  1284. }
  1285. vm_ops = sde_vm_get_ops(sde_kms);
  1286. if (vm_ops && vm_ops->vm_post_commit) {
  1287. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1288. if (rc)
  1289. SDE_ERROR("vm post commit failed, rc = %d\n",
  1290. rc);
  1291. }
  1292. _sde_kms_drm_check_dpms(old_state, false);
  1293. pm_runtime_put_sync(sde_kms->dev->dev);
  1294. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1295. _sde_kms_release_splash_resource(sde_kms, crtc);
  1296. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1297. SDE_ATRACE_END("sde_kms_complete_commit");
  1298. }
  1299. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1300. struct drm_crtc *crtc)
  1301. {
  1302. struct sde_kms *sde_kms;
  1303. struct drm_encoder *encoder;
  1304. struct drm_device *dev;
  1305. int ret;
  1306. bool cwb_disabling;
  1307. if (!kms || !crtc || !crtc->state) {
  1308. SDE_ERROR("invalid params\n");
  1309. return;
  1310. }
  1311. dev = crtc->dev;
  1312. sde_kms = to_sde_kms(kms);
  1313. if (!crtc->state->enable) {
  1314. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1315. return;
  1316. }
  1317. if (!crtc->state->active) {
  1318. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1319. return;
  1320. }
  1321. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1322. SDE_ERROR("power resource is not enabled\n");
  1323. return;
  1324. }
  1325. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1326. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1327. cwb_disabling = false;
  1328. if (encoder->crtc != crtc) {
  1329. cwb_disabling = sde_encoder_is_cwb_disabling(encoder,
  1330. crtc);
  1331. if (!cwb_disabling)
  1332. continue;
  1333. }
  1334. /*
  1335. * Wait for post-flush if necessary to delay before
  1336. * plane_cleanup. For example, wait for vsync in case of video
  1337. * mode panels. This may be a no-op for command mode panels.
  1338. */
  1339. SDE_EVT32_VERBOSE(DRMID(crtc));
  1340. ret = sde_encoder_wait_for_event(encoder, cwb_disabling ?
  1341. MSM_ENC_TX_COMPLETE : MSM_ENC_COMMIT_DONE);
  1342. if (ret && ret != -EWOULDBLOCK) {
  1343. SDE_ERROR("wait for commit done returned %d\n", ret);
  1344. sde_crtc_request_frame_reset(crtc, encoder);
  1345. break;
  1346. }
  1347. sde_crtc_complete_flip(crtc, NULL);
  1348. if (cwb_disabling)
  1349. sde_encoder_virt_reset(encoder);
  1350. }
  1351. /* avoid system cache update to set rd-noalloc bit when NSE feature is enabled */
  1352. if (!test_bit(SDE_FEATURE_SYS_CACHE_NSE, sde_kms->catalog->features))
  1353. sde_crtc_static_cache_read_kickoff(crtc);
  1354. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1355. }
  1356. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1357. struct drm_atomic_state *old_state)
  1358. {
  1359. struct drm_crtc *crtc;
  1360. struct drm_crtc_state *old_crtc_state;
  1361. int i;
  1362. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1363. SDE_ERROR("invalid argument(s)\n");
  1364. return;
  1365. }
  1366. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1367. /* old_state actually contains updated crtc pointers */
  1368. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1369. if (crtc->state->active || crtc->state->active_changed)
  1370. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1371. }
  1372. SDE_ATRACE_END("sde_kms_prepare_fence");
  1373. }
  1374. /**
  1375. * _sde_kms_get_displays - query for underlying display handles and cache them
  1376. * @sde_kms: Pointer to sde kms structure
  1377. * Returns: Zero on success
  1378. */
  1379. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1380. {
  1381. int rc = -ENOMEM;
  1382. if (!sde_kms) {
  1383. SDE_ERROR("invalid sde kms\n");
  1384. return -EINVAL;
  1385. }
  1386. /* dsi */
  1387. sde_kms->dsi_displays = NULL;
  1388. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1389. if (sde_kms->dsi_display_count) {
  1390. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1391. sizeof(void *),
  1392. GFP_KERNEL);
  1393. if (!sde_kms->dsi_displays) {
  1394. SDE_ERROR("failed to allocate dsi displays\n");
  1395. goto exit_deinit_dsi;
  1396. }
  1397. sde_kms->dsi_display_count =
  1398. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1399. sde_kms->dsi_display_count);
  1400. }
  1401. /* wb */
  1402. sde_kms->wb_displays = NULL;
  1403. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1404. if (sde_kms->wb_display_count) {
  1405. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1406. sizeof(void *),
  1407. GFP_KERNEL);
  1408. if (!sde_kms->wb_displays) {
  1409. SDE_ERROR("failed to allocate wb displays\n");
  1410. goto exit_deinit_wb;
  1411. }
  1412. sde_kms->wb_display_count =
  1413. wb_display_get_displays(sde_kms->wb_displays,
  1414. sde_kms->wb_display_count);
  1415. }
  1416. /* dp */
  1417. sde_kms->dp_displays = NULL;
  1418. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1419. if (sde_kms->dp_display_count) {
  1420. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1421. sizeof(void *), GFP_KERNEL);
  1422. if (!sde_kms->dp_displays) {
  1423. SDE_ERROR("failed to allocate dp displays\n");
  1424. goto exit_deinit_dp;
  1425. }
  1426. sde_kms->dp_display_count =
  1427. dp_display_get_displays(sde_kms->dp_displays,
  1428. sde_kms->dp_display_count);
  1429. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1430. }
  1431. return 0;
  1432. exit_deinit_dp:
  1433. kfree(sde_kms->dp_displays);
  1434. sde_kms->dp_stream_count = 0;
  1435. sde_kms->dp_display_count = 0;
  1436. sde_kms->dp_displays = NULL;
  1437. exit_deinit_wb:
  1438. kfree(sde_kms->wb_displays);
  1439. sde_kms->wb_display_count = 0;
  1440. sde_kms->wb_displays = NULL;
  1441. exit_deinit_dsi:
  1442. kfree(sde_kms->dsi_displays);
  1443. sde_kms->dsi_display_count = 0;
  1444. sde_kms->dsi_displays = NULL;
  1445. return rc;
  1446. }
  1447. /**
  1448. * _sde_kms_release_displays - release cache of underlying display handles
  1449. * @sde_kms: Pointer to sde kms structure
  1450. */
  1451. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1452. {
  1453. if (!sde_kms) {
  1454. SDE_ERROR("invalid sde kms\n");
  1455. return;
  1456. }
  1457. kfree(sde_kms->wb_displays);
  1458. sde_kms->wb_displays = NULL;
  1459. sde_kms->wb_display_count = 0;
  1460. kfree(sde_kms->dsi_displays);
  1461. sde_kms->dsi_displays = NULL;
  1462. sde_kms->dsi_display_count = 0;
  1463. }
  1464. /**
  1465. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1466. * for underlying displays
  1467. * @dev: Pointer to drm device structure
  1468. * @priv: Pointer to private drm device data
  1469. * @sde_kms: Pointer to sde kms structure
  1470. * Returns: Zero on success
  1471. */
  1472. static int _sde_kms_setup_displays(struct drm_device *dev,
  1473. struct msm_drm_private *priv,
  1474. struct sde_kms *sde_kms)
  1475. {
  1476. static const struct sde_connector_ops dsi_ops = {
  1477. .set_info_blob = dsi_conn_set_info_blob,
  1478. .detect = dsi_conn_detect,
  1479. .get_modes = dsi_connector_get_modes,
  1480. .pre_destroy = dsi_connector_put_modes,
  1481. .mode_valid = dsi_conn_mode_valid,
  1482. .get_info = dsi_display_get_info,
  1483. .set_backlight = dsi_display_set_backlight,
  1484. .soft_reset = dsi_display_soft_reset,
  1485. .pre_kickoff = dsi_conn_pre_kickoff,
  1486. .clk_ctrl = dsi_display_clk_ctrl,
  1487. .set_power = dsi_display_set_power,
  1488. .get_mode_info = dsi_conn_get_mode_info,
  1489. .get_dst_format = dsi_display_get_dst_format,
  1490. .post_kickoff = dsi_conn_post_kickoff,
  1491. .check_status = dsi_display_check_status,
  1492. .enable_event = dsi_conn_enable_event,
  1493. .cmd_transfer = dsi_display_cmd_transfer,
  1494. .cont_splash_config = dsi_display_cont_splash_config,
  1495. .cont_splash_res_disable = dsi_display_cont_splash_res_disable,
  1496. .get_panel_vfp = dsi_display_get_panel_vfp,
  1497. .get_default_lms = dsi_display_get_default_lms,
  1498. .cmd_receive = dsi_display_cmd_receive,
  1499. .install_properties = NULL,
  1500. .set_allowed_mode_switch = dsi_conn_set_allowed_mode_switch,
  1501. .set_dyn_bit_clk = dsi_conn_set_dyn_bit_clk,
  1502. .get_qsync_min_fps = dsi_conn_get_qsync_min_fps,
  1503. .get_avr_step_req = dsi_display_get_avr_step_req_fps,
  1504. .prepare_commit = dsi_conn_prepare_commit,
  1505. .set_submode_info = dsi_conn_set_submode_blob_info,
  1506. .get_num_lm_from_mode = dsi_conn_get_lm_from_mode,
  1507. .update_transfer_time = dsi_display_update_transfer_time,
  1508. };
  1509. static const struct sde_connector_ops wb_ops = {
  1510. .post_init = sde_wb_connector_post_init,
  1511. .set_info_blob = sde_wb_connector_set_info_blob,
  1512. .detect = sde_wb_connector_detect,
  1513. .get_modes = sde_wb_connector_get_modes,
  1514. .set_property = sde_wb_connector_set_property,
  1515. .get_info = sde_wb_get_info,
  1516. .soft_reset = NULL,
  1517. .get_mode_info = sde_wb_get_mode_info,
  1518. .get_dst_format = NULL,
  1519. .check_status = NULL,
  1520. .cmd_transfer = NULL,
  1521. .cont_splash_config = NULL,
  1522. .cont_splash_res_disable = NULL,
  1523. .get_panel_vfp = NULL,
  1524. .cmd_receive = NULL,
  1525. .install_properties = NULL,
  1526. .set_dyn_bit_clk = NULL,
  1527. .set_allowed_mode_switch = NULL,
  1528. .update_transfer_time = NULL,
  1529. };
  1530. static const struct sde_connector_ops dp_ops = {
  1531. .post_init = dp_connector_post_init,
  1532. .detect = dp_connector_detect,
  1533. .get_modes = dp_connector_get_modes,
  1534. .atomic_check = dp_connector_atomic_check,
  1535. .mode_valid = dp_connector_mode_valid,
  1536. .get_info = dp_connector_get_info,
  1537. .get_mode_info = dp_connector_get_mode_info,
  1538. .post_open = dp_connector_post_open,
  1539. .check_status = NULL,
  1540. .set_colorspace = dp_connector_set_colorspace,
  1541. .config_hdr = dp_connector_config_hdr,
  1542. .cmd_transfer = NULL,
  1543. .cont_splash_config = NULL,
  1544. .cont_splash_res_disable = NULL,
  1545. .get_panel_vfp = NULL,
  1546. .update_pps = dp_connector_update_pps,
  1547. .cmd_receive = NULL,
  1548. .install_properties = dp_connector_install_properties,
  1549. .set_allowed_mode_switch = NULL,
  1550. .set_dyn_bit_clk = NULL,
  1551. .update_transfer_time = NULL,
  1552. };
  1553. struct msm_display_info info;
  1554. struct drm_encoder *encoder;
  1555. void *display, *connector;
  1556. int i, max_encoders;
  1557. int rc = 0;
  1558. u32 dsc_count = 0, mixer_count = 0;
  1559. u32 max_dp_dsc_count, max_dp_mixer_count;
  1560. if (!dev || !priv || !sde_kms) {
  1561. SDE_ERROR("invalid argument(s)\n");
  1562. return -EINVAL;
  1563. }
  1564. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1565. sde_kms->dp_display_count +
  1566. sde_kms->dp_stream_count;
  1567. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1568. max_encoders = ARRAY_SIZE(priv->encoders);
  1569. SDE_ERROR("capping number of displays to %d", max_encoders);
  1570. }
  1571. /* wb */
  1572. for (i = 0; i < sde_kms->wb_display_count &&
  1573. priv->num_encoders < max_encoders; ++i) {
  1574. display = sde_kms->wb_displays[i];
  1575. encoder = NULL;
  1576. memset(&info, 0x0, sizeof(info));
  1577. rc = sde_wb_get_info(NULL, &info, display);
  1578. if (rc) {
  1579. SDE_ERROR("wb get_info %d failed\n", i);
  1580. continue;
  1581. }
  1582. encoder = sde_encoder_init(dev, &info);
  1583. if (IS_ERR_OR_NULL(encoder)) {
  1584. SDE_ERROR("encoder init failed for wb %d\n", i);
  1585. continue;
  1586. }
  1587. rc = sde_wb_drm_init(display, encoder);
  1588. if (rc) {
  1589. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1590. sde_encoder_destroy(encoder);
  1591. continue;
  1592. }
  1593. connector = sde_connector_init(dev,
  1594. encoder,
  1595. 0,
  1596. display,
  1597. &wb_ops,
  1598. DRM_CONNECTOR_POLL_HPD,
  1599. DRM_MODE_CONNECTOR_VIRTUAL);
  1600. if (connector) {
  1601. priv->encoders[priv->num_encoders++] = encoder;
  1602. priv->connectors[priv->num_connectors++] = connector;
  1603. } else {
  1604. SDE_ERROR("wb %d connector init failed\n", i);
  1605. sde_wb_drm_deinit(display);
  1606. sde_encoder_destroy(encoder);
  1607. }
  1608. }
  1609. /* dsi */
  1610. for (i = 0; i < sde_kms->dsi_display_count &&
  1611. priv->num_encoders < max_encoders; ++i) {
  1612. display = sde_kms->dsi_displays[i];
  1613. encoder = NULL;
  1614. memset(&info, 0x0, sizeof(info));
  1615. rc = dsi_display_get_info(NULL, &info, display);
  1616. if (rc) {
  1617. SDE_ERROR("dsi get_info %d failed\n", i);
  1618. continue;
  1619. }
  1620. encoder = sde_encoder_init(dev, &info);
  1621. if (IS_ERR_OR_NULL(encoder)) {
  1622. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1623. continue;
  1624. }
  1625. rc = dsi_display_drm_bridge_init(display, encoder);
  1626. if (rc) {
  1627. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1628. sde_encoder_destroy(encoder);
  1629. continue;
  1630. }
  1631. connector = sde_connector_init(dev,
  1632. encoder,
  1633. dsi_display_get_drm_panel(display),
  1634. display,
  1635. &dsi_ops,
  1636. DRM_CONNECTOR_POLL_HPD,
  1637. DRM_MODE_CONNECTOR_DSI);
  1638. if (connector) {
  1639. priv->encoders[priv->num_encoders++] = encoder;
  1640. priv->connectors[priv->num_connectors++] = connector;
  1641. } else {
  1642. SDE_ERROR("dsi %d connector init failed\n", i);
  1643. dsi_display_drm_bridge_deinit(display);
  1644. sde_encoder_destroy(encoder);
  1645. continue;
  1646. }
  1647. rc = dsi_display_drm_ext_bridge_init(display,
  1648. encoder, connector);
  1649. if (rc) {
  1650. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1651. dsi_display_drm_bridge_deinit(display);
  1652. sde_connector_destroy(connector);
  1653. sde_encoder_destroy(encoder);
  1654. }
  1655. dsc_count += info.dsc_count;
  1656. mixer_count += info.lm_count;
  1657. if (dsi_display_has_dsc_switch_support(display))
  1658. sde_kms->dsc_switch_support = true;
  1659. }
  1660. if (sde_kms->catalog->allowed_dsc_reservation_switch &&
  1661. !sde_kms->dsc_switch_support) {
  1662. SDE_DEBUG("dsc switch not supported\n");
  1663. sde_kms->catalog->allowed_dsc_reservation_switch = 0;
  1664. }
  1665. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1666. sde_kms->catalog->mixer_count - mixer_count : 0;
  1667. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1668. sde_kms->catalog->dsc_count - dsc_count : 0;
  1669. if (sde_kms->catalog->allowed_dsc_reservation_switch &
  1670. SDE_DP_DSC_RESERVATION_SWITCH)
  1671. max_dp_dsc_count = sde_kms->catalog->dsc_count;
  1672. /* dp */
  1673. for (i = 0; i < sde_kms->dp_display_count &&
  1674. priv->num_encoders < max_encoders; ++i) {
  1675. int idx;
  1676. display = sde_kms->dp_displays[i];
  1677. encoder = NULL;
  1678. memset(&info, 0x0, sizeof(info));
  1679. rc = dp_connector_get_info(NULL, &info, display);
  1680. if (rc) {
  1681. SDE_ERROR("dp get_info %d failed\n", i);
  1682. continue;
  1683. }
  1684. encoder = sde_encoder_init(dev, &info);
  1685. if (IS_ERR_OR_NULL(encoder)) {
  1686. SDE_ERROR("dp encoder init failed %d\n", i);
  1687. continue;
  1688. }
  1689. rc = dp_drm_bridge_init(display, encoder,
  1690. max_dp_mixer_count, max_dp_dsc_count);
  1691. if (rc) {
  1692. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1693. sde_encoder_destroy(encoder);
  1694. continue;
  1695. }
  1696. connector = sde_connector_init(dev,
  1697. encoder,
  1698. NULL,
  1699. display,
  1700. &dp_ops,
  1701. DRM_CONNECTOR_POLL_HPD,
  1702. DRM_MODE_CONNECTOR_DisplayPort);
  1703. if (connector) {
  1704. priv->encoders[priv->num_encoders++] = encoder;
  1705. priv->connectors[priv->num_connectors++] = connector;
  1706. } else {
  1707. SDE_ERROR("dp %d connector init failed\n", i);
  1708. dp_drm_bridge_deinit(display);
  1709. sde_encoder_destroy(encoder);
  1710. }
  1711. /* update display cap to MST_MODE for DP MST encoders */
  1712. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1713. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1714. priv->num_encoders < max_encoders; idx++) {
  1715. info.h_tile_instance[0] = idx;
  1716. encoder = sde_encoder_init(dev, &info);
  1717. if (IS_ERR_OR_NULL(encoder)) {
  1718. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1719. continue;
  1720. }
  1721. rc = dp_mst_drm_bridge_init(display, encoder);
  1722. if (rc) {
  1723. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1724. i, rc);
  1725. sde_encoder_destroy(encoder);
  1726. continue;
  1727. }
  1728. priv->encoders[priv->num_encoders++] = encoder;
  1729. }
  1730. }
  1731. return 0;
  1732. }
  1733. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1734. {
  1735. struct msm_drm_private *priv;
  1736. int i;
  1737. if (!sde_kms) {
  1738. SDE_ERROR("invalid sde_kms\n");
  1739. return;
  1740. } else if (!sde_kms->dev) {
  1741. SDE_ERROR("invalid dev\n");
  1742. return;
  1743. } else if (!sde_kms->dev->dev_private) {
  1744. SDE_ERROR("invalid dev_private\n");
  1745. return;
  1746. }
  1747. priv = sde_kms->dev->dev_private;
  1748. for (i = 0; i < priv->num_crtcs; i++)
  1749. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1750. priv->num_crtcs = 0;
  1751. for (i = 0; i < priv->num_planes; i++)
  1752. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1753. priv->num_planes = 0;
  1754. for (i = 0; i < priv->num_connectors; i++)
  1755. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1756. priv->num_connectors = 0;
  1757. for (i = 0; i < priv->num_encoders; i++)
  1758. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1759. priv->num_encoders = 0;
  1760. _sde_kms_release_displays(sde_kms);
  1761. }
  1762. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1763. {
  1764. struct drm_device *dev;
  1765. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1766. struct drm_crtc *crtc;
  1767. struct msm_drm_private *priv;
  1768. struct sde_mdss_cfg *catalog;
  1769. int primary_planes_idx = 0, i, ret;
  1770. int max_crtc_count;
  1771. u32 sspp_id[MAX_PLANES];
  1772. u32 master_plane_id[MAX_PLANES];
  1773. u32 num_virt_planes = 0;
  1774. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1775. SDE_ERROR("invalid sde_kms\n");
  1776. return -EINVAL;
  1777. }
  1778. dev = sde_kms->dev;
  1779. priv = dev->dev_private;
  1780. catalog = sde_kms->catalog;
  1781. ret = sde_core_irq_domain_add(sde_kms);
  1782. if (ret)
  1783. goto fail_irq;
  1784. /*
  1785. * Query for underlying display drivers, and create connectors,
  1786. * bridges and encoders for them.
  1787. */
  1788. if (!_sde_kms_get_displays(sde_kms))
  1789. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1790. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1791. /* Create the planes */
  1792. for (i = 0; i < catalog->sspp_count; i++) {
  1793. bool primary = true;
  1794. if (primary_planes_idx >= max_crtc_count)
  1795. primary = false;
  1796. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1797. (1UL << max_crtc_count) - 1, 0);
  1798. if (IS_ERR(plane)) {
  1799. SDE_ERROR("sde_plane_init failed\n");
  1800. ret = PTR_ERR(plane);
  1801. goto fail;
  1802. }
  1803. priv->planes[priv->num_planes++] = plane;
  1804. if (primary)
  1805. primary_planes[primary_planes_idx++] = plane;
  1806. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1807. sde_is_custom_client()) {
  1808. int priority =
  1809. catalog->sspp[i].sblk->smart_dma_priority;
  1810. sspp_id[priority - 1] = catalog->sspp[i].id;
  1811. master_plane_id[priority - 1] = plane->base.id;
  1812. num_virt_planes++;
  1813. }
  1814. }
  1815. /* Initialize smart DMA virtual planes */
  1816. for (i = 0; i < num_virt_planes; i++) {
  1817. plane = sde_plane_init(dev, sspp_id[i], false,
  1818. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1819. if (IS_ERR(plane)) {
  1820. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1821. ret = PTR_ERR(plane);
  1822. goto fail;
  1823. }
  1824. priv->planes[priv->num_planes++] = plane;
  1825. }
  1826. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1827. /* Create one CRTC per encoder */
  1828. for (i = 0; i < max_crtc_count; i++) {
  1829. crtc = sde_crtc_init(dev, primary_planes[i]);
  1830. if (IS_ERR(crtc)) {
  1831. ret = PTR_ERR(crtc);
  1832. goto fail;
  1833. }
  1834. priv->crtcs[priv->num_crtcs++] = crtc;
  1835. }
  1836. if (sde_is_custom_client()) {
  1837. /* All CRTCs are compatible with all planes */
  1838. for (i = 0; i < priv->num_planes; i++)
  1839. priv->planes[i]->possible_crtcs =
  1840. (1 << priv->num_crtcs) - 1;
  1841. }
  1842. /* All CRTCs are compatible with all encoders */
  1843. for (i = 0; i < priv->num_encoders; i++)
  1844. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1845. return 0;
  1846. fail:
  1847. _sde_kms_drm_obj_destroy(sde_kms);
  1848. fail_irq:
  1849. sde_core_irq_domain_fini(sde_kms);
  1850. return ret;
  1851. }
  1852. /**
  1853. * sde_kms_timeline_status - provides current timeline status
  1854. * This API should be called without mode config lock.
  1855. * @dev: Pointer to drm device
  1856. */
  1857. void sde_kms_timeline_status(struct drm_device *dev)
  1858. {
  1859. struct drm_crtc *crtc;
  1860. struct drm_connector *conn;
  1861. struct drm_connector_list_iter conn_iter;
  1862. if (!dev) {
  1863. SDE_ERROR("invalid drm device node\n");
  1864. return;
  1865. }
  1866. drm_for_each_crtc(crtc, dev)
  1867. sde_crtc_timeline_status(crtc);
  1868. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1869. /*
  1870. *Probably locked from last close dumping status anyway
  1871. */
  1872. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1873. drm_connector_list_iter_begin(dev, &conn_iter);
  1874. drm_for_each_connector_iter(conn, &conn_iter)
  1875. sde_conn_timeline_status(conn);
  1876. drm_connector_list_iter_end(&conn_iter);
  1877. return;
  1878. }
  1879. mutex_lock(&dev->mode_config.mutex);
  1880. drm_connector_list_iter_begin(dev, &conn_iter);
  1881. drm_for_each_connector_iter(conn, &conn_iter)
  1882. sde_conn_timeline_status(conn);
  1883. drm_connector_list_iter_end(&conn_iter);
  1884. mutex_unlock(&dev->mode_config.mutex);
  1885. }
  1886. static int sde_kms_postinit(struct msm_kms *kms)
  1887. {
  1888. struct sde_kms *sde_kms = to_sde_kms(kms);
  1889. struct drm_device *dev;
  1890. struct drm_crtc *crtc;
  1891. struct msm_drm_private *priv;
  1892. int i, rc;
  1893. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev ||
  1894. !sde_kms->dev->dev_private) {
  1895. SDE_ERROR("invalid sde_kms\n");
  1896. return -EINVAL;
  1897. }
  1898. dev = sde_kms->dev;
  1899. priv = sde_kms->dev->dev_private;
  1900. /*
  1901. * Handle (re)initializations during power enable, the sde power
  1902. * event call has to be after drm_irq_install to handle irq update.
  1903. */
  1904. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  1905. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  1906. SDE_POWER_EVENT_POST_ENABLE |
  1907. SDE_POWER_EVENT_PRE_DISABLE,
  1908. sde_kms_handle_power_event, sde_kms, "kms");
  1909. if (sde_kms->splash_data.num_splash_displays) {
  1910. SDE_DEBUG("Skipping MDP Resources disable\n");
  1911. } else {
  1912. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1913. sde_power_data_bus_set_quota(&priv->phandle, i,
  1914. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1915. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1916. pm_runtime_put_sync(sde_kms->dev->dev);
  1917. }
  1918. rc = _sde_debugfs_init(sde_kms);
  1919. if (rc)
  1920. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1921. drm_for_each_crtc(crtc, dev)
  1922. sde_crtc_post_init(dev, crtc);
  1923. return rc;
  1924. }
  1925. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1926. struct drm_encoder *encoder)
  1927. {
  1928. return rate;
  1929. }
  1930. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1931. struct platform_device *pdev)
  1932. {
  1933. struct drm_device *dev;
  1934. struct msm_drm_private *priv;
  1935. struct sde_vm_ops *vm_ops;
  1936. int i;
  1937. if (!sde_kms || !pdev)
  1938. return;
  1939. dev = sde_kms->dev;
  1940. if (!dev)
  1941. return;
  1942. priv = dev->dev_private;
  1943. if (!priv)
  1944. return;
  1945. if (sde_kms->genpd_init) {
  1946. sde_kms->genpd_init = false;
  1947. pm_genpd_remove(&sde_kms->genpd);
  1948. of_genpd_del_provider(pdev->dev.of_node);
  1949. }
  1950. vm_ops = sde_vm_get_ops(sde_kms);
  1951. if (vm_ops && vm_ops->vm_deinit)
  1952. vm_ops->vm_deinit(sde_kms, vm_ops);
  1953. if (sde_kms->hw_intr)
  1954. sde_hw_intr_destroy(sde_kms->hw_intr);
  1955. sde_kms->hw_intr = NULL;
  1956. if (sde_kms->power_event)
  1957. sde_power_handle_unregister_event(
  1958. &priv->phandle, sde_kms->power_event);
  1959. _sde_kms_release_displays(sde_kms);
  1960. _sde_kms_unmap_all_splash_regions(sde_kms);
  1961. if (sde_kms->catalog) {
  1962. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1963. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1964. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1965. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1966. }
  1967. }
  1968. if (sde_kms->rm_init)
  1969. sde_rm_destroy(&sde_kms->rm);
  1970. sde_kms->rm_init = false;
  1971. if (sde_kms->catalog)
  1972. sde_hw_catalog_deinit(sde_kms->catalog);
  1973. sde_kms->catalog = NULL;
  1974. if (sde_kms->sid)
  1975. msm_iounmap(pdev, sde_kms->sid);
  1976. sde_kms->sid = NULL;
  1977. if (sde_kms->reg_dma)
  1978. msm_iounmap(pdev, sde_kms->reg_dma);
  1979. sde_kms->reg_dma = NULL;
  1980. if (sde_kms->vbif[VBIF_NRT])
  1981. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1982. sde_kms->vbif[VBIF_NRT] = NULL;
  1983. if (sde_kms->vbif[VBIF_RT])
  1984. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1985. sde_kms->vbif[VBIF_RT] = NULL;
  1986. if (sde_kms->mmio)
  1987. msm_iounmap(pdev, sde_kms->mmio);
  1988. sde_kms->mmio = NULL;
  1989. sde_reg_dma_deinit();
  1990. _sde_kms_mmu_destroy(sde_kms);
  1991. }
  1992. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1993. {
  1994. int i;
  1995. if (!sde_kms)
  1996. return -EINVAL;
  1997. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1998. struct msm_mmu *mmu;
  1999. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  2000. if (!aspace)
  2001. continue;
  2002. mmu = sde_kms->aspace[i]->mmu;
  2003. if (secure_only &&
  2004. !aspace->mmu->funcs->is_domain_secure(mmu))
  2005. continue;
  2006. /* cleanup aspace before detaching */
  2007. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  2008. SDE_DEBUG("Detaching domain:%d\n", i);
  2009. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  2010. ARRAY_SIZE(iommu_ports));
  2011. aspace->domain_attached = false;
  2012. }
  2013. return 0;
  2014. }
  2015. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  2016. {
  2017. int i;
  2018. if (!sde_kms)
  2019. return -EINVAL;
  2020. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2021. struct msm_mmu *mmu;
  2022. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  2023. if (!aspace)
  2024. continue;
  2025. mmu = sde_kms->aspace[i]->mmu;
  2026. if (secure_only &&
  2027. !aspace->mmu->funcs->is_domain_secure(mmu))
  2028. continue;
  2029. SDE_DEBUG("Attaching domain:%d\n", i);
  2030. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  2031. ARRAY_SIZE(iommu_ports));
  2032. aspace->domain_attached = true;
  2033. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  2034. }
  2035. return 0;
  2036. }
  2037. static void sde_kms_destroy(struct msm_kms *kms)
  2038. {
  2039. struct sde_kms *sde_kms;
  2040. struct drm_device *dev;
  2041. if (!kms) {
  2042. SDE_ERROR("invalid kms\n");
  2043. return;
  2044. }
  2045. sde_kms = to_sde_kms(kms);
  2046. dev = sde_kms->dev;
  2047. if (!dev || !dev->dev) {
  2048. SDE_ERROR("invalid device\n");
  2049. return;
  2050. }
  2051. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  2052. kfree(sde_kms);
  2053. }
  2054. static void sde_kms_helper_clear_dim_layers(struct drm_atomic_state *state, struct drm_crtc *crtc)
  2055. {
  2056. struct drm_crtc_state *crtc_state = NULL;
  2057. struct sde_crtc_state *c_state;
  2058. if (!state || !crtc) {
  2059. SDE_ERROR("invalid params\n");
  2060. return;
  2061. }
  2062. crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
  2063. c_state = to_sde_crtc_state(crtc_state);
  2064. _sde_crtc_clear_dim_layers_v1(crtc_state);
  2065. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, c_state->dirty);
  2066. }
  2067. static int sde_kms_set_crtc_for_conn(struct drm_device *dev,
  2068. struct drm_encoder *enc, struct drm_atomic_state *state)
  2069. {
  2070. struct drm_connector *conn = NULL;
  2071. struct drm_connector *tmp_conn = NULL;
  2072. struct drm_connector_list_iter conn_iter;
  2073. struct drm_crtc_state *crtc_state = NULL;
  2074. struct drm_connector_state *conn_state = NULL;
  2075. int ret = 0;
  2076. drm_connector_list_iter_begin(dev, &conn_iter);
  2077. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2078. if (enc == tmp_conn->state->best_encoder) {
  2079. conn = tmp_conn;
  2080. break;
  2081. }
  2082. }
  2083. drm_connector_list_iter_end(&conn_iter);
  2084. if (!conn || !enc->crtc) {
  2085. SDE_ERROR("invalid params for enc:%d\n", DRMID(enc));
  2086. return -EINVAL;
  2087. }
  2088. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2089. if (IS_ERR(crtc_state)) {
  2090. ret = PTR_ERR(crtc_state);
  2091. SDE_ERROR("error %d getting crtc %d state\n",
  2092. ret, DRMID(enc->crtc));
  2093. return ret;
  2094. }
  2095. conn_state = drm_atomic_get_connector_state(state, conn);
  2096. if (IS_ERR(conn_state)) {
  2097. ret = PTR_ERR(conn_state);
  2098. SDE_ERROR("error %d getting connector %d state\n",
  2099. ret, DRMID(conn));
  2100. return ret;
  2101. }
  2102. crtc_state->active = true;
  2103. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2104. if (ret)
  2105. SDE_ERROR("error %d setting the crtc\n", ret);
  2106. return ret;
  2107. }
  2108. static void _sde_kms_plane_force_remove(struct drm_plane *plane,
  2109. struct drm_atomic_state *state)
  2110. {
  2111. struct drm_plane_state *plane_state;
  2112. int ret = 0;
  2113. plane_state = drm_atomic_get_plane_state(state, plane);
  2114. if (IS_ERR(plane_state)) {
  2115. ret = PTR_ERR(plane_state);
  2116. SDE_ERROR("error %d getting plane %d state\n",
  2117. ret, plane->base.id);
  2118. return;
  2119. }
  2120. plane->old_fb = plane->fb;
  2121. SDE_DEBUG("disabling plane %d\n", plane->base.id);
  2122. ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
  2123. if (ret != 0)
  2124. SDE_ERROR("error %d disabling plane %d\n", ret,
  2125. plane->base.id);
  2126. drm_atomic_set_fb_for_plane(plane_state, NULL);
  2127. }
  2128. static int _sde_kms_remove_fbs(struct sde_kms *sde_kms, struct drm_file *file,
  2129. struct drm_atomic_state *state)
  2130. {
  2131. struct drm_device *dev = sde_kms->dev;
  2132. struct drm_framebuffer *fb, *tfb;
  2133. struct list_head fbs;
  2134. struct drm_plane *plane;
  2135. struct drm_crtc *crtc = NULL;
  2136. unsigned int crtc_mask = 0;
  2137. int ret = 0;
  2138. INIT_LIST_HEAD(&fbs);
  2139. list_for_each_entry_safe(fb, tfb, &file->fbs, filp_head) {
  2140. if (drm_framebuffer_read_refcount(fb) > 1) {
  2141. list_move_tail(&fb->filp_head, &fbs);
  2142. drm_for_each_plane(plane, dev) {
  2143. if (plane->state && plane->state->fb == fb) {
  2144. if (plane->state->crtc)
  2145. crtc_mask |= drm_crtc_mask(plane->state->crtc);
  2146. _sde_kms_plane_force_remove(plane, state);
  2147. }
  2148. }
  2149. } else {
  2150. list_del_init(&fb->filp_head);
  2151. drm_framebuffer_put(fb);
  2152. }
  2153. }
  2154. if (list_empty(&fbs)) {
  2155. SDE_DEBUG("skip commit as no fb(s)\n");
  2156. return 0;
  2157. }
  2158. drm_for_each_crtc(crtc, dev) {
  2159. if ((crtc_mask & drm_crtc_mask(crtc)) && crtc->state->active) {
  2160. struct drm_encoder *drm_enc;
  2161. drm_for_each_encoder_mask(drm_enc, crtc->dev,
  2162. crtc->state->encoder_mask) {
  2163. ret = sde_kms_set_crtc_for_conn(dev, drm_enc, state);
  2164. if (ret)
  2165. goto error;
  2166. }
  2167. sde_kms_helper_clear_dim_layers(state, crtc);
  2168. }
  2169. }
  2170. SDE_EVT32(state, crtc_mask);
  2171. SDE_DEBUG("null commit after removing all the pipes\n");
  2172. ret = drm_atomic_commit(state);
  2173. error:
  2174. if (ret) {
  2175. /*
  2176. * move the fbs back to original list, so it would be
  2177. * handled during drm_release
  2178. */
  2179. list_for_each_entry_safe(fb, tfb, &fbs, filp_head)
  2180. list_move_tail(&fb->filp_head, &file->fbs);
  2181. if (ret == -EDEADLK || ret == -ERESTARTSYS)
  2182. SDE_DEBUG("atomic commit failed in preclose, ret:%d\n", ret);
  2183. else
  2184. SDE_ERROR("atomic commit failed in preclose, ret:%d\n", ret);
  2185. goto end;
  2186. }
  2187. while (!list_empty(&fbs)) {
  2188. fb = list_first_entry(&fbs, typeof(*fb), filp_head);
  2189. list_del_init(&fb->filp_head);
  2190. drm_framebuffer_put(fb);
  2191. }
  2192. end:
  2193. return ret;
  2194. }
  2195. static void sde_kms_preclose(struct msm_kms *kms, struct drm_file *file)
  2196. {
  2197. struct sde_kms *sde_kms = to_sde_kms(kms);
  2198. struct drm_device *dev = sde_kms->dev;
  2199. struct msm_drm_private *priv = dev->dev_private;
  2200. unsigned int i;
  2201. struct drm_atomic_state *state = NULL;
  2202. struct drm_modeset_acquire_ctx ctx;
  2203. int ret = 0;
  2204. /* cancel pending flip event */
  2205. for (i = 0; i < priv->num_crtcs; i++)
  2206. sde_crtc_complete_flip(priv->crtcs[i], file);
  2207. drm_modeset_acquire_init(&ctx, 0);
  2208. retry:
  2209. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2210. if (ret == -EDEADLK) {
  2211. drm_modeset_backoff(&ctx);
  2212. goto retry;
  2213. } else if (WARN_ON(ret)) {
  2214. goto end;
  2215. }
  2216. state = drm_atomic_state_alloc(dev);
  2217. if (!state) {
  2218. ret = -ENOMEM;
  2219. goto end;
  2220. }
  2221. state->acquire_ctx = &ctx;
  2222. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2223. ret = _sde_kms_remove_fbs(sde_kms, file, state);
  2224. if (ret != -EDEADLK && ret != -ERESTARTSYS)
  2225. break;
  2226. drm_atomic_state_clear(state);
  2227. drm_modeset_backoff(&ctx);
  2228. }
  2229. end:
  2230. if (state)
  2231. drm_atomic_state_put(state);
  2232. SDE_DEBUG("sde preclose done, ret:%d\n", ret);
  2233. drm_modeset_drop_locks(&ctx);
  2234. drm_modeset_acquire_fini(&ctx);
  2235. }
  2236. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  2237. struct drm_atomic_state *state)
  2238. {
  2239. struct drm_device *dev = sde_kms->dev;
  2240. struct drm_plane *plane;
  2241. struct drm_plane_state *plane_state;
  2242. struct drm_crtc *crtc;
  2243. struct drm_crtc_state *crtc_state;
  2244. struct drm_connector *conn;
  2245. struct drm_connector_state *conn_state;
  2246. struct drm_connector_list_iter conn_iter;
  2247. int ret = 0;
  2248. drm_for_each_plane(plane, dev) {
  2249. plane_state = drm_atomic_get_plane_state(state, plane);
  2250. if (IS_ERR(plane_state)) {
  2251. ret = PTR_ERR(plane_state);
  2252. SDE_ERROR("error %d getting plane %d state\n",
  2253. ret, DRMID(plane));
  2254. return ret;
  2255. }
  2256. ret = sde_plane_helper_reset_custom_properties(plane,
  2257. plane_state);
  2258. if (ret) {
  2259. SDE_ERROR("error %d resetting plane props %d\n",
  2260. ret, DRMID(plane));
  2261. return ret;
  2262. }
  2263. }
  2264. drm_for_each_crtc(crtc, dev) {
  2265. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  2266. if (IS_ERR(crtc_state)) {
  2267. ret = PTR_ERR(crtc_state);
  2268. SDE_ERROR("error %d getting crtc %d state\n",
  2269. ret, DRMID(crtc));
  2270. return ret;
  2271. }
  2272. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  2273. if (ret) {
  2274. SDE_ERROR("error %d resetting crtc props %d\n",
  2275. ret, DRMID(crtc));
  2276. return ret;
  2277. }
  2278. }
  2279. drm_connector_list_iter_begin(dev, &conn_iter);
  2280. drm_for_each_connector_iter(conn, &conn_iter) {
  2281. conn_state = drm_atomic_get_connector_state(state, conn);
  2282. if (IS_ERR(conn_state)) {
  2283. ret = PTR_ERR(conn_state);
  2284. SDE_ERROR("error %d getting connector %d state\n",
  2285. ret, DRMID(conn));
  2286. return ret;
  2287. }
  2288. ret = sde_connector_helper_reset_custom_properties(conn,
  2289. conn_state);
  2290. if (ret) {
  2291. SDE_ERROR("error %d resetting connector props %d\n",
  2292. ret, DRMID(conn));
  2293. return ret;
  2294. }
  2295. }
  2296. drm_connector_list_iter_end(&conn_iter);
  2297. return ret;
  2298. }
  2299. static void sde_kms_lastclose(struct msm_kms *kms)
  2300. {
  2301. struct sde_kms *sde_kms;
  2302. struct drm_device *dev;
  2303. struct drm_atomic_state *state;
  2304. struct drm_modeset_acquire_ctx ctx;
  2305. int ret;
  2306. if (!kms) {
  2307. SDE_ERROR("invalid argument\n");
  2308. return;
  2309. }
  2310. sde_kms = to_sde_kms(kms);
  2311. dev = sde_kms->dev;
  2312. drm_modeset_acquire_init(&ctx, 0);
  2313. state = drm_atomic_state_alloc(dev);
  2314. if (!state) {
  2315. ret = -ENOMEM;
  2316. goto out_ctx;
  2317. }
  2318. state->acquire_ctx = &ctx;
  2319. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  2320. retry:
  2321. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2322. if (ret)
  2323. goto out_state;
  2324. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  2325. if (ret)
  2326. goto out_state;
  2327. ret = drm_atomic_commit(state);
  2328. out_state:
  2329. if (ret == -EDEADLK)
  2330. goto backoff;
  2331. drm_atomic_state_put(state);
  2332. out_ctx:
  2333. drm_modeset_drop_locks(&ctx);
  2334. drm_modeset_acquire_fini(&ctx);
  2335. if (ret)
  2336. SDE_ERROR("kms lastclose failed: %d\n", ret);
  2337. SDE_EVT32(ret, SDE_EVTLOG_FUNC_EXIT);
  2338. return;
  2339. backoff:
  2340. drm_atomic_state_clear(state);
  2341. drm_modeset_backoff(&ctx);
  2342. SDE_EVT32(ret, SDE_EVTLOG_FUNC_CASE1);
  2343. goto retry;
  2344. }
  2345. static int _sde_kms_validate_vm_request(struct drm_atomic_state *state, struct sde_kms *sde_kms,
  2346. enum sde_crtc_vm_req vm_req, bool vm_owns_hw)
  2347. {
  2348. struct drm_crtc *crtc, *active_crtc = NULL, *global_active_crtc = NULL;
  2349. struct drm_crtc_state *new_cstate, *old_cstate, *active_cstate;
  2350. struct drm_encoder *encoder;
  2351. struct drm_connector *connector;
  2352. struct drm_connector_state *new_connstate;
  2353. struct sde_vm_ops *vm_ops = sde_vm_get_ops(sde_kms);
  2354. struct sde_mdss_cfg *catalog = sde_kms->catalog;
  2355. struct sde_connector *sde_conn;
  2356. struct dsi_display *dsi_display;
  2357. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  2358. uint32_t crtc_encoder_cnt = 0;
  2359. enum sde_crtc_idle_pc_state idle_pc_state;
  2360. int rc = 0;
  2361. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2362. struct sde_crtc_state *new_state = NULL;
  2363. if (!new_cstate->active && !old_cstate->active)
  2364. continue;
  2365. new_state = to_sde_crtc_state(new_cstate);
  2366. idle_pc_state = sde_crtc_get_property(new_state, CRTC_PROP_IDLE_PC_STATE);
  2367. active_crtc = crtc;
  2368. active_cstate = new_cstate;
  2369. commit_crtc_cnt++;
  2370. }
  2371. list_for_each_entry(crtc, &sde_kms->dev->mode_config.crtc_list, head) {
  2372. if (!crtc->state->active)
  2373. continue;
  2374. global_crtc_cnt++;
  2375. global_active_crtc = crtc;
  2376. }
  2377. if (active_crtc) {
  2378. drm_for_each_encoder_mask(encoder, active_crtc->dev, active_cstate->encoder_mask)
  2379. crtc_encoder_cnt++;
  2380. }
  2381. for_each_new_connector_in_state(state, connector, new_connstate, i) {
  2382. int conn_mask = active_cstate->connector_mask;
  2383. if (drm_connector_mask(connector) & conn_mask) {
  2384. sde_conn = to_sde_connector(connector);
  2385. dsi_display = (struct dsi_display *) sde_conn->display;
  2386. SDE_EVT32(DRMID(connector), DRMID(active_crtc), i, dsi_display->type,
  2387. dsi_display->trusted_vm_env);
  2388. SDE_DEBUG("VM display:%s, conn:%d, crtc:%d, type:%d, tvm:%d\n",
  2389. dsi_display->name, DRMID(connector), DRMID(active_crtc),
  2390. dsi_display->type, dsi_display->trusted_vm_env);
  2391. break;
  2392. }
  2393. }
  2394. /* Check for single crtc commits only on valid VM requests */
  2395. if (active_crtc && global_active_crtc &&
  2396. (commit_crtc_cnt > catalog->max_trusted_vm_displays ||
  2397. global_crtc_cnt > catalog->max_trusted_vm_displays ||
  2398. active_crtc != global_active_crtc)) {
  2399. SDE_ERROR("VM switch failed; MAX:%d a_cnt:%d g_cnt:%d a_crtc:%d g_crtc:%d\n",
  2400. catalog->max_trusted_vm_displays, commit_crtc_cnt, global_crtc_cnt,
  2401. DRMID(active_crtc), DRMID(global_active_crtc));
  2402. return -E2BIG;
  2403. } else if ((vm_req == VM_REQ_RELEASE) &&
  2404. ((idle_pc_state == IDLE_PC_ENABLE) ||
  2405. (crtc_encoder_cnt > TRUSTED_VM_MAX_ENCODER_PER_CRTC))) {
  2406. /*
  2407. * disable idle-pc before releasing the HW
  2408. * allow only specified number of encoders on a given crtc
  2409. */
  2410. SDE_ERROR("VM switch failed; idle-pc:%d max:%d encoder_cnt:%d\n",
  2411. idle_pc_state, TRUSTED_VM_MAX_ENCODER_PER_CRTC, crtc_encoder_cnt);
  2412. return -EINVAL;
  2413. }
  2414. if ((vm_req == VM_REQ_ACQUIRE) && !vm_owns_hw) {
  2415. rc = vm_ops->vm_acquire(sde_kms);
  2416. if (rc) {
  2417. SDE_ERROR("VM acquire failed; hw_owner:%d, rc:%d\n", vm_owns_hw, rc);
  2418. return rc;
  2419. }
  2420. if (vm_ops->vm_resource_init)
  2421. rc = vm_ops->vm_resource_init(sde_kms, state);
  2422. }
  2423. return rc;
  2424. }
  2425. static int sde_kms_check_vm_request(struct msm_kms *kms,
  2426. struct drm_atomic_state *state)
  2427. {
  2428. struct sde_kms *sde_kms;
  2429. struct drm_crtc *crtc;
  2430. struct drm_crtc_state *new_cstate, *old_cstate;
  2431. struct sde_vm_ops *vm_ops;
  2432. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  2433. int i, rc = 0;
  2434. bool vm_req_active = false, prev_vm_req = false;
  2435. bool vm_owns_hw;
  2436. if (!kms || !state)
  2437. return -EINVAL;
  2438. sde_kms = to_sde_kms(kms);
  2439. vm_ops = sde_vm_get_ops(sde_kms);
  2440. if (!vm_ops)
  2441. return 0;
  2442. if (!vm_ops->vm_request_valid || !vm_ops->vm_owns_hw || !vm_ops->vm_acquire)
  2443. return -EINVAL;
  2444. drm_for_each_crtc(crtc, state->dev) {
  2445. if (crtc->state && (sde_crtc_get_property(to_sde_crtc_state(crtc->state),
  2446. CRTC_PROP_VM_REQ_STATE) == VM_REQ_RELEASE)) {
  2447. prev_vm_req = true;
  2448. break;
  2449. }
  2450. }
  2451. /* check for an active vm request */
  2452. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2453. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  2454. if (!new_cstate->active && !old_cstate->active)
  2455. continue;
  2456. new_state = to_sde_crtc_state(new_cstate);
  2457. new_vm_req = sde_crtc_get_property(new_state, CRTC_PROP_VM_REQ_STATE);
  2458. old_state = to_sde_crtc_state(old_cstate);
  2459. old_vm_req = sde_crtc_get_property(old_state, CRTC_PROP_VM_REQ_STATE);
  2460. /*
  2461. * VM request should be validated in the following usecases
  2462. * - There is a vm request(other than VM_REQ_NONE) on current/prev crtc state.
  2463. * - Previously, vm transition has taken place on one of the crtc's.
  2464. */
  2465. if (old_vm_req || new_vm_req || prev_vm_req) {
  2466. if (!vm_req_active) {
  2467. sde_vm_lock(sde_kms);
  2468. vm_owns_hw = sde_vm_owns_hw(sde_kms);
  2469. }
  2470. rc = vm_ops->vm_request_valid(sde_kms, old_vm_req, new_vm_req);
  2471. if (rc) {
  2472. SDE_ERROR(
  2473. "VM transition check failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2474. old_vm_req, new_vm_req, vm_owns_hw, rc);
  2475. sde_vm_unlock(sde_kms);
  2476. vm_req_active = false;
  2477. break;
  2478. } else if (old_vm_req == VM_REQ_ACQUIRE && new_vm_req == VM_REQ_NONE) {
  2479. SDE_DEBUG("VM transition valid; ignore further checks\n");
  2480. if (!vm_req_active)
  2481. sde_vm_unlock(sde_kms);
  2482. } else {
  2483. vm_req_active = true;
  2484. }
  2485. }
  2486. }
  2487. /* validate active requests and perform acquire if necessary */
  2488. if (vm_req_active) {
  2489. rc = _sde_kms_validate_vm_request(state, sde_kms, new_vm_req, vm_owns_hw);
  2490. sde_vm_unlock(sde_kms);
  2491. SDE_EVT32(old_vm_req, new_vm_req, vm_req_active, vm_owns_hw, rc);
  2492. SDE_DEBUG("VM o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n", old_vm_req, new_vm_req,
  2493. vm_req_active ? vm_owns_hw : -1, rc);
  2494. }
  2495. return rc;
  2496. }
  2497. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2498. struct drm_atomic_state *state)
  2499. {
  2500. struct sde_kms *sde_kms;
  2501. struct drm_device *dev;
  2502. struct drm_crtc *crtc;
  2503. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2504. struct drm_crtc_state *crtc_state;
  2505. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2506. bool sec_session = false, global_sec_session = false;
  2507. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2508. int i;
  2509. if (!kms || !state) {
  2510. return -EINVAL;
  2511. SDE_ERROR("invalid arguments\n");
  2512. }
  2513. sde_kms = to_sde_kms(kms);
  2514. dev = sde_kms->dev;
  2515. /* iterate state object for active secure/non-secure crtc */
  2516. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2517. if (!crtc_state->active)
  2518. continue;
  2519. active_crtc_cnt++;
  2520. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2521. &fb_sec, &fb_sec_dir);
  2522. if (fb_sec_dir)
  2523. sec_session = true;
  2524. cur_crtc = crtc;
  2525. }
  2526. /* iterate global list for active and secure/non-secure crtc */
  2527. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2528. if (!crtc->state->active)
  2529. continue;
  2530. global_active_crtc_cnt++;
  2531. /* update only when crtc is not the same as current crtc */
  2532. if (crtc != cur_crtc) {
  2533. fb_ns = fb_sec = fb_sec_dir = 0;
  2534. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2535. &fb_sec, &fb_sec_dir);
  2536. if (fb_sec_dir)
  2537. global_sec_session = true;
  2538. global_crtc = crtc;
  2539. }
  2540. }
  2541. if (!global_sec_session && !sec_session)
  2542. return 0;
  2543. /*
  2544. * - fail crtc commit, if secure-camera/secure-ui session is
  2545. * in-progress in any other display
  2546. * - fail secure-camera/secure-ui crtc commit, if any other display
  2547. * session is in-progress
  2548. */
  2549. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2550. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2551. SDE_ERROR(
  2552. "crtc%d secure check failed global_active:%d active:%d\n",
  2553. cur_crtc ? cur_crtc->base.id : -1,
  2554. global_active_crtc_cnt, active_crtc_cnt);
  2555. return -EPERM;
  2556. /*
  2557. * As only one crtc is allowed during secure session, the crtc
  2558. * in this commit should match with the global crtc
  2559. */
  2560. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2561. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2562. cur_crtc->base.id, sec_session,
  2563. global_crtc->base.id, global_sec_session);
  2564. return -EPERM;
  2565. }
  2566. return 0;
  2567. }
  2568. static void sde_kms_vm_res_release(struct msm_kms *kms,
  2569. struct drm_atomic_state *state)
  2570. {
  2571. struct drm_crtc *crtc;
  2572. struct drm_crtc_state *new_cstate;
  2573. struct sde_crtc_state *cstate;
  2574. struct sde_vm_ops *vm_ops;
  2575. enum sde_crtc_vm_req vm_req;
  2576. struct sde_kms *sde_kms = to_sde_kms(kms);
  2577. vm_ops = sde_vm_get_ops(sde_kms);
  2578. if (!vm_ops)
  2579. return;
  2580. crtc = sde_kms_vm_get_vm_crtc(state);
  2581. if (!crtc)
  2582. return;
  2583. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  2584. cstate = to_sde_crtc_state(new_cstate);
  2585. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  2586. if (vm_req != VM_REQ_ACQUIRE)
  2587. return;
  2588. sde_vm_lock(sde_kms);
  2589. if (vm_ops->vm_acquire_fail_handler)
  2590. vm_ops->vm_acquire_fail_handler(sde_kms);
  2591. sde_vm_unlock(sde_kms);
  2592. }
  2593. static int sde_kms_check_cwb_concurreny(struct msm_kms *kms,
  2594. struct drm_atomic_state *state)
  2595. {
  2596. struct sde_kms *sde_kms;
  2597. struct drm_crtc *crtc;
  2598. struct drm_crtc_state *old_crtc_state, *new_crtc_state;
  2599. struct drm_encoder *encoder;
  2600. struct sde_crtc_state *cstate;
  2601. int i = 0, cnt = 0, max_cwb = 0;
  2602. if (!kms || !state) {
  2603. SDE_ERROR("invalid arguments\n");
  2604. return -EINVAL;
  2605. }
  2606. sde_kms = to_sde_kms(kms);
  2607. max_cwb = sde_kms->catalog->max_cwb;
  2608. if (!max_cwb)
  2609. return 0;
  2610. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  2611. cstate = to_sde_crtc_state(new_crtc_state);
  2612. drm_for_each_encoder_mask(encoder, crtc->dev, cstate->cwb_enc_mask) {
  2613. cnt++;
  2614. SDE_DEBUG("crtc%d has cwb%d attached to it\n", crtc->base.id,
  2615. encoder->base.id);
  2616. }
  2617. if (cnt > max_cwb) {
  2618. SDE_ERROR("found %d cwb in the atomic state, max supported %d\n",
  2619. cnt, max_cwb);
  2620. return -EOPNOTSUPP;
  2621. }
  2622. }
  2623. return 0;
  2624. }
  2625. static int sde_kms_atomic_check(struct msm_kms *kms,
  2626. struct drm_atomic_state *state)
  2627. {
  2628. struct sde_kms *sde_kms;
  2629. struct drm_device *dev;
  2630. int ret;
  2631. if (!kms || !state)
  2632. return -EINVAL;
  2633. sde_kms = to_sde_kms(kms);
  2634. dev = sde_kms->dev;
  2635. SDE_ATRACE_BEGIN("atomic_check");
  2636. if (sde_kms_is_suspend_blocked(dev)) {
  2637. SDE_DEBUG("suspended, skip atomic_check\n");
  2638. ret = -EBUSY;
  2639. goto end;
  2640. }
  2641. ret = sde_kms_check_vm_request(kms, state);
  2642. if (ret) {
  2643. SDE_ERROR("vm switch request checks failed\n");
  2644. goto end;
  2645. }
  2646. ret = drm_atomic_helper_check(dev, state);
  2647. if (ret)
  2648. goto vm_clean_up;
  2649. /*
  2650. * Check if any secure transition(moving CRTC between secure and
  2651. * non-secure state and vice-versa) is allowed or not. when moving
  2652. * to secure state, planes with fb_mode set to dir_translated only can
  2653. * be staged on the CRTC, and only one CRTC can be active during
  2654. * Secure state
  2655. */
  2656. ret = sde_kms_check_secure_transition(kms, state);
  2657. if (ret)
  2658. goto vm_clean_up;
  2659. ret = sde_kms_check_cwb_concurreny(kms, state);
  2660. if (ret)
  2661. goto vm_clean_up;
  2662. goto end;
  2663. vm_clean_up:
  2664. sde_kms_vm_res_release(kms, state);
  2665. end:
  2666. SDE_ATRACE_END("atomic_check");
  2667. return ret;
  2668. }
  2669. static struct msm_gem_address_space*
  2670. _sde_kms_get_address_space(struct msm_kms *kms,
  2671. unsigned int domain)
  2672. {
  2673. struct sde_kms *sde_kms;
  2674. if (!kms) {
  2675. SDE_ERROR("invalid kms\n");
  2676. return NULL;
  2677. }
  2678. sde_kms = to_sde_kms(kms);
  2679. if (!sde_kms) {
  2680. SDE_ERROR("invalid sde_kms\n");
  2681. return NULL;
  2682. }
  2683. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2684. return NULL;
  2685. return (sde_kms->aspace[domain] &&
  2686. sde_kms->aspace[domain]->domain_attached) ?
  2687. sde_kms->aspace[domain] : NULL;
  2688. }
  2689. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2690. unsigned int domain)
  2691. {
  2692. struct sde_kms *sde_kms;
  2693. struct msm_gem_address_space *aspace;
  2694. if (!kms) {
  2695. SDE_ERROR("invalid kms\n");
  2696. return NULL;
  2697. }
  2698. sde_kms = to_sde_kms(kms);
  2699. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2700. SDE_ERROR("invalid params\n");
  2701. return NULL;
  2702. }
  2703. aspace = _sde_kms_get_address_space(kms, domain);
  2704. return (aspace && aspace->domain_attached) ?
  2705. msm_gem_get_aspace_device(aspace) : NULL;
  2706. }
  2707. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2708. {
  2709. struct drm_device *dev = NULL;
  2710. struct sde_kms *sde_kms = NULL;
  2711. struct drm_connector *connector = NULL;
  2712. struct drm_connector_list_iter conn_iter;
  2713. struct sde_connector *sde_conn = NULL;
  2714. if (!kms) {
  2715. SDE_ERROR("invalid kms\n");
  2716. return;
  2717. }
  2718. sde_kms = to_sde_kms(kms);
  2719. dev = sde_kms->dev;
  2720. if (!dev) {
  2721. SDE_ERROR("invalid device\n");
  2722. return;
  2723. }
  2724. if (!dev->mode_config.poll_enabled)
  2725. return;
  2726. mutex_lock(&dev->mode_config.mutex);
  2727. drm_connector_list_iter_begin(dev, &conn_iter);
  2728. drm_for_each_connector_iter(connector, &conn_iter) {
  2729. /* Only handle HPD capable connectors. */
  2730. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2731. continue;
  2732. sde_conn = to_sde_connector(connector);
  2733. if (sde_conn->ops.post_open)
  2734. sde_conn->ops.post_open(&sde_conn->base,
  2735. sde_conn->display);
  2736. }
  2737. drm_connector_list_iter_end(&conn_iter);
  2738. mutex_unlock(&dev->mode_config.mutex);
  2739. }
  2740. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2741. struct sde_splash_display *splash_display,
  2742. struct drm_crtc *crtc)
  2743. {
  2744. struct msm_drm_private *priv;
  2745. struct drm_plane *plane;
  2746. struct sde_splash_mem *splash;
  2747. struct sde_splash_mem *demura;
  2748. struct sde_plane_state *pstate;
  2749. struct sde_sspp_index_info *pipe_info;
  2750. enum sde_sspp pipe_id;
  2751. bool is_virtual;
  2752. int i;
  2753. if (!sde_kms || !splash_display || !crtc) {
  2754. SDE_ERROR("invalid input args\n");
  2755. return -EINVAL;
  2756. }
  2757. priv = sde_kms->dev->dev_private;
  2758. pipe_info = &splash_display->pipe_info;
  2759. splash = splash_display->splash;
  2760. demura = splash_display->demura;
  2761. for (i = 0; i < priv->num_planes; i++) {
  2762. plane = priv->planes[i];
  2763. pipe_id = sde_plane_pipe(plane);
  2764. is_virtual = is_sde_plane_virtual(plane);
  2765. if ((is_virtual && test_bit(pipe_id, pipe_info->virt_pipes)) ||
  2766. (!is_virtual && test_bit(pipe_id, pipe_info->pipes))) {
  2767. if (splash && sde_plane_validate_src_addr(plane,
  2768. splash->splash_buf_base,
  2769. splash->splash_buf_size)) {
  2770. if (!demura || sde_plane_validate_src_addr(
  2771. plane, demura->splash_buf_base,
  2772. demura->splash_buf_size)) {
  2773. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2774. pipe_id, DRMID(crtc));
  2775. continue;
  2776. }
  2777. }
  2778. plane->state->crtc = crtc;
  2779. crtc->state->plane_mask |= drm_plane_mask(plane);
  2780. pstate = to_sde_plane_state(plane->state);
  2781. pstate->cont_splash_populated = true;
  2782. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2783. DRMID(crtc), DRMID(plane), is_virtual);
  2784. }
  2785. }
  2786. return 0;
  2787. }
  2788. static int sde_kms_inform_cont_splash_res_disable(struct msm_kms *kms,
  2789. struct dsi_display *dsi_display)
  2790. {
  2791. void *display;
  2792. struct drm_encoder *encoder = NULL;
  2793. struct msm_display_info info;
  2794. struct drm_device *dev;
  2795. struct sde_kms *sde_kms;
  2796. struct drm_connector_list_iter conn_iter;
  2797. struct drm_connector *connector = NULL;
  2798. struct sde_connector *sde_conn = NULL;
  2799. int rc = 0;
  2800. sde_kms = to_sde_kms(kms);
  2801. dev = sde_kms->dev;
  2802. display = dsi_display;
  2803. if (dsi_display) {
  2804. if (dsi_display->bridge->base.encoder) {
  2805. encoder = dsi_display->bridge->base.encoder;
  2806. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2807. }
  2808. memset(&info, 0x0, sizeof(info));
  2809. rc = dsi_display_get_info(NULL, &info, display);
  2810. if (rc) {
  2811. SDE_ERROR("%s: dsi get_info failed: %d\n",
  2812. __func__, rc);
  2813. encoder = NULL;
  2814. }
  2815. }
  2816. drm_connector_list_iter_begin(dev, &conn_iter);
  2817. drm_for_each_connector_iter(connector, &conn_iter) {
  2818. struct drm_encoder *c_encoder;
  2819. drm_connector_for_each_possible_encoder(connector,
  2820. c_encoder)
  2821. break;
  2822. if (!c_encoder) {
  2823. SDE_ERROR("c_encoder not found\n");
  2824. return -EINVAL;
  2825. }
  2826. /**
  2827. * Inform cont_splash is disabled to each interface/connector.
  2828. * This is currently supported for DSI interface.
  2829. */
  2830. sde_conn = to_sde_connector(connector);
  2831. if (sde_conn && sde_conn->ops.cont_splash_res_disable) {
  2832. if (!dsi_display || !encoder) {
  2833. sde_conn->ops.cont_splash_res_disable
  2834. (sde_conn->display);
  2835. } else if (c_encoder->base.id == encoder->base.id) {
  2836. /**
  2837. * This handles dual DSI
  2838. * configuration where one DSI
  2839. * interface has cont_splash
  2840. * enabled and the other doesn't.
  2841. */
  2842. sde_conn->ops.cont_splash_res_disable
  2843. (sde_conn->display);
  2844. break;
  2845. }
  2846. }
  2847. }
  2848. drm_connector_list_iter_end(&conn_iter);
  2849. return 0;
  2850. }
  2851. static int sde_kms_vm_trusted_cont_splash_res_init(struct sde_kms *sde_kms)
  2852. {
  2853. int i;
  2854. void *display;
  2855. struct dsi_display *dsi_display;
  2856. struct drm_encoder *encoder;
  2857. if (!sde_kms)
  2858. return -EINVAL;
  2859. if (!sde_in_trusted_vm(sde_kms))
  2860. return 0;
  2861. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  2862. display = sde_kms->dsi_displays[i];
  2863. dsi_display = (struct dsi_display *)display;
  2864. if (!dsi_display->bridge->base.encoder) {
  2865. SDE_ERROR("no encoder on dsi display:%d", i);
  2866. return -EINVAL;
  2867. }
  2868. encoder = dsi_display->bridge->base.encoder;
  2869. encoder->possible_crtcs = 1 << i;
  2870. SDE_DEBUG(
  2871. "dsi-display:%d encoder id[%d]=%d name=%s crtcs=%x\n", i,
  2872. encoder->index, encoder->base.id,
  2873. encoder->name, encoder->possible_crtcs);
  2874. }
  2875. return 0;
  2876. }
  2877. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2878. struct sde_kms *sde_kms, struct drm_connector *connector,
  2879. struct drm_atomic_state *state)
  2880. {
  2881. struct drm_display_mode *mode, *cur_mode = NULL;
  2882. struct drm_crtc *crtc;
  2883. struct drm_crtc_state *new_cstate, *old_cstate;
  2884. u32 i = 0;
  2885. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2886. list_for_each_entry(mode, &connector->modes, head) {
  2887. if (mode->type & DRM_MODE_TYPE_PREFERRED) {
  2888. cur_mode = mode;
  2889. break;
  2890. }
  2891. }
  2892. } else if (state) {
  2893. /* get the mode from first atomic_check phase for trusted_vm*/
  2894. for_each_oldnew_crtc_in_state(state, crtc, old_cstate,
  2895. new_cstate, i) {
  2896. if (!new_cstate->active && !old_cstate->active)
  2897. continue;
  2898. list_for_each_entry(mode, &connector->modes, head) {
  2899. if (drm_mode_equal(&new_cstate->mode, mode)) {
  2900. cur_mode = mode;
  2901. break;
  2902. }
  2903. }
  2904. }
  2905. }
  2906. return cur_mode;
  2907. }
  2908. static int sde_kms_cont_splash_config(struct msm_kms *kms,
  2909. struct drm_atomic_state *state)
  2910. {
  2911. void *display;
  2912. struct dsi_display *dsi_display;
  2913. struct msm_display_info info;
  2914. struct drm_encoder *encoder = NULL;
  2915. struct drm_crtc *crtc = NULL;
  2916. int i, rc = 0;
  2917. struct drm_display_mode *drm_mode = NULL;
  2918. struct drm_device *dev;
  2919. struct msm_drm_private *priv;
  2920. struct sde_kms *sde_kms;
  2921. struct drm_connector_list_iter conn_iter;
  2922. struct drm_connector *connector = NULL;
  2923. struct sde_connector *sde_conn = NULL;
  2924. struct sde_splash_display *splash_display;
  2925. if (!kms) {
  2926. SDE_ERROR("invalid kms\n");
  2927. return -EINVAL;
  2928. }
  2929. sde_kms = to_sde_kms(kms);
  2930. dev = sde_kms->dev;
  2931. if (!dev) {
  2932. SDE_ERROR("invalid device\n");
  2933. return -EINVAL;
  2934. }
  2935. rc = sde_kms_vm_trusted_cont_splash_res_init(sde_kms);
  2936. if (rc) {
  2937. SDE_ERROR("failed vm cont splash resource init, rc=%d", rc);
  2938. return -EINVAL;
  2939. }
  2940. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2941. && (!sde_kms->splash_data.num_splash_regions)) ||
  2942. !sde_kms->splash_data.num_splash_displays) {
  2943. DRM_INFO("cont_splash feature not enabled\n");
  2944. sde_kms_inform_cont_splash_res_disable(kms, NULL);
  2945. return rc;
  2946. }
  2947. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2948. sde_kms->splash_data.num_splash_displays,
  2949. sde_kms->dsi_display_count);
  2950. /* dsi */
  2951. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2952. struct sde_crtc_state *cstate;
  2953. struct sde_connector_state *conn_state;
  2954. display = sde_kms->dsi_displays[i];
  2955. dsi_display = (struct dsi_display *)display;
  2956. splash_display = &sde_kms->splash_data.splash_display[i];
  2957. if (!splash_display->cont_splash_enabled) {
  2958. SDE_DEBUG("display->name = %s splash not enabled\n",
  2959. dsi_display->name);
  2960. sde_kms_inform_cont_splash_res_disable(kms,
  2961. dsi_display);
  2962. continue;
  2963. }
  2964. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2965. if (dsi_display->bridge->base.encoder) {
  2966. encoder = dsi_display->bridge->base.encoder;
  2967. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2968. }
  2969. memset(&info, 0x0, sizeof(info));
  2970. rc = dsi_display_get_info(NULL, &info, display);
  2971. if (rc) {
  2972. SDE_ERROR("dsi get_info %d failed\n", i);
  2973. encoder = NULL;
  2974. continue;
  2975. }
  2976. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2977. ((info.is_connected) ? "true" : "false"),
  2978. info.display_type);
  2979. if (!encoder) {
  2980. SDE_ERROR("encoder not initialized\n");
  2981. return -EINVAL;
  2982. }
  2983. priv = sde_kms->dev->dev_private;
  2984. encoder->crtc = priv->crtcs[i];
  2985. crtc = encoder->crtc;
  2986. splash_display->encoder = encoder;
  2987. SDE_DEBUG("for dsi-display:%d crtc id[%d]:%d enc id[%d]:%d\n",
  2988. i, crtc->index, crtc->base.id, encoder->index,
  2989. encoder->base.id);
  2990. mutex_lock(&dev->mode_config.mutex);
  2991. drm_connector_list_iter_begin(dev, &conn_iter);
  2992. drm_for_each_connector_iter(connector, &conn_iter) {
  2993. struct drm_encoder *c_encoder;
  2994. drm_connector_for_each_possible_encoder(connector,
  2995. c_encoder)
  2996. break;
  2997. if (!c_encoder) {
  2998. SDE_ERROR("c_encoder not found\n");
  2999. mutex_unlock(&dev->mode_config.mutex);
  3000. return -EINVAL;
  3001. }
  3002. /**
  3003. * SDE_KMS doesn't attach more than one encoder to
  3004. * a DSI connector. So it is safe to check only with
  3005. * the first encoder entry. Revisit this logic if we
  3006. * ever have to support continuous splash for
  3007. * external displays in MST configuration.
  3008. */
  3009. if (c_encoder->base.id == encoder->base.id)
  3010. break;
  3011. }
  3012. drm_connector_list_iter_end(&conn_iter);
  3013. if (!connector) {
  3014. SDE_ERROR("connector not initialized\n");
  3015. mutex_unlock(&dev->mode_config.mutex);
  3016. return -EINVAL;
  3017. }
  3018. mutex_unlock(&dev->mode_config.mutex);
  3019. crtc->state->encoder_mask = drm_encoder_mask(encoder);
  3020. crtc->state->connector_mask = drm_connector_mask(connector);
  3021. connector->state->crtc = crtc;
  3022. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, state);
  3023. if (!drm_mode) {
  3024. SDE_ERROR("drm_mode not found; handoff_type:%d\n",
  3025. sde_kms->splash_data.type);
  3026. return -EINVAL;
  3027. }
  3028. SDE_DEBUG(
  3029. "drm_mode->name:%s, type:0x%x, flags:0x%x, handoff_type:%d\n",
  3030. drm_mode->name, drm_mode->type,
  3031. drm_mode->flags, sde_kms->splash_data.type);
  3032. /* Update CRTC drm structure */
  3033. crtc->state->active = true;
  3034. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  3035. if (rc) {
  3036. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  3037. return rc;
  3038. }
  3039. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  3040. drm_mode_copy(&crtc->mode, drm_mode);
  3041. cstate = to_sde_crtc_state(crtc->state);
  3042. cstate->cont_splash_populated = true;
  3043. /* Update encoder structure */
  3044. sde_encoder_update_caps_for_cont_splash(encoder,
  3045. splash_display, true);
  3046. sde_crtc_update_cont_splash_settings(crtc);
  3047. sde_conn = to_sde_connector(connector);
  3048. if (sde_conn && sde_conn->ops.cont_splash_config)
  3049. sde_conn->ops.cont_splash_config(sde_conn->display);
  3050. conn_state = to_sde_connector_state(connector->state);
  3051. conn_state->cont_splash_populated = true;
  3052. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  3053. splash_display, crtc);
  3054. if (rc) {
  3055. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  3056. return rc;
  3057. }
  3058. }
  3059. return rc;
  3060. }
  3061. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  3062. {
  3063. struct sde_kms *sde_kms;
  3064. if (!kms) {
  3065. SDE_ERROR("invalid kms\n");
  3066. return false;
  3067. }
  3068. sde_kms = to_sde_kms(kms);
  3069. return sde_kms->splash_data.num_splash_displays;
  3070. }
  3071. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  3072. const struct drm_display_mode *mode,
  3073. const struct msm_resource_caps_info *res, u32 *num_lm)
  3074. {
  3075. struct sde_kms *sde_kms;
  3076. s64 mode_clock_hz = 0;
  3077. s64 max_mdp_clock_hz = 0;
  3078. s64 max_lm_width = 0;
  3079. s64 hdisplay_fp = 0;
  3080. s64 htotal_fp = 0;
  3081. s64 vtotal_fp = 0;
  3082. s64 vrefresh_fp = 0;
  3083. s64 mdp_fudge_factor = 0;
  3084. s64 num_lm_fp = 0;
  3085. s64 lm_clk_fp = 0;
  3086. s64 lm_width_fp = 0;
  3087. int rc = 0;
  3088. if (!num_lm) {
  3089. SDE_ERROR("invalid num_lm pointer\n");
  3090. return -EINVAL;
  3091. }
  3092. /* default to 1 layer mixer */
  3093. *num_lm = 1;
  3094. if (!kms || !mode || !res) {
  3095. SDE_ERROR("invalid input args\n");
  3096. return -EINVAL;
  3097. }
  3098. sde_kms = to_sde_kms(kms);
  3099. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  3100. max_lm_width = drm_int2fixp(res->max_mixer_width);
  3101. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  3102. htotal_fp = drm_int2fixp(mode->htotal);
  3103. vtotal_fp = drm_int2fixp(mode->vtotal);
  3104. vrefresh_fp = drm_int2fixp(drm_mode_vrefresh(mode));
  3105. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  3106. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  3107. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  3108. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  3109. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  3110. if (mode_clock_hz > max_mdp_clock_hz ||
  3111. hdisplay_fp > max_lm_width) {
  3112. *num_lm = 0;
  3113. do {
  3114. *num_lm += 2;
  3115. num_lm_fp = drm_int2fixp(*num_lm);
  3116. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  3117. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  3118. if (*num_lm > 4) {
  3119. rc = -EINVAL;
  3120. goto error;
  3121. }
  3122. } while (lm_clk_fp > max_mdp_clock_hz ||
  3123. lm_width_fp > max_lm_width);
  3124. mode_clock_hz = lm_clk_fp;
  3125. }
  3126. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%u max_clk=%llu\n",
  3127. mode->name, mode->htotal, mode->vtotal, drm_mode_vrefresh(mode),
  3128. *num_lm, drm_fixp2int(mode_clock_hz),
  3129. sde_kms->perf.max_core_clk_rate);
  3130. return 0;
  3131. error:
  3132. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  3133. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%u max_clk=%llu\n",
  3134. mode->name, mode->htotal, mode->vtotal, drm_mode_vrefresh(mode),
  3135. *num_lm, drm_fixp2int(mode_clock_hz),
  3136. sde_kms->perf.max_core_clk_rate);
  3137. return rc;
  3138. }
  3139. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  3140. u32 hdisplay, u32 *num_dsc)
  3141. {
  3142. struct sde_kms *sde_kms;
  3143. uint32_t max_dsc_width;
  3144. if (!num_dsc) {
  3145. SDE_ERROR("invalid num_dsc pointer\n");
  3146. return -EINVAL;
  3147. }
  3148. *num_dsc = 0;
  3149. if (!kms || !hdisplay) {
  3150. SDE_ERROR("invalid input args\n");
  3151. return -EINVAL;
  3152. }
  3153. sde_kms = to_sde_kms(kms);
  3154. max_dsc_width = sde_kms->catalog->max_dsc_width;
  3155. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  3156. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  3157. hdisplay, max_dsc_width,
  3158. *num_dsc);
  3159. return 0;
  3160. }
  3161. static void _sde_kms_null_commit(struct drm_device *dev,
  3162. struct drm_encoder *enc)
  3163. {
  3164. struct drm_modeset_acquire_ctx ctx;
  3165. struct drm_atomic_state *state = NULL;
  3166. int retry_cnt = 0;
  3167. int ret = 0;
  3168. drm_modeset_acquire_init(&ctx, 0);
  3169. retry:
  3170. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  3171. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  3172. drm_modeset_backoff(&ctx);
  3173. retry_cnt++;
  3174. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  3175. goto retry;
  3176. } else if (WARN_ON(ret)) {
  3177. goto end;
  3178. }
  3179. state = drm_atomic_state_alloc(dev);
  3180. if (!state) {
  3181. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  3182. goto end;
  3183. }
  3184. state->acquire_ctx = &ctx;
  3185. ret = sde_kms_set_crtc_for_conn(dev, enc, state);
  3186. if (ret)
  3187. goto end;
  3188. ret = drm_atomic_commit(state);
  3189. if (ret)
  3190. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  3191. end:
  3192. if (state)
  3193. drm_atomic_state_put(state);
  3194. drm_modeset_drop_locks(&ctx);
  3195. drm_modeset_acquire_fini(&ctx);
  3196. }
  3197. void sde_kms_display_early_wakeup(struct drm_device *dev,
  3198. const int32_t connector_id)
  3199. {
  3200. struct drm_connector_list_iter conn_iter;
  3201. struct drm_connector *conn;
  3202. struct drm_encoder *drm_enc;
  3203. drm_connector_list_iter_begin(dev, &conn_iter);
  3204. drm_for_each_connector_iter(conn, &conn_iter) {
  3205. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  3206. connector_id != conn->base.id)
  3207. continue;
  3208. if (conn->state && conn->state->best_encoder)
  3209. drm_enc = conn->state->best_encoder;
  3210. else
  3211. drm_enc = conn->encoder;
  3212. if (drm_enc)
  3213. sde_encoder_early_wakeup(drm_enc);
  3214. }
  3215. drm_connector_list_iter_end(&conn_iter);
  3216. }
  3217. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  3218. struct device *dev)
  3219. {
  3220. int i, ret, crtc_id = 0;
  3221. struct drm_device *ddev = dev_get_drvdata(dev);
  3222. struct drm_connector *conn;
  3223. struct drm_connector_list_iter conn_iter;
  3224. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3225. drm_connector_list_iter_begin(ddev, &conn_iter);
  3226. drm_for_each_connector_iter(conn, &conn_iter) {
  3227. uint64_t lp;
  3228. lp = sde_connector_get_lp(conn);
  3229. if (lp != SDE_MODE_DPMS_LP2)
  3230. continue;
  3231. if (sde_encoder_in_clone_mode(conn->encoder))
  3232. continue;
  3233. crtc_id = drm_crtc_index(conn->state->crtc);
  3234. if (priv->disp_thread[crtc_id].thread)
  3235. kthread_flush_worker(
  3236. &priv->disp_thread[crtc_id].worker);
  3237. ret = sde_encoder_wait_for_event(conn->encoder,
  3238. MSM_ENC_TX_COMPLETE);
  3239. if (ret && ret != -EWOULDBLOCK) {
  3240. SDE_ERROR(
  3241. "[conn: %d] wait for commit done returned %d\n",
  3242. conn->base.id, ret);
  3243. } else if (!ret) {
  3244. if (priv->event_thread[crtc_id].thread)
  3245. kthread_flush_worker(
  3246. &priv->event_thread[crtc_id].worker);
  3247. sde_encoder_idle_request(conn->encoder);
  3248. }
  3249. }
  3250. drm_connector_list_iter_end(&conn_iter);
  3251. for (i = 0; i < priv->num_crtcs; i++) {
  3252. if (priv->disp_thread[i].thread)
  3253. kthread_flush_worker(
  3254. &priv->disp_thread[i].worker);
  3255. if (priv->event_thread[i].thread)
  3256. kthread_flush_worker(
  3257. &priv->event_thread[i].worker);
  3258. }
  3259. kthread_flush_worker(&priv->pp_event_worker);
  3260. }
  3261. struct msm_display_mode *sde_kms_get_msm_mode(struct drm_connector_state *conn_state)
  3262. {
  3263. struct sde_connector_state *sde_conn_state;
  3264. if (!conn_state)
  3265. return NULL;
  3266. sde_conn_state = to_sde_connector_state(conn_state);
  3267. return &sde_conn_state->msm_mode;
  3268. }
  3269. static int sde_kms_pm_suspend(struct device *dev)
  3270. {
  3271. struct drm_device *ddev;
  3272. struct drm_modeset_acquire_ctx ctx;
  3273. struct drm_connector *conn;
  3274. struct drm_encoder *enc;
  3275. struct drm_connector_list_iter conn_iter;
  3276. struct drm_atomic_state *state = NULL;
  3277. struct sde_kms *sde_kms;
  3278. int ret = 0, num_crtcs = 0;
  3279. if (!dev)
  3280. return -EINVAL;
  3281. ddev = dev_get_drvdata(dev);
  3282. if (!ddev || !ddev_to_msm_kms(ddev))
  3283. return -EINVAL;
  3284. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  3285. SDE_EVT32(0);
  3286. /* disable hot-plug polling */
  3287. drm_kms_helper_poll_disable(ddev);
  3288. /* if a display stuck in CS trigger a null commit to complete handoff */
  3289. drm_for_each_encoder(enc, ddev) {
  3290. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  3291. _sde_kms_null_commit(ddev, enc);
  3292. }
  3293. /* acquire modeset lock(s) */
  3294. drm_modeset_acquire_init(&ctx, 0);
  3295. retry:
  3296. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  3297. if (ret)
  3298. goto unlock;
  3299. /* save current state for resume */
  3300. if (sde_kms->suspend_state)
  3301. drm_atomic_state_put(sde_kms->suspend_state);
  3302. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  3303. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  3304. ret = PTR_ERR(sde_kms->suspend_state);
  3305. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  3306. sde_kms->suspend_state = NULL;
  3307. goto unlock;
  3308. }
  3309. /* create atomic state to disable all CRTCs */
  3310. state = drm_atomic_state_alloc(ddev);
  3311. if (!state) {
  3312. ret = -ENOMEM;
  3313. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  3314. goto unlock;
  3315. }
  3316. state->acquire_ctx = &ctx;
  3317. drm_connector_list_iter_begin(ddev, &conn_iter);
  3318. drm_for_each_connector_iter(conn, &conn_iter) {
  3319. struct drm_crtc_state *crtc_state;
  3320. uint64_t lp;
  3321. if (!conn->state || !conn->state->crtc ||
  3322. conn->dpms != DRM_MODE_DPMS_ON ||
  3323. sde_encoder_in_clone_mode(conn->encoder))
  3324. continue;
  3325. lp = sde_connector_get_lp(conn);
  3326. if (lp == SDE_MODE_DPMS_LP1) {
  3327. /* transition LP1->LP2 on pm suspend */
  3328. ret = sde_connector_set_property_for_commit(conn, state,
  3329. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  3330. if (ret) {
  3331. DRM_ERROR("failed to set lp2 for conn %d\n",
  3332. conn->base.id);
  3333. drm_connector_list_iter_end(&conn_iter);
  3334. goto unlock;
  3335. }
  3336. }
  3337. if (lp != SDE_MODE_DPMS_LP2) {
  3338. /* force CRTC to be inactive */
  3339. crtc_state = drm_atomic_get_crtc_state(state,
  3340. conn->state->crtc);
  3341. if (IS_ERR_OR_NULL(crtc_state)) {
  3342. DRM_ERROR("failed to get crtc %d state\n",
  3343. conn->state->crtc->base.id);
  3344. drm_connector_list_iter_end(&conn_iter);
  3345. ret = -EINVAL;
  3346. goto unlock;
  3347. }
  3348. if (lp != SDE_MODE_DPMS_LP1)
  3349. crtc_state->active = false;
  3350. ++num_crtcs;
  3351. }
  3352. }
  3353. drm_connector_list_iter_end(&conn_iter);
  3354. /* check for nothing to do */
  3355. if (num_crtcs == 0) {
  3356. DRM_DEBUG("all crtcs are already in the off state\n");
  3357. sde_kms->suspend_block = true;
  3358. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3359. goto unlock;
  3360. }
  3361. /* commit the "disable all" state */
  3362. ret = drm_atomic_commit(state);
  3363. if (ret < 0) {
  3364. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  3365. goto unlock;
  3366. }
  3367. sde_kms->suspend_block = true;
  3368. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3369. unlock:
  3370. if (state) {
  3371. drm_atomic_state_put(state);
  3372. state = NULL;
  3373. }
  3374. if (ret == -EDEADLK) {
  3375. drm_modeset_backoff(&ctx);
  3376. goto retry;
  3377. }
  3378. if ((ret || !num_crtcs) && sde_kms->suspend_state) {
  3379. drm_atomic_state_put(sde_kms->suspend_state);
  3380. sde_kms->suspend_state = NULL;
  3381. }
  3382. drm_modeset_drop_locks(&ctx);
  3383. drm_modeset_acquire_fini(&ctx);
  3384. /*
  3385. * pm runtime driver avoids multiple runtime_suspend API call by
  3386. * checking runtime_status. However, this call helps when there is a
  3387. * race condition between pm_suspend call and doze_suspend/power_off
  3388. * commit. It removes the extra vote from suspend and adds it back
  3389. * later to allow power collapse during pm_suspend call
  3390. */
  3391. pm_runtime_put_sync(dev);
  3392. pm_runtime_get_noresume(dev);
  3393. /* dump clock state before entering suspend */
  3394. if (sde_kms->pm_suspend_clk_dump)
  3395. _sde_kms_dump_clks_state(sde_kms);
  3396. return ret;
  3397. }
  3398. static int sde_kms_pm_resume(struct device *dev)
  3399. {
  3400. struct drm_device *ddev;
  3401. struct sde_kms *sde_kms;
  3402. struct drm_modeset_acquire_ctx ctx;
  3403. int ret, i;
  3404. if (!dev)
  3405. return -EINVAL;
  3406. ddev = dev_get_drvdata(dev);
  3407. if (!ddev || !ddev_to_msm_kms(ddev))
  3408. return -EINVAL;
  3409. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  3410. SDE_EVT32(sde_kms->suspend_state != NULL);
  3411. if (sde_kms->suspend_state)
  3412. drm_mode_config_reset(ddev);
  3413. drm_modeset_acquire_init(&ctx, 0);
  3414. retry:
  3415. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  3416. if (ret == -EDEADLK) {
  3417. drm_modeset_backoff(&ctx);
  3418. goto retry;
  3419. } else if (WARN_ON(ret)) {
  3420. goto end;
  3421. }
  3422. sde_kms->suspend_block = false;
  3423. if (sde_kms->suspend_state) {
  3424. sde_kms->suspend_state->acquire_ctx = &ctx;
  3425. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  3426. ret = drm_atomic_helper_commit_duplicated_state(
  3427. sde_kms->suspend_state, &ctx);
  3428. if (ret != -EDEADLK)
  3429. break;
  3430. drm_modeset_backoff(&ctx);
  3431. }
  3432. if (ret < 0)
  3433. DRM_ERROR("failed to restore state, %d\n", ret);
  3434. drm_atomic_state_put(sde_kms->suspend_state);
  3435. sde_kms->suspend_state = NULL;
  3436. }
  3437. end:
  3438. drm_modeset_drop_locks(&ctx);
  3439. drm_modeset_acquire_fini(&ctx);
  3440. /* enable hot-plug polling */
  3441. drm_kms_helper_poll_enable(ddev);
  3442. return 0;
  3443. }
  3444. static const struct msm_kms_funcs kms_funcs = {
  3445. .hw_init = sde_kms_hw_init,
  3446. .postinit = sde_kms_postinit,
  3447. .irq_preinstall = sde_irq_preinstall,
  3448. .irq_postinstall = sde_irq_postinstall,
  3449. .irq_uninstall = sde_irq_uninstall,
  3450. .irq = sde_irq,
  3451. .preclose = sde_kms_preclose,
  3452. .lastclose = sde_kms_lastclose,
  3453. .prepare_fence = sde_kms_prepare_fence,
  3454. .prepare_commit = sde_kms_prepare_commit,
  3455. .commit = sde_kms_commit,
  3456. .complete_commit = sde_kms_complete_commit,
  3457. .get_msm_mode = sde_kms_get_msm_mode,
  3458. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  3459. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  3460. .check_modified_format = sde_format_check_modified_format,
  3461. .atomic_check = sde_kms_atomic_check,
  3462. .get_format = sde_get_msm_format,
  3463. .round_pixclk = sde_kms_round_pixclk,
  3464. .display_early_wakeup = sde_kms_display_early_wakeup,
  3465. .pm_suspend = sde_kms_pm_suspend,
  3466. .pm_resume = sde_kms_pm_resume,
  3467. .destroy = sde_kms_destroy,
  3468. .debugfs_destroy = sde_kms_debugfs_destroy,
  3469. .cont_splash_config = sde_kms_cont_splash_config,
  3470. .register_events = _sde_kms_register_events,
  3471. .get_address_space = _sde_kms_get_address_space,
  3472. .get_address_space_device = _sde_kms_get_address_space_device,
  3473. .postopen = _sde_kms_post_open,
  3474. .check_for_splash = sde_kms_check_for_splash,
  3475. .get_mixer_count = sde_kms_get_mixer_count,
  3476. .get_dsc_count = sde_kms_get_dsc_count,
  3477. };
  3478. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  3479. {
  3480. int i;
  3481. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  3482. if (!sde_kms->aspace[i])
  3483. continue;
  3484. msm_gem_address_space_put(sde_kms->aspace[i]);
  3485. sde_kms->aspace[i] = NULL;
  3486. }
  3487. return 0;
  3488. }
  3489. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  3490. {
  3491. struct msm_mmu *mmu;
  3492. struct resource *res;
  3493. struct platform_device *pdev;
  3494. int i, ret;
  3495. #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0))
  3496. int early_map = 0;
  3497. #endif
  3498. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  3499. return -EINVAL;
  3500. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  3501. struct msm_gem_address_space *aspace;
  3502. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  3503. if (IS_ERR(mmu)) {
  3504. ret = PTR_ERR(mmu);
  3505. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  3506. i, ret);
  3507. continue;
  3508. }
  3509. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  3510. mmu, "sde");
  3511. if (IS_ERR(aspace)) {
  3512. ret = PTR_ERR(aspace);
  3513. mmu->funcs->destroy(mmu);
  3514. goto fail;
  3515. }
  3516. sde_kms->aspace[i] = aspace;
  3517. aspace->domain_attached = true;
  3518. /* Mapping splash memory block */
  3519. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  3520. sde_kms->splash_data.num_splash_regions) {
  3521. ret = _sde_kms_map_all_splash_regions(sde_kms);
  3522. if (ret) {
  3523. SDE_ERROR("failed to map ret:%d\n", ret);
  3524. goto enable_trans_fail;
  3525. }
  3526. }
  3527. if (i == MSM_SMMU_DOMAIN_UNSECURE && sde_kms->catalog->hw_fence_rev) {
  3528. pdev = to_platform_device(sde_kms->dev->dev);
  3529. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipcc_reg");
  3530. if (!res) {
  3531. SDE_DEBUG("failed to get resource ipcc_reg, cannot map ipcc\n");
  3532. sde_kms->catalog->hw_fence_rev = 0;
  3533. } else {
  3534. sde_kms->ipcc_base_addr = res->start;
  3535. ret = _sde_kms_one2one_mem_map_ipcc_reg(sde_kms, resource_size(res),
  3536. HW_FENCE_IPCC_PROTOCOLp_CLIENTc(res->start,
  3537. sde_kms->catalog->ipcc_protocol_id,
  3538. HW_FENCE_IPCC_CLIENT_DPU));
  3539. /* if mapping fails disable hw-fences */
  3540. if (ret)
  3541. sde_kms->catalog->hw_fence_rev = 0;
  3542. }
  3543. }
  3544. /*
  3545. * disable early-map which would have been enabled during
  3546. * bootup by smmu through the device-tree hint for cont-spash
  3547. */
  3548. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3549. ret = mmu->funcs->enable_smmu_translations(mmu);
  3550. if (ret) {
  3551. SDE_ERROR("failed to enable_s1_translations ret:%d\n", ret);
  3552. goto enable_trans_fail;
  3553. }
  3554. #else
  3555. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  3556. &early_map);
  3557. if (ret) {
  3558. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  3559. ret, early_map);
  3560. goto enable_trans_fail;
  3561. }
  3562. #endif
  3563. }
  3564. sde_kms->base.aspace = sde_kms->aspace[0];
  3565. return 0;
  3566. enable_trans_fail:
  3567. _sde_kms_unmap_all_splash_regions(sde_kms);
  3568. fail:
  3569. _sde_kms_mmu_destroy(sde_kms);
  3570. return ret;
  3571. }
  3572. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  3573. {
  3574. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  3575. return;
  3576. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  3577. }
  3578. static void sde_kms_init_hw_fences(struct sde_kms *sde_kms)
  3579. {
  3580. if (!sde_kms || !sde_kms->hw_mdp)
  3581. return;
  3582. if (sde_kms->hw_mdp->ops.setup_hw_fences)
  3583. sde_kms->hw_mdp->ops.setup_hw_fences(sde_kms->hw_mdp,
  3584. sde_kms->catalog->ipcc_protocol_id, sde_kms->ipcc_base_addr);
  3585. }
  3586. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  3587. {
  3588. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  3589. return;
  3590. if (sde_kms->hw_mdp->ops.reset_ubwc)
  3591. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  3592. sde_kms->catalog);
  3593. }
  3594. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  3595. {
  3596. struct sde_vbif_set_qos_params qos_params;
  3597. struct sde_mdss_cfg *catalog;
  3598. if (!sde_kms->catalog)
  3599. return;
  3600. catalog = sde_kms->catalog;
  3601. memset(&qos_params, 0, sizeof(qos_params));
  3602. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  3603. qos_params.xin_id = catalog->dma_cfg.xin_id;
  3604. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  3605. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  3606. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  3607. }
  3608. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  3609. {
  3610. struct sde_hw_uidle *uidle;
  3611. if (!sde_kms) {
  3612. SDE_ERROR("invalid kms\n");
  3613. return -EINVAL;
  3614. }
  3615. uidle = sde_kms->hw_uidle;
  3616. if (uidle && uidle->ops.active_override_enable)
  3617. uidle->ops.active_override_enable(uidle, enable);
  3618. return 0;
  3619. }
  3620. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  3621. {
  3622. struct device *cpu_dev;
  3623. int cpu = 0;
  3624. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  3625. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3626. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3627. return;
  3628. }
  3629. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3630. cpu_dev = get_cpu_device(cpu);
  3631. if (!cpu_dev) {
  3632. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3633. cpu);
  3634. continue;
  3635. }
  3636. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3637. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  3638. cpu_irq_latency);
  3639. else
  3640. dev_pm_qos_add_request(cpu_dev,
  3641. &sde_kms->pm_qos_irq_req[cpu],
  3642. DEV_PM_QOS_RESUME_LATENCY,
  3643. cpu_irq_latency);
  3644. }
  3645. }
  3646. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  3647. {
  3648. struct device *cpu_dev;
  3649. int cpu = 0;
  3650. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3651. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3652. return;
  3653. }
  3654. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3655. cpu_dev = get_cpu_device(cpu);
  3656. if (!cpu_dev) {
  3657. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3658. cpu);
  3659. continue;
  3660. }
  3661. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3662. dev_pm_qos_remove_request(
  3663. &sde_kms->pm_qos_irq_req[cpu]);
  3664. }
  3665. }
  3666. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  3667. {
  3668. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3669. mutex_lock(&priv->phandle.phandle_lock);
  3670. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3671. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3672. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3673. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3674. mutex_unlock(&priv->phandle.phandle_lock);
  3675. }
  3676. static void sde_kms_irq_affinity_notify(
  3677. struct irq_affinity_notify *affinity_notify,
  3678. const cpumask_t *mask)
  3679. {
  3680. struct msm_drm_private *priv;
  3681. struct sde_kms *sde_kms = container_of(affinity_notify,
  3682. struct sde_kms, affinity_notify);
  3683. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3684. return;
  3685. priv = sde_kms->dev->dev_private;
  3686. mutex_lock(&priv->phandle.phandle_lock);
  3687. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3688. // save irq cpu mask
  3689. sde_kms->irq_cpu_mask = *mask;
  3690. // request vote with updated irq cpu mask
  3691. if (atomic_read(&sde_kms->irq_vote_count))
  3692. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3693. mutex_unlock(&priv->phandle.phandle_lock);
  3694. }
  3695. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3696. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3697. {
  3698. struct sde_kms *sde_kms = usr;
  3699. struct msm_kms *msm_kms;
  3700. msm_kms = &sde_kms->base;
  3701. if (!sde_kms)
  3702. return;
  3703. SDE_DEBUG("event_type:%d\n", event_type);
  3704. SDE_EVT32_VERBOSE(event_type);
  3705. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3706. sde_irq_update(msm_kms, true);
  3707. sde_kms->first_kickoff = true;
  3708. /**
  3709. * Rotator sid and hw fences need to be programmed since uefi doesn't
  3710. * configure them during continuous splash
  3711. */
  3712. sde_kms_init_rot_sid_hw(sde_kms);
  3713. sde_kms_init_hw_fences(sde_kms);
  3714. if (sde_kms->splash_data.num_splash_displays ||
  3715. sde_in_trusted_vm(sde_kms))
  3716. return;
  3717. sde_vbif_init_memtypes(sde_kms);
  3718. sde_kms_init_shared_hw(sde_kms);
  3719. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3720. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3721. sde_irq_update(msm_kms, false);
  3722. sde_kms->first_kickoff = false;
  3723. if (sde_in_trusted_vm(sde_kms))
  3724. return;
  3725. _sde_kms_active_override(sde_kms, true);
  3726. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3727. sde_vbif_axi_halt_request(sde_kms);
  3728. }
  3729. }
  3730. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3731. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3732. {
  3733. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3734. int rc = -EINVAL;
  3735. SDE_DEBUG("\n");
  3736. rc = pm_runtime_resume_and_get(sde_kms->dev->dev);
  3737. rc = (rc > 0) ? 0 : rc;
  3738. SDE_EVT32(rc, genpd->device_count);
  3739. return rc;
  3740. }
  3741. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3742. {
  3743. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3744. SDE_DEBUG("\n");
  3745. pm_runtime_put_sync(sde_kms->dev->dev);
  3746. SDE_EVT32(genpd->device_count);
  3747. return 0;
  3748. }
  3749. static int _sde_kms_get_demura_plane_data(struct sde_splash_data *data)
  3750. {
  3751. int i = 0;
  3752. int ret = 0;
  3753. int count = 0;
  3754. struct device_node *parent, *node;
  3755. struct resource r;
  3756. char node_name[DEMURA_REGION_NAME_MAX];
  3757. struct sde_splash_mem *mem;
  3758. struct sde_splash_display *splash_display;
  3759. if (!data->num_splash_displays) {
  3760. SDE_DEBUG("no splash displays. skipping\n");
  3761. return 0;
  3762. }
  3763. /**
  3764. * It is expected that each active demura block will have
  3765. * its own memory region defined.
  3766. */
  3767. parent = of_find_node_by_path("/reserved-memory");
  3768. for (i = 0; i < data->num_splash_displays; i++) {
  3769. splash_display = &data->splash_display[i];
  3770. snprintf(&node_name[0], DEMURA_REGION_NAME_MAX,
  3771. "demura_region_%d", i);
  3772. splash_display->demura = NULL;
  3773. node = of_find_node_by_name(parent, node_name);
  3774. if (!node) {
  3775. SDE_DEBUG("no Demura node %s! disp count: %d\n",
  3776. node_name, data->num_splash_displays);
  3777. continue;
  3778. } else if (of_address_to_resource(node, 0, &r)) {
  3779. SDE_ERROR("invalid data for:%s\n", node_name);
  3780. ret = -EINVAL;
  3781. break;
  3782. }
  3783. mem = &data->demura_mem[i];
  3784. mem->splash_buf_base = (unsigned long)r.start;
  3785. mem->splash_buf_size = (r.end - r.start) + 1;
  3786. if (!mem->splash_buf_base && !mem->splash_buf_size) {
  3787. SDE_DEBUG("dummy splash mem for disp %d. Skipping\n",
  3788. (i+1));
  3789. continue;
  3790. } else if (!mem->splash_buf_base || !mem->splash_buf_size) {
  3791. SDE_ERROR("mem for disp %d invalid: add:%lx size:%lx\n",
  3792. (i+1), mem->splash_buf_base,
  3793. mem->splash_buf_size);
  3794. continue;
  3795. }
  3796. mem->ref_cnt = 0;
  3797. splash_display->demura = mem;
  3798. count++;
  3799. SDE_DEBUG("demura mem for disp:%d add:%lx size:%x\n", (i + 1),
  3800. mem->splash_buf_base,
  3801. mem->splash_buf_size);
  3802. }
  3803. if (!ret && !count)
  3804. SDE_DEBUG("no demura regions for cont. splash found!\n");
  3805. return ret;
  3806. }
  3807. static int _sde_kms_get_splash_data(struct sde_splash_data *data)
  3808. {
  3809. int i = 0;
  3810. int ret = 0;
  3811. struct device_node *parent, *node, *node1;
  3812. struct resource r, r1;
  3813. const char *node_name = "splash_region";
  3814. struct sde_splash_mem *mem;
  3815. bool share_splash_mem = false;
  3816. int num_displays, num_regions;
  3817. struct sde_splash_display *splash_display;
  3818. if (!data)
  3819. return -EINVAL;
  3820. memset(data, 0, sizeof(*data));
  3821. parent = of_find_node_by_path("/reserved-memory");
  3822. if (!parent) {
  3823. SDE_ERROR("failed to find reserved-memory node\n");
  3824. return -EINVAL;
  3825. }
  3826. node = of_find_node_by_name(parent, node_name);
  3827. if (!node) {
  3828. SDE_DEBUG("failed to find node %s\n", node_name);
  3829. return -EINVAL;
  3830. }
  3831. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3832. if (!node1)
  3833. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3834. /**
  3835. * Support sharing a single splash memory for all the built in displays
  3836. * and also independent splash region per displays. Incase of
  3837. * independent splash region for each connected display, dtsi node of
  3838. * cont_splash_region should be collection of all memory regions
  3839. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3840. */
  3841. num_displays = dsi_display_get_num_of_displays();
  3842. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3843. data->num_splash_displays = num_displays;
  3844. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3845. if (num_displays > num_regions) {
  3846. share_splash_mem = true;
  3847. pr_info(":%d displays share same splash buf\n", num_displays);
  3848. }
  3849. for (i = 0; i < num_displays; i++) {
  3850. splash_display = &data->splash_display[i];
  3851. if (!i || !share_splash_mem) {
  3852. if (of_address_to_resource(node, i, &r)) {
  3853. SDE_ERROR("invalid data for:%s\n", node_name);
  3854. return -EINVAL;
  3855. }
  3856. mem = &data->splash_mem[i];
  3857. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3858. SDE_DEBUG("failed to find ramdump memory\n");
  3859. mem->ramdump_base = 0;
  3860. mem->ramdump_size = 0;
  3861. } else {
  3862. mem->ramdump_base = (unsigned long)r1.start;
  3863. mem->ramdump_size = (r1.end - r1.start) + 1;
  3864. }
  3865. mem->splash_buf_base = (unsigned long)r.start;
  3866. mem->splash_buf_size = (r.end - r.start) + 1;
  3867. mem->ref_cnt = 0;
  3868. splash_display->splash = mem;
  3869. data->num_splash_regions++;
  3870. } else {
  3871. data->splash_display[i].splash = &data->splash_mem[0];
  3872. }
  3873. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3874. splash_display->splash->splash_buf_base,
  3875. splash_display->splash->splash_buf_size);
  3876. }
  3877. data->type = SDE_SPLASH_HANDOFF;
  3878. ret = _sde_kms_get_demura_plane_data(data);
  3879. return ret;
  3880. }
  3881. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3882. struct platform_device *platformdev)
  3883. {
  3884. int rc = -EINVAL;
  3885. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3886. if (IS_ERR(sde_kms->mmio)) {
  3887. rc = PTR_ERR(sde_kms->mmio);
  3888. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3889. sde_kms->mmio = NULL;
  3890. goto error;
  3891. }
  3892. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3893. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3894. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3895. sde_kms->mmio_len,
  3896. msm_get_phys_addr(platformdev, "mdp_phys"),
  3897. SDE_DBG_SDE);
  3898. if (rc)
  3899. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3900. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys", "vbif_phys");
  3901. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3902. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3903. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3904. sde_kms->vbif[VBIF_RT] = NULL;
  3905. goto error;
  3906. }
  3907. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev, "vbif_phys");
  3908. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3909. sde_kms->vbif_len[VBIF_RT],
  3910. msm_get_phys_addr(platformdev, "vbif_phys"),
  3911. SDE_DBG_VBIF_RT);
  3912. if (rc)
  3913. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3914. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys", "vbif_nrt_phys");
  3915. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3916. sde_kms->vbif[VBIF_NRT] = NULL;
  3917. SDE_DEBUG("VBIF NRT is not defined");
  3918. } else {
  3919. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev, "vbif_nrt_phys");
  3920. }
  3921. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys", "regdma_phys");
  3922. if (IS_ERR(sde_kms->reg_dma)) {
  3923. sde_kms->reg_dma = NULL;
  3924. SDE_DEBUG("REG_DMA is not defined");
  3925. } else {
  3926. unsigned long mdp_addr = msm_get_phys_addr(platformdev, "mdp_phys");
  3927. sde_kms->reg_dma_len = msm_iomap_size(platformdev, "regdma_phys");
  3928. sde_kms->reg_dma_off = msm_get_phys_addr(platformdev, "regdma_phys") - mdp_addr;
  3929. rc = sde_dbg_reg_register_base("reg_dma", sde_kms->reg_dma,
  3930. sde_kms->reg_dma_len,
  3931. msm_get_phys_addr(platformdev, "regdma_phys"),
  3932. SDE_DBG_LUTDMA);
  3933. if (rc)
  3934. SDE_ERROR("dbg base register reg_dma failed: %d\n", rc);
  3935. }
  3936. sde_kms->sid = msm_ioremap(platformdev, "sid_phys", "sid_phys");
  3937. if (IS_ERR(sde_kms->sid)) {
  3938. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3939. sde_kms->sid = NULL;
  3940. } else {
  3941. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3942. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3943. sde_kms->sid_len,
  3944. msm_get_phys_addr(platformdev, "sid_phys"),
  3945. SDE_DBG_SID);
  3946. if (rc)
  3947. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3948. }
  3949. error:
  3950. return rc;
  3951. }
  3952. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3953. struct sde_kms *sde_kms)
  3954. {
  3955. int rc = 0;
  3956. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3957. sde_kms->genpd.name = dev->unique;
  3958. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3959. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3960. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3961. if (rc < 0) {
  3962. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3963. sde_kms->genpd.name, rc);
  3964. return rc;
  3965. }
  3966. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3967. &sde_kms->genpd);
  3968. if (rc < 0) {
  3969. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3970. sde_kms->genpd.name, rc);
  3971. pm_genpd_remove(&sde_kms->genpd);
  3972. return rc;
  3973. }
  3974. sde_kms->genpd_init = true;
  3975. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3976. }
  3977. return rc;
  3978. }
  3979. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3980. struct drm_device *dev,
  3981. struct msm_drm_private *priv)
  3982. {
  3983. struct sde_rm *rm = NULL;
  3984. int i, rc = -EINVAL;
  3985. sde_kms->catalog = sde_hw_catalog_init(dev);
  3986. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3987. rc = PTR_ERR(sde_kms->catalog);
  3988. if (!sde_kms->catalog)
  3989. rc = -EINVAL;
  3990. SDE_ERROR("catalog init failed: %d\n", rc);
  3991. sde_kms->catalog = NULL;
  3992. goto power_error;
  3993. }
  3994. sde_kms->core_rev = sde_kms->catalog->hw_rev;
  3995. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3996. /* initialize power domain if defined */
  3997. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3998. if (rc) {
  3999. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  4000. goto genpd_err;
  4001. }
  4002. rc = _sde_kms_mmu_init(sde_kms);
  4003. if (rc) {
  4004. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  4005. goto power_error;
  4006. }
  4007. /* Initialize reg dma block which is a singleton */
  4008. sde_kms->catalog->dma_cfg.base_off = sde_kms->reg_dma_off;
  4009. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  4010. sde_kms->dev);
  4011. if (rc) {
  4012. SDE_ERROR("failed: reg dma init failed\n");
  4013. goto power_error;
  4014. }
  4015. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  4016. rm = &sde_kms->rm;
  4017. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  4018. sde_kms->dev);
  4019. if (rc) {
  4020. SDE_ERROR("rm init failed: %d\n", rc);
  4021. goto power_error;
  4022. }
  4023. sde_kms->rm_init = true;
  4024. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  4025. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  4026. rc = PTR_ERR(sde_kms->hw_intr);
  4027. SDE_ERROR("hw_intr init failed: %d\n", rc);
  4028. sde_kms->hw_intr = NULL;
  4029. goto hw_intr_init_err;
  4030. }
  4031. /*
  4032. * Attempt continuous splash handoff only if reserved
  4033. * splash memory is found & release resources on any error
  4034. * in finding display hw config in splash
  4035. */
  4036. if (sde_kms->splash_data.num_splash_regions) {
  4037. struct sde_splash_display *display;
  4038. int ret, display_count =
  4039. sde_kms->splash_data.num_splash_displays;
  4040. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  4041. &sde_kms->splash_data, sde_kms->catalog);
  4042. for (i = 0; i < display_count; i++) {
  4043. display = &sde_kms->splash_data.splash_display[i];
  4044. /*
  4045. * free splash region on resource init failure and
  4046. * cont-splash disabled case
  4047. */
  4048. if (!display->cont_splash_enabled || ret)
  4049. _sde_kms_free_splash_display_data(
  4050. sde_kms, display);
  4051. }
  4052. }
  4053. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  4054. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  4055. rc = PTR_ERR(sde_kms->hw_mdp);
  4056. if (!sde_kms->hw_mdp)
  4057. rc = -EINVAL;
  4058. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  4059. sde_kms->hw_mdp = NULL;
  4060. goto power_error;
  4061. }
  4062. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  4063. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  4064. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  4065. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  4066. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  4067. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  4068. if (!sde_kms->hw_vbif[vbif_idx])
  4069. rc = -EINVAL;
  4070. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  4071. sde_kms->hw_vbif[vbif_idx] = NULL;
  4072. goto power_error;
  4073. }
  4074. }
  4075. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  4076. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  4077. sde_kms->mmio_len, sde_kms->catalog);
  4078. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  4079. rc = PTR_ERR(sde_kms->hw_uidle);
  4080. if (!sde_kms->hw_uidle)
  4081. rc = -EINVAL;
  4082. /* uidle is optional, so do not make it a fatal error */
  4083. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  4084. sde_kms->hw_uidle = NULL;
  4085. rc = 0;
  4086. }
  4087. } else {
  4088. sde_kms->hw_uidle = NULL;
  4089. }
  4090. if (sde_kms->sid) {
  4091. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  4092. sde_kms->sid_len, sde_kms->catalog);
  4093. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  4094. rc = PTR_ERR(sde_kms->hw_sid);
  4095. SDE_ERROR("failed to init sid %d\n", rc);
  4096. sde_kms->hw_sid = NULL;
  4097. goto power_error;
  4098. }
  4099. }
  4100. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  4101. &priv->phandle, "core_clk");
  4102. if (rc) {
  4103. SDE_ERROR("failed to init perf %d\n", rc);
  4104. goto perf_err;
  4105. }
  4106. /*
  4107. * set the disable_immediate flag when driver supports the precise vsync
  4108. * timestamp as the DRM hooks for vblank timestamp/counters would be set
  4109. * based on the feature
  4110. */
  4111. if (test_bit(SDE_FEATURE_HW_VSYNC_TS, sde_kms->catalog->features))
  4112. dev->vblank_disable_immediate = true;
  4113. /*
  4114. * _sde_kms_drm_obj_init should create the DRM related objects
  4115. * i.e. CRTCs, planes, encoders, connectors and so forth
  4116. */
  4117. rc = _sde_kms_drm_obj_init(sde_kms);
  4118. if (rc) {
  4119. SDE_ERROR("modeset init failed: %d\n", rc);
  4120. goto drm_obj_init_err;
  4121. }
  4122. return 0;
  4123. genpd_err:
  4124. drm_obj_init_err:
  4125. sde_core_perf_destroy(&sde_kms->perf);
  4126. hw_intr_init_err:
  4127. perf_err:
  4128. power_error:
  4129. return rc;
  4130. }
  4131. int _sde_kms_get_tvm_inclusion_mem(struct sde_mdss_cfg *catalog, struct list_head *mem_list)
  4132. {
  4133. struct list_head temp_head;
  4134. struct msm_io_mem_entry *io_mem;
  4135. int rc, i = 0;
  4136. INIT_LIST_HEAD(&temp_head);
  4137. for (i = 0; i < catalog->tvm_reg_count; i++) {
  4138. struct resource *res = &catalog->tvm_reg[i];
  4139. io_mem = kzalloc(sizeof(struct msm_io_mem_entry), GFP_KERNEL);
  4140. if (!io_mem) {
  4141. rc = -ENOMEM;
  4142. goto parse_fail;
  4143. }
  4144. io_mem->base = res->start;
  4145. io_mem->size = resource_size(res);
  4146. list_add(&io_mem->list, &temp_head);
  4147. }
  4148. list_splice(&temp_head, mem_list);
  4149. return 0;
  4150. parse_fail:
  4151. msm_dss_clean_io_mem(&temp_head);
  4152. return rc;
  4153. }
  4154. #ifdef CONFIG_DRM_SDE_VM
  4155. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  4156. {
  4157. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  4158. int rc = 0;
  4159. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  4160. if (rc) {
  4161. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  4162. return rc;
  4163. }
  4164. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  4165. if (rc) {
  4166. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  4167. return rc;
  4168. }
  4169. rc = msm_dss_get_io_irq(pdev, &io_res->irq, GH_IRQ_LABEL_SDE);
  4170. if (rc) {
  4171. SDE_ERROR("failed to get io irq for KMS");
  4172. return rc;
  4173. }
  4174. rc = _sde_kms_get_tvm_inclusion_mem(sde_kms->catalog, &io_res->mem);
  4175. if (rc) {
  4176. SDE_ERROR("failed to get tvm inclusion mem ranges");
  4177. return rc;
  4178. }
  4179. return rc;
  4180. }
  4181. #endif
  4182. static int sde_kms_hw_init(struct msm_kms *kms)
  4183. {
  4184. struct sde_kms *sde_kms;
  4185. struct drm_device *dev;
  4186. struct msm_drm_private *priv;
  4187. struct platform_device *platformdev;
  4188. int irq_num, rc = -EINVAL;
  4189. if (!kms) {
  4190. SDE_ERROR("invalid kms\n");
  4191. goto end;
  4192. }
  4193. sde_kms = to_sde_kms(kms);
  4194. dev = sde_kms->dev;
  4195. if (!dev || !dev->dev) {
  4196. SDE_ERROR("invalid device\n");
  4197. goto end;
  4198. }
  4199. platformdev = to_platform_device(dev->dev);
  4200. priv = dev->dev_private;
  4201. if (!priv) {
  4202. SDE_ERROR("invalid private data\n");
  4203. goto end;
  4204. }
  4205. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  4206. if (rc)
  4207. goto error;
  4208. rc = _sde_kms_get_splash_data(&sde_kms->splash_data);
  4209. if (rc)
  4210. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  4211. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  4212. if (rc)
  4213. goto error;
  4214. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  4215. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  4216. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  4217. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  4218. mutex_init(&sde_kms->secure_transition_lock);
  4219. atomic_set(&sde_kms->detach_sec_cb, 0);
  4220. atomic_set(&sde_kms->detach_all_cb, 0);
  4221. atomic_set(&sde_kms->irq_vote_count, 0);
  4222. /*
  4223. * Support format modifiers for compression etc.
  4224. */
  4225. dev->mode_config.allow_fb_modifiers = true;
  4226. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  4227. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  4228. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  4229. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  4230. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  4231. if (sde_in_trusted_vm(sde_kms)) {
  4232. rc = sde_vm_trusted_init(sde_kms);
  4233. sde_dbg_set_hw_ownership_status(false);
  4234. } else {
  4235. rc = sde_vm_primary_init(sde_kms);
  4236. sde_dbg_set_hw_ownership_status(true);
  4237. }
  4238. if (rc) {
  4239. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  4240. goto error;
  4241. }
  4242. return 0;
  4243. error:
  4244. _sde_kms_hw_destroy(sde_kms, platformdev);
  4245. end:
  4246. return rc;
  4247. }
  4248. struct msm_kms *sde_kms_init(struct drm_device *dev)
  4249. {
  4250. struct msm_drm_private *priv;
  4251. struct sde_kms *sde_kms;
  4252. if (!dev || !dev->dev_private) {
  4253. SDE_ERROR("drm device node invalid\n");
  4254. return ERR_PTR(-EINVAL);
  4255. }
  4256. priv = dev->dev_private;
  4257. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  4258. if (!sde_kms) {
  4259. SDE_ERROR("failed to allocate sde kms\n");
  4260. return ERR_PTR(-ENOMEM);
  4261. }
  4262. msm_kms_init(&sde_kms->base, &kms_funcs);
  4263. sde_kms->dev = dev;
  4264. return &sde_kms->base;
  4265. }
  4266. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  4267. {
  4268. struct dsi_display *display;
  4269. struct sde_splash_display *handoff_display;
  4270. int i;
  4271. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  4272. handoff_display = &sde_kms->splash_data.splash_display[i];
  4273. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  4274. if (handoff_display->cont_splash_enabled)
  4275. _sde_kms_free_splash_display_data(sde_kms,
  4276. handoff_display);
  4277. dsi_display_set_active_state(display, false);
  4278. }
  4279. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  4280. }
  4281. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms,
  4282. struct drm_atomic_state *state)
  4283. {
  4284. struct drm_device *dev;
  4285. struct msm_drm_private *priv;
  4286. struct sde_splash_display *handoff_display;
  4287. struct dsi_display *display;
  4288. int ret, i;
  4289. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  4290. SDE_ERROR("invalid params\n");
  4291. return -EINVAL;
  4292. }
  4293. dev = sde_kms->dev;
  4294. priv = dev->dev_private;
  4295. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  4296. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  4297. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  4298. &sde_kms->splash_data, sde_kms->catalog);
  4299. if (ret) {
  4300. SDE_ERROR("invalid cont splash init, ret:%d\n", ret);
  4301. return -EINVAL;
  4302. }
  4303. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  4304. handoff_display = &sde_kms->splash_data.splash_display[i];
  4305. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  4306. if (!handoff_display->cont_splash_enabled || ret)
  4307. _sde_kms_free_splash_display_data(sde_kms,
  4308. handoff_display);
  4309. else
  4310. dsi_display_set_active_state(display, true);
  4311. }
  4312. if (sde_kms->splash_data.num_splash_displays != 1) {
  4313. SDE_ERROR("no. of displays not supported:%d\n",
  4314. sde_kms->splash_data.num_splash_displays);
  4315. goto error;
  4316. }
  4317. ret = sde_kms_cont_splash_config(&sde_kms->base, state);
  4318. if (ret) {
  4319. SDE_ERROR("error in setting handoff configs\n");
  4320. goto error;
  4321. }
  4322. /**
  4323. * fill-in vote for the continuous splash hanodff path, which will be
  4324. * removed on the successful first commit.
  4325. */
  4326. ret = pm_runtime_resume_and_get(sde_kms->dev->dev);
  4327. if (ret < 0) {
  4328. SDE_ERROR("failed to enable power resource %d\n", ret);
  4329. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  4330. goto error;
  4331. }
  4332. return 0;
  4333. error:
  4334. return ret;
  4335. }
  4336. static int _sde_kms_register_events(struct msm_kms *kms,
  4337. struct drm_mode_object *obj, u32 event, bool en)
  4338. {
  4339. int ret = 0;
  4340. struct drm_crtc *crtc;
  4341. struct drm_connector *conn;
  4342. struct sde_kms *sde_kms;
  4343. if (!kms || !obj) {
  4344. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  4345. return -EINVAL;
  4346. }
  4347. sde_kms = to_sde_kms(kms);
  4348. sde_vm_lock(sde_kms);
  4349. if (!sde_vm_owns_hw(sde_kms)) {
  4350. sde_vm_unlock(sde_kms);
  4351. SDE_DEBUG("HW is owned by other VM\n");
  4352. return -EACCES;
  4353. }
  4354. /* check vm ownership, if event registration requires HW access */
  4355. switch (obj->type) {
  4356. case DRM_MODE_OBJECT_CRTC:
  4357. crtc = obj_to_crtc(obj);
  4358. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  4359. break;
  4360. case DRM_MODE_OBJECT_CONNECTOR:
  4361. conn = obj_to_connector(obj);
  4362. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  4363. en);
  4364. break;
  4365. }
  4366. sde_vm_unlock(sde_kms);
  4367. return ret;
  4368. }
  4369. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  4370. {
  4371. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  4372. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  4373. }
  4374. void sde_kms_add_data_to_minidump_va(struct sde_kms *sde_kms)
  4375. {
  4376. struct msm_drm_private *priv;
  4377. struct sde_crtc *sde_crtc;
  4378. struct sde_crtc_state *cstate;
  4379. struct sde_connector *sde_conn;
  4380. struct sde_connector_state *conn_state;
  4381. u32 i;
  4382. priv = sde_kms->dev->dev_private;
  4383. sde_mini_dump_add_va_region("sde_kms", sizeof(*sde_kms), sde_kms);
  4384. for (i = 0; i < priv->num_crtcs; i++) {
  4385. sde_crtc = to_sde_crtc(priv->crtcs[i]);
  4386. cstate = to_sde_crtc_state(priv->crtcs[i]->state);
  4387. sde_mini_dump_add_va_region("sde_crtc", sizeof(*sde_crtc), sde_crtc);
  4388. sde_mini_dump_add_va_region("crtc_state", sizeof(*cstate), cstate);
  4389. }
  4390. for (i = 0; i < priv->num_planes; i++)
  4391. sde_plane_add_data_to_minidump_va(priv->planes[i]);
  4392. for (i = 0; i < priv->num_encoders; i++)
  4393. sde_encoder_add_data_to_minidump_va(priv->encoders[i]);
  4394. for (i = 0; i < priv->num_connectors; i++) {
  4395. sde_conn = to_sde_connector(priv->connectors[i]);
  4396. conn_state = to_sde_connector_state(priv->connectors[i]->state);
  4397. sde_mini_dump_add_va_region("sde_conn", sizeof(*sde_conn), sde_conn);
  4398. sde_mini_dump_add_va_region("conn_state", sizeof(*conn_state), conn_state);
  4399. }
  4400. }