pinctrl-lpi.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/gpio.h>
  7. #include <linux/io.h>
  8. #include <linux/module.h>
  9. #include <linux/of.h>
  10. #include <linux/pinctrl/pinconf-generic.h>
  11. #include <linux/pinctrl/pinconf.h>
  12. #include <linux/pinctrl/pinmux.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/slab.h>
  15. #include <linux/types.h>
  16. #include <linux/ratelimit.h>
  17. #include <linux/clk.h>
  18. #include <linux/bitops.h>
  19. #include <linux/delay.h>
  20. #include <soc/snd_event.h>
  21. #include <dsp/digital-cdc-rsc-mgr.h>
  22. #include <linux/pm_runtime.h>
  23. #include <dsp/audio_notifier.h>
  24. #include "core.h"
  25. #include "pinctrl-utils.h"
  26. #define LPI_AUTO_SUSPEND_DELAY 100 /* delay in msec */
  27. #define LPI_AUTO_SUSPEND_DELAY_ERROR 1 /* delay in msec */
  28. #define LPI_ADDRESS_SIZE 0x20000
  29. #define LPI_SLEW_ADDRESS_SIZE 0x1000
  30. #define LPI_GPIO_REG_VAL_CTL 0x00
  31. #define LPI_GPIO_REG_DIR_CTL 0x04
  32. #define LPI_SLEW_REG_VAL_CTL 0x00
  33. #define LPI_SLEW_RATE_MAX 0x03
  34. #define LPI_SLEW_BITS_SIZE 0x02
  35. #define LPI_SLEW_OFFSET_INVALID 0xFFFFFFFF
  36. #define LPI_GPIO_REG_PULL_SHIFT 0x0
  37. #define LPI_GPIO_REG_PULL_MASK 0x3
  38. #define LPI_GPIO_REG_FUNCTION_SHIFT 0x2
  39. #define LPI_GPIO_REG_FUNCTION_MASK 0x3C
  40. #define LPI_GPIO_REG_OUT_STRENGTH_SHIFT 0x6
  41. #define LPI_GPIO_REG_OUT_STRENGTH_MASK 0x1C0
  42. #define LPI_GPIO_REG_OE_SHIFT 0x9
  43. #define LPI_GPIO_REG_OE_MASK 0x200
  44. #define LPI_GPIO_REG_DIR_SHIFT 0x1
  45. #define LPI_GPIO_REG_DIR_MASK 0x2
  46. #define LPI_GPIO_BIAS_DISABLE 0x0
  47. #define LPI_GPIO_PULL_DOWN 0x1
  48. #define LPI_GPIO_KEEPER 0x2
  49. #define LPI_GPIO_PULL_UP 0x3
  50. #define LPI_GPIO_FUNC_GPIO "gpio"
  51. #define LPI_GPIO_FUNC_FUNC1 "func1"
  52. #define LPI_GPIO_FUNC_FUNC2 "func2"
  53. #define LPI_GPIO_FUNC_FUNC3 "func3"
  54. #define LPI_GPIO_FUNC_FUNC4 "func4"
  55. #define LPI_GPIO_FUNC_FUNC5 "func5"
  56. #define LPI_GPIO_DRV_2_MA 2
  57. #define LPI_GPIO_DRV_4_MA 4
  58. #define LPI_GPIO_DRV_6_MA 6
  59. #define LPI_GPIO_DRV_8_MA 8
  60. #define LPI_GPIO_DRV_10_MA 10
  61. #define LPI_GPIO_DRV_12_MA 12
  62. #define LPI_GPIO_DRV_14_MA 14
  63. #define LPI_GPIO_DRV_16_MA 16
  64. static bool lpi_dev_up;
  65. static struct device *lpi_dev;
  66. static bool initial_boot = false;
  67. /* The index of each function in lpi_gpio_functions[] array */
  68. enum lpi_gpio_func_index {
  69. LPI_GPIO_FUNC_INDEX_GPIO = 0x00,
  70. LPI_GPIO_FUNC_INDEX_FUNC1 = 0x01,
  71. LPI_GPIO_FUNC_INDEX_FUNC2 = 0x02,
  72. LPI_GPIO_FUNC_INDEX_FUNC3 = 0x03,
  73. LPI_GPIO_FUNC_INDEX_FUNC4 = 0x04,
  74. LPI_GPIO_FUNC_INDEX_FUNC5 = 0x05,
  75. };
  76. /**
  77. * struct lpi_gpio_pad - keep current GPIO settings
  78. * @offset: stores one of gpio_offset or slew_offset at a given time.
  79. * @gpio_offset: Nth GPIO in supported GPIOs.
  80. * @slew_offset: Nth GPIO's position in slew register in supported GPIOs.
  81. * @output_enabled: Set to true if GPIO output logic is enabled.
  82. * @value: value of a pin
  83. * @base: stores one of gpio_base or slew_base at a given time.
  84. * @gpio_base: Address base of LPI GPIO PAD.
  85. * @slew_base: Address base of LPI SLEW PAD.
  86. * @lpi_slew_reg: Address for lpi slew reg.
  87. * @pullup: Constant current which flow through GPIO output buffer.
  88. * @strength: No, Low, Medium, High
  89. * @function: See lpi_gpio_functions[]
  90. */
  91. struct lpi_gpio_pad {
  92. u32 offset;
  93. u32 gpio_offset;
  94. u32 slew_offset;
  95. bool output_enabled;
  96. bool value;
  97. char __iomem *base;
  98. char __iomem *gpio_base;
  99. char __iomem *slew_base;
  100. char __iomem *lpi_slew_reg;
  101. unsigned int pullup;
  102. unsigned int strength;
  103. unsigned int function;
  104. };
  105. struct lpi_gpio_state {
  106. struct device *dev;
  107. struct pinctrl_dev *ctrl;
  108. struct gpio_chip chip;
  109. char __iomem *base;
  110. struct clk *lpass_core_hw_vote;
  111. struct clk *lpass_audio_hw_vote;
  112. struct mutex slew_access_lock;
  113. bool core_hw_vote_status;
  114. struct mutex core_hw_vote_lock;
  115. };
  116. static const char *const lpi_gpio_groups[] = {
  117. "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
  118. "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
  119. "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
  120. "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
  121. "gpio29", "gpio30", "gpio31",
  122. };
  123. #define LPI_TLMM_MAX_PINS 100
  124. static u32 lpi_offset[LPI_TLMM_MAX_PINS];
  125. static u32 lpi_slew_offset[LPI_TLMM_MAX_PINS];
  126. static u32 lpi_slew_base[LPI_TLMM_MAX_PINS];
  127. static const char *const lpi_gpio_functions[] = {
  128. [LPI_GPIO_FUNC_INDEX_GPIO] = LPI_GPIO_FUNC_GPIO,
  129. [LPI_GPIO_FUNC_INDEX_FUNC1] = LPI_GPIO_FUNC_FUNC1,
  130. [LPI_GPIO_FUNC_INDEX_FUNC2] = LPI_GPIO_FUNC_FUNC2,
  131. [LPI_GPIO_FUNC_INDEX_FUNC3] = LPI_GPIO_FUNC_FUNC3,
  132. [LPI_GPIO_FUNC_INDEX_FUNC4] = LPI_GPIO_FUNC_FUNC4,
  133. [LPI_GPIO_FUNC_INDEX_FUNC5] = LPI_GPIO_FUNC_FUNC5,
  134. };
  135. int lpi_pinctrl_runtime_suspend(struct device *dev);
  136. static int lpi_gpio_read(struct lpi_gpio_pad *pad, unsigned int addr)
  137. {
  138. int ret = 0;
  139. struct lpi_gpio_state *state = NULL;
  140. static DEFINE_RATELIMIT_STATE(rtl, 1 * HZ, 1);
  141. if (!lpi_dev) {
  142. if (__ratelimit(&rtl))
  143. pr_err_ratelimited("%s: lpi_dev is NULL, return\n",
  144. __func__);
  145. return -EINVAL;
  146. }
  147. state = dev_get_drvdata(lpi_dev);
  148. if (!lpi_dev_up) {
  149. if (__ratelimit(&rtl))
  150. pr_err_ratelimited("%s: ADSP is down due to SSR, return\n",
  151. __func__);
  152. return 0;
  153. }
  154. pm_runtime_get_sync(lpi_dev);
  155. mutex_lock(&state->core_hw_vote_lock);
  156. if (!state->core_hw_vote_status) {
  157. if (__ratelimit(&rtl))
  158. pr_err_ratelimited("%s: core hw vote clk is not enabled\n",
  159. __func__);
  160. ret = -EINVAL;
  161. goto err;
  162. }
  163. ret = ioread32(pad->base + pad->offset + addr);
  164. if (ret < 0)
  165. pr_err_ratelimited("%s: read 0x%x failed\n", __func__, addr);
  166. err:
  167. mutex_unlock(&state->core_hw_vote_lock);
  168. pm_runtime_mark_last_busy(lpi_dev);
  169. pm_runtime_put_autosuspend(lpi_dev);
  170. return ret;
  171. }
  172. static int lpi_gpio_write(struct lpi_gpio_pad *pad, unsigned int addr,
  173. unsigned int val)
  174. {
  175. struct lpi_gpio_state *state = NULL;
  176. int ret = 0;
  177. static DEFINE_RATELIMIT_STATE(rtl, 1 * HZ, 1);
  178. if (!lpi_dev) {
  179. if (__ratelimit(&rtl))
  180. pr_err_ratelimited("%s: lpi_dev is NULL, return\n",
  181. __func__);
  182. return -EINVAL;
  183. }
  184. state = dev_get_drvdata(lpi_dev);
  185. if (!lpi_dev_up) {
  186. return 0;
  187. }
  188. pm_runtime_get_sync(lpi_dev);
  189. mutex_lock(&state->core_hw_vote_lock);
  190. if (!state->core_hw_vote_status) {
  191. if (__ratelimit(&rtl))
  192. pr_err_ratelimited("%s: core hw vote clk is not enabled\n",
  193. __func__);
  194. ret = -EINVAL;
  195. goto err;
  196. }
  197. iowrite32(val, pad->base + pad->offset + addr);
  198. err:
  199. mutex_unlock(&state->core_hw_vote_lock);
  200. pm_runtime_mark_last_busy(lpi_dev);
  201. pm_runtime_put_autosuspend(lpi_dev);
  202. return ret;
  203. }
  204. static int lpi_gpio_get_groups_count(struct pinctrl_dev *pctldev)
  205. {
  206. /* Every PIN is a group */
  207. return pctldev->desc->npins;
  208. }
  209. static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev,
  210. unsigned int pin)
  211. {
  212. return pctldev->desc->pins[pin].name;
  213. }
  214. static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev,
  215. unsigned int pin,
  216. const unsigned int **pins,
  217. unsigned int *num_pins)
  218. {
  219. *pins = &pctldev->desc->pins[pin].number;
  220. *num_pins = 1;
  221. return 0;
  222. }
  223. static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
  224. .get_groups_count = lpi_gpio_get_groups_count,
  225. .get_group_name = lpi_gpio_get_group_name,
  226. .get_group_pins = lpi_gpio_get_group_pins,
  227. .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
  228. .dt_free_map = pinctrl_utils_free_map,
  229. };
  230. static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev)
  231. {
  232. return ARRAY_SIZE(lpi_gpio_functions);
  233. }
  234. static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev,
  235. unsigned int function)
  236. {
  237. return lpi_gpio_functions[function];
  238. }
  239. static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev,
  240. unsigned int function,
  241. const char *const **groups,
  242. unsigned *const num_qgroups)
  243. {
  244. *groups = lpi_gpio_groups;
  245. *num_qgroups = pctldev->desc->npins;
  246. return 0;
  247. }
  248. static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
  249. unsigned int pin)
  250. {
  251. struct lpi_gpio_pad *pad;
  252. unsigned int val;
  253. pad = pctldev->desc->pins[pin].drv_data;
  254. if (pad != NULL) {
  255. pad->function = function;
  256. val = lpi_gpio_read(pad, LPI_GPIO_REG_VAL_CTL);
  257. val &= ~(LPI_GPIO_REG_FUNCTION_MASK);
  258. val |= pad->function << LPI_GPIO_REG_FUNCTION_SHIFT;
  259. lpi_gpio_write(pad, LPI_GPIO_REG_VAL_CTL, val);
  260. }
  261. return 0;
  262. }
  263. static const struct pinmux_ops lpi_gpio_pinmux_ops = {
  264. .get_functions_count = lpi_gpio_get_functions_count,
  265. .get_function_name = lpi_gpio_get_function_name,
  266. .get_function_groups = lpi_gpio_get_function_groups,
  267. .set_mux = lpi_gpio_set_mux,
  268. };
  269. static int lpi_config_get(struct pinctrl_dev *pctldev,
  270. unsigned int pin, unsigned long *config)
  271. {
  272. unsigned int param = pinconf_to_config_param(*config);
  273. struct lpi_gpio_pad *pad;
  274. unsigned int arg;
  275. pad = pctldev->desc->pins[pin].drv_data;
  276. switch (param) {
  277. case PIN_CONFIG_BIAS_DISABLE:
  278. arg = pad->pullup = LPI_GPIO_BIAS_DISABLE;
  279. break;
  280. case PIN_CONFIG_BIAS_PULL_DOWN:
  281. arg = pad->pullup == LPI_GPIO_PULL_DOWN;
  282. break;
  283. case PIN_CONFIG_BIAS_BUS_HOLD:
  284. arg = pad->pullup = LPI_GPIO_KEEPER;
  285. break;
  286. case PIN_CONFIG_BIAS_PULL_UP:
  287. arg = pad->pullup == LPI_GPIO_PULL_UP;
  288. break;
  289. case PIN_CONFIG_INPUT_ENABLE:
  290. case PIN_CONFIG_OUTPUT:
  291. arg = pad->output_enabled;
  292. break;
  293. default:
  294. return -EINVAL;
  295. }
  296. *config = pinconf_to_config_packed(param, arg);
  297. return 0;
  298. }
  299. static unsigned int lpi_drive_to_regval(u32 arg)
  300. {
  301. if (arg < LPI_GPIO_DRV_2_MA)
  302. arg = LPI_GPIO_DRV_2_MA;
  303. if (arg > LPI_GPIO_DRV_16_MA)
  304. arg = LPI_GPIO_DRV_16_MA;
  305. return (arg/2 - 1);
  306. }
  307. static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
  308. unsigned long *configs, unsigned int nconfs)
  309. {
  310. struct lpi_gpio_pad *pad;
  311. unsigned int param, arg;
  312. int i, ret = 0;
  313. volatile unsigned long val;
  314. struct lpi_gpio_state *state = dev_get_drvdata(pctldev->dev);
  315. pad = pctldev->desc->pins[pin].drv_data;
  316. for (i = 0; i < nconfs; i++) {
  317. param = pinconf_to_config_param(configs[i]);
  318. arg = pinconf_to_config_argument(configs[i]);
  319. dev_dbg(pctldev->dev, "%s: param: %d arg: %d pin: %d\n",
  320. __func__, param, arg, pin);
  321. switch (param) {
  322. case PIN_CONFIG_BIAS_DISABLE:
  323. pad->pullup = LPI_GPIO_BIAS_DISABLE;
  324. break;
  325. case PIN_CONFIG_BIAS_PULL_DOWN:
  326. pad->pullup = LPI_GPIO_PULL_DOWN;
  327. break;
  328. case PIN_CONFIG_BIAS_BUS_HOLD:
  329. pad->pullup = LPI_GPIO_KEEPER;
  330. break;
  331. case PIN_CONFIG_BIAS_PULL_UP:
  332. pad->pullup = LPI_GPIO_PULL_UP;
  333. break;
  334. case PIN_CONFIG_INPUT_ENABLE:
  335. pad->output_enabled = false;
  336. break;
  337. case PIN_CONFIG_OUTPUT:
  338. pad->output_enabled = true;
  339. pad->value = arg;
  340. break;
  341. case PIN_CONFIG_DRIVE_STRENGTH:
  342. pad->strength = arg;
  343. break;
  344. case PIN_CONFIG_SLEW_RATE:
  345. if (pad->slew_base == NULL ||
  346. pad->slew_offset == LPI_SLEW_OFFSET_INVALID) {
  347. dev_dbg(pctldev->dev, "%s: invalid slew settings for pin: %d\n",
  348. __func__, pin);
  349. goto set_gpio;
  350. }
  351. if (arg > LPI_SLEW_RATE_MAX) {
  352. dev_err_ratelimited(pctldev->dev, "%s: invalid slew rate %u for \
  353. pin: %d\n", __func__, arg, pin);
  354. goto set_gpio;
  355. }
  356. pad->base = pad->slew_base;
  357. pad->offset = 0;
  358. mutex_lock(&state->slew_access_lock);
  359. if (pad->lpi_slew_reg != NULL) {
  360. pad->base = pad->lpi_slew_reg;
  361. if (pad->slew_offset != LPI_SLEW_OFFSET_INVALID) {
  362. val = lpi_gpio_read(pad, LPI_SLEW_REG_VAL_CTL); //16-bit
  363. pad->offset = pad->slew_offset;
  364. for (i = 0; i < LPI_SLEW_BITS_SIZE; i++) {
  365. if (arg & 0x01)
  366. set_bit(pad->offset, &val);
  367. else
  368. clear_bit(pad->offset, &val);
  369. pad->offset++;
  370. arg = arg >> 1;
  371. }
  372. pad->offset = 0;
  373. lpi_gpio_write(pad, LPI_SLEW_REG_VAL_CTL, val);
  374. } else {
  375. lpi_gpio_write(pad, LPI_SLEW_REG_VAL_CTL, arg);
  376. }
  377. pad->base = pad->slew_base;
  378. goto slew_exit;
  379. }
  380. val = lpi_gpio_read(pad, LPI_SLEW_REG_VAL_CTL);
  381. pad->offset = pad->slew_offset;
  382. for (i = 0; i < LPI_SLEW_BITS_SIZE; i++) {
  383. if (arg & 0x01)
  384. set_bit(pad->offset, &val);
  385. else
  386. clear_bit(pad->offset, &val);
  387. pad->offset++;
  388. arg = arg >> 1;
  389. }
  390. pad->offset = 0;
  391. lpi_gpio_write(pad, LPI_SLEW_REG_VAL_CTL, val);
  392. slew_exit:
  393. mutex_unlock(&state->slew_access_lock);
  394. break;
  395. default:
  396. ret = -EINVAL;
  397. goto done;
  398. }
  399. }
  400. set_gpio:
  401. pad->base = pad->gpio_base;
  402. pad->offset = pad->gpio_offset;
  403. val = lpi_gpio_read(pad, LPI_GPIO_REG_VAL_CTL);
  404. val &= ~(LPI_GPIO_REG_PULL_MASK | LPI_GPIO_REG_OUT_STRENGTH_MASK |
  405. LPI_GPIO_REG_OE_MASK);
  406. val |= pad->pullup << LPI_GPIO_REG_PULL_SHIFT;
  407. val |= lpi_drive_to_regval(pad->strength) <<
  408. LPI_GPIO_REG_OUT_STRENGTH_SHIFT;
  409. if (pad->output_enabled)
  410. val |= pad->value << LPI_GPIO_REG_OE_SHIFT;
  411. lpi_gpio_write(pad, LPI_GPIO_REG_VAL_CTL, val);
  412. lpi_gpio_write(pad, LPI_GPIO_REG_DIR_CTL,
  413. pad->output_enabled << LPI_GPIO_REG_DIR_SHIFT);
  414. done:
  415. return ret;
  416. }
  417. static const struct pinconf_ops lpi_gpio_pinconf_ops = {
  418. .is_generic = true,
  419. .pin_config_group_get = lpi_config_get,
  420. .pin_config_group_set = lpi_config_set,
  421. };
  422. static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
  423. {
  424. struct lpi_gpio_state *state = gpiochip_get_data(chip);
  425. unsigned long config;
  426. config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
  427. return lpi_config_set(state->ctrl, pin, &config, 1);
  428. }
  429. static int lpi_gpio_direction_output(struct gpio_chip *chip,
  430. unsigned int pin, int val)
  431. {
  432. struct lpi_gpio_state *state = gpiochip_get_data(chip);
  433. unsigned long config;
  434. config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
  435. return lpi_config_set(state->ctrl, pin, &config, 1);
  436. }
  437. static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
  438. {
  439. struct lpi_gpio_state *state = gpiochip_get_data(chip);
  440. struct lpi_gpio_pad *pad;
  441. int value;
  442. pad = state->ctrl->desc->pins[pin].drv_data;
  443. value = lpi_gpio_read(pad, LPI_GPIO_REG_VAL_CTL);
  444. return value;
  445. }
  446. static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
  447. {
  448. struct lpi_gpio_state *state = gpiochip_get_data(chip);
  449. unsigned long config;
  450. config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
  451. lpi_config_set(state->ctrl, pin, &config, 1);
  452. }
  453. static int lpi_notifier_service_cb(struct notifier_block *this,
  454. unsigned long opcode, void *ptr)
  455. {
  456. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  457. switch (opcode) {
  458. case AUDIO_NOTIFIER_SERVICE_DOWN:
  459. if (initial_boot) {
  460. initial_boot = false;
  461. break;
  462. }
  463. lpi_dev_up = false;
  464. break;
  465. case AUDIO_NOTIFIER_SERVICE_UP:
  466. if (initial_boot)
  467. initial_boot = false;
  468. lpi_dev_up = true;
  469. snd_event_notify(lpi_dev, SND_EVENT_UP);
  470. break;
  471. default:
  472. break;
  473. }
  474. return NOTIFY_OK;
  475. }
  476. int lpi_pinctrl_suspend(struct device *dev)
  477. {
  478. int ret = 0;
  479. dev_dbg(dev, "%s: system suspend\n", __func__);
  480. if ((!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev))) {
  481. ret = lpi_pinctrl_runtime_suspend(dev);
  482. if (!ret) {
  483. /*
  484. * Synchronize runtime-pm and system-pm states:
  485. * At this point, we are already suspended. If
  486. * runtime-pm still thinks its active, then
  487. * make sure its status is in sync with HW
  488. * status. The three below calls let the
  489. * runtime-pm know that we are suspended
  490. * already without re-invoking the suspend
  491. * callback
  492. */
  493. pm_runtime_disable(dev);
  494. pm_runtime_set_suspended(dev);
  495. pm_runtime_enable(dev);
  496. }
  497. }
  498. return ret;
  499. }
  500. int lpi_pinctrl_resume(struct device *dev)
  501. {
  502. return 0;
  503. }
  504. static struct notifier_block service_nb = {
  505. .notifier_call = lpi_notifier_service_cb,
  506. .priority = -INT_MAX,
  507. };
  508. static void lpi_pinctrl_ssr_disable(struct device *dev, void *data)
  509. {
  510. lpi_dev_up = false;
  511. lpi_pinctrl_suspend(dev);
  512. }
  513. static int lpi_pinctrl_ssr_enable(struct device *dev, void *data)
  514. {
  515. struct lpi_gpio_state *state = NULL;
  516. dev_dbg(dev, "%s: enter\n", __func__);
  517. if (!lpi_dev) {
  518. dev_err(dev, "%s: lpi_dev is NULL, return\n", __func__);
  519. return -EINVAL;
  520. }
  521. state = dev_get_drvdata(lpi_dev);
  522. if (!initial_boot) {
  523. if (!lpi_dev_up) {
  524. msleep(100);
  525. if (state->lpass_core_hw_vote)
  526. digital_cdc_rsc_mgr_hw_vote_reset(
  527. state->lpass_core_hw_vote);
  528. if (state->lpass_audio_hw_vote)
  529. digital_cdc_rsc_mgr_hw_vote_reset(
  530. state->lpass_audio_hw_vote);
  531. }
  532. lpi_dev_up = true;
  533. }
  534. dev_dbg(dev, "%s: leave\n", __func__);
  535. return 0;
  536. }
  537. static const struct snd_event_ops lpi_pinctrl_ssr_ops = {
  538. .disable = lpi_pinctrl_ssr_disable,
  539. .enable = lpi_pinctrl_ssr_enable,
  540. };
  541. #ifdef CONFIG_DEBUG_FS
  542. #include <linux/seq_file.h>
  543. static unsigned int lpi_regval_to_drive(u32 val)
  544. {
  545. return (val + 1) * 2;
  546. }
  547. static void lpi_gpio_dbg_show_one(struct seq_file *s,
  548. struct pinctrl_dev *pctldev,
  549. struct gpio_chip *chip,
  550. unsigned int offset,
  551. unsigned int gpio)
  552. {
  553. struct lpi_gpio_state *state = gpiochip_get_data(chip);
  554. struct pinctrl_pin_desc pindesc;
  555. struct lpi_gpio_pad *pad;
  556. unsigned int func;
  557. int is_out;
  558. int drive;
  559. int pull;
  560. u32 ctl_reg;
  561. static const char * const pulls[] = {
  562. "no pull",
  563. "pull down",
  564. "keeper",
  565. "pull up"
  566. };
  567. pctldev = pctldev ? : state->ctrl;
  568. pindesc = pctldev->desc->pins[offset];
  569. pad = pctldev->desc->pins[offset].drv_data;
  570. ctl_reg = lpi_gpio_read(pad, LPI_GPIO_REG_DIR_CTL);
  571. is_out = (ctl_reg & LPI_GPIO_REG_DIR_MASK) >> LPI_GPIO_REG_DIR_SHIFT;
  572. ctl_reg = lpi_gpio_read(pad, LPI_GPIO_REG_VAL_CTL);
  573. func = (ctl_reg & LPI_GPIO_REG_FUNCTION_MASK) >>
  574. LPI_GPIO_REG_FUNCTION_SHIFT;
  575. drive = (ctl_reg & LPI_GPIO_REG_OUT_STRENGTH_MASK) >>
  576. LPI_GPIO_REG_OUT_STRENGTH_SHIFT;
  577. pull = (ctl_reg & LPI_GPIO_REG_PULL_MASK) >> LPI_GPIO_REG_PULL_SHIFT;
  578. seq_printf(s, " %-8s: %-3s %d",
  579. pindesc.name, is_out ? "out" : "in", func);
  580. seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
  581. seq_printf(s, " %s", pulls[pull]);
  582. }
  583. static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  584. {
  585. unsigned int gpio = chip->base;
  586. unsigned int i;
  587. for (i = 0; i < chip->ngpio; i++, gpio++) {
  588. lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio);
  589. seq_puts(s, "\n");
  590. }
  591. }
  592. #else
  593. #define lpi_gpio_dbg_show NULL
  594. #endif
  595. static const struct gpio_chip lpi_gpio_template = {
  596. .direction_input = lpi_gpio_direction_input,
  597. .direction_output = lpi_gpio_direction_output,
  598. .get = lpi_gpio_get,
  599. .set = lpi_gpio_set,
  600. .request = gpiochip_generic_request,
  601. .free = gpiochip_generic_free,
  602. .dbg_show = lpi_gpio_dbg_show,
  603. };
  604. static int lpi_pinctrl_probe(struct platform_device *pdev)
  605. {
  606. struct device *dev = &pdev->dev;
  607. struct pinctrl_pin_desc *pindesc;
  608. struct pinctrl_desc *pctrldesc;
  609. struct lpi_gpio_pad *pad, *pads;
  610. struct lpi_gpio_state *state;
  611. int ret, npins, i;
  612. char __iomem *lpi_base;
  613. char __iomem *slew_base;
  614. u32 reg, slew_reg;
  615. struct clk *lpass_core_hw_vote = NULL;
  616. struct clk *lpass_audio_hw_vote = NULL;
  617. if (!audio_notifier_probe_status()) {
  618. pr_err("%s: Audio notify probe not completed, defer lpi pinctrl probe\n",
  619. __func__);
  620. return -EPROBE_DEFER;
  621. }
  622. ret = of_property_read_u32(dev->of_node, "reg", &reg);
  623. if (ret < 0) {
  624. dev_err(dev, "missing base address\n");
  625. return ret;
  626. }
  627. ret = of_property_read_u32(dev->of_node, "qcom,gpios-count", &npins);
  628. if (ret < 0)
  629. return ret;
  630. WARN_ON(npins > ARRAY_SIZE(lpi_gpio_groups));
  631. ret = of_property_read_u32_array(dev->of_node, "qcom,lpi-offset-tbl",
  632. lpi_offset, npins);
  633. if (ret < 0) {
  634. dev_err(dev, "error in reading lpi offset table: %d\n", ret);
  635. return ret;
  636. }
  637. ret = of_property_read_u32_array(dev->of_node,
  638. "qcom,lpi-slew-offset-tbl",
  639. lpi_slew_offset, npins);
  640. if (ret < 0) {
  641. for (i = 0; i < npins; i++)
  642. lpi_slew_offset[i] = LPI_SLEW_OFFSET_INVALID;
  643. dev_dbg(dev, "%s: error in reading lpi slew offset table: %d\n",
  644. __func__, ret);
  645. }
  646. ret = of_property_read_u32_array(dev->of_node,
  647. "qcom,lpi-slew-base-tbl",
  648. lpi_slew_base, npins);
  649. if (ret < 0) {
  650. for (i = 0; i < npins; i++)
  651. lpi_slew_base[i] = LPI_SLEW_OFFSET_INVALID;
  652. dev_dbg(dev, "%s: error in reading lpi slew table: %d\n",
  653. __func__, ret);
  654. }
  655. state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
  656. if (!state)
  657. return -ENOMEM;
  658. platform_set_drvdata(pdev, state);
  659. state->dev = &pdev->dev;
  660. slew_reg = 0;
  661. ret = of_property_read_u32(dev->of_node, "qcom,slew-reg", &slew_reg);
  662. if (!ret) {
  663. slew_base = devm_ioremap(dev, slew_reg, LPI_SLEW_ADDRESS_SIZE);
  664. if (slew_base == NULL) {
  665. dev_err(dev,
  666. "%s devm_ioremap failed for slew rate reg\n",
  667. __func__);
  668. ret = -ENOMEM;
  669. goto err_io;
  670. }
  671. } else {
  672. slew_base = NULL;
  673. dev_dbg(dev, "error in reading lpi slew register: %d\n",
  674. ret);
  675. }
  676. pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
  677. if (!pindesc)
  678. return -ENOMEM;
  679. pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
  680. if (!pads)
  681. return -ENOMEM;
  682. pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
  683. if (!pctrldesc)
  684. return -ENOMEM;
  685. pctrldesc->pctlops = &lpi_gpio_pinctrl_ops;
  686. pctrldesc->pmxops = &lpi_gpio_pinmux_ops;
  687. pctrldesc->confops = &lpi_gpio_pinconf_ops;
  688. pctrldesc->owner = THIS_MODULE;
  689. pctrldesc->name = dev_name(dev);
  690. pctrldesc->pins = pindesc;
  691. pctrldesc->npins = npins;
  692. lpi_base = devm_ioremap(dev, reg, LPI_ADDRESS_SIZE);
  693. if (lpi_base == NULL) {
  694. dev_err(dev, "%s devm_ioremap failed\n", __func__);
  695. return -ENOMEM;
  696. }
  697. state->base = lpi_base;
  698. for (i = 0; i < npins; i++, pindesc++) {
  699. pad = &pads[i];
  700. pindesc->drv_data = pad;
  701. pindesc->number = i;
  702. pindesc->name = lpi_gpio_groups[i];
  703. pad->gpio_base = lpi_base;
  704. pad->slew_base = slew_base;
  705. pad->base = pad->gpio_base;
  706. pad->gpio_offset = lpi_offset[i];
  707. pad->slew_offset = lpi_slew_offset[i];
  708. pad->offset = pad->gpio_offset;
  709. pad->lpi_slew_reg = NULL;
  710. if ((lpi_slew_base[i] != LPI_SLEW_OFFSET_INVALID) &&
  711. lpi_slew_base[i])
  712. pad->lpi_slew_reg = devm_ioremap(dev,
  713. lpi_slew_base[i], 0x4);
  714. }
  715. state->chip = lpi_gpio_template;
  716. state->chip.parent = dev;
  717. state->chip.base = -1;
  718. state->chip.ngpio = npins;
  719. state->chip.label = dev_name(dev);
  720. state->chip.of_gpio_n_cells = 2;
  721. state->chip.can_sleep = false;
  722. mutex_init(&state->slew_access_lock);
  723. mutex_init(&state->core_hw_vote_lock);
  724. state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
  725. if (IS_ERR(state->ctrl))
  726. return PTR_ERR(state->ctrl);
  727. ret = gpiochip_add_data(&state->chip, state);
  728. if (ret) {
  729. dev_err(state->dev, "can't add gpio chip\n");
  730. goto err_chip;
  731. }
  732. ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
  733. if (ret) {
  734. dev_err(dev, "failed to add pin range\n");
  735. goto err_range;
  736. }
  737. lpi_dev = &pdev->dev;
  738. lpi_dev_up = true;
  739. initial_boot = true;
  740. ret = snd_event_client_register(dev, &lpi_pinctrl_ssr_ops, NULL);
  741. if (!ret) {
  742. snd_event_notify(dev, SND_EVENT_UP);
  743. } else {
  744. dev_err(dev, "%s: snd_event registration failed, ret [%d]\n",
  745. __func__, ret);
  746. goto err_range;
  747. }
  748. ret = audio_notifier_register("lpi_tlmm", AUDIO_NOTIFIER_ADSP_DOMAIN,
  749. &service_nb);
  750. if (ret < 0) {
  751. pr_err("%s: Audio notifier register failed ret = %d\n",
  752. __func__, ret);
  753. goto err_range;
  754. }
  755. /* Register LPASS core hw vote */
  756. lpass_core_hw_vote = devm_clk_get(&pdev->dev, "lpass_core_hw_vote");
  757. if (IS_ERR(lpass_core_hw_vote)) {
  758. ret = PTR_ERR(lpass_core_hw_vote);
  759. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  760. __func__, "lpass_core_hw_vote", ret);
  761. lpass_core_hw_vote = NULL;
  762. ret = 0;
  763. }
  764. state->lpass_core_hw_vote = lpass_core_hw_vote;
  765. /* Register LPASS audio hw vote */
  766. lpass_audio_hw_vote = devm_clk_get(&pdev->dev, "lpass_audio_hw_vote");
  767. if (IS_ERR(lpass_audio_hw_vote)) {
  768. ret = PTR_ERR(lpass_audio_hw_vote);
  769. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  770. __func__, "lpass_audio_hw_vote", ret);
  771. lpass_audio_hw_vote = NULL;
  772. ret = 0;
  773. }
  774. state->lpass_audio_hw_vote = lpass_audio_hw_vote;
  775. state->core_hw_vote_status = false;
  776. pm_runtime_set_autosuspend_delay(&pdev->dev, LPI_AUTO_SUSPEND_DELAY);
  777. pm_runtime_use_autosuspend(&pdev->dev);
  778. pm_runtime_set_suspended(&pdev->dev);
  779. pm_runtime_enable(&pdev->dev);
  780. return 0;
  781. //err_snd_evt:
  782. // audio_notifier_deregister("lpi_tlmm");
  783. err_range:
  784. gpiochip_remove(&state->chip);
  785. err_chip:
  786. mutex_destroy(&state->core_hw_vote_lock);
  787. mutex_destroy(&state->slew_access_lock);
  788. err_io:
  789. return ret;
  790. }
  791. static int lpi_pinctrl_remove(struct platform_device *pdev)
  792. {
  793. struct lpi_gpio_state *state = platform_get_drvdata(pdev);
  794. pm_runtime_disable(&pdev->dev);
  795. pm_runtime_set_suspended(&pdev->dev);
  796. snd_event_client_deregister(&pdev->dev);
  797. audio_notifier_deregister("lpi_tlmm");
  798. gpiochip_remove(&state->chip);
  799. mutex_destroy(&state->core_hw_vote_lock);
  800. mutex_destroy(&state->slew_access_lock);
  801. return 0;
  802. }
  803. static const struct of_device_id lpi_pinctrl_of_match[] = {
  804. { .compatible = "qcom,lpi-pinctrl" }, /* Generic */
  805. { },
  806. };
  807. MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
  808. int lpi_pinctrl_runtime_resume(struct device *dev)
  809. {
  810. struct lpi_gpio_state *state = dev_get_drvdata(dev);
  811. int ret = 0;
  812. struct clk *hw_vote = state->lpass_core_hw_vote;
  813. if (state->lpass_core_hw_vote == NULL) {
  814. dev_dbg(dev, "%s: Invalid core hw node\n", __func__);
  815. if (state->lpass_audio_hw_vote == NULL) {
  816. dev_dbg(dev, "%s: Invalid audio hw node\n", __func__);
  817. return 0;
  818. }
  819. hw_vote = state->lpass_audio_hw_vote;
  820. }
  821. mutex_lock(&state->core_hw_vote_lock);
  822. ret = digital_cdc_rsc_mgr_hw_vote_enable(hw_vote, dev);
  823. if (ret < 0) {
  824. pm_runtime_set_autosuspend_delay(dev,
  825. LPI_AUTO_SUSPEND_DELAY_ERROR);
  826. dev_err_ratelimited(dev, "%s:lpass core hw island enable failed\n",
  827. __func__);
  828. goto exit;
  829. } else {
  830. state->core_hw_vote_status = true;
  831. }
  832. pm_runtime_set_autosuspend_delay(dev, LPI_AUTO_SUSPEND_DELAY);
  833. exit:
  834. mutex_unlock(&state->core_hw_vote_lock);
  835. return 0;
  836. }
  837. int lpi_pinctrl_runtime_suspend(struct device *dev)
  838. {
  839. struct lpi_gpio_state *state = dev_get_drvdata(dev);
  840. struct clk *hw_vote = state->lpass_core_hw_vote;
  841. if (state->lpass_core_hw_vote == NULL) {
  842. dev_dbg(dev, "%s: Invalid core hw node\n", __func__);
  843. if (state->lpass_audio_hw_vote == NULL) {
  844. dev_dbg(dev, "%s: Invalid audio hw node\n", __func__);
  845. return 0;
  846. }
  847. hw_vote = state->lpass_audio_hw_vote;
  848. }
  849. mutex_lock(&state->core_hw_vote_lock);
  850. if (state->core_hw_vote_status) {
  851. digital_cdc_rsc_mgr_hw_vote_disable(hw_vote, dev);
  852. state->core_hw_vote_status = false;
  853. }
  854. mutex_unlock(&state->core_hw_vote_lock);
  855. return 0;
  856. }
  857. static const struct dev_pm_ops lpi_pinctrl_dev_pm_ops = {
  858. SET_SYSTEM_SLEEP_PM_OPS(
  859. lpi_pinctrl_suspend,
  860. lpi_pinctrl_resume
  861. )
  862. SET_RUNTIME_PM_OPS(
  863. lpi_pinctrl_runtime_suspend,
  864. lpi_pinctrl_runtime_resume,
  865. NULL
  866. )
  867. };
  868. static struct platform_driver lpi_pinctrl_driver = {
  869. .driver = {
  870. .name = "qcom-lpi-pinctrl",
  871. .pm = &lpi_pinctrl_dev_pm_ops,
  872. .of_match_table = lpi_pinctrl_of_match,
  873. .suppress_bind_attrs = true,
  874. },
  875. .probe = lpi_pinctrl_probe,
  876. .remove = lpi_pinctrl_remove,
  877. };
  878. module_platform_driver(lpi_pinctrl_driver);
  879. MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
  880. MODULE_LICENSE("GPL v2");