holi-port-config.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _HOLI_PORT_CONFIG
  6. #define _HOLI_PORT_CONFIG
  7. #include <soc/swr-common.h>
  8. #define WSA_MSTR_PORT_MASK 0xFF
  9. /*
  10. * Add port configuration in the format
  11. *{ si, off1, off2, hstart, hstop, wd_len, bp_mode, bgp_ctrl, lane_ctrl, dir,
  12. * stream_type}
  13. */
  14. static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {
  15. {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00},
  16. {31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00},
  17. {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x00},
  18. {7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0, 0x00, 0x00},
  19. {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0, 0x00, 0x00},
  20. };
  21. /* Headset + PCM Haptics */
  22. static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = {
  23. {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, /* HPH/EAR */
  24. {31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00}, /* HPH_CLH */
  25. {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x00}, /* HPH_CMP */
  26. {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* LO/AUX */
  27. {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */
  28. {0x18F, 0, 0, 0x8, 0x8, 0x0F, 0x00, 0, 0, 0x00, 0x01}, /* PCM_OUT */
  29. };
  30. /* Headset(44.1K) + PCM Haptics */
  31. static struct port_params rx_frame_params_44p1KHz[SWR_MSTR_PORT_LEN] = {
  32. {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, /* HPH/EAR */
  33. {63, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00}, /* HPH_CLH */
  34. {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x00}, /* HPH_CMP */
  35. {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0, 0x00, 0x00}, /* LO/AUX */
  36. {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */
  37. {0x1FF, 0, 0, 0x8, 0x8, 0x0F, 0, 0, 0, 0x00, 0x01}, /* PCM_OUT */
  38. };
  39. /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */
  40. static struct port_params tx_frame_params_4p8MHz[SWR_MSTR_PORT_LEN] = {
  41. {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX1 */
  42. {3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */
  43. {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
  44. };
  45. static struct port_params tx_frame_params_wcd937x[SWR_MSTR_PORT_LEN] = {
  46. {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX1 */
  47. {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */
  48. {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
  49. };
  50. static struct swr_mstr_port_map sm_port_map[] = {
  51. {VA_MACRO, SWR_UC0, tx_frame_params_4p8MHz},
  52. {RX_MACRO, SWR_UC0, rx_frame_params_default},
  53. {RX_MACRO, SWR_UC1, rx_frame_params_dsd},
  54. {RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz},
  55. };
  56. static struct swr_mstr_port_map sm_port_map_wcd937x[] = {
  57. {VA_MACRO, SWR_UC0, tx_frame_params_wcd937x},
  58. {RX_MACRO, SWR_UC0, rx_frame_params_default},
  59. {RX_MACRO, SWR_UC1, rx_frame_params_dsd},
  60. {RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz},
  61. };
  62. #endif /* _HOLI_PORT_CONFIG */