wcd9xxx-utils.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/kernel.h>
  5. #include <linux/module.h>
  6. #include <linux/of_gpio.h>
  7. #include <linux/of_irq.h>
  8. #include <linux/of_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/regmap.h>
  11. #include <linux/delay.h>
  12. #include <linux/sched.h>
  13. #include <linux/mfd/core.h>
  14. #include <asoc/core.h>
  15. #include <asoc/msm-cdc-supply.h>
  16. #include <asoc/msm-cdc-pinctrl.h>
  17. #include <asoc/pdata.h>
  18. #include <asoc/wcd9xxx-irq.h>
  19. #include "wcd9xxx-utils.h"
  20. #define REG_BYTES 2
  21. #define VAL_BYTES 1
  22. /*
  23. * Page Register Address that APP Proc uses to
  24. * access WCD9335 Codec registers is identified
  25. * as 0x00
  26. */
  27. #define PAGE_REG_ADDR 0x00
  28. static enum wcd9xxx_intf_status wcd9xxx_intf = -1;
  29. static struct mfd_cell tavil_devs[] = {
  30. {
  31. .name = "qcom-wcd-pinctrl",
  32. .of_compatible = "qcom,wcd-pinctrl",
  33. },
  34. {
  35. .name = "tavil_codec",
  36. },
  37. };
  38. static struct mfd_cell tasha_devs[] = {
  39. {
  40. .name = "tasha_codec",
  41. },
  42. };
  43. static struct mfd_cell tomtom_devs[] = {
  44. {
  45. .name = "tomtom_codec",
  46. },
  47. };
  48. static int wcd9xxx_read_of_property_u32(struct device *dev, const char *name,
  49. u32 *val)
  50. {
  51. int rc = 0;
  52. rc = of_property_read_u32(dev->of_node, name, val);
  53. if (rc)
  54. dev_err(dev, "%s: Looking up %s property in node %s failed",
  55. __func__, name, dev->of_node->full_name);
  56. return rc;
  57. }
  58. static void wcd9xxx_dt_parse_micbias_info(struct device *dev,
  59. struct wcd9xxx_micbias_setting *mb)
  60. {
  61. u32 prop_val;
  62. int rc;
  63. if (of_find_property(dev->of_node, "qcom,cdc-micbias-ldoh-v", NULL)) {
  64. rc = wcd9xxx_read_of_property_u32(dev,
  65. "qcom,cdc-micbias-ldoh-v",
  66. &prop_val);
  67. if (!rc)
  68. mb->ldoh_v = (u8)prop_val;
  69. }
  70. /* MB1 */
  71. if (of_find_property(dev->of_node, "qcom,cdc-micbias-cfilt1-mv",
  72. NULL)) {
  73. rc = wcd9xxx_read_of_property_u32(dev,
  74. "qcom,cdc-micbias-cfilt1-mv",
  75. &prop_val);
  76. if (!rc)
  77. mb->cfilt1_mv = prop_val;
  78. rc = wcd9xxx_read_of_property_u32(dev,
  79. "qcom,cdc-micbias1-cfilt-sel",
  80. &prop_val);
  81. if (!rc)
  82. mb->bias1_cfilt_sel = (u8)prop_val;
  83. } else if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  84. NULL)) {
  85. rc = wcd9xxx_read_of_property_u32(dev,
  86. "qcom,cdc-micbias1-mv",
  87. &prop_val);
  88. if (!rc)
  89. mb->micb1_mv = prop_val;
  90. } else {
  91. dev_info(dev, "%s: Micbias1 DT property not found\n",
  92. __func__);
  93. }
  94. /* MB2 */
  95. if (of_find_property(dev->of_node, "qcom,cdc-micbias-cfilt2-mv",
  96. NULL)) {
  97. rc = wcd9xxx_read_of_property_u32(dev,
  98. "qcom,cdc-micbias-cfilt2-mv",
  99. &prop_val);
  100. if (!rc)
  101. mb->cfilt2_mv = prop_val;
  102. rc = wcd9xxx_read_of_property_u32(dev,
  103. "qcom,cdc-micbias2-cfilt-sel",
  104. &prop_val);
  105. if (!rc)
  106. mb->bias2_cfilt_sel = (u8)prop_val;
  107. } else if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  108. NULL)) {
  109. rc = wcd9xxx_read_of_property_u32(dev,
  110. "qcom,cdc-micbias2-mv",
  111. &prop_val);
  112. if (!rc)
  113. mb->micb2_mv = prop_val;
  114. } else {
  115. dev_info(dev, "%s: Micbias2 DT property not found\n",
  116. __func__);
  117. }
  118. /* MB3 */
  119. if (of_find_property(dev->of_node, "qcom,cdc-micbias-cfilt3-mv",
  120. NULL)) {
  121. rc = wcd9xxx_read_of_property_u32(dev,
  122. "qcom,cdc-micbias-cfilt3-mv",
  123. &prop_val);
  124. if (!rc)
  125. mb->cfilt3_mv = prop_val;
  126. rc = wcd9xxx_read_of_property_u32(dev,
  127. "qcom,cdc-micbias3-cfilt-sel",
  128. &prop_val);
  129. if (!rc)
  130. mb->bias3_cfilt_sel = (u8)prop_val;
  131. } else if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  132. NULL)) {
  133. rc = wcd9xxx_read_of_property_u32(dev,
  134. "qcom,cdc-micbias3-mv",
  135. &prop_val);
  136. if (!rc)
  137. mb->micb3_mv = prop_val;
  138. } else {
  139. dev_info(dev, "%s: Micbias3 DT property not found\n",
  140. __func__);
  141. }
  142. /* MB4 */
  143. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-cfilt-sel",
  144. NULL)) {
  145. rc = wcd9xxx_read_of_property_u32(dev,
  146. "qcom,cdc-micbias4-cfilt-sel",
  147. &prop_val);
  148. if (!rc)
  149. mb->bias4_cfilt_sel = (u8)prop_val;
  150. } else if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  151. NULL)) {
  152. rc = wcd9xxx_read_of_property_u32(dev,
  153. "qcom,cdc-micbias4-mv",
  154. &prop_val);
  155. if (!rc)
  156. mb->micb4_mv = prop_val;
  157. } else {
  158. dev_info(dev, "%s: Micbias4 DT property not found\n",
  159. __func__);
  160. }
  161. mb->bias1_cap_mode =
  162. (of_property_read_bool(dev->of_node, "qcom,cdc-micbias1-ext-cap") ?
  163. MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP);
  164. mb->bias2_cap_mode =
  165. (of_property_read_bool(dev->of_node, "qcom,cdc-micbias2-ext-cap") ?
  166. MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP);
  167. mb->bias3_cap_mode =
  168. (of_property_read_bool(dev->of_node, "qcom,cdc-micbias3-ext-cap") ?
  169. MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP);
  170. mb->bias4_cap_mode =
  171. (of_property_read_bool(dev->of_node, "qcom,cdc-micbias4-ext-cap") ?
  172. MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP);
  173. mb->bias2_is_headset_only =
  174. of_property_read_bool(dev->of_node,
  175. "qcom,cdc-micbias2-headset-only");
  176. /* Print micbias info */
  177. dev_dbg(dev, "%s: ldoh_v %u cfilt1_mv %u cfilt2_mv %u cfilt3_mv %u",
  178. __func__, (u32)mb->ldoh_v, (u32)mb->cfilt1_mv,
  179. (u32)mb->cfilt2_mv, (u32)mb->cfilt3_mv);
  180. dev_dbg(dev, "%s: micb1_mv %u micb2_mv %u micb3_mv %u micb4_mv %u",
  181. __func__, mb->micb1_mv, mb->micb2_mv,
  182. mb->micb3_mv, mb->micb4_mv);
  183. dev_dbg(dev, "%s: bias1_cfilt_sel %u bias2_cfilt_sel %u\n",
  184. __func__, (u32)mb->bias1_cfilt_sel, (u32)mb->bias2_cfilt_sel);
  185. dev_dbg(dev, "%s: bias3_cfilt_sel %u bias4_cfilt_sel %u\n",
  186. __func__, (u32)mb->bias3_cfilt_sel, (u32)mb->bias4_cfilt_sel);
  187. dev_dbg(dev, "%s: bias1_ext_cap %d bias2_ext_cap %d\n",
  188. __func__, mb->bias1_cap_mode, mb->bias2_cap_mode);
  189. dev_dbg(dev, "%s: bias3_ext_cap %d bias4_ext_cap %d\n",
  190. __func__, mb->bias3_cap_mode, mb->bias4_cap_mode);
  191. dev_dbg(dev, "%s: bias2_is_headset_only %d\n",
  192. __func__, mb->bias2_is_headset_only);
  193. }
  194. /*
  195. * wcd9xxx_validate_dmic_sample_rate:
  196. * Given the dmic_sample_rate and mclk rate, validate the
  197. * dmic_sample_rate. If dmic rate is found to be invalid,
  198. * assign the dmic rate as undefined, so individual codec
  199. * drivers can use their own defaults
  200. * @dev: the device for which the dmic is to be configured
  201. * @dmic_sample_rate: The input dmic_sample_rate
  202. * @mclk_rate: The input codec mclk rate
  203. * @dmic_rate_type: String to indicate the type of dmic sample
  204. * rate, used for debug/error logging.
  205. */
  206. static u32 wcd9xxx_validate_dmic_sample_rate(struct device *dev,
  207. u32 dmic_sample_rate, u32 mclk_rate,
  208. const char *dmic_rate_type)
  209. {
  210. u32 div_factor;
  211. if (dmic_sample_rate == WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED ||
  212. mclk_rate % dmic_sample_rate != 0)
  213. goto undefined_rate;
  214. div_factor = mclk_rate / dmic_sample_rate;
  215. switch (div_factor) {
  216. case 2:
  217. case 3:
  218. case 4:
  219. case 8:
  220. case 16:
  221. /* Valid dmic DIV factors */
  222. dev_dbg(dev, "%s: DMIC_DIV = %u, mclk_rate = %u\n",
  223. __func__, div_factor, mclk_rate);
  224. break;
  225. case 6:
  226. /*
  227. * DIV 6 is valid for both 9.6MHz and 12.288MHz
  228. * MCLK on Tavil. Older codecs support DIV6 only
  229. * for 12.288MHz MCLK.
  230. */
  231. if ((mclk_rate == WCD9XXX_MCLK_CLK_9P6HZ) &&
  232. (of_device_is_compatible(dev->of_node,
  233. "qcom,tavil-slim-pgd")))
  234. dev_dbg(dev, "%s: DMIC_DIV = %u, mclk_rate = %u\n",
  235. __func__, div_factor, mclk_rate);
  236. else if (mclk_rate != WCD9XXX_MCLK_CLK_12P288MHZ)
  237. goto undefined_rate;
  238. break;
  239. default:
  240. /* Any other DIV factor is invalid */
  241. goto undefined_rate;
  242. }
  243. return dmic_sample_rate;
  244. undefined_rate:
  245. dev_dbg(dev, "%s: Invalid %s = %d, for mclk %d\n",
  246. __func__, dmic_rate_type, dmic_sample_rate, mclk_rate);
  247. dmic_sample_rate = WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED;
  248. return dmic_sample_rate;
  249. }
  250. /*
  251. * wcd9xxx_populate_dt_data:
  252. * Parse device tree properties for the given codec device
  253. *
  254. * @dev: pointer to codec device
  255. *
  256. * Returns pointer to the platform data resulting from parsing
  257. * device tree.
  258. */
  259. struct wcd9xxx_pdata *wcd9xxx_populate_dt_data(struct device *dev)
  260. {
  261. struct wcd9xxx_pdata *pdata;
  262. u32 dmic_sample_rate = WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED;
  263. u32 mad_dmic_sample_rate = WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED;
  264. u32 ecpp_dmic_sample_rate = WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED;
  265. u32 dmic_clk_drive = WCD9XXX_DMIC_CLK_DRIVE_UNDEFINED;
  266. u32 prop_val;
  267. int rc = 0;
  268. if (!dev || !dev->of_node)
  269. return NULL;
  270. pdata = devm_kzalloc(dev, sizeof(struct wcd9xxx_pdata),
  271. GFP_KERNEL);
  272. if (!pdata)
  273. return NULL;
  274. /* Parse power supplies */
  275. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  276. &pdata->num_supplies);
  277. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  278. dev_err(dev, "%s: no power supplies defined for codec\n",
  279. __func__);
  280. goto err_power_sup;
  281. }
  282. /* Parse micbias info */
  283. wcd9xxx_dt_parse_micbias_info(dev, &pdata->micbias);
  284. pdata->wcd_rst_np = of_parse_phandle(dev->of_node,
  285. "qcom,wcd-rst-gpio-node", 0);
  286. if (!pdata->wcd_rst_np) {
  287. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  288. __func__, "qcom,wcd-rst-gpio-node",
  289. dev->of_node->full_name);
  290. goto err_parse_dt_prop;
  291. }
  292. pdata->has_buck_vsel_gpio = of_property_read_bool(dev->of_node,
  293. "qcom,has-buck-vsel-gpio");
  294. if (pdata->has_buck_vsel_gpio) {
  295. pdata->buck_vsel_ctl_np = of_parse_phandle(dev->of_node,
  296. "qcom,buck-vsel-gpio-node", 0);
  297. if (!pdata->buck_vsel_ctl_np) {
  298. dev_err(dev, "%s No entry for %s property in node %s\n",
  299. __func__, "qcom,buck-vsel-gpio-node",
  300. dev->of_node->full_name);
  301. goto err_parse_dt_prop;
  302. }
  303. }
  304. pdata->has_micb_supply_en_gpio = of_property_read_bool(dev->of_node,
  305. "qcom,has-micbias-supply-en-gpio");
  306. if (pdata->has_micb_supply_en_gpio) {
  307. pdata->micb_en_ctl = of_parse_phandle(dev->of_node,
  308. "qcom,micbias-supply-en-gpio-node", 0);
  309. if (!pdata->micb_en_ctl) {
  310. dev_err(dev, "%s No entry for %s property in node %s\n",
  311. __func__, "qcom,micbias-supply-en-gpio-node",
  312. dev->of_node->full_name);
  313. goto err_parse_dt_prop;
  314. }
  315. }
  316. if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-mclk-clk-rate",
  317. &prop_val)))
  318. pdata->mclk_rate = prop_val;
  319. if (pdata->mclk_rate != WCD9XXX_MCLK_CLK_9P6HZ &&
  320. pdata->mclk_rate != WCD9XXX_MCLK_CLK_12P288MHZ) {
  321. dev_err(dev, "%s: Invalid mclk_rate = %u\n", __func__,
  322. pdata->mclk_rate);
  323. goto err_parse_dt_prop;
  324. }
  325. if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-dmic-sample-rate",
  326. &prop_val)))
  327. dmic_sample_rate = prop_val;
  328. pdata->dmic_sample_rate = wcd9xxx_validate_dmic_sample_rate(dev,
  329. dmic_sample_rate,
  330. pdata->mclk_rate,
  331. "audio_dmic_rate");
  332. if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-mad-dmic-rate",
  333. &prop_val)))
  334. mad_dmic_sample_rate = prop_val;
  335. pdata->mad_dmic_sample_rate = wcd9xxx_validate_dmic_sample_rate(dev,
  336. mad_dmic_sample_rate,
  337. pdata->mclk_rate,
  338. "mad_dmic_rate");
  339. if (of_find_property(dev->of_node, "qcom,cdc-ecpp-dmic-rate", NULL)) {
  340. rc = wcd9xxx_read_of_property_u32(dev,
  341. "qcom,cdc-ecpp-dmic-rate",
  342. &prop_val);
  343. if (!rc)
  344. ecpp_dmic_sample_rate = prop_val;
  345. }
  346. pdata->ecpp_dmic_sample_rate = wcd9xxx_validate_dmic_sample_rate(dev,
  347. ecpp_dmic_sample_rate,
  348. pdata->mclk_rate,
  349. "ecpp_dmic_rate");
  350. if (!(of_property_read_u32(dev->of_node,
  351. "qcom,cdc-dmic-clk-drv-strength",
  352. &prop_val))) {
  353. dmic_clk_drive = prop_val;
  354. if (dmic_clk_drive != 2 && dmic_clk_drive != 4 &&
  355. dmic_clk_drive != 8 && dmic_clk_drive != 16)
  356. dev_err(dev, "Invalid cdc-dmic-clk-drv-strength %d\n",
  357. dmic_clk_drive);
  358. }
  359. pdata->dmic_clk_drv = dmic_clk_drive;
  360. rc = of_property_read_u32(dev->of_node,
  361. "qcom,vote-dynamic-supply-on-demand",
  362. &pdata->vote_regulator_on_demand);
  363. if (rc)
  364. dev_dbg(dev, "%s No entry for %s property in node %s\n",
  365. __func__, "qcom,vote-dynamic-supply-on-demand",
  366. dev->of_node->full_name);
  367. return pdata;
  368. err_parse_dt_prop:
  369. devm_kfree(dev, pdata->regulator);
  370. pdata->regulator = NULL;
  371. pdata->num_supplies = 0;
  372. err_power_sup:
  373. devm_kfree(dev, pdata);
  374. return NULL;
  375. }
  376. EXPORT_SYMBOL(wcd9xxx_populate_dt_data);
  377. static bool is_wcd9xxx_reg_power_down(struct wcd9xxx *wcd9xxx, u16 rreg)
  378. {
  379. bool ret = false;
  380. int i;
  381. struct wcd9xxx_power_region *wcd9xxx_pwr;
  382. if (!wcd9xxx)
  383. return ret;
  384. for (i = 0; i < WCD9XXX_MAX_PWR_REGIONS; i++) {
  385. wcd9xxx_pwr = wcd9xxx->wcd9xxx_pwr[i];
  386. if (!wcd9xxx_pwr)
  387. continue;
  388. if (((wcd9xxx_pwr->pwr_collapse_reg_min == 0) &&
  389. (wcd9xxx_pwr->pwr_collapse_reg_max == 0)) ||
  390. (wcd9xxx_pwr->power_state ==
  391. WCD_REGION_POWER_COLLAPSE_REMOVE))
  392. ret = false;
  393. else if (((wcd9xxx_pwr->power_state ==
  394. WCD_REGION_POWER_DOWN) ||
  395. (wcd9xxx_pwr->power_state ==
  396. WCD_REGION_POWER_COLLAPSE_BEGIN)) &&
  397. (rreg >= wcd9xxx_pwr->pwr_collapse_reg_min) &&
  398. (rreg <= wcd9xxx_pwr->pwr_collapse_reg_max))
  399. ret = true;
  400. }
  401. return ret;
  402. }
  403. /*
  404. * wcd9xxx_page_write:
  405. * Retrieve page number from register and
  406. * write that page number to the page address.
  407. * Called under io_lock acquisition.
  408. *
  409. * @wcd9xxx: pointer to wcd9xxx
  410. * @reg: Register address from which page number is retrieved
  411. *
  412. * Returns 0 for success and negative error code for failure.
  413. */
  414. int wcd9xxx_page_write(struct wcd9xxx *wcd9xxx, unsigned short *reg)
  415. {
  416. int ret = 0;
  417. unsigned short c_reg, reg_addr;
  418. u8 pg_num, prev_pg_num;
  419. if (wcd9xxx->type != WCD9335 && wcd9xxx->type != WCD934X)
  420. return ret;
  421. c_reg = *reg;
  422. pg_num = c_reg >> 8;
  423. reg_addr = c_reg & 0xff;
  424. if (wcd9xxx->prev_pg_valid) {
  425. prev_pg_num = wcd9xxx->prev_pg;
  426. if (prev_pg_num != pg_num) {
  427. ret = wcd9xxx->write_dev(
  428. wcd9xxx, PAGE_REG_ADDR, 1,
  429. (void *) &pg_num, false);
  430. if (ret < 0)
  431. pr_err("page write error, pg_num: 0x%x\n",
  432. pg_num);
  433. else {
  434. wcd9xxx->prev_pg = pg_num;
  435. dev_dbg(wcd9xxx->dev, "%s: Page 0x%x Write to 0x00\n",
  436. __func__, pg_num);
  437. }
  438. }
  439. } else {
  440. ret = wcd9xxx->write_dev(
  441. wcd9xxx, PAGE_REG_ADDR, 1, (void *) &pg_num,
  442. false);
  443. if (ret < 0)
  444. pr_err("page write error, pg_num: 0x%x\n", pg_num);
  445. else {
  446. wcd9xxx->prev_pg = pg_num;
  447. wcd9xxx->prev_pg_valid = true;
  448. dev_dbg(wcd9xxx->dev, "%s: Page 0x%x Write to 0x00\n",
  449. __func__, pg_num);
  450. }
  451. }
  452. *reg = reg_addr;
  453. return ret;
  454. }
  455. EXPORT_SYMBOL(wcd9xxx_page_write);
  456. static int regmap_bus_read(void *context, const void *reg, size_t reg_size,
  457. void *val, size_t val_size)
  458. {
  459. struct device *dev = context;
  460. struct wcd9xxx *wcd9xxx = dev_get_drvdata(dev);
  461. unsigned short c_reg, rreg;
  462. int ret, i;
  463. if (!wcd9xxx) {
  464. dev_err(dev, "%s: wcd9xxx is NULL\n", __func__);
  465. return -EINVAL;
  466. }
  467. if (!reg || !val) {
  468. dev_err(dev, "%s: reg or val is NULL\n", __func__);
  469. return -EINVAL;
  470. }
  471. if (reg_size != REG_BYTES) {
  472. dev_err(dev, "%s: register size %zd bytes, not supported\n",
  473. __func__, reg_size);
  474. return -EINVAL;
  475. }
  476. mutex_lock(&wcd9xxx->io_lock);
  477. c_reg = *(u16 *)reg;
  478. rreg = c_reg;
  479. if (is_wcd9xxx_reg_power_down(wcd9xxx, rreg)) {
  480. ret = 0;
  481. for (i = 0; i < val_size; i++)
  482. ((u8 *)val)[i] = 0;
  483. goto err;
  484. }
  485. ret = wcd9xxx_page_write(wcd9xxx, &c_reg);
  486. if (ret)
  487. goto err;
  488. ret = wcd9xxx->read_dev(wcd9xxx, c_reg, val_size, val, false);
  489. if (ret < 0)
  490. dev_err(dev, "%s: Codec read failed (%d), reg: 0x%x, size:%zd\n",
  491. __func__, ret, rreg, val_size);
  492. else {
  493. for (i = 0; i < val_size; i++)
  494. dev_dbg(dev, "%s: Read 0x%02x from 0x%x\n",
  495. __func__, ((u8 *)val)[i], rreg + i);
  496. }
  497. err:
  498. mutex_unlock(&wcd9xxx->io_lock);
  499. return ret;
  500. }
  501. static int regmap_bus_gather_write(void *context,
  502. const void *reg, size_t reg_size,
  503. const void *val, size_t val_size)
  504. {
  505. struct device *dev = context;
  506. struct wcd9xxx *wcd9xxx = dev_get_drvdata(dev);
  507. unsigned short c_reg, rreg;
  508. int ret, i;
  509. if (!wcd9xxx) {
  510. dev_err(dev, "%s: wcd9xxx is NULL\n", __func__);
  511. return -EINVAL;
  512. }
  513. if (!reg || !val) {
  514. dev_err(dev, "%s: reg or val is NULL\n", __func__);
  515. return -EINVAL;
  516. }
  517. if (reg_size != REG_BYTES) {
  518. dev_err(dev, "%s: register size %zd bytes, not supported\n",
  519. __func__, reg_size);
  520. return -EINVAL;
  521. }
  522. mutex_lock(&wcd9xxx->io_lock);
  523. c_reg = *(u16 *)reg;
  524. rreg = c_reg;
  525. if (is_wcd9xxx_reg_power_down(wcd9xxx, rreg)) {
  526. ret = 0;
  527. goto err;
  528. }
  529. ret = wcd9xxx_page_write(wcd9xxx, &c_reg);
  530. if (ret)
  531. goto err;
  532. for (i = 0; i < val_size; i++)
  533. dev_dbg(dev, "Write %02x to 0x%x\n", ((u8 *)val)[i],
  534. rreg + i);
  535. ret = wcd9xxx->write_dev(wcd9xxx, c_reg, val_size, (void *) val,
  536. false);
  537. if (ret < 0)
  538. dev_err(dev, "%s: Codec write failed (%d), reg:0x%x, size:%zd\n",
  539. __func__, ret, rreg, val_size);
  540. err:
  541. mutex_unlock(&wcd9xxx->io_lock);
  542. return ret;
  543. }
  544. static int regmap_bus_write(void *context, const void *data, size_t count)
  545. {
  546. struct device *dev = context;
  547. struct wcd9xxx *wcd9xxx = dev_get_drvdata(dev);
  548. if (!wcd9xxx)
  549. return -EINVAL;
  550. WARN_ON(count < REG_BYTES);
  551. if (count > (REG_BYTES + VAL_BYTES)) {
  552. if (wcd9xxx->multi_reg_write)
  553. return wcd9xxx->multi_reg_write(wcd9xxx,
  554. data, count);
  555. } else
  556. return regmap_bus_gather_write(context, data, REG_BYTES,
  557. data + REG_BYTES,
  558. count - REG_BYTES);
  559. dev_err(dev, "%s: bus multi reg write failure\n", __func__);
  560. return -EINVAL;
  561. }
  562. static struct regmap_bus regmap_bus_config = {
  563. .write = regmap_bus_write,
  564. .gather_write = regmap_bus_gather_write,
  565. .read = regmap_bus_read,
  566. .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
  567. .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
  568. };
  569. /*
  570. * wcd9xxx_regmap_init:
  571. * Initialize wcd9xxx register map
  572. *
  573. * @dev: pointer to wcd device
  574. * @config: pointer to register map config
  575. *
  576. * Returns pointer to regmap structure for success
  577. * or NULL in case of failure.
  578. */
  579. struct regmap *wcd9xxx_regmap_init(struct device *dev,
  580. const struct regmap_config *config)
  581. {
  582. return devm_regmap_init(dev, &regmap_bus_config, dev, config);
  583. }
  584. EXPORT_SYMBOL(wcd9xxx_regmap_init);
  585. /*
  586. * wcd9xxx_reset:
  587. * Reset wcd9xxx codec
  588. *
  589. * @dev: pointer to wcd device
  590. *
  591. * Returns 0 for success or negative error code in case of failure
  592. */
  593. int wcd9xxx_reset(struct device *dev)
  594. {
  595. struct wcd9xxx *wcd9xxx;
  596. int rc;
  597. int value;
  598. if (!dev)
  599. return -ENODEV;
  600. wcd9xxx = dev_get_drvdata(dev);
  601. if (!wcd9xxx)
  602. return -EINVAL;
  603. if (!wcd9xxx->wcd_rst_np) {
  604. dev_err(dev, "%s: reset gpio device node not specified\n",
  605. __func__);
  606. return -EINVAL;
  607. }
  608. value = msm_cdc_pinctrl_get_state(wcd9xxx->wcd_rst_np);
  609. if (value > 0) {
  610. wcd9xxx->avoid_cdc_rstlow = 1;
  611. return 0;
  612. }
  613. rc = msm_cdc_pinctrl_select_sleep_state(wcd9xxx->wcd_rst_np);
  614. if (rc) {
  615. dev_err(dev, "%s: wcd sleep state request fail!\n",
  616. __func__);
  617. return rc;
  618. }
  619. /* 20ms sleep required after pulling the reset gpio to LOW */
  620. msleep(20);
  621. rc = msm_cdc_pinctrl_select_active_state(wcd9xxx->wcd_rst_np);
  622. if (rc) {
  623. dev_err(dev, "%s: wcd active state request fail!\n",
  624. __func__);
  625. return rc;
  626. }
  627. msleep(20);
  628. return rc;
  629. }
  630. EXPORT_SYMBOL(wcd9xxx_reset);
  631. /*
  632. * wcd9xxx_reset_low:
  633. * Pull the wcd9xxx codec reset_n to low
  634. *
  635. * @dev: pointer to wcd device
  636. *
  637. * Returns 0 for success or negative error code in case of failure
  638. */
  639. int wcd9xxx_reset_low(struct device *dev)
  640. {
  641. struct wcd9xxx *wcd9xxx;
  642. int rc;
  643. if (!dev)
  644. return -ENODEV;
  645. wcd9xxx = dev_get_drvdata(dev);
  646. if (!wcd9xxx)
  647. return -EINVAL;
  648. if (!wcd9xxx->wcd_rst_np) {
  649. dev_err(dev, "%s: reset gpio device node not specified\n",
  650. __func__);
  651. return -EINVAL;
  652. }
  653. if (wcd9xxx->avoid_cdc_rstlow) {
  654. wcd9xxx->avoid_cdc_rstlow = 0;
  655. dev_dbg(dev, "%s: avoid pull down of reset GPIO\n", __func__);
  656. return 0;
  657. }
  658. rc = msm_cdc_pinctrl_select_sleep_state(wcd9xxx->wcd_rst_np);
  659. if (rc)
  660. dev_err(dev, "%s: wcd sleep state request fail!\n",
  661. __func__);
  662. return rc;
  663. }
  664. EXPORT_SYMBOL(wcd9xxx_reset_low);
  665. /*
  666. * wcd9xxx_bringup:
  667. * Toggle reset analog and digital cores of wcd9xxx codec
  668. *
  669. * @dev: pointer to wcd device
  670. *
  671. * Returns 0 for success or negative error code in case of failure
  672. */
  673. int wcd9xxx_bringup(struct device *dev)
  674. {
  675. struct wcd9xxx *wcd9xxx;
  676. int rc;
  677. codec_bringup_fn cdc_bup_fn;
  678. if (!dev)
  679. return -ENODEV;
  680. wcd9xxx = dev_get_drvdata(dev);
  681. if (!wcd9xxx)
  682. return -EINVAL;
  683. cdc_bup_fn = wcd9xxx_bringup_fn(wcd9xxx->type);
  684. if (!cdc_bup_fn) {
  685. dev_err(dev, "%s: Codec bringup fn NULL!\n",
  686. __func__);
  687. return -EINVAL;
  688. }
  689. rc = cdc_bup_fn(wcd9xxx);
  690. if (rc)
  691. dev_err(dev, "%s: Codec bringup error, rc: %d\n",
  692. __func__, rc);
  693. return rc;
  694. }
  695. EXPORT_SYMBOL(wcd9xxx_bringup);
  696. /*
  697. * wcd9xxx_bringup:
  698. * Set analog and digital cores of wcd9xxx codec in reset state
  699. *
  700. * @dev: pointer to wcd device
  701. *
  702. * Returns 0 for success or negative error code in case of failure
  703. */
  704. int wcd9xxx_bringdown(struct device *dev)
  705. {
  706. struct wcd9xxx *wcd9xxx;
  707. int rc;
  708. codec_bringdown_fn cdc_bdown_fn;
  709. if (!dev)
  710. return -ENODEV;
  711. wcd9xxx = dev_get_drvdata(dev);
  712. if (!wcd9xxx)
  713. return -EINVAL;
  714. cdc_bdown_fn = wcd9xxx_bringdown_fn(wcd9xxx->type);
  715. if (!cdc_bdown_fn) {
  716. dev_err(dev, "%s: Codec bring down fn NULL!\n",
  717. __func__);
  718. return -EINVAL;
  719. }
  720. rc = cdc_bdown_fn(wcd9xxx);
  721. if (rc)
  722. dev_err(dev, "%s: Codec bring down error, rc: %d\n",
  723. __func__, rc);
  724. return rc;
  725. }
  726. EXPORT_SYMBOL(wcd9xxx_bringdown);
  727. /*
  728. * wcd9xxx_get_codec_info:
  729. * Fill codec specific information like interrupts, version
  730. *
  731. * @dev: pointer to wcd device
  732. *
  733. * Returns 0 for success or negative error code in case of failure
  734. */
  735. int wcd9xxx_get_codec_info(struct device *dev)
  736. {
  737. struct wcd9xxx *wcd9xxx;
  738. int rc;
  739. codec_type_fn cdc_type_fn;
  740. struct wcd9xxx_codec_type *cinfo;
  741. if (!dev)
  742. return -ENODEV;
  743. wcd9xxx = dev_get_drvdata(dev);
  744. if (!wcd9xxx)
  745. return -EINVAL;
  746. cdc_type_fn = wcd9xxx_get_codec_info_fn(wcd9xxx->type);
  747. if (!cdc_type_fn) {
  748. dev_err(dev, "%s: Codec fill type fn NULL!\n",
  749. __func__);
  750. return -EINVAL;
  751. }
  752. cinfo = wcd9xxx->codec_type;
  753. if (!cinfo)
  754. return -EINVAL;
  755. rc = cdc_type_fn(wcd9xxx, cinfo);
  756. if (rc) {
  757. dev_err(dev, "%s: Codec type fill failed, rc:%d\n",
  758. __func__, rc);
  759. return rc;
  760. }
  761. switch (wcd9xxx->type) {
  762. case WCD934X:
  763. cinfo->dev = tavil_devs;
  764. cinfo->size = ARRAY_SIZE(tavil_devs);
  765. break;
  766. case WCD9335:
  767. cinfo->dev = tasha_devs;
  768. cinfo->size = ARRAY_SIZE(tasha_devs);
  769. break;
  770. case WCD9330:
  771. cinfo->dev = tomtom_devs;
  772. cinfo->size = ARRAY_SIZE(tomtom_devs);
  773. break;
  774. default:
  775. cinfo->dev = NULL;
  776. cinfo->size = 0;
  777. break;
  778. }
  779. return rc;
  780. }
  781. EXPORT_SYMBOL(wcd9xxx_get_codec_info);
  782. /*
  783. * wcd9xxx_core_irq_init:
  784. * Initialize wcd9xxx codec irq instance
  785. *
  786. * @wcd9xxx_core_res: pointer to wcd core resource
  787. *
  788. * Returns 0 for success or negative error code in case of failure
  789. */
  790. int wcd9xxx_core_irq_init(
  791. struct wcd9xxx_core_resource *wcd9xxx_core_res)
  792. {
  793. int ret = 0;
  794. if (!wcd9xxx_core_res)
  795. return -EINVAL;
  796. if (wcd9xxx_core_res->irq != 1) {
  797. ret = wcd9xxx_irq_init(wcd9xxx_core_res);
  798. if (ret)
  799. pr_err("IRQ initialization failed\n");
  800. }
  801. return ret;
  802. }
  803. EXPORT_SYMBOL(wcd9xxx_core_irq_init);
  804. /*
  805. * wcd9xxx_assign_irq:
  806. * Assign irq and irq_base to wcd9xxx core resource
  807. *
  808. * @wcd9xxx_core_res: pointer to wcd core resource
  809. * @irq: irq number
  810. * @irq_base: base irq number
  811. *
  812. * Returns 0 for success or negative error code in case of failure
  813. */
  814. int wcd9xxx_assign_irq(
  815. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  816. unsigned int irq,
  817. unsigned int irq_base)
  818. {
  819. if (!wcd9xxx_core_res)
  820. return -EINVAL;
  821. wcd9xxx_core_res->irq = irq;
  822. wcd9xxx_core_res->irq_base = irq_base;
  823. return 0;
  824. }
  825. EXPORT_SYMBOL(wcd9xxx_assign_irq);
  826. /*
  827. * wcd9xxx_core_res_init:
  828. * Initialize wcd core resource instance
  829. *
  830. * @wcd9xxx_core_res: pointer to wcd core resource
  831. * @num_irqs: number of irqs for wcd9xxx core
  832. * @num_irq_regs: number of irq registers
  833. * @wcd_regmap: pointer to the wcd register map
  834. *
  835. * Returns 0 for success or negative error code in case of failure
  836. */
  837. int wcd9xxx_core_res_init(
  838. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  839. int num_irqs, int num_irq_regs, struct regmap *wcd_regmap)
  840. {
  841. if (!wcd9xxx_core_res || !wcd_regmap)
  842. return -EINVAL;
  843. mutex_init(&wcd9xxx_core_res->pm_lock);
  844. wcd9xxx_core_res->wlock_holders = 0;
  845. wcd9xxx_core_res->pm_state = WCD9XXX_PM_SLEEPABLE;
  846. init_waitqueue_head(&wcd9xxx_core_res->pm_wq);
  847. pm_qos_add_request(&wcd9xxx_core_res->pm_qos_req,
  848. PM_QOS_CPU_DMA_LATENCY,
  849. PM_QOS_DEFAULT_VALUE);
  850. wcd9xxx_core_res->num_irqs = num_irqs;
  851. wcd9xxx_core_res->num_irq_regs = num_irq_regs;
  852. wcd9xxx_core_res->wcd_core_regmap = wcd_regmap;
  853. pr_debug("%s: num_irqs = %d, num_irq_regs = %d\n",
  854. __func__, wcd9xxx_core_res->num_irqs,
  855. wcd9xxx_core_res->num_irq_regs);
  856. return 0;
  857. }
  858. EXPORT_SYMBOL(wcd9xxx_core_res_init);
  859. /*
  860. * wcd9xxx_core_res_deinit:
  861. * Deinit wcd core resource instance
  862. *
  863. * @wcd9xxx_core_res: pointer to wcd core resource
  864. */
  865. void wcd9xxx_core_res_deinit(struct wcd9xxx_core_resource *wcd9xxx_core_res)
  866. {
  867. if (!wcd9xxx_core_res)
  868. return;
  869. pm_qos_remove_request(&wcd9xxx_core_res->pm_qos_req);
  870. mutex_destroy(&wcd9xxx_core_res->pm_lock);
  871. }
  872. EXPORT_SYMBOL(wcd9xxx_core_res_deinit);
  873. /*
  874. * wcd9xxx_pm_cmpxchg:
  875. * Check old state and exchange with pm new state
  876. * if old state matches with current state
  877. *
  878. * @wcd9xxx_core_res: pointer to wcd core resource
  879. * @o: pm old state
  880. * @n: pm new state
  881. *
  882. * Returns old state
  883. */
  884. enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(
  885. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  886. enum wcd9xxx_pm_state o,
  887. enum wcd9xxx_pm_state n)
  888. {
  889. enum wcd9xxx_pm_state old;
  890. if (!wcd9xxx_core_res)
  891. return o;
  892. mutex_lock(&wcd9xxx_core_res->pm_lock);
  893. old = wcd9xxx_core_res->pm_state;
  894. if (old == o)
  895. wcd9xxx_core_res->pm_state = n;
  896. mutex_unlock(&wcd9xxx_core_res->pm_lock);
  897. return old;
  898. }
  899. EXPORT_SYMBOL(wcd9xxx_pm_cmpxchg);
  900. /*
  901. * wcd9xxx_core_res_suspend:
  902. * Suspend callback function for wcd9xxx core
  903. *
  904. * @wcd9xxx_core_res: pointer to wcd core resource
  905. * @pm_message_t: pm message
  906. *
  907. * Returns 0 for success or negative error code for failure/busy
  908. */
  909. int wcd9xxx_core_res_suspend(
  910. struct wcd9xxx_core_resource *wcd9xxx_core_res,
  911. pm_message_t pmesg)
  912. {
  913. int ret = 0;
  914. pr_debug("%s: enter\n", __func__);
  915. /*
  916. * pm_qos_update_request() can be called after this suspend chain call
  917. * started. thus suspend can be called while lock is being held
  918. */
  919. mutex_lock(&wcd9xxx_core_res->pm_lock);
  920. if (wcd9xxx_core_res->pm_state == WCD9XXX_PM_SLEEPABLE) {
  921. pr_debug("%s: suspending system, state %d, wlock %d\n",
  922. __func__, wcd9xxx_core_res->pm_state,
  923. wcd9xxx_core_res->wlock_holders);
  924. wcd9xxx_core_res->pm_state = WCD9XXX_PM_ASLEEP;
  925. } else if (wcd9xxx_core_res->pm_state == WCD9XXX_PM_AWAKE) {
  926. /*
  927. * unlock to wait for pm_state == WCD9XXX_PM_SLEEPABLE
  928. * then set to WCD9XXX_PM_ASLEEP
  929. */
  930. pr_debug("%s: waiting to suspend system, state %d, wlock %d\n",
  931. __func__, wcd9xxx_core_res->pm_state,
  932. wcd9xxx_core_res->wlock_holders);
  933. mutex_unlock(&wcd9xxx_core_res->pm_lock);
  934. if (!(wait_event_timeout(wcd9xxx_core_res->pm_wq,
  935. wcd9xxx_pm_cmpxchg(wcd9xxx_core_res,
  936. WCD9XXX_PM_SLEEPABLE,
  937. WCD9XXX_PM_ASLEEP) ==
  938. WCD9XXX_PM_SLEEPABLE,
  939. HZ))) {
  940. pr_debug("%s: suspend failed state %d, wlock %d\n",
  941. __func__, wcd9xxx_core_res->pm_state,
  942. wcd9xxx_core_res->wlock_holders);
  943. ret = -EBUSY;
  944. } else {
  945. pr_debug("%s: done, state %d, wlock %d\n", __func__,
  946. wcd9xxx_core_res->pm_state,
  947. wcd9xxx_core_res->wlock_holders);
  948. }
  949. mutex_lock(&wcd9xxx_core_res->pm_lock);
  950. } else if (wcd9xxx_core_res->pm_state == WCD9XXX_PM_ASLEEP) {
  951. pr_warn("%s: system is already suspended, state %d, wlock %dn",
  952. __func__, wcd9xxx_core_res->pm_state,
  953. wcd9xxx_core_res->wlock_holders);
  954. }
  955. mutex_unlock(&wcd9xxx_core_res->pm_lock);
  956. return ret;
  957. }
  958. EXPORT_SYMBOL(wcd9xxx_core_res_suspend);
  959. /*
  960. * wcd9xxx_core_res_resume:
  961. * Resume callback function for wcd9xxx core
  962. *
  963. * @wcd9xxx_core_res: pointer to wcd core resource
  964. *
  965. * Returns 0 for success or negative error code for failure/busy
  966. */
  967. int wcd9xxx_core_res_resume(
  968. struct wcd9xxx_core_resource *wcd9xxx_core_res)
  969. {
  970. int ret = 0;
  971. pr_debug("%s: enter\n", __func__);
  972. mutex_lock(&wcd9xxx_core_res->pm_lock);
  973. if (wcd9xxx_core_res->pm_state == WCD9XXX_PM_ASLEEP) {
  974. pr_debug("%s: resuming system, state %d, wlock %d\n", __func__,
  975. wcd9xxx_core_res->pm_state,
  976. wcd9xxx_core_res->wlock_holders);
  977. wcd9xxx_core_res->pm_state = WCD9XXX_PM_SLEEPABLE;
  978. } else {
  979. pr_warn("%s: system is already awake, state %d wlock %d\n",
  980. __func__, wcd9xxx_core_res->pm_state,
  981. wcd9xxx_core_res->wlock_holders);
  982. }
  983. mutex_unlock(&wcd9xxx_core_res->pm_lock);
  984. wake_up_all(&wcd9xxx_core_res->pm_wq);
  985. return ret;
  986. }
  987. EXPORT_SYMBOL(wcd9xxx_core_res_resume);
  988. /*
  989. * wcd9xxx_get_intf_type:
  990. * Get interface type of wcd9xxx core
  991. *
  992. * Returns interface type
  993. */
  994. enum wcd9xxx_intf_status wcd9xxx_get_intf_type(void)
  995. {
  996. return wcd9xxx_intf;
  997. }
  998. EXPORT_SYMBOL(wcd9xxx_get_intf_type);
  999. /*
  1000. * wcd9xxx_set_intf_type:
  1001. * Set interface type of wcd9xxx core
  1002. *
  1003. */
  1004. void wcd9xxx_set_intf_type(enum wcd9xxx_intf_status intf_status)
  1005. {
  1006. wcd9xxx_intf = intf_status;
  1007. }
  1008. EXPORT_SYMBOL(wcd9xxx_set_intf_type);
  1009. /*
  1010. * wcd9xxx_set_power_state: set power state for the region
  1011. * @wcd9xxx: handle to wcd core
  1012. * @state: power state to be set
  1013. * @region: region index
  1014. *
  1015. * Returns error code in case of failure or 0 for success
  1016. */
  1017. int wcd9xxx_set_power_state(struct wcd9xxx *wcd9xxx,
  1018. enum codec_power_states state,
  1019. enum wcd_power_regions region)
  1020. {
  1021. if (!wcd9xxx) {
  1022. pr_err("%s: wcd9xxx is NULL\n", __func__);
  1023. return -EINVAL;
  1024. }
  1025. if ((region < 0) || (region >= WCD9XXX_MAX_PWR_REGIONS)) {
  1026. dev_err(wcd9xxx->dev, "%s: region index %d out of bounds\n",
  1027. __func__, region);
  1028. return -EINVAL;
  1029. }
  1030. if (!wcd9xxx->wcd9xxx_pwr[region]) {
  1031. dev_err(wcd9xxx->dev, "%s: memory not created for region: %d\n",
  1032. __func__, region);
  1033. return -EINVAL;
  1034. }
  1035. mutex_lock(&wcd9xxx->io_lock);
  1036. wcd9xxx->wcd9xxx_pwr[region]->power_state = state;
  1037. mutex_unlock(&wcd9xxx->io_lock);
  1038. return 0;
  1039. }
  1040. EXPORT_SYMBOL(wcd9xxx_set_power_state);
  1041. /*
  1042. * wcd9xxx_get_current_power_state: Get power state of the region
  1043. * @wcd9xxx: handle to wcd core
  1044. * @region: region index
  1045. *
  1046. * Returns current power state of the region or error code for failure
  1047. */
  1048. int wcd9xxx_get_current_power_state(struct wcd9xxx *wcd9xxx,
  1049. enum wcd_power_regions region)
  1050. {
  1051. int state;
  1052. if (!wcd9xxx) {
  1053. pr_err("%s: wcd9xxx is NULL\n", __func__);
  1054. return -EINVAL;
  1055. }
  1056. if ((region < 0) || (region >= WCD9XXX_MAX_PWR_REGIONS)) {
  1057. dev_err(wcd9xxx->dev, "%s: region index %d out of bounds\n",
  1058. __func__, region);
  1059. return -EINVAL;
  1060. }
  1061. if (!wcd9xxx->wcd9xxx_pwr[region]) {
  1062. dev_err(wcd9xxx->dev, "%s: memory not created for region: %d\n",
  1063. __func__, region);
  1064. return -EINVAL;
  1065. }
  1066. mutex_lock(&wcd9xxx->io_lock);
  1067. state = wcd9xxx->wcd9xxx_pwr[region]->power_state;
  1068. mutex_unlock(&wcd9xxx->io_lock);
  1069. return state;
  1070. }
  1071. EXPORT_SYMBOL(wcd9xxx_get_current_power_state);