wcd934x-routing.h 50 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef WCD934X_ROUTING_H
  6. #define WCD934X_ROUTING_H
  7. #include <sound/soc-dapm.h>
  8. const struct snd_soc_dapm_route tavil_slim_audio_map[] = {
  9. {"AIF4 MAD", NULL, "AIF4_MAD Mixer"},
  10. /* Virtual input widget Mixer SLIMBUS*/
  11. {"AIF1_CAP Mixer", "SLIM TX0", "SLIM TX0"},
  12. {"AIF1_CAP Mixer", "SLIM TX1", "SLIM TX1"},
  13. {"AIF1_CAP Mixer", "SLIM TX2", "SLIM TX2"},
  14. {"AIF1_CAP Mixer", "SLIM TX3", "SLIM TX3"},
  15. {"AIF1_CAP Mixer", "SLIM TX4", "SLIM TX4"},
  16. {"AIF1_CAP Mixer", "SLIM TX5", "SLIM TX5"},
  17. {"AIF1_CAP Mixer", "SLIM TX6", "SLIM TX6"},
  18. {"AIF1_CAP Mixer", "SLIM TX7", "SLIM TX7"},
  19. {"AIF1_CAP Mixer", "SLIM TX8", "SLIM TX8"},
  20. {"AIF1_CAP Mixer", "SLIM TX9", "SLIM TX9"},
  21. {"AIF1_CAP Mixer", "SLIM TX10", "SLIM TX10"},
  22. {"AIF1_CAP Mixer", "SLIM TX11", "SLIM TX11"},
  23. {"AIF1_CAP Mixer", "SLIM TX13", "SLIM TX13"},
  24. {"AIF2_CAP Mixer", "SLIM TX0", "SLIM TX0"},
  25. {"AIF2_CAP Mixer", "SLIM TX1", "SLIM TX1"},
  26. {"AIF2_CAP Mixer", "SLIM TX2", "SLIM TX2"},
  27. {"AIF2_CAP Mixer", "SLIM TX3", "SLIM TX3"},
  28. {"AIF2_CAP Mixer", "SLIM TX4", "SLIM TX4"},
  29. {"AIF2_CAP Mixer", "SLIM TX5", "SLIM TX5"},
  30. {"AIF2_CAP Mixer", "SLIM TX6", "SLIM TX6"},
  31. {"AIF2_CAP Mixer", "SLIM TX7", "SLIM TX7"},
  32. {"AIF2_CAP Mixer", "SLIM TX8", "SLIM TX8"},
  33. {"AIF2_CAP Mixer", "SLIM TX9", "SLIM TX9"},
  34. {"AIF2_CAP Mixer", "SLIM TX10", "SLIM TX10"},
  35. {"AIF2_CAP Mixer", "SLIM TX11", "SLIM TX11"},
  36. {"AIF2_CAP Mixer", "SLIM TX13", "SLIM TX13"},
  37. {"AIF3_CAP Mixer", "SLIM TX0", "SLIM TX0"},
  38. {"AIF3_CAP Mixer", "SLIM TX1", "SLIM TX1"},
  39. {"AIF3_CAP Mixer", "SLIM TX2", "SLIM TX2"},
  40. {"AIF3_CAP Mixer", "SLIM TX3", "SLIM TX3"},
  41. {"AIF3_CAP Mixer", "SLIM TX4", "SLIM TX4"},
  42. {"AIF3_CAP Mixer", "SLIM TX5", "SLIM TX5"},
  43. {"AIF3_CAP Mixer", "SLIM TX6", "SLIM TX6"},
  44. {"AIF3_CAP Mixer", "SLIM TX7", "SLIM TX7"},
  45. {"AIF3_CAP Mixer", "SLIM TX8", "SLIM TX8"},
  46. {"AIF3_CAP Mixer", "SLIM TX9", "SLIM TX9"},
  47. {"AIF3_CAP Mixer", "SLIM TX10", "SLIM TX10"},
  48. {"AIF3_CAP Mixer", "SLIM TX11", "SLIM TX11"},
  49. {"AIF3_CAP Mixer", "SLIM TX13", "SLIM TX13"},
  50. {"AIF4_MAD Mixer", "SLIM TX13", "SLIM TX13"},
  51. /* CDC Tx interface with SLIMBUS */
  52. {"SLIM TX0", NULL, "CDC_IF TX0 MUX"},
  53. {"SLIM TX1", NULL, "CDC_IF TX1 MUX"},
  54. {"SLIM TX2", NULL, "CDC_IF TX2 MUX"},
  55. {"SLIM TX3", NULL, "CDC_IF TX3 MUX"},
  56. {"SLIM TX4", NULL, "CDC_IF TX4 MUX"},
  57. {"SLIM TX5", NULL, "CDC_IF TX5 MUX"},
  58. {"SLIM TX6", NULL, "CDC_IF TX6 MUX"},
  59. {"SLIM TX7", NULL, "CDC_IF TX7 MUX"},
  60. {"SLIM TX8", NULL, "CDC_IF TX8 MUX"},
  61. {"SLIM TX9", NULL, "CDC_IF TX9 MUX"},
  62. {"SLIM TX10", NULL, "CDC_IF TX10 MUX"},
  63. {"SLIM TX11", NULL, "CDC_IF TX11 MUX"},
  64. {"SLIM TX13", NULL, "CDC_IF TX13 MUX"},
  65. {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
  66. {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
  67. {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
  68. {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
  69. {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
  70. {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
  71. {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
  72. {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
  73. {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
  74. {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
  75. {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
  76. {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
  77. {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
  78. {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
  79. {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
  80. {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
  81. {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
  82. {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
  83. {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
  84. {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
  85. {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
  86. {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
  87. {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
  88. {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
  89. {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
  90. {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
  91. {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
  92. {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
  93. {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
  94. {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
  95. {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
  96. {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
  97. {"SLIM RX0", NULL, "SLIM RX0 MUX"},
  98. {"SLIM RX1", NULL, "SLIM RX1 MUX"},
  99. {"SLIM RX2", NULL, "SLIM RX2 MUX"},
  100. {"SLIM RX3", NULL, "SLIM RX3 MUX"},
  101. {"SLIM RX4", NULL, "SLIM RX4 MUX"},
  102. {"SLIM RX5", NULL, "SLIM RX5 MUX"},
  103. {"SLIM RX6", NULL, "SLIM RX6 MUX"},
  104. {"SLIM RX7", NULL, "SLIM RX7 MUX"},
  105. /* CDC Rx interface with SLIMBUS */
  106. {"CDC_IF RX0 MUX", "SLIM RX0", "SLIM RX0"},
  107. {"CDC_IF RX1 MUX", "SLIM RX1", "SLIM RX1"},
  108. {"CDC_IF RX2 MUX", "SLIM RX2", "SLIM RX2"},
  109. {"CDC_IF RX3 MUX", "SLIM RX3", "SLIM RX3"},
  110. {"CDC_IF RX4 MUX", "SLIM RX4", "SLIM RX4"},
  111. {"CDC_IF RX5 MUX", "SLIM RX5", "SLIM RX5"},
  112. {"CDC_IF RX6 MUX", "SLIM RX6", "SLIM RX6"},
  113. {"CDC_IF RX7 MUX", "SLIM RX7", "SLIM RX7"},
  114. /* VI Feedback */
  115. {"AIF4_VI Mixer", "SPKR_VI_1", "VIINPUT"},
  116. {"AIF4_VI Mixer", "SPKR_VI_2", "VIINPUT"},
  117. {"AIF4 VI", NULL, "AIF4_VI Mixer"},
  118. };
  119. const struct snd_soc_dapm_route tavil_i2s_audio_map[] = {
  120. /* Virtual input widget Mixer I2S*/
  121. {"AIF1_CAP Mixer", "I2S TX1", "I2S TX1"},
  122. {"AIF1_CAP Mixer", "I2S TX2", "I2S TX2"},
  123. {"AIF1_CAP Mixer", "I2S TX3", "I2S TX3"},
  124. {"AIF1_CAP Mixer", "I2S TX4", "I2S TX4"},
  125. {"AIF1_CAP Mixer", "I2S TX5", "I2S TX5"},
  126. {"AIF1_CAP Mixer", "I2S TX6", "I2S TX6"},
  127. {"AIF1_CAP Mixer", "I2S TX7", "I2S TX7"},
  128. {"AIF2_CAP Mixer", "I2S TX8", "I2S TX8"},
  129. {"AIF2_CAP Mixer", "I2S TX11", "I2S TX11"},
  130. {"AIF3_CAP Mixer", "I2S TX0", "I2S TX0"},
  131. {"AIF3_CAP Mixer", "I2S TX1", "I2S TX1"},
  132. /* CDC Tx interface with I2S */
  133. {"I2S TX0", NULL, "CDC_IF TX0 MUX"},
  134. {"I2S TX1", NULL, "CDC_IF TX1 MUX"},
  135. {"I2S TX2", NULL, "CDC_IF TX2 MUX"},
  136. {"I2S TX3", NULL, "CDC_IF TX3 MUX"},
  137. {"I2S TX4", NULL, "CDC_IF TX4 MUX"},
  138. {"I2S TX5", NULL, "CDC_IF TX5 MUX"},
  139. {"I2S TX6", NULL, "CDC_IF TX6 MUX"},
  140. {"I2S TX7", NULL, "CDC_IF TX7 MUX"},
  141. {"I2S TX8", NULL, "CDC_IF TX8 MUX"},
  142. {"I2S TX11", NULL, "CDC_IF TX11 MUX"},
  143. {"I2S RX0 MUX", "AIF1_PB", "AIF1 PB"},
  144. {"I2S RX1 MUX", "AIF1_PB", "AIF1 PB"},
  145. {"I2S RX2 MUX", "AIF1_PB", "AIF1 PB"},
  146. {"I2S RX3 MUX", "AIF1_PB", "AIF1 PB"},
  147. {"I2S RX4 MUX", "AIF1_PB", "AIF1 PB"},
  148. {"I2S RX5 MUX", "AIF1_PB", "AIF1 PB"},
  149. {"I2S RX6 MUX", "AIF1_PB", "AIF1 PB"},
  150. {"I2S RX7 MUX", "AIF1_PB", "AIF1 PB"},
  151. {"I2S RX2 MUX", "AIF2_PB", "AIF2 PB"},
  152. {"I2S RX3 MUX", "AIF2_PB", "AIF2 PB"},
  153. {"I2S RX4 MUX", "AIF3_PB", "AIF3 PB"},
  154. {"I2S RX5 MUX", "AIF3_PB", "AIF3 PB"},
  155. {"I2S RX0", NULL, "I2S RX0 MUX"},
  156. {"I2S RX1", NULL, "I2S RX1 MUX"},
  157. {"I2S RX2", NULL, "I2S RX2 MUX"},
  158. {"I2S RX3", NULL, "I2S RX3 MUX"},
  159. {"I2S RX4", NULL, "I2S RX4 MUX"},
  160. {"I2S RX5", NULL, "I2S RX5 MUX"},
  161. {"I2S RX6", NULL, "I2S RX6 MUX"},
  162. {"I2S RX7", NULL, "I2S RX7 MUX"},
  163. /* CDC Rx interface with I2S */
  164. {"CDC_IF RX0 MUX", "I2S RX0", "I2S RX0"},
  165. {"CDC_IF RX1 MUX", "I2S RX1", "I2S RX1"},
  166. {"CDC_IF RX2 MUX", "I2S RX2", "I2S RX2"},
  167. {"CDC_IF RX3 MUX", "I2S RX3", "I2S RX3"},
  168. {"CDC_IF RX4 MUX", "I2S RX4", "I2S RX4"},
  169. {"CDC_IF RX5 MUX", "I2S RX5", "I2S RX5"},
  170. {"CDC_IF RX6 MUX", "I2S RX6", "I2S RX6"},
  171. {"CDC_IF RX7 MUX", "I2S RX7", "I2S RX7"},
  172. };
  173. const struct snd_soc_dapm_route tavil_audio_map[] = {
  174. /*
  175. * AIF CAP to Mixer routes are common
  176. * for both SLIM as well as I2S
  177. */
  178. /* Virtual input widgets */
  179. {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
  180. {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
  181. {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
  182. /* WDMA3 */
  183. {"WDMA3 PORT0 MUX", "DEC0", "ADC MUX0"},
  184. {"WDMA3 PORT0 MUX", "RX_MIX_TX0", "RX MIX TX0 MUX"},
  185. {"WDMA3 PORT1 MUX", "DEC1", "ADC MUX1"},
  186. {"WDMA3 PORT1 MUX", "RX_MIX_TX1", "RX MIX TX1 MUX"},
  187. {"WDMA3 PORT2 MUX", "DEC2", "ADC MUX2"},
  188. {"WDMA3 PORT2 MUX", "RX_MIX_TX2", "RX MIX TX2 MUX"},
  189. {"WDMA3 PORT3 MUX", "DEC3", "ADC MUX3"},
  190. {"WDMA3 PORT3 MUX", "RX_MIX_TX3", "RX MIX TX3 MUX"},
  191. {"WDMA3 PORT4 MUX", "DEC4", "ADC MUX4"},
  192. {"WDMA3 PORT4 MUX", "RX_MIX_TX4", "RX MIX TX4 MUX"},
  193. {"WDMA3 PORT5 MUX", "DEC5", "ADC MUX5"},
  194. {"WDMA3 PORT5 MUX", "RX_MIX_TX5", "RX MIX TX5 MUX"},
  195. {"WDMA3 PORT6 MUX", "DEC6", "ADC MUX6"},
  196. {"WDMA3 PORT6 MUX", "RX_MIX_TX6", "RX MIX TX6 MUX"},
  197. {"WDMA3 CH0 MUX", "PORT_0", "WDMA3 PORT0 MUX"},
  198. {"WDMA3 CH0 MUX", "PORT_1", "WDMA3 PORT1 MUX"},
  199. {"WDMA3 CH0 MUX", "PORT_2", "WDMA3 PORT2 MUX"},
  200. {"WDMA3 CH0 MUX", "PORT_3", "WDMA3 PORT3 MUX"},
  201. {"WDMA3 CH0 MUX", "PORT_4", "WDMA3 PORT4 MUX"},
  202. {"WDMA3 CH0 MUX", "PORT_5", "WDMA3 PORT5 MUX"},
  203. {"WDMA3 CH0 MUX", "PORT_6", "WDMA3 PORT6 MUX"},
  204. {"WDMA3 CH0 MUX", "PORT_7", "ADC MUX7"},
  205. {"WDMA3 CH0 MUX", "PORT_8", "ADC MUX8"},
  206. {"WDMA3 CH1 MUX", "PORT_0", "WDMA3 PORT0 MUX"},
  207. {"WDMA3 CH1 MUX", "PORT_1", "WDMA3 PORT1 MUX"},
  208. {"WDMA3 CH1 MUX", "PORT_2", "WDMA3 PORT2 MUX"},
  209. {"WDMA3 CH1 MUX", "PORT_3", "WDMA3 PORT3 MUX"},
  210. {"WDMA3 CH1 MUX", "PORT_4", "WDMA3 PORT4 MUX"},
  211. {"WDMA3 CH1 MUX", "PORT_5", "WDMA3 PORT5 MUX"},
  212. {"WDMA3 CH1 MUX", "PORT_6", "WDMA3 PORT6 MUX"},
  213. {"WDMA3 CH1 MUX", "PORT_7", "ADC MUX7"},
  214. {"WDMA3 CH1 MUX", "PORT_8", "ADC MUX8"},
  215. {"WDMA3 CH2 MUX", "PORT_0", "WDMA3 PORT0 MUX"},
  216. {"WDMA3 CH2 MUX", "PORT_1", "WDMA3 PORT1 MUX"},
  217. {"WDMA3 CH2 MUX", "PORT_2", "WDMA3 PORT2 MUX"},
  218. {"WDMA3 CH2 MUX", "PORT_3", "WDMA3 PORT3 MUX"},
  219. {"WDMA3 CH2 MUX", "PORT_4", "WDMA3 PORT4 MUX"},
  220. {"WDMA3 CH2 MUX", "PORT_5", "WDMA3 PORT5 MUX"},
  221. {"WDMA3 CH2 MUX", "PORT_6", "WDMA3 PORT6 MUX"},
  222. {"WDMA3 CH2 MUX", "PORT_7", "ADC MUX7"},
  223. {"WDMA3 CH2 MUX", "PORT_8", "ADC MUX8"},
  224. {"WDMA3 CH3 MUX", "PORT_0", "WDMA3 PORT0 MUX"},
  225. {"WDMA3 CH3 MUX", "PORT_1", "WDMA3 PORT1 MUX"},
  226. {"WDMA3 CH3 MUX", "PORT_2", "WDMA3 PORT2 MUX"},
  227. {"WDMA3 CH3 MUX", "PORT_3", "WDMA3 PORT3 MUX"},
  228. {"WDMA3 CH3 MUX", "PORT_4", "WDMA3 PORT4 MUX"},
  229. {"WDMA3 CH3 MUX", "PORT_5", "WDMA3 PORT5 MUX"},
  230. {"WDMA3 CH3 MUX", "PORT_6", "WDMA3 PORT6 MUX"},
  231. {"WDMA3 CH3 MUX", "PORT_7", "ADC MUX7"},
  232. {"WDMA3 CH3 MUX", "PORT_8", "ADC MUX8"},
  233. {"WDMA3_CH_MIXER", NULL, "WDMA3 CH0 MUX"},
  234. {"WDMA3_CH_MIXER", NULL, "WDMA3 CH1 MUX"},
  235. {"WDMA3_CH_MIXER", NULL, "WDMA3 CH2 MUX"},
  236. {"WDMA3_CH_MIXER", NULL, "WDMA3 CH3 MUX"},
  237. {"WDMA3_ON_OFF", "Switch", "WDMA3_CH_MIXER"},
  238. {"WDMA3_OUT", NULL, "WDMA3_ON_OFF"},
  239. /* MAD */
  240. {"MAD_SEL MUX", "SPE", "MAD_CPE_INPUT"},
  241. {"MAD_SEL MUX", "MSM", "MADINPUT"},
  242. {"MAD_INP MUX", "MAD", "MAD_SEL MUX"},
  243. {"MAD_INP MUX", "DEC1", "ADC MUX1"},
  244. {"MAD_BROADCAST", "Switch", "MAD_INP MUX"},
  245. {"MAD_CPE1", "Switch", "MAD_INP MUX"},
  246. {"MAD_CPE2", "Switch", "MAD_INP MUX"},
  247. {"MAD_CPE_OUT1", NULL, "MAD_CPE1"},
  248. {"MAD_CPE_OUT2", NULL, "MAD_CPE2"},
  249. {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
  250. {"CDC_IF TX0 MUX", "RX_MIX_TX0", "RX MIX TX0 MUX"},
  251. {"CDC_IF TX0 MUX", "DEC0_192", "ADC US MUX0"},
  252. {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
  253. {"CDC_IF TX1 MUX", "RX_MIX_TX1", "RX MIX TX1 MUX"},
  254. {"CDC_IF TX1 MUX", "DEC1_192", "ADC US MUX1"},
  255. {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
  256. {"CDC_IF TX2 MUX", "RX_MIX_TX2", "RX MIX TX2 MUX"},
  257. {"CDC_IF TX2 MUX", "DEC2_192", "ADC US MUX2"},
  258. {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
  259. {"CDC_IF TX3 MUX", "RX_MIX_TX3", "RX MIX TX3 MUX"},
  260. {"CDC_IF TX3 MUX", "DEC3_192", "ADC US MUX3"},
  261. {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
  262. {"CDC_IF TX4 MUX", "RX_MIX_TX4", "RX MIX TX4 MUX"},
  263. {"CDC_IF TX4 MUX", "DEC4_192", "ADC US MUX4"},
  264. {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
  265. {"CDC_IF TX5 MUX", "RX_MIX_TX5", "RX MIX TX5 MUX"},
  266. {"CDC_IF TX5 MUX", "DEC5_192", "ADC US MUX5"},
  267. {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
  268. {"CDC_IF TX6 MUX", "RX_MIX_TX6", "RX MIX TX6 MUX"},
  269. {"CDC_IF TX6 MUX", "DEC6_192", "ADC US MUX6"},
  270. {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
  271. {"CDC_IF TX7 MUX", "RX_MIX_TX7", "RX MIX TX7 MUX"},
  272. {"CDC_IF TX7 MUX", "DEC7_192", "ADC US MUX7"},
  273. {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
  274. {"CDC_IF TX8 MUX", "RX_MIX_TX8", "RX MIX TX8 MUX"},
  275. {"CDC_IF TX8 MUX", "DEC8_192", "ADC US MUX8"},
  276. {"CDC_IF TX9 MUX", "DEC7", "ADC MUX7"},
  277. {"CDC_IF TX9 MUX", "DEC7_192", "ADC US MUX7"},
  278. {"CDC_IF TX10 MUX", "DEC6", "ADC MUX6"},
  279. {"CDC_IF TX10 MUX", "DEC6_192", "ADC US MUX6"},
  280. {"CDC_IF TX11 MUX", "DEC_0_5", "CDC_IF TX11 INP1 MUX"},
  281. {"CDC_IF TX11 MUX", "DEC_9_12", "CDC_IF TX11 INP1 MUX"},
  282. {"CDC_IF TX11 INP1 MUX", "DEC0", "ADC MUX0"},
  283. {"CDC_IF TX11 INP1 MUX", "DEC1", "ADC MUX1"},
  284. {"CDC_IF TX11 INP1 MUX", "DEC2", "ADC MUX2"},
  285. {"CDC_IF TX11 INP1 MUX", "DEC3", "ADC MUX3"},
  286. {"CDC_IF TX11 INP1 MUX", "DEC4", "ADC MUX4"},
  287. {"CDC_IF TX11 INP1 MUX", "DEC5", "ADC MUX5"},
  288. {"CDC_IF TX11 INP1 MUX", "RX_MIX_TX5", "RX MIX TX5 MUX"},
  289. {"CDC_IF TX13 MUX", "MAD_BRDCST", "MAD_BROADCAST"},
  290. {"CDC_IF TX13 MUX", "CDC_DEC_5", "CDC_IF TX13 INP1 MUX"},
  291. {"CDC_IF TX13 INP1 MUX", "DEC5", "ADC MUX5"},
  292. {"CDC_IF TX13 INP1 MUX", "DEC5_192", "ADC US MUX5"},
  293. {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
  294. {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
  295. {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
  296. {"RX MIX TX0 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
  297. {"RX MIX TX0 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
  298. {"RX MIX TX0 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
  299. {"RX MIX TX0 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
  300. {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
  301. {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
  302. {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
  303. {"RX MIX TX1 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
  304. {"RX MIX TX1 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
  305. {"RX MIX TX1 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
  306. {"RX MIX TX1 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
  307. {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
  308. {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
  309. {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
  310. {"RX MIX TX2 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
  311. {"RX MIX TX2 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
  312. {"RX MIX TX2 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
  313. {"RX MIX TX2 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
  314. {"RX MIX TX3 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
  315. {"RX MIX TX3 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
  316. {"RX MIX TX3 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
  317. {"RX MIX TX3 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
  318. {"RX MIX TX3 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
  319. {"RX MIX TX3 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
  320. {"RX MIX TX3 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
  321. {"RX MIX TX4 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
  322. {"RX MIX TX4 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
  323. {"RX MIX TX4 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
  324. {"RX MIX TX4 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
  325. {"RX MIX TX4 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
  326. {"RX MIX TX4 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
  327. {"RX MIX TX4 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
  328. {"RX MIX TX5 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
  329. {"RX MIX TX5 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
  330. {"RX MIX TX5 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
  331. {"RX MIX TX5 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
  332. {"RX MIX TX5 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
  333. {"RX MIX TX5 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
  334. {"RX MIX TX5 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
  335. {"RX MIX TX6 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
  336. {"RX MIX TX6 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
  337. {"RX MIX TX6 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
  338. {"RX MIX TX6 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
  339. {"RX MIX TX6 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
  340. {"RX MIX TX6 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
  341. {"RX MIX TX6 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
  342. {"RX MIX TX7 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
  343. {"RX MIX TX7 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
  344. {"RX MIX TX7 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
  345. {"RX MIX TX7 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
  346. {"RX MIX TX7 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
  347. {"RX MIX TX7 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
  348. {"RX MIX TX7 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
  349. {"RX MIX TX8 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
  350. {"RX MIX TX8 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
  351. {"RX MIX TX8 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
  352. {"RX MIX TX8 MUX", "RX_MIX3", "RX INT3 SEC MIX"},
  353. {"RX MIX TX8 MUX", "RX_MIX4", "RX INT4 SEC MIX"},
  354. {"RX MIX TX8 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
  355. {"RX MIX TX8 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
  356. {"ADC US MUX0", "US_Switch", "ADC MUX0"},
  357. {"ADC US MUX1", "US_Switch", "ADC MUX1"},
  358. {"ADC US MUX2", "US_Switch", "ADC MUX2"},
  359. {"ADC US MUX3", "US_Switch", "ADC MUX3"},
  360. {"ADC US MUX4", "US_Switch", "ADC MUX4"},
  361. {"ADC US MUX5", "US_Switch", "ADC MUX5"},
  362. {"ADC US MUX6", "US_Switch", "ADC MUX6"},
  363. {"ADC US MUX7", "US_Switch", "ADC MUX7"},
  364. {"ADC US MUX8", "US_Switch", "ADC MUX8"},
  365. {"ADC MUX0", "DMIC", "DMIC MUX0"},
  366. {"ADC MUX0", "AMIC", "AMIC MUX0"},
  367. {"ADC MUX1", "DMIC", "DMIC MUX1"},
  368. {"ADC MUX1", "AMIC", "AMIC MUX1"},
  369. {"ADC MUX2", "DMIC", "DMIC MUX2"},
  370. {"ADC MUX2", "AMIC", "AMIC MUX2"},
  371. {"ADC MUX3", "DMIC", "DMIC MUX3"},
  372. {"ADC MUX3", "AMIC", "AMIC MUX3"},
  373. {"ADC MUX4", "DMIC", "DMIC MUX4"},
  374. {"ADC MUX4", "AMIC", "AMIC MUX4"},
  375. {"ADC MUX5", "DMIC", "DMIC MUX5"},
  376. {"ADC MUX5", "AMIC", "AMIC MUX5"},
  377. {"ADC MUX6", "DMIC", "DMIC MUX6"},
  378. {"ADC MUX6", "AMIC", "AMIC MUX6"},
  379. {"ADC MUX7", "DMIC", "DMIC MUX7"},
  380. {"ADC MUX7", "AMIC", "AMIC MUX7"},
  381. {"ADC MUX8", "DMIC", "DMIC MUX8"},
  382. {"ADC MUX8", "AMIC", "AMIC MUX8"},
  383. {"ADC MUX10", "DMIC", "DMIC MUX10"},
  384. {"ADC MUX10", "AMIC", "AMIC MUX10"},
  385. {"ADC MUX11", "DMIC", "DMIC MUX11"},
  386. {"ADC MUX11", "AMIC", "AMIC MUX11"},
  387. {"ADC MUX12", "DMIC", "DMIC MUX12"},
  388. {"ADC MUX12", "AMIC", "AMIC MUX12"},
  389. {"ADC MUX13", "DMIC", "DMIC MUX13"},
  390. {"ADC MUX13", "AMIC", "AMIC MUX13"},
  391. {"ADC MUX0", "ANC_FB_TUNE1", "ADC MUX10"},
  392. {"ADC MUX0", "ANC_FB_TUNE1", "ADC MUX11"},
  393. {"ADC MUX0", "ANC_FB_TUNE2", "ADC MUX12"},
  394. {"ADC MUX0", "ANC_FB_TUNE2", "ADC MUX13"},
  395. {"ADC MUX1", "ANC_FB_TUNE1", "ADC MUX10"},
  396. {"ADC MUX1", "ANC_FB_TUNE1", "ADC MUX11"},
  397. {"ADC MUX1", "ANC_FB_TUNE2", "ADC MUX12"},
  398. {"ADC MUX1", "ANC_FB_TUNE2", "ADC MUX13"},
  399. {"ADC MUX2", "ANC_FB_TUNE1", "ADC MUX10"},
  400. {"ADC MUX2", "ANC_FB_TUNE1", "ADC MUX11"},
  401. {"ADC MUX2", "ANC_FB_TUNE2", "ADC MUX12"},
  402. {"ADC MUX2", "ANC_FB_TUNE2", "ADC MUX13"},
  403. {"ADC MUX3", "ANC_FB_TUNE1", "ADC MUX10"},
  404. {"ADC MUX3", "ANC_FB_TUNE1", "ADC MUX11"},
  405. {"ADC MUX3", "ANC_FB_TUNE2", "ADC MUX12"},
  406. {"ADC MUX3", "ANC_FB_TUNE2", "ADC MUX13"},
  407. {"ADC MUX4", "ANC_FB_TUNE1", "ADC MUX10"},
  408. {"ADC MUX4", "ANC_FB_TUNE1", "ADC MUX11"},
  409. {"ADC MUX4", "ANC_FB_TUNE2", "ADC MUX12"},
  410. {"ADC MUX4", "ANC_FB_TUNE2", "ADC MUX13"},
  411. {"ADC MUX5", "ANC_FB_TUNE1", "ADC MUX10"},
  412. {"ADC MUX5", "ANC_FB_TUNE1", "ADC MUX11"},
  413. {"ADC MUX5", "ANC_FB_TUNE2", "ADC MUX12"},
  414. {"ADC MUX5", "ANC_FB_TUNE2", "ADC MUX13"},
  415. {"ADC MUX6", "ANC_FB_TUNE1", "ADC MUX10"},
  416. {"ADC MUX6", "ANC_FB_TUNE1", "ADC MUX11"},
  417. {"ADC MUX6", "ANC_FB_TUNE2", "ADC MUX12"},
  418. {"ADC MUX6", "ANC_FB_TUNE2", "ADC MUX13"},
  419. {"ADC MUX7", "ANC_FB_TUNE1", "ADC MUX10"},
  420. {"ADC MUX7", "ANC_FB_TUNE1", "ADC MUX11"},
  421. {"ADC MUX7", "ANC_FB_TUNE2", "ADC MUX12"},
  422. {"ADC MUX7", "ANC_FB_TUNE2", "ADC MUX13"},
  423. {"ADC MUX8", "ANC_FB_TUNE1", "ADC MUX10"},
  424. {"ADC MUX8", "ANC_FB_TUNE1", "ADC MUX11"},
  425. {"ADC MUX8", "ANC_FB_TUNE2", "ADC MUX12"},
  426. {"ADC MUX8", "ANC_FB_TUNE2", "ADC MUX13"},
  427. {"DMIC MUX0", "DMIC0", "DMIC0"},
  428. {"DMIC MUX0", "DMIC1", "DMIC1"},
  429. {"DMIC MUX0", "DMIC2", "DMIC2"},
  430. {"DMIC MUX0", "DMIC3", "DMIC3"},
  431. {"DMIC MUX0", "DMIC4", "DMIC4"},
  432. {"DMIC MUX0", "DMIC5", "DMIC5"},
  433. {"AMIC MUX0", "ADC1", "ADC1"},
  434. {"AMIC MUX0", "ADC2", "ADC2"},
  435. {"AMIC MUX0", "ADC3", "ADC3"},
  436. {"AMIC MUX0", "ADC4", "ADC4"},
  437. {"DMIC MUX1", "DMIC0", "DMIC0"},
  438. {"DMIC MUX1", "DMIC1", "DMIC1"},
  439. {"DMIC MUX1", "DMIC2", "DMIC2"},
  440. {"DMIC MUX1", "DMIC3", "DMIC3"},
  441. {"DMIC MUX1", "DMIC4", "DMIC4"},
  442. {"DMIC MUX1", "DMIC5", "DMIC5"},
  443. {"AMIC MUX1", "ADC1", "ADC1"},
  444. {"AMIC MUX1", "ADC2", "ADC2"},
  445. {"AMIC MUX1", "ADC3", "ADC3"},
  446. {"AMIC MUX1", "ADC4", "ADC4"},
  447. {"DMIC MUX2", "DMIC0", "DMIC0"},
  448. {"DMIC MUX2", "DMIC1", "DMIC1"},
  449. {"DMIC MUX2", "DMIC2", "DMIC2"},
  450. {"DMIC MUX2", "DMIC3", "DMIC3"},
  451. {"DMIC MUX2", "DMIC4", "DMIC4"},
  452. {"DMIC MUX2", "DMIC5", "DMIC5"},
  453. {"AMIC MUX2", "ADC1", "ADC1"},
  454. {"AMIC MUX2", "ADC2", "ADC2"},
  455. {"AMIC MUX2", "ADC3", "ADC3"},
  456. {"AMIC MUX2", "ADC4", "ADC4"},
  457. {"DMIC MUX3", "DMIC0", "DMIC0"},
  458. {"DMIC MUX3", "DMIC1", "DMIC1"},
  459. {"DMIC MUX3", "DMIC2", "DMIC2"},
  460. {"DMIC MUX3", "DMIC3", "DMIC3"},
  461. {"DMIC MUX3", "DMIC4", "DMIC4"},
  462. {"DMIC MUX3", "DMIC5", "DMIC5"},
  463. {"AMIC MUX3", "ADC1", "ADC1"},
  464. {"AMIC MUX3", "ADC2", "ADC2"},
  465. {"AMIC MUX3", "ADC3", "ADC3"},
  466. {"AMIC MUX3", "ADC4", "ADC4"},
  467. {"DMIC MUX4", "DMIC0", "DMIC0"},
  468. {"DMIC MUX4", "DMIC1", "DMIC1"},
  469. {"DMIC MUX4", "DMIC2", "DMIC2"},
  470. {"DMIC MUX4", "DMIC3", "DMIC3"},
  471. {"DMIC MUX4", "DMIC4", "DMIC4"},
  472. {"DMIC MUX4", "DMIC5", "DMIC5"},
  473. {"AMIC MUX4", "ADC1", "ADC1"},
  474. {"AMIC MUX4", "ADC2", "ADC2"},
  475. {"AMIC MUX4", "ADC3", "ADC3"},
  476. {"AMIC MUX4", "ADC4", "ADC4"},
  477. {"DMIC MUX5", "DMIC0", "DMIC0"},
  478. {"DMIC MUX5", "DMIC1", "DMIC1"},
  479. {"DMIC MUX5", "DMIC2", "DMIC2"},
  480. {"DMIC MUX5", "DMIC3", "DMIC3"},
  481. {"DMIC MUX5", "DMIC4", "DMIC4"},
  482. {"DMIC MUX5", "DMIC5", "DMIC5"},
  483. {"AMIC MUX5", "ADC1", "ADC1"},
  484. {"AMIC MUX5", "ADC2", "ADC2"},
  485. {"AMIC MUX5", "ADC3", "ADC3"},
  486. {"AMIC MUX5", "ADC4", "ADC4"},
  487. {"DMIC MUX6", "DMIC0", "DMIC0"},
  488. {"DMIC MUX6", "DMIC1", "DMIC1"},
  489. {"DMIC MUX6", "DMIC2", "DMIC2"},
  490. {"DMIC MUX6", "DMIC3", "DMIC3"},
  491. {"DMIC MUX6", "DMIC4", "DMIC4"},
  492. {"DMIC MUX6", "DMIC5", "DMIC5"},
  493. {"AMIC MUX6", "ADC1", "ADC1"},
  494. {"AMIC MUX6", "ADC2", "ADC2"},
  495. {"AMIC MUX6", "ADC3", "ADC3"},
  496. {"AMIC MUX6", "ADC4", "ADC4"},
  497. {"DMIC MUX7", "DMIC0", "DMIC0"},
  498. {"DMIC MUX7", "DMIC1", "DMIC1"},
  499. {"DMIC MUX7", "DMIC2", "DMIC2"},
  500. {"DMIC MUX7", "DMIC3", "DMIC3"},
  501. {"DMIC MUX7", "DMIC4", "DMIC4"},
  502. {"DMIC MUX7", "DMIC5", "DMIC5"},
  503. {"AMIC MUX7", "ADC1", "ADC1"},
  504. {"AMIC MUX7", "ADC2", "ADC2"},
  505. {"AMIC MUX7", "ADC3", "ADC3"},
  506. {"AMIC MUX7", "ADC4", "ADC4"},
  507. {"DMIC MUX8", "DMIC0", "DMIC0"},
  508. {"DMIC MUX8", "DMIC1", "DMIC1"},
  509. {"DMIC MUX8", "DMIC2", "DMIC2"},
  510. {"DMIC MUX8", "DMIC3", "DMIC3"},
  511. {"DMIC MUX8", "DMIC4", "DMIC4"},
  512. {"DMIC MUX8", "DMIC5", "DMIC5"},
  513. {"AMIC MUX8", "ADC1", "ADC1"},
  514. {"AMIC MUX8", "ADC2", "ADC2"},
  515. {"AMIC MUX8", "ADC3", "ADC3"},
  516. {"AMIC MUX8", "ADC4", "ADC4"},
  517. {"DMIC MUX10", "DMIC0", "DMIC0"},
  518. {"DMIC MUX10", "DMIC1", "DMIC1"},
  519. {"DMIC MUX10", "DMIC2", "DMIC2"},
  520. {"DMIC MUX10", "DMIC3", "DMIC3"},
  521. {"DMIC MUX10", "DMIC4", "DMIC4"},
  522. {"DMIC MUX10", "DMIC5", "DMIC5"},
  523. {"AMIC MUX10", "ADC1", "ADC1"},
  524. {"AMIC MUX10", "ADC2", "ADC2"},
  525. {"AMIC MUX10", "ADC3", "ADC3"},
  526. {"AMIC MUX10", "ADC4", "ADC4"},
  527. {"DMIC MUX11", "DMIC0", "DMIC0"},
  528. {"DMIC MUX11", "DMIC1", "DMIC1"},
  529. {"DMIC MUX11", "DMIC2", "DMIC2"},
  530. {"DMIC MUX11", "DMIC3", "DMIC3"},
  531. {"DMIC MUX11", "DMIC4", "DMIC4"},
  532. {"DMIC MUX11", "DMIC5", "DMIC5"},
  533. {"AMIC MUX11", "ADC1", "ADC1"},
  534. {"AMIC MUX11", "ADC2", "ADC2"},
  535. {"AMIC MUX11", "ADC3", "ADC3"},
  536. {"AMIC MUX11", "ADC4", "ADC4"},
  537. {"DMIC MUX12", "DMIC0", "DMIC0"},
  538. {"DMIC MUX12", "DMIC1", "DMIC1"},
  539. {"DMIC MUX12", "DMIC2", "DMIC2"},
  540. {"DMIC MUX12", "DMIC3", "DMIC3"},
  541. {"DMIC MUX12", "DMIC4", "DMIC4"},
  542. {"DMIC MUX12", "DMIC5", "DMIC5"},
  543. {"AMIC MUX12", "ADC1", "ADC1"},
  544. {"AMIC MUX12", "ADC2", "ADC2"},
  545. {"AMIC MUX12", "ADC3", "ADC3"},
  546. {"AMIC MUX12", "ADC4", "ADC4"},
  547. {"DMIC MUX13", "DMIC0", "DMIC0"},
  548. {"DMIC MUX13", "DMIC1", "DMIC1"},
  549. {"DMIC MUX13", "DMIC2", "DMIC2"},
  550. {"DMIC MUX13", "DMIC3", "DMIC3"},
  551. {"DMIC MUX13", "DMIC4", "DMIC4"},
  552. {"DMIC MUX13", "DMIC5", "DMIC5"},
  553. {"AMIC MUX13", "ADC1", "ADC1"},
  554. {"AMIC MUX13", "ADC2", "ADC2"},
  555. {"AMIC MUX13", "ADC3", "ADC3"},
  556. {"AMIC MUX13", "ADC4", "ADC4"},
  557. {"AMIC4_5 SEL", "AMIC4", "AMIC4"},
  558. {"AMIC4_5 SEL", "AMIC5", "AMIC5"},
  559. {"ADC1", NULL, "AMIC1"},
  560. {"ADC2", NULL, "AMIC2"},
  561. {"ADC3", NULL, "AMIC3"},
  562. {"ADC4", NULL, "AMIC4_5 SEL"},
  563. {"RX INT0_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
  564. {"RX INT0_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
  565. {"RX INT0_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
  566. {"RX INT0_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
  567. {"RX INT0_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
  568. {"RX INT0_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
  569. {"RX INT0_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
  570. {"RX INT0_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
  571. {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
  572. {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"},
  573. {"RX INT0_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
  574. {"RX INT0_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
  575. {"RX INT0_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
  576. {"RX INT0_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
  577. {"RX INT0_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
  578. {"RX INT0_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
  579. {"RX INT0_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
  580. {"RX INT0_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
  581. {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
  582. {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"},
  583. {"RX INT0_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
  584. {"RX INT0_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
  585. {"RX INT0_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
  586. {"RX INT0_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
  587. {"RX INT0_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
  588. {"RX INT0_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
  589. {"RX INT0_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
  590. {"RX INT0_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
  591. {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
  592. {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"},
  593. {"RX INT1_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
  594. {"RX INT1_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
  595. {"RX INT1_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
  596. {"RX INT1_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
  597. {"RX INT1_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
  598. {"RX INT1_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
  599. {"RX INT1_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
  600. {"RX INT1_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
  601. {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
  602. {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"},
  603. {"RX INT1_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
  604. {"RX INT1_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
  605. {"RX INT1_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
  606. {"RX INT1_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
  607. {"RX INT1_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
  608. {"RX INT1_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
  609. {"RX INT1_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
  610. {"RX INT1_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
  611. {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
  612. {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"},
  613. {"RX INT1_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
  614. {"RX INT1_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
  615. {"RX INT1_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
  616. {"RX INT1_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
  617. {"RX INT1_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
  618. {"RX INT1_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
  619. {"RX INT1_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
  620. {"RX INT1_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
  621. {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
  622. {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"},
  623. {"RX INT2_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
  624. {"RX INT2_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
  625. {"RX INT2_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
  626. {"RX INT2_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
  627. {"RX INT2_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
  628. {"RX INT2_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
  629. {"RX INT2_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
  630. {"RX INT2_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
  631. {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
  632. {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"},
  633. {"RX INT2_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
  634. {"RX INT2_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
  635. {"RX INT2_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
  636. {"RX INT2_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
  637. {"RX INT2_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
  638. {"RX INT2_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
  639. {"RX INT2_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
  640. {"RX INT2_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
  641. {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
  642. {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"},
  643. {"RX INT2_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
  644. {"RX INT2_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
  645. {"RX INT2_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
  646. {"RX INT2_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
  647. {"RX INT2_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
  648. {"RX INT2_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
  649. {"RX INT2_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
  650. {"RX INT2_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
  651. {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
  652. {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"},
  653. {"RX INT3_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
  654. {"RX INT3_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
  655. {"RX INT3_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
  656. {"RX INT3_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
  657. {"RX INT3_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
  658. {"RX INT3_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
  659. {"RX INT3_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
  660. {"RX INT3_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
  661. {"RX INT3_1 MIX1 INP0", "IIR0", "IIR0"},
  662. {"RX INT3_1 MIX1 INP0", "IIR1", "IIR1"},
  663. {"RX INT3_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
  664. {"RX INT3_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
  665. {"RX INT3_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
  666. {"RX INT3_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
  667. {"RX INT3_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
  668. {"RX INT3_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
  669. {"RX INT3_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
  670. {"RX INT3_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
  671. {"RX INT3_1 MIX1 INP1", "IIR0", "IIR0"},
  672. {"RX INT3_1 MIX1 INP1", "IIR1", "IIR1"},
  673. {"RX INT3_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
  674. {"RX INT3_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
  675. {"RX INT3_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
  676. {"RX INT3_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
  677. {"RX INT3_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
  678. {"RX INT3_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
  679. {"RX INT3_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
  680. {"RX INT3_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
  681. {"RX INT3_1 MIX1 INP2", "IIR0", "IIR0"},
  682. {"RX INT3_1 MIX1 INP2", "IIR1", "IIR1"},
  683. {"RX INT4_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
  684. {"RX INT4_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
  685. {"RX INT4_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
  686. {"RX INT4_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
  687. {"RX INT4_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
  688. {"RX INT4_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
  689. {"RX INT4_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
  690. {"RX INT4_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
  691. {"RX INT4_1 MIX1 INP0", "IIR0", "IIR0"},
  692. {"RX INT4_1 MIX1 INP0", "IIR1", "IIR1"},
  693. {"RX INT4_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
  694. {"RX INT4_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
  695. {"RX INT4_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
  696. {"RX INT4_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
  697. {"RX INT4_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
  698. {"RX INT4_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
  699. {"RX INT4_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
  700. {"RX INT4_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
  701. {"RX INT4_1 MIX1 INP1", "IIR0", "IIR0"},
  702. {"RX INT4_1 MIX1 INP1", "IIR1", "IIR1"},
  703. {"RX INT4_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
  704. {"RX INT4_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
  705. {"RX INT4_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
  706. {"RX INT4_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
  707. {"RX INT4_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
  708. {"RX INT4_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
  709. {"RX INT4_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
  710. {"RX INT4_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
  711. {"RX INT4_1 MIX1 INP2", "IIR0", "IIR0"},
  712. {"RX INT4_1 MIX1 INP2", "IIR1", "IIR1"},
  713. {"RX INT7_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
  714. {"RX INT7_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
  715. {"RX INT7_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
  716. {"RX INT7_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
  717. {"RX INT7_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
  718. {"RX INT7_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
  719. {"RX INT7_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
  720. {"RX INT7_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
  721. {"RX INT7_1 MIX1 INP0", "IIR0", "IIR0"},
  722. {"RX INT7_1 MIX1 INP0", "IIR1", "IIR1"},
  723. {"RX INT7_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
  724. {"RX INT7_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
  725. {"RX INT7_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
  726. {"RX INT7_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
  727. {"RX INT7_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
  728. {"RX INT7_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
  729. {"RX INT7_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
  730. {"RX INT7_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
  731. {"RX INT7_1 MIX1 INP1", "IIR0", "IIR0"},
  732. {"RX INT7_1 MIX1 INP1", "IIR1", "IIR1"},
  733. {"RX INT7_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
  734. {"RX INT7_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
  735. {"RX INT7_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
  736. {"RX INT7_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
  737. {"RX INT7_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
  738. {"RX INT7_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
  739. {"RX INT7_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
  740. {"RX INT7_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
  741. {"RX INT7_1 MIX1 INP2", "IIR0", "IIR0"},
  742. {"RX INT7_1 MIX1 INP2", "IIR1", "IIR1"},
  743. {"RX INT8_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
  744. {"RX INT8_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
  745. {"RX INT8_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
  746. {"RX INT8_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
  747. {"RX INT8_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
  748. {"RX INT8_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
  749. {"RX INT8_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
  750. {"RX INT8_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
  751. {"RX INT8_1 MIX1 INP0", "IIR0", "IIR0"},
  752. {"RX INT8_1 MIX1 INP0", "IIR1", "IIR1"},
  753. {"RX INT8_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
  754. {"RX INT8_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
  755. {"RX INT8_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
  756. {"RX INT8_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
  757. {"RX INT8_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
  758. {"RX INT8_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
  759. {"RX INT8_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
  760. {"RX INT8_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
  761. {"RX INT8_1 MIX1 INP1", "IIR0", "IIR0"},
  762. {"RX INT8_1 MIX1 INP1", "IIR1", "IIR1"},
  763. {"RX INT8_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
  764. {"RX INT8_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
  765. {"RX INT8_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
  766. {"RX INT8_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
  767. {"RX INT8_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
  768. {"RX INT8_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
  769. {"RX INT8_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
  770. {"RX INT8_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
  771. {"RX INT8_1 MIX1 INP2", "IIR0", "IIR0"},
  772. {"RX INT8_1 MIX1 INP2", "IIR1", "IIR1"},
  773. {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
  774. {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
  775. {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
  776. {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"},
  777. {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"},
  778. {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"},
  779. {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"},
  780. {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"},
  781. {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"},
  782. {"RX INT3_1 MIX1", NULL, "RX INT3_1 MIX1 INP0"},
  783. {"RX INT3_1 MIX1", NULL, "RX INT3_1 MIX1 INP1"},
  784. {"RX INT3_1 MIX1", NULL, "RX INT3_1 MIX1 INP2"},
  785. {"RX INT4_1 MIX1", NULL, "RX INT4_1 MIX1 INP0"},
  786. {"RX INT4_1 MIX1", NULL, "RX INT4_1 MIX1 INP1"},
  787. {"RX INT4_1 MIX1", NULL, "RX INT4_1 MIX1 INP2"},
  788. {"RX INT7_1 MIX1", NULL, "RX INT7_1 MIX1 INP0"},
  789. {"RX INT7_1 MIX1", NULL, "RX INT7_1 MIX1 INP1"},
  790. {"RX INT7_1 MIX1", NULL, "RX INT7_1 MIX1 INP2"},
  791. {"RX INT8_1 MIX1", NULL, "RX INT8_1 MIX1 INP0"},
  792. {"RX INT8_1 MIX1", NULL, "RX INT8_1 MIX1 INP1"},
  793. {"RX INT8_1 MIX1", NULL, "RX INT8_1 MIX1 INP2"},
  794. /* Mixing path INT0 */
  795. {"RX INT0_2 MUX", "RX0", "CDC_IF RX0 MUX"},
  796. {"RX INT0_2 MUX", "RX1", "CDC_IF RX1 MUX"},
  797. {"RX INT0_2 MUX", "RX2", "CDC_IF RX2 MUX"},
  798. {"RX INT0_2 MUX", "RX3", "CDC_IF RX3 MUX"},
  799. {"RX INT0_2 MUX", "RX4", "CDC_IF RX4 MUX"},
  800. {"RX INT0_2 MUX", "RX5", "CDC_IF RX5 MUX"},
  801. {"RX INT0_2 MUX", "RX6", "CDC_IF RX6 MUX"},
  802. {"RX INT0_2 MUX", "RX7", "CDC_IF RX7 MUX"},
  803. {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
  804. {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
  805. /* Mixing path INT1 */
  806. {"RX INT1_2 MUX", "RX0", "CDC_IF RX0 MUX"},
  807. {"RX INT1_2 MUX", "RX1", "CDC_IF RX1 MUX"},
  808. {"RX INT1_2 MUX", "RX2", "CDC_IF RX2 MUX"},
  809. {"RX INT1_2 MUX", "RX3", "CDC_IF RX3 MUX"},
  810. {"RX INT1_2 MUX", "RX4", "CDC_IF RX4 MUX"},
  811. {"RX INT1_2 MUX", "RX5", "CDC_IF RX5 MUX"},
  812. {"RX INT1_2 MUX", "RX6", "CDC_IF RX6 MUX"},
  813. {"RX INT1_2 MUX", "RX7", "CDC_IF RX7 MUX"},
  814. {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"},
  815. {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"},
  816. /* Mixing path INT2 */
  817. {"RX INT2_2 MUX", "RX0", "CDC_IF RX0 MUX"},
  818. {"RX INT2_2 MUX", "RX1", "CDC_IF RX1 MUX"},
  819. {"RX INT2_2 MUX", "RX2", "CDC_IF RX2 MUX"},
  820. {"RX INT2_2 MUX", "RX3", "CDC_IF RX3 MUX"},
  821. {"RX INT2_2 MUX", "RX4", "CDC_IF RX4 MUX"},
  822. {"RX INT2_2 MUX", "RX5", "CDC_IF RX5 MUX"},
  823. {"RX INT2_2 MUX", "RX6", "CDC_IF RX6 MUX"},
  824. {"RX INT2_2 MUX", "RX7", "CDC_IF RX7 MUX"},
  825. {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"},
  826. {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"},
  827. /* Mixing path INT3 */
  828. {"RX INT3_2 MUX", "RX0", "CDC_IF RX0 MUX"},
  829. {"RX INT3_2 MUX", "RX1", "CDC_IF RX1 MUX"},
  830. {"RX INT3_2 MUX", "RX2", "CDC_IF RX2 MUX"},
  831. {"RX INT3_2 MUX", "RX3", "CDC_IF RX3 MUX"},
  832. {"RX INT3_2 MUX", "RX4", "CDC_IF RX4 MUX"},
  833. {"RX INT3_2 MUX", "RX5", "CDC_IF RX5 MUX"},
  834. {"RX INT3_2 MUX", "RX6", "CDC_IF RX6 MUX"},
  835. {"RX INT3_2 MUX", "RX7", "CDC_IF RX7 MUX"},
  836. {"RX INT3_2 INTERP", NULL, "RX INT3_2 MUX"},
  837. {"RX INT3 SEC MIX", NULL, "RX INT3_2 INTERP"},
  838. /* Mixing path INT4 */
  839. {"RX INT4_2 MUX", "RX0", "CDC_IF RX0 MUX"},
  840. {"RX INT4_2 MUX", "RX1", "CDC_IF RX1 MUX"},
  841. {"RX INT4_2 MUX", "RX2", "CDC_IF RX2 MUX"},
  842. {"RX INT4_2 MUX", "RX3", "CDC_IF RX3 MUX"},
  843. {"RX INT4_2 MUX", "RX4", "CDC_IF RX4 MUX"},
  844. {"RX INT4_2 MUX", "RX5", "CDC_IF RX5 MUX"},
  845. {"RX INT4_2 MUX", "RX6", "CDC_IF RX6 MUX"},
  846. {"RX INT4_2 MUX", "RX7", "CDC_IF RX7 MUX"},
  847. {"RX INT4_2 INTERP", NULL, "RX INT4_2 MUX"},
  848. {"RX INT4 SEC MIX", NULL, "RX INT4_2 INTERP"},
  849. /* Mixing path INT7 */
  850. {"RX INT7_2 MUX", "RX0", "CDC_IF RX0 MUX"},
  851. {"RX INT7_2 MUX", "RX1", "CDC_IF RX1 MUX"},
  852. {"RX INT7_2 MUX", "RX2", "CDC_IF RX2 MUX"},
  853. {"RX INT7_2 MUX", "RX3", "CDC_IF RX3 MUX"},
  854. {"RX INT7_2 MUX", "RX4", "CDC_IF RX4 MUX"},
  855. {"RX INT7_2 MUX", "RX5", "CDC_IF RX5 MUX"},
  856. {"RX INT7_2 MUX", "RX6", "CDC_IF RX6 MUX"},
  857. {"RX INT7_2 MUX", "RX7", "CDC_IF RX7 MUX"},
  858. {"RX INT7_2 INTERP", NULL, "RX INT7_2 MUX"},
  859. {"RX INT7 SEC MIX", NULL, "RX INT7_2 INTERP"},
  860. /* Mixing path INT8 */
  861. {"RX INT8_2 MUX", "RX0", "CDC_IF RX0 MUX"},
  862. {"RX INT8_2 MUX", "RX1", "CDC_IF RX1 MUX"},
  863. {"RX INT8_2 MUX", "RX2", "CDC_IF RX2 MUX"},
  864. {"RX INT8_2 MUX", "RX3", "CDC_IF RX3 MUX"},
  865. {"RX INT8_2 MUX", "RX4", "CDC_IF RX4 MUX"},
  866. {"RX INT8_2 MUX", "RX5", "CDC_IF RX5 MUX"},
  867. {"RX INT8_2 MUX", "RX6", "CDC_IF RX6 MUX"},
  868. {"RX INT8_2 MUX", "RX7", "CDC_IF RX7 MUX"},
  869. {"RX INT8_2 INTERP", NULL, "RX INT8_2 MUX"},
  870. {"RX INT8 SEC MIX", NULL, "RX INT8_2 INTERP"},
  871. {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
  872. {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
  873. {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
  874. {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
  875. {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
  876. {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
  877. {"RX INT0 DAC", NULL, "RX_BIAS"},
  878. {"EAR PA", NULL, "RX INT0 DAC"},
  879. {"EAR", NULL, "EAR PA"},
  880. {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"},
  881. {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"},
  882. {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"},
  883. {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"},
  884. {"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
  885. {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
  886. {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
  887. {"RX INT1 DAC", NULL, "RX_BIAS"},
  888. {"HPHL PA", NULL, "RX INT1 DAC"},
  889. {"HPHL", NULL, "HPHL PA"},
  890. {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"},
  891. {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"},
  892. {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"},
  893. {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"},
  894. {"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
  895. {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
  896. {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
  897. {"RX INT2 DAC", NULL, "RX_BIAS"},
  898. {"HPHR PA", NULL, "RX INT2 DAC"},
  899. {"HPHR", NULL, "HPHR PA"},
  900. {"RX INT3_1 INTERP", NULL, "RX INT3_1 MIX1"},
  901. {"RX INT3 SEC MIX", NULL, "RX INT3_1 INTERP"},
  902. {"RX INT3 MIX2", NULL, "RX INT3 SEC MIX"},
  903. {"RX INT3 MIX2", NULL, "RX INT3 MIX2 INP"},
  904. {"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
  905. {"RX INT3 DAC", NULL, "RX INT3 MIX3"},
  906. {"RX INT3 DAC", NULL, "RX_BIAS"},
  907. {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
  908. {"LINEOUT1", NULL, "LINEOUT1 PA"},
  909. {"RX INT4_1 INTERP", NULL, "RX INT4_1 MIX1"},
  910. {"RX INT4 SEC MIX", NULL, "RX INT4_1 INTERP"},
  911. {"RX INT4 SEC MIX", NULL, "RX INT4_1 MIX1"},
  912. {"RX INT4 MIX2", NULL, "RX INT4 SEC MIX"},
  913. {"RX INT4 MIX2", NULL, "RX INT4 MIX2 INP"},
  914. {"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
  915. {"RX INT4 DAC", NULL, "RX INT4 MIX3"},
  916. {"RX INT4 DAC", NULL, "RX_BIAS"},
  917. {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
  918. {"LINEOUT2", NULL, "LINEOUT2 PA"},
  919. {"RX INT7_1 INTERP", NULL, "RX INT7_1 MIX1"},
  920. {"RX INT7 SEC MIX", NULL, "RX INT7_1 INTERP"},
  921. {"RX INT7 MIX2", NULL, "RX INT7 SEC MIX"},
  922. {"RX INT7 MIX2", NULL, "RX INT7 MIX2 INP"},
  923. {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
  924. {"RX INT7 CHAIN", NULL, "RX_BIAS"},
  925. {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
  926. {"RX INT8_1 INTERP", NULL, "RX INT8_1 MIX1"},
  927. {"RX INT8 SEC MIX", NULL, "RX INT8_1 INTERP"},
  928. {"RX INT8 SEC MIX", NULL, "RX INT8_1 MIX1"},
  929. {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
  930. {"RX INT8 CHAIN", NULL, "RX_BIAS"},
  931. {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
  932. /* ANC Routing */
  933. {"ANC0 FB MUX", "ANC_IN_EAR", "RX INT0 MIX2"},
  934. {"ANC0 FB MUX", "ANC_IN_HPHL", "RX INT1 MIX2"},
  935. {"ANC0 FB MUX", "ANC_IN_LO1", "RX INT3 MIX2"},
  936. {"ANC0 FB MUX", "ANC_IN_EAR_SPKR", "RX INT7 MIX2"},
  937. {"ANC1 FB MUX", "ANC_IN_HPHR", "RX INT2 MIX2"},
  938. {"ANC1 FB MUX", "ANC_IN_LO2", "RX INT4 MIX2"},
  939. {"ANC OUT EAR Enable", "Switch", "ADC MUX10"},
  940. {"ANC OUT EAR Enable", "Switch", "ADC MUX11"},
  941. {"RX INT0 MIX2", NULL, "ANC OUT EAR Enable"},
  942. {"ANC OUT HPHL Enable", "Switch", "ADC MUX10"},
  943. {"ANC OUT HPHL Enable", "Switch", "ADC MUX11"},
  944. {"RX INT1 MIX2", NULL, "ANC OUT HPHL Enable"},
  945. {"ANC OUT HPHR Enable", "Switch", "ADC MUX12"},
  946. {"ANC OUT HPHR Enable", "Switch", "ADC MUX13"},
  947. {"RX INT2 MIX2", NULL, "ANC OUT HPHR Enable"},
  948. {"ANC EAR PA", NULL, "RX INT0 DAC"},
  949. {"ANC EAR", NULL, "ANC EAR PA"},
  950. {"ANC HPHL PA", NULL, "RX INT1 DAC"},
  951. {"ANC HPHL", NULL, "ANC HPHL PA"},
  952. {"ANC HPHR PA", NULL, "RX INT2 DAC"},
  953. {"ANC HPHR", NULL, "ANC HPHR PA"},
  954. {"ANC OUT EAR SPKR Enable", "Switch", "ADC MUX10"},
  955. {"ANC OUT EAR SPKR Enable", "Switch", "ADC MUX11"},
  956. {"RX INT7 MIX2", NULL, "ANC OUT EAR SPKR Enable"},
  957. {"ANC SPKR PA Enable", "Switch", "RX INT7 CHAIN"},
  958. {"ANC SPK1 PA", NULL, "ANC SPKR PA Enable"},
  959. {"SPK1 OUT", NULL, "ANC SPK1 PA"},
  960. /*
  961. * SRC0, SRC1 inputs to Sidetone RX Mixer
  962. * on RX0, RX1, RX2, RX3, RX4 and RX7 chains
  963. */
  964. {"IIR0", NULL, "IIR0 INP0 MUX"},
  965. {"IIR0 INP0 MUX", "DEC0", "ADC MUX0"},
  966. {"IIR0 INP0 MUX", "DEC1", "ADC MUX1"},
  967. {"IIR0 INP0 MUX", "DEC2", "ADC MUX2"},
  968. {"IIR0 INP0 MUX", "DEC3", "ADC MUX3"},
  969. {"IIR0 INP0 MUX", "DEC4", "ADC MUX4"},
  970. {"IIR0 INP0 MUX", "DEC5", "ADC MUX5"},
  971. {"IIR0 INP0 MUX", "DEC6", "ADC MUX6"},
  972. {"IIR0 INP0 MUX", "DEC7", "ADC MUX7"},
  973. {"IIR0 INP0 MUX", "DEC8", "ADC MUX8"},
  974. {"IIR0 INP0 MUX", "RX0", "CDC_IF RX0 MUX"},
  975. {"IIR0 INP0 MUX", "RX1", "CDC_IF RX1 MUX"},
  976. {"IIR0 INP0 MUX", "RX2", "CDC_IF RX2 MUX"},
  977. {"IIR0 INP0 MUX", "RX3", "CDC_IF RX3 MUX"},
  978. {"IIR0 INP0 MUX", "RX4", "CDC_IF RX4 MUX"},
  979. {"IIR0 INP0 MUX", "RX5", "CDC_IF RX5 MUX"},
  980. {"IIR0 INP0 MUX", "RX6", "CDC_IF RX6 MUX"},
  981. {"IIR0 INP0 MUX", "RX7", "CDC_IF RX7 MUX"},
  982. {"IIR0", NULL, "IIR0 INP1 MUX"},
  983. {"IIR0 INP1 MUX", "DEC0", "ADC MUX0"},
  984. {"IIR0 INP1 MUX", "DEC1", "ADC MUX1"},
  985. {"IIR0 INP1 MUX", "DEC2", "ADC MUX2"},
  986. {"IIR0 INP1 MUX", "DEC3", "ADC MUX3"},
  987. {"IIR0 INP1 MUX", "DEC4", "ADC MUX4"},
  988. {"IIR0 INP1 MUX", "DEC5", "ADC MUX5"},
  989. {"IIR0 INP1 MUX", "DEC6", "ADC MUX6"},
  990. {"IIR0 INP1 MUX", "DEC7", "ADC MUX7"},
  991. {"IIR0 INP1 MUX", "DEC8", "ADC MUX8"},
  992. {"IIR0 INP1 MUX", "RX0", "CDC_IF RX0 MUX"},
  993. {"IIR0 INP1 MUX", "RX1", "CDC_IF RX1 MUX"},
  994. {"IIR0 INP1 MUX", "RX2", "CDC_IF RX2 MUX"},
  995. {"IIR0 INP1 MUX", "RX3", "CDC_IF RX3 MUX"},
  996. {"IIR0 INP1 MUX", "RX4", "CDC_IF RX4 MUX"},
  997. {"IIR0 INP1 MUX", "RX5", "CDC_IF RX5 MUX"},
  998. {"IIR0 INP1 MUX", "RX6", "CDC_IF RX6 MUX"},
  999. {"IIR0 INP1 MUX", "RX7", "CDC_IF RX7 MUX"},
  1000. {"IIR0", NULL, "IIR0 INP2 MUX"},
  1001. {"IIR0 INP2 MUX", "DEC0", "ADC MUX0"},
  1002. {"IIR0 INP2 MUX", "DEC1", "ADC MUX1"},
  1003. {"IIR0 INP2 MUX", "DEC2", "ADC MUX2"},
  1004. {"IIR0 INP2 MUX", "DEC3", "ADC MUX3"},
  1005. {"IIR0 INP2 MUX", "DEC4", "ADC MUX4"},
  1006. {"IIR0 INP2 MUX", "DEC5", "ADC MUX5"},
  1007. {"IIR0 INP2 MUX", "DEC6", "ADC MUX6"},
  1008. {"IIR0 INP2 MUX", "DEC7", "ADC MUX7"},
  1009. {"IIR0 INP2 MUX", "DEC8", "ADC MUX8"},
  1010. {"IIR0 INP2 MUX", "RX0", "CDC_IF RX0 MUX"},
  1011. {"IIR0 INP2 MUX", "RX1", "CDC_IF RX1 MUX"},
  1012. {"IIR0 INP2 MUX", "RX2", "CDC_IF RX2 MUX"},
  1013. {"IIR0 INP2 MUX", "RX3", "CDC_IF RX3 MUX"},
  1014. {"IIR0 INP2 MUX", "RX4", "CDC_IF RX4 MUX"},
  1015. {"IIR0 INP2 MUX", "RX5", "CDC_IF RX5 MUX"},
  1016. {"IIR0 INP2 MUX", "RX6", "CDC_IF RX6 MUX"},
  1017. {"IIR0 INP2 MUX", "RX7", "CDC_IF RX7 MUX"},
  1018. {"IIR0", NULL, "IIR0 INP3 MUX"},
  1019. {"IIR0 INP3 MUX", "DEC0", "ADC MUX0"},
  1020. {"IIR0 INP3 MUX", "DEC1", "ADC MUX1"},
  1021. {"IIR0 INP3 MUX", "DEC2", "ADC MUX2"},
  1022. {"IIR0 INP3 MUX", "DEC3", "ADC MUX3"},
  1023. {"IIR0 INP3 MUX", "DEC4", "ADC MUX4"},
  1024. {"IIR0 INP3 MUX", "DEC5", "ADC MUX5"},
  1025. {"IIR0 INP3 MUX", "DEC6", "ADC MUX6"},
  1026. {"IIR0 INP3 MUX", "DEC7", "ADC MUX7"},
  1027. {"IIR0 INP3 MUX", "DEC8", "ADC MUX8"},
  1028. {"IIR0 INP3 MUX", "RX0", "CDC_IF RX0 MUX"},
  1029. {"IIR0 INP3 MUX", "RX1", "CDC_IF RX1 MUX"},
  1030. {"IIR0 INP3 MUX", "RX2", "CDC_IF RX2 MUX"},
  1031. {"IIR0 INP3 MUX", "RX3", "CDC_IF RX3 MUX"},
  1032. {"IIR0 INP3 MUX", "RX4", "CDC_IF RX4 MUX"},
  1033. {"IIR0 INP3 MUX", "RX5", "CDC_IF RX5 MUX"},
  1034. {"IIR0 INP3 MUX", "RX6", "CDC_IF RX6 MUX"},
  1035. {"IIR0 INP3 MUX", "RX7", "CDC_IF RX7 MUX"},
  1036. {"IIR1", NULL, "IIR1 INP0 MUX"},
  1037. {"IIR1 INP0 MUX", "DEC0", "ADC MUX0"},
  1038. {"IIR1 INP0 MUX", "DEC1", "ADC MUX1"},
  1039. {"IIR1 INP0 MUX", "DEC2", "ADC MUX2"},
  1040. {"IIR1 INP0 MUX", "DEC3", "ADC MUX3"},
  1041. {"IIR1 INP0 MUX", "DEC4", "ADC MUX4"},
  1042. {"IIR1 INP0 MUX", "DEC5", "ADC MUX5"},
  1043. {"IIR1 INP0 MUX", "DEC6", "ADC MUX6"},
  1044. {"IIR1 INP0 MUX", "DEC7", "ADC MUX7"},
  1045. {"IIR1 INP0 MUX", "DEC8", "ADC MUX8"},
  1046. {"IIR1 INP0 MUX", "RX0", "CDC_IF RX0 MUX"},
  1047. {"IIR1 INP0 MUX", "RX1", "CDC_IF RX1 MUX"},
  1048. {"IIR1 INP0 MUX", "RX2", "CDC_IF RX2 MUX"},
  1049. {"IIR1 INP0 MUX", "RX3", "CDC_IF RX3 MUX"},
  1050. {"IIR1 INP0 MUX", "RX4", "CDC_IF RX4 MUX"},
  1051. {"IIR1 INP0 MUX", "RX5", "CDC_IF RX5 MUX"},
  1052. {"IIR1 INP0 MUX", "RX6", "CDC_IF RX6 MUX"},
  1053. {"IIR1 INP0 MUX", "RX7", "CDC_IF RX7 MUX"},
  1054. {"IIR1", NULL, "IIR1 INP1 MUX"},
  1055. {"IIR1 INP1 MUX", "DEC0", "ADC MUX0"},
  1056. {"IIR1 INP1 MUX", "DEC1", "ADC MUX1"},
  1057. {"IIR1 INP1 MUX", "DEC2", "ADC MUX2"},
  1058. {"IIR1 INP1 MUX", "DEC3", "ADC MUX3"},
  1059. {"IIR1 INP1 MUX", "DEC4", "ADC MUX4"},
  1060. {"IIR1 INP1 MUX", "DEC5", "ADC MUX5"},
  1061. {"IIR1 INP1 MUX", "DEC6", "ADC MUX6"},
  1062. {"IIR1 INP1 MUX", "DEC7", "ADC MUX7"},
  1063. {"IIR1 INP1 MUX", "DEC8", "ADC MUX8"},
  1064. {"IIR1 INP1 MUX", "RX0", "CDC_IF RX0 MUX"},
  1065. {"IIR1 INP1 MUX", "RX1", "CDC_IF RX1 MUX"},
  1066. {"IIR1 INP1 MUX", "RX2", "CDC_IF RX2 MUX"},
  1067. {"IIR1 INP1 MUX", "RX3", "CDC_IF RX3 MUX"},
  1068. {"IIR1 INP1 MUX", "RX4", "CDC_IF RX4 MUX"},
  1069. {"IIR1 INP1 MUX", "RX5", "CDC_IF RX5 MUX"},
  1070. {"IIR1 INP1 MUX", "RX6", "CDC_IF RX6 MUX"},
  1071. {"IIR1 INP1 MUX", "RX7", "CDC_IF RX7 MUX"},
  1072. {"IIR1", NULL, "IIR1 INP2 MUX"},
  1073. {"IIR1 INP2 MUX", "DEC0", "ADC MUX0"},
  1074. {"IIR1 INP2 MUX", "DEC1", "ADC MUX1"},
  1075. {"IIR1 INP2 MUX", "DEC2", "ADC MUX2"},
  1076. {"IIR1 INP2 MUX", "DEC3", "ADC MUX3"},
  1077. {"IIR1 INP2 MUX", "DEC4", "ADC MUX4"},
  1078. {"IIR1 INP2 MUX", "DEC5", "ADC MUX5"},
  1079. {"IIR1 INP2 MUX", "DEC6", "ADC MUX6"},
  1080. {"IIR1 INP2 MUX", "DEC7", "ADC MUX7"},
  1081. {"IIR1 INP2 MUX", "DEC8", "ADC MUX8"},
  1082. {"IIR1 INP2 MUX", "RX0", "CDC_IF RX0 MUX"},
  1083. {"IIR1 INP2 MUX", "RX1", "CDC_IF RX1 MUX"},
  1084. {"IIR1 INP2 MUX", "RX2", "CDC_IF RX2 MUX"},
  1085. {"IIR1 INP2 MUX", "RX3", "CDC_IF RX3 MUX"},
  1086. {"IIR1 INP2 MUX", "RX4", "CDC_IF RX4 MUX"},
  1087. {"IIR1 INP2 MUX", "RX5", "CDC_IF RX5 MUX"},
  1088. {"IIR1 INP2 MUX", "RX6", "CDC_IF RX6 MUX"},
  1089. {"IIR1 INP2 MUX", "RX7", "CDC_IF RX7 MUX"},
  1090. {"IIR1", NULL, "IIR1 INP3 MUX"},
  1091. {"IIR1 INP3 MUX", "DEC0", "ADC MUX0"},
  1092. {"IIR1 INP3 MUX", "DEC1", "ADC MUX1"},
  1093. {"IIR1 INP3 MUX", "DEC2", "ADC MUX2"},
  1094. {"IIR1 INP3 MUX", "DEC3", "ADC MUX3"},
  1095. {"IIR1 INP3 MUX", "DEC4", "ADC MUX4"},
  1096. {"IIR1 INP3 MUX", "DEC5", "ADC MUX5"},
  1097. {"IIR1 INP3 MUX", "DEC6", "ADC MUX6"},
  1098. {"IIR1 INP3 MUX", "DEC7", "ADC MUX7"},
  1099. {"IIR1 INP3 MUX", "DEC8", "ADC MUX8"},
  1100. {"IIR1 INP3 MUX", "RX0", "CDC_IF RX0 MUX"},
  1101. {"IIR1 INP3 MUX", "RX1", "CDC_IF RX1 MUX"},
  1102. {"IIR1 INP3 MUX", "RX2", "CDC_IF RX2 MUX"},
  1103. {"IIR1 INP3 MUX", "RX3", "CDC_IF RX3 MUX"},
  1104. {"IIR1 INP3 MUX", "RX4", "CDC_IF RX4 MUX"},
  1105. {"IIR1 INP3 MUX", "RX5", "CDC_IF RX5 MUX"},
  1106. {"IIR1 INP3 MUX", "RX6", "CDC_IF RX6 MUX"},
  1107. {"IIR1 INP3 MUX", "RX7", "CDC_IF RX7 MUX"},
  1108. {"SRC0", NULL, "IIR0"},
  1109. {"SRC1", NULL, "IIR1"},
  1110. {"RX INT0 MIX2 INP", "SRC0", "SRC0"},
  1111. {"RX INT0 MIX2 INP", "SRC1", "SRC1"},
  1112. {"RX INT1 MIX2 INP", "SRC0", "SRC0"},
  1113. {"RX INT1 MIX2 INP", "SRC1", "SRC1"},
  1114. {"RX INT2 MIX2 INP", "SRC0", "SRC0"},
  1115. {"RX INT2 MIX2 INP", "SRC1", "SRC1"},
  1116. {"RX INT3 MIX2 INP", "SRC0", "SRC0"},
  1117. {"RX INT3 MIX2 INP", "SRC1", "SRC1"},
  1118. {"RX INT4 MIX2 INP", "SRC0", "SRC0"},
  1119. {"RX INT4 MIX2 INP", "SRC1", "SRC1"},
  1120. {"RX INT7 MIX2 INP", "SRC0", "SRC0"},
  1121. {"RX INT7 MIX2 INP", "SRC1", "SRC1"},
  1122. /* Native clk main path routing */
  1123. {"RX INT1_1 NATIVE MUX", "ON", "RX INT1_1 MIX1"},
  1124. {"RX INT1_1 INTERP", NULL, "RX INT1_1 NATIVE MUX"},
  1125. {"RX INT1_1 NATIVE MUX", NULL, "RX INT1 NATIVE SUPPLY"},
  1126. {"RX INT2_1 NATIVE MUX", "ON", "RX INT2_1 MIX1"},
  1127. {"RX INT2_1 INTERP", NULL, "RX INT2_1 NATIVE MUX"},
  1128. {"RX INT2_1 NATIVE MUX", NULL, "RX INT2 NATIVE SUPPLY"},
  1129. {"RX INT3_1 NATIVE MUX", "ON", "RX INT3_1 MIX1"},
  1130. {"RX INT3_1 INTERP", NULL, "RX INT3_1 NATIVE MUX"},
  1131. {"RX INT3_1 NATIVE MUX", NULL, "RX INT3 NATIVE SUPPLY"},
  1132. {"RX INT4_1 NATIVE MUX", "ON", "RX INT4_1 MIX1"},
  1133. {"RX INT4_1 INTERP", NULL, "RX INT4_1 NATIVE MUX"},
  1134. {"RX INT4_1 NATIVE MUX", NULL, "RX INT4 NATIVE SUPPLY"},
  1135. /* Native clk mix path routing */
  1136. {"RX INT1_2 NATIVE MUX", "ON", "RX INT1_2 MUX"},
  1137. {"RX INT1_2 INTERP", NULL, "RX INT1_2 NATIVE MUX"},
  1138. {"RX INT1_2 NATIVE MUX", NULL, "RX INT1 NATIVE SUPPLY"},
  1139. {"RX INT2_2 NATIVE MUX", "ON", "RX INT2_2 MUX"},
  1140. {"RX INT2_2 INTERP", NULL, "RX INT2_2 NATIVE MUX"},
  1141. {"RX INT2_2 NATIVE MUX", NULL, "RX INT2 NATIVE SUPPLY"},
  1142. {"RX INT3_2 NATIVE MUX", "ON", "RX INT3_2 MUX"},
  1143. {"RX INT3_2 INTERP", NULL, "RX INT3_2 NATIVE MUX"},
  1144. {"RX INT3_2 NATIVE MUX", NULL, "RX INT3 NATIVE SUPPLY"},
  1145. {"RX INT4_2 NATIVE MUX", "ON", "RX INT4_2 MUX"},
  1146. {"RX INT4_2 INTERP", NULL, "RX INT4_2 NATIVE MUX"},
  1147. {"RX INT4_2 NATIVE MUX", NULL, "RX INT4 NATIVE SUPPLY"},
  1148. {"RX INT7_2 NATIVE MUX", "ON", "RX INT7_2 MUX"},
  1149. {"RX INT7_2 INTERP", NULL, "RX INT7_2 NATIVE MUX"},
  1150. {"RX INT7_2 NATIVE MUX", NULL, "RX INT7 NATIVE SUPPLY"},
  1151. {"RX INT8_2 NATIVE MUX", "ON", "RX INT8_2 MUX"},
  1152. {"RX INT8_2 INTERP", NULL, "RX INT8_2 NATIVE MUX"},
  1153. {"RX INT8_2 NATIVE MUX", NULL, "RX INT8 NATIVE SUPPLY"},
  1154. /* ASRC Routing */
  1155. {"ASRC0 MUX", "ASRC_IN_HPHL", "RX INT1_2 INTERP"},
  1156. {"RX INT1 SEC MIX", "HPHL Switch", "ASRC0 MUX"},
  1157. {"ASRC1 MUX", "ASRC_IN_HPHR", "RX INT2_2 INTERP"},
  1158. {"RX INT2 SEC MIX", "HPHR Switch", "ASRC1 MUX"},
  1159. {"ASRC0 MUX", "ASRC_IN_LO1", "RX INT3_2 INTERP"},
  1160. {"RX INT3 SEC MIX", "LO1 Switch", "ASRC0 MUX"},
  1161. {"ASRC1 MUX", "ASRC_IN_LO2", "RX INT4_2 INTERP"},
  1162. {"RX INT4 SEC MIX", "LO2 Switch", "ASRC1 MUX"},
  1163. {"ASRC2 MUX", "ASRC_IN_SPKR1", "RX INT7_2 INTERP"},
  1164. {"RX INT7 SEC MIX", NULL, "ASRC2 MUX"},
  1165. {"ASRC3 MUX", "ASRC_IN_SPKR2", "RX INT8_2 INTERP"},
  1166. {"RX INT8 SEC MIX", NULL, "ASRC3 MUX"},
  1167. };
  1168. #endif