aqt1000-routing.h 5.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  3. */
  4. #ifndef AQT1000_ROUTING_H
  5. #define AQT1000_ROUTING_H
  6. #include <sound/soc-dapm.h>
  7. const struct snd_soc_dapm_route aqt_audio_map[] = {
  8. /* CDC Tx interface */
  9. {"AQT AIF1 CAP", NULL, "AQT AIF1 CAP Mixer"},
  10. {"AQT AIF1 CAP Mixer", "TX0", "AQT TX0_MUX"},
  11. {"AQT AIF1 CAP Mixer", "TX1", "AQT TX1_MUX"},
  12. {"AQT TX0_MUX", "DEC_L", "AQT ADC0 MUX"},
  13. {"AQT TX0_MUX", "DEC_R", "AQT ADC1 MUX"},
  14. {"AQT TX0_MUX", "DEC_V", "AQT ADC2 MUX"},
  15. {"AQT TX1_MUX", "DEC_L", "AQT ADC0 MUX"},
  16. {"AQT TX1_MUX", "DEC_R", "AQT ADC1 MUX"},
  17. {"AQT TX1_MUX", "DEC_V", "AQT ADC2 MUX"},
  18. {"AQT ADC0 MUX", "AMIC", "AQT AMIC0_MUX"},
  19. {"AQT ADC0 MUX", "ANC_FB0", "AQT ANC_FB_TUNE0"},
  20. {"AQT ADC0 MUX", "ANC_FB1", "AQT ANC_FB_TUNE1"},
  21. {"AQT ADC1 MUX", "AMIC", "AQT AMIC1_MUX"},
  22. {"AQT ADC1 MUX", "ANC_FB0", "AQT ANC_FB_TUNE0"},
  23. {"AQT ADC1 MUX", "ANC_FB1", "AQT ANC_FB_TUNE1"},
  24. {"AQT ADC2 MUX", "AMIC", "AQT AMIC2_MUX"},
  25. {"AQT ADC2 MUX", "ANC_FB0", "AQT ANC_FB_TUNE0"},
  26. {"AQT ADC2 MUX", "ANC_FB1", "AQT ANC_FB_TUNE1"},
  27. {"AQT AMIC0_MUX", "ADC_L", "AQT ADC_L"},
  28. {"AQT AMIC0_MUX", "ADC_R", "AQT ADC_R"},
  29. {"AQT AMIC0_MUX", "ADC_V", "AQT ADC_V"},
  30. {"AQT AMIC1_MUX", "ADC_L", "AQT ADC_L"},
  31. {"AQT AMIC1_MUX", "ADC_R", "AQT ADC_R"},
  32. {"AQT AMIC1_MUX", "ADC_V", "AQT ADC_V"},
  33. {"AQT AMIC2_MUX", "ADC_L", "AQT ADC_L"},
  34. {"AQT AMIC2_MUX", "ADC_R", "AQT ADC_R"},
  35. {"AQT AMIC2_MUX", "ADC_V", "AQT ADC_V"},
  36. {"AQT ADC_L", NULL, "AQT AMIC1"},
  37. {"AQT ADC_R", NULL, "AQT AMIC2"},
  38. {"AQT ADC_V", NULL, "AQT AMIC3"},
  39. {"AQT AMIC10_MUX", "ADC_L", "AQT ADC_L"},
  40. {"AQT AMIC10_MUX", "ADC_R", "AQT ADC_R"},
  41. {"AQT AMIC10_MUX", "ADC_V", "AQT ADC_V"},
  42. {"AQT AMIC11_MUX", "ADC_L", "AQT ADC_L"},
  43. {"AQT AMIC11_MUX", "ADC_R", "AQT ADC_R"},
  44. {"AQT AMIC11_MUX", "ADC_V", "AQT ADC_V"},
  45. {"AQT AMIC12_MUX", "ADC_L", "AQT ADC_L"},
  46. {"AQT AMIC12_MUX", "ADC_R", "AQT ADC_R"},
  47. {"AQT AMIC12_MUX", "ADC_V", "AQT ADC_V"},
  48. {"AQT AMIC13_MUX", "ADC_L", "AQT ADC_L"},
  49. {"AQT AMIC13_MUX", "ADC_R", "AQT ADC_R"},
  50. {"AQT AMIC13_MUX", "ADC_V", "AQT ADC_V"},
  51. {"AQT ANC OUT HPHL Enable", "Switch", "AQT AMIC10_MUX"},
  52. {"AQT ANC OUT HPHL Enable", "Switch", "AQT AMIC11_MUX"},
  53. {"AQT ANC OUT HPHR Enable", "Switch", "AQT AMIC12_MUX"},
  54. {"AQT ANC OUT HPHR Enable", "Switch", "AQT AMIC13_MUX"},
  55. {"AQT RX INT1 MIX2", NULL, "AQT ANC OUT HPHL Enable"},
  56. {"AQT RX INT2 MIX2", NULL, "AQT ANC OUT HPHR Enable"},
  57. {"AQT ANC0 FB MUX", "ANC_IN_HPHL", "AQT RX INT1 MIX2"},
  58. {"AQT ANC1 FB MUX", "ANC_IN_HPHR", "AQT RX INT2 MIX2"},
  59. {"AQT I2S_L RX", NULL, "AQT AIF1 PB"},
  60. {"AQT I2S_R RX", NULL, "AQT AIF1 PB"},
  61. {"AQT RX INT1_1 MUX", "I2S0_L", "AQT I2S_L RX"},
  62. {"AQT RX INT1_1 MUX", "I2S0_R", "AQT I2S_R RX"},
  63. {"AQT RX INT1_1 MUX", "DEC_L", "AQT ADC0 MUX"},
  64. {"AQT RX INT1_1 MUX", "DEC_R", "AQT ADC1 MUX"},
  65. {"AQT RX INT1_1 MUX", "DEC_V", "AQT ADC2 MUX"},
  66. {"AQT RX INT2_1 MUX", "I2S0_L", "AQT I2S_L RX"},
  67. {"AQT RX INT2_1 MUX", "I2S0_R", "AQT I2S_R RX"},
  68. {"AQT RX INT2_1 MUX", "DEC_L", "AQT ADC0 MUX"},
  69. {"AQT RX INT2_1 MUX", "DEC_R", "AQT ADC1 MUX"},
  70. {"AQT RX INT2_1 MUX", "DEC_V", "AQT ADC2 MUX"},
  71. {"AQT RX INT1_2 MUX", "I2S0_L", "AQT I2S_L RX"},
  72. {"AQT RX INT1_2 MUX", "I2S0_R", "AQT I2S_R RX"},
  73. {"AQT RX INT1_2 MUX", "DEC_L", "AQT ADC0 MUX"},
  74. {"AQT RX INT1_2 MUX", "DEC_R", "AQT ADC1 MUX"},
  75. {"AQT RX INT1_2 MUX", "DEC_V", "AQT ADC2 MUX"},
  76. {"AQT RX INT1_2 MUX", "IIR0", "AQT IIR0"},
  77. {"AQT RX INT2_2 MUX", "I2S0_L", "AQT I2S_L RX"},
  78. {"AQT RX INT2_2 MUX", "I2S0_R", "AQT I2S_R RX"},
  79. {"AQT RX INT2_2 MUX", "DEC_L", "AQT ADC0 MUX"},
  80. {"AQT RX INT2_2 MUX", "DEC_R", "AQT ADC1 MUX"},
  81. {"AQT RX INT2_2 MUX", "DEC_V", "AQT ADC2 MUX"},
  82. {"AQT RX INT2_2 MUX", "IIR0", "AQT IIR0"},
  83. {"AQT RX INT1_1 INTERP", NULL, "AQT RX INT1_1 MUX"},
  84. {"AQT RX INT1 MIX1", NULL, "AQT RX INT1_1 INTERP"},
  85. {"AQT RX INT1 MIX2", NULL, "AQT RX INT1 MIX1"},
  86. {"AQT RX INT1_2 INTERP", NULL, "AQT RX INT1_2 MUX"},
  87. {"AQT RX INT1 MIX1", NULL, "AQT RX INT1_2 INTERP"},
  88. {"AQT ASRC0 MUX", "ASRC_IN_HPHL", "AQT RX INT1_2 INTERP"},
  89. {"AQT RX INT1 MIX1", "HPHL Switch", "AQT ASRC0 MUX"},
  90. {"AQT RX INT2_1 INTERP", NULL, "AQT RX INT2_1 MUX"},
  91. {"AQT RX INT2 MIX1", NULL, "AQT RX INT2_1 INTERP"},
  92. {"AQT RX INT2 MIX2", NULL, "AQT RX INT2 MIX1"},
  93. {"AQT RX INT2_2 INTERP", NULL, "AQT RX INT2_2 MUX"},
  94. {"AQT RX INT2 MIX1", NULL, "AQT RX INT2_2 INTERP"},
  95. {"AQT ASRC1 MUX", "ASRC_IN_HPHR", "AQT RX INT2_2 INTERP"},
  96. {"AQT RX INT2 MIX1", "HPHR Switch", "AQT ASRC1 MUX"},
  97. {"AQT RX INT1 DEM MUX", "CLSH_DSM_OUT", "AQT RX INT1 MIX2"},
  98. {"AQT RX INT1 DAC", NULL, "AQT RX INT1 DEM MUX"},
  99. {"AQT RX INT1 DAC", NULL, "AQT RX_BIAS"},
  100. {"AQT RX_BIAS", NULL, "AQT MCLK"},
  101. {"AQT MIC BIAS1", NULL, "AQT MCLK"},
  102. {"AQT HPHL PA", NULL, "AQT RX INT1 DAC"},
  103. {"AQT HPHL", NULL, "AQT HPHL PA"},
  104. {"AQT RX INT2 DEM MUX", "CLSH_DSM_OUT", "AQT RX INT2 MIX2"},
  105. {"AQT RX INT2 DAC", NULL, "AQT RX INT2 DEM MUX"},
  106. {"AQT RX INT2 DAC", NULL, "AQT RX_BIAS"},
  107. {"AQT HPHR PA", NULL, "AQT RX INT2 DAC"},
  108. {"AQT HPHR", NULL, "AQT HPHR PA"},
  109. {"AQT ANC HPHL PA", NULL, "AQT RX INT1 DAC"},
  110. {"AQT ANC HPHL", NULL, "AQT ANC HPHL PA"},
  111. {"AQT ANC HPHR PA", NULL, "AQT RX INT2 DAC"},
  112. {"AQT ANC HPHR", NULL, "AQT ANC HPHR PA"},
  113. {"AQT IIR0", NULL, "AQT ADC2 MUX"},
  114. {"AQT SRC0", NULL, "AQT IIR0"},
  115. {"AQT RX ST MUX", "SRC0", "AQT SRC0"},
  116. {"AQT RX INT1 MIX2", NULL, "AQT RX ST MUX"},
  117. {"AQT RX INT2 MIX2", NULL, "AQT RX ST MUX"},
  118. /* Native clk main path routing */
  119. {"AQT RX INT1_1 NATIVE MUX", "ON", "AQT RX INT1_1 MUX"},
  120. {"AQT RX INT1_1 INTERP", NULL, "AQT RX INT1_1 NATIVE MUX"},
  121. {"AQT RX INT1_1 NATIVE MUX", NULL, "AQT RX INT1 NATIVE SUPPLY"},
  122. {"AQT RX INT2_1 NATIVE MUX", "ON", "AQT RX INT2_1 MUX"},
  123. {"AQT RX INT2_1 INTERP", NULL, "AQT RX INT2_1 NATIVE MUX"},
  124. {"AQT RX INT2_1 NATIVE MUX", NULL, "AQT RX INT2 NATIVE SUPPLY"},
  125. };
  126. #endif