qcs405.c 205 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/input.h>
  21. #include <linux/of_device.h>
  22. #include <linux/pm_qos.h>
  23. #include <sound/core.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/info.h>
  29. #include <dsp/audio_notifier.h>
  30. #include <dsp/q6afe-v2.h>
  31. #include <dsp/q6core.h>
  32. #include "device_event.h"
  33. #include "msm-pcm-routing-v2.h"
  34. #include "codecs/msm-cdc-pinctrl.h"
  35. #include "codecs/wcd9335.h"
  36. #include "codecs/wsa881x.h"
  37. #define DRV_NAME "qcs405-asoc-snd"
  38. #define __CHIPSET__ "QCS405 "
  39. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  40. #define DEV_NAME_STR_LEN 32
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define WSA8810_NAME_1 "wsa881x.20170211"
  55. #define WSA8810_NAME_2 "wsa881x.20170212"
  56. #define WCN_CDC_SLIM_RX_CH_MAX 2
  57. #define WCN_CDC_SLIM_TX_CH_MAX 3
  58. #define TDM_CHANNEL_MAX 8
  59. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  60. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  61. enum {
  62. SLIM_RX_0 = 0,
  63. SLIM_RX_1,
  64. SLIM_RX_2,
  65. SLIM_RX_3,
  66. SLIM_RX_4,
  67. SLIM_RX_5,
  68. SLIM_RX_6,
  69. SLIM_RX_7,
  70. SLIM_RX_MAX,
  71. };
  72. enum {
  73. SLIM_TX_0 = 0,
  74. SLIM_TX_1,
  75. SLIM_TX_2,
  76. SLIM_TX_3,
  77. SLIM_TX_4,
  78. SLIM_TX_5,
  79. SLIM_TX_6,
  80. SLIM_TX_7,
  81. SLIM_TX_8,
  82. SLIM_TX_MAX,
  83. };
  84. enum {
  85. PRIM_MI2S = 0,
  86. SEC_MI2S,
  87. TERT_MI2S,
  88. QUAT_MI2S,
  89. QUIN_MI2S,
  90. MI2S_MAX,
  91. };
  92. enum {
  93. PRIM_AUX_PCM = 0,
  94. SEC_AUX_PCM,
  95. TERT_AUX_PCM,
  96. QUAT_AUX_PCM,
  97. QUIN_AUX_PCM,
  98. AUX_PCM_MAX,
  99. };
  100. enum {
  101. WSA_CDC_DMA_RX_0 = 0,
  102. WSA_CDC_DMA_RX_1,
  103. CDC_DMA_RX_MAX,
  104. };
  105. enum {
  106. WSA_CDC_DMA_TX_0 = 0,
  107. WSA_CDC_DMA_TX_1,
  108. WSA_CDC_DMA_TX_2,
  109. VA_CDC_DMA_TX_0,
  110. VA_CDC_DMA_TX_1,
  111. CDC_DMA_TX_MAX,
  112. };
  113. struct mi2s_conf {
  114. struct mutex lock;
  115. u32 ref_cnt;
  116. u32 msm_is_mi2s_master;
  117. };
  118. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  119. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  120. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  121. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  122. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  123. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  124. };
  125. struct dev_config {
  126. u32 sample_rate;
  127. u32 bit_format;
  128. u32 channels;
  129. };
  130. struct msm_wsa881x_dev_info {
  131. struct device_node *of_node;
  132. u32 index;
  133. };
  134. enum pinctrl_pin_state {
  135. STATE_DISABLE = 0, /* All pins are in sleep state */
  136. STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
  137. STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
  138. };
  139. struct msm_pinctrl_info {
  140. struct pinctrl *pinctrl;
  141. struct pinctrl_state *mi2s_disable;
  142. struct pinctrl_state *tdm_disable;
  143. struct pinctrl_state *mi2s_active;
  144. struct pinctrl_state *tdm_active;
  145. enum pinctrl_pin_state curr_state;
  146. };
  147. struct msm_asoc_mach_data {
  148. struct snd_info_entry *codec_root;
  149. struct msm_pinctrl_info pinctrl_info;
  150. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  151. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  152. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  153. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  154. int dmic_01_gpio_cnt;
  155. int dmic_23_gpio_cnt;
  156. int dmic_45_gpio_cnt;
  157. int dmic_67_gpio_cnt;
  158. };
  159. struct msm_asoc_wcd93xx_codec {
  160. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  161. enum afe_config_type config_type);
  162. };
  163. static const char *const pin_states[] = {"sleep", "i2s-active",
  164. "tdm-active"};
  165. enum {
  166. TDM_0 = 0,
  167. TDM_1,
  168. TDM_2,
  169. TDM_3,
  170. TDM_4,
  171. TDM_5,
  172. TDM_6,
  173. TDM_7,
  174. TDM_PORT_MAX,
  175. };
  176. enum {
  177. TDM_PRI = 0,
  178. TDM_SEC,
  179. TDM_TERT,
  180. TDM_QUAT,
  181. TDM_QUIN,
  182. TDM_INTERFACE_MAX,
  183. };
  184. struct tdm_port {
  185. u32 mode;
  186. u32 channel;
  187. };
  188. /* TDM default config */
  189. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  190. { /* PRI TDM */
  191. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  192. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  193. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  194. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  195. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  196. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  197. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  198. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  199. },
  200. { /* SEC TDM */
  201. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  202. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  203. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  205. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  206. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  209. },
  210. { /* TERT TDM */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  212. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  219. },
  220. { /* QUAT TDM */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  229. },
  230. { /* QUIN TDM */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  239. }
  240. };
  241. /* TDM default config */
  242. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  243. { /* PRI TDM */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  252. },
  253. { /* SEC TDM */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  262. },
  263. { /* TERT TDM */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  272. },
  273. { /* QUAT TDM */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  282. },
  283. { /* QUIN TDM */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  292. }
  293. };
  294. /* Default configuration of slimbus channels */
  295. static struct dev_config slim_rx_cfg[] = {
  296. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  297. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  298. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  299. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  300. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  301. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  302. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  303. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  304. };
  305. static struct dev_config slim_tx_cfg[] = {
  306. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  307. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  308. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  309. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  311. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  315. };
  316. /* Default configuration of Codec DMA Interface Tx */
  317. static struct dev_config cdc_dma_rx_cfg[] = {
  318. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  319. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  320. };
  321. /* Default configuration of Codec DMA Interface Rx */
  322. static struct dev_config cdc_dma_tx_cfg[] = {
  323. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  324. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  325. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  326. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  327. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  328. };
  329. static struct dev_config usb_rx_cfg = {
  330. .sample_rate = SAMPLING_RATE_48KHZ,
  331. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  332. .channels = 2,
  333. };
  334. static struct dev_config usb_tx_cfg = {
  335. .sample_rate = SAMPLING_RATE_48KHZ,
  336. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  337. .channels = 1,
  338. };
  339. static struct dev_config proxy_rx_cfg = {
  340. .sample_rate = SAMPLING_RATE_48KHZ,
  341. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  342. .channels = 2,
  343. };
  344. /* Default configuration of MI2S channels */
  345. static struct dev_config mi2s_rx_cfg[] = {
  346. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  347. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  349. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  350. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  351. };
  352. static struct dev_config mi2s_tx_cfg[] = {
  353. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  354. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  355. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  356. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  357. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  358. };
  359. static struct dev_config aux_pcm_rx_cfg[] = {
  360. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  361. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  362. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  363. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  364. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  365. };
  366. static struct dev_config aux_pcm_tx_cfg[] = {
  367. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  368. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  369. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  370. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  371. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  372. };
  373. static int msm_vi_feed_tx_ch = 2;
  374. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  375. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  376. "Five", "Six", "Seven",
  377. "Eight"};
  378. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  379. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  380. "S32_LE"};
  381. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  382. "KHZ_32", "KHZ_44P1", "KHZ_48",
  383. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  384. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  385. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  386. "KHZ_44P1", "KHZ_48",
  387. "KHZ_88P2", "KHZ_96"};
  388. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  389. "Five", "Six", "Seven",
  390. "Eight"};
  391. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  392. "Six", "Seven", "Eight"};
  393. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  394. "KHZ_16", "KHZ_22P05",
  395. "KHZ_32", "KHZ_44P1", "KHZ_48",
  396. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  397. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  398. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  399. "Five", "Six", "Seven", "Eight"};
  400. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  401. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  402. "KHZ_48", "KHZ_176P4",
  403. "KHZ_352P8"};
  404. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  405. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  406. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  407. "KHZ_48", "KHZ_96", "KHZ_192"};
  408. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  409. "Five", "Six", "Seven",
  410. "Eight"};
  411. static const char *const qos_text[] = {"Disable", "Enable"};
  412. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  413. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  414. "Five", "Six", "Seven",
  415. "Eight"};
  416. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  417. "KHZ_32", "KHZ_44P1", "KHZ_48",
  418. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  419. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  420. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  421. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  422. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  423. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  424. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  425. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  426. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  427. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  428. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  429. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  430. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  431. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  432. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  433. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  434. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  435. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  436. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  437. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  438. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  439. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  440. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  441. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  442. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  443. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  444. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  445. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  446. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  447. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  448. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  449. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  498. cdc_dma_sample_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  500. cdc_dma_sample_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  502. cdc_dma_sample_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  504. cdc_dma_sample_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  506. cdc_dma_sample_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  508. cdc_dma_sample_rate_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  510. cdc_dma_sample_rate_text);
  511. static struct platform_device *spdev;
  512. static bool is_initial_boot;
  513. static bool codec_reg_done;
  514. static struct snd_soc_aux_dev *msm_aux_dev;
  515. static struct snd_soc_codec_conf *msm_codec_conf;
  516. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  517. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  518. int enable, bool dapm);
  519. static int msm_wsa881x_init(struct snd_soc_component *component);
  520. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  521. {"MIC BIAS1", NULL, "MCLK TX"},
  522. {"MIC BIAS2", NULL, "MCLK TX"},
  523. {"MIC BIAS3", NULL, "MCLK TX"},
  524. {"MIC BIAS4", NULL, "MCLK TX"},
  525. };
  526. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  527. {
  528. AFE_API_VERSION_I2S_CONFIG,
  529. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  530. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  531. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  532. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  533. 0,
  534. },
  535. {
  536. AFE_API_VERSION_I2S_CONFIG,
  537. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  538. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  539. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  540. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  541. 0,
  542. },
  543. {
  544. AFE_API_VERSION_I2S_CONFIG,
  545. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  546. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  547. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  548. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  549. 0,
  550. },
  551. {
  552. AFE_API_VERSION_I2S_CONFIG,
  553. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  554. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  555. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  556. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  557. 0,
  558. },
  559. {
  560. AFE_API_VERSION_I2S_CONFIG,
  561. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  562. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  563. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  564. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  565. 0,
  566. }
  567. };
  568. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  569. static int slim_get_sample_rate_val(int sample_rate)
  570. {
  571. int sample_rate_val = 0;
  572. switch (sample_rate) {
  573. case SAMPLING_RATE_8KHZ:
  574. sample_rate_val = 0;
  575. break;
  576. case SAMPLING_RATE_16KHZ:
  577. sample_rate_val = 1;
  578. break;
  579. case SAMPLING_RATE_32KHZ:
  580. sample_rate_val = 2;
  581. break;
  582. case SAMPLING_RATE_44P1KHZ:
  583. sample_rate_val = 3;
  584. break;
  585. case SAMPLING_RATE_48KHZ:
  586. sample_rate_val = 4;
  587. break;
  588. case SAMPLING_RATE_88P2KHZ:
  589. sample_rate_val = 5;
  590. break;
  591. case SAMPLING_RATE_96KHZ:
  592. sample_rate_val = 6;
  593. break;
  594. case SAMPLING_RATE_176P4KHZ:
  595. sample_rate_val = 7;
  596. break;
  597. case SAMPLING_RATE_192KHZ:
  598. sample_rate_val = 8;
  599. break;
  600. case SAMPLING_RATE_352P8KHZ:
  601. sample_rate_val = 9;
  602. break;
  603. case SAMPLING_RATE_384KHZ:
  604. sample_rate_val = 10;
  605. break;
  606. default:
  607. sample_rate_val = 4;
  608. break;
  609. }
  610. return sample_rate_val;
  611. }
  612. static int slim_get_sample_rate(int value)
  613. {
  614. int sample_rate = 0;
  615. switch (value) {
  616. case 0:
  617. sample_rate = SAMPLING_RATE_8KHZ;
  618. break;
  619. case 1:
  620. sample_rate = SAMPLING_RATE_16KHZ;
  621. break;
  622. case 2:
  623. sample_rate = SAMPLING_RATE_32KHZ;
  624. break;
  625. case 3:
  626. sample_rate = SAMPLING_RATE_44P1KHZ;
  627. break;
  628. case 4:
  629. sample_rate = SAMPLING_RATE_48KHZ;
  630. break;
  631. case 5:
  632. sample_rate = SAMPLING_RATE_88P2KHZ;
  633. break;
  634. case 6:
  635. sample_rate = SAMPLING_RATE_96KHZ;
  636. break;
  637. case 7:
  638. sample_rate = SAMPLING_RATE_176P4KHZ;
  639. break;
  640. case 8:
  641. sample_rate = SAMPLING_RATE_192KHZ;
  642. break;
  643. case 9:
  644. sample_rate = SAMPLING_RATE_352P8KHZ;
  645. break;
  646. case 10:
  647. sample_rate = SAMPLING_RATE_384KHZ;
  648. break;
  649. default:
  650. sample_rate = SAMPLING_RATE_48KHZ;
  651. break;
  652. }
  653. return sample_rate;
  654. }
  655. static int slim_get_bit_format_val(int bit_format)
  656. {
  657. int val = 0;
  658. switch (bit_format) {
  659. case SNDRV_PCM_FORMAT_S32_LE:
  660. val = 3;
  661. break;
  662. case SNDRV_PCM_FORMAT_S24_3LE:
  663. val = 2;
  664. break;
  665. case SNDRV_PCM_FORMAT_S24_LE:
  666. val = 1;
  667. break;
  668. case SNDRV_PCM_FORMAT_S16_LE:
  669. default:
  670. val = 0;
  671. break;
  672. }
  673. return val;
  674. }
  675. static int slim_get_bit_format(int val)
  676. {
  677. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  678. switch (val) {
  679. case 0:
  680. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  681. break;
  682. case 1:
  683. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  684. break;
  685. case 2:
  686. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  687. break;
  688. case 3:
  689. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  690. break;
  691. default:
  692. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  693. break;
  694. }
  695. return bit_fmt;
  696. }
  697. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  698. {
  699. int port_id = 0;
  700. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  701. port_id = SLIM_RX_0;
  702. } else if (strnstr(kcontrol->id.name,
  703. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  704. port_id = SLIM_RX_2;
  705. } else if (strnstr(kcontrol->id.name,
  706. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  707. port_id = SLIM_RX_5;
  708. } else if (strnstr(kcontrol->id.name,
  709. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  710. port_id = SLIM_RX_6;
  711. } else if (strnstr(kcontrol->id.name,
  712. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  713. port_id = SLIM_TX_0;
  714. } else if (strnstr(kcontrol->id.name,
  715. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  716. port_id = SLIM_TX_1;
  717. } else {
  718. pr_err("%s: unsupported channel: %s",
  719. __func__, kcontrol->id.name);
  720. return -EINVAL;
  721. }
  722. return port_id;
  723. }
  724. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  725. struct snd_ctl_elem_value *ucontrol)
  726. {
  727. int ch_num = slim_get_port_idx(kcontrol);
  728. if (ch_num < 0)
  729. return ch_num;
  730. ucontrol->value.enumerated.item[0] =
  731. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  732. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  733. ch_num, slim_rx_cfg[ch_num].sample_rate,
  734. ucontrol->value.enumerated.item[0]);
  735. return 0;
  736. }
  737. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  738. struct snd_ctl_elem_value *ucontrol)
  739. {
  740. int ch_num = slim_get_port_idx(kcontrol);
  741. if (ch_num < 0)
  742. return ch_num;
  743. slim_rx_cfg[ch_num].sample_rate =
  744. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  745. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  746. ch_num, slim_rx_cfg[ch_num].sample_rate,
  747. ucontrol->value.enumerated.item[0]);
  748. return 0;
  749. }
  750. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  751. struct snd_ctl_elem_value *ucontrol)
  752. {
  753. int ch_num = slim_get_port_idx(kcontrol);
  754. if (ch_num < 0)
  755. return ch_num;
  756. ucontrol->value.enumerated.item[0] =
  757. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  758. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  759. ch_num, slim_tx_cfg[ch_num].sample_rate,
  760. ucontrol->value.enumerated.item[0]);
  761. return 0;
  762. }
  763. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  764. struct snd_ctl_elem_value *ucontrol)
  765. {
  766. int sample_rate = 0;
  767. int ch_num = slim_get_port_idx(kcontrol);
  768. if (ch_num < 0)
  769. return ch_num;
  770. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  771. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  772. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  773. __func__, sample_rate);
  774. return -EINVAL;
  775. }
  776. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  777. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  778. ch_num, slim_tx_cfg[ch_num].sample_rate,
  779. ucontrol->value.enumerated.item[0]);
  780. return 0;
  781. }
  782. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  783. struct snd_ctl_elem_value *ucontrol)
  784. {
  785. int ch_num = slim_get_port_idx(kcontrol);
  786. if (ch_num < 0)
  787. return ch_num;
  788. ucontrol->value.enumerated.item[0] =
  789. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  790. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  791. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  792. ucontrol->value.enumerated.item[0]);
  793. return 0;
  794. }
  795. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  796. struct snd_ctl_elem_value *ucontrol)
  797. {
  798. int ch_num = slim_get_port_idx(kcontrol);
  799. if (ch_num < 0)
  800. return ch_num;
  801. slim_rx_cfg[ch_num].bit_format =
  802. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  803. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  804. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  805. ucontrol->value.enumerated.item[0]);
  806. return 0;
  807. }
  808. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  809. struct snd_ctl_elem_value *ucontrol)
  810. {
  811. int ch_num = slim_get_port_idx(kcontrol);
  812. if (ch_num < 0)
  813. return ch_num;
  814. ucontrol->value.enumerated.item[0] =
  815. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  816. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  817. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  818. ucontrol->value.enumerated.item[0]);
  819. return 0;
  820. }
  821. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  822. struct snd_ctl_elem_value *ucontrol)
  823. {
  824. int ch_num = slim_get_port_idx(kcontrol);
  825. if (ch_num < 0)
  826. return ch_num;
  827. slim_tx_cfg[ch_num].bit_format =
  828. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  829. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  830. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  831. ucontrol->value.enumerated.item[0]);
  832. return 0;
  833. }
  834. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  835. struct snd_ctl_elem_value *ucontrol)
  836. {
  837. int ch_num = slim_get_port_idx(kcontrol);
  838. if (ch_num < 0)
  839. return ch_num;
  840. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  841. ch_num, slim_rx_cfg[ch_num].channels);
  842. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  843. return 0;
  844. }
  845. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  846. struct snd_ctl_elem_value *ucontrol)
  847. {
  848. int ch_num = slim_get_port_idx(kcontrol);
  849. if (ch_num < 0)
  850. return ch_num;
  851. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  852. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  853. ch_num, slim_rx_cfg[ch_num].channels);
  854. return 1;
  855. }
  856. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  857. struct snd_ctl_elem_value *ucontrol)
  858. {
  859. int ch_num = slim_get_port_idx(kcontrol);
  860. if (ch_num < 0)
  861. return ch_num;
  862. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  863. ch_num, slim_tx_cfg[ch_num].channels);
  864. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  865. return 0;
  866. }
  867. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  868. struct snd_ctl_elem_value *ucontrol)
  869. {
  870. int ch_num = slim_get_port_idx(kcontrol);
  871. if (ch_num < 0)
  872. return ch_num;
  873. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  874. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  875. ch_num, slim_tx_cfg[ch_num].channels);
  876. return 1;
  877. }
  878. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  879. struct snd_ctl_elem_value *ucontrol)
  880. {
  881. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  882. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  883. ucontrol->value.integer.value[0]);
  884. return 0;
  885. }
  886. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  887. struct snd_ctl_elem_value *ucontrol)
  888. {
  889. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  890. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  891. return 1;
  892. }
  893. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  894. struct snd_ctl_elem_value *ucontrol)
  895. {
  896. /*
  897. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  898. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  899. * value.
  900. */
  901. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  902. case SAMPLING_RATE_96KHZ:
  903. ucontrol->value.integer.value[0] = 5;
  904. break;
  905. case SAMPLING_RATE_88P2KHZ:
  906. ucontrol->value.integer.value[0] = 4;
  907. break;
  908. case SAMPLING_RATE_48KHZ:
  909. ucontrol->value.integer.value[0] = 3;
  910. break;
  911. case SAMPLING_RATE_44P1KHZ:
  912. ucontrol->value.integer.value[0] = 2;
  913. break;
  914. case SAMPLING_RATE_16KHZ:
  915. ucontrol->value.integer.value[0] = 1;
  916. break;
  917. case SAMPLING_RATE_8KHZ:
  918. default:
  919. ucontrol->value.integer.value[0] = 0;
  920. break;
  921. }
  922. pr_debug("%s: sample rate = %d", __func__,
  923. slim_rx_cfg[SLIM_RX_7].sample_rate);
  924. return 0;
  925. }
  926. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  927. struct snd_ctl_elem_value *ucontrol)
  928. {
  929. switch (ucontrol->value.integer.value[0]) {
  930. case 1:
  931. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  932. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  933. break;
  934. case 2:
  935. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  936. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  937. break;
  938. case 3:
  939. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  940. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  941. break;
  942. case 4:
  943. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  944. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  945. break;
  946. case 5:
  947. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  948. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  949. break;
  950. case 0:
  951. default:
  952. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  953. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  954. break;
  955. }
  956. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  957. __func__,
  958. slim_rx_cfg[SLIM_RX_7].sample_rate,
  959. slim_tx_cfg[SLIM_TX_7].sample_rate,
  960. ucontrol->value.enumerated.item[0]);
  961. return 0;
  962. }
  963. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  964. {
  965. int idx = 0;
  966. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  967. sizeof("WSA_CDC_DMA_RX_0")))
  968. idx = WSA_CDC_DMA_RX_0;
  969. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  970. sizeof("WSA_CDC_DMA_RX_0")))
  971. idx = WSA_CDC_DMA_RX_1;
  972. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  973. sizeof("WSA_CDC_DMA_TX_0")))
  974. idx = WSA_CDC_DMA_TX_0;
  975. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  976. sizeof("WSA_CDC_DMA_TX_1")))
  977. idx = WSA_CDC_DMA_TX_1;
  978. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  979. sizeof("WSA_CDC_DMA_TX_2")))
  980. idx = WSA_CDC_DMA_TX_2;
  981. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  982. sizeof("VA_CDC_DMA_TX_0")))
  983. idx = VA_CDC_DMA_TX_0;
  984. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  985. sizeof("VA_CDC_DMA_TX_1")))
  986. idx = VA_CDC_DMA_TX_1;
  987. else {
  988. pr_err("%s: unsupported port: %s\n",
  989. __func__, kcontrol->id.name);
  990. return -EINVAL;
  991. }
  992. return idx;
  993. }
  994. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  995. struct snd_ctl_elem_value *ucontrol)
  996. {
  997. int ch_num = cdc_dma_get_port_idx(kcontrol);
  998. if (ch_num < 0)
  999. return ch_num;
  1000. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1001. cdc_dma_rx_cfg[ch_num].channels - 1);
  1002. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1003. return 0;
  1004. }
  1005. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1006. struct snd_ctl_elem_value *ucontrol)
  1007. {
  1008. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1009. if (ch_num < 0)
  1010. return ch_num;
  1011. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1012. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1013. cdc_dma_rx_cfg[ch_num].channels);
  1014. return 1;
  1015. }
  1016. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1017. struct snd_ctl_elem_value *ucontrol)
  1018. {
  1019. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1020. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1021. case SNDRV_PCM_FORMAT_S32_LE:
  1022. ucontrol->value.integer.value[0] = 3;
  1023. break;
  1024. case SNDRV_PCM_FORMAT_S24_3LE:
  1025. ucontrol->value.integer.value[0] = 2;
  1026. break;
  1027. case SNDRV_PCM_FORMAT_S24_LE:
  1028. ucontrol->value.integer.value[0] = 1;
  1029. break;
  1030. case SNDRV_PCM_FORMAT_S16_LE:
  1031. default:
  1032. ucontrol->value.integer.value[0] = 0;
  1033. break;
  1034. }
  1035. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1036. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1037. ucontrol->value.integer.value[0]);
  1038. return 0;
  1039. }
  1040. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1041. struct snd_ctl_elem_value *ucontrol)
  1042. {
  1043. int rc = 0;
  1044. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1045. switch (ucontrol->value.integer.value[0]) {
  1046. case 3:
  1047. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1048. break;
  1049. case 2:
  1050. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1051. break;
  1052. case 1:
  1053. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1054. break;
  1055. case 0:
  1056. default:
  1057. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1058. break;
  1059. }
  1060. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1061. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1062. ucontrol->value.integer.value[0]);
  1063. return rc;
  1064. }
  1065. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1066. {
  1067. int sample_rate_val = 0;
  1068. switch (sample_rate) {
  1069. case SAMPLING_RATE_8KHZ:
  1070. sample_rate_val = 0;
  1071. break;
  1072. case SAMPLING_RATE_16KHZ:
  1073. sample_rate_val = 1;
  1074. break;
  1075. case SAMPLING_RATE_32KHZ:
  1076. sample_rate_val = 2;
  1077. break;
  1078. case SAMPLING_RATE_44P1KHZ:
  1079. sample_rate_val = 3;
  1080. break;
  1081. case SAMPLING_RATE_48KHZ:
  1082. sample_rate_val = 4;
  1083. break;
  1084. case SAMPLING_RATE_88P2KHZ:
  1085. sample_rate_val = 5;
  1086. break;
  1087. case SAMPLING_RATE_96KHZ:
  1088. sample_rate_val = 6;
  1089. break;
  1090. case SAMPLING_RATE_176P4KHZ:
  1091. sample_rate_val = 7;
  1092. break;
  1093. case SAMPLING_RATE_192KHZ:
  1094. sample_rate_val = 8;
  1095. break;
  1096. case SAMPLING_RATE_352P8KHZ:
  1097. sample_rate_val = 9;
  1098. break;
  1099. case SAMPLING_RATE_384KHZ:
  1100. sample_rate_val = 10;
  1101. break;
  1102. default:
  1103. sample_rate_val = 4;
  1104. break;
  1105. }
  1106. return sample_rate_val;
  1107. }
  1108. static int cdc_dma_get_sample_rate(int value)
  1109. {
  1110. int sample_rate = 0;
  1111. switch (value) {
  1112. case 0:
  1113. sample_rate = SAMPLING_RATE_8KHZ;
  1114. break;
  1115. case 1:
  1116. sample_rate = SAMPLING_RATE_16KHZ;
  1117. break;
  1118. case 2:
  1119. sample_rate = SAMPLING_RATE_32KHZ;
  1120. break;
  1121. case 3:
  1122. sample_rate = SAMPLING_RATE_44P1KHZ;
  1123. break;
  1124. case 4:
  1125. sample_rate = SAMPLING_RATE_48KHZ;
  1126. break;
  1127. case 5:
  1128. sample_rate = SAMPLING_RATE_88P2KHZ;
  1129. break;
  1130. case 6:
  1131. sample_rate = SAMPLING_RATE_96KHZ;
  1132. break;
  1133. case 7:
  1134. sample_rate = SAMPLING_RATE_176P4KHZ;
  1135. break;
  1136. case 8:
  1137. sample_rate = SAMPLING_RATE_192KHZ;
  1138. break;
  1139. case 9:
  1140. sample_rate = SAMPLING_RATE_352P8KHZ;
  1141. break;
  1142. case 10:
  1143. sample_rate = SAMPLING_RATE_384KHZ;
  1144. break;
  1145. default:
  1146. sample_rate = SAMPLING_RATE_48KHZ;
  1147. break;
  1148. }
  1149. return sample_rate;
  1150. }
  1151. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1152. struct snd_ctl_elem_value *ucontrol)
  1153. {
  1154. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1155. if (ch_num < 0)
  1156. return ch_num;
  1157. ucontrol->value.enumerated.item[0] =
  1158. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1159. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1160. cdc_dma_rx_cfg[ch_num].sample_rate);
  1161. return 0;
  1162. }
  1163. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1164. struct snd_ctl_elem_value *ucontrol)
  1165. {
  1166. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1167. if (ch_num < 0)
  1168. return ch_num;
  1169. cdc_dma_rx_cfg[ch_num].sample_rate =
  1170. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1171. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1172. __func__, ucontrol->value.enumerated.item[0],
  1173. cdc_dma_rx_cfg[ch_num].sample_rate);
  1174. return 0;
  1175. }
  1176. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1177. struct snd_ctl_elem_value *ucontrol)
  1178. {
  1179. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1180. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1181. cdc_dma_tx_cfg[ch_num].channels);
  1182. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1183. return 0;
  1184. }
  1185. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1186. struct snd_ctl_elem_value *ucontrol)
  1187. {
  1188. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1189. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1190. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1191. cdc_dma_tx_cfg[ch_num].channels);
  1192. return 1;
  1193. }
  1194. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1195. struct snd_ctl_elem_value *ucontrol)
  1196. {
  1197. int sample_rate_val;
  1198. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1199. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1200. case SAMPLING_RATE_384KHZ:
  1201. sample_rate_val = 12;
  1202. break;
  1203. case SAMPLING_RATE_352P8KHZ:
  1204. sample_rate_val = 11;
  1205. break;
  1206. case SAMPLING_RATE_192KHZ:
  1207. sample_rate_val = 10;
  1208. break;
  1209. case SAMPLING_RATE_176P4KHZ:
  1210. sample_rate_val = 9;
  1211. break;
  1212. case SAMPLING_RATE_96KHZ:
  1213. sample_rate_val = 8;
  1214. break;
  1215. case SAMPLING_RATE_88P2KHZ:
  1216. sample_rate_val = 7;
  1217. break;
  1218. case SAMPLING_RATE_48KHZ:
  1219. sample_rate_val = 6;
  1220. break;
  1221. case SAMPLING_RATE_44P1KHZ:
  1222. sample_rate_val = 5;
  1223. break;
  1224. case SAMPLING_RATE_32KHZ:
  1225. sample_rate_val = 4;
  1226. break;
  1227. case SAMPLING_RATE_22P05KHZ:
  1228. sample_rate_val = 3;
  1229. break;
  1230. case SAMPLING_RATE_16KHZ:
  1231. sample_rate_val = 2;
  1232. break;
  1233. case SAMPLING_RATE_11P025KHZ:
  1234. sample_rate_val = 1;
  1235. break;
  1236. case SAMPLING_RATE_8KHZ:
  1237. sample_rate_val = 0;
  1238. break;
  1239. default:
  1240. sample_rate_val = 6;
  1241. break;
  1242. }
  1243. ucontrol->value.integer.value[0] = sample_rate_val;
  1244. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1245. cdc_dma_tx_cfg[ch_num].sample_rate);
  1246. return 0;
  1247. }
  1248. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1249. struct snd_ctl_elem_value *ucontrol)
  1250. {
  1251. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1252. switch (ucontrol->value.integer.value[0]) {
  1253. case 12:
  1254. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1255. break;
  1256. case 11:
  1257. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1258. break;
  1259. case 10:
  1260. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1261. break;
  1262. case 9:
  1263. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1264. break;
  1265. case 8:
  1266. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1267. break;
  1268. case 7:
  1269. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1270. break;
  1271. case 6:
  1272. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1273. break;
  1274. case 5:
  1275. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1276. break;
  1277. case 4:
  1278. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1279. break;
  1280. case 3:
  1281. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1282. break;
  1283. case 2:
  1284. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1285. break;
  1286. case 1:
  1287. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1288. break;
  1289. case 0:
  1290. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1291. break;
  1292. default:
  1293. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1294. break;
  1295. }
  1296. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1297. __func__, ucontrol->value.integer.value[0],
  1298. cdc_dma_tx_cfg[ch_num].sample_rate);
  1299. return 0;
  1300. }
  1301. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1302. struct snd_ctl_elem_value *ucontrol)
  1303. {
  1304. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1305. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1306. case SNDRV_PCM_FORMAT_S32_LE:
  1307. ucontrol->value.integer.value[0] = 3;
  1308. break;
  1309. case SNDRV_PCM_FORMAT_S24_3LE:
  1310. ucontrol->value.integer.value[0] = 2;
  1311. break;
  1312. case SNDRV_PCM_FORMAT_S24_LE:
  1313. ucontrol->value.integer.value[0] = 1;
  1314. break;
  1315. case SNDRV_PCM_FORMAT_S16_LE:
  1316. default:
  1317. ucontrol->value.integer.value[0] = 0;
  1318. break;
  1319. }
  1320. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1321. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1322. ucontrol->value.integer.value[0]);
  1323. return 0;
  1324. }
  1325. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1326. struct snd_ctl_elem_value *ucontrol)
  1327. {
  1328. int rc = 0;
  1329. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1330. switch (ucontrol->value.integer.value[0]) {
  1331. case 3:
  1332. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1333. break;
  1334. case 2:
  1335. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1336. break;
  1337. case 1:
  1338. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1339. break;
  1340. case 0:
  1341. default:
  1342. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1343. break;
  1344. }
  1345. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1346. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1347. ucontrol->value.integer.value[0]);
  1348. return rc;
  1349. }
  1350. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1351. struct snd_ctl_elem_value *ucontrol)
  1352. {
  1353. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1354. usb_rx_cfg.channels);
  1355. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1356. return 0;
  1357. }
  1358. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1359. struct snd_ctl_elem_value *ucontrol)
  1360. {
  1361. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1362. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1363. return 1;
  1364. }
  1365. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1366. struct snd_ctl_elem_value *ucontrol)
  1367. {
  1368. int sample_rate_val;
  1369. switch (usb_rx_cfg.sample_rate) {
  1370. case SAMPLING_RATE_384KHZ:
  1371. sample_rate_val = 12;
  1372. break;
  1373. case SAMPLING_RATE_352P8KHZ:
  1374. sample_rate_val = 11;
  1375. break;
  1376. case SAMPLING_RATE_192KHZ:
  1377. sample_rate_val = 10;
  1378. break;
  1379. case SAMPLING_RATE_176P4KHZ:
  1380. sample_rate_val = 9;
  1381. break;
  1382. case SAMPLING_RATE_96KHZ:
  1383. sample_rate_val = 8;
  1384. break;
  1385. case SAMPLING_RATE_88P2KHZ:
  1386. sample_rate_val = 7;
  1387. break;
  1388. case SAMPLING_RATE_48KHZ:
  1389. sample_rate_val = 6;
  1390. break;
  1391. case SAMPLING_RATE_44P1KHZ:
  1392. sample_rate_val = 5;
  1393. break;
  1394. case SAMPLING_RATE_32KHZ:
  1395. sample_rate_val = 4;
  1396. break;
  1397. case SAMPLING_RATE_22P05KHZ:
  1398. sample_rate_val = 3;
  1399. break;
  1400. case SAMPLING_RATE_16KHZ:
  1401. sample_rate_val = 2;
  1402. break;
  1403. case SAMPLING_RATE_11P025KHZ:
  1404. sample_rate_val = 1;
  1405. break;
  1406. case SAMPLING_RATE_8KHZ:
  1407. default:
  1408. sample_rate_val = 0;
  1409. break;
  1410. }
  1411. ucontrol->value.integer.value[0] = sample_rate_val;
  1412. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1413. usb_rx_cfg.sample_rate);
  1414. return 0;
  1415. }
  1416. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1417. struct snd_ctl_elem_value *ucontrol)
  1418. {
  1419. switch (ucontrol->value.integer.value[0]) {
  1420. case 12:
  1421. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1422. break;
  1423. case 11:
  1424. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1425. break;
  1426. case 10:
  1427. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1428. break;
  1429. case 9:
  1430. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1431. break;
  1432. case 8:
  1433. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1434. break;
  1435. case 7:
  1436. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1437. break;
  1438. case 6:
  1439. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1440. break;
  1441. case 5:
  1442. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1443. break;
  1444. case 4:
  1445. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1446. break;
  1447. case 3:
  1448. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1449. break;
  1450. case 2:
  1451. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1452. break;
  1453. case 1:
  1454. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1455. break;
  1456. case 0:
  1457. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1458. break;
  1459. default:
  1460. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1461. break;
  1462. }
  1463. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1464. __func__, ucontrol->value.integer.value[0],
  1465. usb_rx_cfg.sample_rate);
  1466. return 0;
  1467. }
  1468. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1469. struct snd_ctl_elem_value *ucontrol)
  1470. {
  1471. switch (usb_rx_cfg.bit_format) {
  1472. case SNDRV_PCM_FORMAT_S32_LE:
  1473. ucontrol->value.integer.value[0] = 3;
  1474. break;
  1475. case SNDRV_PCM_FORMAT_S24_3LE:
  1476. ucontrol->value.integer.value[0] = 2;
  1477. break;
  1478. case SNDRV_PCM_FORMAT_S24_LE:
  1479. ucontrol->value.integer.value[0] = 1;
  1480. break;
  1481. case SNDRV_PCM_FORMAT_S16_LE:
  1482. default:
  1483. ucontrol->value.integer.value[0] = 0;
  1484. break;
  1485. }
  1486. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1487. __func__, usb_rx_cfg.bit_format,
  1488. ucontrol->value.integer.value[0]);
  1489. return 0;
  1490. }
  1491. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1492. struct snd_ctl_elem_value *ucontrol)
  1493. {
  1494. int rc = 0;
  1495. switch (ucontrol->value.integer.value[0]) {
  1496. case 3:
  1497. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1498. break;
  1499. case 2:
  1500. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1501. break;
  1502. case 1:
  1503. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1504. break;
  1505. case 0:
  1506. default:
  1507. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1508. break;
  1509. }
  1510. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1511. __func__, usb_rx_cfg.bit_format,
  1512. ucontrol->value.integer.value[0]);
  1513. return rc;
  1514. }
  1515. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1516. struct snd_ctl_elem_value *ucontrol)
  1517. {
  1518. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1519. usb_tx_cfg.channels);
  1520. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1521. return 0;
  1522. }
  1523. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1524. struct snd_ctl_elem_value *ucontrol)
  1525. {
  1526. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1527. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1528. return 1;
  1529. }
  1530. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1531. struct snd_ctl_elem_value *ucontrol)
  1532. {
  1533. int sample_rate_val;
  1534. switch (usb_tx_cfg.sample_rate) {
  1535. case SAMPLING_RATE_384KHZ:
  1536. sample_rate_val = 12;
  1537. break;
  1538. case SAMPLING_RATE_352P8KHZ:
  1539. sample_rate_val = 11;
  1540. break;
  1541. case SAMPLING_RATE_192KHZ:
  1542. sample_rate_val = 10;
  1543. break;
  1544. case SAMPLING_RATE_176P4KHZ:
  1545. sample_rate_val = 9;
  1546. break;
  1547. case SAMPLING_RATE_96KHZ:
  1548. sample_rate_val = 8;
  1549. break;
  1550. case SAMPLING_RATE_88P2KHZ:
  1551. sample_rate_val = 7;
  1552. break;
  1553. case SAMPLING_RATE_48KHZ:
  1554. sample_rate_val = 6;
  1555. break;
  1556. case SAMPLING_RATE_44P1KHZ:
  1557. sample_rate_val = 5;
  1558. break;
  1559. case SAMPLING_RATE_32KHZ:
  1560. sample_rate_val = 4;
  1561. break;
  1562. case SAMPLING_RATE_22P05KHZ:
  1563. sample_rate_val = 3;
  1564. break;
  1565. case SAMPLING_RATE_16KHZ:
  1566. sample_rate_val = 2;
  1567. break;
  1568. case SAMPLING_RATE_11P025KHZ:
  1569. sample_rate_val = 1;
  1570. break;
  1571. case SAMPLING_RATE_8KHZ:
  1572. sample_rate_val = 0;
  1573. break;
  1574. default:
  1575. sample_rate_val = 6;
  1576. break;
  1577. }
  1578. ucontrol->value.integer.value[0] = sample_rate_val;
  1579. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1580. usb_tx_cfg.sample_rate);
  1581. return 0;
  1582. }
  1583. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1584. struct snd_ctl_elem_value *ucontrol)
  1585. {
  1586. switch (ucontrol->value.integer.value[0]) {
  1587. case 12:
  1588. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1589. break;
  1590. case 11:
  1591. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1592. break;
  1593. case 10:
  1594. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1595. break;
  1596. case 9:
  1597. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1598. break;
  1599. case 8:
  1600. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1601. break;
  1602. case 7:
  1603. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1604. break;
  1605. case 6:
  1606. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1607. break;
  1608. case 5:
  1609. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1610. break;
  1611. case 4:
  1612. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1613. break;
  1614. case 3:
  1615. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1616. break;
  1617. case 2:
  1618. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1619. break;
  1620. case 1:
  1621. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1622. break;
  1623. case 0:
  1624. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1625. break;
  1626. default:
  1627. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1628. break;
  1629. }
  1630. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1631. __func__, ucontrol->value.integer.value[0],
  1632. usb_tx_cfg.sample_rate);
  1633. return 0;
  1634. }
  1635. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1636. struct snd_ctl_elem_value *ucontrol)
  1637. {
  1638. switch (usb_tx_cfg.bit_format) {
  1639. case SNDRV_PCM_FORMAT_S32_LE:
  1640. ucontrol->value.integer.value[0] = 3;
  1641. break;
  1642. case SNDRV_PCM_FORMAT_S24_3LE:
  1643. ucontrol->value.integer.value[0] = 2;
  1644. break;
  1645. case SNDRV_PCM_FORMAT_S24_LE:
  1646. ucontrol->value.integer.value[0] = 1;
  1647. break;
  1648. case SNDRV_PCM_FORMAT_S16_LE:
  1649. default:
  1650. ucontrol->value.integer.value[0] = 0;
  1651. break;
  1652. }
  1653. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1654. __func__, usb_tx_cfg.bit_format,
  1655. ucontrol->value.integer.value[0]);
  1656. return 0;
  1657. }
  1658. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1659. struct snd_ctl_elem_value *ucontrol)
  1660. {
  1661. int rc = 0;
  1662. switch (ucontrol->value.integer.value[0]) {
  1663. case 3:
  1664. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1665. break;
  1666. case 2:
  1667. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1668. break;
  1669. case 1:
  1670. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1671. break;
  1672. case 0:
  1673. default:
  1674. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1675. break;
  1676. }
  1677. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1678. __func__, usb_tx_cfg.bit_format,
  1679. ucontrol->value.integer.value[0]);
  1680. return rc;
  1681. }
  1682. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1683. struct snd_ctl_elem_value *ucontrol)
  1684. {
  1685. pr_debug("%s: proxy_rx channels = %d\n",
  1686. __func__, proxy_rx_cfg.channels);
  1687. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1688. return 0;
  1689. }
  1690. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1691. struct snd_ctl_elem_value *ucontrol)
  1692. {
  1693. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1694. pr_debug("%s: proxy_rx channels = %d\n",
  1695. __func__, proxy_rx_cfg.channels);
  1696. return 1;
  1697. }
  1698. static int tdm_get_sample_rate(int value)
  1699. {
  1700. int sample_rate = 0;
  1701. switch (value) {
  1702. case 0:
  1703. sample_rate = SAMPLING_RATE_8KHZ;
  1704. break;
  1705. case 1:
  1706. sample_rate = SAMPLING_RATE_16KHZ;
  1707. break;
  1708. case 2:
  1709. sample_rate = SAMPLING_RATE_32KHZ;
  1710. break;
  1711. case 3:
  1712. sample_rate = SAMPLING_RATE_48KHZ;
  1713. break;
  1714. case 4:
  1715. sample_rate = SAMPLING_RATE_176P4KHZ;
  1716. break;
  1717. case 5:
  1718. sample_rate = SAMPLING_RATE_352P8KHZ;
  1719. break;
  1720. default:
  1721. sample_rate = SAMPLING_RATE_48KHZ;
  1722. break;
  1723. }
  1724. return sample_rate;
  1725. }
  1726. static int aux_pcm_get_sample_rate(int value)
  1727. {
  1728. int sample_rate;
  1729. switch (value) {
  1730. case 1:
  1731. sample_rate = SAMPLING_RATE_16KHZ;
  1732. break;
  1733. case 0:
  1734. default:
  1735. sample_rate = SAMPLING_RATE_8KHZ;
  1736. break;
  1737. }
  1738. return sample_rate;
  1739. }
  1740. static int tdm_get_sample_rate_val(int sample_rate)
  1741. {
  1742. int sample_rate_val = 0;
  1743. switch (sample_rate) {
  1744. case SAMPLING_RATE_8KHZ:
  1745. sample_rate_val = 0;
  1746. break;
  1747. case SAMPLING_RATE_16KHZ:
  1748. sample_rate_val = 1;
  1749. break;
  1750. case SAMPLING_RATE_32KHZ:
  1751. sample_rate_val = 2;
  1752. break;
  1753. case SAMPLING_RATE_48KHZ:
  1754. sample_rate_val = 3;
  1755. break;
  1756. case SAMPLING_RATE_176P4KHZ:
  1757. sample_rate_val = 4;
  1758. break;
  1759. case SAMPLING_RATE_352P8KHZ:
  1760. sample_rate_val = 5;
  1761. break;
  1762. default:
  1763. sample_rate_val = 3;
  1764. break;
  1765. }
  1766. return sample_rate_val;
  1767. }
  1768. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1769. {
  1770. int sample_rate_val;
  1771. switch (sample_rate) {
  1772. case SAMPLING_RATE_16KHZ:
  1773. sample_rate_val = 1;
  1774. break;
  1775. case SAMPLING_RATE_8KHZ:
  1776. default:
  1777. sample_rate_val = 0;
  1778. break;
  1779. }
  1780. return sample_rate_val;
  1781. }
  1782. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1783. struct tdm_port *port)
  1784. {
  1785. if (port) {
  1786. if (strnstr(kcontrol->id.name, "PRI",
  1787. sizeof(kcontrol->id.name))) {
  1788. port->mode = TDM_PRI;
  1789. } else if (strnstr(kcontrol->id.name, "SEC",
  1790. sizeof(kcontrol->id.name))) {
  1791. port->mode = TDM_SEC;
  1792. } else if (strnstr(kcontrol->id.name, "TERT",
  1793. sizeof(kcontrol->id.name))) {
  1794. port->mode = TDM_TERT;
  1795. } else if (strnstr(kcontrol->id.name, "QUAT",
  1796. sizeof(kcontrol->id.name))) {
  1797. port->mode = TDM_QUAT;
  1798. } else if (strnstr(kcontrol->id.name, "QUIN",
  1799. sizeof(kcontrol->id.name))) {
  1800. port->mode = TDM_QUIN;
  1801. } else {
  1802. pr_err("%s: unsupported mode in: %s",
  1803. __func__, kcontrol->id.name);
  1804. return -EINVAL;
  1805. }
  1806. if (strnstr(kcontrol->id.name, "RX_0",
  1807. sizeof(kcontrol->id.name)) ||
  1808. strnstr(kcontrol->id.name, "TX_0",
  1809. sizeof(kcontrol->id.name))) {
  1810. port->channel = TDM_0;
  1811. } else if (strnstr(kcontrol->id.name, "RX_1",
  1812. sizeof(kcontrol->id.name)) ||
  1813. strnstr(kcontrol->id.name, "TX_1",
  1814. sizeof(kcontrol->id.name))) {
  1815. port->channel = TDM_1;
  1816. } else if (strnstr(kcontrol->id.name, "RX_2",
  1817. sizeof(kcontrol->id.name)) ||
  1818. strnstr(kcontrol->id.name, "TX_2",
  1819. sizeof(kcontrol->id.name))) {
  1820. port->channel = TDM_2;
  1821. } else if (strnstr(kcontrol->id.name, "RX_3",
  1822. sizeof(kcontrol->id.name)) ||
  1823. strnstr(kcontrol->id.name, "TX_3",
  1824. sizeof(kcontrol->id.name))) {
  1825. port->channel = TDM_3;
  1826. } else if (strnstr(kcontrol->id.name, "RX_4",
  1827. sizeof(kcontrol->id.name)) ||
  1828. strnstr(kcontrol->id.name, "TX_4",
  1829. sizeof(kcontrol->id.name))) {
  1830. port->channel = TDM_4;
  1831. } else if (strnstr(kcontrol->id.name, "RX_5",
  1832. sizeof(kcontrol->id.name)) ||
  1833. strnstr(kcontrol->id.name, "TX_5",
  1834. sizeof(kcontrol->id.name))) {
  1835. port->channel = TDM_5;
  1836. } else if (strnstr(kcontrol->id.name, "RX_6",
  1837. sizeof(kcontrol->id.name)) ||
  1838. strnstr(kcontrol->id.name, "TX_6",
  1839. sizeof(kcontrol->id.name))) {
  1840. port->channel = TDM_6;
  1841. } else if (strnstr(kcontrol->id.name, "RX_7",
  1842. sizeof(kcontrol->id.name)) ||
  1843. strnstr(kcontrol->id.name, "TX_7",
  1844. sizeof(kcontrol->id.name))) {
  1845. port->channel = TDM_7;
  1846. } else {
  1847. pr_err("%s: unsupported channel in: %s",
  1848. __func__, kcontrol->id.name);
  1849. return -EINVAL;
  1850. }
  1851. } else
  1852. return -EINVAL;
  1853. return 0;
  1854. }
  1855. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1856. struct snd_ctl_elem_value *ucontrol)
  1857. {
  1858. struct tdm_port port;
  1859. int ret = tdm_get_port_idx(kcontrol, &port);
  1860. if (ret) {
  1861. pr_err("%s: unsupported control: %s",
  1862. __func__, kcontrol->id.name);
  1863. } else {
  1864. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1865. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1866. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1867. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1868. ucontrol->value.enumerated.item[0]);
  1869. }
  1870. return ret;
  1871. }
  1872. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1873. struct snd_ctl_elem_value *ucontrol)
  1874. {
  1875. struct tdm_port port;
  1876. int ret = tdm_get_port_idx(kcontrol, &port);
  1877. if (ret) {
  1878. pr_err("%s: unsupported control: %s",
  1879. __func__, kcontrol->id.name);
  1880. } else {
  1881. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1882. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1883. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1884. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1885. ucontrol->value.enumerated.item[0]);
  1886. }
  1887. return ret;
  1888. }
  1889. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1890. struct snd_ctl_elem_value *ucontrol)
  1891. {
  1892. struct tdm_port port;
  1893. int ret = tdm_get_port_idx(kcontrol, &port);
  1894. if (ret) {
  1895. pr_err("%s: unsupported control: %s",
  1896. __func__, kcontrol->id.name);
  1897. } else {
  1898. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1899. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1900. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1901. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1902. ucontrol->value.enumerated.item[0]);
  1903. }
  1904. return ret;
  1905. }
  1906. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1907. struct snd_ctl_elem_value *ucontrol)
  1908. {
  1909. struct tdm_port port;
  1910. int ret = tdm_get_port_idx(kcontrol, &port);
  1911. if (ret) {
  1912. pr_err("%s: unsupported control: %s",
  1913. __func__, kcontrol->id.name);
  1914. } else {
  1915. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1916. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1917. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1918. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1919. ucontrol->value.enumerated.item[0]);
  1920. }
  1921. return ret;
  1922. }
  1923. static int tdm_get_format(int value)
  1924. {
  1925. int format = 0;
  1926. switch (value) {
  1927. case 0:
  1928. format = SNDRV_PCM_FORMAT_S16_LE;
  1929. break;
  1930. case 1:
  1931. format = SNDRV_PCM_FORMAT_S24_LE;
  1932. break;
  1933. case 2:
  1934. format = SNDRV_PCM_FORMAT_S32_LE;
  1935. break;
  1936. default:
  1937. format = SNDRV_PCM_FORMAT_S16_LE;
  1938. break;
  1939. }
  1940. return format;
  1941. }
  1942. static int tdm_get_format_val(int format)
  1943. {
  1944. int value = 0;
  1945. switch (format) {
  1946. case SNDRV_PCM_FORMAT_S16_LE:
  1947. value = 0;
  1948. break;
  1949. case SNDRV_PCM_FORMAT_S24_LE:
  1950. value = 1;
  1951. break;
  1952. case SNDRV_PCM_FORMAT_S32_LE:
  1953. value = 2;
  1954. break;
  1955. default:
  1956. value = 0;
  1957. break;
  1958. }
  1959. return value;
  1960. }
  1961. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1962. struct snd_ctl_elem_value *ucontrol)
  1963. {
  1964. struct tdm_port port;
  1965. int ret = tdm_get_port_idx(kcontrol, &port);
  1966. if (ret) {
  1967. pr_err("%s: unsupported control: %s",
  1968. __func__, kcontrol->id.name);
  1969. } else {
  1970. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1971. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1972. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1973. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1974. ucontrol->value.enumerated.item[0]);
  1975. }
  1976. return ret;
  1977. }
  1978. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1979. struct snd_ctl_elem_value *ucontrol)
  1980. {
  1981. struct tdm_port port;
  1982. int ret = tdm_get_port_idx(kcontrol, &port);
  1983. if (ret) {
  1984. pr_err("%s: unsupported control: %s",
  1985. __func__, kcontrol->id.name);
  1986. } else {
  1987. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1988. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1989. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1990. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1991. ucontrol->value.enumerated.item[0]);
  1992. }
  1993. return ret;
  1994. }
  1995. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1996. struct snd_ctl_elem_value *ucontrol)
  1997. {
  1998. struct tdm_port port;
  1999. int ret = tdm_get_port_idx(kcontrol, &port);
  2000. if (ret) {
  2001. pr_err("%s: unsupported control: %s",
  2002. __func__, kcontrol->id.name);
  2003. } else {
  2004. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2005. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2006. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2007. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2008. ucontrol->value.enumerated.item[0]);
  2009. }
  2010. return ret;
  2011. }
  2012. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2013. struct snd_ctl_elem_value *ucontrol)
  2014. {
  2015. struct tdm_port port;
  2016. int ret = tdm_get_port_idx(kcontrol, &port);
  2017. if (ret) {
  2018. pr_err("%s: unsupported control: %s",
  2019. __func__, kcontrol->id.name);
  2020. } else {
  2021. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2022. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2023. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2024. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2025. ucontrol->value.enumerated.item[0]);
  2026. }
  2027. return ret;
  2028. }
  2029. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2030. struct snd_ctl_elem_value *ucontrol)
  2031. {
  2032. struct tdm_port port;
  2033. int ret = tdm_get_port_idx(kcontrol, &port);
  2034. if (ret) {
  2035. pr_err("%s: unsupported control: %s",
  2036. __func__, kcontrol->id.name);
  2037. } else {
  2038. ucontrol->value.enumerated.item[0] =
  2039. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2040. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2041. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2042. ucontrol->value.enumerated.item[0]);
  2043. }
  2044. return ret;
  2045. }
  2046. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2047. struct snd_ctl_elem_value *ucontrol)
  2048. {
  2049. struct tdm_port port;
  2050. int ret = tdm_get_port_idx(kcontrol, &port);
  2051. if (ret) {
  2052. pr_err("%s: unsupported control: %s",
  2053. __func__, kcontrol->id.name);
  2054. } else {
  2055. tdm_rx_cfg[port.mode][port.channel].channels =
  2056. ucontrol->value.enumerated.item[0] + 1;
  2057. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2058. tdm_rx_cfg[port.mode][port.channel].channels,
  2059. ucontrol->value.enumerated.item[0] + 1);
  2060. }
  2061. return ret;
  2062. }
  2063. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2064. struct snd_ctl_elem_value *ucontrol)
  2065. {
  2066. struct tdm_port port;
  2067. int ret = tdm_get_port_idx(kcontrol, &port);
  2068. if (ret) {
  2069. pr_err("%s: unsupported control: %s",
  2070. __func__, kcontrol->id.name);
  2071. } else {
  2072. ucontrol->value.enumerated.item[0] =
  2073. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2074. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2075. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2076. ucontrol->value.enumerated.item[0]);
  2077. }
  2078. return ret;
  2079. }
  2080. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2081. struct snd_ctl_elem_value *ucontrol)
  2082. {
  2083. struct tdm_port port;
  2084. int ret = tdm_get_port_idx(kcontrol, &port);
  2085. if (ret) {
  2086. pr_err("%s: unsupported control: %s",
  2087. __func__, kcontrol->id.name);
  2088. } else {
  2089. tdm_tx_cfg[port.mode][port.channel].channels =
  2090. ucontrol->value.enumerated.item[0] + 1;
  2091. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2092. tdm_tx_cfg[port.mode][port.channel].channels,
  2093. ucontrol->value.enumerated.item[0] + 1);
  2094. }
  2095. return ret;
  2096. }
  2097. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2098. {
  2099. int idx;
  2100. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2101. sizeof("PRIM_AUX_PCM")))
  2102. idx = PRIM_AUX_PCM;
  2103. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2104. sizeof("SEC_AUX_PCM")))
  2105. idx = SEC_AUX_PCM;
  2106. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2107. sizeof("TERT_AUX_PCM")))
  2108. idx = TERT_AUX_PCM;
  2109. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2110. sizeof("QUAT_AUX_PCM")))
  2111. idx = QUAT_AUX_PCM;
  2112. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2113. sizeof("QUIN_AUX_PCM")))
  2114. idx = QUIN_AUX_PCM;
  2115. else {
  2116. pr_err("%s: unsupported port: %s",
  2117. __func__, kcontrol->id.name);
  2118. idx = -EINVAL;
  2119. }
  2120. return idx;
  2121. }
  2122. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2123. struct snd_ctl_elem_value *ucontrol)
  2124. {
  2125. int idx = aux_pcm_get_port_idx(kcontrol);
  2126. if (idx < 0)
  2127. return idx;
  2128. aux_pcm_rx_cfg[idx].sample_rate =
  2129. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2130. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2131. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2132. ucontrol->value.enumerated.item[0]);
  2133. return 0;
  2134. }
  2135. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2136. struct snd_ctl_elem_value *ucontrol)
  2137. {
  2138. int idx = aux_pcm_get_port_idx(kcontrol);
  2139. if (idx < 0)
  2140. return idx;
  2141. ucontrol->value.enumerated.item[0] =
  2142. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2143. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2144. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2145. ucontrol->value.enumerated.item[0]);
  2146. return 0;
  2147. }
  2148. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2149. struct snd_ctl_elem_value *ucontrol)
  2150. {
  2151. int idx = aux_pcm_get_port_idx(kcontrol);
  2152. if (idx < 0)
  2153. return idx;
  2154. aux_pcm_tx_cfg[idx].sample_rate =
  2155. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2156. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2157. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2158. ucontrol->value.enumerated.item[0]);
  2159. return 0;
  2160. }
  2161. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2162. struct snd_ctl_elem_value *ucontrol)
  2163. {
  2164. int idx = aux_pcm_get_port_idx(kcontrol);
  2165. if (idx < 0)
  2166. return idx;
  2167. ucontrol->value.enumerated.item[0] =
  2168. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2169. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2170. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2171. ucontrol->value.enumerated.item[0]);
  2172. return 0;
  2173. }
  2174. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2175. {
  2176. int idx;
  2177. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2178. sizeof("PRIM_MI2S_RX")))
  2179. idx = PRIM_MI2S;
  2180. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2181. sizeof("SEC_MI2S_RX")))
  2182. idx = SEC_MI2S;
  2183. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2184. sizeof("TERT_MI2S_RX")))
  2185. idx = TERT_MI2S;
  2186. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2187. sizeof("QUAT_MI2S_RX")))
  2188. idx = QUAT_MI2S;
  2189. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2190. sizeof("QUIN_MI2S_RX")))
  2191. idx = QUIN_MI2S;
  2192. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2193. sizeof("PRIM_MI2S_TX")))
  2194. idx = PRIM_MI2S;
  2195. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2196. sizeof("SEC_MI2S_TX")))
  2197. idx = SEC_MI2S;
  2198. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2199. sizeof("TERT_MI2S_TX")))
  2200. idx = TERT_MI2S;
  2201. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2202. sizeof("QUAT_MI2S_TX")))
  2203. idx = QUAT_MI2S;
  2204. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2205. sizeof("QUIN_MI2S_TX")))
  2206. idx = QUIN_MI2S;
  2207. else {
  2208. pr_err("%s: unsupported channel: %s",
  2209. __func__, kcontrol->id.name);
  2210. idx = -EINVAL;
  2211. }
  2212. return idx;
  2213. }
  2214. static int mi2s_get_sample_rate_val(int sample_rate)
  2215. {
  2216. int sample_rate_val;
  2217. switch (sample_rate) {
  2218. case SAMPLING_RATE_8KHZ:
  2219. sample_rate_val = 0;
  2220. break;
  2221. case SAMPLING_RATE_11P025KHZ:
  2222. sample_rate_val = 1;
  2223. break;
  2224. case SAMPLING_RATE_16KHZ:
  2225. sample_rate_val = 2;
  2226. break;
  2227. case SAMPLING_RATE_22P05KHZ:
  2228. sample_rate_val = 3;
  2229. break;
  2230. case SAMPLING_RATE_32KHZ:
  2231. sample_rate_val = 4;
  2232. break;
  2233. case SAMPLING_RATE_44P1KHZ:
  2234. sample_rate_val = 5;
  2235. break;
  2236. case SAMPLING_RATE_48KHZ:
  2237. sample_rate_val = 6;
  2238. break;
  2239. case SAMPLING_RATE_96KHZ:
  2240. sample_rate_val = 7;
  2241. break;
  2242. case SAMPLING_RATE_192KHZ:
  2243. sample_rate_val = 8;
  2244. break;
  2245. default:
  2246. sample_rate_val = 6;
  2247. break;
  2248. }
  2249. return sample_rate_val;
  2250. }
  2251. static int mi2s_get_sample_rate(int value)
  2252. {
  2253. int sample_rate;
  2254. switch (value) {
  2255. case 0:
  2256. sample_rate = SAMPLING_RATE_8KHZ;
  2257. break;
  2258. case 1:
  2259. sample_rate = SAMPLING_RATE_11P025KHZ;
  2260. break;
  2261. case 2:
  2262. sample_rate = SAMPLING_RATE_16KHZ;
  2263. break;
  2264. case 3:
  2265. sample_rate = SAMPLING_RATE_22P05KHZ;
  2266. break;
  2267. case 4:
  2268. sample_rate = SAMPLING_RATE_32KHZ;
  2269. break;
  2270. case 5:
  2271. sample_rate = SAMPLING_RATE_44P1KHZ;
  2272. break;
  2273. case 6:
  2274. sample_rate = SAMPLING_RATE_48KHZ;
  2275. break;
  2276. case 7:
  2277. sample_rate = SAMPLING_RATE_96KHZ;
  2278. break;
  2279. case 8:
  2280. sample_rate = SAMPLING_RATE_192KHZ;
  2281. break;
  2282. default:
  2283. sample_rate = SAMPLING_RATE_48KHZ;
  2284. break;
  2285. }
  2286. return sample_rate;
  2287. }
  2288. static int mi2s_auxpcm_get_format(int value)
  2289. {
  2290. int format;
  2291. switch (value) {
  2292. case 0:
  2293. format = SNDRV_PCM_FORMAT_S16_LE;
  2294. break;
  2295. case 1:
  2296. format = SNDRV_PCM_FORMAT_S24_LE;
  2297. break;
  2298. case 2:
  2299. format = SNDRV_PCM_FORMAT_S24_3LE;
  2300. break;
  2301. case 3:
  2302. format = SNDRV_PCM_FORMAT_S32_LE;
  2303. break;
  2304. default:
  2305. format = SNDRV_PCM_FORMAT_S16_LE;
  2306. break;
  2307. }
  2308. return format;
  2309. }
  2310. static int mi2s_auxpcm_get_format_value(int format)
  2311. {
  2312. int value;
  2313. switch (format) {
  2314. case SNDRV_PCM_FORMAT_S16_LE:
  2315. value = 0;
  2316. break;
  2317. case SNDRV_PCM_FORMAT_S24_LE:
  2318. value = 1;
  2319. break;
  2320. case SNDRV_PCM_FORMAT_S24_3LE:
  2321. value = 2;
  2322. break;
  2323. case SNDRV_PCM_FORMAT_S32_LE:
  2324. value = 3;
  2325. break;
  2326. default:
  2327. value = 0;
  2328. break;
  2329. }
  2330. return value;
  2331. }
  2332. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2333. struct snd_ctl_elem_value *ucontrol)
  2334. {
  2335. int idx = mi2s_get_port_idx(kcontrol);
  2336. if (idx < 0)
  2337. return idx;
  2338. mi2s_rx_cfg[idx].sample_rate =
  2339. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2340. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2341. idx, mi2s_rx_cfg[idx].sample_rate,
  2342. ucontrol->value.enumerated.item[0]);
  2343. return 0;
  2344. }
  2345. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2346. struct snd_ctl_elem_value *ucontrol)
  2347. {
  2348. int idx = mi2s_get_port_idx(kcontrol);
  2349. if (idx < 0)
  2350. return idx;
  2351. ucontrol->value.enumerated.item[0] =
  2352. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2353. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2354. idx, mi2s_rx_cfg[idx].sample_rate,
  2355. ucontrol->value.enumerated.item[0]);
  2356. return 0;
  2357. }
  2358. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2359. struct snd_ctl_elem_value *ucontrol)
  2360. {
  2361. int idx = mi2s_get_port_idx(kcontrol);
  2362. if (idx < 0)
  2363. return idx;
  2364. mi2s_tx_cfg[idx].sample_rate =
  2365. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2366. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2367. idx, mi2s_tx_cfg[idx].sample_rate,
  2368. ucontrol->value.enumerated.item[0]);
  2369. return 0;
  2370. }
  2371. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2372. struct snd_ctl_elem_value *ucontrol)
  2373. {
  2374. int idx = mi2s_get_port_idx(kcontrol);
  2375. if (idx < 0)
  2376. return idx;
  2377. ucontrol->value.enumerated.item[0] =
  2378. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2379. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2380. idx, mi2s_tx_cfg[idx].sample_rate,
  2381. ucontrol->value.enumerated.item[0]);
  2382. return 0;
  2383. }
  2384. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2385. struct snd_ctl_elem_value *ucontrol)
  2386. {
  2387. int idx = mi2s_get_port_idx(kcontrol);
  2388. if (idx < 0)
  2389. return idx;
  2390. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2391. idx, mi2s_rx_cfg[idx].channels);
  2392. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2393. return 0;
  2394. }
  2395. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2396. struct snd_ctl_elem_value *ucontrol)
  2397. {
  2398. int idx = mi2s_get_port_idx(kcontrol);
  2399. if (idx < 0)
  2400. return idx;
  2401. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2402. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2403. idx, mi2s_rx_cfg[idx].channels);
  2404. return 1;
  2405. }
  2406. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2407. struct snd_ctl_elem_value *ucontrol)
  2408. {
  2409. int idx = mi2s_get_port_idx(kcontrol);
  2410. if (idx < 0)
  2411. return idx;
  2412. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2413. idx, mi2s_tx_cfg[idx].channels);
  2414. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2415. return 0;
  2416. }
  2417. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2418. struct snd_ctl_elem_value *ucontrol)
  2419. {
  2420. int idx = mi2s_get_port_idx(kcontrol);
  2421. if (idx < 0)
  2422. return idx;
  2423. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2424. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2425. idx, mi2s_tx_cfg[idx].channels);
  2426. return 1;
  2427. }
  2428. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2429. struct snd_ctl_elem_value *ucontrol)
  2430. {
  2431. int idx = mi2s_get_port_idx(kcontrol);
  2432. if (idx < 0)
  2433. return idx;
  2434. ucontrol->value.enumerated.item[0] =
  2435. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2436. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2437. idx, mi2s_rx_cfg[idx].bit_format,
  2438. ucontrol->value.enumerated.item[0]);
  2439. return 0;
  2440. }
  2441. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2442. struct snd_ctl_elem_value *ucontrol)
  2443. {
  2444. int idx = mi2s_get_port_idx(kcontrol);
  2445. if (idx < 0)
  2446. return idx;
  2447. mi2s_rx_cfg[idx].bit_format =
  2448. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2449. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2450. idx, mi2s_rx_cfg[idx].bit_format,
  2451. ucontrol->value.enumerated.item[0]);
  2452. return 0;
  2453. }
  2454. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2455. struct snd_ctl_elem_value *ucontrol)
  2456. {
  2457. int idx = mi2s_get_port_idx(kcontrol);
  2458. if (idx < 0)
  2459. return idx;
  2460. ucontrol->value.enumerated.item[0] =
  2461. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2462. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2463. idx, mi2s_tx_cfg[idx].bit_format,
  2464. ucontrol->value.enumerated.item[0]);
  2465. return 0;
  2466. }
  2467. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2468. struct snd_ctl_elem_value *ucontrol)
  2469. {
  2470. int idx = mi2s_get_port_idx(kcontrol);
  2471. if (idx < 0)
  2472. return idx;
  2473. mi2s_tx_cfg[idx].bit_format =
  2474. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2475. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2476. idx, mi2s_tx_cfg[idx].bit_format,
  2477. ucontrol->value.enumerated.item[0]);
  2478. return 0;
  2479. }
  2480. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2481. struct snd_ctl_elem_value *ucontrol)
  2482. {
  2483. int idx = aux_pcm_get_port_idx(kcontrol);
  2484. if (idx < 0)
  2485. return idx;
  2486. ucontrol->value.enumerated.item[0] =
  2487. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2488. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2489. idx, aux_pcm_rx_cfg[idx].bit_format,
  2490. ucontrol->value.enumerated.item[0]);
  2491. return 0;
  2492. }
  2493. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2494. struct snd_ctl_elem_value *ucontrol)
  2495. {
  2496. int idx = aux_pcm_get_port_idx(kcontrol);
  2497. if (idx < 0)
  2498. return idx;
  2499. aux_pcm_rx_cfg[idx].bit_format =
  2500. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2501. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2502. idx, aux_pcm_rx_cfg[idx].bit_format,
  2503. ucontrol->value.enumerated.item[0]);
  2504. return 0;
  2505. }
  2506. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2507. struct snd_ctl_elem_value *ucontrol)
  2508. {
  2509. int idx = aux_pcm_get_port_idx(kcontrol);
  2510. if (idx < 0)
  2511. return idx;
  2512. ucontrol->value.enumerated.item[0] =
  2513. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2514. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2515. idx, aux_pcm_tx_cfg[idx].bit_format,
  2516. ucontrol->value.enumerated.item[0]);
  2517. return 0;
  2518. }
  2519. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2520. struct snd_ctl_elem_value *ucontrol)
  2521. {
  2522. int idx = aux_pcm_get_port_idx(kcontrol);
  2523. if (idx < 0)
  2524. return idx;
  2525. aux_pcm_tx_cfg[idx].bit_format =
  2526. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2527. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2528. idx, aux_pcm_tx_cfg[idx].bit_format,
  2529. ucontrol->value.enumerated.item[0]);
  2530. return 0;
  2531. }
  2532. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2533. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2534. slim_rx_ch_get, slim_rx_ch_put),
  2535. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2536. slim_rx_ch_get, slim_rx_ch_put),
  2537. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2538. slim_tx_ch_get, slim_tx_ch_put),
  2539. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2540. slim_tx_ch_get, slim_tx_ch_put),
  2541. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2542. slim_rx_ch_get, slim_rx_ch_put),
  2543. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2544. slim_rx_ch_get, slim_rx_ch_put),
  2545. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2546. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2547. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2548. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2549. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2550. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2551. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2552. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2553. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2554. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2555. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2556. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2557. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2558. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2559. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2560. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2561. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2562. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2563. };
  2564. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2565. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2566. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2567. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2568. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2569. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2570. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2571. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2572. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2573. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2574. va_cdc_dma_tx_0_sample_rate,
  2575. cdc_dma_tx_sample_rate_get,
  2576. cdc_dma_tx_sample_rate_put),
  2577. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2578. va_cdc_dma_tx_1_sample_rate,
  2579. cdc_dma_tx_sample_rate_get,
  2580. cdc_dma_tx_sample_rate_put),
  2581. };
  2582. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2583. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2584. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2585. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2586. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2587. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2588. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2589. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2590. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2591. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2592. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2593. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2594. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2595. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2596. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2597. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2598. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2599. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2600. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2601. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2602. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2603. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2604. wsa_cdc_dma_rx_0_sample_rate,
  2605. cdc_dma_rx_sample_rate_get,
  2606. cdc_dma_rx_sample_rate_put),
  2607. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2608. wsa_cdc_dma_rx_1_sample_rate,
  2609. cdc_dma_rx_sample_rate_get,
  2610. cdc_dma_rx_sample_rate_put),
  2611. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2612. wsa_cdc_dma_tx_0_sample_rate,
  2613. cdc_dma_tx_sample_rate_get,
  2614. cdc_dma_tx_sample_rate_put),
  2615. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2616. wsa_cdc_dma_tx_1_sample_rate,
  2617. cdc_dma_tx_sample_rate_get,
  2618. cdc_dma_tx_sample_rate_put),
  2619. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2620. wsa_cdc_dma_tx_2_sample_rate,
  2621. cdc_dma_tx_sample_rate_get,
  2622. cdc_dma_tx_sample_rate_put),
  2623. };
  2624. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2625. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2626. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2627. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2628. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2629. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2630. proxy_rx_ch_get, proxy_rx_ch_put),
  2631. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2632. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2633. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2634. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2635. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2636. msm_bt_sample_rate_get,
  2637. msm_bt_sample_rate_put),
  2638. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2639. usb_audio_rx_sample_rate_get,
  2640. usb_audio_rx_sample_rate_put),
  2641. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2642. usb_audio_tx_sample_rate_get,
  2643. usb_audio_tx_sample_rate_put),
  2644. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2645. tdm_rx_sample_rate_get,
  2646. tdm_rx_sample_rate_put),
  2647. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2648. tdm_tx_sample_rate_get,
  2649. tdm_tx_sample_rate_put),
  2650. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2651. tdm_rx_format_get,
  2652. tdm_rx_format_put),
  2653. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2654. tdm_tx_format_get,
  2655. tdm_tx_format_put),
  2656. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2657. tdm_rx_ch_get,
  2658. tdm_rx_ch_put),
  2659. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2660. tdm_tx_ch_get,
  2661. tdm_tx_ch_put),
  2662. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2663. tdm_rx_sample_rate_get,
  2664. tdm_rx_sample_rate_put),
  2665. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2666. tdm_tx_sample_rate_get,
  2667. tdm_tx_sample_rate_put),
  2668. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2669. tdm_rx_format_get,
  2670. tdm_rx_format_put),
  2671. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2672. tdm_tx_format_get,
  2673. tdm_tx_format_put),
  2674. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2675. tdm_rx_ch_get,
  2676. tdm_rx_ch_put),
  2677. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2678. tdm_tx_ch_get,
  2679. tdm_tx_ch_put),
  2680. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2681. tdm_rx_sample_rate_get,
  2682. tdm_rx_sample_rate_put),
  2683. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2684. tdm_tx_sample_rate_get,
  2685. tdm_tx_sample_rate_put),
  2686. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2687. tdm_rx_format_get,
  2688. tdm_rx_format_put),
  2689. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2690. tdm_tx_format_get,
  2691. tdm_tx_format_put),
  2692. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  2693. tdm_rx_ch_get,
  2694. tdm_rx_ch_put),
  2695. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  2696. tdm_tx_ch_get,
  2697. tdm_tx_ch_put),
  2698. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2699. tdm_rx_sample_rate_get,
  2700. tdm_rx_sample_rate_put),
  2701. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2702. tdm_tx_sample_rate_get,
  2703. tdm_tx_sample_rate_put),
  2704. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  2705. tdm_rx_format_get,
  2706. tdm_rx_format_put),
  2707. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  2708. tdm_tx_format_get,
  2709. tdm_tx_format_put),
  2710. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  2711. tdm_rx_ch_get,
  2712. tdm_rx_ch_put),
  2713. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  2714. tdm_tx_ch_get,
  2715. tdm_tx_ch_put),
  2716. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2717. tdm_rx_sample_rate_get,
  2718. tdm_rx_sample_rate_put),
  2719. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2720. tdm_tx_sample_rate_get,
  2721. tdm_tx_sample_rate_put),
  2722. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  2723. tdm_rx_format_get,
  2724. tdm_rx_format_put),
  2725. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  2726. tdm_tx_format_get,
  2727. tdm_tx_format_put),
  2728. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  2729. tdm_rx_ch_get,
  2730. tdm_rx_ch_put),
  2731. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  2732. tdm_tx_ch_get,
  2733. tdm_tx_ch_put),
  2734. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2735. aux_pcm_rx_sample_rate_get,
  2736. aux_pcm_rx_sample_rate_put),
  2737. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  2738. aux_pcm_rx_sample_rate_get,
  2739. aux_pcm_rx_sample_rate_put),
  2740. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  2741. aux_pcm_rx_sample_rate_get,
  2742. aux_pcm_rx_sample_rate_put),
  2743. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  2744. aux_pcm_rx_sample_rate_get,
  2745. aux_pcm_rx_sample_rate_put),
  2746. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  2747. aux_pcm_rx_sample_rate_get,
  2748. aux_pcm_rx_sample_rate_put),
  2749. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2750. aux_pcm_tx_sample_rate_get,
  2751. aux_pcm_tx_sample_rate_put),
  2752. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  2753. aux_pcm_tx_sample_rate_get,
  2754. aux_pcm_tx_sample_rate_put),
  2755. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  2756. aux_pcm_tx_sample_rate_get,
  2757. aux_pcm_tx_sample_rate_put),
  2758. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  2759. aux_pcm_tx_sample_rate_get,
  2760. aux_pcm_tx_sample_rate_put),
  2761. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  2762. aux_pcm_tx_sample_rate_get,
  2763. aux_pcm_tx_sample_rate_put),
  2764. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  2765. mi2s_rx_sample_rate_get,
  2766. mi2s_rx_sample_rate_put),
  2767. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  2768. mi2s_rx_sample_rate_get,
  2769. mi2s_rx_sample_rate_put),
  2770. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  2771. mi2s_rx_sample_rate_get,
  2772. mi2s_rx_sample_rate_put),
  2773. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  2774. mi2s_rx_sample_rate_get,
  2775. mi2s_rx_sample_rate_put),
  2776. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  2777. mi2s_rx_sample_rate_get,
  2778. mi2s_rx_sample_rate_put),
  2779. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  2780. mi2s_tx_sample_rate_get,
  2781. mi2s_tx_sample_rate_put),
  2782. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  2783. mi2s_tx_sample_rate_get,
  2784. mi2s_tx_sample_rate_put),
  2785. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  2786. mi2s_tx_sample_rate_get,
  2787. mi2s_tx_sample_rate_put),
  2788. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  2789. mi2s_tx_sample_rate_get,
  2790. mi2s_tx_sample_rate_put),
  2791. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  2792. mi2s_tx_sample_rate_get,
  2793. mi2s_tx_sample_rate_put),
  2794. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  2795. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2796. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  2797. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2798. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  2799. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2800. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  2801. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2802. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  2803. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2804. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  2805. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2806. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  2807. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2808. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  2809. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2810. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  2811. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2812. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  2813. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2814. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  2815. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2816. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  2817. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2818. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  2819. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2820. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  2821. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2822. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  2823. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2824. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  2825. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2826. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  2827. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2828. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  2829. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2830. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  2831. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2832. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  2833. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2834. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2835. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2836. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2837. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2838. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  2839. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2840. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  2841. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2842. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2843. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2844. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2845. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2846. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2847. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2848. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2849. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2850. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  2851. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2852. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  2853. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2854. };
  2855. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  2856. int enable, bool dapm)
  2857. {
  2858. int ret = 0;
  2859. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2860. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  2861. } else {
  2862. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  2863. __func__);
  2864. ret = -EINVAL;
  2865. }
  2866. return ret;
  2867. }
  2868. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  2869. int enable, bool dapm)
  2870. {
  2871. int ret = 0;
  2872. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2873. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  2874. } else {
  2875. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  2876. __func__);
  2877. ret = -EINVAL;
  2878. }
  2879. return ret;
  2880. }
  2881. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  2882. struct snd_kcontrol *kcontrol, int event)
  2883. {
  2884. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2885. pr_debug("%s: event = %d\n", __func__, event);
  2886. switch (event) {
  2887. case SND_SOC_DAPM_PRE_PMU:
  2888. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  2889. case SND_SOC_DAPM_POST_PMD:
  2890. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  2891. }
  2892. return 0;
  2893. }
  2894. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  2895. struct snd_kcontrol *kcontrol, int event)
  2896. {
  2897. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2898. pr_debug("%s: event = %d\n", __func__, event);
  2899. switch (event) {
  2900. case SND_SOC_DAPM_PRE_PMU:
  2901. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  2902. case SND_SOC_DAPM_POST_PMD:
  2903. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  2904. }
  2905. return 0;
  2906. }
  2907. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  2908. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  2909. msm_mclk_event,
  2910. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2911. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  2912. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2913. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  2914. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  2915. };
  2916. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  2917. struct snd_kcontrol *kcontrol, int event)
  2918. {
  2919. struct msm_asoc_mach_data *pdata = NULL;
  2920. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2921. int ret = 0;
  2922. uint32_t dmic_idx;
  2923. int *dmic_gpio_cnt;
  2924. struct device_node *dmic_gpio;
  2925. char *wname;
  2926. wname = strpbrk(w->name, "01234567");
  2927. if (!wname) {
  2928. dev_err(codec->dev, "%s: widget not found\n", __func__);
  2929. return -EINVAL;
  2930. }
  2931. ret = kstrtouint(wname, 10, &dmic_idx);
  2932. if (ret < 0) {
  2933. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  2934. __func__);
  2935. return -EINVAL;
  2936. }
  2937. pdata = snd_soc_card_get_drvdata(codec->component.card);
  2938. switch (dmic_idx) {
  2939. case 0:
  2940. case 1:
  2941. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  2942. dmic_gpio = pdata->dmic_01_gpio_p;
  2943. break;
  2944. case 2:
  2945. case 3:
  2946. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  2947. dmic_gpio = pdata->dmic_23_gpio_p;
  2948. break;
  2949. case 4:
  2950. case 5:
  2951. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  2952. dmic_gpio = pdata->dmic_45_gpio_p;
  2953. break;
  2954. case 6:
  2955. case 7:
  2956. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  2957. dmic_gpio = pdata->dmic_67_gpio_p;
  2958. break;
  2959. default:
  2960. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  2961. __func__);
  2962. return -EINVAL;
  2963. }
  2964. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  2965. __func__, event, dmic_idx, *dmic_gpio_cnt);
  2966. switch (event) {
  2967. case SND_SOC_DAPM_PRE_PMU:
  2968. (*dmic_gpio_cnt)++;
  2969. if (*dmic_gpio_cnt == 1) {
  2970. ret = msm_cdc_pinctrl_select_active_state(
  2971. dmic_gpio);
  2972. if (ret < 0) {
  2973. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  2974. __func__, "dmic_gpio");
  2975. return ret;
  2976. }
  2977. }
  2978. break;
  2979. case SND_SOC_DAPM_POST_PMD:
  2980. (*dmic_gpio_cnt)--;
  2981. if (*dmic_gpio_cnt == 0) {
  2982. ret = msm_cdc_pinctrl_select_sleep_state(
  2983. dmic_gpio);
  2984. if (ret < 0) {
  2985. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  2986. __func__, "dmic_gpio");
  2987. return ret;
  2988. }
  2989. }
  2990. break;
  2991. default:
  2992. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  2993. __func__, event);
  2994. return -EINVAL;
  2995. }
  2996. return 0;
  2997. }
  2998. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  2999. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3000. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3001. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3002. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3003. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3004. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3005. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3006. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3007. };
  3008. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3009. };
  3010. static inline int param_is_mask(int p)
  3011. {
  3012. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3013. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3014. }
  3015. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3016. int n)
  3017. {
  3018. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3019. }
  3020. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3021. unsigned int bit)
  3022. {
  3023. if (bit >= SNDRV_MASK_MAX)
  3024. return;
  3025. if (param_is_mask(n)) {
  3026. struct snd_mask *m = param_to_mask(p, n);
  3027. m->bits[0] = 0;
  3028. m->bits[1] = 0;
  3029. m->bits[bit >> 5] |= (1 << (bit & 31));
  3030. }
  3031. }
  3032. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3033. {
  3034. int ch_id = 0;
  3035. switch (be_id) {
  3036. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3037. ch_id = SLIM_RX_0;
  3038. break;
  3039. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3040. ch_id = SLIM_RX_1;
  3041. break;
  3042. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3043. ch_id = SLIM_RX_2;
  3044. break;
  3045. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3046. ch_id = SLIM_RX_3;
  3047. break;
  3048. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3049. ch_id = SLIM_RX_4;
  3050. break;
  3051. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3052. ch_id = SLIM_RX_6;
  3053. break;
  3054. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3055. ch_id = SLIM_TX_0;
  3056. break;
  3057. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3058. ch_id = SLIM_TX_3;
  3059. break;
  3060. default:
  3061. ch_id = SLIM_RX_0;
  3062. break;
  3063. }
  3064. return ch_id;
  3065. }
  3066. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3067. {
  3068. int idx = 0;
  3069. switch (be_id) {
  3070. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3071. idx = WSA_CDC_DMA_RX_0;
  3072. break;
  3073. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3074. idx = WSA_CDC_DMA_TX_0;
  3075. break;
  3076. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3077. idx = WSA_CDC_DMA_RX_1;
  3078. break;
  3079. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3080. idx = WSA_CDC_DMA_TX_1;
  3081. break;
  3082. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3083. idx = WSA_CDC_DMA_TX_2;
  3084. break;
  3085. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3086. idx = VA_CDC_DMA_TX_0;
  3087. break;
  3088. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3089. idx = VA_CDC_DMA_TX_1;
  3090. break;
  3091. default:
  3092. idx = VA_CDC_DMA_TX_0;
  3093. break;
  3094. }
  3095. return idx;
  3096. }
  3097. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3098. struct snd_pcm_hw_params *params)
  3099. {
  3100. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3101. struct snd_interval *rate = hw_param_interval(params,
  3102. SNDRV_PCM_HW_PARAM_RATE);
  3103. struct snd_interval *channels = hw_param_interval(params,
  3104. SNDRV_PCM_HW_PARAM_CHANNELS);
  3105. int rc = 0;
  3106. int idx;
  3107. void *config = NULL;
  3108. struct snd_soc_codec *codec = NULL;
  3109. pr_debug("%s: format = %d, rate = %d\n",
  3110. __func__, params_format(params), params_rate(params));
  3111. switch (dai_link->id) {
  3112. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3113. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3114. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3115. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3116. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3117. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3118. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3119. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3120. slim_rx_cfg[idx].bit_format);
  3121. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3122. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3123. break;
  3124. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3125. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3126. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3127. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3128. slim_tx_cfg[idx].bit_format);
  3129. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3130. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3131. break;
  3132. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3133. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3134. slim_tx_cfg[1].bit_format);
  3135. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3136. channels->min = channels->max = slim_tx_cfg[1].channels;
  3137. break;
  3138. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3139. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3140. SNDRV_PCM_FORMAT_S32_LE);
  3141. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3142. channels->min = channels->max = msm_vi_feed_tx_ch;
  3143. break;
  3144. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3145. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3146. slim_rx_cfg[5].bit_format);
  3147. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3148. channels->min = channels->max = slim_rx_cfg[5].channels;
  3149. break;
  3150. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3151. codec = rtd->codec;
  3152. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3153. channels->min = channels->max = 1;
  3154. config = msm_codec_fn.get_afe_config_fn(codec,
  3155. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3156. if (config) {
  3157. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3158. config, SLIMBUS_5_TX);
  3159. if (rc)
  3160. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3161. __func__, rc);
  3162. }
  3163. break;
  3164. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3165. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3166. slim_rx_cfg[SLIM_RX_7].bit_format);
  3167. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3168. channels->min = channels->max =
  3169. slim_rx_cfg[SLIM_RX_7].channels;
  3170. break;
  3171. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3172. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3173. channels->min = channels->max =
  3174. slim_tx_cfg[SLIM_TX_7].channels;
  3175. break;
  3176. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3177. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3178. channels->min = channels->max =
  3179. slim_tx_cfg[SLIM_TX_8].channels;
  3180. break;
  3181. case MSM_BACKEND_DAI_USB_RX:
  3182. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3183. usb_rx_cfg.bit_format);
  3184. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3185. channels->min = channels->max = usb_rx_cfg.channels;
  3186. break;
  3187. case MSM_BACKEND_DAI_USB_TX:
  3188. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3189. usb_tx_cfg.bit_format);
  3190. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3191. channels->min = channels->max = usb_tx_cfg.channels;
  3192. break;
  3193. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3194. channels->min = channels->max = proxy_rx_cfg.channels;
  3195. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3196. break;
  3197. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3198. channels->min = channels->max =
  3199. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3200. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3201. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3202. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3203. break;
  3204. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3205. channels->min = channels->max =
  3206. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3207. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3208. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3209. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3210. break;
  3211. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3212. channels->min = channels->max =
  3213. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3214. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3215. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3216. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3217. break;
  3218. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3219. channels->min = channels->max =
  3220. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3221. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3222. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3223. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3224. break;
  3225. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3226. channels->min = channels->max =
  3227. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3228. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3229. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3230. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3231. break;
  3232. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3233. channels->min = channels->max =
  3234. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3235. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3236. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3237. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3238. break;
  3239. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3240. channels->min = channels->max =
  3241. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3242. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3243. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3244. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3245. break;
  3246. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3247. channels->min = channels->max =
  3248. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3249. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3250. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3251. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3252. break;
  3253. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3254. channels->min = channels->max =
  3255. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3256. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3257. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3258. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3259. break;
  3260. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3261. channels->min = channels->max =
  3262. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3263. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3264. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3265. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3266. break;
  3267. case MSM_BACKEND_DAI_AUXPCM_RX:
  3268. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3269. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3270. rate->min = rate->max =
  3271. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3272. channels->min = channels->max =
  3273. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3274. break;
  3275. case MSM_BACKEND_DAI_AUXPCM_TX:
  3276. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3277. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3278. rate->min = rate->max =
  3279. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3280. channels->min = channels->max =
  3281. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3282. break;
  3283. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3284. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3285. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3286. rate->min = rate->max =
  3287. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3288. channels->min = channels->max =
  3289. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3290. break;
  3291. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3292. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3293. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3294. rate->min = rate->max =
  3295. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3296. channels->min = channels->max =
  3297. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3298. break;
  3299. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3300. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3301. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3302. rate->min = rate->max =
  3303. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3304. channels->min = channels->max =
  3305. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3306. break;
  3307. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3308. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3309. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3310. rate->min = rate->max =
  3311. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3312. channels->min = channels->max =
  3313. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3314. break;
  3315. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3316. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3317. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3318. rate->min = rate->max =
  3319. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3320. channels->min = channels->max =
  3321. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3322. break;
  3323. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3324. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3325. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3326. rate->min = rate->max =
  3327. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3328. channels->min = channels->max =
  3329. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3330. break;
  3331. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3332. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3333. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3334. rate->min = rate->max =
  3335. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3336. channels->min = channels->max =
  3337. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3338. break;
  3339. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3340. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3341. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3342. rate->min = rate->max =
  3343. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3344. channels->min = channels->max =
  3345. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3346. break;
  3347. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3348. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3349. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3350. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3351. channels->min = channels->max =
  3352. mi2s_rx_cfg[PRIM_MI2S].channels;
  3353. break;
  3354. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3355. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3356. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3357. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3358. channels->min = channels->max =
  3359. mi2s_tx_cfg[PRIM_MI2S].channels;
  3360. break;
  3361. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3362. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3363. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3364. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3365. channels->min = channels->max =
  3366. mi2s_rx_cfg[SEC_MI2S].channels;
  3367. break;
  3368. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3369. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3370. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3371. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3372. channels->min = channels->max =
  3373. mi2s_tx_cfg[SEC_MI2S].channels;
  3374. break;
  3375. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3376. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3377. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3378. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3379. channels->min = channels->max =
  3380. mi2s_rx_cfg[TERT_MI2S].channels;
  3381. break;
  3382. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3383. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3384. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3385. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3386. channels->min = channels->max =
  3387. mi2s_tx_cfg[TERT_MI2S].channels;
  3388. break;
  3389. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3390. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3391. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3392. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3393. channels->min = channels->max =
  3394. mi2s_rx_cfg[QUAT_MI2S].channels;
  3395. break;
  3396. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3397. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3398. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3399. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3400. channels->min = channels->max =
  3401. mi2s_tx_cfg[QUAT_MI2S].channels;
  3402. break;
  3403. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3404. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3405. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3406. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3407. channels->min = channels->max =
  3408. mi2s_rx_cfg[QUIN_MI2S].channels;
  3409. break;
  3410. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3411. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3412. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3413. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3414. channels->min = channels->max =
  3415. mi2s_tx_cfg[QUIN_MI2S].channels;
  3416. break;
  3417. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3418. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3419. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3420. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3421. cdc_dma_rx_cfg[idx].bit_format);
  3422. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3423. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3424. break;
  3425. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3426. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3427. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3428. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3429. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3430. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3431. cdc_dma_tx_cfg[idx].bit_format);
  3432. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3433. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3434. break;
  3435. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3436. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3437. SNDRV_PCM_FORMAT_S32_LE);
  3438. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3439. channels->min = channels->max = msm_vi_feed_tx_ch;
  3440. break;
  3441. default:
  3442. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3443. break;
  3444. }
  3445. return rc;
  3446. }
  3447. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3448. {
  3449. int ret = 0;
  3450. void *config_data = NULL;
  3451. if (!msm_codec_fn.get_afe_config_fn) {
  3452. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3453. __func__);
  3454. return -EINVAL;
  3455. }
  3456. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3457. AFE_CDC_REGISTERS_CONFIG);
  3458. if (config_data) {
  3459. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3460. if (ret) {
  3461. dev_err(codec->dev,
  3462. "%s: Failed to set codec registers config %d\n",
  3463. __func__, ret);
  3464. return ret;
  3465. }
  3466. }
  3467. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3468. AFE_CDC_REGISTER_PAGE_CONFIG);
  3469. if (config_data) {
  3470. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3471. 0);
  3472. if (ret)
  3473. dev_err(codec->dev,
  3474. "%s: Failed to set cdc register page config\n",
  3475. __func__);
  3476. }
  3477. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3478. AFE_SLIMBUS_SLAVE_CONFIG);
  3479. if (config_data) {
  3480. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3481. if (ret) {
  3482. dev_err(codec->dev,
  3483. "%s: Failed to set slimbus slave config %d\n",
  3484. __func__, ret);
  3485. return ret;
  3486. }
  3487. }
  3488. return 0;
  3489. }
  3490. static void msm_afe_clear_config(void)
  3491. {
  3492. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3493. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3494. }
  3495. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3496. struct snd_card *card)
  3497. {
  3498. int ret = 0;
  3499. unsigned long timeout;
  3500. int adsp_ready = 0;
  3501. bool snd_card_online = 0;
  3502. timeout = jiffies +
  3503. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3504. do {
  3505. if (!snd_card_online) {
  3506. snd_card_online = snd_card_is_online_state(card);
  3507. pr_debug("%s: Sound card is %s\n", __func__,
  3508. snd_card_online ? "Online" : "Offline");
  3509. }
  3510. if (!adsp_ready) {
  3511. adsp_ready = q6core_is_adsp_ready();
  3512. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3513. adsp_ready ? "ready" : "not ready");
  3514. }
  3515. if (snd_card_online && adsp_ready)
  3516. break;
  3517. /*
  3518. * Sound card/ADSP will be coming up after subsystem restart and
  3519. * it might not be fully up when the control reaches
  3520. * here. So, wait for 50msec before checking ADSP state
  3521. */
  3522. msleep(50);
  3523. } while (time_after(timeout, jiffies));
  3524. if (!snd_card_online || !adsp_ready) {
  3525. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3526. __func__,
  3527. snd_card_online ? "Online" : "Offline",
  3528. adsp_ready ? "ready" : "not ready");
  3529. ret = -ETIMEDOUT;
  3530. goto err;
  3531. }
  3532. ret = msm_afe_set_config(codec);
  3533. if (ret)
  3534. pr_err("%s: Failed to set AFE config. err %d\n",
  3535. __func__, ret);
  3536. return 0;
  3537. err:
  3538. return ret;
  3539. }
  3540. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3541. unsigned long opcode, void *ptr)
  3542. {
  3543. int ret;
  3544. struct snd_soc_card *card = NULL;
  3545. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3546. struct snd_soc_pcm_runtime *rtd;
  3547. struct snd_soc_codec *codec;
  3548. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3549. switch (opcode) {
  3550. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3551. /*
  3552. * Use flag to ignore initial boot notifications
  3553. * On initial boot msm_adsp_power_up_config is
  3554. * called on init. There is no need to clear
  3555. * and set the config again on initial boot.
  3556. */
  3557. if (is_initial_boot)
  3558. break;
  3559. msm_afe_clear_config();
  3560. break;
  3561. case AUDIO_NOTIFIER_SERVICE_UP:
  3562. if (is_initial_boot) {
  3563. is_initial_boot = false;
  3564. break;
  3565. }
  3566. if (!spdev)
  3567. return -EINVAL;
  3568. card = platform_get_drvdata(spdev);
  3569. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3570. if (!rtd) {
  3571. dev_err(card->dev,
  3572. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3573. __func__, be_dl_name);
  3574. ret = -EINVAL;
  3575. goto err;
  3576. }
  3577. codec = rtd->codec;
  3578. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3579. if (ret < 0) {
  3580. dev_err(card->dev,
  3581. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3582. __func__, ret);
  3583. goto err;
  3584. }
  3585. break;
  3586. default:
  3587. break;
  3588. }
  3589. err:
  3590. return NOTIFY_OK;
  3591. }
  3592. static struct notifier_block service_nb = {
  3593. .notifier_call = qcs405_notifier_service_cb,
  3594. .priority = -INT_MAX,
  3595. };
  3596. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3597. {
  3598. int ret = 0;
  3599. void *config_data;
  3600. struct snd_soc_codec *codec = rtd->codec;
  3601. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3602. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3603. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3604. struct snd_card *card;
  3605. struct snd_info_entry *entry;
  3606. struct msm_asoc_mach_data *pdata =
  3607. snd_soc_card_get_drvdata(rtd->card);
  3608. /*
  3609. * Codec SLIMBUS configuration
  3610. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  3611. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  3612. * TX14, TX15, TX16
  3613. */
  3614. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  3615. 151, 152, 153, 154, 155, 156};
  3616. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  3617. 134, 135, 136, 137, 138, 139,
  3618. 140, 141, 142, 143};
  3619. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  3620. rtd->pmdown_time = 0;
  3621. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  3622. ARRAY_SIZE(msm_snd_sb_controls));
  3623. if (ret < 0) {
  3624. pr_err("%s: add_codec_controls failed, err %d\n",
  3625. __func__, ret);
  3626. return ret;
  3627. }
  3628. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  3629. ARRAY_SIZE(msm_dapm_widgets));
  3630. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  3631. ARRAY_SIZE(wcd_audio_paths));
  3632. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  3633. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  3634. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  3635. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  3636. snd_soc_dapm_sync(dapm);
  3637. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3638. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3639. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  3640. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  3641. if (ret) {
  3642. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  3643. __func__, ret);
  3644. goto err;
  3645. }
  3646. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3647. AFE_AANC_VERSION);
  3648. if (config_data) {
  3649. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  3650. if (ret) {
  3651. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  3652. __func__, ret);
  3653. goto err;
  3654. }
  3655. }
  3656. card = rtd->card->snd_card;
  3657. entry = snd_info_create_subdir(card->module, "codecs",
  3658. card->proc_root);
  3659. if (!entry) {
  3660. pr_debug("%s: Cannot create codecs module entry\n",
  3661. __func__);
  3662. ret = 0;
  3663. goto err;
  3664. }
  3665. pdata->codec_root = entry;
  3666. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  3667. codec_reg_done = true;
  3668. return 0;
  3669. err:
  3670. return ret;
  3671. }
  3672. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3673. {
  3674. int ret = 0;
  3675. struct snd_soc_codec *codec = rtd->codec;
  3676. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3677. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  3678. ARRAY_SIZE(msm_snd_va_controls));
  3679. if (ret < 0) {
  3680. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3681. __func__, ret);
  3682. return ret;
  3683. }
  3684. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  3685. ARRAY_SIZE(msm_va_dapm_widgets));
  3686. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  3687. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  3688. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  3689. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  3690. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  3691. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  3692. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  3693. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  3694. snd_soc_dapm_sync(dapm);
  3695. return ret;
  3696. }
  3697. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3698. {
  3699. int ret = 0;
  3700. struct snd_soc_codec *codec = rtd->codec;
  3701. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3702. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  3703. ARRAY_SIZE(msm_snd_wsa_controls));
  3704. if (ret < 0) {
  3705. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3706. __func__, ret);
  3707. return ret;
  3708. }
  3709. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  3710. ARRAY_SIZE(msm_wsa_dapm_widgets));
  3711. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  3712. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  3713. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  3714. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  3715. snd_soc_dapm_sync(dapm);
  3716. return ret;
  3717. }
  3718. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  3719. {
  3720. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3721. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  3722. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3723. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3724. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3725. }
  3726. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  3727. struct snd_pcm_hw_params *params)
  3728. {
  3729. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3730. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3731. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3732. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3733. int ret = 0;
  3734. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3735. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3736. u32 user_set_tx_ch = 0;
  3737. u32 rx_ch_count;
  3738. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3739. ret = snd_soc_dai_get_channel_map(codec_dai,
  3740. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3741. if (ret < 0) {
  3742. pr_err("%s: failed to get codec chan map, err:%d\n",
  3743. __func__, ret);
  3744. goto err;
  3745. }
  3746. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  3747. pr_debug("%s: rx_5_ch=%d\n", __func__,
  3748. slim_rx_cfg[5].channels);
  3749. rx_ch_count = slim_rx_cfg[5].channels;
  3750. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  3751. pr_debug("%s: rx_2_ch=%d\n", __func__,
  3752. slim_rx_cfg[2].channels);
  3753. rx_ch_count = slim_rx_cfg[2].channels;
  3754. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  3755. pr_debug("%s: rx_6_ch=%d\n", __func__,
  3756. slim_rx_cfg[6].channels);
  3757. rx_ch_count = slim_rx_cfg[6].channels;
  3758. } else {
  3759. pr_debug("%s: rx_0_ch=%d\n", __func__,
  3760. slim_rx_cfg[0].channels);
  3761. rx_ch_count = slim_rx_cfg[0].channels;
  3762. }
  3763. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3764. rx_ch_count, rx_ch);
  3765. if (ret < 0) {
  3766. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3767. __func__, ret);
  3768. goto err;
  3769. }
  3770. } else {
  3771. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  3772. codec_dai->name, codec_dai->id, user_set_tx_ch);
  3773. ret = snd_soc_dai_get_channel_map(codec_dai,
  3774. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3775. if (ret < 0) {
  3776. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3777. __func__, ret);
  3778. goto err;
  3779. }
  3780. /* For <codec>_tx1 case */
  3781. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  3782. user_set_tx_ch = slim_tx_cfg[0].channels;
  3783. /* For <codec>_tx3 case */
  3784. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  3785. user_set_tx_ch = slim_tx_cfg[1].channels;
  3786. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  3787. user_set_tx_ch = msm_vi_feed_tx_ch;
  3788. else
  3789. user_set_tx_ch = tx_ch_cnt;
  3790. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  3791. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  3792. tx_ch_cnt, dai_link->id);
  3793. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3794. user_set_tx_ch, tx_ch, 0, 0);
  3795. if (ret < 0)
  3796. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3797. __func__, ret);
  3798. }
  3799. err:
  3800. return ret;
  3801. }
  3802. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3803. struct snd_pcm_hw_params *params)
  3804. {
  3805. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3806. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3807. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3808. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3809. int ret = 0;
  3810. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3811. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3812. u32 user_set_tx_ch = 0;
  3813. u32 user_set_rx_ch = 0;
  3814. u32 ch_id;
  3815. ret = snd_soc_dai_get_channel_map(codec_dai,
  3816. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3817. &rx_ch_cdc_dma);
  3818. if (ret < 0) {
  3819. pr_err("%s: failed to get codec chan map, err:%d\n",
  3820. __func__, ret);
  3821. goto err;
  3822. }
  3823. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3824. switch (dai_link->id) {
  3825. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3826. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3827. {
  3828. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3829. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3830. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3831. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3832. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3833. user_set_rx_ch, &rx_ch_cdc_dma);
  3834. if (ret < 0) {
  3835. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3836. __func__, ret);
  3837. goto err;
  3838. }
  3839. }
  3840. break;
  3841. }
  3842. } else {
  3843. switch (dai_link->id) {
  3844. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3845. {
  3846. user_set_tx_ch = msm_vi_feed_tx_ch;
  3847. }
  3848. break;
  3849. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3850. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3851. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3852. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3853. {
  3854. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3855. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3856. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3857. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3858. }
  3859. break;
  3860. }
  3861. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3862. &tx_ch_cdc_dma, 0, 0);
  3863. if (ret < 0) {
  3864. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3865. __func__, ret);
  3866. goto err;
  3867. }
  3868. }
  3869. err:
  3870. return ret;
  3871. }
  3872. static int msm_slimbus_2_hw_params(struct snd_pcm_substream *substream,
  3873. struct snd_pcm_hw_params *params)
  3874. {
  3875. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3876. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3877. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3878. unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3879. unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0;
  3880. unsigned int num_tx_ch = 0;
  3881. unsigned int num_rx_ch = 0;
  3882. int ret = 0;
  3883. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3884. num_rx_ch = params_channels(params);
  3885. pr_debug("%s: %s rx_dai_id = %d num_ch = %d\n", __func__,
  3886. codec_dai->name, codec_dai->id, num_rx_ch);
  3887. ret = snd_soc_dai_get_channel_map(codec_dai,
  3888. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3889. if (ret < 0) {
  3890. pr_err("%s: failed to get codec chan map, err:%d\n",
  3891. __func__, ret);
  3892. goto err;
  3893. }
  3894. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3895. num_rx_ch, rx_ch);
  3896. if (ret < 0) {
  3897. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3898. __func__, ret);
  3899. goto err;
  3900. }
  3901. } else {
  3902. num_tx_ch = params_channels(params);
  3903. pr_debug("%s: %s tx_dai_id = %d num_ch = %d\n", __func__,
  3904. codec_dai->name, codec_dai->id, num_tx_ch);
  3905. ret = snd_soc_dai_get_channel_map(codec_dai,
  3906. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3907. if (ret < 0) {
  3908. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3909. __func__, ret);
  3910. goto err;
  3911. }
  3912. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3913. num_tx_ch, tx_ch, 0, 0);
  3914. if (ret < 0) {
  3915. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3916. __func__, ret);
  3917. goto err;
  3918. }
  3919. }
  3920. err:
  3921. return ret;
  3922. }
  3923. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  3924. struct snd_pcm_hw_params *params)
  3925. {
  3926. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3927. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3928. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3929. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3930. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  3931. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3932. int ret;
  3933. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3934. codec_dai->name, codec_dai->id);
  3935. ret = snd_soc_dai_get_channel_map(codec_dai,
  3936. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3937. if (ret) {
  3938. dev_err(rtd->dev,
  3939. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3940. __func__, ret);
  3941. goto err;
  3942. }
  3943. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3944. __func__, tx_ch_cnt, dai_link->id);
  3945. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3946. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3947. if (ret)
  3948. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3949. __func__, ret);
  3950. err:
  3951. return ret;
  3952. }
  3953. static int msm_get_port_id(int be_id)
  3954. {
  3955. int afe_port_id;
  3956. switch (be_id) {
  3957. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3958. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  3959. break;
  3960. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3961. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  3962. break;
  3963. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3964. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  3965. break;
  3966. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3967. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  3968. break;
  3969. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3970. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  3971. break;
  3972. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3973. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  3974. break;
  3975. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3976. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  3977. break;
  3978. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3979. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  3980. break;
  3981. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3982. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  3983. break;
  3984. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3985. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3986. break;
  3987. default:
  3988. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  3989. afe_port_id = -EINVAL;
  3990. }
  3991. return afe_port_id;
  3992. }
  3993. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  3994. {
  3995. u32 bit_per_sample;
  3996. switch (bit_format) {
  3997. case SNDRV_PCM_FORMAT_S32_LE:
  3998. case SNDRV_PCM_FORMAT_S24_3LE:
  3999. case SNDRV_PCM_FORMAT_S24_LE:
  4000. bit_per_sample = 32;
  4001. break;
  4002. case SNDRV_PCM_FORMAT_S16_LE:
  4003. default:
  4004. bit_per_sample = 16;
  4005. break;
  4006. }
  4007. return bit_per_sample;
  4008. }
  4009. static void update_mi2s_clk_val(int dai_id, int stream)
  4010. {
  4011. u32 bit_per_sample;
  4012. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4013. bit_per_sample =
  4014. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4015. mi2s_clk[dai_id].clk_freq_in_hz =
  4016. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4017. } else {
  4018. bit_per_sample =
  4019. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4020. mi2s_clk[dai_id].clk_freq_in_hz =
  4021. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4022. }
  4023. }
  4024. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4025. {
  4026. int ret = 0;
  4027. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4028. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4029. int port_id = 0;
  4030. int index = cpu_dai->id;
  4031. port_id = msm_get_port_id(rtd->dai_link->id);
  4032. if (port_id < 0) {
  4033. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4034. ret = port_id;
  4035. goto err;
  4036. }
  4037. if (enable) {
  4038. update_mi2s_clk_val(index, substream->stream);
  4039. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4040. mi2s_clk[index].clk_freq_in_hz);
  4041. }
  4042. mi2s_clk[index].enable = enable;
  4043. ret = afe_set_lpass_clock_v2(port_id,
  4044. &mi2s_clk[index]);
  4045. if (ret < 0) {
  4046. dev_err(rtd->card->dev,
  4047. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4048. __func__, port_id, ret);
  4049. goto err;
  4050. }
  4051. err:
  4052. return ret;
  4053. }
  4054. static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
  4055. enum pinctrl_pin_state new_state)
  4056. {
  4057. int ret = 0;
  4058. int curr_state = 0;
  4059. if (pinctrl_info == NULL) {
  4060. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4061. ret = -EINVAL;
  4062. goto err;
  4063. }
  4064. if (pinctrl_info->pinctrl == NULL) {
  4065. pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
  4066. ret = -EINVAL;
  4067. goto err;
  4068. }
  4069. curr_state = pinctrl_info->curr_state;
  4070. pinctrl_info->curr_state = new_state;
  4071. pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
  4072. pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
  4073. if (curr_state == pinctrl_info->curr_state) {
  4074. pr_debug("%s: Already in same state\n", __func__);
  4075. goto err;
  4076. }
  4077. if (curr_state != STATE_DISABLE &&
  4078. pinctrl_info->curr_state != STATE_DISABLE) {
  4079. pr_debug("%s: state already active cannot switch\n", __func__);
  4080. ret = -EIO;
  4081. goto err;
  4082. }
  4083. switch (pinctrl_info->curr_state) {
  4084. case STATE_MI2S_ACTIVE:
  4085. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4086. pinctrl_info->mi2s_active);
  4087. if (ret) {
  4088. pr_err("%s: MI2S state select failed with %d\n",
  4089. __func__, ret);
  4090. ret = -EIO;
  4091. goto err;
  4092. }
  4093. break;
  4094. case STATE_TDM_ACTIVE:
  4095. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4096. pinctrl_info->tdm_active);
  4097. if (ret) {
  4098. pr_err("%s: TDM state select failed with %d\n",
  4099. __func__, ret);
  4100. ret = -EIO;
  4101. goto err;
  4102. }
  4103. break;
  4104. case STATE_DISABLE:
  4105. if (curr_state == STATE_MI2S_ACTIVE) {
  4106. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4107. pinctrl_info->mi2s_disable);
  4108. } else {
  4109. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4110. pinctrl_info->tdm_disable);
  4111. }
  4112. if (ret) {
  4113. pr_err("%s: state disable failed with %d\n",
  4114. __func__, ret);
  4115. ret = -EIO;
  4116. goto err;
  4117. }
  4118. break;
  4119. default:
  4120. pr_err("%s: TLMM pin state is invalid\n", __func__);
  4121. return -EINVAL;
  4122. }
  4123. err:
  4124. return ret;
  4125. }
  4126. static void msm_release_pinctrl(struct platform_device *pdev)
  4127. {
  4128. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4129. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4130. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4131. if (pinctrl_info->pinctrl) {
  4132. devm_pinctrl_put(pinctrl_info->pinctrl);
  4133. pinctrl_info->pinctrl = NULL;
  4134. }
  4135. }
  4136. static int msm_get_pinctrl(struct platform_device *pdev)
  4137. {
  4138. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4139. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4140. struct msm_pinctrl_info *pinctrl_info = NULL;
  4141. struct pinctrl *pinctrl;
  4142. int ret;
  4143. pinctrl_info = &pdata->pinctrl_info;
  4144. if (pinctrl_info == NULL) {
  4145. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4146. return -EINVAL;
  4147. }
  4148. pinctrl = devm_pinctrl_get(&pdev->dev);
  4149. if (IS_ERR_OR_NULL(pinctrl)) {
  4150. pr_err("%s: Unable to get pinctrl handle\n", __func__);
  4151. return -EINVAL;
  4152. }
  4153. pinctrl_info->pinctrl = pinctrl;
  4154. /* get all the states handles from Device Tree */
  4155. pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
  4156. "quat-mi2s-sleep");
  4157. if (IS_ERR(pinctrl_info->mi2s_disable)) {
  4158. pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
  4159. goto err;
  4160. }
  4161. pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
  4162. "quat-mi2s-active");
  4163. if (IS_ERR(pinctrl_info->mi2s_active)) {
  4164. pr_err("%s: could not get mi2s_active pinstate\n", __func__);
  4165. goto err;
  4166. }
  4167. pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
  4168. "quat-tdm-sleep");
  4169. if (IS_ERR(pinctrl_info->tdm_disable)) {
  4170. pr_err("%s: could not get tdm_disable pinstate\n", __func__);
  4171. goto err;
  4172. }
  4173. pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
  4174. "quat-tdm-active");
  4175. if (IS_ERR(pinctrl_info->tdm_active)) {
  4176. pr_err("%s: could not get tdm_active pinstate\n",
  4177. __func__);
  4178. goto err;
  4179. }
  4180. /* Reset the TLMM pins to a default state */
  4181. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4182. pinctrl_info->mi2s_disable);
  4183. if (ret != 0) {
  4184. pr_err("%s: Disable TLMM pins failed with %d\n",
  4185. __func__, ret);
  4186. ret = -EIO;
  4187. goto err;
  4188. }
  4189. pinctrl_info->curr_state = STATE_DISABLE;
  4190. return 0;
  4191. err:
  4192. devm_pinctrl_put(pinctrl);
  4193. pinctrl_info->pinctrl = NULL;
  4194. return -EINVAL;
  4195. }
  4196. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4197. struct snd_pcm_hw_params *params)
  4198. {
  4199. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4200. struct snd_interval *rate = hw_param_interval(params,
  4201. SNDRV_PCM_HW_PARAM_RATE);
  4202. struct snd_interval *channels = hw_param_interval(params,
  4203. SNDRV_PCM_HW_PARAM_CHANNELS);
  4204. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4205. channels->min = channels->max =
  4206. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4207. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4208. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4209. rate->min = rate->max =
  4210. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4211. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4212. channels->min = channels->max =
  4213. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4214. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4215. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4216. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4217. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4218. channels->min = channels->max =
  4219. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4220. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4221. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4222. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4223. } else {
  4224. pr_err("%s: dai id 0x%x not supported\n",
  4225. __func__, cpu_dai->id);
  4226. return -EINVAL;
  4227. }
  4228. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4229. __func__, cpu_dai->id, channels->max, rate->max,
  4230. params_format(params));
  4231. return 0;
  4232. }
  4233. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4234. struct snd_pcm_hw_params *params)
  4235. {
  4236. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4237. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4238. int ret = 0;
  4239. int slot_width = 32;
  4240. int channels, slots;
  4241. unsigned int slot_mask, rate, clk_freq;
  4242. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4243. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4244. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4245. switch (cpu_dai->id) {
  4246. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4247. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4248. break;
  4249. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4250. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4251. break;
  4252. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4253. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4254. break;
  4255. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4256. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4257. break;
  4258. case AFE_PORT_ID_QUINARY_TDM_RX:
  4259. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4260. break;
  4261. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4262. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4263. break;
  4264. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4265. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4266. break;
  4267. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4268. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4269. break;
  4270. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4271. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4272. break;
  4273. case AFE_PORT_ID_QUINARY_TDM_TX:
  4274. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4275. break;
  4276. default:
  4277. pr_err("%s: dai id 0x%x not supported\n",
  4278. __func__, cpu_dai->id);
  4279. return -EINVAL;
  4280. }
  4281. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4282. /*2 slot config - bits 0 and 1 set for the first two slots */
  4283. slot_mask = 0x0000FFFF >> (16-slots);
  4284. channels = slots;
  4285. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4286. __func__, slot_width, slots);
  4287. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4288. slots, slot_width);
  4289. if (ret < 0) {
  4290. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4291. __func__, ret);
  4292. goto end;
  4293. }
  4294. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4295. 0, NULL, channels, slot_offset);
  4296. if (ret < 0) {
  4297. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4298. __func__, ret);
  4299. goto end;
  4300. }
  4301. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4302. /*2 slot config - bits 0 and 1 set for the first two slots */
  4303. slot_mask = 0x0000FFFF >> (16-slots);
  4304. channels = slots;
  4305. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4306. __func__, slot_width, slots);
  4307. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4308. slots, slot_width);
  4309. if (ret < 0) {
  4310. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4311. __func__, ret);
  4312. goto end;
  4313. }
  4314. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4315. channels, slot_offset, 0, NULL);
  4316. if (ret < 0) {
  4317. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4318. __func__, ret);
  4319. goto end;
  4320. }
  4321. } else {
  4322. ret = -EINVAL;
  4323. pr_err("%s: invalid use case, err:%d\n",
  4324. __func__, ret);
  4325. goto end;
  4326. }
  4327. rate = params_rate(params);
  4328. clk_freq = rate * slot_width * slots;
  4329. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4330. if (ret < 0)
  4331. pr_err("%s: failed to set tdm clk, err:%d\n",
  4332. __func__, ret);
  4333. end:
  4334. return ret;
  4335. }
  4336. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4337. {
  4338. int ret = 0;
  4339. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4340. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4341. struct snd_soc_card *card = rtd->card;
  4342. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4343. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4344. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4345. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4346. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4347. ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
  4348. if (ret)
  4349. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4350. __func__, ret);
  4351. }
  4352. return ret;
  4353. }
  4354. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4355. {
  4356. int ret = 0;
  4357. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4358. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4359. struct snd_soc_card *card = rtd->card;
  4360. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4361. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4362. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4363. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4364. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4365. ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
  4366. if (ret)
  4367. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4368. __func__, ret);
  4369. }
  4370. }
  4371. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4372. .hw_params = qcs405_tdm_snd_hw_params,
  4373. .startup = qcs405_tdm_snd_startup,
  4374. .shutdown = qcs405_tdm_snd_shutdown
  4375. };
  4376. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4377. {
  4378. cpumask_t mask;
  4379. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4380. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4381. cpumask_clear(&mask);
  4382. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4383. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4384. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4385. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4386. pm_qos_add_request(&substream->latency_pm_qos_req,
  4387. PM_QOS_CPU_DMA_LATENCY,
  4388. MSM_LL_QOS_VALUE);
  4389. return 0;
  4390. }
  4391. static struct snd_soc_ops msm_fe_qos_ops = {
  4392. .prepare = msm_fe_qos_prepare,
  4393. };
  4394. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4395. {
  4396. int ret = 0;
  4397. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4398. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4399. int index = cpu_dai->id;
  4400. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4401. struct snd_soc_card *card = rtd->card;
  4402. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4403. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4404. int ret_pinctrl = 0;
  4405. dev_dbg(rtd->card->dev,
  4406. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4407. __func__, substream->name, substream->stream,
  4408. cpu_dai->name, cpu_dai->id);
  4409. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4410. ret = -EINVAL;
  4411. dev_err(rtd->card->dev,
  4412. "%s: CPU DAI id (%d) out of range\n",
  4413. __func__, cpu_dai->id);
  4414. goto err;
  4415. }
  4416. /*
  4417. * Mutex protection in case the same MI2S
  4418. * interface using for both TX and RX so
  4419. * that the same clock won't be enable twice.
  4420. */
  4421. mutex_lock(&mi2s_intf_conf[index].lock);
  4422. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4423. /* Check if msm needs to provide the clock to the interface */
  4424. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4425. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4426. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4427. }
  4428. ret = msm_mi2s_set_sclk(substream, true);
  4429. if (ret < 0) {
  4430. dev_err(rtd->card->dev,
  4431. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4432. __func__, ret);
  4433. goto clean_up;
  4434. }
  4435. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4436. if (ret < 0) {
  4437. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4438. __func__, index, ret);
  4439. goto clk_off;
  4440. }
  4441. if (index == QUAT_MI2S) {
  4442. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4443. STATE_MI2S_ACTIVE);
  4444. if (ret_pinctrl)
  4445. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4446. __func__, ret_pinctrl);
  4447. }
  4448. }
  4449. clk_off:
  4450. if (ret < 0)
  4451. msm_mi2s_set_sclk(substream, false);
  4452. clean_up:
  4453. if (ret < 0)
  4454. mi2s_intf_conf[index].ref_cnt--;
  4455. mutex_unlock(&mi2s_intf_conf[index].lock);
  4456. err:
  4457. return ret;
  4458. }
  4459. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4460. {
  4461. int ret;
  4462. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4463. int index = rtd->cpu_dai->id;
  4464. struct snd_soc_card *card = rtd->card;
  4465. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4466. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4467. int ret_pinctrl = 0;
  4468. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4469. substream->name, substream->stream);
  4470. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4471. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4472. return;
  4473. }
  4474. mutex_lock(&mi2s_intf_conf[index].lock);
  4475. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4476. ret = msm_mi2s_set_sclk(substream, false);
  4477. if (ret < 0)
  4478. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4479. __func__, index, ret);
  4480. if (index == QUAT_MI2S) {
  4481. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4482. STATE_DISABLE);
  4483. if (ret_pinctrl)
  4484. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4485. __func__, ret_pinctrl);
  4486. }
  4487. }
  4488. mutex_unlock(&mi2s_intf_conf[index].lock);
  4489. }
  4490. static struct snd_soc_ops msm_mi2s_be_ops = {
  4491. .startup = msm_mi2s_snd_startup,
  4492. .shutdown = msm_mi2s_snd_shutdown,
  4493. };
  4494. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4495. .hw_params = msm_snd_cdc_dma_hw_params,
  4496. };
  4497. static struct snd_soc_ops msm_be_ops = {
  4498. .hw_params = msm_snd_hw_params,
  4499. };
  4500. static struct snd_soc_ops msm_slimbus_2_be_ops = {
  4501. .hw_params = msm_slimbus_2_hw_params,
  4502. };
  4503. static struct snd_soc_ops msm_wcn_ops = {
  4504. .hw_params = msm_wcn_hw_params,
  4505. };
  4506. /* Digital audio interface glue - connects codec <---> CPU */
  4507. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4508. /* FrontEnd DAI Links */
  4509. {
  4510. .name = MSM_DAILINK_NAME(Media1),
  4511. .stream_name = "MultiMedia1",
  4512. .cpu_dai_name = "MultiMedia1",
  4513. .platform_name = "msm-pcm-dsp.0",
  4514. .dynamic = 1,
  4515. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4516. .dpcm_playback = 1,
  4517. .dpcm_capture = 1,
  4518. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4519. SND_SOC_DPCM_TRIGGER_POST},
  4520. .codec_dai_name = "snd-soc-dummy-dai",
  4521. .codec_name = "snd-soc-dummy",
  4522. .ignore_suspend = 1,
  4523. /* this dainlink has playback support */
  4524. .ignore_pmdown_time = 1,
  4525. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4526. },
  4527. {
  4528. .name = MSM_DAILINK_NAME(Media2),
  4529. .stream_name = "MultiMedia2",
  4530. .cpu_dai_name = "MultiMedia2",
  4531. .platform_name = "msm-pcm-dsp.0",
  4532. .dynamic = 1,
  4533. .dpcm_playback = 1,
  4534. .dpcm_capture = 1,
  4535. .codec_dai_name = "snd-soc-dummy-dai",
  4536. .codec_name = "snd-soc-dummy",
  4537. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4538. SND_SOC_DPCM_TRIGGER_POST},
  4539. .ignore_suspend = 1,
  4540. /* this dainlink has playback support */
  4541. .ignore_pmdown_time = 1,
  4542. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4543. },
  4544. {
  4545. .name = "VoiceMMode1",
  4546. .stream_name = "VoiceMMode1",
  4547. .cpu_dai_name = "VoiceMMode1",
  4548. .platform_name = "msm-pcm-voice",
  4549. .dynamic = 1,
  4550. .dpcm_playback = 1,
  4551. .dpcm_capture = 1,
  4552. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4553. SND_SOC_DPCM_TRIGGER_POST},
  4554. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4555. .ignore_suspend = 1,
  4556. .ignore_pmdown_time = 1,
  4557. .codec_dai_name = "snd-soc-dummy-dai",
  4558. .codec_name = "snd-soc-dummy",
  4559. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4560. },
  4561. {
  4562. .name = "MSM VoIP",
  4563. .stream_name = "VoIP",
  4564. .cpu_dai_name = "VoIP",
  4565. .platform_name = "msm-voip-dsp",
  4566. .dynamic = 1,
  4567. .dpcm_playback = 1,
  4568. .dpcm_capture = 1,
  4569. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4570. SND_SOC_DPCM_TRIGGER_POST},
  4571. .codec_dai_name = "snd-soc-dummy-dai",
  4572. .codec_name = "snd-soc-dummy",
  4573. .ignore_suspend = 1,
  4574. /* this dainlink has playback support */
  4575. .ignore_pmdown_time = 1,
  4576. .id = MSM_FRONTEND_DAI_VOIP,
  4577. },
  4578. {
  4579. .name = MSM_DAILINK_NAME(ULL),
  4580. .stream_name = "MultiMedia3",
  4581. .cpu_dai_name = "MultiMedia3",
  4582. .platform_name = "msm-pcm-dsp.2",
  4583. .dynamic = 1,
  4584. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4585. .dpcm_playback = 1,
  4586. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4587. SND_SOC_DPCM_TRIGGER_POST},
  4588. .codec_dai_name = "snd-soc-dummy-dai",
  4589. .codec_name = "snd-soc-dummy",
  4590. .ignore_suspend = 1,
  4591. /* this dainlink has playback support */
  4592. .ignore_pmdown_time = 1,
  4593. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4594. },
  4595. /* Hostless PCM purpose */
  4596. {
  4597. .name = "SLIMBUS_0 Hostless",
  4598. .stream_name = "SLIMBUS_0 Hostless",
  4599. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  4600. .platform_name = "msm-pcm-hostless",
  4601. .dynamic = 1,
  4602. .dpcm_playback = 1,
  4603. .dpcm_capture = 1,
  4604. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4605. SND_SOC_DPCM_TRIGGER_POST},
  4606. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4607. .ignore_suspend = 1,
  4608. /* this dailink has playback support */
  4609. .ignore_pmdown_time = 1,
  4610. .codec_dai_name = "snd-soc-dummy-dai",
  4611. .codec_name = "snd-soc-dummy",
  4612. },
  4613. {
  4614. .name = "MSM AFE-PCM RX",
  4615. .stream_name = "AFE-PROXY RX",
  4616. .cpu_dai_name = "msm-dai-q6-dev.241",
  4617. .codec_name = "msm-stub-codec.1",
  4618. .codec_dai_name = "msm-stub-rx",
  4619. .platform_name = "msm-pcm-afe",
  4620. .dpcm_playback = 1,
  4621. .ignore_suspend = 1,
  4622. /* this dainlink has playback support */
  4623. .ignore_pmdown_time = 1,
  4624. },
  4625. {
  4626. .name = "MSM AFE-PCM TX",
  4627. .stream_name = "AFE-PROXY TX",
  4628. .cpu_dai_name = "msm-dai-q6-dev.240",
  4629. .codec_name = "msm-stub-codec.1",
  4630. .codec_dai_name = "msm-stub-tx",
  4631. .platform_name = "msm-pcm-afe",
  4632. .dpcm_capture = 1,
  4633. .ignore_suspend = 1,
  4634. },
  4635. {
  4636. .name = MSM_DAILINK_NAME(Compress1),
  4637. .stream_name = "Compress1",
  4638. .cpu_dai_name = "MultiMedia4",
  4639. .platform_name = "msm-compress-dsp",
  4640. .dynamic = 1,
  4641. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4642. .dpcm_playback = 1,
  4643. .dpcm_capture = 1,
  4644. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4645. SND_SOC_DPCM_TRIGGER_POST},
  4646. .codec_dai_name = "snd-soc-dummy-dai",
  4647. .codec_name = "snd-soc-dummy",
  4648. .ignore_suspend = 1,
  4649. .ignore_pmdown_time = 1,
  4650. /* this dainlink has playback support */
  4651. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4652. },
  4653. {
  4654. .name = "AUXPCM Hostless",
  4655. .stream_name = "AUXPCM Hostless",
  4656. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4657. .platform_name = "msm-pcm-hostless",
  4658. .dynamic = 1,
  4659. .dpcm_playback = 1,
  4660. .dpcm_capture = 1,
  4661. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4662. SND_SOC_DPCM_TRIGGER_POST},
  4663. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4664. .ignore_suspend = 1,
  4665. /* this dainlink has playback support */
  4666. .ignore_pmdown_time = 1,
  4667. .codec_dai_name = "snd-soc-dummy-dai",
  4668. .codec_name = "snd-soc-dummy",
  4669. },
  4670. {
  4671. .name = "SLIMBUS_1 Hostless",
  4672. .stream_name = "SLIMBUS_1 Hostless",
  4673. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  4674. .platform_name = "msm-pcm-hostless",
  4675. .dynamic = 1,
  4676. .dpcm_playback = 1,
  4677. .dpcm_capture = 1,
  4678. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4679. SND_SOC_DPCM_TRIGGER_POST},
  4680. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4681. .ignore_suspend = 1,
  4682. /* this dailink has playback support */
  4683. .ignore_pmdown_time = 1,
  4684. .codec_dai_name = "snd-soc-dummy-dai",
  4685. .codec_name = "snd-soc-dummy",
  4686. },
  4687. {
  4688. .name = "SLIMBUS_3 Hostless",
  4689. .stream_name = "SLIMBUS_3 Hostless",
  4690. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  4691. .platform_name = "msm-pcm-hostless",
  4692. .dynamic = 1,
  4693. .dpcm_playback = 1,
  4694. .dpcm_capture = 1,
  4695. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4696. SND_SOC_DPCM_TRIGGER_POST},
  4697. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4698. .ignore_suspend = 1,
  4699. /* this dailink has playback support */
  4700. .ignore_pmdown_time = 1,
  4701. .codec_dai_name = "snd-soc-dummy-dai",
  4702. .codec_name = "snd-soc-dummy",
  4703. },
  4704. {
  4705. .name = "SLIMBUS_4 Hostless",
  4706. .stream_name = "SLIMBUS_4 Hostless",
  4707. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  4708. .platform_name = "msm-pcm-hostless",
  4709. .dynamic = 1,
  4710. .dpcm_playback = 1,
  4711. .dpcm_capture = 1,
  4712. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4713. SND_SOC_DPCM_TRIGGER_POST},
  4714. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4715. .ignore_suspend = 1,
  4716. /* this dailink has playback support */
  4717. .ignore_pmdown_time = 1,
  4718. .codec_dai_name = "snd-soc-dummy-dai",
  4719. .codec_name = "snd-soc-dummy",
  4720. },
  4721. {
  4722. .name = MSM_DAILINK_NAME(LowLatency),
  4723. .stream_name = "MultiMedia5",
  4724. .cpu_dai_name = "MultiMedia5",
  4725. .platform_name = "msm-pcm-dsp.1",
  4726. .dynamic = 1,
  4727. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4728. .dpcm_playback = 1,
  4729. .dpcm_capture = 1,
  4730. .codec_dai_name = "snd-soc-dummy-dai",
  4731. .codec_name = "snd-soc-dummy",
  4732. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4733. SND_SOC_DPCM_TRIGGER_POST},
  4734. .ignore_suspend = 1,
  4735. /* this dainlink has playback support */
  4736. .ignore_pmdown_time = 1,
  4737. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4738. .ops = &msm_fe_qos_ops,
  4739. },
  4740. {
  4741. .name = "Listen 1 Audio Service",
  4742. .stream_name = "Listen 1 Audio Service",
  4743. .cpu_dai_name = "LSM1",
  4744. .platform_name = "msm-lsm-client",
  4745. .dynamic = 1,
  4746. .dpcm_capture = 1,
  4747. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4748. SND_SOC_DPCM_TRIGGER_POST },
  4749. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4750. .ignore_suspend = 1,
  4751. .codec_dai_name = "snd-soc-dummy-dai",
  4752. .codec_name = "snd-soc-dummy",
  4753. .id = MSM_FRONTEND_DAI_LSM1,
  4754. },
  4755. /* Multiple Tunnel instances */
  4756. {
  4757. .name = MSM_DAILINK_NAME(Compress2),
  4758. .stream_name = "Compress2",
  4759. .cpu_dai_name = "MultiMedia7",
  4760. .platform_name = "msm-compress-dsp",
  4761. .dynamic = 1,
  4762. .dpcm_playback = 1,
  4763. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4764. SND_SOC_DPCM_TRIGGER_POST},
  4765. .codec_dai_name = "snd-soc-dummy-dai",
  4766. .codec_name = "snd-soc-dummy",
  4767. .ignore_suspend = 1,
  4768. .ignore_pmdown_time = 1,
  4769. /* this dainlink has playback support */
  4770. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4771. },
  4772. {
  4773. .name = MSM_DAILINK_NAME(MultiMedia10),
  4774. .stream_name = "MultiMedia10",
  4775. .cpu_dai_name = "MultiMedia10",
  4776. .platform_name = "msm-pcm-dsp.1",
  4777. .dynamic = 1,
  4778. .dpcm_playback = 1,
  4779. .dpcm_capture = 1,
  4780. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4781. SND_SOC_DPCM_TRIGGER_POST},
  4782. .codec_dai_name = "snd-soc-dummy-dai",
  4783. .codec_name = "snd-soc-dummy",
  4784. .ignore_suspend = 1,
  4785. .ignore_pmdown_time = 1,
  4786. /* this dainlink has playback support */
  4787. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4788. },
  4789. {
  4790. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4791. .stream_name = "MM_NOIRQ",
  4792. .cpu_dai_name = "MultiMedia8",
  4793. .platform_name = "msm-pcm-dsp-noirq",
  4794. .dynamic = 1,
  4795. .dpcm_playback = 1,
  4796. .dpcm_capture = 1,
  4797. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4798. SND_SOC_DPCM_TRIGGER_POST},
  4799. .codec_dai_name = "snd-soc-dummy-dai",
  4800. .codec_name = "snd-soc-dummy",
  4801. .ignore_suspend = 1,
  4802. .ignore_pmdown_time = 1,
  4803. /* this dainlink has playback support */
  4804. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4805. .ops = &msm_fe_qos_ops,
  4806. },
  4807. /* HDMI Hostless */
  4808. {
  4809. .name = "HDMI_RX_HOSTLESS",
  4810. .stream_name = "HDMI_RX_HOSTLESS",
  4811. .cpu_dai_name = "HDMI_HOSTLESS",
  4812. .platform_name = "msm-pcm-hostless",
  4813. .dynamic = 1,
  4814. .dpcm_playback = 1,
  4815. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4816. SND_SOC_DPCM_TRIGGER_POST},
  4817. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4818. .ignore_suspend = 1,
  4819. .ignore_pmdown_time = 1,
  4820. .codec_dai_name = "snd-soc-dummy-dai",
  4821. .codec_name = "snd-soc-dummy",
  4822. },
  4823. {
  4824. .name = "VoiceMMode2",
  4825. .stream_name = "VoiceMMode2",
  4826. .cpu_dai_name = "VoiceMMode2",
  4827. .platform_name = "msm-pcm-voice",
  4828. .dynamic = 1,
  4829. .dpcm_playback = 1,
  4830. .dpcm_capture = 1,
  4831. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4832. SND_SOC_DPCM_TRIGGER_POST},
  4833. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4834. .ignore_suspend = 1,
  4835. .ignore_pmdown_time = 1,
  4836. .codec_dai_name = "snd-soc-dummy-dai",
  4837. .codec_name = "snd-soc-dummy",
  4838. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4839. },
  4840. /* LSM FE */
  4841. {
  4842. .name = "Listen 2 Audio Service",
  4843. .stream_name = "Listen 2 Audio Service",
  4844. .cpu_dai_name = "LSM2",
  4845. .platform_name = "msm-lsm-client",
  4846. .dynamic = 1,
  4847. .dpcm_capture = 1,
  4848. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4849. SND_SOC_DPCM_TRIGGER_POST },
  4850. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4851. .ignore_suspend = 1,
  4852. .codec_dai_name = "snd-soc-dummy-dai",
  4853. .codec_name = "snd-soc-dummy",
  4854. .id = MSM_FRONTEND_DAI_LSM2,
  4855. },
  4856. {
  4857. .name = "Listen 3 Audio Service",
  4858. .stream_name = "Listen 3 Audio Service",
  4859. .cpu_dai_name = "LSM3",
  4860. .platform_name = "msm-lsm-client",
  4861. .dynamic = 1,
  4862. .dpcm_capture = 1,
  4863. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4864. SND_SOC_DPCM_TRIGGER_POST },
  4865. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4866. .ignore_suspend = 1,
  4867. .codec_dai_name = "snd-soc-dummy-dai",
  4868. .codec_name = "snd-soc-dummy",
  4869. .id = MSM_FRONTEND_DAI_LSM3,
  4870. },
  4871. {
  4872. .name = "Listen 4 Audio Service",
  4873. .stream_name = "Listen 4 Audio Service",
  4874. .cpu_dai_name = "LSM4",
  4875. .platform_name = "msm-lsm-client",
  4876. .dynamic = 1,
  4877. .dpcm_capture = 1,
  4878. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4879. SND_SOC_DPCM_TRIGGER_POST },
  4880. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4881. .ignore_suspend = 1,
  4882. .codec_dai_name = "snd-soc-dummy-dai",
  4883. .codec_name = "snd-soc-dummy",
  4884. .id = MSM_FRONTEND_DAI_LSM4,
  4885. },
  4886. {
  4887. .name = "Listen 5 Audio Service",
  4888. .stream_name = "Listen 5 Audio Service",
  4889. .cpu_dai_name = "LSM5",
  4890. .platform_name = "msm-lsm-client",
  4891. .dynamic = 1,
  4892. .dpcm_capture = 1,
  4893. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4894. SND_SOC_DPCM_TRIGGER_POST },
  4895. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4896. .ignore_suspend = 1,
  4897. .codec_dai_name = "snd-soc-dummy-dai",
  4898. .codec_name = "snd-soc-dummy",
  4899. .id = MSM_FRONTEND_DAI_LSM5,
  4900. },
  4901. {
  4902. .name = "Listen 6 Audio Service",
  4903. .stream_name = "Listen 6 Audio Service",
  4904. .cpu_dai_name = "LSM6",
  4905. .platform_name = "msm-lsm-client",
  4906. .dynamic = 1,
  4907. .dpcm_capture = 1,
  4908. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4909. SND_SOC_DPCM_TRIGGER_POST },
  4910. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4911. .ignore_suspend = 1,
  4912. .codec_dai_name = "snd-soc-dummy-dai",
  4913. .codec_name = "snd-soc-dummy",
  4914. .id = MSM_FRONTEND_DAI_LSM6,
  4915. },
  4916. {
  4917. .name = "Listen 7 Audio Service",
  4918. .stream_name = "Listen 7 Audio Service",
  4919. .cpu_dai_name = "LSM7",
  4920. .platform_name = "msm-lsm-client",
  4921. .dynamic = 1,
  4922. .dpcm_capture = 1,
  4923. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4924. SND_SOC_DPCM_TRIGGER_POST },
  4925. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4926. .ignore_suspend = 1,
  4927. .codec_dai_name = "snd-soc-dummy-dai",
  4928. .codec_name = "snd-soc-dummy",
  4929. .id = MSM_FRONTEND_DAI_LSM7,
  4930. },
  4931. {
  4932. .name = "Listen 8 Audio Service",
  4933. .stream_name = "Listen 8 Audio Service",
  4934. .cpu_dai_name = "LSM8",
  4935. .platform_name = "msm-lsm-client",
  4936. .dynamic = 1,
  4937. .dpcm_capture = 1,
  4938. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4939. SND_SOC_DPCM_TRIGGER_POST },
  4940. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4941. .ignore_suspend = 1,
  4942. .codec_dai_name = "snd-soc-dummy-dai",
  4943. .codec_name = "snd-soc-dummy",
  4944. .id = MSM_FRONTEND_DAI_LSM8,
  4945. },
  4946. {
  4947. .name = MSM_DAILINK_NAME(Media9),
  4948. .stream_name = "MultiMedia9",
  4949. .cpu_dai_name = "MultiMedia9",
  4950. .platform_name = "msm-pcm-dsp.0",
  4951. .dynamic = 1,
  4952. .dpcm_playback = 1,
  4953. .dpcm_capture = 1,
  4954. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4955. SND_SOC_DPCM_TRIGGER_POST},
  4956. .codec_dai_name = "snd-soc-dummy-dai",
  4957. .codec_name = "snd-soc-dummy",
  4958. .ignore_suspend = 1,
  4959. /* this dainlink has playback support */
  4960. .ignore_pmdown_time = 1,
  4961. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4962. },
  4963. {
  4964. .name = MSM_DAILINK_NAME(Compress4),
  4965. .stream_name = "Compress4",
  4966. .cpu_dai_name = "MultiMedia11",
  4967. .platform_name = "msm-compress-dsp",
  4968. .dynamic = 1,
  4969. .dpcm_playback = 1,
  4970. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4971. SND_SOC_DPCM_TRIGGER_POST},
  4972. .codec_dai_name = "snd-soc-dummy-dai",
  4973. .codec_name = "snd-soc-dummy",
  4974. .ignore_suspend = 1,
  4975. .ignore_pmdown_time = 1,
  4976. /* this dainlink has playback support */
  4977. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  4978. },
  4979. {
  4980. .name = MSM_DAILINK_NAME(Compress5),
  4981. .stream_name = "Compress5",
  4982. .cpu_dai_name = "MultiMedia12",
  4983. .platform_name = "msm-compress-dsp",
  4984. .dynamic = 1,
  4985. .dpcm_playback = 1,
  4986. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4987. SND_SOC_DPCM_TRIGGER_POST},
  4988. .codec_dai_name = "snd-soc-dummy-dai",
  4989. .codec_name = "snd-soc-dummy",
  4990. .ignore_suspend = 1,
  4991. .ignore_pmdown_time = 1,
  4992. /* this dainlink has playback support */
  4993. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  4994. },
  4995. {
  4996. .name = MSM_DAILINK_NAME(Compress6),
  4997. .stream_name = "Compress6",
  4998. .cpu_dai_name = "MultiMedia13",
  4999. .platform_name = "msm-compress-dsp",
  5000. .dynamic = 1,
  5001. .dpcm_playback = 1,
  5002. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5003. SND_SOC_DPCM_TRIGGER_POST},
  5004. .codec_dai_name = "snd-soc-dummy-dai",
  5005. .codec_name = "snd-soc-dummy",
  5006. .ignore_suspend = 1,
  5007. .ignore_pmdown_time = 1,
  5008. /* this dainlink has playback support */
  5009. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5010. },
  5011. {
  5012. .name = MSM_DAILINK_NAME(Compress7),
  5013. .stream_name = "Compress7",
  5014. .cpu_dai_name = "MultiMedia14",
  5015. .platform_name = "msm-compress-dsp",
  5016. .dynamic = 1,
  5017. .dpcm_playback = 1,
  5018. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5019. SND_SOC_DPCM_TRIGGER_POST},
  5020. .codec_dai_name = "snd-soc-dummy-dai",
  5021. .codec_name = "snd-soc-dummy",
  5022. .ignore_suspend = 1,
  5023. .ignore_pmdown_time = 1,
  5024. /* this dainlink has playback support */
  5025. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5026. },
  5027. {
  5028. .name = MSM_DAILINK_NAME(Compress8),
  5029. .stream_name = "Compress8",
  5030. .cpu_dai_name = "MultiMedia15",
  5031. .platform_name = "msm-compress-dsp",
  5032. .dynamic = 1,
  5033. .dpcm_playback = 1,
  5034. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5035. SND_SOC_DPCM_TRIGGER_POST},
  5036. .codec_dai_name = "snd-soc-dummy-dai",
  5037. .codec_name = "snd-soc-dummy",
  5038. .ignore_suspend = 1,
  5039. .ignore_pmdown_time = 1,
  5040. /* this dainlink has playback support */
  5041. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5042. },
  5043. {
  5044. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5045. .stream_name = "MM_NOIRQ_2",
  5046. .cpu_dai_name = "MultiMedia16",
  5047. .platform_name = "msm-pcm-dsp-noirq",
  5048. .dynamic = 1,
  5049. .dpcm_playback = 1,
  5050. .dpcm_capture = 1,
  5051. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5052. SND_SOC_DPCM_TRIGGER_POST},
  5053. .codec_dai_name = "snd-soc-dummy-dai",
  5054. .codec_name = "snd-soc-dummy",
  5055. .ignore_suspend = 1,
  5056. .ignore_pmdown_time = 1,
  5057. /* this dainlink has playback support */
  5058. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5059. },
  5060. {
  5061. .name = "SLIMBUS_8 Hostless",
  5062. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5063. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5064. .platform_name = "msm-pcm-hostless",
  5065. .dynamic = 1,
  5066. .dpcm_capture = 1,
  5067. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5068. SND_SOC_DPCM_TRIGGER_POST},
  5069. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5070. .ignore_suspend = 1,
  5071. .codec_dai_name = "snd-soc-dummy-dai",
  5072. .codec_name = "snd-soc-dummy",
  5073. },
  5074. };
  5075. static struct snd_soc_dai_link msm_tasha_fe_dai_links[] = {
  5076. /* Ultrasound RX DAI Link */
  5077. {
  5078. .name = "SLIMBUS_2 Hostless Playback",
  5079. .stream_name = "SLIMBUS_2 Hostless Playback",
  5080. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5081. .platform_name = "msm-pcm-hostless",
  5082. .codec_name = "tasha_codec",
  5083. .codec_dai_name = "tasha_rx2",
  5084. .ignore_suspend = 1,
  5085. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5086. .ops = &msm_slimbus_2_be_ops,
  5087. },
  5088. /* Ultrasound TX DAI Link */
  5089. {
  5090. .name = "SLIMBUS_2 Hostless Capture",
  5091. .stream_name = "SLIMBUS_2 Hostless Capture",
  5092. .cpu_dai_name = "msm-dai-q6-dev.16389",
  5093. .platform_name = "msm-pcm-hostless",
  5094. .codec_name = "tasha_codec",
  5095. .codec_dai_name = "tasha_tx2",
  5096. .ignore_suspend = 1,
  5097. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5098. .ops = &msm_slimbus_2_be_ops,
  5099. },
  5100. {
  5101. .name = "SLIMBUS_6 Hostless Playback",
  5102. .stream_name = "SLIMBUS_6 Hostless",
  5103. .cpu_dai_name = "SLIMBUS6_HOSTLESS",
  5104. .platform_name = "msm-pcm-hostless",
  5105. .dynamic = 1,
  5106. .dpcm_playback = 1,
  5107. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5108. SND_SOC_DPCM_TRIGGER_POST},
  5109. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5110. .ignore_suspend = 1,
  5111. /* this dailink has playback support */
  5112. .ignore_pmdown_time = 1,
  5113. .codec_dai_name = "snd-soc-dummy-dai",
  5114. .codec_name = "snd-soc-dummy",
  5115. },
  5116. };
  5117. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5118. {
  5119. .name = MSM_DAILINK_NAME(ASM Loopback),
  5120. .stream_name = "MultiMedia6",
  5121. .cpu_dai_name = "MultiMedia6",
  5122. .platform_name = "msm-pcm-loopback",
  5123. .dynamic = 1,
  5124. .dpcm_playback = 1,
  5125. .dpcm_capture = 1,
  5126. .codec_dai_name = "snd-soc-dummy-dai",
  5127. .codec_name = "snd-soc-dummy",
  5128. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5129. SND_SOC_DPCM_TRIGGER_POST},
  5130. .ignore_suspend = 1,
  5131. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5132. .ignore_pmdown_time = 1,
  5133. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5134. },
  5135. {
  5136. .name = "USB Audio Hostless",
  5137. .stream_name = "USB Audio Hostless",
  5138. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5139. .platform_name = "msm-pcm-hostless",
  5140. .dynamic = 1,
  5141. .dpcm_playback = 1,
  5142. .dpcm_capture = 1,
  5143. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5144. SND_SOC_DPCM_TRIGGER_POST},
  5145. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5146. .ignore_suspend = 1,
  5147. .ignore_pmdown_time = 1,
  5148. .codec_dai_name = "snd-soc-dummy-dai",
  5149. .codec_name = "snd-soc-dummy",
  5150. },
  5151. {
  5152. .name = "SLIMBUS_7 Hostless",
  5153. .stream_name = "SLIMBUS_7 Hostless",
  5154. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5155. .platform_name = "msm-pcm-hostless",
  5156. .dynamic = 1,
  5157. .dpcm_capture = 1,
  5158. .dpcm_playback = 1,
  5159. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5160. SND_SOC_DPCM_TRIGGER_POST},
  5161. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5162. .ignore_suspend = 1,
  5163. .ignore_pmdown_time = 1,
  5164. .codec_dai_name = "snd-soc-dummy-dai",
  5165. .codec_name = "snd-soc-dummy",
  5166. },
  5167. };
  5168. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5169. /* Backend AFE DAI Links */
  5170. {
  5171. .name = LPASS_BE_AFE_PCM_RX,
  5172. .stream_name = "AFE Playback",
  5173. .cpu_dai_name = "msm-dai-q6-dev.224",
  5174. .platform_name = "msm-pcm-routing",
  5175. .codec_name = "msm-stub-codec.1",
  5176. .codec_dai_name = "msm-stub-rx",
  5177. .no_pcm = 1,
  5178. .dpcm_playback = 1,
  5179. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5180. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5181. /* this dainlink has playback support */
  5182. .ignore_pmdown_time = 1,
  5183. .ignore_suspend = 1,
  5184. },
  5185. {
  5186. .name = LPASS_BE_AFE_PCM_TX,
  5187. .stream_name = "AFE Capture",
  5188. .cpu_dai_name = "msm-dai-q6-dev.225",
  5189. .platform_name = "msm-pcm-routing",
  5190. .codec_name = "msm-stub-codec.1",
  5191. .codec_dai_name = "msm-stub-tx",
  5192. .no_pcm = 1,
  5193. .dpcm_capture = 1,
  5194. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5195. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5196. .ignore_suspend = 1,
  5197. },
  5198. /* Incall Record Uplink BACK END DAI Link */
  5199. {
  5200. .name = LPASS_BE_INCALL_RECORD_TX,
  5201. .stream_name = "Voice Uplink Capture",
  5202. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5203. .platform_name = "msm-pcm-routing",
  5204. .codec_name = "msm-stub-codec.1",
  5205. .codec_dai_name = "msm-stub-tx",
  5206. .no_pcm = 1,
  5207. .dpcm_capture = 1,
  5208. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5209. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5210. .ignore_suspend = 1,
  5211. },
  5212. /* Incall Record Downlink BACK END DAI Link */
  5213. {
  5214. .name = LPASS_BE_INCALL_RECORD_RX,
  5215. .stream_name = "Voice Downlink Capture",
  5216. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5217. .platform_name = "msm-pcm-routing",
  5218. .codec_name = "msm-stub-codec.1",
  5219. .codec_dai_name = "msm-stub-tx",
  5220. .no_pcm = 1,
  5221. .dpcm_capture = 1,
  5222. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5223. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5224. .ignore_suspend = 1,
  5225. },
  5226. /* Incall Music BACK END DAI Link */
  5227. {
  5228. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5229. .stream_name = "Voice Farend Playback",
  5230. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5231. .platform_name = "msm-pcm-routing",
  5232. .codec_name = "msm-stub-codec.1",
  5233. .codec_dai_name = "msm-stub-rx",
  5234. .no_pcm = 1,
  5235. .dpcm_playback = 1,
  5236. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5237. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5238. .ignore_suspend = 1,
  5239. .ignore_pmdown_time = 1,
  5240. },
  5241. /* Incall Music 2 BACK END DAI Link */
  5242. {
  5243. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5244. .stream_name = "Voice2 Farend Playback",
  5245. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5246. .platform_name = "msm-pcm-routing",
  5247. .codec_name = "msm-stub-codec.1",
  5248. .codec_dai_name = "msm-stub-rx",
  5249. .no_pcm = 1,
  5250. .dpcm_playback = 1,
  5251. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5252. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5253. .ignore_suspend = 1,
  5254. .ignore_pmdown_time = 1,
  5255. },
  5256. {
  5257. .name = LPASS_BE_USB_AUDIO_RX,
  5258. .stream_name = "USB Audio Playback",
  5259. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5260. .platform_name = "msm-pcm-routing",
  5261. .codec_name = "msm-stub-codec.1",
  5262. .codec_dai_name = "msm-stub-rx",
  5263. .no_pcm = 1,
  5264. .dpcm_playback = 1,
  5265. .id = MSM_BACKEND_DAI_USB_RX,
  5266. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5267. .ignore_pmdown_time = 1,
  5268. .ignore_suspend = 1,
  5269. },
  5270. {
  5271. .name = LPASS_BE_USB_AUDIO_TX,
  5272. .stream_name = "USB Audio Capture",
  5273. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5274. .platform_name = "msm-pcm-routing",
  5275. .codec_name = "msm-stub-codec.1",
  5276. .codec_dai_name = "msm-stub-tx",
  5277. .no_pcm = 1,
  5278. .dpcm_capture = 1,
  5279. .id = MSM_BACKEND_DAI_USB_TX,
  5280. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5281. .ignore_suspend = 1,
  5282. },
  5283. {
  5284. .name = LPASS_BE_PRI_TDM_RX_0,
  5285. .stream_name = "Primary TDM0 Playback",
  5286. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5287. .platform_name = "msm-pcm-routing",
  5288. .codec_name = "msm-stub-codec.1",
  5289. .codec_dai_name = "msm-stub-rx",
  5290. .no_pcm = 1,
  5291. .dpcm_playback = 1,
  5292. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5293. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5294. .ops = &qcs405_tdm_be_ops,
  5295. .ignore_suspend = 1,
  5296. .ignore_pmdown_time = 1,
  5297. },
  5298. {
  5299. .name = LPASS_BE_PRI_TDM_TX_0,
  5300. .stream_name = "Primary TDM0 Capture",
  5301. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5302. .platform_name = "msm-pcm-routing",
  5303. .codec_name = "msm-stub-codec.1",
  5304. .codec_dai_name = "msm-stub-tx",
  5305. .no_pcm = 1,
  5306. .dpcm_capture = 1,
  5307. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5308. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5309. .ops = &qcs405_tdm_be_ops,
  5310. .ignore_suspend = 1,
  5311. },
  5312. {
  5313. .name = LPASS_BE_SEC_TDM_RX_0,
  5314. .stream_name = "Secondary TDM0 Playback",
  5315. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5316. .platform_name = "msm-pcm-routing",
  5317. .codec_name = "msm-stub-codec.1",
  5318. .codec_dai_name = "msm-stub-rx",
  5319. .no_pcm = 1,
  5320. .dpcm_playback = 1,
  5321. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5322. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5323. .ops = &qcs405_tdm_be_ops,
  5324. .ignore_suspend = 1,
  5325. .ignore_pmdown_time = 1,
  5326. },
  5327. {
  5328. .name = LPASS_BE_SEC_TDM_TX_0,
  5329. .stream_name = "Secondary TDM0 Capture",
  5330. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5331. .platform_name = "msm-pcm-routing",
  5332. .codec_name = "msm-stub-codec.1",
  5333. .codec_dai_name = "msm-stub-tx",
  5334. .no_pcm = 1,
  5335. .dpcm_capture = 1,
  5336. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5337. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5338. .ops = &qcs405_tdm_be_ops,
  5339. .ignore_suspend = 1,
  5340. },
  5341. {
  5342. .name = LPASS_BE_TERT_TDM_RX_0,
  5343. .stream_name = "Tertiary TDM0 Playback",
  5344. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5345. .platform_name = "msm-pcm-routing",
  5346. .codec_name = "msm-stub-codec.1",
  5347. .codec_dai_name = "msm-stub-rx",
  5348. .no_pcm = 1,
  5349. .dpcm_playback = 1,
  5350. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5351. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5352. .ops = &qcs405_tdm_be_ops,
  5353. .ignore_suspend = 1,
  5354. .ignore_pmdown_time = 1,
  5355. },
  5356. {
  5357. .name = LPASS_BE_TERT_TDM_TX_0,
  5358. .stream_name = "Tertiary TDM0 Capture",
  5359. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5360. .platform_name = "msm-pcm-routing",
  5361. .codec_name = "msm-stub-codec.1",
  5362. .codec_dai_name = "msm-stub-tx",
  5363. .no_pcm = 1,
  5364. .dpcm_capture = 1,
  5365. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5366. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5367. .ops = &qcs405_tdm_be_ops,
  5368. .ignore_suspend = 1,
  5369. },
  5370. {
  5371. .name = LPASS_BE_QUAT_TDM_RX_0,
  5372. .stream_name = "Quaternary TDM0 Playback",
  5373. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5374. .platform_name = "msm-pcm-routing",
  5375. .codec_name = "msm-stub-codec.1",
  5376. .codec_dai_name = "msm-stub-rx",
  5377. .no_pcm = 1,
  5378. .dpcm_playback = 1,
  5379. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5380. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5381. .ops = &qcs405_tdm_be_ops,
  5382. .ignore_suspend = 1,
  5383. .ignore_pmdown_time = 1,
  5384. },
  5385. {
  5386. .name = LPASS_BE_QUAT_TDM_TX_0,
  5387. .stream_name = "Quaternary TDM0 Capture",
  5388. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5389. .platform_name = "msm-pcm-routing",
  5390. .codec_name = "msm-stub-codec.1",
  5391. .codec_dai_name = "msm-stub-tx",
  5392. .no_pcm = 1,
  5393. .dpcm_capture = 1,
  5394. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5395. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5396. .ops = &qcs405_tdm_be_ops,
  5397. .ignore_suspend = 1,
  5398. },
  5399. };
  5400. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5401. {
  5402. .name = LPASS_BE_SLIMBUS_0_RX,
  5403. .stream_name = "Slimbus Playback",
  5404. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5405. .platform_name = "msm-pcm-routing",
  5406. .codec_name = "tasha_codec",
  5407. .codec_dai_name = "tasha_rx1",
  5408. .no_pcm = 1,
  5409. .dpcm_playback = 1,
  5410. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5411. .init = &msm_audrx_init,
  5412. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5413. /* this dainlink has playback support */
  5414. .ignore_pmdown_time = 1,
  5415. .ignore_suspend = 1,
  5416. .ops = &msm_be_ops,
  5417. },
  5418. {
  5419. .name = LPASS_BE_SLIMBUS_0_TX,
  5420. .stream_name = "Slimbus Capture",
  5421. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5422. .platform_name = "msm-pcm-routing",
  5423. .codec_name = "tasha_codec",
  5424. .codec_dai_name = "tasha_tx1",
  5425. .no_pcm = 1,
  5426. .dpcm_capture = 1,
  5427. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5428. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5429. .ignore_suspend = 1,
  5430. .ops = &msm_be_ops,
  5431. },
  5432. {
  5433. .name = LPASS_BE_SLIMBUS_1_RX,
  5434. .stream_name = "Slimbus1 Playback",
  5435. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5436. .platform_name = "msm-pcm-routing",
  5437. .codec_name = "tasha_codec",
  5438. .codec_dai_name = "tasha_rx1",
  5439. .no_pcm = 1,
  5440. .dpcm_playback = 1,
  5441. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5442. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5443. .ops = &msm_be_ops,
  5444. /* dai link has playback support */
  5445. .ignore_pmdown_time = 1,
  5446. .ignore_suspend = 1,
  5447. },
  5448. {
  5449. .name = LPASS_BE_SLIMBUS_1_TX,
  5450. .stream_name = "Slimbus1 Capture",
  5451. .cpu_dai_name = "msm-dai-q6-dev.16387",
  5452. .platform_name = "msm-pcm-routing",
  5453. .codec_name = "tasha_codec",
  5454. .codec_dai_name = "tasha_tx3",
  5455. .no_pcm = 1,
  5456. .dpcm_capture = 1,
  5457. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  5458. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5459. .ops = &msm_be_ops,
  5460. .ignore_suspend = 1,
  5461. },
  5462. {
  5463. .name = LPASS_BE_SLIMBUS_2_RX,
  5464. .stream_name = "Slimbus2 Playback",
  5465. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5466. .platform_name = "msm-pcm-routing",
  5467. .codec_name = "tasha_codec",
  5468. .codec_dai_name = "tasha_rx2",
  5469. .no_pcm = 1,
  5470. .dpcm_playback = 1,
  5471. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  5472. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5473. .ops = &msm_be_ops,
  5474. .ignore_pmdown_time = 1,
  5475. .ignore_suspend = 1,
  5476. },
  5477. {
  5478. .name = LPASS_BE_SLIMBUS_3_RX,
  5479. .stream_name = "Slimbus3 Playback",
  5480. .cpu_dai_name = "msm-dai-q6-dev.16390",
  5481. .platform_name = "msm-pcm-routing",
  5482. .codec_name = "tasha_codec",
  5483. .codec_dai_name = "tasha_rx1",
  5484. .no_pcm = 1,
  5485. .dpcm_playback = 1,
  5486. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  5487. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5488. .ops = &msm_be_ops,
  5489. /* dai link has playback support */
  5490. .ignore_pmdown_time = 1,
  5491. .ignore_suspend = 1,
  5492. },
  5493. {
  5494. .name = LPASS_BE_SLIMBUS_3_TX,
  5495. .stream_name = "Slimbus3 Capture",
  5496. .cpu_dai_name = "msm-dai-q6-dev.16391",
  5497. .platform_name = "msm-pcm-routing",
  5498. .codec_name = "tasha_codec",
  5499. .codec_dai_name = "tasha_tx1",
  5500. .no_pcm = 1,
  5501. .dpcm_capture = 1,
  5502. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  5503. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5504. .ops = &msm_be_ops,
  5505. .ignore_suspend = 1,
  5506. },
  5507. {
  5508. .name = LPASS_BE_SLIMBUS_4_RX,
  5509. .stream_name = "Slimbus4 Playback",
  5510. .cpu_dai_name = "msm-dai-q6-dev.16392",
  5511. .platform_name = "msm-pcm-routing",
  5512. .codec_name = "tasha_codec",
  5513. .codec_dai_name = "tasha_rx1",
  5514. .no_pcm = 1,
  5515. .dpcm_playback = 1,
  5516. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  5517. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5518. .ops = &msm_be_ops,
  5519. /* dai link has playback support */
  5520. .ignore_pmdown_time = 1,
  5521. .ignore_suspend = 1,
  5522. },
  5523. {
  5524. .name = LPASS_BE_SLIMBUS_5_RX,
  5525. .stream_name = "Slimbus5 Playback",
  5526. .cpu_dai_name = "msm-dai-q6-dev.16394",
  5527. .platform_name = "msm-pcm-routing",
  5528. .codec_name = "tasha_codec",
  5529. .codec_dai_name = "tasha_rx3",
  5530. .no_pcm = 1,
  5531. .dpcm_playback = 1,
  5532. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  5533. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5534. .ops = &msm_be_ops,
  5535. /* dai link has playback support */
  5536. .ignore_pmdown_time = 1,
  5537. .ignore_suspend = 1,
  5538. },
  5539. {
  5540. .name = LPASS_BE_SLIMBUS_6_RX,
  5541. .stream_name = "Slimbus6 Playback",
  5542. .cpu_dai_name = "msm-dai-q6-dev.16396",
  5543. .platform_name = "msm-pcm-routing",
  5544. .codec_name = "tasha_codec",
  5545. .codec_dai_name = "tasha_rx4",
  5546. .no_pcm = 1,
  5547. .dpcm_playback = 1,
  5548. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  5549. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5550. .ops = &msm_be_ops,
  5551. /* dai link has playback support */
  5552. .ignore_pmdown_time = 1,
  5553. .ignore_suspend = 1,
  5554. },
  5555. /* Slimbus VI Recording */
  5556. {
  5557. .name = LPASS_BE_SLIMBUS_TX_VI,
  5558. .stream_name = "Slimbus4 Capture",
  5559. .cpu_dai_name = "msm-dai-q6-dev.16393",
  5560. .platform_name = "msm-pcm-routing",
  5561. .codec_name = "tasha_codec",
  5562. .codec_dai_name = "tasha_vifeedback",
  5563. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  5564. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5565. .ops = &msm_be_ops,
  5566. .ignore_suspend = 1,
  5567. .no_pcm = 1,
  5568. .dpcm_capture = 1,
  5569. .ignore_pmdown_time = 1,
  5570. },
  5571. };
  5572. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5573. {
  5574. .name = LPASS_BE_SLIMBUS_7_RX,
  5575. .stream_name = "Slimbus7 Playback",
  5576. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5577. .platform_name = "msm-pcm-routing",
  5578. .codec_name = "btfmslim_slave",
  5579. /* BT codec driver determines capabilities based on
  5580. * dai name, bt codecdai name should always contains
  5581. * supported usecase information
  5582. */
  5583. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5584. .no_pcm = 1,
  5585. .dpcm_playback = 1,
  5586. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5587. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5588. .ops = &msm_wcn_ops,
  5589. /* dai link has playback support */
  5590. .ignore_pmdown_time = 1,
  5591. .ignore_suspend = 1,
  5592. },
  5593. {
  5594. .name = LPASS_BE_SLIMBUS_7_TX,
  5595. .stream_name = "Slimbus7 Capture",
  5596. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5597. .platform_name = "msm-pcm-routing",
  5598. .codec_name = "btfmslim_slave",
  5599. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5600. .no_pcm = 1,
  5601. .dpcm_capture = 1,
  5602. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5603. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5604. .ops = &msm_wcn_ops,
  5605. .ignore_suspend = 1,
  5606. },
  5607. {
  5608. .name = LPASS_BE_SLIMBUS_8_TX,
  5609. .stream_name = "Slimbus8 Capture",
  5610. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5611. .platform_name = "msm-pcm-routing",
  5612. .codec_name = "btfmslim_slave",
  5613. .codec_dai_name = "btfm_fm_slim_tx",
  5614. .no_pcm = 1,
  5615. .dpcm_capture = 1,
  5616. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5617. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5618. .init = &msm_wcn_init,
  5619. .ops = &msm_wcn_ops,
  5620. .ignore_suspend = 1,
  5621. },
  5622. };
  5623. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5624. {
  5625. .name = LPASS_BE_PRI_MI2S_RX,
  5626. .stream_name = "Primary MI2S Playback",
  5627. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5628. .platform_name = "msm-pcm-routing",
  5629. .codec_name = "msm-stub-codec.1",
  5630. .codec_dai_name = "msm-stub-rx",
  5631. .no_pcm = 1,
  5632. .dpcm_playback = 1,
  5633. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5634. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5635. .ops = &msm_mi2s_be_ops,
  5636. .ignore_suspend = 1,
  5637. .ignore_pmdown_time = 1,
  5638. },
  5639. {
  5640. .name = LPASS_BE_PRI_MI2S_TX,
  5641. .stream_name = "Primary MI2S Capture",
  5642. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5643. .platform_name = "msm-pcm-routing",
  5644. .codec_name = "msm-stub-codec.1",
  5645. .codec_dai_name = "msm-stub-tx",
  5646. .no_pcm = 1,
  5647. .dpcm_capture = 1,
  5648. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5649. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5650. .ops = &msm_mi2s_be_ops,
  5651. .ignore_suspend = 1,
  5652. },
  5653. {
  5654. .name = LPASS_BE_SEC_MI2S_RX,
  5655. .stream_name = "Secondary MI2S Playback",
  5656. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5657. .platform_name = "msm-pcm-routing",
  5658. .codec_name = "msm-stub-codec.1",
  5659. .codec_dai_name = "msm-stub-rx",
  5660. .no_pcm = 1,
  5661. .dpcm_playback = 1,
  5662. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5663. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5664. .ops = &msm_mi2s_be_ops,
  5665. .ignore_suspend = 1,
  5666. .ignore_pmdown_time = 1,
  5667. },
  5668. {
  5669. .name = LPASS_BE_SEC_MI2S_TX,
  5670. .stream_name = "Secondary MI2S Capture",
  5671. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5672. .platform_name = "msm-pcm-routing",
  5673. .codec_name = "msm-stub-codec.1",
  5674. .codec_dai_name = "msm-stub-tx",
  5675. .no_pcm = 1,
  5676. .dpcm_capture = 1,
  5677. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5678. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5679. .ops = &msm_mi2s_be_ops,
  5680. .ignore_suspend = 1,
  5681. },
  5682. {
  5683. .name = LPASS_BE_TERT_MI2S_RX,
  5684. .stream_name = "Tertiary MI2S Playback",
  5685. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5686. .platform_name = "msm-pcm-routing",
  5687. .codec_name = "msm-stub-codec.1",
  5688. .codec_dai_name = "msm-stub-rx",
  5689. .no_pcm = 1,
  5690. .dpcm_playback = 1,
  5691. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5692. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5693. .ops = &msm_mi2s_be_ops,
  5694. .ignore_suspend = 1,
  5695. .ignore_pmdown_time = 1,
  5696. },
  5697. {
  5698. .name = LPASS_BE_TERT_MI2S_TX,
  5699. .stream_name = "Tertiary MI2S Capture",
  5700. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5701. .platform_name = "msm-pcm-routing",
  5702. .codec_name = "msm-stub-codec.1",
  5703. .codec_dai_name = "msm-stub-tx",
  5704. .no_pcm = 1,
  5705. .dpcm_capture = 1,
  5706. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5707. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5708. .ops = &msm_mi2s_be_ops,
  5709. .ignore_suspend = 1,
  5710. },
  5711. {
  5712. .name = LPASS_BE_QUAT_MI2S_RX,
  5713. .stream_name = "Quaternary MI2S Playback",
  5714. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5715. .platform_name = "msm-pcm-routing",
  5716. .codec_name = "msm-stub-codec.1",
  5717. .codec_dai_name = "msm-stub-rx",
  5718. .no_pcm = 1,
  5719. .dpcm_playback = 1,
  5720. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5721. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5722. .ops = &msm_mi2s_be_ops,
  5723. .ignore_suspend = 1,
  5724. .ignore_pmdown_time = 1,
  5725. },
  5726. {
  5727. .name = LPASS_BE_QUAT_MI2S_TX,
  5728. .stream_name = "Quaternary MI2S Capture",
  5729. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5730. .platform_name = "msm-pcm-routing",
  5731. .codec_name = "msm-stub-codec.1",
  5732. .codec_dai_name = "msm-stub-tx",
  5733. .no_pcm = 1,
  5734. .dpcm_capture = 1,
  5735. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5736. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5737. .ops = &msm_mi2s_be_ops,
  5738. .ignore_suspend = 1,
  5739. },
  5740. {
  5741. .name = LPASS_BE_QUIN_MI2S_RX,
  5742. .stream_name = "Quinary MI2S Playback",
  5743. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5744. .platform_name = "msm-pcm-routing",
  5745. .codec_name = "msm-stub-codec.1",
  5746. .codec_dai_name = "msm-stub-rx",
  5747. .no_pcm = 1,
  5748. .dpcm_playback = 1,
  5749. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5750. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5751. .ops = &msm_mi2s_be_ops,
  5752. .ignore_suspend = 1,
  5753. .ignore_pmdown_time = 1,
  5754. },
  5755. {
  5756. .name = LPASS_BE_QUIN_MI2S_TX,
  5757. .stream_name = "Quinary MI2S Capture",
  5758. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5759. .platform_name = "msm-pcm-routing",
  5760. .codec_name = "msm-stub-codec.1",
  5761. .codec_dai_name = "msm-stub-tx",
  5762. .no_pcm = 1,
  5763. .dpcm_capture = 1,
  5764. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5765. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5766. .ops = &msm_mi2s_be_ops,
  5767. .ignore_suspend = 1,
  5768. },
  5769. };
  5770. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5771. /* Primary AUX PCM Backend DAI Links */
  5772. {
  5773. .name = LPASS_BE_AUXPCM_RX,
  5774. .stream_name = "AUX PCM Playback",
  5775. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5776. .platform_name = "msm-pcm-routing",
  5777. .codec_name = "msm-stub-codec.1",
  5778. .codec_dai_name = "msm-stub-rx",
  5779. .no_pcm = 1,
  5780. .dpcm_playback = 1,
  5781. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5782. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5783. .ignore_pmdown_time = 1,
  5784. .ignore_suspend = 1,
  5785. },
  5786. {
  5787. .name = LPASS_BE_AUXPCM_TX,
  5788. .stream_name = "AUX PCM Capture",
  5789. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5790. .platform_name = "msm-pcm-routing",
  5791. .codec_name = "msm-stub-codec.1",
  5792. .codec_dai_name = "msm-stub-tx",
  5793. .no_pcm = 1,
  5794. .dpcm_capture = 1,
  5795. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5796. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5797. .ignore_suspend = 1,
  5798. },
  5799. /* Secondary AUX PCM Backend DAI Links */
  5800. {
  5801. .name = LPASS_BE_SEC_AUXPCM_RX,
  5802. .stream_name = "Sec AUX PCM Playback",
  5803. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5804. .platform_name = "msm-pcm-routing",
  5805. .codec_name = "msm-stub-codec.1",
  5806. .codec_dai_name = "msm-stub-rx",
  5807. .no_pcm = 1,
  5808. .dpcm_playback = 1,
  5809. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5810. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5811. .ignore_pmdown_time = 1,
  5812. .ignore_suspend = 1,
  5813. },
  5814. {
  5815. .name = LPASS_BE_SEC_AUXPCM_TX,
  5816. .stream_name = "Sec AUX PCM Capture",
  5817. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5818. .platform_name = "msm-pcm-routing",
  5819. .codec_name = "msm-stub-codec.1",
  5820. .codec_dai_name = "msm-stub-tx",
  5821. .no_pcm = 1,
  5822. .dpcm_capture = 1,
  5823. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5824. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5825. .ignore_suspend = 1,
  5826. },
  5827. /* Tertiary AUX PCM Backend DAI Links */
  5828. {
  5829. .name = LPASS_BE_TERT_AUXPCM_RX,
  5830. .stream_name = "Tert AUX PCM Playback",
  5831. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5832. .platform_name = "msm-pcm-routing",
  5833. .codec_name = "msm-stub-codec.1",
  5834. .codec_dai_name = "msm-stub-rx",
  5835. .no_pcm = 1,
  5836. .dpcm_playback = 1,
  5837. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5838. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5839. .ignore_suspend = 1,
  5840. },
  5841. {
  5842. .name = LPASS_BE_TERT_AUXPCM_TX,
  5843. .stream_name = "Tert AUX PCM Capture",
  5844. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5845. .platform_name = "msm-pcm-routing",
  5846. .codec_name = "msm-stub-codec.1",
  5847. .codec_dai_name = "msm-stub-tx",
  5848. .no_pcm = 1,
  5849. .dpcm_capture = 1,
  5850. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5851. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5852. .ignore_suspend = 1,
  5853. },
  5854. /* Quaternary AUX PCM Backend DAI Links */
  5855. {
  5856. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5857. .stream_name = "Quat AUX PCM Playback",
  5858. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5859. .platform_name = "msm-pcm-routing",
  5860. .codec_name = "msm-stub-codec.1",
  5861. .codec_dai_name = "msm-stub-rx",
  5862. .no_pcm = 1,
  5863. .dpcm_playback = 1,
  5864. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5865. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5866. .ignore_pmdown_time = 1,
  5867. .ignore_suspend = 1,
  5868. },
  5869. {
  5870. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5871. .stream_name = "Quat AUX PCM Capture",
  5872. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5873. .platform_name = "msm-pcm-routing",
  5874. .codec_name = "msm-stub-codec.1",
  5875. .codec_dai_name = "msm-stub-tx",
  5876. .no_pcm = 1,
  5877. .dpcm_capture = 1,
  5878. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5879. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5880. .ignore_suspend = 1,
  5881. },
  5882. /* Quinary AUX PCM Backend DAI Links */
  5883. {
  5884. .name = LPASS_BE_QUIN_AUXPCM_RX,
  5885. .stream_name = "Quin AUX PCM Playback",
  5886. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5887. .platform_name = "msm-pcm-routing",
  5888. .codec_name = "msm-stub-codec.1",
  5889. .codec_dai_name = "msm-stub-rx",
  5890. .no_pcm = 1,
  5891. .dpcm_playback = 1,
  5892. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  5893. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5894. .ignore_pmdown_time = 1,
  5895. .ignore_suspend = 1,
  5896. },
  5897. {
  5898. .name = LPASS_BE_QUIN_AUXPCM_TX,
  5899. .stream_name = "Quin AUX PCM Capture",
  5900. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5901. .platform_name = "msm-pcm-routing",
  5902. .codec_name = "msm-stub-codec.1",
  5903. .codec_dai_name = "msm-stub-tx",
  5904. .no_pcm = 1,
  5905. .dpcm_capture = 1,
  5906. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  5907. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5908. .ignore_suspend = 1,
  5909. },
  5910. };
  5911. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  5912. /* WSA CDC DMA Backend DAI Links */
  5913. {
  5914. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  5915. .stream_name = "WSA CDC DMA0 Playback",
  5916. .cpu_dai_name = "msm-dai-cdc-dma.45056",
  5917. .platform_name = "msm-pcm-routing",
  5918. .codec_name = "bolero_codec",
  5919. .codec_dai_name = "wsa_macro_rx1",
  5920. .no_pcm = 1,
  5921. .dpcm_playback = 1,
  5922. .init = &msm_wsa_cdc_dma_init,
  5923. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  5924. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5925. .ignore_pmdown_time = 1,
  5926. .ignore_suspend = 1,
  5927. .ops = &msm_cdc_dma_be_ops,
  5928. },
  5929. {
  5930. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5931. .stream_name = "WSA CDC DMA0 Capture",
  5932. .cpu_dai_name = "msm-dai-cdc-dma.45057",
  5933. .platform_name = "msm-pcm-hostless",
  5934. .codec_name = "bolero_codec",
  5935. .codec_dai_name = "wsa_macro_vifeedback",
  5936. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5937. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5938. .ignore_suspend = 1,
  5939. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5940. .ops = &msm_cdc_dma_be_ops,
  5941. },
  5942. {
  5943. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  5944. .stream_name = "WSA CDC DMA1 Playback",
  5945. .cpu_dai_name = "msm-dai-cdc-dma.45058",
  5946. .platform_name = "msm-pcm-routing",
  5947. .codec_name = "bolero_codec",
  5948. .codec_dai_name = "wsa_macro_rx_mix",
  5949. .no_pcm = 1,
  5950. .dpcm_playback = 1,
  5951. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  5952. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5953. .ignore_pmdown_time = 1,
  5954. .ignore_suspend = 1,
  5955. .ops = &msm_cdc_dma_be_ops,
  5956. },
  5957. {
  5958. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  5959. .stream_name = "WSA CDC DMA1 Capture",
  5960. .cpu_dai_name = "msm-dai-cdc-dma.45059",
  5961. .platform_name = "msm-pcm-routing",
  5962. .codec_name = "bolero_codec",
  5963. .codec_dai_name = "wsa_macro_echo",
  5964. .no_pcm = 1,
  5965. .dpcm_capture = 1,
  5966. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  5967. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5968. .ignore_suspend = 1,
  5969. .ops = &msm_cdc_dma_be_ops,
  5970. },
  5971. {
  5972. .name = LPASS_BE_WSA_CDC_DMA_TX_2,
  5973. .stream_name = "WSA CDC DMA2 Capture",
  5974. .cpu_dai_name = "msm-dai-cdc-dma.45061",
  5975. .platform_name = "msm-pcm-routing",
  5976. .codec_name = "bolero_codec",
  5977. .codec_dai_name = "msm-stub-tx",
  5978. .no_pcm = 1,
  5979. .dpcm_capture = 1,
  5980. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2,
  5981. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5982. .ignore_suspend = 1,
  5983. .ops = &msm_cdc_dma_be_ops,
  5984. },
  5985. };
  5986. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  5987. {
  5988. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  5989. .stream_name = "VA CDC DMA0 Capture",
  5990. .cpu_dai_name = "msm-dai-cdc-dma.49153",
  5991. .platform_name = "msm-pcm-routing",
  5992. .codec_name = "bolero_codec",
  5993. .codec_dai_name = "va_macro_tx1",
  5994. .no_pcm = 1,
  5995. .dpcm_capture = 1,
  5996. .init = &msm_va_cdc_dma_init,
  5997. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  5998. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5999. .ignore_suspend = 1,
  6000. .ops = &msm_cdc_dma_be_ops,
  6001. },
  6002. {
  6003. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6004. .stream_name = "VA CDC DMA1 Capture",
  6005. .cpu_dai_name = "msm-dai-cdc-dma.49155",
  6006. .platform_name = "msm-pcm-routing",
  6007. .codec_name = "bolero_codec",
  6008. .codec_dai_name = "va_macro_tx2",
  6009. .no_pcm = 1,
  6010. .dpcm_capture = 1,
  6011. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6012. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6013. .ignore_suspend = 1,
  6014. .ops = &msm_cdc_dma_be_ops,
  6015. },
  6016. };
  6017. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6018. ARRAY_SIZE(msm_common_dai_links) +
  6019. ARRAY_SIZE(msm_tasha_fe_dai_links) +
  6020. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6021. ARRAY_SIZE(msm_common_be_dai_links) +
  6022. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6023. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6024. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6025. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6026. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6027. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links)];
  6028. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6029. {
  6030. int ret = 0;
  6031. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6032. &service_nb);
  6033. if (ret < 0)
  6034. pr_err("%s: Audio notifier register failed ret = %d\n",
  6035. __func__, ret);
  6036. return ret;
  6037. }
  6038. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6039. .name = "qcs405-snd-card",
  6040. .controls = msm_snd_controls,
  6041. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6042. };
  6043. static int msm_populate_dai_link_component_of_node(
  6044. struct snd_soc_card *card)
  6045. {
  6046. int i, index, ret = 0;
  6047. struct device *cdev = card->dev;
  6048. struct snd_soc_dai_link *dai_link = card->dai_link;
  6049. struct device_node *np;
  6050. if (!cdev) {
  6051. pr_err("%s: Sound card device memory NULL\n", __func__);
  6052. return -ENODEV;
  6053. }
  6054. for (i = 0; i < card->num_links; i++) {
  6055. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6056. continue;
  6057. /* populate platform_of_node for snd card dai links */
  6058. if (dai_link[i].platform_name &&
  6059. !dai_link[i].platform_of_node) {
  6060. index = of_property_match_string(cdev->of_node,
  6061. "asoc-platform-names",
  6062. dai_link[i].platform_name);
  6063. if (index < 0) {
  6064. pr_err("%s: No match found for platform name: %s\n",
  6065. __func__, dai_link[i].platform_name);
  6066. ret = index;
  6067. goto err;
  6068. }
  6069. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6070. index);
  6071. if (!np) {
  6072. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6073. __func__, dai_link[i].platform_name,
  6074. index);
  6075. ret = -ENODEV;
  6076. goto err;
  6077. }
  6078. dai_link[i].platform_of_node = np;
  6079. dai_link[i].platform_name = NULL;
  6080. }
  6081. /* populate cpu_of_node for snd card dai links */
  6082. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6083. index = of_property_match_string(cdev->of_node,
  6084. "asoc-cpu-names",
  6085. dai_link[i].cpu_dai_name);
  6086. if (index >= 0) {
  6087. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6088. index);
  6089. if (!np) {
  6090. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6091. __func__,
  6092. dai_link[i].cpu_dai_name);
  6093. ret = -ENODEV;
  6094. goto err;
  6095. }
  6096. dai_link[i].cpu_of_node = np;
  6097. dai_link[i].cpu_dai_name = NULL;
  6098. }
  6099. }
  6100. /* populate codec_of_node for snd card dai links */
  6101. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6102. index = of_property_match_string(cdev->of_node,
  6103. "asoc-codec-names",
  6104. dai_link[i].codec_name);
  6105. if (index < 0)
  6106. continue;
  6107. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6108. index);
  6109. if (!np) {
  6110. pr_err("%s: retrieving phandle for codec %s failed\n",
  6111. __func__, dai_link[i].codec_name);
  6112. ret = -ENODEV;
  6113. goto err;
  6114. }
  6115. dai_link[i].codec_of_node = np;
  6116. dai_link[i].codec_name = NULL;
  6117. }
  6118. }
  6119. err:
  6120. return ret;
  6121. }
  6122. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  6123. {
  6124. return 0;
  6125. }
  6126. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  6127. struct snd_pcm_hw_params *params)
  6128. {
  6129. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  6130. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  6131. int ret = 0;
  6132. unsigned int rx_ch[] = {144, 145, 146, 147, 148, 149, 150,
  6133. 151};
  6134. unsigned int tx_ch[] = {128, 129, 130, 131, 132, 133,
  6135. 134, 135, 136, 137, 138, 139,
  6136. 140, 141, 142, 143};
  6137. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  6138. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  6139. slim_rx_cfg[SLIM_RX_0].channels,
  6140. rx_ch);
  6141. if (ret < 0)
  6142. pr_err("%s: RX failed to set cpu chan map error %d\n",
  6143. __func__, ret);
  6144. } else {
  6145. ret = snd_soc_dai_set_channel_map(cpu_dai,
  6146. slim_tx_cfg[SLIM_TX_0].channels,
  6147. tx_ch, 0, 0);
  6148. if (ret < 0)
  6149. pr_err("%s: TX failed to set cpu chan map error %d\n",
  6150. __func__, ret);
  6151. }
  6152. return ret;
  6153. }
  6154. static struct snd_soc_ops msm_stub_be_ops = {
  6155. .hw_params = msm_snd_stub_hw_params,
  6156. };
  6157. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6158. /* FrontEnd DAI Links */
  6159. {
  6160. .name = "MSMSTUB Media1",
  6161. .stream_name = "MultiMedia1",
  6162. .cpu_dai_name = "MultiMedia1",
  6163. .platform_name = "msm-pcm-dsp.0",
  6164. .dynamic = 1,
  6165. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6166. .dpcm_playback = 1,
  6167. .dpcm_capture = 1,
  6168. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6169. SND_SOC_DPCM_TRIGGER_POST},
  6170. .codec_dai_name = "snd-soc-dummy-dai",
  6171. .codec_name = "snd-soc-dummy",
  6172. .ignore_suspend = 1,
  6173. /* this dainlink has playback support */
  6174. .ignore_pmdown_time = 1,
  6175. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6176. },
  6177. };
  6178. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6179. /* Backend DAI Links */
  6180. {
  6181. .name = LPASS_BE_SLIMBUS_0_RX,
  6182. .stream_name = "Slimbus Playback",
  6183. .cpu_dai_name = "msm-dai-q6-dev.16384",
  6184. .platform_name = "msm-pcm-routing",
  6185. .codec_name = "msm-stub-codec.1",
  6186. .codec_dai_name = "msm-stub-rx",
  6187. .no_pcm = 1,
  6188. .dpcm_playback = 1,
  6189. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  6190. .init = &msm_audrx_stub_init,
  6191. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6192. .ignore_pmdown_time = 1, /* dai link has playback support */
  6193. .ignore_suspend = 1,
  6194. .ops = &msm_stub_be_ops,
  6195. },
  6196. {
  6197. .name = LPASS_BE_SLIMBUS_0_TX,
  6198. .stream_name = "Slimbus Capture",
  6199. .cpu_dai_name = "msm-dai-q6-dev.16385",
  6200. .platform_name = "msm-pcm-routing",
  6201. .codec_name = "msm-stub-codec.1",
  6202. .codec_dai_name = "msm-stub-tx",
  6203. .no_pcm = 1,
  6204. .dpcm_capture = 1,
  6205. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  6206. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6207. .ignore_suspend = 1,
  6208. .ops = &msm_stub_be_ops,
  6209. },
  6210. };
  6211. static struct snd_soc_dai_link msm_stub_dai_links[
  6212. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6213. ARRAY_SIZE(msm_stub_be_dai_links)];
  6214. struct snd_soc_card snd_soc_card_stub_msm = {
  6215. .name = "qcs405-stub-snd-card",
  6216. };
  6217. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6218. { .compatible = "qcom,qcs405-asoc-snd",
  6219. .data = "codec"},
  6220. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6221. .data = "stub_codec"},
  6222. {},
  6223. };
  6224. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6225. {
  6226. struct snd_soc_card *card = NULL;
  6227. struct snd_soc_dai_link *dailink;
  6228. int total_links = 0;
  6229. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6230. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6231. const struct of_device_id *match;
  6232. int rc = 0;
  6233. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6234. if (!match) {
  6235. dev_err(dev, "%s: No DT match found for sound card\n",
  6236. __func__);
  6237. return NULL;
  6238. }
  6239. if (!strcmp(match->data, "codec")) {
  6240. card = &snd_soc_card_qcs405_msm;
  6241. memcpy(msm_qcs405_dai_links + total_links,
  6242. msm_common_dai_links,
  6243. sizeof(msm_common_dai_links));
  6244. total_links += ARRAY_SIZE(msm_common_dai_links);
  6245. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6246. &tasha_codec);
  6247. if (rc) {
  6248. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6249. __func__);
  6250. } else {
  6251. if (tasha_codec) {
  6252. dev_dbg(dev, "%s(): Tasha codec is present\n",
  6253. __func__);
  6254. card->late_probe =
  6255. msm_snd_card_tasha_late_probe;
  6256. memcpy(msm_qcs405_dai_links + total_links,
  6257. msm_tasha_fe_dai_links,
  6258. sizeof(msm_tasha_fe_dai_links));
  6259. total_links +=
  6260. ARRAY_SIZE(msm_tasha_fe_dai_links);
  6261. }
  6262. }
  6263. memcpy(msm_qcs405_dai_links + total_links,
  6264. msm_common_misc_fe_dai_links,
  6265. sizeof(msm_common_misc_fe_dai_links));
  6266. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6267. memcpy(msm_qcs405_dai_links + total_links,
  6268. msm_common_be_dai_links,
  6269. sizeof(msm_common_be_dai_links));
  6270. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6271. if (tasha_codec) {
  6272. memcpy(msm_qcs405_dai_links + total_links,
  6273. msm_tasha_be_dai_links,
  6274. sizeof(msm_tasha_be_dai_links));
  6275. total_links += ARRAY_SIZE(msm_tasha_be_dai_links);
  6276. }
  6277. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6278. &va_bolero_codec);
  6279. if (rc) {
  6280. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6281. __func__);
  6282. } else {
  6283. if (va_bolero_codec) {
  6284. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6285. __func__);
  6286. memcpy(msm_qcs405_dai_links + total_links,
  6287. msm_va_cdc_dma_be_dai_links,
  6288. sizeof(msm_va_cdc_dma_be_dai_links));
  6289. total_links +=
  6290. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6291. }
  6292. }
  6293. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6294. &wsa_bolero_codec);
  6295. if (rc) {
  6296. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6297. __func__);
  6298. } else {
  6299. if (wsa_bolero_codec) {
  6300. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6301. __func__);
  6302. memcpy(msm_qcs405_dai_links + total_links,
  6303. msm_wsa_cdc_dma_be_dai_links,
  6304. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6305. total_links +=
  6306. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6307. }
  6308. }
  6309. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6310. &mi2s_audio_intf);
  6311. if (rc) {
  6312. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6313. __func__);
  6314. } else {
  6315. if (mi2s_audio_intf) {
  6316. memcpy(msm_qcs405_dai_links + total_links,
  6317. msm_mi2s_be_dai_links,
  6318. sizeof(msm_mi2s_be_dai_links));
  6319. total_links +=
  6320. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6321. }
  6322. }
  6323. rc = of_property_read_u32(dev->of_node,
  6324. "qcom,auxpcm-audio-intf",
  6325. &auxpcm_audio_intf);
  6326. if (rc) {
  6327. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6328. __func__);
  6329. } else {
  6330. if (auxpcm_audio_intf) {
  6331. memcpy(msm_qcs405_dai_links + total_links,
  6332. msm_auxpcm_be_dai_links,
  6333. sizeof(msm_auxpcm_be_dai_links));
  6334. total_links +=
  6335. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6336. }
  6337. }
  6338. dailink = msm_qcs405_dai_links;
  6339. } else if (!strcmp(match->data, "stub_codec")) {
  6340. card = &snd_soc_card_stub_msm;
  6341. memcpy(msm_stub_dai_links + total_links,
  6342. msm_stub_fe_dai_links,
  6343. sizeof(msm_stub_fe_dai_links));
  6344. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6345. memcpy(msm_stub_dai_links + total_links,
  6346. msm_stub_be_dai_links,
  6347. sizeof(msm_stub_be_dai_links));
  6348. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6349. dailink = msm_stub_dai_links;
  6350. }
  6351. if (card) {
  6352. card->dai_link = dailink;
  6353. card->num_links = total_links;
  6354. }
  6355. return card;
  6356. }
  6357. static int msm_wsa881x_init(struct snd_soc_component *component)
  6358. {
  6359. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106};
  6360. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107};
  6361. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6362. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6363. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6364. struct msm_asoc_mach_data *pdata;
  6365. struct snd_soc_dapm_context *dapm;
  6366. int ret = 0;
  6367. if (!codec) {
  6368. pr_err("%s codec is NULL\n", __func__);
  6369. return -EINVAL;
  6370. }
  6371. dapm = snd_soc_codec_get_dapm(codec);
  6372. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6373. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  6374. __func__, codec->component.name);
  6375. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  6376. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6377. &ch_rate[0]);
  6378. if (dapm->component) {
  6379. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6380. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6381. }
  6382. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6383. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  6384. __func__, codec->component.name);
  6385. wsa881x_set_channel_map(codec, &spkright_ports[0],
  6386. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6387. &ch_rate[0]);
  6388. if (dapm->component) {
  6389. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6390. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6391. }
  6392. } else {
  6393. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  6394. codec->component.name);
  6395. ret = -EINVAL;
  6396. goto err;
  6397. }
  6398. pdata = snd_soc_card_get_drvdata(component->card);
  6399. if (pdata && pdata->codec_root)
  6400. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6401. codec);
  6402. err:
  6403. return ret;
  6404. }
  6405. static int msm_init_wsa_dev(struct platform_device *pdev,
  6406. struct snd_soc_card *card)
  6407. {
  6408. struct device_node *wsa_of_node;
  6409. u32 wsa_max_devs;
  6410. u32 wsa_dev_cnt;
  6411. int i;
  6412. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6413. const char *wsa_auxdev_name_prefix[1];
  6414. char *dev_name_str = NULL;
  6415. int found = 0;
  6416. int ret = 0;
  6417. /* Get maximum WSA device count for this platform */
  6418. ret = of_property_read_u32(pdev->dev.of_node,
  6419. "qcom,wsa-max-devs", &wsa_max_devs);
  6420. if (ret) {
  6421. dev_info(&pdev->dev,
  6422. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6423. __func__, pdev->dev.of_node->full_name, ret);
  6424. card->num_aux_devs = 0;
  6425. return 0;
  6426. }
  6427. if (wsa_max_devs == 0) {
  6428. dev_warn(&pdev->dev,
  6429. "%s: Max WSA devices is 0 for this target?\n",
  6430. __func__);
  6431. card->num_aux_devs = 0;
  6432. return 0;
  6433. }
  6434. /* Get count of WSA device phandles for this platform */
  6435. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6436. "qcom,wsa-devs", NULL);
  6437. if (wsa_dev_cnt == -ENOENT) {
  6438. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6439. __func__);
  6440. goto err;
  6441. } else if (wsa_dev_cnt <= 0) {
  6442. dev_err(&pdev->dev,
  6443. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6444. __func__, wsa_dev_cnt);
  6445. ret = -EINVAL;
  6446. goto err;
  6447. }
  6448. /*
  6449. * Expect total phandles count to be NOT less than maximum possible
  6450. * WSA count. However, if it is less, then assign same value to
  6451. * max count as well.
  6452. */
  6453. if (wsa_dev_cnt < wsa_max_devs) {
  6454. dev_dbg(&pdev->dev,
  6455. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6456. __func__, wsa_max_devs, wsa_dev_cnt);
  6457. wsa_max_devs = wsa_dev_cnt;
  6458. }
  6459. /* Make sure prefix string passed for each WSA device */
  6460. ret = of_property_count_strings(pdev->dev.of_node,
  6461. "qcom,wsa-aux-dev-prefix");
  6462. if (ret != wsa_dev_cnt) {
  6463. dev_err(&pdev->dev,
  6464. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6465. __func__, wsa_dev_cnt, ret);
  6466. ret = -EINVAL;
  6467. goto err;
  6468. }
  6469. /*
  6470. * Alloc mem to store phandle and index info of WSA device, if already
  6471. * registered with ALSA core
  6472. */
  6473. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6474. sizeof(struct msm_wsa881x_dev_info),
  6475. GFP_KERNEL);
  6476. if (!wsa881x_dev_info) {
  6477. ret = -ENOMEM;
  6478. goto err;
  6479. }
  6480. /*
  6481. * search and check whether all WSA devices are already
  6482. * registered with ALSA core or not. If found a node, store
  6483. * the node and the index in a local array of struct for later
  6484. * use.
  6485. */
  6486. for (i = 0; i < wsa_dev_cnt; i++) {
  6487. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6488. "qcom,wsa-devs", i);
  6489. if (unlikely(!wsa_of_node)) {
  6490. /* we should not be here */
  6491. dev_err(&pdev->dev,
  6492. "%s: wsa dev node is not present\n",
  6493. __func__);
  6494. ret = -EINVAL;
  6495. goto err_free_dev_info;
  6496. }
  6497. if (soc_find_component(wsa_of_node, NULL)) {
  6498. /* WSA device registered with ALSA core */
  6499. wsa881x_dev_info[found].of_node = wsa_of_node;
  6500. wsa881x_dev_info[found].index = i;
  6501. found++;
  6502. if (found == wsa_max_devs)
  6503. break;
  6504. }
  6505. }
  6506. if (found < wsa_max_devs) {
  6507. dev_dbg(&pdev->dev,
  6508. "%s: failed to find %d components. Found only %d\n",
  6509. __func__, wsa_max_devs, found);
  6510. return -EPROBE_DEFER;
  6511. }
  6512. dev_info(&pdev->dev,
  6513. "%s: found %d wsa881x devices registered with ALSA core\n",
  6514. __func__, found);
  6515. card->num_aux_devs = wsa_max_devs;
  6516. card->num_configs = wsa_max_devs;
  6517. /* Alloc array of AUX devs struct */
  6518. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6519. sizeof(struct snd_soc_aux_dev),
  6520. GFP_KERNEL);
  6521. if (!msm_aux_dev) {
  6522. ret = -ENOMEM;
  6523. goto err_free_dev_info;
  6524. }
  6525. /* Alloc array of codec conf struct */
  6526. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6527. sizeof(struct snd_soc_codec_conf),
  6528. GFP_KERNEL);
  6529. if (!msm_codec_conf) {
  6530. ret = -ENOMEM;
  6531. goto err_free_aux_dev;
  6532. }
  6533. for (i = 0; i < card->num_aux_devs; i++) {
  6534. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6535. GFP_KERNEL);
  6536. if (!dev_name_str) {
  6537. ret = -ENOMEM;
  6538. goto err_free_cdc_conf;
  6539. }
  6540. ret = of_property_read_string_index(pdev->dev.of_node,
  6541. "qcom,wsa-aux-dev-prefix",
  6542. wsa881x_dev_info[i].index,
  6543. wsa_auxdev_name_prefix);
  6544. if (ret) {
  6545. dev_err(&pdev->dev,
  6546. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  6547. __func__, ret);
  6548. ret = -EINVAL;
  6549. goto err_free_dev_name_str;
  6550. }
  6551. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  6552. msm_aux_dev[i].name = dev_name_str;
  6553. msm_aux_dev[i].codec_name = NULL;
  6554. msm_aux_dev[i].codec_of_node =
  6555. wsa881x_dev_info[i].of_node;
  6556. msm_aux_dev[i].init = msm_wsa881x_init;
  6557. msm_codec_conf[i].dev_name = NULL;
  6558. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  6559. msm_codec_conf[i].of_node =
  6560. wsa881x_dev_info[i].of_node;
  6561. }
  6562. card->codec_conf = msm_codec_conf;
  6563. card->aux_dev = msm_aux_dev;
  6564. return 0;
  6565. err_free_dev_name_str:
  6566. devm_kfree(&pdev->dev, dev_name_str);
  6567. err_free_cdc_conf:
  6568. devm_kfree(&pdev->dev, msm_codec_conf);
  6569. err_free_aux_dev:
  6570. devm_kfree(&pdev->dev, msm_aux_dev);
  6571. err_free_dev_info:
  6572. devm_kfree(&pdev->dev, wsa881x_dev_info);
  6573. err:
  6574. return ret;
  6575. }
  6576. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  6577. {
  6578. int count;
  6579. u32 mi2s_master_slave[MI2S_MAX];
  6580. int ret;
  6581. for (count = 0; count < MI2S_MAX; count++) {
  6582. mutex_init(&mi2s_intf_conf[count].lock);
  6583. mi2s_intf_conf[count].ref_cnt = 0;
  6584. }
  6585. ret = of_property_read_u32_array(pdev->dev.of_node,
  6586. "qcom,msm-mi2s-master",
  6587. mi2s_master_slave, MI2S_MAX);
  6588. if (ret) {
  6589. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  6590. __func__);
  6591. } else {
  6592. for (count = 0; count < MI2S_MAX; count++) {
  6593. mi2s_intf_conf[count].msm_is_mi2s_master =
  6594. mi2s_master_slave[count];
  6595. }
  6596. }
  6597. }
  6598. static void msm_i2s_auxpcm_deinit(void)
  6599. {
  6600. int count;
  6601. for (count = 0; count < MI2S_MAX; count++) {
  6602. mutex_destroy(&mi2s_intf_conf[count].lock);
  6603. mi2s_intf_conf[count].ref_cnt = 0;
  6604. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  6605. }
  6606. }
  6607. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6608. {
  6609. struct snd_soc_card *card;
  6610. struct msm_asoc_mach_data *pdata;
  6611. int ret;
  6612. if (!pdev->dev.of_node) {
  6613. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  6614. return -EINVAL;
  6615. }
  6616. pdata = devm_kzalloc(&pdev->dev,
  6617. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6618. if (!pdata)
  6619. return -ENOMEM;
  6620. card = populate_snd_card_dailinks(&pdev->dev);
  6621. if (!card) {
  6622. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6623. ret = -EINVAL;
  6624. goto err;
  6625. }
  6626. card->dev = &pdev->dev;
  6627. platform_set_drvdata(pdev, card);
  6628. snd_soc_card_set_drvdata(card, pdata);
  6629. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6630. if (ret) {
  6631. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  6632. ret);
  6633. goto err;
  6634. }
  6635. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6636. if (ret) {
  6637. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  6638. ret);
  6639. goto err;
  6640. }
  6641. ret = msm_populate_dai_link_component_of_node(card);
  6642. if (ret) {
  6643. ret = -EPROBE_DEFER;
  6644. goto err;
  6645. }
  6646. ret = msm_init_wsa_dev(pdev, card);
  6647. if (ret)
  6648. goto err;
  6649. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6650. "qcom,cdc-dmic01-gpios",
  6651. 0);
  6652. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6653. "qcom,cdc-dmic23-gpios",
  6654. 0);
  6655. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6656. "qcom,cdc-dmic45-gpios",
  6657. 0);
  6658. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6659. "qcom,cdc-dmic67-gpios",
  6660. 0);
  6661. ret = devm_snd_soc_register_card(&pdev->dev, card);
  6662. if (ret == -EPROBE_DEFER) {
  6663. if (codec_reg_done)
  6664. ret = -EINVAL;
  6665. goto err;
  6666. } else if (ret) {
  6667. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  6668. ret);
  6669. goto err;
  6670. }
  6671. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  6672. spdev = pdev;
  6673. /* Parse pinctrl info from devicetree */
  6674. ret = msm_get_pinctrl(pdev);
  6675. if (!ret) {
  6676. pr_debug("%s: pinctrl parsing successful\n", __func__);
  6677. } else {
  6678. dev_dbg(&pdev->dev,
  6679. "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
  6680. __func__, ret);
  6681. ret = 0;
  6682. }
  6683. msm_i2s_auxpcm_init(pdev);
  6684. is_initial_boot = true;
  6685. return 0;
  6686. err:
  6687. msm_release_pinctrl(pdev);
  6688. return ret;
  6689. }
  6690. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6691. {
  6692. audio_notifier_deregister("qcs405");
  6693. msm_i2s_auxpcm_deinit();
  6694. msm_release_pinctrl(pdev);
  6695. return 0;
  6696. }
  6697. static struct platform_driver qcs405_asoc_machine_driver = {
  6698. .driver = {
  6699. .name = DRV_NAME,
  6700. .owner = THIS_MODULE,
  6701. .pm = &snd_soc_pm_ops,
  6702. .of_match_table = qcs405_asoc_machine_of_match,
  6703. },
  6704. .probe = msm_asoc_machine_probe,
  6705. .remove = msm_asoc_machine_remove,
  6706. };
  6707. module_platform_driver(qcs405_asoc_machine_driver);
  6708. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  6709. MODULE_LICENSE("GPL v2");
  6710. MODULE_ALIAS("platform:" DRV_NAME);
  6711. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);