hal_be_generic_api.h 119 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_BE_GENERIC_API_H_
  20. #define _HAL_BE_GENERIC_API_H_
  21. #include <hal_be_hw_headers.h>
  22. #include "hal_be_tx.h"
  23. #include "hal_be_reo.h"
  24. #include <hal_api_mon.h>
  25. #include <hal_generic_api.h>
  26. #include "txmon_tlvs.h"
  27. /*
  28. * Debug macro to print the TLV header tag
  29. */
  30. #define SHOW_DEFINED(x) do {} while (0)
  31. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  32. static inline void
  33. hal_tx_comp_get_buffer_timestamp_be(void *desc,
  34. struct hal_tx_completion_status *ts)
  35. {
  36. ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  37. BUFFER_TIMESTAMP);
  38. }
  39. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */
  40. static inline void
  41. hal_tx_comp_get_buffer_timestamp_be(void *desc,
  42. struct hal_tx_completion_status *ts)
  43. {
  44. }
  45. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */
  46. /**
  47. * hal_tx_comp_get_status_generic_be() - TQM Release reason
  48. * @desc: WBM descriptor
  49. * @ts1: completion ring Tx status
  50. * @hal: hal_soc
  51. *
  52. * This function will parse the WBM completion descriptor and populate in
  53. * HAL structure
  54. *
  55. * Return: none
  56. */
  57. static inline void
  58. hal_tx_comp_get_status_generic_be(void *desc, void *ts1,
  59. struct hal_soc *hal)
  60. {
  61. uint8_t rate_stats_valid = 0;
  62. uint32_t rate_stats = 0;
  63. struct hal_tx_completion_status *ts =
  64. (struct hal_tx_completion_status *)ts1;
  65. ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  66. TQM_STATUS_NUMBER);
  67. ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  68. ACK_FRAME_RSSI);
  69. ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  70. FIRST_MSDU);
  71. ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  72. LAST_MSDU);
  73. #if 0
  74. // TODO - This has to be calculated form first and last msdu
  75. ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc,
  76. WBM2SW_COMPLETION_RING_TX,
  77. MSDU_PART_OF_AMSDU);
  78. #endif
  79. ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  80. SW_PEER_ID);
  81. ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID);
  82. ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  83. TRANSMIT_COUNT);
  84. rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS);
  85. rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO,
  86. TX_RATE_STATS_INFO_VALID, rate_stats);
  87. ts->valid = rate_stats_valid;
  88. if (rate_stats_valid) {
  89. ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW,
  90. rate_stats);
  91. ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO,
  92. TRANSMIT_PKT_TYPE, rate_stats);
  93. ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO,
  94. TRANSMIT_STBC, rate_stats);
  95. ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC,
  96. rate_stats);
  97. ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI,
  98. rate_stats);
  99. ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS,
  100. rate_stats);
  101. ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION,
  102. rate_stats);
  103. ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU,
  104. rate_stats);
  105. }
  106. ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc);
  107. ts->status = hal_tx_comp_get_release_reason(
  108. desc,
  109. hal_soc_to_hal_soc_handle(hal));
  110. ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
  111. TX_RATE_STATS_INFO_TX_RATE_STATS);
  112. hal_tx_comp_get_buffer_timestamp_be(desc, ts);
  113. }
  114. /**
  115. * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table
  116. * @soc: HAL SoC context
  117. * @map: PCP-TID mapping table
  118. *
  119. * PCP are mapped to 8 TID values using TID values programmed
  120. * in one set of mapping registers PCP_TID_MAP_<0 to 6>
  121. * The mapping register has TID mapping for 8 PCP values
  122. *
  123. * Return: none
  124. */
  125. static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map)
  126. {
  127. uint32_t addr, value;
  128. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  129. MAC_TCL_REG_REG_BASE);
  130. value = (map[0] |
  131. (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) |
  132. (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) |
  133. (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) |
  134. (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) |
  135. (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) |
  136. (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) |
  137. (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT));
  138. HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  139. }
  140. /**
  141. * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with
  142. * value received from user-space
  143. * @soc: HAL SoC context
  144. * @pcp: pcp value
  145. * @tid : tid value
  146. *
  147. * Return: void
  148. */
  149. static void
  150. hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc,
  151. uint8_t pcp, uint8_t tid)
  152. {
  153. uint32_t addr, value, regval;
  154. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  155. MAC_TCL_REG_REG_BASE);
  156. value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp);
  157. /* Read back previous PCP TID config and update
  158. * with new config.
  159. */
  160. regval = HAL_REG_READ(soc, addr);
  161. regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp));
  162. regval |= value;
  163. HAL_REG_WRITE(soc, addr,
  164. (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  165. }
  166. /**
  167. * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority
  168. * @soc: HAL SoC context
  169. * @value: priority value
  170. *
  171. * Return: void
  172. */
  173. static
  174. void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value)
  175. {
  176. uint32_t addr;
  177. addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR(
  178. MAC_TCL_REG_REG_BASE);
  179. HAL_REG_WRITE(soc, addr,
  180. (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK));
  181. }
  182. /**
  183. * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size
  184. * @rx_pkt_tlv_size: TLV size for regular RX packets
  185. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  186. *
  187. * Return: size of rx pkt tlv before the actual data
  188. */
  189. static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size,
  190. uint16_t *rx_mon_pkt_tlv_size)
  191. {
  192. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  193. /* For now mon pkt tlv is same as rx pkt tlv */
  194. *rx_mon_pkt_tlv_size = MON_RX_PKT_TLVS_LEN;
  195. }
  196. /**
  197. * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST
  198. * @rx_fst: Pointer to the Rx Flow Search Table
  199. * @hal_hash: HAL 5 tuple hash
  200. * @flow_tuple_info: 5-tuple info of the flow returned to the caller
  201. *
  202. * Return: Success/Failure
  203. */
  204. static void *
  205. hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash,
  206. uint8_t *flow_tuple_info)
  207. {
  208. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  209. void *hal_fse = NULL;
  210. struct hal_flow_tuple_info *tuple_info
  211. = (struct hal_flow_tuple_info *)flow_tuple_info;
  212. hal_fse = (uint8_t *)fst->base_vaddr +
  213. (hal_hash * HAL_RX_FST_ENTRY_SIZE);
  214. if (!hal_fse || !tuple_info)
  215. return NULL;
  216. if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY, VALID))
  217. return NULL;
  218. tuple_info->src_ip_127_96 =
  219. qdf_ntohl(HAL_GET_FLD(hal_fse,
  220. RX_FLOW_SEARCH_ENTRY,
  221. SRC_IP_127_96));
  222. tuple_info->src_ip_95_64 =
  223. qdf_ntohl(HAL_GET_FLD(hal_fse,
  224. RX_FLOW_SEARCH_ENTRY,
  225. SRC_IP_95_64));
  226. tuple_info->src_ip_63_32 =
  227. qdf_ntohl(HAL_GET_FLD(hal_fse,
  228. RX_FLOW_SEARCH_ENTRY,
  229. SRC_IP_63_32));
  230. tuple_info->src_ip_31_0 =
  231. qdf_ntohl(HAL_GET_FLD(hal_fse,
  232. RX_FLOW_SEARCH_ENTRY,
  233. SRC_IP_31_0));
  234. tuple_info->dest_ip_127_96 =
  235. qdf_ntohl(HAL_GET_FLD(hal_fse,
  236. RX_FLOW_SEARCH_ENTRY,
  237. DEST_IP_127_96));
  238. tuple_info->dest_ip_95_64 =
  239. qdf_ntohl(HAL_GET_FLD(hal_fse,
  240. RX_FLOW_SEARCH_ENTRY,
  241. DEST_IP_95_64));
  242. tuple_info->dest_ip_63_32 =
  243. qdf_ntohl(HAL_GET_FLD(hal_fse,
  244. RX_FLOW_SEARCH_ENTRY,
  245. DEST_IP_63_32));
  246. tuple_info->dest_ip_31_0 =
  247. qdf_ntohl(HAL_GET_FLD(hal_fse,
  248. RX_FLOW_SEARCH_ENTRY,
  249. DEST_IP_31_0));
  250. tuple_info->dest_port = HAL_GET_FLD(hal_fse,
  251. RX_FLOW_SEARCH_ENTRY,
  252. DEST_PORT);
  253. tuple_info->src_port = HAL_GET_FLD(hal_fse,
  254. RX_FLOW_SEARCH_ENTRY,
  255. SRC_PORT);
  256. tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
  257. RX_FLOW_SEARCH_ENTRY,
  258. L4_PROTOCOL);
  259. return hal_fse;
  260. }
  261. /**
  262. * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST
  263. * @rx_fst: Pointer to the Rx Flow Search Table
  264. * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
  265. *
  266. * Return: Success/Failure
  267. */
  268. static QDF_STATUS
  269. hal_rx_flow_delete_entry_be(uint8_t *rx_fst, void *hal_rx_fse)
  270. {
  271. uint8_t *fse = (uint8_t *)hal_rx_fse;
  272. if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID))
  273. return QDF_STATUS_E_NOENT;
  274. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  275. return QDF_STATUS_SUCCESS;
  276. }
  277. /**
  278. * hal_rx_fst_get_fse_size_be() - Retrieve the size of each entry in Rx FST
  279. *
  280. * Return: size of each entry/flow in Rx FST
  281. */
  282. static inline uint32_t
  283. hal_rx_fst_get_fse_size_be(void)
  284. {
  285. return HAL_RX_FST_ENTRY_SIZE;
  286. }
  287. /*
  288. * TX MONITOR
  289. */
  290. #ifdef QCA_MONITOR_2_0_SUPPORT
  291. /**
  292. * hal_txmon_is_mon_buf_addr_tlv_generic_be() - api to find mon buffer tlv
  293. * @tx_tlv_hdr: pointer to TLV header
  294. *
  295. * Return: bool based on tlv tag matches monitor buffer address tlv
  296. */
  297. static inline bool
  298. hal_txmon_is_mon_buf_addr_tlv_generic_be(void *tx_tlv_hdr)
  299. {
  300. uint32_t tlv_tag;
  301. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr);
  302. if (WIFIMON_BUFFER_ADDR_E == tlv_tag)
  303. return true;
  304. return false;
  305. }
  306. /**
  307. * hal_txmon_populate_packet_info_generic_be() - api to populate packet info
  308. * @tx_tlv: pointer to TLV header
  309. * @packet_info: place holder for packet info
  310. *
  311. * Return: Address to void
  312. */
  313. static inline void
  314. hal_txmon_populate_packet_info_generic_be(void *tx_tlv, void *packet_info)
  315. {
  316. struct hal_mon_packet_info *pkt_info;
  317. struct mon_buffer_addr *addr = (struct mon_buffer_addr *)tx_tlv;
  318. pkt_info = (struct hal_mon_packet_info *)packet_info;
  319. pkt_info->sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) |
  320. (addr->buffer_virt_addr_31_0));
  321. pkt_info->dma_length = addr->dma_length + 1;
  322. pkt_info->msdu_continuation = addr->msdu_continuation;
  323. pkt_info->truncated = addr->truncated;
  324. }
  325. #if defined(TX_MONITOR_WORD_MASK)
  326. /**
  327. * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv
  328. *
  329. * @tx_tlv: pointer to tx_fes_setup tlv header
  330. *
  331. * Return: number of users
  332. */
  333. static inline uint8_t
  334. hal_txmon_get_num_users(void *tx_tlv)
  335. {
  336. hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv;
  337. return tx_fes_setup->number_of_users;
  338. }
  339. /**
  340. * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv
  341. *
  342. * @tx_tlv: pointer to tx_fes_setup tlv header
  343. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  344. *
  345. * Return: void
  346. */
  347. static inline void
  348. hal_txmon_parse_tx_fes_setup(void *tx_tlv,
  349. struct hal_tx_ppdu_info *tx_ppdu_info)
  350. {
  351. hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv;
  352. tx_ppdu_info->num_users = tx_fes_setup->number_of_users;
  353. if (tx_ppdu_info->num_users == 0)
  354. tx_ppdu_info->num_users = 1;
  355. TXMON_HAL(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id;
  356. TXMON_HAL_STATUS(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id;
  357. }
  358. /**
  359. * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv
  360. *
  361. * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header
  362. * @data_status_info: pointer to data hal_tx_status_info
  363. * @prot_status_info: pointer to protection hal_tx_status_info
  364. *
  365. * Return: void
  366. */
  367. static inline void
  368. hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv,
  369. struct hal_tx_status_info *data_status_info,
  370. struct hal_tx_status_info *prot_status_info)
  371. {
  372. }
  373. /**
  374. * hal_txmon_parse_peer_entry() - parse peer entry tlv
  375. *
  376. * @tx_tlv: pointer to peer_entry tlv header
  377. * @user_id: user_id
  378. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  379. * @tx_status_info: pointer to hal_tx_status_info
  380. *
  381. * Return: void
  382. */
  383. static inline void
  384. hal_txmon_parse_peer_entry(void *tx_tlv,
  385. uint8_t user_id,
  386. struct hal_tx_ppdu_info *tx_ppdu_info,
  387. struct hal_tx_status_info *tx_status_info)
  388. {
  389. }
  390. /**
  391. * hal_txmon_parse_queue_exten() - parse queue exten tlv
  392. *
  393. * @tx_tlv: pointer to queue exten tlv header
  394. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  395. *
  396. * Return: void
  397. */
  398. static inline void
  399. hal_txmon_parse_queue_exten(void *tx_tlv,
  400. struct hal_tx_ppdu_info *tx_ppdu_info)
  401. {
  402. }
  403. /**
  404. * hal_txmon_parse_mpdu_start() - parse mpdu start tlv
  405. *
  406. * @tx_tlv: pointer to mpdu start tlv header
  407. * @user_id: user id
  408. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  409. *
  410. * Return: void
  411. */
  412. static inline void
  413. hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id,
  414. struct hal_tx_ppdu_info *tx_ppdu_info)
  415. {
  416. }
  417. #else
  418. /**
  419. * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv
  420. *
  421. * @tx_tlv: pointer to tx_fes_setup tlv header
  422. *
  423. * Return: number of users
  424. */
  425. static inline uint8_t
  426. hal_txmon_get_num_users(void *tx_tlv)
  427. {
  428. uint8_t num_users = HAL_TX_DESC_GET_64(tx_tlv,
  429. TX_FES_SETUP, NUMBER_OF_USERS);
  430. return num_users;
  431. }
  432. /**
  433. * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv
  434. *
  435. * @tx_tlv: pointer to tx_fes_setup tlv header
  436. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  437. *
  438. * Return: void
  439. */
  440. static inline void
  441. hal_txmon_parse_tx_fes_setup(void *tx_tlv,
  442. struct hal_tx_ppdu_info *tx_ppdu_info)
  443. {
  444. uint32_t num_users = 0;
  445. uint32_t ppdu_id = 0;
  446. num_users = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_SETUP, NUMBER_OF_USERS);
  447. ppdu_id = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_SETUP, SCHEDULE_ID);
  448. if (num_users == 0)
  449. num_users = 1;
  450. tx_ppdu_info->num_users = num_users;
  451. TXMON_HAL(tx_ppdu_info, ppdu_id) = ppdu_id;
  452. TXMON_HAL_STATUS(tx_ppdu_info, ppdu_id) = ppdu_id;
  453. }
  454. /**
  455. * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv
  456. *
  457. * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header
  458. * @data_status_info: pointer to data hal_tx_status_info
  459. * @prot_status_info: pointer to protection hal_tx_status_info
  460. *
  461. * Return: void
  462. */
  463. static inline void
  464. hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv,
  465. struct hal_tx_status_info *data_status_info,
  466. struct hal_tx_status_info *prot_status_info)
  467. {
  468. prot_status_info->protection_addr =
  469. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  470. USE_ADDRESS_FIELDS_FOR_PROTECTION);
  471. /* protection frame address 1 */
  472. *(uint32_t *)&prot_status_info->addr1[0] =
  473. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  474. PROTECTION_FRAME_AD1_31_0);
  475. *(uint32_t *)&prot_status_info->addr1[4] =
  476. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  477. PROTECTION_FRAME_AD1_47_32);
  478. /* protection frame address 2 */
  479. *(uint32_t *)&prot_status_info->addr2[0] =
  480. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  481. PROTECTION_FRAME_AD2_15_0);
  482. *(uint32_t *)&prot_status_info->addr2[2] =
  483. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  484. PROTECTION_FRAME_AD2_47_16);
  485. /* protection frame address 3 */
  486. *(uint32_t *)&prot_status_info->addr3[0] =
  487. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  488. PROTECTION_FRAME_AD3_31_0);
  489. *(uint32_t *)&prot_status_info->addr3[4] =
  490. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  491. PROTECTION_FRAME_AD3_47_32);
  492. /* protection frame address 4 */
  493. *(uint32_t *)&prot_status_info->addr4[0] =
  494. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  495. PROTECTION_FRAME_AD4_15_0);
  496. *(uint32_t *)&prot_status_info->addr4[2] =
  497. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  498. PROTECTION_FRAME_AD4_47_16);
  499. }
  500. /**
  501. * hal_txmon_parse_peer_entry() - parse peer entry tlv
  502. *
  503. * @tx_tlv: pointer to peer_entry tlv header
  504. * @user_id: user_id
  505. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  506. * @tx_status_info: pointer to hal_tx_status_info
  507. *
  508. * Return: void
  509. */
  510. static inline void
  511. hal_txmon_parse_peer_entry(void *tx_tlv,
  512. uint8_t user_id,
  513. struct hal_tx_ppdu_info *tx_ppdu_info,
  514. struct hal_tx_status_info *tx_status_info)
  515. {
  516. *(uint32_t *)&tx_status_info->addr1[0] =
  517. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_A_31_0);
  518. *(uint32_t *)&tx_status_info->addr1[4] =
  519. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_A_47_32);
  520. *(uint32_t *)&tx_status_info->addr2[0] =
  521. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_B_15_0);
  522. *(uint32_t *)&tx_status_info->addr2[2] =
  523. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_B_47_16);
  524. TXMON_HAL_USER(tx_ppdu_info, user_id, sw_peer_id) =
  525. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, SW_PEER_ID);
  526. }
  527. /**
  528. * hal_txmon_parse_queue_exten() - parse queue exten tlv
  529. *
  530. * @tx_tlv: pointer to queue exten tlv header
  531. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  532. *
  533. * Return: void
  534. */
  535. static inline void
  536. hal_txmon_parse_queue_exten(void *tx_tlv,
  537. struct hal_tx_ppdu_info *tx_ppdu_info)
  538. {
  539. TXMON_HAL_STATUS(tx_ppdu_info, frame_control) =
  540. HAL_TX_DESC_GET_64(tx_tlv, TX_QUEUE_EXTENSION,
  541. FRAME_CTL);
  542. TXMON_HAL_STATUS(tx_ppdu_info, frame_control_info_valid) = true;
  543. }
  544. /**
  545. * hal_txmon_parse_mpdu_start() - parse mpdu start tlv
  546. *
  547. * @tx_tlv: pointer to mpdu start tlv header
  548. * @user_id: user id
  549. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  550. *
  551. * Return: void
  552. */
  553. static inline void
  554. hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id,
  555. struct hal_tx_ppdu_info *tx_ppdu_info)
  556. {
  557. TXMON_HAL_USER(tx_ppdu_info, user_id,
  558. start_seq) = HAL_TX_DESC_GET_64(tx_tlv, TX_MPDU_START,
  559. MPDU_SEQUENCE_NUMBER);
  560. TXMON_HAL(tx_ppdu_info, cur_usr_idx) = user_id;
  561. }
  562. #endif
  563. /**
  564. * get_ru_offset_from_start_index() - api to get ru offset from ru index
  565. *
  566. * @ru_size: RU size
  567. * @start_idx: Start index
  568. *
  569. * Return: uint8_t ru allocation offset
  570. */
  571. static inline
  572. uint8_t get_ru_offset_from_start_index(uint8_t ru_size, uint8_t start_idx)
  573. {
  574. uint8_t ru_alloc_offset[HAL_MAX_DL_MU_USERS][HAL_MAX_RU_INDEX] = {
  575. {0, 0, 0, 0, 0, 0, 0},
  576. {1, 0, 0, 0, 0, 0, 0},
  577. {2, 1, 0, 0, 0, 0, 0},
  578. {3, 1, 0, 0, 0, 0, 0},
  579. {4, 0, 0, 0, 0, 0, 0},
  580. {5, 2, 1, 0, 0, 0, 0},
  581. {6, 2, 1, 0, 0, 0, 0},
  582. {7, 3, 1, 0, 0, 0, 0},
  583. {8, 3, 1, 0, 0, 0, 0},
  584. {9, 4, 2, 1, 0, 0, 0},
  585. {10, 4, 2, 1, 0, 0, 0},
  586. {11, 5, 2, 1, 0, 0, 0},
  587. {12, 5, 2, 1, 0, 0, 0},
  588. {13, 0, 0, 1, 0, 0, 0},
  589. {14, 6, 3, 1, 0, 0, 0},
  590. {15, 6, 3, 1, 0, 0, 0},
  591. {16, 7, 3, 1, 0, 0, 0},
  592. {17, 7, 3, 1, 0, 0, 0},
  593. {18, 0, 0, 0, 0, 0, 0},
  594. {19, 8, 4, 2, 1, 0, 0},
  595. {20, 8, 4, 2, 1, 0, 0},
  596. {21, 9, 4, 2, 1, 0, 0},
  597. {22, 9, 4, 2, 1, 0, 0},
  598. {23, 0, 0, 2, 1, 0, 0},
  599. {24, 10, 5, 2, 1, 0, 0},
  600. {25, 10, 5, 2, 1, 0, 0},
  601. {26, 11, 5, 2, 1, 0, 0},
  602. {27, 11, 5, 2, 1, 0, 0},
  603. {28, 12, 6, 3, 1, 0, 0},
  604. {29, 12, 6, 3, 1, 0, 0},
  605. {30, 13, 6, 3, 1, 0, 0},
  606. {31, 13, 6, 3, 1, 0, 0},
  607. {32, 0, 0, 3, 1, 0, 0},
  608. {33, 14, 7, 3, 1, 0, 0},
  609. {34, 14, 7, 3, 1, 0, 0},
  610. {35, 15, 7, 3, 1, 0, 0},
  611. {36, 15, 7, 3, 1, 0, 0},
  612. };
  613. if (start_idx >= HAL_MAX_UL_MU_USERS || ru_size >= HAL_MAX_RU_INDEX)
  614. return 0;
  615. return ru_alloc_offset[start_idx][ru_size];
  616. }
  617. /**
  618. * hal_txmon_parse_fw2sw() - parse firmware to software tlv
  619. *
  620. * @tx_tlv: pointer to firmware to software tlvmpdu start tlv header
  621. * @type: place where this tlv is generated
  622. * @status_info: pointer to hal_tx_status_info
  623. *
  624. * Return: void
  625. */
  626. static inline void
  627. hal_txmon_parse_fw2sw(void *tx_tlv, uint8_t type,
  628. struct hal_tx_status_info *status_info)
  629. {
  630. uint32_t *msg = (uint32_t *)tx_tlv;
  631. switch (type) {
  632. case TXMON_FW2SW_TYPE_FES_SETUP:
  633. {
  634. uint32_t schedule_id;
  635. uint16_t c_freq1;
  636. uint16_t c_freq2;
  637. uint16_t freq_mhz;
  638. uint8_t phy_mode;
  639. c_freq1 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_GET(*msg);
  640. c_freq2 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_GET(*msg);
  641. msg++;
  642. phy_mode = TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_GET(*msg);
  643. freq_mhz = TXMON_FW2SW_MON_FES_SETUP_MHZ_GET(*msg);
  644. msg++;
  645. schedule_id = TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_GET(*msg);
  646. TXMON_STATUS_INFO(status_info, band_center_freq1) = c_freq1;
  647. TXMON_STATUS_INFO(status_info, band_center_freq2) = c_freq2;
  648. TXMON_STATUS_INFO(status_info, freq) = freq_mhz;
  649. TXMON_STATUS_INFO(status_info, phy_mode) = phy_mode;
  650. TXMON_STATUS_INFO(status_info, schedule_id) = schedule_id;
  651. break;
  652. }
  653. case TXMON_FW2SW_TYPE_FES_SETUP_USER:
  654. {
  655. break;
  656. }
  657. case TXMON_FW2SW_TYPE_FES_SETUP_EXT:
  658. {
  659. break;
  660. }
  661. };
  662. }
  663. /**
  664. * hal_txmon_parse_u_sig_hdr() - parse u_sig header information from tlv
  665. *
  666. * @tx_tlv: pointer to mactx_u_sig_eht_su_mu/tb tlv
  667. * @ppdu_info: pointer to hal_tx_ppdu_info
  668. *
  669. * Return: void
  670. */
  671. static inline void
  672. hal_txmon_parse_u_sig_hdr(void *tx_tlv, struct hal_tx_ppdu_info *ppdu_info)
  673. {
  674. struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)tx_tlv;
  675. struct hal_mon_usig_cmn *usig_1 = &usig->usig_1;
  676. uint8_t bad_usig_crc;
  677. bad_usig_crc = HAL_TX_DESC_GET_64(tx_tlv,
  678. MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS,
  679. CRC) ? 0 : 1;
  680. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  681. QDF_MON_STATUS_USIG_PHY_VERSION_KNOWN |
  682. QDF_MON_STATUS_USIG_BW_KNOWN |
  683. QDF_MON_STATUS_USIG_UL_DL_KNOWN |
  684. QDF_MON_STATUS_USIG_BSS_COLOR_KNOWN |
  685. QDF_MON_STATUS_USIG_TXOP_KNOWN;
  686. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  687. (usig_1->phy_version <<
  688. QDF_MON_STATUS_USIG_PHY_VERSION_SHIFT);
  689. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  690. (usig_1->bw << QDF_MON_STATUS_USIG_BW_SHIFT);
  691. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  692. (usig_1->ul_dl << QDF_MON_STATUS_USIG_UL_DL_SHIFT);
  693. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  694. (usig_1->bss_color <<
  695. QDF_MON_STATUS_USIG_BSS_COLOR_SHIFT);
  696. TXMON_HAL_STATUS(ppdu_info, usig_common) |=
  697. (usig_1->txop << QDF_MON_STATUS_USIG_TXOP_SHIFT);
  698. TXMON_HAL_STATUS(ppdu_info, usig_common) |= bad_usig_crc;
  699. TXMON_HAL_STATUS(ppdu_info, bw) = usig_1->bw;
  700. TXMON_HAL_STATUS(ppdu_info, usig_flags) = 1;
  701. }
  702. /**
  703. * hal_txmon_populate_he_data_per_user() - populate he data per user
  704. *
  705. * @usr: pointer to hal_txmon_user_desc_per_user
  706. * @user_id: user index
  707. * @ppdu_info: pointer to hal_tx_ppdu_info
  708. *
  709. * Return: void
  710. */
  711. static inline void
  712. hal_txmon_populate_he_data_per_user(struct hal_txmon_user_desc_per_user *usr,
  713. uint32_t user_id,
  714. struct hal_tx_ppdu_info *ppdu_info)
  715. {
  716. uint32_t he_data1 = TXMON_HAL_USER(ppdu_info, user_id, he_data1);
  717. uint32_t he_data2 = TXMON_HAL_USER(ppdu_info, user_id, he_data2);
  718. uint32_t he_data3 = TXMON_HAL_USER(ppdu_info, user_id, he_data3);
  719. uint32_t he_data5 = TXMON_HAL_USER(ppdu_info, user_id, he_data5);
  720. uint32_t he_data6 = TXMON_HAL_USER(ppdu_info, user_id, he_data6);
  721. /* populate */
  722. /* BEAM CHANGE */
  723. he_data1 |= QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN;
  724. he_data1 |= QDF_MON_STATUS_TXBF_KNOWN;
  725. he_data5 |= (!!usr->user_bf_type << QDF_MON_STATUS_TXBF_SHIFT);
  726. he_data3 |= (!!usr->user_bf_type << QDF_MON_STATUS_BEAM_CHANGE_SHIFT);
  727. /* UL/DL known */
  728. he_data1 |= QDF_MON_STATUS_HE_DL_UL_KNOWN;
  729. he_data3 |= (1 << QDF_MON_STATUS_DL_UL_SHIFT);
  730. /* MCS */
  731. he_data1 |= QDF_MON_STATUS_HE_MCS_KNOWN;
  732. he_data3 |= (usr->mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT);
  733. /* DCM */
  734. he_data1 |= QDF_MON_STATUS_HE_DCM_KNOWN;
  735. he_data3 |= (usr->dcm << QDF_MON_STATUS_DCM_SHIFT);
  736. /* LDPC EXTRA SYMB */
  737. he_data1 |= QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN;
  738. he_data3 |= (usr->ldpc_extra_symbol <<
  739. QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT);
  740. /* RU offset and RU */
  741. he_data2 |= QDF_MON_STATUS_RU_ALLOCATION_OFFSET_KNOWN;
  742. he_data2 |= (get_ru_offset_from_start_index(usr->ru_size,
  743. usr->ru_start_index) <<
  744. QDF_MON_STATUS_RU_ALLOCATION_SHIFT);
  745. /* Data BW and RU allocation */
  746. if (usr->ru_size < HAL_MAX_RU_INDEX) {
  747. /* update bandwidth if it is full bandwidth */
  748. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  749. he_data5 = (he_data5 & 0xFFF0) | (4 + usr->ru_size);
  750. }
  751. he_data6 |= (usr->nss & 0xF);
  752. TXMON_HAL_USER(ppdu_info, user_id, mcs) = usr->mcs;
  753. /* update stack variable to ppdu_info */
  754. TXMON_HAL_USER(ppdu_info, user_id, he_data1) = he_data1;
  755. TXMON_HAL_USER(ppdu_info, user_id, he_data2) = he_data2;
  756. TXMON_HAL_USER(ppdu_info, user_id, he_data3) = he_data3;
  757. TXMON_HAL_USER(ppdu_info, user_id, he_data5) = he_data5;
  758. TXMON_HAL_USER(ppdu_info, user_id, he_data6) = he_data6;
  759. }
  760. /**
  761. * hal_txmon_get_user_desc_per_user() - get mactx user desc per user from tlv
  762. *
  763. * @tx_tlv: pointer to mactx_user_desc_per_user tlv
  764. * @usr: pointer to hal_txmon_user_desc_per_user
  765. *
  766. * Return: void
  767. */
  768. static inline void
  769. hal_txmon_get_user_desc_per_user(void *tx_tlv,
  770. struct hal_txmon_user_desc_per_user *usr)
  771. {
  772. usr->psdu_length = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  773. PSDU_LENGTH);
  774. usr->ru_start_index = HAL_TX_DESC_GET_64(tx_tlv,
  775. MACTX_USER_DESC_PER_USER,
  776. RU_START_INDEX);
  777. usr->ru_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  778. RU_SIZE);
  779. usr->ofdma_mu_mimo_enabled =
  780. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  781. OFDMA_MU_MIMO_ENABLED);
  782. usr->nss = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, NSS);
  783. usr->stream_offset = HAL_TX_DESC_GET_64(tx_tlv,
  784. MACTX_USER_DESC_PER_USER,
  785. STREAM_OFFSET);
  786. usr->mcs = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, MCS);
  787. usr->dcm = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, DCM);
  788. usr->fec_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  789. FEC_TYPE);
  790. usr->user_bf_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  791. USER_BF_TYPE);
  792. usr->drop_user_cbf = HAL_TX_DESC_GET_64(tx_tlv,
  793. MACTX_USER_DESC_PER_USER,
  794. DROP_USER_CBF);
  795. usr->ldpc_extra_symbol = HAL_TX_DESC_GET_64(tx_tlv,
  796. MACTX_USER_DESC_PER_USER,
  797. LDPC_EXTRA_SYMBOL);
  798. usr->force_extra_symbol = HAL_TX_DESC_GET_64(tx_tlv,
  799. MACTX_USER_DESC_PER_USER,
  800. FORCE_EXTRA_SYMBOL);
  801. usr->sw_peer_id = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  802. SW_PEER_ID);
  803. }
  804. /**
  805. * hal_txmon_populate_eht_sig_per_user() - populate eht sig user information
  806. *
  807. * @usr: pointer to hal_txmon_user_desc_per_user
  808. * @user_id: user index
  809. * @ppdu_info: pointer to hal_tx_ppdu_info
  810. *
  811. * Return: void
  812. */
  813. static inline void
  814. hal_txmon_populate_eht_sig_per_user(struct hal_txmon_user_desc_per_user *usr,
  815. uint32_t user_id,
  816. struct hal_tx_ppdu_info *ppdu_info)
  817. {
  818. uint32_t eht_known = 0;
  819. uint32_t eht_data[6] = {0};
  820. uint8_t i = 0;
  821. eht_known = QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_KNOWN;
  822. eht_data[0] |= (usr->ldpc_extra_symbol <<
  823. QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_SHIFT);
  824. TXMON_HAL_STATUS(ppdu_info, eht_known) |= eht_known;
  825. for (i = 0; i < 6; i++)
  826. TXMON_HAL_STATUS(ppdu_info, eht_data[i]) |= eht_data[i];
  827. }
  828. /**
  829. * hal_txmon_parse_user_desc_per_user() - parse mactx user desc per user
  830. *
  831. * @tx_tlv: pointer to mactx_user_desc_per_user tlv
  832. * @user_id: user index
  833. * @ppdu_info: pointer to hal_tx_ppdu_info
  834. *
  835. * Return: void
  836. */
  837. static inline void
  838. hal_txmon_parse_user_desc_per_user(void *tx_tlv, uint32_t user_id,
  839. struct hal_tx_ppdu_info *ppdu_info)
  840. {
  841. struct hal_txmon_user_desc_per_user usr_info = {0};
  842. hal_txmon_get_user_desc_per_user(tx_tlv, &usr_info);
  843. /* based on preamble type populate user desc user info */
  844. if (TXMON_HAL_STATUS(ppdu_info, he_flags))
  845. hal_txmon_populate_he_data_per_user(&usr_info,
  846. user_id, ppdu_info);
  847. hal_txmon_populate_eht_sig_per_user(&usr_info, user_id, ppdu_info);
  848. }
  849. /**
  850. * hal_txmon_get_user_desc_common() - update hal_txmon_usr_desc_common from tlv
  851. *
  852. * @tx_tlv: pointer to mactx_user_desc_common tlv
  853. * @usr_common: pointer to hal_txmon_usr_desc_common
  854. *
  855. * Return: void
  856. */
  857. static inline void
  858. hal_txmon_get_user_desc_common(void *tx_tlv,
  859. struct hal_txmon_usr_desc_common *usr_common)
  860. {
  861. usr_common->ltf_size =
  862. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, LTF_SIZE);
  863. usr_common->pkt_extn_pe =
  864. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  865. PACKET_EXTENSION_PE_DISAMBIGUITY);
  866. usr_common->a_factor =
  867. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  868. PACKET_EXTENSION_A_FACTOR);
  869. usr_common->center_ru_0 =
  870. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, CENTER_RU_0);
  871. usr_common->center_ru_1 =
  872. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, CENTER_RU_1);
  873. usr_common->num_ltf_symbols =
  874. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  875. NUM_LTF_SYMBOLS);
  876. usr_common->doppler_indication =
  877. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  878. DOPPLER_INDICATION);
  879. usr_common->spatial_reuse =
  880. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  881. SPATIAL_REUSE);
  882. usr_common->ru_channel_0[0] =
  883. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  884. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0);
  885. usr_common->ru_channel_0[1] =
  886. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  887. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1);
  888. usr_common->ru_channel_0[2] =
  889. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  890. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2);
  891. usr_common->ru_channel_0[3] =
  892. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  893. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3);
  894. usr_common->ru_channel_0[4] =
  895. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  896. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0);
  897. usr_common->ru_channel_0[5] =
  898. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  899. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1);
  900. usr_common->ru_channel_0[6] =
  901. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  902. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2);
  903. usr_common->ru_channel_0[7] =
  904. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  905. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3);
  906. usr_common->ru_channel_1[0] =
  907. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  908. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0);
  909. usr_common->ru_channel_1[1] =
  910. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  911. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1);
  912. usr_common->ru_channel_1[2] =
  913. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  914. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2);
  915. usr_common->ru_channel_1[3] =
  916. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  917. RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3);
  918. usr_common->ru_channel_1[4] =
  919. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  920. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0);
  921. usr_common->ru_channel_1[5] =
  922. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  923. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1);
  924. usr_common->ru_channel_1[6] =
  925. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  926. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2);
  927. usr_common->ru_channel_1[7] =
  928. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON,
  929. RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3);
  930. }
  931. /**
  932. * hal_txmon_populate_he_data_common() - populate he data common information
  933. *
  934. * @usr_common: pointer to hal_txmon_usr_desc_common
  935. * @user_id: user index
  936. * @ppdu_info: pointer to hal_tx_ppdu_info
  937. *
  938. * Return: void
  939. */
  940. static inline void
  941. hal_txmon_populate_he_data_common(struct hal_txmon_usr_desc_common *usr_common,
  942. uint32_t user_id,
  943. struct hal_tx_ppdu_info *ppdu_info)
  944. {
  945. /* HE data 1 */
  946. TXMON_HAL_USER(ppdu_info,
  947. user_id, he_data1) |= QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  948. /* HE data 2 */
  949. TXMON_HAL_USER(ppdu_info, user_id,
  950. he_data2) |= (QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  951. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN);
  952. /* HE data 5 */
  953. TXMON_HAL_USER(ppdu_info, user_id, he_data5) |=
  954. (usr_common->pkt_extn_pe <<
  955. QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT) |
  956. (usr_common->a_factor << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT) |
  957. ((1 + usr_common->ltf_size) <<
  958. QDF_MON_STATUS_HE_LTF_SIZE_SHIFT) |
  959. (usr_common->num_ltf_symbols <<
  960. QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  961. /* HE data 6 */
  962. TXMON_HAL_USER(ppdu_info, user_id,
  963. he_data6) |= (usr_common->doppler_indication <<
  964. QDF_MON_STATUS_DOPPLER_SHIFT);
  965. }
  966. /**
  967. * hal_txmon_populate_he_mu_common() - populate he mu common information
  968. *
  969. * @usr_common: pointer to hal_txmon_usr_desc_common
  970. * @user_id: user index
  971. * @ppdu_info: pointer to hal_tx_ppdu_info
  972. *
  973. * Return: void
  974. */
  975. static inline void
  976. hal_txmon_populate_he_mu_common(struct hal_txmon_usr_desc_common *usr_common,
  977. uint32_t user_id,
  978. struct hal_tx_ppdu_info *ppdu_info)
  979. {
  980. uint16_t he_mu_flag_1 = 0;
  981. uint16_t he_mu_flag_2 = 0;
  982. uint16_t i = 0;
  983. he_mu_flag_1 |= (QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  984. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN |
  985. ((usr_common->center_ru_0 <<
  986. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_SHIFT) &
  987. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_VALUE));
  988. he_mu_flag_2 |= ((usr_common->center_ru_1 <<
  989. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_SHIFT) &
  990. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_VALUE);
  991. for (i = 0; i < usr_common->num_users; i++) {
  992. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  993. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  994. /* channel 1 */
  995. TXMON_HAL_USER(ppdu_info, i, he_RU[0]) =
  996. usr_common->ru_channel_0[0];
  997. TXMON_HAL_USER(ppdu_info, i, he_RU[1]) =
  998. usr_common->ru_channel_0[1];
  999. TXMON_HAL_USER(ppdu_info, i, he_RU[2]) =
  1000. usr_common->ru_channel_0[2];
  1001. TXMON_HAL_USER(ppdu_info, i, he_RU[3]) =
  1002. usr_common->ru_channel_0[3];
  1003. /* channel 2 */
  1004. TXMON_HAL_USER(ppdu_info, i, he_RU[4]) =
  1005. usr_common->ru_channel_1[0];
  1006. TXMON_HAL_USER(ppdu_info, i, he_RU[5]) =
  1007. usr_common->ru_channel_1[1];
  1008. TXMON_HAL_USER(ppdu_info, i, he_RU[6]) =
  1009. usr_common->ru_channel_1[2];
  1010. TXMON_HAL_USER(ppdu_info, i, he_RU[7]) =
  1011. usr_common->ru_channel_1[3];
  1012. }
  1013. }
  1014. /**
  1015. * hal_txmon_populate_eht_sig_common() - populate eht sig common information
  1016. *
  1017. * @usr_common: pointer to hal_txmon_usr_desc_common
  1018. * @user_id: user index
  1019. * @ppdu_info: pointer to hal_tx_ppdu_info
  1020. *
  1021. * Return: void
  1022. */
  1023. static inline void
  1024. hal_txmon_populate_eht_sig_common(struct hal_txmon_usr_desc_common *usr_common,
  1025. uint32_t user_id,
  1026. struct hal_tx_ppdu_info *ppdu_info)
  1027. {
  1028. uint32_t eht_known = 0;
  1029. uint32_t eht_data[9] = {0};
  1030. uint8_t num_ru_allocation_known = 0;
  1031. uint8_t i = 0;
  1032. eht_known = (QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN |
  1033. QDF_MON_STATUS_EHT_EHT_LTF_KNOWN |
  1034. QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_KNOWN |
  1035. QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_KNOWN |
  1036. QDF_MON_STATUS_EHT_DISREARD_KNOWN);
  1037. eht_data[0] |= (usr_common->spatial_reuse <<
  1038. QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT);
  1039. eht_data[0] |= (usr_common->num_ltf_symbols <<
  1040. QDF_MON_STATUS_EHT_EHT_LTF_SHIFT);
  1041. eht_data[0] |= (usr_common->a_factor <<
  1042. QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_SHIFT);
  1043. eht_data[0] |= (usr_common->pkt_extn_pe <<
  1044. QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_SHIFT);
  1045. eht_data[0] |= (0xF << QDF_MON_STATUS_EHT_DISREGARD_SHIFT);
  1046. switch (TXMON_HAL_STATUS(ppdu_info, bw)) {
  1047. case HAL_EHT_BW_320_2:
  1048. case HAL_EHT_BW_320_1:
  1049. num_ru_allocation_known += 4;
  1050. eht_data[3] |= (usr_common->ru_channel_0[7] <<
  1051. QDF_MON_STATUS_EHT_RU_ALLOCATION2_6_SHIFT);
  1052. eht_data[3] |= (usr_common->ru_channel_0[6] <<
  1053. QDF_MON_STATUS_EHT_RU_ALLOCATION2_5_SHIFT);
  1054. eht_data[3] |= (usr_common->ru_channel_0[5] <<
  1055. QDF_MON_STATUS_EHT_RU_ALLOCATION2_4_SHIFT);
  1056. eht_data[2] |= (usr_common->ru_channel_0[4] <<
  1057. QDF_MON_STATUS_EHT_RU_ALLOCATION2_3_SHIFT);
  1058. fallthrough;
  1059. case HAL_EHT_BW_160:
  1060. num_ru_allocation_known += 2;
  1061. eht_data[2] |= (usr_common->ru_channel_0[3] <<
  1062. QDF_MON_STATUS_EHT_RU_ALLOCATION2_2_SHIFT);
  1063. eht_data[2] |= (usr_common->ru_channel_0[2] <<
  1064. QDF_MON_STATUS_EHT_RU_ALLOCATION2_1_SHIFT);
  1065. fallthrough;
  1066. case HAL_EHT_BW_80:
  1067. num_ru_allocation_known += 1;
  1068. eht_data[1] |= (usr_common->ru_channel_0[1] <<
  1069. QDF_MON_STATUS_EHT_RU_ALLOCATION1_2_SHIFT);
  1070. fallthrough;
  1071. case HAL_EHT_BW_40:
  1072. case HAL_EHT_BW_20:
  1073. num_ru_allocation_known += 1;
  1074. eht_data[1] |= (usr_common->ru_channel_0[0] <<
  1075. QDF_MON_STATUS_EHT_RU_ALLOCATION1_1_SHIFT);
  1076. break;
  1077. default:
  1078. break;
  1079. }
  1080. eht_known |= (num_ru_allocation_known <<
  1081. QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT);
  1082. TXMON_HAL_STATUS(ppdu_info, eht_known) |= eht_known;
  1083. for (i = 0; i < 4; i++)
  1084. TXMON_HAL_STATUS(ppdu_info, eht_data[i]) |= eht_data[i];
  1085. }
  1086. /**
  1087. * hal_txmon_parse_user_desc_common() - parse mactx user desc common tlv
  1088. *
  1089. * @tx_tlv: pointer to mactx_user_desc_common tlv
  1090. * @user_id: user index
  1091. * @ppdu_info: pointer to hal_tx_ppdu_info
  1092. *
  1093. * Return: void
  1094. */
  1095. static inline void
  1096. hal_txmon_parse_user_desc_common(void *tx_tlv, uint32_t user_id,
  1097. struct hal_tx_ppdu_info *ppdu_info)
  1098. {
  1099. struct hal_txmon_usr_desc_common usr_common = {0};
  1100. usr_common.num_users = TXMON_HAL(ppdu_info, num_users);
  1101. hal_txmon_get_user_desc_common(tx_tlv, &usr_common);
  1102. TXMON_HAL_STATUS(ppdu_info,
  1103. he_mu_flags) = IS_MULTI_USERS(usr_common.num_users);
  1104. switch (TXMON_HAL_STATUS(ppdu_info, preamble_type)) {
  1105. case TXMON_PKT_TYPE_11AX:
  1106. if (TXMON_HAL_STATUS(ppdu_info, he_flags))
  1107. hal_txmon_populate_he_data_common(&usr_common,
  1108. user_id, ppdu_info);
  1109. if (TXMON_HAL_STATUS(ppdu_info, he_mu_flags))
  1110. hal_txmon_populate_he_mu_common(&usr_common,
  1111. user_id, ppdu_info);
  1112. break;
  1113. case TXMON_PKT_TYPE_11BE:
  1114. hal_txmon_populate_eht_sig_common(&usr_common,
  1115. user_id, ppdu_info);
  1116. break;
  1117. }
  1118. }
  1119. /**
  1120. * hal_txmon_parse_eht_sig_non_mumimo_user_info() - parse eht sig non mumimo tlv
  1121. *
  1122. * @tx_tlv: pointer to hal_eht_sig_non_mu_mimo_user_info
  1123. * @user_id: user index
  1124. * @ppdu_info: pointer to hal_tx_ppdu_info
  1125. *
  1126. * Return: void
  1127. */
  1128. static inline void
  1129. hal_txmon_parse_eht_sig_non_mumimo_user_info(void *tx_tlv, uint32_t user_id,
  1130. struct hal_tx_ppdu_info *ppdu_info)
  1131. {
  1132. struct hal_eht_sig_non_mu_mimo_user_info *user_info;
  1133. uint32_t idx = TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid);
  1134. user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tx_tlv;
  1135. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1136. QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN |
  1137. QDF_MON_STATUS_EHT_USER_MCS_KNOWN |
  1138. QDF_MON_STATUS_EHT_USER_CODING_KNOWN |
  1139. QDF_MON_STATUS_EHT_USER_NSS_KNOWN |
  1140. QDF_MON_STATUS_EHT_USER_BEAMFORMING_KNOWN;
  1141. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1142. (user_info->sta_id <<
  1143. QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT);
  1144. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1145. (user_info->mcs <<
  1146. QDF_MON_STATUS_EHT_USER_MCS_SHIFT);
  1147. TXMON_HAL_STATUS(ppdu_info, mcs) = user_info->mcs;
  1148. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1149. (user_info->nss <<
  1150. QDF_MON_STATUS_EHT_USER_NSS_SHIFT);
  1151. TXMON_HAL_STATUS(ppdu_info, nss) = user_info->nss + 1;
  1152. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1153. (user_info->beamformed <<
  1154. QDF_MON_STATUS_EHT_USER_BEAMFORMING_SHIFT);
  1155. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1156. (user_info->coding <<
  1157. QDF_MON_STATUS_EHT_USER_CODING_SHIFT);
  1158. /* TODO: CRC */
  1159. TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid) += 1;
  1160. }
  1161. /**
  1162. * hal_txmon_parse_eht_sig_mumimo_user_info() - parse eht sig mumimo tlv
  1163. *
  1164. * @tx_tlv: pointer to hal_eht_sig_mu_mimo_user_info
  1165. * @user_id: user index
  1166. * @ppdu_info: pointer to hal_tx_ppdu_info
  1167. *
  1168. * Return: void
  1169. */
  1170. static inline void
  1171. hal_txmon_parse_eht_sig_mumimo_user_info(void *tx_tlv, uint32_t user_id,
  1172. struct hal_tx_ppdu_info *ppdu_info)
  1173. {
  1174. struct hal_eht_sig_mu_mimo_user_info *user_info;
  1175. uint32_t idx = TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid);
  1176. user_info = (struct hal_eht_sig_mu_mimo_user_info *)tx_tlv;
  1177. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1178. QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN |
  1179. QDF_MON_STATUS_EHT_USER_MCS_KNOWN |
  1180. QDF_MON_STATUS_EHT_USER_CODING_KNOWN |
  1181. QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_KNOWN;
  1182. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1183. (user_info->sta_id <<
  1184. QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT);
  1185. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1186. (user_info->mcs <<
  1187. QDF_MON_STATUS_EHT_USER_MCS_SHIFT);
  1188. TXMON_HAL_STATUS(ppdu_info, mcs) = user_info->mcs;
  1189. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1190. (user_info->coding <<
  1191. QDF_MON_STATUS_EHT_USER_CODING_SHIFT);
  1192. TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |=
  1193. (user_info->spatial_coding <<
  1194. QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_SHIFT);
  1195. /* TODO: CRC */
  1196. TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid) += 1;
  1197. }
  1198. /**
  1199. * hal_txmon_status_get_num_users_generic_be() - api to get num users
  1200. * from start of fes window
  1201. *
  1202. * @tx_tlv_hdr: pointer to TLV header
  1203. * @num_users: reference to number of user
  1204. *
  1205. * Return: status
  1206. */
  1207. static inline uint32_t
  1208. hal_txmon_status_get_num_users_generic_be(void *tx_tlv_hdr, uint8_t *num_users)
  1209. {
  1210. uint32_t tlv_tag, user_id, tlv_len;
  1211. uint32_t tlv_status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  1212. void *tx_tlv;
  1213. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr);
  1214. user_id = HAL_RX_GET_USER_TLV32_USERID(tx_tlv_hdr);
  1215. tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv_hdr);
  1216. tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  1217. /* window starts with either initiator or response */
  1218. switch (tlv_tag) {
  1219. case WIFITX_FES_SETUP_E:
  1220. {
  1221. *num_users = hal_txmon_get_num_users(tx_tlv);
  1222. if (*num_users == 0)
  1223. *num_users = 1;
  1224. tlv_status = HAL_MON_TX_FES_SETUP;
  1225. break;
  1226. }
  1227. case WIFIRX_RESPONSE_REQUIRED_INFO_E:
  1228. {
  1229. *num_users = HAL_TX_DESC_GET_64(tx_tlv,
  1230. RX_RESPONSE_REQUIRED_INFO,
  1231. RESPONSE_STA_COUNT);
  1232. if (*num_users == 0)
  1233. *num_users = 1;
  1234. tlv_status = HAL_MON_RX_RESPONSE_REQUIRED_INFO;
  1235. break;
  1236. }
  1237. };
  1238. return tlv_status;
  1239. }
  1240. /**
  1241. * hal_tx_get_ppdu_info() - api to get tx ppdu info
  1242. * @data_info: populate dp_ppdu_info data
  1243. * @prot_info: populate dp_ppdu_info protection
  1244. * @tlv_tag: Tag
  1245. *
  1246. * Return: dp_tx_ppdu_info pointer
  1247. */
  1248. static inline void *
  1249. hal_tx_get_ppdu_info(void *data_info, void *prot_info, uint32_t tlv_tag)
  1250. {
  1251. struct hal_tx_ppdu_info *prot_ppdu_info = prot_info;
  1252. switch (tlv_tag) {
  1253. case WIFITX_FES_SETUP_E:/* DOWNSTREAM */
  1254. case WIFITX_FLUSH_E:/* DOWNSTREAM */
  1255. case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */
  1256. case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */
  1257. case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */
  1258. case WIFITX_MPDU_START_E:/* DOWNSTREAM */
  1259. case WIFITX_MSDU_START_E:/* DOWNSTREAM */
  1260. case WIFITX_DATA_E:/* DOWNSTREAM */
  1261. case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */
  1262. case WIFITX_MPDU_END_E:/* DOWNSTREAM */
  1263. case WIFITX_MSDU_END_E:/* DOWNSTREAM */
  1264. case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */
  1265. case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */
  1266. case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */
  1267. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */
  1268. case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */
  1269. case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */
  1270. case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */
  1271. case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */
  1272. case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */
  1273. case WIFITX_WUR_DATA_E:/* DOWNSTREAM */
  1274. case WIFISCHEDULER_END_E:/* DOWNSTREAM */
  1275. case WIFITX_FES_STATUS_START_PPDU_E:/* UPSTREAM */
  1276. {
  1277. return data_info;
  1278. }
  1279. }
  1280. /*
  1281. * check current prot_tlv_status is start protection
  1282. * check current tlv_tag is either start protection or end protection
  1283. */
  1284. if (TXMON_HAL(prot_ppdu_info,
  1285. prot_tlv_status) == WIFITX_FES_STATUS_START_PROT_E) {
  1286. return prot_info;
  1287. } else if (tlv_tag == WIFITX_FES_STATUS_PROT_E ||
  1288. tlv_tag == WIFITX_FES_STATUS_START_PROT_E) {
  1289. TXMON_HAL(prot_ppdu_info, prot_tlv_status) = tlv_tag;
  1290. return prot_info;
  1291. }
  1292. return data_info;
  1293. }
  1294. /**
  1295. * hal_txmon_status_parse_tlv_generic_be() - api to parse status tlv.
  1296. * @data_ppdu_info: hal_txmon data ppdu info
  1297. * @prot_ppdu_info: hal_txmon prot ppdu info
  1298. * @data_status_info: pointer to data status info
  1299. * @prot_status_info: pointer to prot status info
  1300. * @tx_tlv_hdr: fragment of tx_tlv_hdr
  1301. * @status_frag: qdf_frag_t buffer
  1302. *
  1303. * Return: status
  1304. */
  1305. static inline uint32_t
  1306. hal_txmon_status_parse_tlv_generic_be(void *data_ppdu_info,
  1307. void *prot_ppdu_info,
  1308. void *data_status_info,
  1309. void *prot_status_info,
  1310. void *tx_tlv_hdr,
  1311. qdf_frag_t status_frag)
  1312. {
  1313. struct hal_tx_ppdu_info *ppdu_info;
  1314. struct hal_tx_status_info *tx_status_info;
  1315. struct hal_mon_packet_info *packet_info = NULL;
  1316. uint32_t tlv_tag, user_id, tlv_len, tlv_user_id;
  1317. uint32_t status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  1318. void *tx_tlv;
  1319. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr);
  1320. tlv_user_id = HAL_RX_GET_USER_TLV64_USERID(tx_tlv_hdr);
  1321. tlv_len = HAL_RX_GET_USER_TLV64_LEN(tx_tlv_hdr);
  1322. tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  1323. /* parse tlv and populate tx_ppdu_info */
  1324. ppdu_info = hal_tx_get_ppdu_info(data_ppdu_info,
  1325. prot_ppdu_info, tlv_tag);
  1326. tx_status_info = (ppdu_info->is_data ? data_status_info :
  1327. prot_status_info);
  1328. user_id = (tlv_user_id > ppdu_info->num_users ? 0 : tlv_user_id);
  1329. switch (tlv_tag) {
  1330. /* start of initiator FES window */
  1331. case WIFITX_FES_SETUP_E:/* DOWNSTREAM */
  1332. {
  1333. /* initiator PPDU window start */
  1334. hal_txmon_parse_tx_fes_setup(tx_tlv, ppdu_info);
  1335. status = HAL_MON_TX_FES_SETUP;
  1336. SHOW_DEFINED(WIFITX_FES_SETUP_E);
  1337. break;
  1338. }
  1339. /* end of initiator FES window */
  1340. case WIFITX_FES_STATUS_END_E:/* UPSTREAM */
  1341. {
  1342. /* initiator PPDU window end */
  1343. uint32_t ppdu_timestamp_start = 0;
  1344. uint32_t ppdu_timestamp_end = 0;
  1345. uint16_t phy_abort_reason = 0;
  1346. uint8_t phy_abort_is_valid = 0;
  1347. uint8_t abort_usr_id = 0;
  1348. uint8_t response_type = 0;
  1349. uint8_t r2r_end_status_follow = 0;
  1350. status = HAL_MON_TX_FES_STATUS_END;
  1351. ppdu_timestamp_start =
  1352. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  1353. START_OF_FRAME_TIMESTAMP_15_0) |
  1354. (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  1355. START_OF_FRAME_TIMESTAMP_31_16) <<
  1356. HAL_TX_LSB(TX_FES_STATUS_END,
  1357. START_OF_FRAME_TIMESTAMP_31_16));
  1358. ppdu_timestamp_end =
  1359. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  1360. END_OF_FRAME_TIMESTAMP_15_0) |
  1361. (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  1362. END_OF_FRAME_TIMESTAMP_31_16) <<
  1363. HAL_TX_LSB(TX_FES_STATUS_END,
  1364. END_OF_FRAME_TIMESTAMP_31_16));
  1365. response_type = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  1366. RESPONSE_TYPE);
  1367. /*
  1368. * r2r end status follow to inform whether to look for
  1369. * rx_response_required_info
  1370. */
  1371. r2r_end_status_follow =
  1372. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  1373. R2R_END_STATUS_TO_FOLLOW);
  1374. phy_abort_is_valid =
  1375. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  1376. PHYTX_ABORT_REQUEST_INFO_VALID);
  1377. if (phy_abort_is_valid) {
  1378. phy_abort_reason =
  1379. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  1380. PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON);
  1381. abort_usr_id =
  1382. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  1383. PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER);
  1384. TXMON_STATUS_INFO(tx_status_info,
  1385. phy_abort_reason) = phy_abort_reason;
  1386. TXMON_STATUS_INFO(tx_status_info,
  1387. phy_abort_user_number) = abort_usr_id;
  1388. }
  1389. TXMON_STATUS_INFO(tx_status_info,
  1390. response_type) = response_type;
  1391. TXMON_STATUS_INFO(tx_status_info,
  1392. r2r_to_follow) = r2r_end_status_follow;
  1393. /* update phy timestamp to ppdu timestamp */
  1394. TXMON_HAL_STATUS(ppdu_info,
  1395. ppdu_timestamp) = ppdu_timestamp_start;
  1396. SHOW_DEFINED(WIFITX_FES_STATUS_END_E);
  1397. break;
  1398. }
  1399. /* response window open */
  1400. case WIFIRX_RESPONSE_REQUIRED_INFO_E:/* UPSTREAM */
  1401. {
  1402. /* response PPDU window start */
  1403. uint32_t ppdu_id = 0;
  1404. uint8_t reception_type = 0;
  1405. uint8_t response_sta_count = 0;
  1406. status = HAL_MON_RX_RESPONSE_REQUIRED_INFO;
  1407. ppdu_id = HAL_TX_DESC_GET_64(tx_tlv,
  1408. RX_RESPONSE_REQUIRED_INFO,
  1409. PHY_PPDU_ID);
  1410. reception_type =
  1411. HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO,
  1412. SU_OR_UPLINK_MU_RECEPTION);
  1413. response_sta_count =
  1414. HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO,
  1415. RESPONSE_STA_COUNT);
  1416. /* get mac address */
  1417. *(uint32_t *)&tx_status_info->addr1[0] =
  1418. HAL_TX_DESC_GET_64(tx_tlv,
  1419. RX_RESPONSE_REQUIRED_INFO,
  1420. ADDR1_31_0);
  1421. *(uint32_t *)&tx_status_info->addr1[4] =
  1422. HAL_TX_DESC_GET_64(tx_tlv,
  1423. RX_RESPONSE_REQUIRED_INFO,
  1424. ADDR1_47_32);
  1425. *(uint32_t *)&tx_status_info->addr2[0] =
  1426. HAL_TX_DESC_GET_64(tx_tlv,
  1427. RX_RESPONSE_REQUIRED_INFO,
  1428. ADDR2_15_0);
  1429. *(uint32_t *)&tx_status_info->addr2[2] =
  1430. HAL_TX_DESC_GET_64(tx_tlv,
  1431. RX_RESPONSE_REQUIRED_INFO,
  1432. ADDR2_47_16);
  1433. TXMON_HAL(ppdu_info, ppdu_id) = ppdu_id;
  1434. TXMON_HAL_STATUS(ppdu_info, ppdu_id) = ppdu_id;
  1435. if (response_sta_count == 0)
  1436. response_sta_count = 1;
  1437. TXMON_HAL(ppdu_info, num_users) = response_sta_count;
  1438. if (reception_type)
  1439. TXMON_STATUS_INFO(tx_status_info,
  1440. transmission_type) =
  1441. TXMON_SU_TRANSMISSION;
  1442. else
  1443. TXMON_STATUS_INFO(tx_status_info,
  1444. transmission_type) =
  1445. TXMON_MU_TRANSMISSION;
  1446. SHOW_DEFINED(WIFIRX_RESPONSE_REQUIRED_INFO_E);
  1447. break;
  1448. }
  1449. /* Response window close */
  1450. case WIFIRESPONSE_END_STATUS_E:/* UPSTREAM */
  1451. {
  1452. /* response PPDU window end */
  1453. uint8_t generated_response = 0;
  1454. uint32_t bandwidth = 0;
  1455. uint32_t ppdu_timestamp_start = 0;
  1456. uint32_t ppdu_timestamp_end = 0;
  1457. uint32_t mba_usr_cnt = 0;
  1458. uint32_t mba_fake_bitmap_cnt = 0;
  1459. status = HAL_MON_RESPONSE_END_STATUS_INFO;
  1460. generated_response = HAL_TX_DESC_GET_64(tx_tlv,
  1461. RESPONSE_END_STATUS,
  1462. GENERATED_RESPONSE);
  1463. mba_usr_cnt = HAL_TX_DESC_GET_64(tx_tlv,
  1464. RESPONSE_END_STATUS,
  1465. MBA_USER_COUNT);
  1466. mba_fake_bitmap_cnt = HAL_TX_DESC_GET_64(tx_tlv,
  1467. RESPONSE_END_STATUS,
  1468. MBA_FAKE_BITMAP_COUNT);
  1469. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  1470. COEX_BASED_TX_BW);
  1471. /* 32 bits TSF */
  1472. ppdu_timestamp_start =
  1473. (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  1474. START_OF_FRAME_TIMESTAMP_15_0) |
  1475. (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  1476. START_OF_FRAME_TIMESTAMP_31_16) <<
  1477. 16));
  1478. ppdu_timestamp_end =
  1479. (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  1480. END_OF_FRAME_TIMESTAMP_15_0) |
  1481. (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  1482. END_OF_FRAME_TIMESTAMP_31_16) <<
  1483. 16));
  1484. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  1485. /* update phy timestamp to ppdu timestamp */
  1486. TXMON_HAL_STATUS(ppdu_info,
  1487. ppdu_timestamp) = ppdu_timestamp_start;
  1488. TXMON_STATUS_INFO(tx_status_info,
  1489. generated_response) = generated_response;
  1490. TXMON_STATUS_INFO(tx_status_info, mba_count) = mba_usr_cnt;
  1491. TXMON_STATUS_INFO(tx_status_info,
  1492. mba_fake_bitmap_count) = mba_fake_bitmap_cnt;
  1493. SHOW_DEFINED(WIFIRESPONSE_END_STATUS_E);
  1494. break;
  1495. }
  1496. case WIFITX_FLUSH_E:/* DOWNSTREAM */
  1497. {
  1498. SHOW_DEFINED(WIFITX_FLUSH_E);
  1499. break;
  1500. }
  1501. /* Downstream tlv */
  1502. case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */
  1503. {
  1504. hal_txmon_parse_pcu_ppdu_setup_init(tx_tlv, data_status_info,
  1505. prot_status_info);
  1506. status = HAL_MON_TX_PCU_PPDU_SETUP_INIT;
  1507. SHOW_DEFINED(WIFIPCU_PPDU_SETUP_INIT_E);
  1508. break;
  1509. }
  1510. case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */
  1511. {
  1512. hal_txmon_parse_peer_entry(tx_tlv, user_id,
  1513. ppdu_info, tx_status_info);
  1514. SHOW_DEFINED(WIFITX_PEER_ENTRY_E);
  1515. break;
  1516. }
  1517. case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */
  1518. {
  1519. status = HAL_MON_TX_QUEUE_EXTENSION;
  1520. hal_txmon_parse_queue_exten(tx_tlv, ppdu_info);
  1521. SHOW_DEFINED(WIFITX_QUEUE_EXTENSION_E);
  1522. break;
  1523. }
  1524. /* payload and data frame handling */
  1525. case WIFITX_MPDU_START_E:/* DOWNSTREAM */
  1526. {
  1527. hal_txmon_parse_mpdu_start(tx_tlv, user_id, ppdu_info);
  1528. status = HAL_MON_TX_MPDU_START;
  1529. SHOW_DEFINED(WIFITX_MPDU_START_E);
  1530. break;
  1531. }
  1532. case WIFITX_MSDU_START_E:/* DOWNSTREAM */
  1533. {
  1534. /* compacted */
  1535. /* we expect frame to be 802.11 frame type */
  1536. status = HAL_MON_TX_MSDU_START;
  1537. SHOW_DEFINED(WIFITX_MSDU_START_E);
  1538. break;
  1539. }
  1540. case WIFITX_DATA_E:/* DOWNSTREAM */
  1541. {
  1542. status = HAL_MON_TX_DATA;
  1543. /*
  1544. * TODO: do we need a conversion api to convert
  1545. * user_id from hw to get host user_index
  1546. */
  1547. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1548. TXMON_STATUS_INFO(tx_status_info,
  1549. buffer) = (void *)status_frag;
  1550. TXMON_STATUS_INFO(tx_status_info,
  1551. offset) = ((void *)tx_tlv -
  1552. (void *)status_frag);
  1553. TXMON_STATUS_INFO(tx_status_info,
  1554. length) = tlv_len;
  1555. /*
  1556. * reference of the status buffer will be held in
  1557. * dp_tx_update_ppdu_info_status()
  1558. */
  1559. status = HAL_MON_TX_DATA;
  1560. SHOW_DEFINED(WIFITX_DATA_E);
  1561. break;
  1562. }
  1563. case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */
  1564. {
  1565. packet_info = &ppdu_info->packet_info;
  1566. status = HAL_MON_TX_BUFFER_ADDR;
  1567. /*
  1568. * TODO: do we need a conversion api to convert
  1569. * user_id from hw to get host user_index
  1570. */
  1571. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1572. hal_txmon_populate_packet_info_generic_be(tx_tlv, packet_info);
  1573. SHOW_DEFINED(WIFIMON_BUFFER_ADDR_E);
  1574. break;
  1575. }
  1576. case WIFITX_MPDU_END_E:/* DOWNSTREAM */
  1577. {
  1578. /* no tlv content */
  1579. SHOW_DEFINED(WIFITX_MPDU_END_E);
  1580. break;
  1581. }
  1582. case WIFITX_MSDU_END_E:/* DOWNSTREAM */
  1583. {
  1584. /* no tlv content */
  1585. SHOW_DEFINED(WIFITX_MSDU_END_E);
  1586. break;
  1587. }
  1588. case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */
  1589. {
  1590. /* no tlv content */
  1591. SHOW_DEFINED(WIFITX_LAST_MPDU_FETCHED_E);
  1592. break;
  1593. }
  1594. case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */
  1595. {
  1596. /* no tlv content */
  1597. SHOW_DEFINED(WIFITX_LAST_MPDU_END_E);
  1598. break;
  1599. }
  1600. case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */
  1601. {
  1602. /*
  1603. * transmitting power
  1604. * minimum transmitting power
  1605. * desired nss
  1606. * tx chain mask
  1607. * desired bw
  1608. * duration of transmit and response
  1609. *
  1610. * since most of the field we are deriving from other tlv
  1611. * we don't need to enable this in our tlv.
  1612. */
  1613. SHOW_DEFINED(WIFICOEX_TX_REQ_E);
  1614. break;
  1615. }
  1616. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */
  1617. {
  1618. /* user tlv */
  1619. /*
  1620. * All Tx monitor will have 802.11 hdr
  1621. * we don't need to enable this TLV
  1622. */
  1623. SHOW_DEFINED(WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E);
  1624. break;
  1625. }
  1626. case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */
  1627. {
  1628. /*
  1629. * no tlv content
  1630. *
  1631. * TLV that indicates to TXPCU that preamble phase for the NDP
  1632. * frame transmission is now over
  1633. */
  1634. SHOW_DEFINED(WIFINDP_PREAMBLE_DONE_E);
  1635. break;
  1636. }
  1637. case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */
  1638. {
  1639. /*
  1640. * no tlv content
  1641. *
  1642. * TLV indicates to the SCH that all timing critical TLV
  1643. * has been passed on to the transmit path
  1644. */
  1645. SHOW_DEFINED(WIFISCH_CRITICAL_TLV_REFERENCE_E);
  1646. break;
  1647. }
  1648. case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */
  1649. {
  1650. /*
  1651. * Loopback specific setup info - not needed for Tx monitor
  1652. */
  1653. SHOW_DEFINED(WIFITX_LOOPBACK_SETUP_E);
  1654. break;
  1655. }
  1656. case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */
  1657. {
  1658. /*
  1659. * no tlv content
  1660. *
  1661. * TLV indicates that other modules besides the scheduler can
  1662. * now also start generating TLV's
  1663. * prevent colliding or generating TLV's out of order
  1664. */
  1665. SHOW_DEFINED(WIFITX_FES_SETUP_COMPLETE_E);
  1666. break;
  1667. }
  1668. case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */
  1669. {
  1670. /*
  1671. * no tlv content
  1672. *
  1673. * TLV indicates to SCH that a burst of MPDU info will
  1674. * start to come in over the TLV
  1675. */
  1676. SHOW_DEFINED(WIFITQM_MPDU_GLOBAL_START_E);
  1677. break;
  1678. }
  1679. case WIFITX_WUR_DATA_E:/* DOWNSTREAM */
  1680. {
  1681. SHOW_DEFINED(WIFITX_WUR_DATA_E);
  1682. break;
  1683. }
  1684. case WIFISCHEDULER_END_E:/* DOWNSTREAM */
  1685. {
  1686. /*
  1687. * no tlv content
  1688. *
  1689. * TLV indicates END of all TLV's within the scheduler TLV
  1690. */
  1691. SHOW_DEFINED(WIFISCHEDULER_END_E);
  1692. break;
  1693. }
  1694. /* Upstream tlv */
  1695. case WIFIPDG_TX_REQ_E:
  1696. {
  1697. SHOW_DEFINED(WIFIPDG_TX_REQ_E);
  1698. break;
  1699. }
  1700. case WIFITX_FES_STATUS_START_E:
  1701. {
  1702. /*
  1703. * TLV indicating that first transmission on the medium
  1704. */
  1705. uint8_t medium_prot_type = 0;
  1706. status = HAL_MON_TX_FES_STATUS_START;
  1707. medium_prot_type = HAL_TX_DESC_GET_64(tx_tlv,
  1708. TX_FES_STATUS_START,
  1709. MEDIUM_PROT_TYPE);
  1710. ppdu_info = (struct hal_tx_ppdu_info *)prot_ppdu_info;
  1711. /* update what type of medium protection frame */
  1712. TXMON_STATUS_INFO(tx_status_info,
  1713. medium_prot_type) = medium_prot_type;
  1714. SHOW_DEFINED(WIFITX_FES_STATUS_START_E);
  1715. break;
  1716. }
  1717. case WIFITX_FES_STATUS_PROT_E:
  1718. {
  1719. uint32_t start_timestamp = 0;
  1720. uint32_t end_timestamp = 0;
  1721. /*
  1722. * generated by TXPCU to indicate the result of having
  1723. * received of the expected protection frame
  1724. */
  1725. status = HAL_MON_TX_FES_STATUS_PROT;
  1726. start_timestamp =
  1727. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT,
  1728. START_OF_FRAME_TIMESTAMP_15_0);
  1729. start_timestamp |=
  1730. (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT,
  1731. START_OF_FRAME_TIMESTAMP_31_16) <<
  1732. 15);
  1733. end_timestamp = HAL_TX_DESC_GET_64(tx_tlv,
  1734. TX_FES_STATUS_PROT,
  1735. END_OF_FRAME_TIMESTAMP_15_0);
  1736. end_timestamp |=
  1737. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT,
  1738. END_OF_FRAME_TIMESTAMP_31_16) << 15;
  1739. /* ppdu timestamp as phy timestamp */
  1740. TXMON_HAL_STATUS(ppdu_info,
  1741. ppdu_timestamp) = start_timestamp;
  1742. TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag;
  1743. SHOW_DEFINED(WIFITX_FES_STATUS_PROT_E);
  1744. break;
  1745. }
  1746. case WIFITX_FES_STATUS_START_PROT_E:
  1747. {
  1748. uint64_t tsft_64;
  1749. uint32_t response_type;
  1750. status = HAL_MON_TX_FES_STATUS_START_PROT;
  1751. TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag;
  1752. /* timestamp */
  1753. tsft_64 = HAL_TX_DESC_GET_64(tx_tlv,
  1754. TX_FES_STATUS_START_PROT,
  1755. PROT_TIMESTAMP_LOWER_32);
  1756. tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv,
  1757. TX_FES_STATUS_START_PROT,
  1758. PROT_TIMESTAMP_UPPER_32) << 32);
  1759. response_type = HAL_TX_DESC_GET_64(tx_tlv,
  1760. TX_FES_STATUS_START_PROT,
  1761. RESPONSE_TYPE);
  1762. TXMON_STATUS_INFO(tx_status_info,
  1763. response_type) = response_type;
  1764. TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64;
  1765. SHOW_DEFINED(WIFITX_FES_STATUS_START_PROT_E);
  1766. break;
  1767. }
  1768. case WIFIPROT_TX_END_E:
  1769. {
  1770. /*
  1771. * no tlv content
  1772. *
  1773. * generated by TXPCU the moment that protection frame
  1774. * transmission has finished on the medium
  1775. */
  1776. SHOW_DEFINED(WIFIPROT_TX_END_E);
  1777. break;
  1778. }
  1779. case WIFITX_FES_STATUS_START_PPDU_E:
  1780. {
  1781. uint64_t tsft_64;
  1782. uint8_t ndp_frame;
  1783. status = HAL_MON_TX_FES_STATUS_START_PPDU;
  1784. tsft_64 = HAL_TX_DESC_GET_64(tx_tlv,
  1785. TX_FES_STATUS_START_PPDU,
  1786. PPDU_TIMESTAMP_LOWER_32);
  1787. tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv,
  1788. TX_FES_STATUS_START_PPDU,
  1789. PPDU_TIMESTAMP_UPPER_32) << 32);
  1790. ndp_frame = HAL_TX_DESC_GET_64(tx_tlv,
  1791. TX_FES_STATUS_START_PPDU,
  1792. NDP_FRAME);
  1793. TXMON_STATUS_INFO(tx_status_info, ndp_frame) = ndp_frame;
  1794. TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64;
  1795. SHOW_DEFINED(WIFITX_FES_STATUS_START_PPDU_E);
  1796. break;
  1797. }
  1798. case WIFITX_FES_STATUS_USER_PPDU_E:
  1799. {
  1800. /* user tlv */
  1801. uint16_t duration;
  1802. uint8_t transmitted_tid;
  1803. duration = HAL_TX_DESC_GET_64(tx_tlv,
  1804. TX_FES_STATUS_USER_PPDU,
  1805. DURATION);
  1806. transmitted_tid = HAL_TX_DESC_GET_64(tx_tlv,
  1807. TX_FES_STATUS_USER_PPDU,
  1808. TRANSMITTED_TID);
  1809. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1810. TXMON_HAL_USER(ppdu_info, user_id, tid) = transmitted_tid;
  1811. TXMON_HAL_USER(ppdu_info, user_id, duration) = duration;
  1812. status = HAL_MON_TX_FES_STATUS_USER_PPDU;
  1813. SHOW_DEFINED(WIFITX_FES_STATUS_USER_PPDU_E);
  1814. break;
  1815. }
  1816. case WIFIPPDU_TX_END_E:
  1817. {
  1818. /*
  1819. * no tlv content
  1820. *
  1821. * generated by TXPCU the moment that PPDU transmission has
  1822. * finished on the medium
  1823. */
  1824. SHOW_DEFINED(WIFIPPDU_TX_END_E);
  1825. break;
  1826. }
  1827. case WIFITX_FES_STATUS_USER_RESPONSE_E:
  1828. {
  1829. /*
  1830. * TLV contains the FES transmit result of the each
  1831. * of the MAC users. TLV are forwarded to HWSCH
  1832. */
  1833. SHOW_DEFINED(WIFITX_FES_STATUS_USER_RESPONSE_E);
  1834. break;
  1835. }
  1836. case WIFITX_FES_STATUS_ACK_OR_BA_E:
  1837. {
  1838. /* user tlv */
  1839. /*
  1840. * TLV generated by RXPCU and provide information related to
  1841. * the received BA or ACK frame
  1842. */
  1843. SHOW_DEFINED(WIFITX_FES_STATUS_ACK_OR_BA_E);
  1844. break;
  1845. }
  1846. case WIFITX_FES_STATUS_1K_BA_E:
  1847. {
  1848. /* user tlv */
  1849. /*
  1850. * TLV generated by RXPCU and providing information related
  1851. * to the received BA frame in case of 512/1024 bitmaps
  1852. */
  1853. SHOW_DEFINED(WIFITX_FES_STATUS_1K_BA_E);
  1854. break;
  1855. }
  1856. case WIFIRECEIVED_RESPONSE_USER_7_0_E:
  1857. {
  1858. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_7_0_E);
  1859. break;
  1860. }
  1861. case WIFIRECEIVED_RESPONSE_USER_15_8_E:
  1862. {
  1863. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_15_8_E);
  1864. break;
  1865. }
  1866. case WIFIRECEIVED_RESPONSE_USER_23_16_E:
  1867. {
  1868. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_23_16_E);
  1869. break;
  1870. }
  1871. case WIFIRECEIVED_RESPONSE_USER_31_24_E:
  1872. {
  1873. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_31_24_E);
  1874. break;
  1875. }
  1876. case WIFIRECEIVED_RESPONSE_USER_36_32_E:
  1877. {
  1878. /*
  1879. * RXPCU generates this TLV when it receives a response frame
  1880. * that TXPCU pre-announced it was waiting for and in
  1881. * RXPCU_SETUP TLV, TLV generated before the
  1882. * RECEIVED_RESPONSE_INFO TLV.
  1883. *
  1884. * received info user fields are there which is not needed
  1885. * for TX monitor
  1886. */
  1887. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_36_32_E);
  1888. break;
  1889. }
  1890. case WIFITXPCU_BUFFER_STATUS_E:
  1891. {
  1892. SHOW_DEFINED(WIFITXPCU_BUFFER_STATUS_E);
  1893. break;
  1894. }
  1895. case WIFITXPCU_USER_BUFFER_STATUS_E:
  1896. {
  1897. /*
  1898. * WIFITXPCU_USER_BUFFER_STATUS_E - user tlv
  1899. * for TX monitor we aren't interested in this tlv
  1900. */
  1901. SHOW_DEFINED(WIFITXPCU_USER_BUFFER_STATUS_E);
  1902. break;
  1903. }
  1904. case WIFITXDMA_STOP_REQUEST_E:
  1905. {
  1906. /*
  1907. * no tlv content
  1908. *
  1909. * TLV is destined to TXDMA and informs TXDMA to stop
  1910. * pushing data into the transmit path.
  1911. */
  1912. SHOW_DEFINED(WIFITXDMA_STOP_REQUEST_E);
  1913. break;
  1914. }
  1915. case WIFITX_CBF_INFO_E:
  1916. {
  1917. /*
  1918. * After NDPA + NDP is received, RXPCU sends the TX_CBF_INFO to
  1919. * TXPCU to respond the CBF frame
  1920. *
  1921. * compressed beamforming pkt doesn't has mac header
  1922. * Tx monitor not interested in this pkt.
  1923. */
  1924. SHOW_DEFINED(WIFITX_CBF_INFO_E);
  1925. break;
  1926. }
  1927. case WIFITX_MPDU_COUNT_TRANSFER_END_E:
  1928. {
  1929. /*
  1930. * no tlv content
  1931. *
  1932. * TLV indicates that TXPCU has finished generating the
  1933. * TQM_UPDATE_TX_MPDU_COUNT TLV for all users
  1934. */
  1935. SHOW_DEFINED(WIFITX_MPDU_COUNT_TRANSFER_END_E);
  1936. break;
  1937. }
  1938. case WIFIPDG_RESPONSE_E:
  1939. {
  1940. /*
  1941. * most of the feilds are already covered in
  1942. * other TLV
  1943. * This is generated by TX_PCU to PDG to calculate
  1944. * all the PHY header info.
  1945. *
  1946. * some useful fields like min transmit power,
  1947. * rate used for transmitting packet is present.
  1948. */
  1949. SHOW_DEFINED(WIFIPDG_RESPONSE_E);
  1950. break;
  1951. }
  1952. case WIFIPDG_TRIG_RESPONSE_E:
  1953. {
  1954. /* no tlv content */
  1955. SHOW_DEFINED(WIFIPDG_TRIG_RESPONSE_E);
  1956. break;
  1957. }
  1958. case WIFIRECEIVED_TRIGGER_INFO_E:
  1959. {
  1960. /*
  1961. * TLV generated by RXPCU to inform the scheduler that
  1962. * a trigger frame has been received
  1963. */
  1964. SHOW_DEFINED(WIFIRECEIVED_TRIGGER_INFO_E);
  1965. break;
  1966. }
  1967. case WIFIOFDMA_TRIGGER_DETAILS_E:
  1968. {
  1969. SHOW_DEFINED(WIFIOFDMA_TRIGGER_DETAILS_E);
  1970. break;
  1971. }
  1972. case WIFIRX_FRAME_BITMAP_ACK_E:
  1973. {
  1974. /* user tlv */
  1975. status = HAL_MON_RX_FRAME_BITMAP_ACK;
  1976. SHOW_DEFINED(WIFIRX_FRAME_BITMAP_ACK_E);
  1977. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1978. TXMON_STATUS_INFO(tx_status_info, no_bitmap_avail) =
  1979. HAL_TX_DESC_GET_64(tx_tlv,
  1980. RX_FRAME_BITMAP_ACK,
  1981. NO_BITMAP_AVAILABLE);
  1982. TXMON_STATUS_INFO(tx_status_info, explicit_ack) =
  1983. HAL_TX_DESC_GET_64(tx_tlv,
  1984. RX_FRAME_BITMAP_ACK,
  1985. EXPLICIT_ACK);
  1986. /*
  1987. * get mac address, since address is received frame
  1988. * change the order and store it
  1989. */
  1990. *(uint32_t *)&tx_status_info->addr2[0] =
  1991. HAL_TX_DESC_GET_64(tx_tlv,
  1992. RX_FRAME_BITMAP_ACK,
  1993. ADDR1_31_0);
  1994. *(uint32_t *)&tx_status_info->addr2[4] =
  1995. HAL_TX_DESC_GET_64(tx_tlv,
  1996. RX_FRAME_BITMAP_ACK,
  1997. ADDR1_47_32);
  1998. *(uint32_t *)&tx_status_info->addr1[0] =
  1999. HAL_TX_DESC_GET_64(tx_tlv,
  2000. RX_FRAME_BITMAP_ACK,
  2001. ADDR2_15_0);
  2002. *(uint32_t *)&tx_status_info->addr1[2] =
  2003. HAL_TX_DESC_GET_64(tx_tlv,
  2004. RX_FRAME_BITMAP_ACK,
  2005. ADDR2_47_16);
  2006. TXMON_STATUS_INFO(tx_status_info, explicit_ack_type) =
  2007. HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_BITMAP_ACK,
  2008. EXPLICT_ACK_TYPE);
  2009. TXMON_HAL_USER(ppdu_info, user_id, tid) =
  2010. HAL_TX_DESC_GET_64(tx_tlv,
  2011. RX_FRAME_BITMAP_ACK,
  2012. BA_TID);
  2013. TXMON_HAL_USER(ppdu_info, user_id, aid) =
  2014. HAL_TX_DESC_GET_64(tx_tlv,
  2015. RX_FRAME_BITMAP_ACK,
  2016. STA_FULL_AID);
  2017. TXMON_HAL_USER(ppdu_info, user_id, start_seq) =
  2018. HAL_TX_DESC_GET_64(tx_tlv,
  2019. RX_FRAME_BITMAP_ACK,
  2020. BA_TS_SEQ);
  2021. TXMON_HAL_USER(ppdu_info, user_id, ba_control) =
  2022. HAL_TX_DESC_GET_64(tx_tlv,
  2023. RX_FRAME_BITMAP_ACK,
  2024. BA_TS_CTRL);
  2025. TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) =
  2026. HAL_TX_DESC_GET_64(tx_tlv,
  2027. RX_FRAME_BITMAP_ACK,
  2028. BA_BITMAP_SIZE);
  2029. /* ba bitmap */
  2030. qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap),
  2031. &HAL_SET_FLD_OFFSET_64(tx_tlv,
  2032. RX_FRAME_BITMAP_ACK,
  2033. BA_TS_BITMAP_31_0, 0), 32);
  2034. break;
  2035. }
  2036. case WIFIRX_FRAME_1K_BITMAP_ACK_E:
  2037. {
  2038. /* user tlv */
  2039. status = HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K;
  2040. SHOW_DEFINED(WIFIRX_FRAME_1K_BITMAP_ACK_E);
  2041. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  2042. TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) =
  2043. (4 + HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_1K_BITMAP_ACK,
  2044. BA_BITMAP_SIZE));
  2045. TXMON_HAL_USER(ppdu_info, user_id, tid) =
  2046. HAL_TX_DESC_GET_64(tx_tlv,
  2047. RX_FRAME_1K_BITMAP_ACK,
  2048. BA_TID);
  2049. TXMON_HAL_USER(ppdu_info, user_id, aid) =
  2050. HAL_TX_DESC_GET_64(tx_tlv,
  2051. RX_FRAME_1K_BITMAP_ACK,
  2052. STA_FULL_AID);
  2053. /* get mac address */
  2054. *(uint32_t *)&tx_status_info->addr1[0] =
  2055. HAL_TX_DESC_GET_64(tx_tlv,
  2056. RX_FRAME_1K_BITMAP_ACK,
  2057. ADDR1_31_0);
  2058. *(uint32_t *)&tx_status_info->addr1[4] =
  2059. HAL_TX_DESC_GET_64(tx_tlv,
  2060. RX_FRAME_1K_BITMAP_ACK,
  2061. ADDR1_47_32);
  2062. *(uint32_t *)&tx_status_info->addr2[0] =
  2063. HAL_TX_DESC_GET_64(tx_tlv,
  2064. RX_FRAME_1K_BITMAP_ACK,
  2065. ADDR2_15_0);
  2066. *(uint32_t *)&tx_status_info->addr2[2] =
  2067. HAL_TX_DESC_GET_64(tx_tlv,
  2068. RX_FRAME_1K_BITMAP_ACK,
  2069. ADDR2_47_16);
  2070. TXMON_HAL_USER(ppdu_info, user_id, start_seq) =
  2071. HAL_TX_DESC_GET_64(tx_tlv,
  2072. RX_FRAME_1K_BITMAP_ACK,
  2073. BA_TS_SEQ);
  2074. TXMON_HAL_USER(ppdu_info, user_id, ba_control) =
  2075. HAL_TX_DESC_GET_64(tx_tlv,
  2076. RX_FRAME_1K_BITMAP_ACK,
  2077. BA_TS_CTRL);
  2078. /* memcpy ba bitmap */
  2079. qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap),
  2080. &HAL_SET_FLD_OFFSET_64(tx_tlv,
  2081. RX_FRAME_1K_BITMAP_ACK,
  2082. BA_TS_BITMAP_31_0, 0),
  2083. 4 << TXMON_HAL_USER(ppdu_info,
  2084. user_id, ba_bitmap_sz));
  2085. break;
  2086. }
  2087. case WIFIRESPONSE_START_STATUS_E:
  2088. {
  2089. /*
  2090. * TLV indicates which HW response the TXPCU
  2091. * started generating
  2092. *
  2093. * HW generated frames like
  2094. * ACK frame - handled
  2095. * CTS frame - handled
  2096. * BA frame - handled
  2097. * MBA frame - handled
  2098. * CBF frame - no frame header
  2099. * Trigger response - TODO
  2100. * NDP LMR - no frame header
  2101. */
  2102. SHOW_DEFINED(WIFIRESPONSE_START_STATUS_E);
  2103. break;
  2104. }
  2105. case WIFIRX_START_PARAM_E:
  2106. {
  2107. /*
  2108. * RXPCU send this TLV after PHY RX detected a frame
  2109. * in the medium
  2110. *
  2111. * TX monitor not interested in this TLV
  2112. */
  2113. SHOW_DEFINED(WIFIRX_START_PARAM_E);
  2114. break;
  2115. }
  2116. case WIFIRXPCU_EARLY_RX_INDICATION_E:
  2117. {
  2118. /*
  2119. * early indication of pkt type and mcs rate
  2120. * already captured in other tlv
  2121. */
  2122. SHOW_DEFINED(WIFIRXPCU_EARLY_RX_INDICATION_E);
  2123. break;
  2124. }
  2125. case WIFIRX_PM_INFO_E:
  2126. {
  2127. SHOW_DEFINED(WIFIRX_PM_INFO_E);
  2128. break;
  2129. }
  2130. /* Active window */
  2131. case WIFITX_FLUSH_REQ_E:
  2132. {
  2133. SHOW_DEFINED(WIFITX_FLUSH_REQ_E);
  2134. break;
  2135. }
  2136. case WIFICOEX_TX_STATUS_E:
  2137. {
  2138. /* duration are retrieved from coex tx status */
  2139. uint16_t duration;
  2140. uint8_t status_reason;
  2141. status = HAL_MON_COEX_TX_STATUS;
  2142. duration = HAL_TX_DESC_GET_64(tx_tlv,
  2143. COEX_TX_STATUS,
  2144. CURRENT_TX_DURATION);
  2145. status_reason = HAL_TX_DESC_GET_64(tx_tlv,
  2146. COEX_TX_STATUS,
  2147. TX_STATUS_REASON);
  2148. /* update duration */
  2149. if (status_reason == COEX_FES_TX_START ||
  2150. status_reason == COEX_RESPONSE_TX_START)
  2151. TXMON_HAL_USER(ppdu_info, user_id, duration) = duration;
  2152. SHOW_DEFINED(WIFICOEX_TX_STATUS_E);
  2153. break;
  2154. }
  2155. case WIFIR2R_STATUS_END_E:
  2156. {
  2157. SHOW_DEFINED(WIFIR2R_STATUS_END_E);
  2158. break;
  2159. }
  2160. case WIFIRX_PREAMBLE_E:
  2161. {
  2162. SHOW_DEFINED(WIFIRX_PREAMBLE_E);
  2163. break;
  2164. }
  2165. case WIFIMACTX_SERVICE_E:
  2166. {
  2167. SHOW_DEFINED(WIFIMACTX_SERVICE_E);
  2168. break;
  2169. }
  2170. case WIFIMACTX_U_SIG_EHT_SU_MU_E:
  2171. {
  2172. struct hal_mon_usig_hdr *usig = NULL;
  2173. struct hal_mon_usig_mu *usig_mu = NULL;
  2174. usig = (struct hal_mon_usig_hdr *)tx_tlv;
  2175. usig_mu = &usig->usig_2.mu;
  2176. hal_txmon_parse_u_sig_hdr(tx_tlv, ppdu_info);
  2177. TXMON_HAL_STATUS(ppdu_info, usig_mask) |=
  2178. QDF_MON_STATUS_USIG_DISREGARD_KNOWN |
  2179. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN |
  2180. QDF_MON_STATUS_USIG_VALIDATE_KNOWN |
  2181. QDF_MON_STATUS_USIG_MU_VALIDATE1_KNOWN |
  2182. QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_KNOWN |
  2183. QDF_MON_STATUS_USIG_MU_VALIDATE2_KNOWN |
  2184. QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_KNOWN |
  2185. QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_KNOWN |
  2186. QDF_MON_STATUS_USIG_CRC_KNOWN |
  2187. QDF_MON_STATUS_USIG_TAIL_KNOWN;
  2188. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2189. (0x1F << QDF_MON_STATUS_USIG_DISREGARD_SHIFT);
  2190. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2191. (0x1 << QDF_MON_STATUS_USIG_MU_VALIDATE1_SHIFT);
  2192. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2193. (usig_mu->ppdu_type_comp_mode <<
  2194. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT);
  2195. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2196. (0x1 << QDF_MON_STATUS_USIG_VALIDATE_SHIFT);
  2197. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2198. (usig_mu->punc_ch_info <<
  2199. QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_SHIFT);
  2200. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2201. (0x1 << QDF_MON_STATUS_USIG_MU_VALIDATE2_SHIFT);
  2202. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2203. (usig_mu->eht_sig_mcs <<
  2204. QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_SHIFT);
  2205. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2206. (usig_mu->num_eht_sig_sym <<
  2207. QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_SHIFT);
  2208. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2209. (usig_mu->crc << QDF_MON_STATUS_USIG_CRC_SHIFT);
  2210. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2211. (usig_mu->tail << QDF_MON_STATUS_USIG_TAIL_SHIFT);
  2212. SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_SU_MU_E);
  2213. break;
  2214. }
  2215. case WIFIMACTX_U_SIG_EHT_TB_E:
  2216. {
  2217. struct hal_mon_usig_hdr *usig = NULL;
  2218. struct hal_mon_usig_tb *usig_tb = NULL;
  2219. usig = (struct hal_mon_usig_hdr *)tx_tlv;
  2220. usig_tb = &usig->usig_2.tb;
  2221. hal_txmon_parse_u_sig_hdr(tx_tlv, ppdu_info);
  2222. TXMON_HAL_STATUS(ppdu_info, usig_mask) |=
  2223. QDF_MON_STATUS_USIG_DISREGARD_KNOWN |
  2224. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN |
  2225. QDF_MON_STATUS_USIG_VALIDATE_KNOWN |
  2226. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_KNOWN |
  2227. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_KNOWN |
  2228. QDF_MON_STATUS_USIG_TB_DISREGARD1_KNOWN |
  2229. QDF_MON_STATUS_USIG_CRC_KNOWN |
  2230. QDF_MON_STATUS_USIG_TAIL_KNOWN;
  2231. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2232. (0x3F << QDF_MON_STATUS_USIG_DISREGARD_SHIFT);
  2233. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2234. (usig_tb->ppdu_type_comp_mode <<
  2235. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT);
  2236. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2237. (0x1 << QDF_MON_STATUS_USIG_VALIDATE_SHIFT);
  2238. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2239. (usig_tb->spatial_reuse_1 <<
  2240. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_SHIFT);
  2241. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2242. (usig_tb->spatial_reuse_2 <<
  2243. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_SHIFT);
  2244. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2245. (0x1F << QDF_MON_STATUS_USIG_TB_DISREGARD1_SHIFT);
  2246. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2247. (usig_tb->crc << QDF_MON_STATUS_USIG_CRC_SHIFT);
  2248. TXMON_HAL_STATUS(ppdu_info, usig_value) |=
  2249. (usig_tb->tail << QDF_MON_STATUS_USIG_TAIL_SHIFT);
  2250. SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_TB_E);
  2251. break;
  2252. }
  2253. case WIFIMACTX_EHT_SIG_USR_OFDMA_E:
  2254. {
  2255. hal_txmon_parse_eht_sig_non_mumimo_user_info(tx_tlv, user_id,
  2256. ppdu_info);
  2257. TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1;
  2258. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_OFDMA_E);
  2259. break;
  2260. }
  2261. case WIFIMACTX_EHT_SIG_USR_MU_MIMO_E:
  2262. {
  2263. hal_txmon_parse_eht_sig_mumimo_user_info(tx_tlv, user_id,
  2264. ppdu_info);
  2265. TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1;
  2266. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_MU_MIMO_E);
  2267. break;
  2268. }
  2269. case WIFIMACTX_EHT_SIG_USR_SU_E:
  2270. {
  2271. hal_txmon_parse_eht_sig_non_mumimo_user_info(tx_tlv, user_id,
  2272. ppdu_info);
  2273. TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1;
  2274. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_SU_E);
  2275. /* TODO: no radiotap info available */
  2276. break;
  2277. }
  2278. case WIFIMACTX_HE_SIG_A_SU_E:
  2279. {
  2280. uint16_t he_mu_flag_1 = 0;
  2281. uint16_t he_mu_flag_2 = 0;
  2282. uint16_t num_users = 0;
  2283. uint8_t mcs_of_sig_b = 0;
  2284. uint8_t dcm_of_sig_b = 0;
  2285. uint8_t sig_a_bw = 0;
  2286. uint8_t i = 0;
  2287. uint8_t bss_color_id;
  2288. uint8_t coding;
  2289. uint8_t stbc;
  2290. uint8_t a_factor;
  2291. uint8_t pe_disambiguity;
  2292. uint8_t txbf;
  2293. uint8_t txbw;
  2294. uint8_t txop;
  2295. status = HAL_MON_MACTX_HE_SIG_A_SU;
  2296. num_users = TXMON_HAL(ppdu_info, num_users);
  2297. mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2298. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2299. TRANSMIT_MCS);
  2300. dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2301. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2302. DCM);
  2303. sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv,
  2304. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2305. TRANSMIT_BW);
  2306. bss_color_id = HAL_TX_DESC_GET_64(tx_tlv,
  2307. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2308. BSS_COLOR_ID);
  2309. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2310. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2311. CODING);
  2312. stbc = HAL_TX_DESC_GET_64(tx_tlv,
  2313. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2314. STBC);
  2315. a_factor = HAL_TX_DESC_GET_64(tx_tlv,
  2316. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2317. PACKET_EXTENSION_A_FACTOR);
  2318. pe_disambiguity = HAL_TX_DESC_GET_64(tx_tlv,
  2319. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2320. PACKET_EXTENSION_PE_DISAMBIGUITY);
  2321. txbf = HAL_TX_DESC_GET_64(tx_tlv,
  2322. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2323. TXBF);
  2324. txbw = HAL_TX_DESC_GET_64(tx_tlv,
  2325. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2326. TRANSMIT_BW);
  2327. txop = HAL_TX_DESC_GET_64(tx_tlv,
  2328. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  2329. TXOP_DURATION);
  2330. he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  2331. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  2332. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  2333. QDF_MON_STATUS_CHANNEL_1_RU_KNOWN |
  2334. QDF_MON_STATUS_CHANNEL_2_RU_KNOWN |
  2335. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN;
  2336. /* MCS */
  2337. he_mu_flag_1 |= mcs_of_sig_b <<
  2338. QDF_MON_STATUS_SIG_B_MCS_SHIFT;
  2339. /* DCM */
  2340. he_mu_flag_1 |= dcm_of_sig_b <<
  2341. QDF_MON_STATUS_SIG_B_DCM_SHIFT;
  2342. /* bandwidth */
  2343. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN;
  2344. he_mu_flag_2 |= sig_a_bw <<
  2345. QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT;
  2346. TXMON_HAL_STATUS(ppdu_info,
  2347. he_mu_flags) = IS_MULTI_USERS(num_users);
  2348. for (i = 0; i < num_users; i++) {
  2349. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2350. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2351. }
  2352. /* HE data 1 */
  2353. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2354. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  2355. QDF_MON_STATUS_HE_CODING_KNOWN;
  2356. /* HE data 2 */
  2357. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2358. QDF_MON_STATUS_TXBF_KNOWN |
  2359. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  2360. QDF_MON_STATUS_TXOP_KNOWN |
  2361. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  2362. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  2363. /* HE data 3 */
  2364. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2365. bss_color_id |
  2366. (!!txbf << QDF_MON_STATUS_BEAM_CHANGE_SHIFT) |
  2367. (coding << QDF_MON_STATUS_CODING_SHIFT) |
  2368. (stbc << QDF_MON_STATUS_STBC_SHIFT);
  2369. /* HE data 6 */
  2370. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |=
  2371. (txop << QDF_MON_STATUS_TXOP_SHIFT);
  2372. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_SU_E);
  2373. break;
  2374. }
  2375. case WIFIMACTX_HE_SIG_A_MU_DL_E:
  2376. {
  2377. uint16_t he_mu_flag_1 = 0;
  2378. uint16_t he_mu_flag_2 = 0;
  2379. uint16_t num_users = 0;
  2380. uint8_t bss_color_id;
  2381. uint8_t txop;
  2382. uint8_t mcs_of_sig_b = 0;
  2383. uint8_t dcm_of_sig_b = 0;
  2384. uint8_t sig_a_bw = 0;
  2385. uint8_t num_sig_b_symb = 0;
  2386. uint8_t comp_mode_sig_b = 0;
  2387. uint8_t punc_bw = 0;
  2388. uint8_t i = 0;
  2389. status = HAL_MON_MACTX_HE_SIG_A_MU_DL;
  2390. num_users = TXMON_HAL(ppdu_info, num_users);
  2391. mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2392. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2393. MCS_OF_SIG_B);
  2394. dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2395. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2396. DCM_OF_SIG_B);
  2397. sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv,
  2398. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2399. TRANSMIT_BW);
  2400. num_sig_b_symb = HAL_TX_DESC_GET_64(tx_tlv,
  2401. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2402. NUM_SIG_B_SYMBOLS);
  2403. comp_mode_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  2404. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2405. COMP_MODE_SIG_B);
  2406. bss_color_id = HAL_TX_DESC_GET_64(tx_tlv,
  2407. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2408. BSS_COLOR_ID);
  2409. txop = HAL_TX_DESC_GET_64(tx_tlv,
  2410. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  2411. TXOP_DURATION);
  2412. he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  2413. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  2414. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  2415. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  2416. QDF_MON_STATUS_CHANNEL_1_RU_KNOWN |
  2417. QDF_MON_STATUS_CHANNEL_2_RU_KNOWN |
  2418. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN |
  2419. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  2420. QDF_MON_STATUS_SIG_B_SYMBOL_USER_KNOWN;
  2421. /* MCS */
  2422. he_mu_flag_1 |= mcs_of_sig_b <<
  2423. QDF_MON_STATUS_SIG_B_MCS_SHIFT;
  2424. /* DCM */
  2425. he_mu_flag_1 |= dcm_of_sig_b <<
  2426. QDF_MON_STATUS_SIG_B_DCM_SHIFT;
  2427. /* Compression */
  2428. he_mu_flag_2 |= comp_mode_sig_b <<
  2429. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  2430. /* bandwidth */
  2431. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN;
  2432. he_mu_flag_2 |= sig_a_bw <<
  2433. QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT;
  2434. he_mu_flag_2 |= comp_mode_sig_b <<
  2435. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  2436. /* number of symbol */
  2437. he_mu_flag_2 |= num_sig_b_symb <<
  2438. QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  2439. /* puncture bw */
  2440. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_KNOWN;
  2441. punc_bw = sig_a_bw;
  2442. he_mu_flag_2 |=
  2443. punc_bw << QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_SHIFT;
  2444. /* copy per user info to all user */
  2445. TXMON_HAL_STATUS(ppdu_info,
  2446. he_mu_flags) = IS_MULTI_USERS(num_users);
  2447. for (i = 0; i < num_users; i++) {
  2448. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2449. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2450. }
  2451. /* HE data 1 */
  2452. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2453. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN;
  2454. /* HE data 2 */
  2455. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2456. QDF_MON_STATUS_TXOP_KNOWN;
  2457. /* HE data 3 */
  2458. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= bss_color_id;
  2459. /* HE data 6 */
  2460. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |=
  2461. (txop << QDF_MON_STATUS_TXOP_SHIFT);
  2462. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_DL_E);
  2463. break;
  2464. }
  2465. case WIFIMACTX_HE_SIG_A_MU_UL_E:
  2466. {
  2467. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_UL_E);
  2468. break;
  2469. }
  2470. case WIFIMACTX_HE_SIG_B1_MU_E:
  2471. {
  2472. status = HAL_MON_MACTX_HE_SIG_B1_MU;
  2473. SHOW_DEFINED(WIFIMACTX_HE_SIG_B1_MU_E);
  2474. break;
  2475. }
  2476. case WIFIMACTX_HE_SIG_B2_MU_E:
  2477. {
  2478. /* user tlv */
  2479. uint16_t sta_id = 0;
  2480. uint16_t sta_spatial_config = 0;
  2481. uint8_t sta_mcs = 0;
  2482. uint8_t coding = 0;
  2483. uint8_t nss = 0;
  2484. uint8_t user_order = 0;
  2485. status = HAL_MON_MACTX_HE_SIG_B2_MU;
  2486. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  2487. sta_id = HAL_TX_DESC_GET_64(tx_tlv,
  2488. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2489. STA_ID);
  2490. sta_spatial_config = HAL_TX_DESC_GET_64(tx_tlv,
  2491. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2492. STA_SPATIAL_CONFIG);
  2493. sta_mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2494. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2495. STA_MCS);
  2496. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2497. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2498. STA_CODING);
  2499. nss = HAL_TX_DESC_GET_64(tx_tlv,
  2500. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2501. NSTS) + 1;
  2502. user_order = HAL_TX_DESC_GET_64(tx_tlv,
  2503. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  2504. USER_ORDER);
  2505. /* HE data 1 */
  2506. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2507. QDF_MON_STATUS_HE_MCS_KNOWN |
  2508. QDF_MON_STATUS_HE_CODING_KNOWN;
  2509. /* HE data 2 */
  2510. /* HE data 3 */
  2511. TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs;
  2512. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2513. sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  2514. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2515. coding << QDF_MON_STATUS_CODING_SHIFT;
  2516. /* HE data 4 */
  2517. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |=
  2518. sta_id << QDF_MON_STATUS_STA_ID_SHIFT;
  2519. /* HE data 5 */
  2520. /* HE data 6 */
  2521. TXMON_HAL_USER(ppdu_info, user_id, nss) = nss;
  2522. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss;
  2523. SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_MU_E);
  2524. break;
  2525. }
  2526. case WIFIMACTX_HE_SIG_B2_OFDMA_E:
  2527. {
  2528. /* user tlv */
  2529. uint8_t *he_sig_b2_ofdma_info = NULL;
  2530. uint16_t sta_id = 0;
  2531. uint8_t nss = 0;
  2532. uint8_t txbf = 0;
  2533. uint8_t sta_mcs = 0;
  2534. uint8_t sta_dcm = 0;
  2535. uint8_t coding = 0;
  2536. uint8_t user_order = 0;
  2537. status = HAL_MON_MACTX_HE_SIG_B2_OFDMA;
  2538. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  2539. he_sig_b2_ofdma_info = (uint8_t *)tx_tlv +
  2540. HAL_OFFSET(MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2541. STA_ID);
  2542. sta_id = HAL_TX_DESC_GET_64(tx_tlv,
  2543. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2544. STA_ID);
  2545. nss = HAL_TX_DESC_GET_64(tx_tlv,
  2546. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2547. NSTS);
  2548. txbf = HAL_TX_DESC_GET_64(tx_tlv,
  2549. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2550. TXBF);
  2551. sta_mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2552. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2553. STA_MCS);
  2554. sta_dcm = HAL_TX_DESC_GET_64(tx_tlv,
  2555. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2556. STA_DCM);
  2557. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2558. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2559. STA_CODING);
  2560. user_order = HAL_TX_DESC_GET_64(tx_tlv,
  2561. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  2562. USER_ORDER);
  2563. /* HE data 1 */
  2564. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  2565. QDF_MON_STATUS_HE_MCS_KNOWN |
  2566. QDF_MON_STATUS_HE_CODING_KNOWN |
  2567. QDF_MON_STATUS_HE_DCM_KNOWN;
  2568. /* HE data 2 */
  2569. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  2570. QDF_MON_STATUS_TXBF_KNOWN;
  2571. /* HE data 3 */
  2572. TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs;
  2573. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2574. sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  2575. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2576. sta_dcm << QDF_MON_STATUS_DCM_SHIFT;
  2577. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  2578. coding << QDF_MON_STATUS_CODING_SHIFT;
  2579. /* HE data 4 */
  2580. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |=
  2581. sta_id << QDF_MON_STATUS_STA_ID_SHIFT;
  2582. /* HE data 5 */
  2583. TXMON_HAL_USER(ppdu_info, user_id, he_data5) |=
  2584. txbf << QDF_MON_STATUS_TXBF_SHIFT;
  2585. /* HE data 6 */
  2586. TXMON_HAL_USER(ppdu_info, user_id, nss) = nss;
  2587. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss;
  2588. SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_OFDMA_E);
  2589. break;
  2590. }
  2591. case WIFIMACTX_L_SIG_A_E:
  2592. {
  2593. uint8_t *l_sig_a_info = NULL;
  2594. uint8_t rate = 0;
  2595. status = HAL_MON_MACTX_L_SIG_A;
  2596. l_sig_a_info = (uint8_t *)tx_tlv +
  2597. HAL_OFFSET(MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS,
  2598. RATE);
  2599. rate = HAL_TX_DESC_GET_64(tx_tlv,
  2600. MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS,
  2601. RATE);
  2602. switch (rate) {
  2603. case 8:
  2604. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_0MCS;
  2605. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0;
  2606. break;
  2607. case 9:
  2608. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_1MCS;
  2609. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1;
  2610. break;
  2611. case 10:
  2612. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_2MCS;
  2613. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2;
  2614. break;
  2615. case 11:
  2616. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_3MCS;
  2617. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3;
  2618. break;
  2619. case 12:
  2620. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_4MCS;
  2621. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4;
  2622. break;
  2623. case 13:
  2624. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_5MCS;
  2625. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5;
  2626. break;
  2627. case 14:
  2628. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_6MCS;
  2629. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6;
  2630. break;
  2631. case 15:
  2632. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_7MCS;
  2633. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS7;
  2634. break;
  2635. default:
  2636. break;
  2637. }
  2638. TXMON_HAL_STATUS(ppdu_info, ofdm_flag) = 1;
  2639. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2640. TXMON_HAL_STATUS(ppdu_info,
  2641. l_sig_a_info) = *((uint32_t *)l_sig_a_info);
  2642. SHOW_DEFINED(WIFIMACTX_L_SIG_A_E);
  2643. break;
  2644. }
  2645. case WIFIMACTX_L_SIG_B_E:
  2646. {
  2647. uint8_t *l_sig_b_info = NULL;
  2648. uint8_t rate = 0;
  2649. status = HAL_MON_MACTX_L_SIG_B;
  2650. l_sig_b_info = (uint8_t *)tx_tlv +
  2651. HAL_OFFSET(MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS,
  2652. RATE);
  2653. rate = HAL_TX_DESC_GET_64(tx_tlv,
  2654. MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS,
  2655. RATE);
  2656. switch (rate) {
  2657. case 1:
  2658. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_3MCS;
  2659. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3;
  2660. break;
  2661. case 2:
  2662. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_2MCS;
  2663. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2;
  2664. break;
  2665. case 3:
  2666. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_1MCS;
  2667. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1;
  2668. break;
  2669. case 4:
  2670. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_0MCS;
  2671. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0;
  2672. break;
  2673. case 5:
  2674. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_6MCS;
  2675. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6;
  2676. break;
  2677. case 6:
  2678. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_5MCS;
  2679. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5;
  2680. break;
  2681. case 7:
  2682. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_4MCS;
  2683. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4;
  2684. break;
  2685. default:
  2686. break;
  2687. }
  2688. TXMON_HAL_STATUS(ppdu_info, cck_flag) = 1;
  2689. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2690. TXMON_HAL_STATUS(ppdu_info, l_sig_b_info) = *l_sig_b_info;
  2691. SHOW_DEFINED(WIFIMACTX_L_SIG_B_E);
  2692. break;
  2693. }
  2694. case WIFIMACTX_HT_SIG_E:
  2695. {
  2696. uint8_t mcs = 0;
  2697. uint8_t bw = 0;
  2698. uint8_t is_stbc = 0;
  2699. uint8_t coding = 0;
  2700. uint8_t gi = 0;
  2701. status = HAL_MON_MACTX_HT_SIG;
  2702. mcs = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, MCS);
  2703. bw = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, CBW);
  2704. is_stbc = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, STBC);
  2705. coding = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, FEC_CODING);
  2706. gi = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, SHORT_GI);
  2707. TXMON_HAL_STATUS(ppdu_info, ldpc) =
  2708. (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0;
  2709. TXMON_HAL_STATUS(ppdu_info, ht_mcs) = mcs;
  2710. TXMON_HAL_STATUS(ppdu_info, bw) = bw;
  2711. TXMON_HAL_STATUS(ppdu_info, sgi) = gi;
  2712. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2713. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  2714. SHOW_DEFINED(WIFIMACTX_HT_SIG_E);
  2715. break;
  2716. }
  2717. case WIFIMACTX_VHT_SIG_A_E:
  2718. {
  2719. uint8_t bandwidth = 0;
  2720. uint8_t is_stbc = 0;
  2721. uint8_t group_id = 0;
  2722. uint32_t nss_comb = 0;
  2723. uint8_t nss_su = 0;
  2724. uint8_t nss_mu[4] = {0};
  2725. uint8_t sgi = 0;
  2726. uint8_t coding = 0;
  2727. uint8_t mcs = 0;
  2728. uint8_t beamformed = 0;
  2729. uint8_t partial_aid = 0;
  2730. status = HAL_MON_MACTX_VHT_SIG_A;
  2731. bandwidth = HAL_TX_DESC_GET_64(tx_tlv,
  2732. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2733. BANDWIDTH);
  2734. is_stbc = HAL_TX_DESC_GET_64(tx_tlv,
  2735. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2736. STBC);
  2737. group_id = HAL_TX_DESC_GET_64(tx_tlv,
  2738. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2739. GROUP_ID);
  2740. /* nss_comb is su nss, MU nss and partial AID */
  2741. nss_comb = HAL_TX_DESC_GET_64(tx_tlv,
  2742. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2743. N_STS);
  2744. /* if it is SU */
  2745. nss_su = (nss_comb & 0x7) + 1;
  2746. /* partial aid - applicable only for SU */
  2747. partial_aid = (nss_comb >> 3) & 0x1F;
  2748. /* if it is MU */
  2749. nss_mu[0] = (nss_comb & 0x7) + 1;
  2750. nss_mu[1] = ((nss_comb >> 3) & 0x7) + 1;
  2751. nss_mu[2] = ((nss_comb >> 6) & 0x7) + 1;
  2752. nss_mu[3] = ((nss_comb >> 9) & 0x7) + 1;
  2753. sgi = HAL_TX_DESC_GET_64(tx_tlv,
  2754. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2755. GI_SETTING);
  2756. coding = HAL_TX_DESC_GET_64(tx_tlv,
  2757. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2758. SU_MU_CODING);
  2759. mcs = HAL_TX_DESC_GET_64(tx_tlv,
  2760. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2761. MCS);
  2762. beamformed = HAL_TX_DESC_GET_64(tx_tlv,
  2763. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  2764. BEAMFORMED);
  2765. TXMON_HAL_STATUS(ppdu_info, ldpc) =
  2766. (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0;
  2767. TXMON_STATUS_INFO(tx_status_info, sw_frame_group_id) = group_id;
  2768. TXMON_HAL_STATUS(ppdu_info, sgi) = sgi;
  2769. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2770. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  2771. TXMON_HAL_STATUS(ppdu_info, beamformed) = beamformed;
  2772. if (group_id == 0 || group_id == 63) {
  2773. TXMON_HAL_STATUS(ppdu_info, reception_type) =
  2774. HAL_RX_TYPE_SU;
  2775. TXMON_HAL_STATUS(ppdu_info, mcs) = mcs;
  2776. TXMON_HAL_STATUS(ppdu_info, nss) =
  2777. nss_su & VHT_SIG_SU_NSS_MASK;
  2778. TXMON_HAL_USER(ppdu_info, user_id,
  2779. vht_flag_values3[0]) = ((mcs << 4) |
  2780. nss_su);
  2781. } else {
  2782. TXMON_HAL_STATUS(ppdu_info, reception_type) =
  2783. HAL_RX_TYPE_MU_MIMO;
  2784. TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs;
  2785. TXMON_HAL_USER(ppdu_info, user_id, nss) =
  2786. nss_su & VHT_SIG_SU_NSS_MASK;
  2787. TXMON_HAL_USER(ppdu_info, user_id,
  2788. vht_flag_values3[0]) = ((mcs << 4) |
  2789. nss_su);
  2790. TXMON_HAL_USER(ppdu_info, user_id,
  2791. vht_flag_values3[1]) = ((mcs << 4) |
  2792. nss_mu[1]);
  2793. TXMON_HAL_USER(ppdu_info, user_id,
  2794. vht_flag_values3[2]) = ((mcs << 4) |
  2795. nss_mu[2]);
  2796. TXMON_HAL_USER(ppdu_info, user_id,
  2797. vht_flag_values3[3]) = ((mcs << 4) |
  2798. nss_mu[3]);
  2799. }
  2800. /* TODO: loop over multiple user */
  2801. TXMON_HAL_USER(ppdu_info, user_id,
  2802. vht_flag_values2) = bandwidth;
  2803. TXMON_HAL_USER(ppdu_info, user_id,
  2804. vht_flag_values4) = coding;
  2805. TXMON_HAL_USER(ppdu_info, user_id,
  2806. vht_flag_values5) = group_id;
  2807. TXMON_HAL_USER(ppdu_info, user_id,
  2808. vht_flag_values6) = partial_aid;
  2809. SHOW_DEFINED(WIFIMACTX_VHT_SIG_A_E);
  2810. break;
  2811. }
  2812. case WIFIMACTX_VHT_SIG_B_MU160_E:
  2813. {
  2814. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU160_E);
  2815. break;
  2816. }
  2817. case WIFIMACTX_VHT_SIG_B_MU80_E:
  2818. {
  2819. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU80_E);
  2820. break;
  2821. }
  2822. case WIFIMACTX_VHT_SIG_B_MU40_E:
  2823. {
  2824. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU40_E);
  2825. break;
  2826. }
  2827. case WIFIMACTX_VHT_SIG_B_MU20_E:
  2828. {
  2829. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU20_E);
  2830. break;
  2831. }
  2832. case WIFIMACTX_VHT_SIG_B_SU160_E:
  2833. {
  2834. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU160_E);
  2835. break;
  2836. }
  2837. case WIFIMACTX_VHT_SIG_B_SU80_E:
  2838. {
  2839. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU80_E);
  2840. break;
  2841. }
  2842. case WIFIMACTX_VHT_SIG_B_SU40_E:
  2843. {
  2844. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU40_E);
  2845. break;
  2846. }
  2847. case WIFIMACTX_VHT_SIG_B_SU20_E:
  2848. {
  2849. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU20_E);
  2850. break;
  2851. }
  2852. case WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E:
  2853. {
  2854. SHOW_DEFINED(WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E);
  2855. break;
  2856. }
  2857. case WIFIMACTX_USER_DESC_PER_USER_E:
  2858. {
  2859. hal_txmon_parse_user_desc_per_user(tx_tlv, user_id, ppdu_info);
  2860. SHOW_DEFINED(WIFIMACTX_USER_DESC_PER_USER_E);
  2861. break;
  2862. }
  2863. case WIFIMACTX_USER_DESC_COMMON_E:
  2864. {
  2865. hal_txmon_parse_user_desc_common(tx_tlv, user_id, ppdu_info);
  2866. /* copy per user info to all user */
  2867. SHOW_DEFINED(WIFIMACTX_USER_DESC_COMMON_E);
  2868. break;
  2869. }
  2870. case WIFIMACTX_PHY_DESC_E:
  2871. {
  2872. /* pkt_type - preamble type */
  2873. uint32_t pkt_type = 0;
  2874. uint8_t bandwidth = 0;
  2875. uint8_t is_stbc = 0;
  2876. uint8_t is_triggered = 0;
  2877. uint8_t gi = 0;
  2878. uint8_t he_ppdu_subtype = 0;
  2879. uint32_t ltf_size = 0;
  2880. uint32_t he_data1 = 0;
  2881. uint32_t he_data2 = 0;
  2882. uint32_t he_data3 = 0;
  2883. uint32_t he_data5 = 0;
  2884. uint16_t he_mu_flag_1 = 0;
  2885. uint16_t he_mu_flag_2 = 0;
  2886. uint16_t num_users = 0;
  2887. uint8_t i = 0;
  2888. SHOW_DEFINED(WIFIMACTX_PHY_DESC_E);
  2889. status = HAL_MON_MACTX_PHY_DESC;
  2890. num_users = TXMON_HAL(ppdu_info, num_users);
  2891. pkt_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, PKT_TYPE);
  2892. is_stbc = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, STBC);
  2893. is_triggered = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2894. TRIGGERED);
  2895. if (!is_triggered) {
  2896. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2897. BANDWIDTH);
  2898. } else {
  2899. /*
  2900. * is_triggered, bw is minimum of AP pkt bw
  2901. * or STA bw
  2902. */
  2903. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2904. AP_PKT_BW);
  2905. }
  2906. gi = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2907. CP_SETTING);
  2908. ltf_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, LTF_SIZE);
  2909. he_ppdu_subtype = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2910. HE_PPDU_SUBTYPE);
  2911. TXMON_HAL_STATUS(ppdu_info, preamble_type) = pkt_type;
  2912. TXMON_HAL_STATUS(ppdu_info, ltf_size) = ltf_size;
  2913. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2914. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  2915. switch (ppdu_info->rx_status.preamble_type) {
  2916. case TXMON_PKT_TYPE_11N_MM:
  2917. TXMON_HAL_STATUS(ppdu_info, ht_flags) = 1;
  2918. TXMON_HAL_STATUS(ppdu_info,
  2919. rtap_flags) |= HT_SGI_PRESENT;
  2920. break;
  2921. case TXMON_PKT_TYPE_11AC:
  2922. TXMON_HAL_STATUS(ppdu_info, vht_flags) = 1;
  2923. break;
  2924. case TXMON_PKT_TYPE_11AX:
  2925. TXMON_HAL_STATUS(ppdu_info, he_flags) = 1;
  2926. break;
  2927. default:
  2928. break;
  2929. }
  2930. if (!TXMON_HAL_STATUS(ppdu_info, he_flags))
  2931. break;
  2932. /* update he flags */
  2933. /* PPDU FORMAT */
  2934. switch (he_ppdu_subtype) {
  2935. case TXMON_HE_SUBTYPE_SU:
  2936. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2937. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  2938. break;
  2939. case TXMON_HE_SUBTYPE_TRIG:
  2940. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2941. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  2942. break;
  2943. case TXMON_HE_SUBTYPE_MU:
  2944. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2945. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  2946. break;
  2947. case TXMON_HE_SUBTYPE_EXT_SU:
  2948. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2949. QDF_MON_STATUS_HE_EXT_SU_FORMAT_TYPE;
  2950. break;
  2951. };
  2952. /* STBC */
  2953. he_data1 |= QDF_MON_STATUS_HE_STBC_KNOWN;
  2954. he_data3 |= (is_stbc << QDF_MON_STATUS_STBC_SHIFT);
  2955. /* GI */
  2956. he_data2 |= QDF_MON_STATUS_HE_GI_KNOWN;
  2957. he_data5 |= (gi << QDF_MON_STATUS_GI_SHIFT);
  2958. /* Data BW and RU allocation */
  2959. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  2960. he_data5 = (he_data5 & 0xFFF0) | bandwidth;
  2961. he_data2 |= QDF_MON_STATUS_LTF_SYMBOLS_KNOWN;
  2962. he_data5 |= ((1 + ltf_size) <<
  2963. QDF_MON_STATUS_HE_LTF_SIZE_SHIFT);
  2964. TXMON_HAL_STATUS(ppdu_info,
  2965. he_mu_flags) = IS_MULTI_USERS(num_users);
  2966. /* MAC TX PHY DESC is not a user tlv */
  2967. for (i = 0; i < num_users; i++) {
  2968. TXMON_HAL_USER(ppdu_info, i, he_data1) = he_data1;
  2969. TXMON_HAL_USER(ppdu_info, i, he_data2) = he_data2;
  2970. TXMON_HAL_USER(ppdu_info, i, he_data3) = he_data3;
  2971. TXMON_HAL_USER(ppdu_info, i, he_data5) = he_data5;
  2972. /* HE MU flags */
  2973. TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1;
  2974. TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2;
  2975. }
  2976. break;
  2977. }
  2978. case WIFICOEX_RX_STATUS_E:
  2979. {
  2980. SHOW_DEFINED(WIFICOEX_RX_STATUS_E);
  2981. break;
  2982. }
  2983. case WIFIRX_PPDU_ACK_REPORT_E:
  2984. {
  2985. SHOW_DEFINED(WIFIRX_PPDU_ACK_REPORT_E);
  2986. break;
  2987. }
  2988. case WIFIRX_PPDU_NO_ACK_REPORT_E:
  2989. {
  2990. SHOW_DEFINED(WIFIRX_PPDU_NO_ACK_REPORT_E);
  2991. break;
  2992. }
  2993. case WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E:
  2994. {
  2995. SHOW_DEFINED(WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E);
  2996. break;
  2997. }
  2998. case WIFITXPCU_PHYTX_DEBUG32_E:
  2999. {
  3000. SHOW_DEFINED(WIFITXPCU_PHYTX_DEBUG32_E);
  3001. break;
  3002. }
  3003. case WIFITXPCU_PREAMBLE_DONE_E:
  3004. {
  3005. SHOW_DEFINED(WIFITXPCU_PREAMBLE_DONE_E);
  3006. break;
  3007. }
  3008. case WIFIRX_PHY_SLEEP_E:
  3009. {
  3010. SHOW_DEFINED(WIFIRX_PHY_SLEEP_E);
  3011. break;
  3012. }
  3013. case WIFIRX_FRAME_BITMAP_REQ_E:
  3014. {
  3015. SHOW_DEFINED(WIFIRX_FRAME_BITMAP_REQ_E);
  3016. break;
  3017. }
  3018. case WIFIRXPCU_TX_SETUP_CLEAR_E:
  3019. {
  3020. SHOW_DEFINED(WIFIRXPCU_TX_SETUP_CLEAR_E);
  3021. break;
  3022. }
  3023. case WIFIRX_TRIG_INFO_E:
  3024. {
  3025. SHOW_DEFINED(WIFIRX_TRIG_INFO_E);
  3026. break;
  3027. }
  3028. case WIFIEXPECTED_RESPONSE_E:
  3029. {
  3030. SHOW_DEFINED(WIFIEXPECTED_RESPONSE_E);
  3031. break;
  3032. }
  3033. case WIFITRIGGER_RESPONSE_TX_DONE_E:
  3034. {
  3035. SHOW_DEFINED(WIFITRIGGER_RESPONSE_TX_DONE_E);
  3036. break;
  3037. }
  3038. case WIFIFW2SW_MON_E:
  3039. {
  3040. /* parse fw2sw tlv */
  3041. hal_txmon_parse_fw2sw(tx_tlv, tlv_user_id, data_status_info);
  3042. status = HAL_MON_TX_FW2SW;
  3043. SHOW_DEFINED(WIFIFW2SW_MON_E);
  3044. break;
  3045. }
  3046. }
  3047. return status;
  3048. }
  3049. #endif /* QCA_MONITOR_2_0_SUPPORT */
  3050. #ifdef REO_SHARED_QREF_TABLE_EN
  3051. static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl)
  3052. {
  3053. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3054. uint32_t reg_val = 0;
  3055. /* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers
  3056. * of 37 peer/tids
  3057. */
  3058. reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE));
  3059. reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1);
  3060. HAL_REG_WRITE(hal,
  3061. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  3062. reg_val);
  3063. /* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers
  3064. * of 37 peer/tids
  3065. */
  3066. reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1));
  3067. HAL_REG_WRITE(hal,
  3068. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  3069. reg_val);
  3070. hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of"
  3071. "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back"
  3072. "to erase stale entries in reo storage: regval:%x", hal, reg_val);
  3073. }
  3074. /* hal_reo_shared_qaddr_write(): Write REO tid queue addr
  3075. * LUT shared by SW and HW at the index given by peer id
  3076. * and tid.
  3077. *
  3078. * @hal_soc: hal soc pointer
  3079. * @reo_qref_addr: pointer to index pointed to be peer_id
  3080. * and tid
  3081. * @tid: tid queue number
  3082. * @hw_qdesc_paddr: reo queue addr
  3083. */
  3084. static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl,
  3085. uint16_t peer_id,
  3086. int tid,
  3087. qdf_dma_addr_t hw_qdesc_paddr)
  3088. {
  3089. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3090. struct rx_reo_queue_reference *reo_qref;
  3091. uint32_t peer_tid_idx;
  3092. /* Plug hw_desc_addr in Host reo queue reference table */
  3093. if (HAL_PEER_ID_IS_MLO(peer_id)) {
  3094. peer_tid_idx = ((peer_id - HAL_ML_PEER_ID_START) *
  3095. DP_MAX_TIDS) + tid;
  3096. reo_qref = (struct rx_reo_queue_reference *)
  3097. &hal->reo_qref.mlo_reo_qref_table_vaddr[peer_tid_idx];
  3098. } else {
  3099. peer_tid_idx = (peer_id * DP_MAX_TIDS) + tid;
  3100. reo_qref = (struct rx_reo_queue_reference *)
  3101. &hal->reo_qref.non_mlo_reo_qref_table_vaddr[peer_tid_idx];
  3102. }
  3103. reo_qref->rx_reo_queue_desc_addr_31_0 =
  3104. hw_qdesc_paddr & 0xffffffff;
  3105. reo_qref->rx_reo_queue_desc_addr_39_32 =
  3106. (hw_qdesc_paddr & 0xff00000000) >> 32;
  3107. if (hw_qdesc_paddr != 0)
  3108. reo_qref->receive_queue_number = tid;
  3109. else
  3110. reo_qref->receive_queue_number = 0;
  3111. hal_reo_shared_qaddr_cache_clear_be(hal_soc_hdl);
  3112. hal_verbose_debug("hw_qdesc_paddr: %pK, tid: %d, reo_qref:%pK,"
  3113. "rx_reo_queue_desc_addr_31_0: %x,"
  3114. "rx_reo_queue_desc_addr_39_32: %x",
  3115. (void *)hw_qdesc_paddr, tid, reo_qref,
  3116. reo_qref->rx_reo_queue_desc_addr_31_0,
  3117. reo_qref->rx_reo_queue_desc_addr_39_32);
  3118. }
  3119. /**
  3120. * hal_reo_shared_qaddr_setup_be() - Allocate MLO and Non MLO reo queue
  3121. * reference table shared between SW and HW and initialize in Qdesc Base0
  3122. * base1 registers provided by HW.
  3123. *
  3124. * @hal_soc_hdl: HAL Soc handle
  3125. * @reo_qref: REO queue reference table
  3126. *
  3127. * Return: QDF_STATUS_SUCCESS on success else a QDF error.
  3128. */
  3129. static QDF_STATUS
  3130. hal_reo_shared_qaddr_setup_be(hal_soc_handle_t hal_soc_hdl,
  3131. struct reo_queue_ref_table *reo_qref)
  3132. {
  3133. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3134. reo_qref->reo_qref_table_en = 1;
  3135. reo_qref->mlo_reo_qref_table_vaddr =
  3136. (uint64_t *)qdf_mem_alloc_consistent(
  3137. hal->qdf_dev, hal->qdf_dev->dev,
  3138. REO_QUEUE_REF_ML_TABLE_SIZE,
  3139. &reo_qref->mlo_reo_qref_table_paddr);
  3140. if (!reo_qref->mlo_reo_qref_table_vaddr)
  3141. return QDF_STATUS_E_NOMEM;
  3142. reo_qref->non_mlo_reo_qref_table_vaddr =
  3143. (uint64_t *)qdf_mem_alloc_consistent(
  3144. hal->qdf_dev, hal->qdf_dev->dev,
  3145. REO_QUEUE_REF_NON_ML_TABLE_SIZE,
  3146. &reo_qref->non_mlo_reo_qref_table_paddr);
  3147. if (!reo_qref->non_mlo_reo_qref_table_vaddr) {
  3148. qdf_mem_free_consistent(
  3149. hal->qdf_dev, hal->qdf_dev->dev,
  3150. REO_QUEUE_REF_ML_TABLE_SIZE,
  3151. reo_qref->mlo_reo_qref_table_vaddr,
  3152. reo_qref->mlo_reo_qref_table_paddr,
  3153. 0);
  3154. reo_qref->mlo_reo_qref_table_vaddr = NULL;
  3155. return QDF_STATUS_E_NOMEM;
  3156. }
  3157. hal_verbose_debug("MLO table start paddr:%pK,"
  3158. "Non-MLO table start paddr:%pK,"
  3159. "MLO table start vaddr: %pK,"
  3160. "Non MLO table start vaddr: %pK",
  3161. (void *)reo_qref->mlo_reo_qref_table_paddr,
  3162. (void *)reo_qref->non_mlo_reo_qref_table_paddr,
  3163. reo_qref->mlo_reo_qref_table_vaddr,
  3164. reo_qref->non_mlo_reo_qref_table_vaddr);
  3165. return QDF_STATUS_SUCCESS;
  3166. }
  3167. /**
  3168. * hal_reo_shared_qaddr_init_be() - Zero out REO qref LUT and
  3169. * write start addr of MLO and Non MLO table in HW
  3170. *
  3171. * @hal_soc_hdl: HAL Soc handle
  3172. * @qref_reset: reset qref LUT
  3173. *
  3174. * Return: None
  3175. */
  3176. static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl,
  3177. int qref_reset)
  3178. {
  3179. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3180. if (qref_reset) {
  3181. qdf_mem_zero(hal->reo_qref.mlo_reo_qref_table_vaddr,
  3182. REO_QUEUE_REF_ML_TABLE_SIZE);
  3183. qdf_mem_zero(hal->reo_qref.non_mlo_reo_qref_table_vaddr,
  3184. REO_QUEUE_REF_NON_ML_TABLE_SIZE);
  3185. }
  3186. /* LUT_BASE0 and BASE1 registers expect upper 32bits of LUT base address
  3187. * and lower 8 bits to be 0. Shift the physical address by 8 to plug
  3188. * upper 32bits only
  3189. */
  3190. HAL_REG_WRITE(hal,
  3191. HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE),
  3192. hal->reo_qref.non_mlo_reo_qref_table_paddr >> 8);
  3193. HAL_REG_WRITE(hal,
  3194. HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
  3195. hal->reo_qref.mlo_reo_qref_table_paddr >> 8);
  3196. HAL_REG_WRITE(hal,
  3197. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  3198. HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE,
  3199. 1));
  3200. HAL_REG_WRITE(hal,
  3201. HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(REO_REG_REG_BASE),
  3202. HAL_MS(HWIO_REO_R0_QDESC, MAX_SW_PEER_ID_MAX_SUPPORTED,
  3203. 0x1fff));
  3204. }
  3205. /**
  3206. * hal_reo_shared_qaddr_detach_be() - Free MLO and Non MLO reo queue
  3207. * reference table shared between SW and HW
  3208. *
  3209. * @hal_soc_hdl: HAL Soc handle
  3210. *
  3211. * Return: None
  3212. */
  3213. static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl)
  3214. {
  3215. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3216. HAL_REG_WRITE(hal,
  3217. HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE),
  3218. 0);
  3219. HAL_REG_WRITE(hal,
  3220. HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
  3221. 0);
  3222. }
  3223. #endif
  3224. /**
  3225. * hal_tx_vdev_mismatch_routing_set_generic_be() - set vdev mismatch exception routing
  3226. * @hal_soc_hdl: HAL SoC context
  3227. * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM
  3228. * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW
  3229. *
  3230. * Return: void
  3231. */
  3232. #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK
  3233. static inline void
  3234. hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
  3235. enum hal_tx_vdev_mismatch_notify
  3236. config)
  3237. {
  3238. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3239. uint32_t reg_addr, reg_val = 0;
  3240. uint32_t val = 0;
  3241. reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
  3242. val = HAL_REG_READ(hal_soc, reg_addr);
  3243. /* reset the corresponding bits in register */
  3244. val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK));
  3245. /* set config value */
  3246. reg_val = val | (config <<
  3247. HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT);
  3248. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3249. }
  3250. #else
  3251. static inline void
  3252. hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
  3253. enum hal_tx_vdev_mismatch_notify
  3254. config)
  3255. {
  3256. }
  3257. #endif
  3258. /**
  3259. * hal_tx_mcast_mlo_reinject_routing_set_generic_be() - set MLO multicast reinject routing
  3260. * @hal_soc_hdl: HAL SoC context
  3261. * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW
  3262. * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM
  3263. *
  3264. * Return: void
  3265. */
  3266. #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \
  3267. defined(WLAN_MCAST_MLO)
  3268. static inline void
  3269. hal_tx_mcast_mlo_reinject_routing_set_generic_be(
  3270. hal_soc_handle_t hal_soc_hdl,
  3271. enum hal_tx_mcast_mlo_reinject_notify config)
  3272. {
  3273. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3274. uint32_t reg_addr, reg_val = 0;
  3275. uint32_t val = 0;
  3276. reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
  3277. val = HAL_REG_READ(hal_soc, reg_addr);
  3278. /* reset the corresponding bits in register */
  3279. val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK));
  3280. /* set config value */
  3281. reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT);
  3282. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3283. }
  3284. #else
  3285. static inline void
  3286. hal_tx_mcast_mlo_reinject_routing_set_generic_be(
  3287. hal_soc_handle_t hal_soc_hdl,
  3288. enum hal_tx_mcast_mlo_reinject_notify config)
  3289. {
  3290. }
  3291. #endif
  3292. /**
  3293. * hal_get_ba_aging_timeout_be_generic() - Get BA Aging timeout
  3294. *
  3295. * @hal_soc_hdl: Opaque HAL SOC handle
  3296. * @ac: Access category
  3297. * @value: window size to get
  3298. */
  3299. static inline
  3300. void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
  3301. uint8_t ac, uint32_t *value)
  3302. {
  3303. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3304. switch (ac) {
  3305. case WME_AC_BE:
  3306. *value = HAL_REG_READ(soc,
  3307. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  3308. REO_REG_REG_BASE)) / 1000;
  3309. break;
  3310. case WME_AC_BK:
  3311. *value = HAL_REG_READ(soc,
  3312. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  3313. REO_REG_REG_BASE)) / 1000;
  3314. break;
  3315. case WME_AC_VI:
  3316. *value = HAL_REG_READ(soc,
  3317. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  3318. REO_REG_REG_BASE)) / 1000;
  3319. break;
  3320. case WME_AC_VO:
  3321. *value = HAL_REG_READ(soc,
  3322. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  3323. REO_REG_REG_BASE)) / 1000;
  3324. break;
  3325. default:
  3326. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3327. "Invalid AC: %d\n", ac);
  3328. }
  3329. }
  3330. /**
  3331. * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the
  3332. * buffer list provided
  3333. *
  3334. * @soc: Opaque HAL SOC handle
  3335. * @scatter_bufs_base_paddr: Array of physical base addresses
  3336. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  3337. * @num_scatter_bufs: Number of scatter buffers in the above lists
  3338. * @scatter_buf_size: Size of each scatter buffer
  3339. * @last_buf_end_offset: Offset to the last entry
  3340. * @num_entries: Total entries of all scatter bufs
  3341. *
  3342. * Return: None
  3343. */
  3344. static inline void
  3345. hal_setup_link_idle_list_generic_be(struct hal_soc *soc,
  3346. qdf_dma_addr_t scatter_bufs_base_paddr[],
  3347. void *scatter_bufs_base_vaddr[],
  3348. uint32_t num_scatter_bufs,
  3349. uint32_t scatter_buf_size,
  3350. uint32_t last_buf_end_offset,
  3351. uint32_t num_entries)
  3352. {
  3353. int i;
  3354. uint32_t *prev_buf_link_ptr = NULL;
  3355. uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size;
  3356. uint32_t val;
  3357. /* Link the scatter buffers */
  3358. for (i = 0; i < num_scatter_bufs; i++) {
  3359. if (i > 0) {
  3360. prev_buf_link_ptr[0] =
  3361. scatter_bufs_base_paddr[i] & 0xffffffff;
  3362. prev_buf_link_ptr[1] = HAL_SM(
  3363. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3364. BASE_ADDRESS_39_32,
  3365. ((uint64_t)(scatter_bufs_base_paddr[i])
  3366. >> 32)) | HAL_SM(
  3367. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3368. ADDRESS_MATCH_TAG,
  3369. ADDRESS_MATCH_TAG_VAL);
  3370. }
  3371. prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
  3372. scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
  3373. }
  3374. /* TBD: Register programming partly based on MLD & the rest based on
  3375. * inputs from HW team. Not complete yet.
  3376. */
  3377. reg_scatter_buf_size = (scatter_buf_size -
  3378. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64;
  3379. reg_tot_scatter_buf_size = ((scatter_buf_size -
  3380. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64;
  3381. HAL_REG_WRITE(soc,
  3382. HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(
  3383. WBM_REG_REG_BASE),
  3384. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE,
  3385. reg_scatter_buf_size) |
  3386. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE,
  3387. 0x1));
  3388. HAL_REG_WRITE(soc,
  3389. HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(
  3390. WBM_REG_REG_BASE),
  3391. HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE,
  3392. SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
  3393. reg_tot_scatter_buf_size));
  3394. HAL_REG_WRITE(soc,
  3395. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(
  3396. WBM_REG_REG_BASE),
  3397. scatter_bufs_base_paddr[0] & 0xffffffff);
  3398. HAL_REG_WRITE(soc,
  3399. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  3400. WBM_REG_REG_BASE),
  3401. ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
  3402. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
  3403. HAL_REG_WRITE(soc,
  3404. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  3405. WBM_REG_REG_BASE),
  3406. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3407. BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0])
  3408. >> 32)) |
  3409. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  3410. ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL));
  3411. /* ADDRESS_MATCH_TAG field in the above register is expected to match
  3412. * with the upper bits of link pointer. The above write sets this field
  3413. * to zero and we are also setting the upper bits of link pointers to
  3414. * zero while setting up the link list of scatter buffers above
  3415. */
  3416. /* Setup head and tail pointers for the idle list */
  3417. HAL_REG_WRITE(soc,
  3418. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  3419. WBM_REG_REG_BASE),
  3420. scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff);
  3421. HAL_REG_WRITE(soc,
  3422. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(
  3423. WBM_REG_REG_BASE),
  3424. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  3425. BUFFER_ADDRESS_39_32,
  3426. ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1])
  3427. >> 32)) |
  3428. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  3429. HEAD_POINTER_OFFSET, last_buf_end_offset >> 2));
  3430. HAL_REG_WRITE(soc,
  3431. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  3432. WBM_REG_REG_BASE),
  3433. scatter_bufs_base_paddr[0] & 0xffffffff);
  3434. HAL_REG_WRITE(soc,
  3435. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(
  3436. WBM_REG_REG_BASE),
  3437. scatter_bufs_base_paddr[0] & 0xffffffff);
  3438. HAL_REG_WRITE(soc,
  3439. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(
  3440. WBM_REG_REG_BASE),
  3441. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  3442. BUFFER_ADDRESS_39_32,
  3443. ((uint64_t)(scatter_bufs_base_paddr[0]) >>
  3444. 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  3445. TAIL_POINTER_OFFSET, 0));
  3446. HAL_REG_WRITE(soc,
  3447. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(
  3448. WBM_REG_REG_BASE),
  3449. 2 * num_entries);
  3450. /* Set RING_ID_DISABLE */
  3451. val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1);
  3452. /*
  3453. * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence
  3454. * check the presence of the bit before toggling it.
  3455. */
  3456. #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK
  3457. val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1);
  3458. #endif
  3459. HAL_REG_WRITE(soc,
  3460. HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE),
  3461. val);
  3462. }
  3463. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  3464. #define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000
  3465. #endif
  3466. /**
  3467. * hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register
  3468. * for REO/WBM
  3469. * @hal_soc_hdl: HAL soc handle
  3470. * @cc_cfg: structure pointer for HW cookie conversion configuration
  3471. *
  3472. * Return: None
  3473. */
  3474. static inline
  3475. void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl,
  3476. struct hal_hw_cc_config *cc_cfg)
  3477. {
  3478. uint32_t reg_addr, reg_val = 0;
  3479. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3480. /* REO CFG */
  3481. reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE);
  3482. reg_val = cc_cfg->lut_base_addr_31_0;
  3483. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3484. reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE);
  3485. reg_val = 0;
  3486. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3487. SW_COOKIE_CONVERT_GLOBAL_ENABLE,
  3488. cc_cfg->cc_global_en);
  3489. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3490. SW_COOKIE_CONVERT_ENABLE,
  3491. cc_cfg->cc_global_en);
  3492. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3493. PAGE_ALIGNMENT,
  3494. cc_cfg->page_4k_align);
  3495. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3496. COOKIE_OFFSET_MSB,
  3497. cc_cfg->cookie_offset_msb);
  3498. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3499. COOKIE_PAGE_MSB,
  3500. cc_cfg->cookie_page_msb);
  3501. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  3502. CMEM_LUT_BASE_ADDR_39_32,
  3503. cc_cfg->lut_base_addr_39_32);
  3504. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3505. /* WBM CFG */
  3506. reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE);
  3507. reg_val = cc_cfg->lut_base_addr_31_0;
  3508. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3509. reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE);
  3510. reg_val = 0;
  3511. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3512. PAGE_ALIGNMENT,
  3513. cc_cfg->page_4k_align);
  3514. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3515. COOKIE_OFFSET_MSB,
  3516. cc_cfg->cookie_offset_msb);
  3517. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3518. COOKIE_PAGE_MSB,
  3519. cc_cfg->cookie_page_msb);
  3520. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  3521. CMEM_LUT_BASE_ADDR_39_32,
  3522. cc_cfg->lut_base_addr_39_32);
  3523. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3524. /*
  3525. * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE,
  3526. */
  3527. reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE);
  3528. reg_val = 0;
  3529. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3530. WBM_COOKIE_CONV_GLOBAL_ENABLE,
  3531. cc_cfg->cc_global_en);
  3532. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3533. WBM2SW6_COOKIE_CONVERSION_EN,
  3534. cc_cfg->wbm2sw6_cc_en);
  3535. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3536. WBM2SW5_COOKIE_CONVERSION_EN,
  3537. cc_cfg->wbm2sw5_cc_en);
  3538. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3539. WBM2SW4_COOKIE_CONVERSION_EN,
  3540. cc_cfg->wbm2sw4_cc_en);
  3541. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3542. WBM2SW3_COOKIE_CONVERSION_EN,
  3543. cc_cfg->wbm2sw3_cc_en);
  3544. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3545. WBM2SW2_COOKIE_CONVERSION_EN,
  3546. cc_cfg->wbm2sw2_cc_en);
  3547. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3548. WBM2SW1_COOKIE_CONVERSION_EN,
  3549. cc_cfg->wbm2sw1_cc_en);
  3550. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3551. WBM2SW0_COOKIE_CONVERSION_EN,
  3552. cc_cfg->wbm2sw0_cc_en);
  3553. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  3554. WBM2FW_COOKIE_CONVERSION_EN,
  3555. cc_cfg->wbm2fw_cc_en);
  3556. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3557. #ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK
  3558. reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE);
  3559. reg_val = 0;
  3560. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3561. COOKIE_DEBUG_SEL,
  3562. cc_cfg->cc_global_en);
  3563. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3564. COOKIE_CONV_INDICATION_EN,
  3565. cc_cfg->cc_global_en);
  3566. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3567. ERROR_PATH_COOKIE_CONV_EN,
  3568. cc_cfg->error_path_cookie_conv_en);
  3569. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  3570. RELEASE_PATH_COOKIE_CONV_EN,
  3571. cc_cfg->release_path_cookie_conv_en);
  3572. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3573. #endif
  3574. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  3575. /*
  3576. * To enable indication for HW cookie conversion done or not for
  3577. * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th
  3578. * bit spare_control[15] should be set.
  3579. */
  3580. reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE);
  3581. reg_val = HAL_REG_READ(soc, reg_addr);
  3582. reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL,
  3583. SPARE_CONTROL,
  3584. HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15);
  3585. HAL_REG_WRITE(soc, reg_addr, reg_val);
  3586. #endif
  3587. }
  3588. /**
  3589. * hal_set_ba_aging_timeout_be_generic() - Set BA Aging timeout
  3590. * @hal_soc_hdl: Opaque HAL SOC handle
  3591. * @ac: Access category
  3592. * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice
  3593. * @value: Input value to set
  3594. */
  3595. static inline
  3596. void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
  3597. uint8_t ac, uint32_t value)
  3598. {
  3599. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  3600. switch (ac) {
  3601. case WME_AC_BE:
  3602. HAL_REG_WRITE(soc,
  3603. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  3604. REO_REG_REG_BASE),
  3605. value * 1000);
  3606. break;
  3607. case WME_AC_BK:
  3608. HAL_REG_WRITE(soc,
  3609. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  3610. REO_REG_REG_BASE),
  3611. value * 1000);
  3612. break;
  3613. case WME_AC_VI:
  3614. HAL_REG_WRITE(soc,
  3615. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  3616. REO_REG_REG_BASE),
  3617. value * 1000);
  3618. break;
  3619. case WME_AC_VO:
  3620. HAL_REG_WRITE(soc,
  3621. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  3622. REO_REG_REG_BASE),
  3623. value * 1000);
  3624. break;
  3625. default:
  3626. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3627. "Invalid AC: %d\n", ac);
  3628. }
  3629. }
  3630. /**
  3631. * hal_tx_populate_bank_register_be() - populate the bank register with
  3632. * the software configs.
  3633. * @hal_soc_hdl: HAL soc handle
  3634. * @config: bank config
  3635. * @bank_id: bank id to be configured
  3636. *
  3637. * Returns: None
  3638. */
  3639. #ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT
  3640. static inline void
  3641. hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
  3642. union hal_tx_bank_config *config,
  3643. uint8_t bank_id)
  3644. {
  3645. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3646. uint32_t reg_addr, reg_val = 0;
  3647. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  3648. bank_id);
  3649. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  3650. reg_val |= (config->encap_type <<
  3651. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  3652. reg_val |= (config->encrypt_type <<
  3653. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  3654. reg_val |= (config->src_buffer_swap <<
  3655. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  3656. reg_val |= (config->link_meta_swap <<
  3657. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  3658. reg_val |= (config->index_lookup_enable <<
  3659. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  3660. reg_val |= (config->addrx_en <<
  3661. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  3662. reg_val |= (config->addry_en <<
  3663. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  3664. reg_val |= (config->mesh_enable <<
  3665. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  3666. reg_val |= (config->vdev_id_check_en <<
  3667. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  3668. reg_val |= (config->pmac_id <<
  3669. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  3670. reg_val |= (config->mcast_pkt_ctrl <<
  3671. HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT);
  3672. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3673. }
  3674. #else
  3675. static inline void
  3676. hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
  3677. union hal_tx_bank_config *config,
  3678. uint8_t bank_id)
  3679. {
  3680. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3681. uint32_t reg_addr, reg_val = 0;
  3682. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  3683. bank_id);
  3684. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  3685. reg_val |= (config->encap_type <<
  3686. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  3687. reg_val |= (config->encrypt_type <<
  3688. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  3689. reg_val |= (config->src_buffer_swap <<
  3690. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  3691. reg_val |= (config->link_meta_swap <<
  3692. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  3693. reg_val |= (config->index_lookup_enable <<
  3694. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  3695. reg_val |= (config->addrx_en <<
  3696. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  3697. reg_val |= (config->addry_en <<
  3698. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  3699. reg_val |= (config->mesh_enable <<
  3700. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  3701. reg_val |= (config->vdev_id_check_en <<
  3702. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  3703. reg_val |= (config->pmac_id <<
  3704. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  3705. reg_val |= (config->dscp_tid_map_id <<
  3706. HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT);
  3707. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3708. }
  3709. #endif
  3710. #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT
  3711. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4)
  3712. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF)
  3713. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3
  3714. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2
  3715. /**
  3716. * hal_tx_vdev_mcast_ctrl_set_be() - set mcast_ctrl value
  3717. * @hal_soc_hdl: HAL SoC context
  3718. * @vdev_id: vdev identifier
  3719. * @mcast_ctrl_val: mcast ctrl value for this VAP
  3720. *
  3721. * Return: void
  3722. */
  3723. static inline void
  3724. hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
  3725. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  3726. {
  3727. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3728. uint32_t reg_addr, reg_val = 0;
  3729. uint32_t val;
  3730. uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id);
  3731. uint8_t index_in_reg =
  3732. HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id);
  3733. reg_addr =
  3734. HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE,
  3735. reg_idx);
  3736. val = HAL_REG_READ(hal_soc, reg_addr);
  3737. /* mask out other stored value */
  3738. val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK <<
  3739. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)));
  3740. reg_val = val |
  3741. ((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) <<
  3742. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg));
  3743. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  3744. }
  3745. #else
  3746. static inline void
  3747. hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
  3748. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  3749. {
  3750. }
  3751. #endif
  3752. #endif /* _HAL_BE_GENERIC_API_H_ */