wsa884x.c 63 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/init.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/printk.h>
  11. #include <linux/bitops.h>
  12. #include <linux/regulator/consumer.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/delay.h>
  15. #include <linux/kernel.h>
  16. #include <linux/gpio.h>
  17. #include <linux/of_gpio.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/regmap.h>
  20. #include <linux/debugfs.h>
  21. #include <soc/soundwire.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/tlv.h>
  27. #include <asoc/msm-cdc-pinctrl.h>
  28. #include <asoc/msm-cdc-supply.h>
  29. #include "wsa884x.h"
  30. #include "internal.h"
  31. #include "asoc/bolero-slave-internal.h"
  32. #include <linux/qti-regmap-debugfs.h>
  33. #define T1_TEMP -10
  34. #define T2_TEMP 150
  35. #define LOW_TEMP_THRESHOLD 5
  36. #define HIGH_TEMP_THRESHOLD 45
  37. #define TEMP_INVALID 0xFFFF
  38. #define WSA884X_TEMP_RETRY 3
  39. #define MAX_NAME_LEN 40
  40. #define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  41. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  42. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  43. SNDRV_PCM_RATE_384000)
  44. /* Fractional Rates */
  45. #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  46. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  47. #define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  48. SNDRV_PCM_FMTBIT_S24_LE |\
  49. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  50. #define REG_FIELD_VALUE(register_name, field_name, value) \
  51. WSA884X_##register_name, FIELD_MASK(register_name, field_name), \
  52. value << FIELD_SHIFT(register_name, field_name)
  53. struct wsa_temp_register {
  54. u8 d1_msb;
  55. u8 d1_lsb;
  56. u8 d2_msb;
  57. u8 d2_lsb;
  58. u8 dmeas_msb;
  59. u8 dmeas_lsb;
  60. };
  61. enum {
  62. COMP_OFFSET0,
  63. COMP_OFFSET1,
  64. COMP_OFFSET2,
  65. COMP_OFFSET3,
  66. COMP_OFFSET4,
  67. };
  68. enum {
  69. EXT_ABOVE_3S,
  70. CONFIG_1S,
  71. CONFIG_2S,
  72. CONFIG_3S,
  73. EXT_1S,
  74. EXT_2S,
  75. EXT_3S,
  76. };
  77. enum {
  78. WSA_4OHMS = 0,
  79. WSA_6OHMS,
  80. WSA_8OHMS,
  81. WSA_32OHMS,
  82. WSA_MAXOHMS,
  83. };
  84. /* Aux gain from system gain */
  85. static const u8 pa_aux_no_comp[G_MAX_DB] = {
  86. PA_AUX_18_DB, /* G_21_DB */
  87. PA_AUX_18_DB, /* G_19P5_DB */
  88. PA_AUX_18_DB, /* G_18_DB */
  89. PA_AUX_18_DB, /* G_16P5_DB */
  90. PA_AUX_18_DB, /* G_15_DB */
  91. PA_AUX_12_DB, /* G_13P5_DB */
  92. PA_AUX_12_DB, /* G_12_DB */
  93. PA_AUX_12_DB, /* G_10P5_DB */
  94. PA_AUX_7P5_DB, /* G_9_DB */
  95. PA_AUX_7P5_DB, /* G_7P5_DB */
  96. PA_AUX_7P5_DB, /* G_6_DB */
  97. PA_AUX_7P5_DB, /* G_4P5_DB */
  98. PA_AUX_0_DB, /* G_3_DB */
  99. PA_AUX_0_DB, /* G_1P5_DB */
  100. PA_AUX_0_DB, /* G_0_DB */
  101. PA_AUX_M1P5_DB,/* G_M1P5_DB */
  102. PA_AUX_M3_DB, /* G_M3_DB */
  103. PA_AUX_M4P5_DB,/* G_M4P5_DB */
  104. PA_AUX_M6_DB /* G_M6_DB */
  105. };
  106. /*
  107. * Isense data indexed by system_gain and rload
  108. * WSA_4OHMS, WSA_6OHMS, WSA_8OHMS, WSA_32OHMS
  109. */
  110. static const u8 isense_gain_data[G_MAX_DB][WSA_MAXOHMS] = {
  111. {ISENSE_18_DB, ISENSE_6_DB, ISENSE_12_DB, ISENSE_18_DB}, /*G_21_DB */
  112. {ISENSE_18_DB, ISENSE_6_DB, ISENSE_12_DB, ISENSE_18_DB}, /*G_19P5_DB */
  113. {ISENSE_18_DB, ISENSE_6_DB, ISENSE_15_DB, ISENSE_18_DB}, /*G_18_DB */
  114. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_15_DB, ISENSE_18_DB}, /*G_16P5_DB */
  115. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_15_DB */
  116. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_13P5_DB */
  117. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_12_DB */
  118. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_10P5_DB */
  119. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_9_DB */
  120. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_7P5_DB */
  121. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_6_DB */
  122. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_4P5_DB */
  123. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_3_DB */
  124. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_1P5_DB */
  125. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_0_DB */
  126. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_M1P5_DB */
  127. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_M3_DB */
  128. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_M4P5_DB */
  129. {ISENSE_18_DB, ISENSE_12_DB, ISENSE_18_DB, ISENSE_18_DB}, /*G_M6_DB */
  130. };
  131. /* Vsense gain from system gain */
  132. static const u8 vsense_gain_data[G_MAX_DB] = {
  133. VSENSE_M24_DB, /* G_21_DB */
  134. VSENSE_M24_DB, /* G_19P5_DB */
  135. VSENSE_M21_DB, /* G_18_DB */
  136. VSENSE_M18_DB, /* G_16P5_DB */
  137. VSENSE_M18_DB, /* G_15_DB */
  138. VSENSE_M15_DB, /* G_13P5_DB */
  139. VSENSE_M15_DB, /* G_12_DB */
  140. VSENSE_M12_DB, /* G_10P5_DB */
  141. VSENSE_M12_DB, /* G_9_DB */
  142. VSENSE_M12_DB, /* G_7P5_DB */
  143. VSENSE_M12_DB, /* G_6_DB */
  144. VSENSE_M12_DB, /* G_4P5_DB */
  145. VSENSE_M12_DB, /* G_3_DB */
  146. VSENSE_M12_DB, /* G_1P5_DB */
  147. VSENSE_M12_DB, /* G_0_DB */
  148. VSENSE_M12_DB, /* G_M1P5_DB */
  149. VSENSE_M12_DB, /* G_M3_DB */
  150. VSENSE_M12_DB, /* G_M4P5_DB */
  151. VSENSE_M12_DB /* G_M6_DB */
  152. };
  153. struct wsa_reg_mask_val {
  154. u16 reg;
  155. u8 mask;
  156. u8 val;
  157. };
  158. static const struct wsa_reg_mask_val reg_init[] = {
  159. {REG_FIELD_VALUE(CKWD_CTL_1, VPP_SW_CTL, 0x00)},
  160. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)},
  161. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_1, COEF_A2, 0x08)},
  162. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_0, COEF_A3, 0xF3)},
  163. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_1, COEF_A3, 0x07)},
  164. {REG_FIELD_VALUE(CDC_SPK_DSM_A4_0, COEF_A4, 0x79)},
  165. {REG_FIELD_VALUE(CDC_SPK_DSM_A5_0, COEF_A5, 0x0B)},
  166. {REG_FIELD_VALUE(CDC_SPK_DSM_A6_0, COEF_A6, 0x8A)},
  167. {REG_FIELD_VALUE(CDC_SPK_DSM_A7_0, COEF_A7, 0x9B)},
  168. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C3, 0x06)},
  169. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C2, 0x08)},
  170. {REG_FIELD_VALUE(CDC_SPK_DSM_C_2, COEF_C7, 0x0F)},
  171. {REG_FIELD_VALUE(CDC_SPK_DSM_C_3, COEF_C7, 0x20)},
  172. {REG_FIELD_VALUE(CDC_SPK_DSM_R1, SAT_LIMIT_R1, 0x83)},
  173. {REG_FIELD_VALUE(CDC_SPK_DSM_R2, SAT_LIMIT_R2, 0x7F)},
  174. {REG_FIELD_VALUE(CDC_SPK_DSM_R3, SAT_LIMIT_R3, 0x9D)},
  175. {REG_FIELD_VALUE(CDC_SPK_DSM_R4, SAT_LIMIT_R4, 0x82)},
  176. {REG_FIELD_VALUE(CDC_SPK_DSM_R5, SAT_LIMIT_R5, 0x8B)},
  177. {REG_FIELD_VALUE(CDC_SPK_DSM_R6, SAT_LIMIT_R6, 0x9B)},
  178. {REG_FIELD_VALUE(CDC_SPK_DSM_R7, SAT_LIMIT_R7, 0x3F)},
  179. {REG_FIELD_VALUE(BOP_DEGLITCH_CTL, BOP_DEGLITCH_SETTING, 0x08)},
  180. {REG_FIELD_VALUE(CLSH_CTL_0, DLY_CODE, 0x06)},
  181. {REG_FIELD_VALUE(CLSH_SOFT_MAX, SOFT_MAX, 0xFF)},
  182. {REG_FIELD_VALUE(OTP_REG_38, BOOST_ILIM_TUNE, 0x00)},
  183. {REG_FIELD_VALUE(OTP_REG_40, ISENSE_RESCAL, 0x08)},
  184. {REG_FIELD_VALUE(STB_CTRL1, SLOPE_COMP_CURRENT, 0x0D)},
  185. {REG_FIELD_VALUE(ILIM_CTRL1, ILIM_OFFSET_PB, 0x03)},
  186. {REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x13)},
  187. };
  188. static int wsa884x_handle_post_irq(void *data);
  189. static int wsa884x_get_temperature(struct snd_soc_component *component,
  190. int *temp);
  191. enum {
  192. WSA8840 = 0,
  193. WSA8845 = 5,
  194. WSA8845H = 0xC,
  195. };
  196. enum {
  197. SPKR_STATUS = 0,
  198. WSA_SUPPLIES_LPM_MODE,
  199. SPKR_ADIE_LB,
  200. };
  201. enum {
  202. WSA884X_IRQ_INT_SAF2WAR = 0,
  203. WSA884X_IRQ_INT_WAR2SAF,
  204. WSA884X_IRQ_INT_DISABLE,
  205. WSA884X_IRQ_INT_OCP,
  206. WSA884X_IRQ_INT_CLIP,
  207. WSA884X_IRQ_INT_PDM_WD,
  208. WSA884X_IRQ_INT_CLK_WD,
  209. WSA884X_IRQ_INT_INTR_PIN,
  210. WSA884X_IRQ_INT_UVLO,
  211. WSA884X_IRQ_INT_PA_ON_ERR,
  212. WSA884X_NUM_IRQS,
  213. };
  214. static const struct regmap_irq wsa884x_irqs[WSA884X_NUM_IRQS] = {
  215. REGMAP_IRQ_REG(WSA884X_IRQ_INT_SAF2WAR, 0, 0x01),
  216. REGMAP_IRQ_REG(WSA884X_IRQ_INT_WAR2SAF, 0, 0x02),
  217. REGMAP_IRQ_REG(WSA884X_IRQ_INT_DISABLE, 0, 0x04),
  218. REGMAP_IRQ_REG(WSA884X_IRQ_INT_OCP, 0, 0x08),
  219. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLIP, 0, 0x10),
  220. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PDM_WD, 0, 0x20),
  221. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLK_WD, 0, 0x40),
  222. REGMAP_IRQ_REG(WSA884X_IRQ_INT_INTR_PIN, 0, 0x80),
  223. REGMAP_IRQ_REG(WSA884X_IRQ_INT_UVLO, 1, 0x01),
  224. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PA_ON_ERR, 1, 0x02),
  225. };
  226. static struct regmap_irq_chip wsa884x_regmap_irq_chip = {
  227. .name = "wsa884x",
  228. .irqs = wsa884x_irqs,
  229. .num_irqs = ARRAY_SIZE(wsa884x_irqs),
  230. .num_regs = 2,
  231. .status_base = WSA884X_INTR_STATUS0,
  232. .mask_base = WSA884X_INTR_MASK0,
  233. .type_base = WSA884X_INTR_LEVEL0,
  234. .ack_base = WSA884X_INTR_CLEAR0,
  235. .use_ack = 1,
  236. .runtime_pm = false,
  237. .handle_post_irq = wsa884x_handle_post_irq,
  238. .irq_drv_data = NULL,
  239. };
  240. static int wsa884x_handle_post_irq(void *data)
  241. {
  242. struct wsa884x_priv *wsa884x = data;
  243. u32 sts1 = 0, sts2 = 0;
  244. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS0, &sts1);
  245. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS1, &sts2);
  246. wsa884x->swr_slave->slave_irq_pending =
  247. ((sts1 || sts2) ? true : false);
  248. return IRQ_HANDLED;
  249. }
  250. #ifdef CONFIG_DEBUG_FS
  251. static int codec_debug_open(struct inode *inode, struct file *file)
  252. {
  253. file->private_data = inode->i_private;
  254. return 0;
  255. }
  256. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  257. {
  258. char *token;
  259. int base, cnt;
  260. token = strsep(&buf, " ");
  261. for (cnt = 0; cnt < num_of_par; cnt++) {
  262. if (token) {
  263. if ((token[1] == 'x') || (token[1] == 'X'))
  264. base = 16;
  265. else
  266. base = 10;
  267. if (kstrtou32(token, base, &param1[cnt]) != 0)
  268. return -EINVAL;
  269. token = strsep(&buf, " ");
  270. } else {
  271. return -EINVAL;
  272. }
  273. }
  274. return 0;
  275. }
  276. static bool is_swr_slave_reg_readable(int reg)
  277. {
  278. int ret = true;
  279. if (((reg > 0x46) && (reg < 0x4A)) ||
  280. ((reg > 0x4A) && (reg < 0x50)) ||
  281. ((reg > 0x55) && (reg < 0xD0)) ||
  282. ((reg > 0xD0) && (reg < 0xE0)) ||
  283. ((reg > 0xE0) && (reg < 0xF0)) ||
  284. ((reg > 0xF0) && (reg < 0x100)) ||
  285. ((reg > 0x105) && (reg < 0x120)) ||
  286. ((reg > 0x205) && (reg < 0x220)) ||
  287. ((reg > 0x305) && (reg < 0x320)) ||
  288. ((reg > 0x405) && (reg < 0x420)) ||
  289. ((reg > 0x128) && (reg < 0x130)) ||
  290. ((reg > 0x228) && (reg < 0x230)) ||
  291. ((reg > 0x328) && (reg < 0x330)) ||
  292. ((reg > 0x428) && (reg < 0x430)) ||
  293. ((reg > 0x138) && (reg < 0x205)) ||
  294. ((reg > 0x238) && (reg < 0x305)) ||
  295. ((reg > 0x338) && (reg < 0x405)) ||
  296. ((reg > 0x405) && (reg < 0xF00)) ||
  297. ((reg > 0xF05) && (reg < 0xF20)) ||
  298. ((reg > 0xF25) && (reg < 0xF30)) ||
  299. ((reg > 0xF35) && (reg < 0x2000)))
  300. ret = false;
  301. return ret;
  302. }
  303. static ssize_t swr_slave_reg_show(struct swr_device *pdev, char __user *ubuf,
  304. size_t count, loff_t *ppos)
  305. {
  306. int i, reg_val, len;
  307. ssize_t total = 0;
  308. char tmp_buf[SWR_SLV_MAX_BUF_LEN];
  309. if (!ubuf || !ppos)
  310. return 0;
  311. for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
  312. i <= SWR_SLV_MAX_REG_ADDR; i++) {
  313. if (!is_swr_slave_reg_readable(i))
  314. continue;
  315. swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
  316. len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
  317. (reg_val & 0xFF));
  318. if (len < 0) {
  319. pr_err("%s: fail to fill the buffer\n", __func__);
  320. total = -EFAULT;
  321. goto copy_err;
  322. }
  323. if ((total + len) >= count - 1)
  324. break;
  325. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  326. pr_err("%s: fail to copy reg dump\n", __func__);
  327. total = -EFAULT;
  328. goto copy_err;
  329. }
  330. total += len;
  331. *ppos += len;
  332. }
  333. copy_err:
  334. *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
  335. return total;
  336. }
  337. static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
  338. size_t count, loff_t *ppos)
  339. {
  340. struct swr_device *pdev;
  341. if (!count || !file || !ppos || !ubuf)
  342. return -EINVAL;
  343. pdev = file->private_data;
  344. if (!pdev)
  345. return -EINVAL;
  346. if (*ppos < 0)
  347. return -EINVAL;
  348. return swr_slave_reg_show(pdev, ubuf, count, ppos);
  349. }
  350. static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
  351. size_t count, loff_t *ppos)
  352. {
  353. char lbuf[SWR_SLV_RD_BUF_LEN];
  354. struct swr_device *pdev = NULL;
  355. struct wsa884x_priv *wsa884x = NULL;
  356. if (!count || !file || !ppos || !ubuf)
  357. return -EINVAL;
  358. pdev = file->private_data;
  359. if (!pdev)
  360. return -EINVAL;
  361. wsa884x = swr_get_dev_data(pdev);
  362. if (!wsa884x)
  363. return -EINVAL;
  364. if (*ppos < 0)
  365. return -EINVAL;
  366. snprintf(lbuf, sizeof(lbuf), "0x%x\n",
  367. (wsa884x->read_data & 0xFF));
  368. return simple_read_from_buffer(ubuf, count, ppos, lbuf,
  369. strnlen(lbuf, 7));
  370. }
  371. static ssize_t codec_debug_peek_write(struct file *file,
  372. const char __user *ubuf, size_t cnt, loff_t *ppos)
  373. {
  374. char lbuf[SWR_SLV_WR_BUF_LEN];
  375. int rc = 0;
  376. u32 param[5];
  377. struct swr_device *pdev = NULL;
  378. struct wsa884x_priv *wsa884x = NULL;
  379. if (!cnt || !file || !ppos || !ubuf)
  380. return -EINVAL;
  381. pdev = file->private_data;
  382. if (!pdev)
  383. return -EINVAL;
  384. wsa884x = swr_get_dev_data(pdev);
  385. if (!wsa884x)
  386. return -EINVAL;
  387. if (*ppos < 0)
  388. return -EINVAL;
  389. if (cnt > sizeof(lbuf) - 1)
  390. return -EINVAL;
  391. rc = copy_from_user(lbuf, ubuf, cnt);
  392. if (rc)
  393. return -EFAULT;
  394. lbuf[cnt] = '\0';
  395. rc = get_parameters(lbuf, param, 1);
  396. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
  397. return -EINVAL;
  398. swr_read(pdev, pdev->dev_num, param[0], &wsa884x->read_data, 1);
  399. if (rc == 0)
  400. rc = cnt;
  401. else
  402. pr_err("%s: rc = %d\n", __func__, rc);
  403. return rc;
  404. }
  405. static ssize_t codec_debug_write(struct file *file,
  406. const char __user *ubuf, size_t cnt, loff_t *ppos)
  407. {
  408. char lbuf[SWR_SLV_WR_BUF_LEN];
  409. int rc = 0;
  410. u32 param[5];
  411. struct swr_device *pdev;
  412. if (!file || !ppos || !ubuf)
  413. return -EINVAL;
  414. pdev = file->private_data;
  415. if (!pdev)
  416. return -EINVAL;
  417. if (cnt > sizeof(lbuf) - 1)
  418. return -EINVAL;
  419. rc = copy_from_user(lbuf, ubuf, cnt);
  420. if (rc)
  421. return -EFAULT;
  422. lbuf[cnt] = '\0';
  423. rc = get_parameters(lbuf, param, 2);
  424. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
  425. (param[1] <= 0xFF) && (rc == 0)))
  426. return -EINVAL;
  427. swr_write(pdev, pdev->dev_num, param[0], &param[1]);
  428. if (rc == 0)
  429. rc = cnt;
  430. else
  431. pr_err("%s: rc = %d\n", __func__, rc);
  432. return rc;
  433. }
  434. static const struct file_operations codec_debug_write_ops = {
  435. .open = codec_debug_open,
  436. .write = codec_debug_write,
  437. };
  438. static const struct file_operations codec_debug_read_ops = {
  439. .open = codec_debug_open,
  440. .read = codec_debug_read,
  441. .write = codec_debug_peek_write,
  442. };
  443. static const struct file_operations codec_debug_dump_ops = {
  444. .open = codec_debug_open,
  445. .read = codec_debug_dump,
  446. };
  447. #endif
  448. static void wsa884x_regcache_sync(struct wsa884x_priv *wsa884x)
  449. {
  450. mutex_lock(&wsa884x->res_lock);
  451. regcache_mark_dirty(wsa884x->regmap);
  452. regcache_sync(wsa884x->regmap);
  453. mutex_unlock(&wsa884x->res_lock);
  454. }
  455. static irqreturn_t wsa884x_saf2war_handle_irq(int irq, void *data)
  456. {
  457. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  458. __func__, irq);
  459. return IRQ_HANDLED;
  460. }
  461. static irqreturn_t wsa884x_war2saf_handle_irq(int irq, void *data)
  462. {
  463. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  464. __func__, irq);
  465. return IRQ_HANDLED;
  466. }
  467. static irqreturn_t wsa884x_otp_handle_irq(int irq, void *data)
  468. {
  469. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  470. __func__, irq);
  471. return IRQ_HANDLED;
  472. }
  473. static irqreturn_t wsa884x_ocp_handle_irq(int irq, void *data)
  474. {
  475. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  476. __func__, irq);
  477. return IRQ_HANDLED;
  478. }
  479. static irqreturn_t wsa884x_clip_handle_irq(int irq, void *data)
  480. {
  481. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  482. __func__, irq);
  483. return IRQ_HANDLED;
  484. }
  485. static irqreturn_t wsa884x_pdm_wd_handle_irq(int irq, void *data)
  486. {
  487. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  488. __func__, irq);
  489. return IRQ_HANDLED;
  490. }
  491. static irqreturn_t wsa884x_clk_wd_handle_irq(int irq, void *data)
  492. {
  493. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  494. __func__, irq);
  495. return IRQ_HANDLED;
  496. }
  497. static irqreturn_t wsa884x_ext_int_handle_irq(int irq, void *data)
  498. {
  499. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  500. __func__, irq);
  501. return IRQ_HANDLED;
  502. }
  503. static irqreturn_t wsa884x_uvlo_handle_irq(int irq, void *data)
  504. {
  505. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  506. __func__, irq);
  507. return IRQ_HANDLED;
  508. }
  509. static irqreturn_t wsa884x_pa_on_err_handle_irq(int irq, void *data)
  510. {
  511. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  512. __func__, irq);
  513. return IRQ_HANDLED;
  514. }
  515. static const char * const wsa_dev_mode_text[] = {
  516. "speaker", "receiver", "ultrasound"
  517. };
  518. enum {
  519. SPEAKER,
  520. RECEIVER,
  521. ULTRASOUND,
  522. };
  523. static const struct soc_enum wsa_dev_mode_enum =
  524. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_dev_mode_text), wsa_dev_mode_text);
  525. static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
  526. struct snd_ctl_elem_value *ucontrol)
  527. {
  528. struct snd_soc_component *component =
  529. snd_soc_kcontrol_component(kcontrol);
  530. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  531. ucontrol->value.integer.value[0] = wsa884x->dev_mode;
  532. dev_dbg(component->dev, "%s: mode = 0x%x\n", __func__,
  533. wsa884x->dev_mode);
  534. return 0;
  535. }
  536. static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
  537. struct snd_ctl_elem_value *ucontrol)
  538. {
  539. struct snd_soc_component *component =
  540. snd_soc_kcontrol_component(kcontrol);
  541. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  542. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  543. __func__, ucontrol->value.integer.value[0]);
  544. wsa884x->dev_mode = ucontrol->value.integer.value[0];
  545. return 0;
  546. }
  547. static const char * const wsa_pa_gain_text[] = {
  548. "G_18_DB", "G_16P5_DB", "G_15_DB", "G_13P5_DB", "G_12_DB", "G_10P5_DB",
  549. "G_9_DB", "G_7P5_DB", "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB",
  550. "G_0_DB"
  551. };
  552. static const struct soc_enum wsa_pa_gain_enum =
  553. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_pa_gain_text), wsa_pa_gain_text);
  554. static int wsa_pa_gain_get(struct snd_kcontrol *kcontrol,
  555. struct snd_ctl_elem_value *ucontrol)
  556. {
  557. struct snd_soc_component *component =
  558. snd_soc_kcontrol_component(kcontrol);
  559. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  560. ucontrol->value.integer.value[0] = wsa884x->pa_gain;
  561. dev_dbg(component->dev, "%s: PA gain = 0x%x\n", __func__,
  562. wsa884x->pa_gain);
  563. return 0;
  564. }
  565. static int wsa_pa_gain_put(struct snd_kcontrol *kcontrol,
  566. struct snd_ctl_elem_value *ucontrol)
  567. {
  568. struct snd_soc_component *component =
  569. snd_soc_kcontrol_component(kcontrol);
  570. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  571. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  572. __func__, ucontrol->value.integer.value[0]);
  573. wsa884x->pa_gain = ucontrol->value.integer.value[0];
  574. return 0;
  575. }
  576. static int wsa884x_get_mute(struct snd_kcontrol *kcontrol,
  577. struct snd_ctl_elem_value *ucontrol)
  578. {
  579. struct snd_soc_component *component =
  580. snd_soc_kcontrol_component(kcontrol);
  581. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  582. ucontrol->value.integer.value[0] = wsa884x->pa_mute;
  583. return 0;
  584. }
  585. static int wsa884x_set_mute(struct snd_kcontrol *kcontrol,
  586. struct snd_ctl_elem_value *ucontrol)
  587. {
  588. struct snd_soc_component *component =
  589. snd_soc_kcontrol_component(kcontrol);
  590. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  591. int value = ucontrol->value.integer.value[0];
  592. dev_dbg(component->dev, "%s: mute current %d, new %d\n",
  593. __func__, wsa884x->pa_mute, value);
  594. wsa884x->pa_mute = value;
  595. return 0;
  596. }
  597. static int wsa_get_temp(struct snd_kcontrol *kcontrol,
  598. struct snd_ctl_elem_value *ucontrol)
  599. {
  600. struct snd_soc_component *component =
  601. snd_soc_kcontrol_component(kcontrol);
  602. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  603. int temp = 0;
  604. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  605. temp = wsa884x->curr_temp;
  606. else
  607. wsa884x_get_temperature(component, &temp);
  608. ucontrol->value.integer.value[0] = temp;
  609. return 0;
  610. }
  611. static ssize_t wsa884x_codec_version_read(struct snd_info_entry *entry,
  612. void *file_private_data, struct file *file,
  613. char __user *buf, size_t count, loff_t pos)
  614. {
  615. struct wsa884x_priv *wsa884x;
  616. char buffer[WSA884X_VERSION_ENTRY_SIZE];
  617. int len = 0;
  618. wsa884x = (struct wsa884x_priv *) entry->private_data;
  619. if (!wsa884x) {
  620. pr_err("%s: wsa884x priv is null\n", __func__);
  621. return -EINVAL;
  622. }
  623. switch (wsa884x->version) {
  624. case WSA884X_VERSION_1_0:
  625. len = snprintf(buffer, sizeof(buffer), "WSA884X_1_0\n");
  626. break;
  627. default:
  628. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  629. break;
  630. }
  631. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  632. }
  633. static struct snd_info_entry_ops wsa884x_codec_info_ops = {
  634. .read = wsa884x_codec_version_read,
  635. };
  636. static ssize_t wsa884x_variant_read(struct snd_info_entry *entry,
  637. void *file_private_data,
  638. struct file *file,
  639. char __user *buf, size_t count,
  640. loff_t pos)
  641. {
  642. struct wsa884x_priv *wsa884x;
  643. char buffer[WSA884X_VARIANT_ENTRY_SIZE];
  644. int len = 0;
  645. wsa884x = (struct wsa884x_priv *) entry->private_data;
  646. if (!wsa884x) {
  647. pr_err("%s: wsa884x priv is null\n", __func__);
  648. return -EINVAL;
  649. }
  650. switch (wsa884x->variant) {
  651. case WSA8840:
  652. len = snprintf(buffer, sizeof(buffer), "WSA8840\n");
  653. break;
  654. case WSA8845:
  655. len = snprintf(buffer, sizeof(buffer), "WSA8845\n");
  656. break;
  657. case WSA8845H:
  658. len = snprintf(buffer, sizeof(buffer), "WSA8845H\n");
  659. break;
  660. default:
  661. len = snprintf(buffer, sizeof(buffer), "UNDEFINED\n");
  662. break;
  663. }
  664. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  665. }
  666. static struct snd_info_entry_ops wsa884x_variant_ops = {
  667. .read = wsa884x_variant_read,
  668. };
  669. /*
  670. * wsa884x_codec_info_create_codec_entry - creates wsa884x module
  671. * @codec_root: The parent directory
  672. * @component: Codec instance
  673. *
  674. * Creates wsa884x module and version entry under the given
  675. * parent directory.
  676. *
  677. * Return: 0 on success or negative error code on failure.
  678. */
  679. int wsa884x_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
  680. struct snd_soc_component *component)
  681. {
  682. struct snd_info_entry *version_entry;
  683. struct snd_info_entry *variant_entry;
  684. struct wsa884x_priv *wsa884x;
  685. struct snd_soc_card *card;
  686. char name[80];
  687. if (!codec_root || !component)
  688. return -EINVAL;
  689. wsa884x = snd_soc_component_get_drvdata(component);
  690. if (wsa884x->entry) {
  691. dev_dbg(wsa884x->dev,
  692. "%s:wsa884x module already created\n", __func__);
  693. return 0;
  694. }
  695. card = component->card;
  696. snprintf(name, sizeof(name), "%s.%llx", "wsa884x",
  697. wsa884x->swr_slave->addr);
  698. wsa884x->entry = snd_info_create_module_entry(codec_root->module,
  699. (const char *)name,
  700. codec_root);
  701. if (!wsa884x->entry) {
  702. dev_dbg(component->dev, "%s: failed to create wsa884x entry\n",
  703. __func__);
  704. return -ENOMEM;
  705. }
  706. wsa884x->entry->mode = S_IFDIR | 0555;
  707. if (snd_info_register(wsa884x->entry) < 0) {
  708. snd_info_free_entry(wsa884x->entry);
  709. return -ENOMEM;
  710. }
  711. version_entry = snd_info_create_card_entry(card->snd_card,
  712. "version",
  713. wsa884x->entry);
  714. if (!version_entry) {
  715. dev_dbg(component->dev, "%s: failed to create wsa884x version entry\n",
  716. __func__);
  717. snd_info_free_entry(wsa884x->entry);
  718. return -ENOMEM;
  719. }
  720. version_entry->private_data = wsa884x;
  721. version_entry->size = WSA884X_VERSION_ENTRY_SIZE;
  722. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  723. version_entry->c.ops = &wsa884x_codec_info_ops;
  724. if (snd_info_register(version_entry) < 0) {
  725. snd_info_free_entry(version_entry);
  726. snd_info_free_entry(wsa884x->entry);
  727. return -ENOMEM;
  728. }
  729. wsa884x->version_entry = version_entry;
  730. variant_entry = snd_info_create_card_entry(card->snd_card,
  731. "variant",
  732. wsa884x->entry);
  733. if (!variant_entry) {
  734. dev_dbg(component->dev,
  735. "%s: failed to create wsa884x variant entry\n",
  736. __func__);
  737. snd_info_free_entry(version_entry);
  738. snd_info_free_entry(wsa884x->entry);
  739. return -ENOMEM;
  740. }
  741. variant_entry->private_data = wsa884x;
  742. variant_entry->size = WSA884X_VARIANT_ENTRY_SIZE;
  743. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  744. variant_entry->c.ops = &wsa884x_variant_ops;
  745. if (snd_info_register(variant_entry) < 0) {
  746. snd_info_free_entry(variant_entry);
  747. snd_info_free_entry(version_entry);
  748. snd_info_free_entry(wsa884x->entry);
  749. return -ENOMEM;
  750. }
  751. wsa884x->variant_entry = variant_entry;
  752. return 0;
  753. }
  754. EXPORT_SYMBOL(wsa884x_codec_info_create_codec_entry);
  755. int wsa884x_set_configuration(struct snd_soc_component *component,
  756. u8 rload, u8 bat_cfg, u8 system_gain)
  757. {
  758. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  759. wsa884x->rload = rload;
  760. wsa884x->bat_cfg = bat_cfg;
  761. wsa884x->system_gain = system_gain;
  762. return 0;
  763. }
  764. EXPORT_SYMBOL(wsa884x_set_configuration);
  765. /*
  766. * wsa884x_codec_get_dev_num - returns swr device number
  767. * @component: Codec instance
  768. *
  769. * Return: swr device number on success or negative error
  770. * code on failure.
  771. */
  772. int wsa884x_codec_get_dev_num(struct snd_soc_component *component)
  773. {
  774. struct wsa884x_priv *wsa884x;
  775. if (!component)
  776. return -EINVAL;
  777. wsa884x = snd_soc_component_get_drvdata(component);
  778. if (!wsa884x) {
  779. pr_err("%s: wsa884x component is NULL\n", __func__);
  780. return -EINVAL;
  781. }
  782. return wsa884x->swr_slave->dev_num;
  783. }
  784. EXPORT_SYMBOL(wsa884x_codec_get_dev_num);
  785. static int wsa884x_get_dev_num(struct snd_kcontrol *kcontrol,
  786. struct snd_ctl_elem_value *ucontrol)
  787. {
  788. struct snd_soc_component *component =
  789. snd_soc_kcontrol_component(kcontrol);
  790. struct wsa884x_priv *wsa884x;
  791. if (!component)
  792. return -EINVAL;
  793. wsa884x = snd_soc_component_get_drvdata(component);
  794. if (!wsa884x) {
  795. pr_err("%s: wsa884x component is NULL\n", __func__);
  796. return -EINVAL;
  797. }
  798. ucontrol->value.integer.value[0] = wsa884x->swr_slave->dev_num;
  799. return 0;
  800. }
  801. static int wsa884x_get_compander(struct snd_kcontrol *kcontrol,
  802. struct snd_ctl_elem_value *ucontrol)
  803. {
  804. struct snd_soc_component *component =
  805. snd_soc_kcontrol_component(kcontrol);
  806. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  807. ucontrol->value.integer.value[0] = wsa884x->comp_enable;
  808. return 0;
  809. }
  810. static int wsa884x_set_compander(struct snd_kcontrol *kcontrol,
  811. struct snd_ctl_elem_value *ucontrol)
  812. {
  813. struct snd_soc_component *component =
  814. snd_soc_kcontrol_component(kcontrol);
  815. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  816. int value = ucontrol->value.integer.value[0];
  817. dev_dbg(component->dev, "%s: Compander enable current %d, new %d\n",
  818. __func__, wsa884x->comp_enable, value);
  819. wsa884x->comp_enable = value;
  820. return 0;
  821. }
  822. static int wsa884x_get_comp_offset(struct snd_kcontrol *kcontrol,
  823. struct snd_ctl_elem_value *ucontrol)
  824. {
  825. struct snd_soc_component *component =
  826. snd_soc_kcontrol_component(kcontrol);
  827. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  828. ucontrol->value.integer.value[0] = wsa884x->comp_offset;
  829. return 0;
  830. }
  831. static int wsa884x_set_comp_offset(struct snd_kcontrol *kcontrol,
  832. struct snd_ctl_elem_value *ucontrol)
  833. {
  834. struct snd_soc_component *component =
  835. snd_soc_kcontrol_component(kcontrol);
  836. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  837. int value = ucontrol->value.integer.value[0];
  838. dev_dbg(component->dev, "%s: comp_offset %d\n",
  839. __func__, wsa884x->comp_offset);
  840. wsa884x->comp_offset = value;
  841. return 0;
  842. }
  843. static int wsa884x_get_visense(struct snd_kcontrol *kcontrol,
  844. struct snd_ctl_elem_value *ucontrol)
  845. {
  846. struct snd_soc_component *component =
  847. snd_soc_kcontrol_component(kcontrol);
  848. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  849. ucontrol->value.integer.value[0] = wsa884x->visense_enable;
  850. return 0;
  851. }
  852. static int wsa884x_set_visense(struct snd_kcontrol *kcontrol,
  853. struct snd_ctl_elem_value *ucontrol)
  854. {
  855. struct snd_soc_component *component =
  856. snd_soc_kcontrol_component(kcontrol);
  857. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  858. int value = ucontrol->value.integer.value[0];
  859. dev_dbg(component->dev, "%s: VIsense enable current %d, new %d\n",
  860. __func__, wsa884x->visense_enable, value);
  861. wsa884x->visense_enable = value;
  862. return 0;
  863. }
  864. static int wsa884x_get_pbr(struct snd_kcontrol *kcontrol,
  865. struct snd_ctl_elem_value *ucontrol)
  866. {
  867. struct snd_soc_component *component =
  868. snd_soc_kcontrol_component(kcontrol);
  869. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  870. ucontrol->value.integer.value[0] = wsa884x->pbr_enable;
  871. return 0;
  872. }
  873. static int wsa884x_set_pbr(struct snd_kcontrol *kcontrol,
  874. struct snd_ctl_elem_value *ucontrol)
  875. {
  876. struct snd_soc_component *component =
  877. snd_soc_kcontrol_component(kcontrol);
  878. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  879. int value = ucontrol->value.integer.value[0];
  880. dev_dbg(component->dev, "%s: PBR enable current %d, new %d\n",
  881. __func__, wsa884x->pbr_enable, value);
  882. wsa884x->pbr_enable = value;
  883. if (value) {
  884. snd_soc_component_update_bits(component,
  885. WSA884X_CLSH_VTH1,
  886. 0xFF, 0xFF);
  887. }
  888. return 0;
  889. }
  890. static int wsa884x_get_cps(struct snd_kcontrol *kcontrol,
  891. struct snd_ctl_elem_value *ucontrol)
  892. {
  893. struct snd_soc_component *component =
  894. snd_soc_kcontrol_component(kcontrol);
  895. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  896. ucontrol->value.integer.value[0] = wsa884x->cps_enable;
  897. return 0;
  898. }
  899. static int wsa884x_set_cps(struct snd_kcontrol *kcontrol,
  900. struct snd_ctl_elem_value *ucontrol)
  901. {
  902. struct snd_soc_component *component =
  903. snd_soc_kcontrol_component(kcontrol);
  904. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  905. int value = ucontrol->value.integer.value[0];
  906. dev_dbg(component->dev, "%s: VIsense enable current %d, new %d\n",
  907. __func__, wsa884x->cps_enable, value);
  908. wsa884x->cps_enable = value;
  909. return 0;
  910. }
  911. static int wsa884x_get_ext_vdd_spk(struct snd_kcontrol *kcontrol,
  912. struct snd_ctl_elem_value *ucontrol)
  913. {
  914. struct snd_soc_component *component =
  915. snd_soc_kcontrol_component(kcontrol);
  916. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  917. ucontrol->value.integer.value[0] = wsa884x->ext_vdd_spk;
  918. return 0;
  919. }
  920. static int wsa884x_put_ext_vdd_spk(struct snd_kcontrol *kcontrol,
  921. struct snd_ctl_elem_value *ucontrol)
  922. {
  923. struct snd_soc_component *component =
  924. snd_soc_kcontrol_component(kcontrol);
  925. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  926. int value = ucontrol->value.integer.value[0];
  927. dev_dbg(component->dev, "%s: Ext VDD SPK enable current %d, new %d\n",
  928. __func__, wsa884x->ext_vdd_spk, value);
  929. wsa884x->ext_vdd_spk = value;
  930. return 0;
  931. }
  932. static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
  933. SOC_ENUM_EXT("WSA PA Gain", wsa_pa_gain_enum,
  934. wsa_pa_gain_get, wsa_pa_gain_put),
  935. SOC_SINGLE_EXT("WSA PA Mute", SND_SOC_NOPM, 0, 1, 0,
  936. wsa884x_get_mute, wsa884x_set_mute),
  937. SOC_SINGLE_EXT("WSA Temp", SND_SOC_NOPM, 0, UINT_MAX, 0,
  938. wsa_get_temp, NULL),
  939. SOC_SINGLE_EXT("WSA Get DevNum", SND_SOC_NOPM, 0, UINT_MAX, 0,
  940. wsa884x_get_dev_num, NULL),
  941. SOC_ENUM_EXT("WSA MODE", wsa_dev_mode_enum,
  942. wsa_dev_mode_get, wsa_dev_mode_put),
  943. SOC_SINGLE_EXT("COMP Offset", SND_SOC_NOPM, 0, 4, 0,
  944. wsa884x_get_comp_offset, wsa884x_set_comp_offset),
  945. SOC_SINGLE_EXT("COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  946. wsa884x_get_compander, wsa884x_set_compander),
  947. SOC_SINGLE_EXT("VISENSE Switch", SND_SOC_NOPM, 0, 1, 0,
  948. wsa884x_get_visense, wsa884x_set_visense),
  949. SOC_SINGLE_EXT("PBR Switch", SND_SOC_NOPM, 0, 1, 0,
  950. wsa884x_get_pbr, wsa884x_set_pbr),
  951. SOC_SINGLE_EXT("CPS Switch", SND_SOC_NOPM, 0, 1, 0,
  952. wsa884x_get_cps, wsa884x_set_cps),
  953. SOC_SINGLE_EXT("External VDD_SPK", SND_SOC_NOPM, 0, 1, 0,
  954. wsa884x_get_ext_vdd_spk, wsa884x_put_ext_vdd_spk),
  955. };
  956. static const struct snd_kcontrol_new swr_dac_port[] = {
  957. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  958. };
  959. static int wsa884x_set_port(struct snd_soc_component *component, int port_idx,
  960. u8 *port_id, u8 *num_ch, u8 *ch_mask, u32 *ch_rate,
  961. u8 *port_type)
  962. {
  963. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  964. *port_id = wsa884x->port[port_idx].port_id;
  965. *num_ch = wsa884x->port[port_idx].num_ch;
  966. *ch_mask = wsa884x->port[port_idx].ch_mask;
  967. *ch_rate = wsa884x->port[port_idx].ch_rate;
  968. *port_type = wsa884x->port[port_idx].port_type;
  969. return 0;
  970. }
  971. static int wsa884x_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
  972. struct snd_kcontrol *kcontrol, int event)
  973. {
  974. struct snd_soc_component *component =
  975. snd_soc_dapm_to_component(w->dapm);
  976. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  977. u8 port_id[WSA884X_MAX_SWR_PORTS];
  978. u8 num_ch[WSA884X_MAX_SWR_PORTS];
  979. u8 ch_mask[WSA884X_MAX_SWR_PORTS];
  980. u32 ch_rate[WSA884X_MAX_SWR_PORTS];
  981. u8 port_type[WSA884X_MAX_SWR_PORTS];
  982. u8 num_port = 0;
  983. dev_dbg(component->dev, "%s: event %d name %s\n", __func__,
  984. event, w->name);
  985. if (wsa884x == NULL)
  986. return -EINVAL;
  987. switch (event) {
  988. case SND_SOC_DAPM_PRE_PMU:
  989. wsa884x_set_port(component, SWR_DAC_PORT,
  990. &port_id[num_port], &num_ch[num_port],
  991. &ch_mask[num_port], &ch_rate[num_port],
  992. &port_type[num_port]);
  993. ++num_port;
  994. if (wsa884x->comp_enable) {
  995. wsa884x_set_port(component, SWR_COMP_PORT,
  996. &port_id[num_port], &num_ch[num_port],
  997. &ch_mask[num_port], &ch_rate[num_port],
  998. &port_type[num_port]);
  999. ++num_port;
  1000. }
  1001. if (wsa884x->pbr_enable) {
  1002. wsa884x_set_port(component, SWR_PBR_PORT,
  1003. &port_id[num_port], &num_ch[num_port],
  1004. &ch_mask[num_port], &ch_rate[num_port],
  1005. &port_type[num_port]);
  1006. ++num_port;
  1007. }
  1008. if (wsa884x->visense_enable) {
  1009. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1010. &port_id[num_port], &num_ch[num_port],
  1011. &ch_mask[num_port], &ch_rate[num_port],
  1012. &port_type[num_port]);
  1013. ++num_port;
  1014. }
  1015. if (wsa884x->cps_enable) {
  1016. wsa884x_set_port(component, SWR_CPS_PORT,
  1017. &port_id[num_port], &num_ch[num_port],
  1018. &ch_mask[num_port], &ch_rate[num_port],
  1019. &port_type[num_port]);
  1020. ++num_port;
  1021. }
  1022. swr_connect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1023. &ch_mask[0], &ch_rate[0], &num_ch[0],
  1024. &port_type[0]);
  1025. break;
  1026. case SND_SOC_DAPM_POST_PMU:
  1027. set_bit(SPKR_STATUS, &wsa884x->status_mask);
  1028. break;
  1029. case SND_SOC_DAPM_PRE_PMD:
  1030. wsa884x_set_port(component, SWR_DAC_PORT,
  1031. &port_id[num_port], &num_ch[num_port],
  1032. &ch_mask[num_port], &ch_rate[num_port],
  1033. &port_type[num_port]);
  1034. ++num_port;
  1035. if (wsa884x->comp_enable) {
  1036. wsa884x_set_port(component, SWR_COMP_PORT,
  1037. &port_id[num_port], &num_ch[num_port],
  1038. &ch_mask[num_port], &ch_rate[num_port],
  1039. &port_type[num_port]);
  1040. ++num_port;
  1041. }
  1042. if (wsa884x->pbr_enable) {
  1043. wsa884x_set_port(component, SWR_PBR_PORT,
  1044. &port_id[num_port], &num_ch[num_port],
  1045. &ch_mask[num_port], &ch_rate[num_port],
  1046. &port_type[num_port]);
  1047. ++num_port;
  1048. }
  1049. if (wsa884x->visense_enable) {
  1050. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1051. &port_id[num_port], &num_ch[num_port],
  1052. &ch_mask[num_port], &ch_rate[num_port],
  1053. &port_type[num_port]);
  1054. ++num_port;
  1055. }
  1056. if (wsa884x->cps_enable) {
  1057. wsa884x_set_port(component, SWR_CPS_PORT,
  1058. &port_id[num_port], &num_ch[num_port],
  1059. &ch_mask[num_port], &ch_rate[num_port],
  1060. &port_type[num_port]);
  1061. ++num_port;
  1062. }
  1063. swr_disconnect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1064. &ch_mask[0], &port_type[0]);
  1065. break;
  1066. case SND_SOC_DAPM_POST_PMD:
  1067. if (swr_set_device_group(wsa884x->swr_slave, SWR_GROUP_NONE))
  1068. dev_err(component->dev,
  1069. "%s: set num ch failed\n", __func__);
  1070. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1071. wsa884x->swr_slave->dev_num,
  1072. false);
  1073. break;
  1074. default:
  1075. break;
  1076. }
  1077. return 0;
  1078. }
  1079. static int wsa884x_set_gain_parameters(struct snd_soc_component *component)
  1080. {
  1081. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1082. switch (wsa884x->bat_cfg) {
  1083. case CONFIG_1S:
  1084. case EXT_1S:
  1085. switch (wsa884x->system_gain) {
  1086. case G_21_DB:
  1087. wsa884x->comp_offset = COMP_OFFSET0;
  1088. wsa884x->min_gain = G_0_DB;
  1089. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  1090. break;
  1091. case G_19P5_DB:
  1092. wsa884x->comp_offset = COMP_OFFSET1;
  1093. wsa884x->min_gain = G_M1P5_DB;
  1094. wsa884x->pa_aux_gain = PA_AUX_M1P5_DB;
  1095. break;
  1096. case G_18_DB:
  1097. wsa884x->comp_offset = COMP_OFFSET2;
  1098. wsa884x->min_gain = G_M3_DB;
  1099. wsa884x->pa_aux_gain = PA_AUX_M3_DB;
  1100. break;
  1101. case G_16P5_DB:
  1102. wsa884x->comp_offset = COMP_OFFSET3;
  1103. wsa884x->min_gain = G_M4P5_DB;
  1104. wsa884x->pa_aux_gain = PA_AUX_M4P5_DB;
  1105. break;
  1106. default:
  1107. wsa884x->comp_offset = COMP_OFFSET4;
  1108. wsa884x->min_gain = G_M6_DB;
  1109. wsa884x->pa_aux_gain = PA_AUX_M6_DB;
  1110. break;
  1111. }
  1112. break;
  1113. case CONFIG_3S:
  1114. case EXT_3S:
  1115. wsa884x->comp_offset = COMP_OFFSET0;
  1116. wsa884x->min_gain = G_7P5_DB;
  1117. wsa884x->pa_aux_gain = PA_AUX_7P5_DB;
  1118. break;
  1119. case EXT_ABOVE_3S:
  1120. wsa884x->comp_offset = COMP_OFFSET0;
  1121. wsa884x->min_gain = G_12_DB;
  1122. wsa884x->pa_aux_gain = PA_AUX_12_DB;
  1123. break;
  1124. default:
  1125. wsa884x->comp_offset = COMP_OFFSET0;
  1126. wsa884x->min_gain = G_0_DB;
  1127. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  1128. break;
  1129. }
  1130. if (!wsa884x->comp_enable)
  1131. wsa884x->pa_aux_gain = pa_aux_no_comp[wsa884x->system_gain];
  1132. snd_soc_component_update_bits(component,
  1133. REG_FIELD_VALUE(GAIN_RAMPING_MIN, MIN_GAIN, wsa884x->min_gain));
  1134. if (wsa884x->comp_enable)
  1135. snd_soc_component_update_bits(component,
  1136. REG_FIELD_VALUE(DRE_CTL_0, OFFSET,
  1137. wsa884x->comp_offset));
  1138. return 0;
  1139. }
  1140. static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
  1141. struct snd_kcontrol *kcontrol, int event)
  1142. {
  1143. struct snd_soc_component *component =
  1144. snd_soc_dapm_to_component(w->dapm);
  1145. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1146. u8 igain;
  1147. u8 vgain;
  1148. u8 ana_wo_ctl_0_value;
  1149. u8 pa_aux_shift = 0x02;
  1150. u8 vphx_shift = 0x06;
  1151. dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
  1152. switch (event) {
  1153. case SND_SOC_DAPM_POST_PMU:
  1154. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1155. wsa884x->swr_slave->dev_num,
  1156. true);
  1157. wsa884x_set_gain_parameters(component);
  1158. /* Must write WO registers in a single write */
  1159. ana_wo_ctl_0_value = ((wsa884x->bat_cfg & 0x03) << vphx_shift) |
  1160. (wsa884x->pa_aux_gain << pa_aux_shift) |
  1161. wsa884x->dev_mode;
  1162. snd_soc_component_update_bits(component,
  1163. WSA884X_ANA_WO_CTL_0, 0xFF, ana_wo_ctl_0_value);
  1164. snd_soc_component_update_bits(component,
  1165. WSA884X_ANA_WO_CTL_1, 0xFF, 0);
  1166. if (wsa884x->rload == WSA_4OHMS ||
  1167. wsa884x->rload == WSA_6OHMS)
  1168. snd_soc_component_update_bits(component,
  1169. REG_FIELD_VALUE(OCP_CTL, OCP_CURR_LIMIT, 0x07));
  1170. if (wsa884x->dev_mode == SPEAKER) {
  1171. snd_soc_component_update_bits(component,
  1172. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1173. } else {
  1174. snd_soc_component_update_bits(component,
  1175. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1176. snd_soc_component_update_bits(component,
  1177. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1178. snd_soc_component_update_bits(component,
  1179. REG_FIELD_VALUE(PWM_CLK_CTL,
  1180. PWM_CLK_FREQ_SEL, 0x01));
  1181. }
  1182. if (!wsa884x->pbr_enable) {
  1183. snd_soc_component_update_bits(component,
  1184. REG_FIELD_VALUE(CURRENT_LIMIT,
  1185. CURRENT_LIMIT_OVRD_EN, 0x01));
  1186. snd_soc_component_update_bits(component,
  1187. REG_FIELD_VALUE(CURRENT_LIMIT,
  1188. CURRENT_LIMIT, 0x09));
  1189. }
  1190. igain = isense_gain_data[wsa884x->system_gain][wsa884x->rload];
  1191. vgain = vsense_gain_data[wsa884x->system_gain];
  1192. snd_soc_component_update_bits(component,
  1193. REG_FIELD_VALUE(ISENSE2, ISENSE_GAIN_CTL, igain));
  1194. snd_soc_component_update_bits(component,
  1195. REG_FIELD_VALUE(VSENSE1, GAIN_VSENSE_FE, vgain));
  1196. wcd_enable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO);
  1197. /* Force remove group */
  1198. swr_remove_from_group(wsa884x->swr_slave,
  1199. wsa884x->swr_slave->dev_num);
  1200. snd_soc_component_update_bits(component,
  1201. REG_FIELD_VALUE(VBAT_THRM_FLT_CTL, VBAT_COEF_SEL, 0x04));
  1202. if (test_bit(SPKR_ADIE_LB, &wsa884x->status_mask))
  1203. snd_soc_component_update_bits(component,
  1204. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1205. break;
  1206. case SND_SOC_DAPM_PRE_PMD:
  1207. if (!test_bit(SPKR_ADIE_LB, &wsa884x->status_mask))
  1208. wcd_disable_irq(&wsa884x->irq_info,
  1209. WSA884X_IRQ_INT_PDM_WD);
  1210. snd_soc_component_update_bits(component,
  1211. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1212. snd_soc_component_update_bits(component,
  1213. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  1214. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO);
  1215. clear_bit(SPKR_STATUS, &wsa884x->status_mask);
  1216. clear_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1217. break;
  1218. }
  1219. return 0;
  1220. }
  1221. static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
  1222. SND_SOC_DAPM_INPUT("IN"),
  1223. SND_SOC_DAPM_MIXER_E("SWR DAC_Port", SND_SOC_NOPM, 0, 0, swr_dac_port,
  1224. ARRAY_SIZE(swr_dac_port), wsa884x_enable_swr_dac_port,
  1225. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1226. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1227. SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
  1228. };
  1229. static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
  1230. {"SWR DAC_Port", "Switch", "IN"},
  1231. {"SPKR", NULL, "SWR DAC_Port"},
  1232. };
  1233. int wsa884x_set_channel_map(struct snd_soc_component *component, u8 *port,
  1234. u8 num_port, unsigned int *ch_mask,
  1235. unsigned int *ch_rate, u8 *port_type)
  1236. {
  1237. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1238. int i;
  1239. if (!port || !ch_mask || !ch_rate ||
  1240. (num_port > WSA884X_MAX_SWR_PORTS)) {
  1241. dev_err(component->dev,
  1242. "%s: Invalid port=%pK, ch_mask=%pK, ch_rate=%pK\n",
  1243. __func__, port, ch_mask, ch_rate);
  1244. return -EINVAL;
  1245. }
  1246. for (i = 0; i < num_port; i++) {
  1247. wsa884x->port[i].port_id = port[i];
  1248. wsa884x->port[i].ch_mask = ch_mask[i];
  1249. wsa884x->port[i].ch_rate = ch_rate[i];
  1250. wsa884x->port[i].num_ch = __sw_hweight8(ch_mask[i]);
  1251. if (port_type)
  1252. wsa884x->port[i].port_type = port_type[i];
  1253. }
  1254. return 0;
  1255. }
  1256. EXPORT_SYMBOL(wsa884x_set_channel_map);
  1257. static void wsa884x_codec_init(struct snd_soc_component *component)
  1258. {
  1259. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1260. int i;
  1261. if (!wsa884x)
  1262. return;
  1263. for (i = 0; i < ARRAY_SIZE(reg_init); i++)
  1264. snd_soc_component_update_bits(component, reg_init[i].reg,
  1265. reg_init[i].mask, reg_init[i].val);
  1266. if (wsa884x->variant == WSA8845H)
  1267. snd_soc_component_update_bits(wsa884x->component,
  1268. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
  1269. }
  1270. static int32_t wsa884x_temp_reg_read(struct snd_soc_component *component,
  1271. struct wsa_temp_register *wsa_temp_reg)
  1272. {
  1273. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1274. if (!wsa884x) {
  1275. dev_err(component->dev, "%s: wsa884x is NULL\n", __func__);
  1276. return -EINVAL;
  1277. }
  1278. mutex_lock(&wsa884x->res_lock);
  1279. snd_soc_component_update_bits(component,
  1280. REG_FIELD_VALUE(PA_FSM_BYP0, DC_CAL_EN, 0x01));
  1281. snd_soc_component_update_bits(component,
  1282. REG_FIELD_VALUE(PA_FSM_BYP0, BG_EN, 0x01));
  1283. snd_soc_component_update_bits(component,
  1284. REG_FIELD_VALUE(PA_FSM_BYP0, CLK_WD_EN, 0x01));
  1285. snd_soc_component_update_bits(component,
  1286. REG_FIELD_VALUE(PA_FSM_BYP0, TSADC_EN, 0x01));
  1287. snd_soc_component_update_bits(component,
  1288. REG_FIELD_VALUE(PA_FSM_BYP0, D_UNMUTE, 0x01));
  1289. snd_soc_component_update_bits(component,
  1290. REG_FIELD_VALUE(PA_FSM_BYP0, SPKR_PROT_EN, 0x01));
  1291. snd_soc_component_update_bits(component,
  1292. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x00));
  1293. wsa_temp_reg->dmeas_msb = snd_soc_component_read(component,
  1294. WSA884X_TEMP_DIN_MSB);
  1295. wsa_temp_reg->dmeas_lsb = snd_soc_component_read(component,
  1296. WSA884X_TEMP_DIN_LSB);
  1297. snd_soc_component_update_bits(component,
  1298. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x01));
  1299. wsa_temp_reg->d1_msb = snd_soc_component_read(component,
  1300. WSA884X_OTP_REG_1);
  1301. wsa_temp_reg->d1_lsb = snd_soc_component_read(component,
  1302. WSA884X_OTP_REG_2);
  1303. wsa_temp_reg->d2_msb = snd_soc_component_read(component,
  1304. WSA884X_OTP_REG_3);
  1305. wsa_temp_reg->d2_lsb = snd_soc_component_read(component,
  1306. WSA884X_OTP_REG_4);
  1307. snd_soc_component_update_bits(component,
  1308. WSA884X_PA_FSM_BYP0, 0xE7, 0x00);
  1309. mutex_unlock(&wsa884x->res_lock);
  1310. return 0;
  1311. }
  1312. static int wsa884x_get_temperature(struct snd_soc_component *component,
  1313. int *temp)
  1314. {
  1315. struct wsa_temp_register reg;
  1316. int dmeas, d1, d2;
  1317. int ret = 0;
  1318. int temp_val = 0;
  1319. int t1 = T1_TEMP;
  1320. int t2 = T2_TEMP;
  1321. u8 retry = WSA884X_TEMP_RETRY;
  1322. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1323. if (!wsa884x)
  1324. return -EINVAL;
  1325. do {
  1326. ret = wsa884x_temp_reg_read(component, &reg);
  1327. if (ret) {
  1328. pr_err("%s: temp read failed: %d, current temp: %d\n",
  1329. __func__, ret, wsa884x->curr_temp);
  1330. if (temp)
  1331. *temp = wsa884x->curr_temp;
  1332. return 0;
  1333. }
  1334. /*
  1335. * Temperature register values are expected to be in the
  1336. * following range.
  1337. * d1_msb = 68 - 92 and d1_lsb = 0, 64, 128, 192
  1338. * d2_msb = 185 -218 and d2_lsb = 0, 64, 128, 192
  1339. */
  1340. if ((reg.d1_msb < 68 || reg.d1_msb > 92) ||
  1341. (!(reg.d1_lsb == 0 || reg.d1_lsb == 64 || reg.d1_lsb == 128 ||
  1342. reg.d1_lsb == 192)) ||
  1343. (reg.d2_msb < 185 || reg.d2_msb > 218) ||
  1344. (!(reg.d2_lsb == 0 || reg.d2_lsb == 64 || reg.d2_lsb == 128 ||
  1345. reg.d2_lsb == 192))) {
  1346. printk_ratelimited("%s: Temperature registers[%d %d %d %d] are out of range\n",
  1347. __func__, reg.d1_msb, reg.d1_lsb, reg.d2_msb,
  1348. reg.d2_lsb);
  1349. }
  1350. dmeas = ((reg.dmeas_msb << 0x8) | reg.dmeas_lsb) >> 0x6;
  1351. d1 = ((reg.d1_msb << 0x8) | reg.d1_lsb) >> 0x6;
  1352. d2 = ((reg.d2_msb << 0x8) | reg.d2_lsb) >> 0x6;
  1353. if (d1 == d2)
  1354. temp_val = TEMP_INVALID;
  1355. else
  1356. temp_val = t1 + (((dmeas - d1) * (t2 - t1))/(d2 - d1));
  1357. if (temp_val <= LOW_TEMP_THRESHOLD ||
  1358. temp_val >= HIGH_TEMP_THRESHOLD) {
  1359. pr_debug("%s: T0: %d is out of range[%d, %d]\n", __func__,
  1360. temp_val, LOW_TEMP_THRESHOLD, HIGH_TEMP_THRESHOLD);
  1361. if (retry--)
  1362. msleep(10);
  1363. } else {
  1364. break;
  1365. }
  1366. } while (retry);
  1367. wsa884x->curr_temp = temp_val;
  1368. if (temp)
  1369. *temp = temp_val;
  1370. pr_debug("%s: t0 measured: %d dmeas = %d, d1 = %d, d2 = %d\n",
  1371. __func__, temp_val, dmeas, d1, d2);
  1372. return ret;
  1373. }
  1374. static int wsa884x_codec_probe(struct snd_soc_component *component)
  1375. {
  1376. char w_name[MAX_NAME_LEN];
  1377. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1378. struct swr_device *dev;
  1379. int variant = 0, version = 0;
  1380. struct snd_soc_dapm_context *dapm =
  1381. snd_soc_component_get_dapm(component);
  1382. if (!wsa884x)
  1383. return -EINVAL;
  1384. if (!component->name_prefix)
  1385. return -EINVAL;
  1386. snd_soc_component_init_regmap(component, wsa884x->regmap);
  1387. dev = wsa884x->swr_slave;
  1388. wsa884x->component = component;
  1389. variant = (snd_soc_component_read(component, WSA884X_OTP_REG_0)
  1390. & FIELD_MASK(OTP_REG_0, WSA884X_ID));
  1391. wsa884x->variant = variant;
  1392. version = (snd_soc_component_read(component, WSA884X_CHIP_ID0)
  1393. & FIELD_MASK(CHIP_ID0, BYTE_0));
  1394. wsa884x->version = version;
  1395. wsa884x->comp_offset = COMP_OFFSET2;
  1396. wsa884x->bat_cfg = CONFIG_1S;
  1397. wsa884x->rload = WSA_8OHMS;
  1398. wsa884x->system_gain = G_19P5_DB;
  1399. wsa884x_codec_init(component);
  1400. wsa884x->global_pa_cnt = 0;
  1401. memset(w_name, 0, sizeof(w_name));
  1402. strlcpy(w_name, component->name_prefix, sizeof(w_name));
  1403. strlcat(w_name, " ", sizeof(w_name));
  1404. strlcat(w_name, wsa884x->dai_driver->playback.stream_name,
  1405. sizeof(w_name));
  1406. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1407. memset(w_name, 0, sizeof(w_name));
  1408. strlcpy(w_name, component->name_prefix, sizeof(w_name));
  1409. strlcat(w_name, " IN", sizeof(w_name));
  1410. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1411. memset(w_name, 0, sizeof(w_name));
  1412. strlcpy(w_name, component->name_prefix, sizeof(w_name));
  1413. strlcat(w_name, " SWR DAC_Port", sizeof(w_name));
  1414. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1415. memset(w_name, 0, sizeof(w_name));
  1416. strlcpy(w_name, component->name_prefix, sizeof(w_name));
  1417. strlcat(w_name, " SPKR", sizeof(w_name));
  1418. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1419. snd_soc_dapm_sync(dapm);
  1420. return 0;
  1421. }
  1422. static void wsa884x_codec_remove(struct snd_soc_component *component)
  1423. {
  1424. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1425. if (!wsa884x)
  1426. return;
  1427. snd_soc_component_exit_regmap(component);
  1428. return;
  1429. }
  1430. static int wsa884x_soc_codec_suspend(struct snd_soc_component *component)
  1431. {
  1432. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1433. if (!wsa884x)
  1434. return 0;
  1435. wsa884x->dapm_bias_off = true;
  1436. return 0;
  1437. }
  1438. static int wsa884x_soc_codec_resume(struct snd_soc_component *component)
  1439. {
  1440. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1441. if (!wsa884x)
  1442. return 0;
  1443. wsa884x->dapm_bias_off = false;
  1444. return 0;
  1445. }
  1446. static const struct snd_soc_component_driver soc_codec_dev_wsa884x_wsa = {
  1447. .name = "",
  1448. .probe = wsa884x_codec_probe,
  1449. .remove = wsa884x_codec_remove,
  1450. .controls = wsa884x_snd_controls,
  1451. .num_controls = ARRAY_SIZE(wsa884x_snd_controls),
  1452. .dapm_widgets = wsa884x_dapm_widgets,
  1453. .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
  1454. .dapm_routes = wsa884x_audio_map,
  1455. .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
  1456. .suspend = wsa884x_soc_codec_suspend,
  1457. .resume = wsa884x_soc_codec_resume,
  1458. };
  1459. static int wsa884x_gpio_ctrl(struct wsa884x_priv *wsa884x, bool enable)
  1460. {
  1461. int ret = 0;
  1462. if (enable)
  1463. ret = msm_cdc_pinctrl_select_active_state(
  1464. wsa884x->wsa_rst_np);
  1465. else
  1466. ret = msm_cdc_pinctrl_select_sleep_state(
  1467. wsa884x->wsa_rst_np);
  1468. if (ret != 0)
  1469. dev_err(wsa884x->dev,
  1470. "%s: Failed to turn state %d; ret=%d\n",
  1471. __func__, enable, ret);
  1472. return ret;
  1473. }
  1474. static int wsa884x_swr_up(struct wsa884x_priv *wsa884x)
  1475. {
  1476. int ret;
  1477. ret = wsa884x_gpio_ctrl(wsa884x, true);
  1478. if (ret)
  1479. dev_err(wsa884x->dev, "%s: Failed to enable gpio\n", __func__);
  1480. return ret;
  1481. }
  1482. static int wsa884x_swr_down(struct wsa884x_priv *wsa884x)
  1483. {
  1484. int ret;
  1485. ret = wsa884x_gpio_ctrl(wsa884x, false);
  1486. if (ret)
  1487. dev_err(wsa884x->dev, "%s: Failed to disable gpio\n", __func__);
  1488. return ret;
  1489. }
  1490. static int wsa884x_swr_reset(struct wsa884x_priv *wsa884x)
  1491. {
  1492. u8 retry = WSA884X_NUM_RETRY;
  1493. u8 devnum = 0;
  1494. struct swr_device *pdev;
  1495. pdev = wsa884x->swr_slave;
  1496. while (swr_get_logical_dev_num(pdev, pdev->addr, &devnum) && retry--) {
  1497. /* Retry after 1 msec delay */
  1498. usleep_range(1000, 1100);
  1499. }
  1500. pdev->dev_num = devnum;
  1501. wsa884x_regcache_sync(wsa884x);
  1502. return 0;
  1503. }
  1504. static int wsa884x_event_notify(struct notifier_block *nb,
  1505. unsigned long val, void *ptr)
  1506. {
  1507. u16 event = (val & 0xffff);
  1508. struct wsa884x_priv *wsa884x = container_of(nb, struct wsa884x_priv,
  1509. parent_nblock);
  1510. if (!wsa884x)
  1511. return -EINVAL;
  1512. switch (event) {
  1513. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1514. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1515. snd_soc_component_update_bits(wsa884x->component,
  1516. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1517. wsa884x_swr_down(wsa884x);
  1518. break;
  1519. case BOLERO_SLV_EVT_SSR_UP:
  1520. wsa884x_swr_up(wsa884x);
  1521. /* Add delay to allow enumerate */
  1522. usleep_range(20000, 20010);
  1523. wsa884x_swr_reset(wsa884x);
  1524. break;
  1525. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK:
  1526. if (test_bit(SPKR_STATUS, &wsa884x->status_mask)) {
  1527. snd_soc_component_update_bits(wsa884x->component,
  1528. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  1529. snd_soc_component_update_bits(wsa884x->component,
  1530. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1531. wcd_enable_irq(&wsa884x->irq_info,
  1532. WSA884X_IRQ_INT_PDM_WD);
  1533. /* Added delay as per HW sequence */
  1534. usleep_range(3000, 3100);
  1535. snd_soc_component_update_bits(wsa884x->component,
  1536. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x00));
  1537. /* Added delay as per HW sequence */
  1538. usleep_range(5000, 5050);
  1539. }
  1540. break;
  1541. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK_ADIE_LB:
  1542. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1543. set_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1544. break;
  1545. default:
  1546. dev_dbg(wsa884x->dev, "%s: unknown event %d\n",
  1547. __func__, event);
  1548. break;
  1549. }
  1550. return 0;
  1551. }
  1552. static int wsa884x_enable_supplies(struct device *dev,
  1553. struct wsa884x_priv *priv)
  1554. {
  1555. int ret = 0;
  1556. /* Parse power supplies */
  1557. msm_cdc_get_power_supplies(dev, &priv->regulator,
  1558. &priv->num_supplies);
  1559. if (!priv->regulator || (priv->num_supplies <= 0)) {
  1560. dev_err(dev, "%s: no power supplies defined\n", __func__);
  1561. return -EINVAL;
  1562. }
  1563. ret = msm_cdc_init_supplies(dev, &priv->supplies,
  1564. priv->regulator, priv->num_supplies);
  1565. if (!priv->supplies) {
  1566. dev_err(dev, "%s: Cannot init wsa supplies\n",
  1567. __func__);
  1568. return ret;
  1569. }
  1570. ret = msm_cdc_enable_static_supplies(dev, priv->supplies,
  1571. priv->regulator,
  1572. priv->num_supplies);
  1573. if (ret)
  1574. dev_err(dev, "%s: wsa static supply enable failed!\n",
  1575. __func__);
  1576. return ret;
  1577. }
  1578. static struct snd_soc_dai_driver wsa_dai[] = {
  1579. {
  1580. .name = "",
  1581. .playback = {
  1582. .stream_name = "",
  1583. .rates = WSA884X_RATES | WSA884X_FRAC_RATES,
  1584. .formats = WSA884X_FORMATS,
  1585. .rate_max = 192000,
  1586. .rate_min = 8000,
  1587. .channels_min = 1,
  1588. .channels_max = 2,
  1589. },
  1590. },
  1591. };
  1592. static int wsa884x_swr_probe(struct swr_device *pdev)
  1593. {
  1594. int ret = 0, i = 0;
  1595. struct wsa884x_priv *wsa884x;
  1596. u8 devnum = 0;
  1597. bool pin_state_current = false;
  1598. struct wsa_ctrl_platform_data *plat_data = NULL;
  1599. struct snd_soc_component *component;
  1600. const char *wsa884x_name_prefix_of = NULL;
  1601. char buffer[MAX_NAME_LEN];
  1602. int dev_index = 0;
  1603. wsa884x = devm_kzalloc(&pdev->dev, sizeof(struct wsa884x_priv),
  1604. GFP_KERNEL);
  1605. if (!wsa884x)
  1606. return -ENOMEM;
  1607. ret = wsa884x_enable_supplies(&pdev->dev, wsa884x);
  1608. if (ret) {
  1609. ret = -EPROBE_DEFER;
  1610. goto err;
  1611. }
  1612. wsa884x->wsa_rst_np = of_parse_phandle(pdev->dev.of_node,
  1613. "qcom,spkr-sd-n-node", 0);
  1614. if (!wsa884x->wsa_rst_np) {
  1615. dev_dbg(&pdev->dev, "%s: pinctrl not defined\n", __func__);
  1616. goto err_supply;
  1617. }
  1618. swr_set_dev_data(pdev, wsa884x);
  1619. wsa884x->swr_slave = pdev;
  1620. pin_state_current = msm_cdc_pinctrl_get_state(wsa884x->wsa_rst_np);
  1621. wsa884x_gpio_ctrl(wsa884x, true);
  1622. /*
  1623. * Add 5msec delay to provide sufficient time for
  1624. * soundwire auto enumeration of slave devices as
  1625. * per HW requirement.
  1626. */
  1627. usleep_range(5000, 5010);
  1628. ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
  1629. if (ret) {
  1630. dev_dbg(&pdev->dev,
  1631. "%s get devnum %d for dev addr %lx failed\n",
  1632. __func__, devnum, pdev->addr);
  1633. ret = -EPROBE_DEFER;
  1634. goto err_supply;
  1635. }
  1636. pdev->dev_num = devnum;
  1637. wsa884x->regmap = devm_regmap_init_swr(pdev,
  1638. &wsa884x_regmap_config);
  1639. if (IS_ERR(wsa884x->regmap)) {
  1640. ret = PTR_ERR(wsa884x->regmap);
  1641. dev_err(&pdev->dev, "%s: regmap_init failed %d\n",
  1642. __func__, ret);
  1643. goto dev_err;
  1644. }
  1645. devm_regmap_qti_debugfs_register(&pdev->dev, wsa884x->regmap);
  1646. /* Set all interrupts as edge triggered */
  1647. for (i = 0; i < wsa884x_regmap_irq_chip.num_regs; i++)
  1648. regmap_write(wsa884x->regmap, (WSA884X_INTR_LEVEL0 + i), 0);
  1649. wsa884x_regmap_irq_chip.irq_drv_data = wsa884x;
  1650. wsa884x->irq_info.wcd_regmap_irq_chip = &wsa884x_regmap_irq_chip;
  1651. wsa884x->irq_info.codec_name = "WSA884X";
  1652. wsa884x->irq_info.regmap = wsa884x->regmap;
  1653. wsa884x->irq_info.dev = &pdev->dev;
  1654. ret = wcd_irq_init(&wsa884x->irq_info, &wsa884x->virq);
  1655. if (ret) {
  1656. dev_err(wsa884x->dev, "%s: IRQ init failed: %d\n",
  1657. __func__, ret);
  1658. goto dev_err;
  1659. }
  1660. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR,
  1661. "WSA SAF2WAR", wsa884x_saf2war_handle_irq, NULL);
  1662. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR);
  1663. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF,
  1664. "WSA WAR2SAF", wsa884x_war2saf_handle_irq, NULL);
  1665. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF);
  1666. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE,
  1667. "WSA OTP", wsa884x_otp_handle_irq, NULL);
  1668. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE);
  1669. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP,
  1670. "WSA OCP", wsa884x_ocp_handle_irq, NULL);
  1671. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP);
  1672. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP,
  1673. "WSA CLIP", wsa884x_clip_handle_irq, NULL);
  1674. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP);
  1675. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD,
  1676. "WSA PDM WD", wsa884x_pdm_wd_handle_irq, NULL);
  1677. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD);
  1678. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD,
  1679. "WSA CLK WD", wsa884x_clk_wd_handle_irq, NULL);
  1680. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD);
  1681. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN,
  1682. "WSA EXT INT", wsa884x_ext_int_handle_irq, NULL);
  1683. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN);
  1684. /* Under Voltage Lock out (UVLO) interrupt handle */
  1685. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO,
  1686. "WSA UVLO", wsa884x_uvlo_handle_irq, NULL);
  1687. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO);
  1688. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR,
  1689. "WSA PA ERR", wsa884x_pa_on_err_handle_irq, NULL);
  1690. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR);
  1691. ret = of_property_read_string(pdev->dev.of_node, "qcom,wsa-prefix",
  1692. &wsa884x_name_prefix_of);
  1693. if (ret) {
  1694. dev_err(&pdev->dev,
  1695. "%s: Looking up %s property in node %s failed\n",
  1696. __func__, "qcom,wsa-prefix",
  1697. pdev->dev.of_node->full_name);
  1698. goto err_irq;
  1699. }
  1700. wsa884x->driver = devm_kzalloc(&pdev->dev,
  1701. sizeof(struct snd_soc_component_driver), GFP_KERNEL);
  1702. if (!wsa884x->driver) {
  1703. ret = -ENOMEM;
  1704. goto err_irq;
  1705. }
  1706. memcpy(wsa884x->driver, &soc_codec_dev_wsa884x_wsa,
  1707. sizeof(struct snd_soc_component_driver));
  1708. wsa884x->dai_driver = devm_kzalloc(&pdev->dev,
  1709. sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
  1710. if (!wsa884x->dai_driver) {
  1711. ret = -ENOMEM;
  1712. goto err_mem;
  1713. }
  1714. memcpy(wsa884x->dai_driver, wsa_dai, sizeof(struct snd_soc_dai_driver));
  1715. /* Get last digit from HEX format */
  1716. dev_index = (int)((char)(pdev->addr & 0xF));
  1717. dev_index += 1;
  1718. if (of_device_is_compatible(pdev->dev.of_node, "qcom,wsa884x_2"))
  1719. dev_index += 2;
  1720. snprintf(buffer, sizeof(buffer), "wsa-codec.%d", dev_index);
  1721. wsa884x->driver->name = kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1722. snprintf(buffer, sizeof(buffer), "wsa_rx%d", dev_index);
  1723. wsa884x->dai_driver->name =
  1724. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1725. snprintf(buffer, sizeof(buffer), "WSA884X_AIF%d Playback", dev_index);
  1726. wsa884x->dai_driver->playback.stream_name =
  1727. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1728. /* Number of DAI's used is 1 */
  1729. ret = snd_soc_register_component(&pdev->dev,
  1730. wsa884x->driver, wsa884x->dai_driver, 1);
  1731. wsa884x->wsa884x_name_prefix = kstrndup(wsa884x_name_prefix_of,
  1732. strlen(wsa884x_name_prefix_of), GFP_KERNEL);
  1733. component = snd_soc_lookup_component(&pdev->dev, wsa884x->driver->name);
  1734. if (!component) {
  1735. dev_err(&pdev->dev, "%s: component is NULL\n", __func__);
  1736. ret = -EINVAL;
  1737. goto err_mem;
  1738. }
  1739. component->name_prefix = wsa884x->wsa884x_name_prefix;
  1740. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1741. "qcom,bolero-handle", 0);
  1742. if (!wsa884x->parent_np)
  1743. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1744. "qcom,lpass-cdc-handle", 0);
  1745. if (wsa884x->parent_np) {
  1746. wsa884x->parent_dev =
  1747. of_find_device_by_node(wsa884x->parent_np);
  1748. if (wsa884x->parent_dev) {
  1749. plat_data = dev_get_platdata(&wsa884x->parent_dev->dev);
  1750. if (plat_data) {
  1751. wsa884x->parent_nblock.notifier_call =
  1752. wsa884x_event_notify;
  1753. if (plat_data->register_notifier)
  1754. plat_data->register_notifier(
  1755. plat_data->handle,
  1756. &wsa884x->parent_nblock,
  1757. true);
  1758. wsa884x->register_notifier =
  1759. plat_data->register_notifier;
  1760. wsa884x->handle = plat_data->handle;
  1761. } else {
  1762. dev_err(&pdev->dev, "%s: plat data not found\n",
  1763. __func__);
  1764. }
  1765. } else {
  1766. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1767. __func__);
  1768. }
  1769. } else {
  1770. dev_info(&pdev->dev, "%s: parent node not found\n", __func__);
  1771. }
  1772. mutex_init(&wsa884x->res_lock);
  1773. #ifdef CONFIG_DEBUG_FS
  1774. if (!wsa884x->debugfs_dent) {
  1775. wsa884x->debugfs_dent = debugfs_create_dir(
  1776. dev_name(&pdev->dev), 0);
  1777. if (!IS_ERR(wsa884x->debugfs_dent)) {
  1778. wsa884x->debugfs_peek =
  1779. debugfs_create_file("swrslave_peek",
  1780. S_IFREG | 0444,
  1781. wsa884x->debugfs_dent,
  1782. (void *) pdev,
  1783. &codec_debug_read_ops);
  1784. wsa884x->debugfs_poke =
  1785. debugfs_create_file("swrslave_poke",
  1786. S_IFREG | 0444,
  1787. wsa884x->debugfs_dent,
  1788. (void *) pdev,
  1789. &codec_debug_write_ops);
  1790. wsa884x->debugfs_reg_dump =
  1791. debugfs_create_file(
  1792. "swrslave_reg_dump",
  1793. S_IFREG | 0444,
  1794. wsa884x->debugfs_dent,
  1795. (void *) pdev,
  1796. &codec_debug_dump_ops);
  1797. }
  1798. }
  1799. #endif
  1800. return 0;
  1801. err_mem:
  1802. kfree(wsa884x->wsa884x_name_prefix);
  1803. if (wsa884x->dai_driver) {
  1804. kfree(wsa884x->dai_driver->name);
  1805. kfree(wsa884x->dai_driver->playback.stream_name);
  1806. kfree(wsa884x->dai_driver);
  1807. }
  1808. if (wsa884x->driver) {
  1809. kfree(wsa884x->driver->name);
  1810. kfree(wsa884x->driver);
  1811. }
  1812. err_irq:
  1813. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR, NULL);
  1814. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF, NULL);
  1815. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE, NULL);
  1816. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP, NULL);
  1817. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP, NULL);
  1818. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD, NULL);
  1819. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD, NULL);
  1820. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN, NULL);
  1821. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO, NULL);
  1822. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR, NULL);
  1823. wcd_irq_exit(&wsa884x->irq_info, wsa884x->virq);
  1824. dev_err:
  1825. if (pin_state_current == false)
  1826. wsa884x_gpio_ctrl(wsa884x, false);
  1827. swr_remove_device(pdev);
  1828. err_supply:
  1829. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  1830. wsa884x->regulator,
  1831. wsa884x->num_supplies);
  1832. err:
  1833. swr_set_dev_data(pdev, NULL);
  1834. return ret;
  1835. }
  1836. static int wsa884x_swr_remove(struct swr_device *pdev)
  1837. {
  1838. struct wsa884x_priv *wsa884x;
  1839. wsa884x = swr_get_dev_data(pdev);
  1840. if (!wsa884x) {
  1841. dev_err(&pdev->dev, "%s: wsa884x is NULL\n", __func__);
  1842. return -EINVAL;
  1843. }
  1844. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR, NULL);
  1845. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF, NULL);
  1846. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE, NULL);
  1847. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP, NULL);
  1848. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP, NULL);
  1849. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD, NULL);
  1850. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD, NULL);
  1851. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN, NULL);
  1852. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO, NULL);
  1853. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR, NULL);
  1854. if (wsa884x->register_notifier)
  1855. wsa884x->register_notifier(wsa884x->handle,
  1856. &wsa884x->parent_nblock, false);
  1857. #ifdef CONFIG_DEBUG_FS
  1858. debugfs_remove_recursive(wsa884x->debugfs_dent);
  1859. wsa884x->debugfs_dent = NULL;
  1860. #endif
  1861. mutex_destroy(&wsa884x->res_lock);
  1862. snd_soc_unregister_component(&pdev->dev);
  1863. kfree(wsa884x->wsa884x_name_prefix);
  1864. if (wsa884x->dai_driver) {
  1865. kfree(wsa884x->dai_driver->name);
  1866. kfree(wsa884x->dai_driver->playback.stream_name);
  1867. kfree(wsa884x->dai_driver);
  1868. }
  1869. if (wsa884x->driver) {
  1870. kfree(wsa884x->driver->name);
  1871. kfree(wsa884x->driver);
  1872. }
  1873. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  1874. wsa884x->regulator,
  1875. wsa884x->num_supplies);
  1876. swr_set_dev_data(pdev, NULL);
  1877. return 0;
  1878. }
  1879. #ifdef CONFIG_PM_SLEEP
  1880. static int wsa884x_swr_suspend(struct device *dev)
  1881. {
  1882. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  1883. if (!wsa884x) {
  1884. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  1885. return -EINVAL;
  1886. }
  1887. dev_dbg(dev, "%s: system suspend\n", __func__);
  1888. if (wsa884x->dapm_bias_off) {
  1889. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  1890. wsa884x->regulator,
  1891. wsa884x->num_supplies,
  1892. true);
  1893. set_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  1894. }
  1895. return 0;
  1896. }
  1897. static int wsa884x_swr_resume(struct device *dev)
  1898. {
  1899. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  1900. if (!wsa884x) {
  1901. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  1902. return -EINVAL;
  1903. }
  1904. if (test_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask)) {
  1905. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  1906. wsa884x->regulator,
  1907. wsa884x->num_supplies,
  1908. false);
  1909. clear_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  1910. }
  1911. dev_dbg(dev, "%s: system resume\n", __func__);
  1912. return 0;
  1913. }
  1914. #endif /* CONFIG_PM_SLEEP */
  1915. static const struct dev_pm_ops wsa884x_swr_pm_ops = {
  1916. .suspend_late = wsa884x_swr_suspend,
  1917. .resume_early = wsa884x_swr_resume,
  1918. };
  1919. static const struct swr_device_id wsa884x_swr_id[] = {
  1920. {"wsa884x", 0},
  1921. {"wsa884x_2", 0},
  1922. {}
  1923. };
  1924. static const struct of_device_id wsa884x_swr_dt_match[] = {
  1925. {
  1926. .compatible = "qcom,wsa884x",
  1927. },
  1928. {
  1929. .compatible = "qcom,wsa884x_2",
  1930. },
  1931. {}
  1932. };
  1933. static struct swr_driver wsa884x_swr_driver = {
  1934. .driver = {
  1935. .name = "wsa884x",
  1936. .owner = THIS_MODULE,
  1937. .pm = &wsa884x_swr_pm_ops,
  1938. .of_match_table = wsa884x_swr_dt_match,
  1939. },
  1940. .probe = wsa884x_swr_probe,
  1941. .remove = wsa884x_swr_remove,
  1942. .id_table = wsa884x_swr_id,
  1943. };
  1944. static int __init wsa884x_swr_init(void)
  1945. {
  1946. return swr_driver_register(&wsa884x_swr_driver);
  1947. }
  1948. static void __exit wsa884x_swr_exit(void)
  1949. {
  1950. swr_driver_unregister(&wsa884x_swr_driver);
  1951. }
  1952. module_init(wsa884x_swr_init);
  1953. module_exit(wsa884x_swr_exit);
  1954. MODULE_DESCRIPTION("WSA884x codec driver");
  1955. MODULE_LICENSE("GPL v2");