wcd938x.c 136 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <bindings/audio-codec-port-types.h>
  22. #include <linux/qti-regmap-debugfs.h>
  23. #include "wcd938x-registers.h"
  24. #include "wcd938x.h"
  25. #include "internal.h"
  26. #include "asoc/bolero-slave-internal.h"
  27. #define NUM_SWRS_DT_PARAMS 5
  28. #define WCD938X_VARIANT_ENTRY_SIZE 32
  29. #define WCD938X_VERSION_1_0 1
  30. #define WCD938X_VERSION_ENTRY_SIZE 32
  31. #define EAR_RX_PATH_AUX 1
  32. #define ADC_MODE_VAL_HIFI 0x01
  33. #define ADC_MODE_VAL_LO_HIF 0x02
  34. #define ADC_MODE_VAL_NORMAL 0x03
  35. #define ADC_MODE_VAL_LP 0x05
  36. #define ADC_MODE_VAL_ULP1 0x09
  37. #define ADC_MODE_VAL_ULP2 0x0B
  38. #define NUM_ATTEMPTS 5
  39. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  40. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  41. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  42. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  43. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  44. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  45. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  46. SNDRV_PCM_RATE_384000)
  47. /* Fractional Rates */
  48. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  49. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  50. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  51. SNDRV_PCM_FMTBIT_S24_LE |\
  52. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  53. enum {
  54. CODEC_TX = 0,
  55. CODEC_RX,
  56. };
  57. enum {
  58. WCD_ADC1 = 0,
  59. WCD_ADC2,
  60. WCD_ADC3,
  61. WCD_ADC4,
  62. ALLOW_BUCK_DISABLE,
  63. HPH_COMP_DELAY,
  64. HPH_PA_DELAY,
  65. AMIC2_BCS_ENABLE,
  66. WCD_SUPPLIES_LPM_MODE,
  67. WCD_ADC1_MODE,
  68. WCD_ADC2_MODE,
  69. WCD_ADC3_MODE,
  70. WCD_ADC4_MODE,
  71. };
  72. enum {
  73. ADC_MODE_INVALID = 0,
  74. ADC_MODE_HIFI,
  75. ADC_MODE_LO_HIF,
  76. ADC_MODE_NORMAL,
  77. ADC_MODE_LP,
  78. ADC_MODE_ULP1,
  79. ADC_MODE_ULP2,
  80. };
  81. static u8 tx_mode_bit[] = {
  82. [ADC_MODE_INVALID] = 0x00,
  83. [ADC_MODE_HIFI] = 0x01,
  84. [ADC_MODE_LO_HIF] = 0x02,
  85. [ADC_MODE_NORMAL] = 0x04,
  86. [ADC_MODE_LP] = 0x08,
  87. [ADC_MODE_ULP1] = 0x10,
  88. [ADC_MODE_ULP2] = 0x20,
  89. };
  90. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  91. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  92. static int wcd938x_handle_post_irq(void *data);
  93. static int wcd938x_reset(struct device *dev);
  94. static int wcd938x_reset_low(struct device *dev);
  95. static int wcd938x_get_adc_mode(int val);
  96. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  97. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  98. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  109. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  110. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  111. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  112. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  113. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  114. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  115. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  116. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  117. };
  118. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  119. .name = "wcd938x",
  120. .irqs = wcd938x_irqs,
  121. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  122. .num_regs = 3,
  123. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  124. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  125. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  126. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  127. .use_ack = 1,
  128. .runtime_pm = false,
  129. .handle_post_irq = wcd938x_handle_post_irq,
  130. .irq_drv_data = NULL,
  131. };
  132. static int wcd938x_handle_post_irq(void *data)
  133. {
  134. struct wcd938x_priv *wcd938x = data;
  135. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  136. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  137. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  138. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  139. wcd938x->tx_swr_dev->slave_irq_pending =
  140. ((sts1 || sts2 || sts3) ? true : false);
  141. return IRQ_HANDLED;
  142. }
  143. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  144. {
  145. int ret = 0;
  146. int bank = 0;
  147. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  148. if (ret)
  149. return -EINVAL;
  150. return ((bank & 0x40) ? 1: 0);
  151. }
  152. static int wcd938x_get_clk_rate(int mode)
  153. {
  154. int rate;
  155. switch (mode) {
  156. case ADC_MODE_ULP2:
  157. rate = SWR_CLK_RATE_0P6MHZ;
  158. break;
  159. case ADC_MODE_ULP1:
  160. rate = SWR_CLK_RATE_1P2MHZ;
  161. break;
  162. case ADC_MODE_LP:
  163. rate = SWR_CLK_RATE_4P8MHZ;
  164. break;
  165. case ADC_MODE_NORMAL:
  166. case ADC_MODE_LO_HIF:
  167. case ADC_MODE_HIFI:
  168. case ADC_MODE_INVALID:
  169. default:
  170. rate = SWR_CLK_RATE_9P6MHZ;
  171. break;
  172. }
  173. return rate;
  174. }
  175. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  176. int rate, int bank)
  177. {
  178. u8 mask = (bank ? 0xF0 : 0x0F);
  179. u8 val = 0;
  180. switch (rate) {
  181. case SWR_CLK_RATE_0P6MHZ:
  182. val = (bank ? 0x60 : 0x06);
  183. break;
  184. case SWR_CLK_RATE_1P2MHZ:
  185. val = (bank ? 0x50 : 0x05);
  186. break;
  187. case SWR_CLK_RATE_2P4MHZ:
  188. val = (bank ? 0x30 : 0x03);
  189. break;
  190. case SWR_CLK_RATE_4P8MHZ:
  191. val = (bank ? 0x10 : 0x01);
  192. break;
  193. case SWR_CLK_RATE_9P6MHZ:
  194. default:
  195. val = 0x00;
  196. break;
  197. }
  198. snd_soc_component_update_bits(component,
  199. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  200. mask, val);
  201. return 0;
  202. }
  203. static int wcd938x_init_reg(struct snd_soc_component *component)
  204. {
  205. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  206. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  207. /* 1 msec delay as per HW requirement */
  208. usleep_range(1000, 1010);
  209. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  210. /* 1 msec delay as per HW requirement */
  211. usleep_range(1000, 1010);
  212. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  213. 0x10, 0x00);
  214. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  215. 0xF0, 0x80);
  216. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  217. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  218. /* 10 msec delay as per HW requirement */
  219. usleep_range(10000, 10010);
  220. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  221. snd_soc_component_update_bits(component,
  222. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  223. 0xF0, 0x00);
  224. snd_soc_component_update_bits(component,
  225. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  226. 0x1F, 0x15);
  227. snd_soc_component_update_bits(component,
  228. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  229. 0x1F, 0x15);
  230. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  231. 0xC0, 0x80);
  232. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  233. 0x02, 0x02);
  234. snd_soc_component_update_bits(component,
  235. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  236. 0xFF, 0x14);
  237. snd_soc_component_update_bits(component,
  238. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  239. 0x1F, 0x08);
  240. snd_soc_component_update_bits(component,
  241. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  242. snd_soc_component_update_bits(component,
  243. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  244. snd_soc_component_update_bits(component,
  245. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  246. snd_soc_component_update_bits(component,
  247. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  248. snd_soc_component_update_bits(component,
  249. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  250. snd_soc_component_update_bits(component,
  251. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  252. snd_soc_component_update_bits(component,
  253. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  254. snd_soc_component_update_bits(component,
  255. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  256. snd_soc_component_update_bits(component,
  257. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  258. snd_soc_component_update_bits(component,
  259. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  260. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E,
  261. ((snd_soc_component_read(component,
  262. WCD938X_DIGITAL_EFUSE_REG_30) & 0x07) << 1));
  263. snd_soc_component_update_bits(component,
  264. WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
  265. return 0;
  266. }
  267. static int wcd938x_set_port_params(struct snd_soc_component *component,
  268. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  269. u8 *ch_mask, u32 *ch_rate,
  270. u8 *port_type, u8 path)
  271. {
  272. int i, j;
  273. u8 num_ports = 0;
  274. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  275. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  276. switch (path) {
  277. case CODEC_RX:
  278. map = &wcd938x->rx_port_mapping;
  279. num_ports = wcd938x->num_rx_ports;
  280. break;
  281. case CODEC_TX:
  282. map = &wcd938x->tx_port_mapping;
  283. num_ports = wcd938x->num_tx_ports;
  284. break;
  285. default:
  286. dev_err(component->dev, "%s Invalid path selected %u\n",
  287. __func__, path);
  288. return -EINVAL;
  289. }
  290. for (i = 0; i <= num_ports; i++) {
  291. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  292. if ((*map)[i][j].slave_port_type == slv_prt_type)
  293. goto found;
  294. }
  295. }
  296. found:
  297. if (i > num_ports || j == MAX_CH_PER_PORT) {
  298. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  299. __func__, slv_prt_type);
  300. return -EINVAL;
  301. }
  302. *port_id = i;
  303. *num_ch = (*map)[i][j].num_ch;
  304. *ch_mask = (*map)[i][j].ch_mask;
  305. *ch_rate = (*map)[i][j].ch_rate;
  306. *port_type = (*map)[i][j].master_port_type;
  307. return 0;
  308. }
  309. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  310. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  311. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  312. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  313. static int wcd938x_parse_port_params(struct device *dev,
  314. char *prop, u8 path)
  315. {
  316. u32 *dt_array, map_size, max_uc;
  317. int ret = 0;
  318. u32 cnt = 0;
  319. u32 i, j;
  320. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  321. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  322. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  323. switch (path) {
  324. case CODEC_TX:
  325. map = &wcd938x->tx_port_params;
  326. map_uc = &wcd938x->swr_tx_port_params;
  327. break;
  328. default:
  329. ret = -EINVAL;
  330. goto err_port_map;
  331. }
  332. if (!of_find_property(dev->of_node, prop,
  333. &map_size)) {
  334. dev_err(dev, "missing port mapping prop %s\n", prop);
  335. ret = -EINVAL;
  336. goto err_port_map;
  337. }
  338. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  339. if (max_uc != SWR_UC_MAX) {
  340. dev_err(dev, "%s: port params not provided for all usecases\n",
  341. __func__);
  342. ret = -EINVAL;
  343. goto err_port_map;
  344. }
  345. dt_array = kzalloc(map_size, GFP_KERNEL);
  346. if (!dt_array) {
  347. ret = -ENOMEM;
  348. goto err_alloc;
  349. }
  350. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  351. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  352. if (ret) {
  353. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  354. __func__, prop);
  355. goto err_pdata_fail;
  356. }
  357. for (i = 0; i < max_uc; i++) {
  358. for (j = 0; j < SWR_NUM_PORTS; j++) {
  359. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  360. (*map)[i][j].offset1 = dt_array[cnt];
  361. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  362. }
  363. (*map_uc)[i].pp = &(*map)[i][0];
  364. }
  365. kfree(dt_array);
  366. return 0;
  367. err_pdata_fail:
  368. kfree(dt_array);
  369. err_alloc:
  370. err_port_map:
  371. return ret;
  372. }
  373. static int wcd938x_parse_port_mapping(struct device *dev,
  374. char *prop, u8 path)
  375. {
  376. u32 *dt_array, map_size, map_length;
  377. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  378. u32 slave_port_type, master_port_type;
  379. u32 i, ch_iter = 0;
  380. int ret = 0;
  381. u8 *num_ports = NULL;
  382. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  383. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  384. switch (path) {
  385. case CODEC_RX:
  386. map = &wcd938x->rx_port_mapping;
  387. num_ports = &wcd938x->num_rx_ports;
  388. break;
  389. case CODEC_TX:
  390. map = &wcd938x->tx_port_mapping;
  391. num_ports = &wcd938x->num_tx_ports;
  392. break;
  393. default:
  394. dev_err(dev, "%s Invalid path selected %u\n",
  395. __func__, path);
  396. return -EINVAL;
  397. }
  398. if (!of_find_property(dev->of_node, prop,
  399. &map_size)) {
  400. dev_err(dev, "missing port mapping prop %s\n", prop);
  401. ret = -EINVAL;
  402. goto err_port_map;
  403. }
  404. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  405. dt_array = kzalloc(map_size, GFP_KERNEL);
  406. if (!dt_array) {
  407. ret = -ENOMEM;
  408. goto err_alloc;
  409. }
  410. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  411. NUM_SWRS_DT_PARAMS * map_length);
  412. if (ret) {
  413. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  414. __func__, prop);
  415. goto err_pdata_fail;
  416. }
  417. for (i = 0; i < map_length; i++) {
  418. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  419. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  420. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  421. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  422. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  423. if (port_num != old_port_num)
  424. ch_iter = 0;
  425. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  426. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  427. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  428. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  429. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  430. old_port_num = port_num;
  431. }
  432. *num_ports = port_num;
  433. kfree(dt_array);
  434. return 0;
  435. err_pdata_fail:
  436. kfree(dt_array);
  437. err_alloc:
  438. err_port_map:
  439. return ret;
  440. }
  441. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  442. u8 slv_port_type, int clk_rate,
  443. u8 enable)
  444. {
  445. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  446. u8 port_id, num_ch, ch_mask;
  447. u8 ch_type = 0;
  448. u32 ch_rate;
  449. int slave_ch_idx;
  450. u8 num_port = 1;
  451. int ret = 0;
  452. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  453. &num_ch, &ch_mask, &ch_rate,
  454. &ch_type, CODEC_TX);
  455. if (ret)
  456. return ret;
  457. if (clk_rate)
  458. ch_rate = clk_rate;
  459. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  460. if (slave_ch_idx != -EINVAL)
  461. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  462. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  463. __func__, slave_ch_idx, ch_type);
  464. if (enable)
  465. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  466. num_port, &ch_mask, &ch_rate,
  467. &num_ch, &ch_type);
  468. else
  469. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  470. num_port, &ch_mask, &ch_type);
  471. return ret;
  472. }
  473. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  474. u8 slv_port_type, u8 enable)
  475. {
  476. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  477. u8 port_id, num_ch, ch_mask, port_type;
  478. u32 ch_rate;
  479. u8 num_port = 1;
  480. int ret = 0;
  481. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  482. &num_ch, &ch_mask, &ch_rate,
  483. &port_type, CODEC_RX);
  484. if (ret)
  485. return ret;
  486. if (enable)
  487. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  488. num_port, &ch_mask, &ch_rate,
  489. &num_ch, &port_type);
  490. else
  491. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  492. num_port, &ch_mask, &port_type);
  493. return ret;
  494. }
  495. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  496. {
  497. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  498. if (wcd938x->rx_clk_cnt == 0) {
  499. snd_soc_component_update_bits(component,
  500. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  501. snd_soc_component_update_bits(component,
  502. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  503. snd_soc_component_update_bits(component,
  504. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  505. snd_soc_component_update_bits(component,
  506. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  507. snd_soc_component_update_bits(component,
  508. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  509. snd_soc_component_update_bits(component,
  510. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  511. snd_soc_component_update_bits(component,
  512. WCD938X_AUX_AUXPA, 0x10, 0x10);
  513. }
  514. wcd938x->rx_clk_cnt++;
  515. return 0;
  516. }
  517. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  518. {
  519. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  520. wcd938x->rx_clk_cnt--;
  521. if (wcd938x->rx_clk_cnt == 0) {
  522. snd_soc_component_update_bits(component,
  523. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  524. snd_soc_component_update_bits(component,
  525. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  526. snd_soc_component_update_bits(component,
  527. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  528. snd_soc_component_update_bits(component,
  529. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  530. snd_soc_component_update_bits(component,
  531. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  532. }
  533. return 0;
  534. }
  535. /*
  536. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  537. * @component: handle to snd_soc_component *
  538. *
  539. * return wcd938x_mbhc handle or error code in case of failure
  540. */
  541. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  542. {
  543. struct wcd938x_priv *wcd938x;
  544. if (!component) {
  545. pr_err("%s: Invalid params, NULL component\n", __func__);
  546. return NULL;
  547. }
  548. wcd938x = snd_soc_component_get_drvdata(component);
  549. if (!wcd938x) {
  550. pr_err("%s: wcd938x is NULL\n", __func__);
  551. return NULL;
  552. }
  553. return wcd938x->mbhc;
  554. }
  555. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  556. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  557. struct snd_kcontrol *kcontrol,
  558. int event)
  559. {
  560. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  561. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  562. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  563. w->name, event);
  564. switch (event) {
  565. case SND_SOC_DAPM_PRE_PMU:
  566. wcd938x_rx_clk_enable(component);
  567. snd_soc_component_update_bits(component,
  568. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  569. snd_soc_component_update_bits(component,
  570. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  571. snd_soc_component_update_bits(component,
  572. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  573. break;
  574. case SND_SOC_DAPM_POST_PMU:
  575. snd_soc_component_update_bits(component,
  576. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  577. if (wcd938x->comp1_enable) {
  578. snd_soc_component_update_bits(component,
  579. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  580. /* 5msec compander delay as per HW requirement */
  581. if (!wcd938x->comp2_enable ||
  582. (snd_soc_component_read(component,
  583. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  584. usleep_range(5000, 5010);
  585. snd_soc_component_update_bits(component,
  586. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  587. } else {
  588. snd_soc_component_update_bits(component,
  589. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  590. 0x02, 0x00);
  591. snd_soc_component_update_bits(component,
  592. WCD938X_HPH_L_EN, 0x20, 0x20);
  593. }
  594. break;
  595. case SND_SOC_DAPM_POST_PMD:
  596. snd_soc_component_update_bits(component,
  597. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  598. 0x0F, 0x01);
  599. break;
  600. }
  601. return 0;
  602. }
  603. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  604. struct snd_kcontrol *kcontrol,
  605. int event)
  606. {
  607. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  608. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  609. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  610. w->name, event);
  611. switch (event) {
  612. case SND_SOC_DAPM_PRE_PMU:
  613. wcd938x_rx_clk_enable(component);
  614. snd_soc_component_update_bits(component,
  615. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  616. snd_soc_component_update_bits(component,
  617. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  618. snd_soc_component_update_bits(component,
  619. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  620. break;
  621. case SND_SOC_DAPM_POST_PMU:
  622. snd_soc_component_update_bits(component,
  623. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  624. if (wcd938x->comp2_enable) {
  625. snd_soc_component_update_bits(component,
  626. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  627. /* 5msec compander delay as per HW requirement */
  628. if (!wcd938x->comp1_enable ||
  629. (snd_soc_component_read(component,
  630. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  631. usleep_range(5000, 5010);
  632. snd_soc_component_update_bits(component,
  633. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  634. } else {
  635. snd_soc_component_update_bits(component,
  636. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  637. 0x01, 0x00);
  638. snd_soc_component_update_bits(component,
  639. WCD938X_HPH_R_EN, 0x20, 0x20);
  640. }
  641. break;
  642. case SND_SOC_DAPM_POST_PMD:
  643. snd_soc_component_update_bits(component,
  644. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  645. 0x0F, 0x01);
  646. break;
  647. }
  648. return 0;
  649. }
  650. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  651. struct snd_kcontrol *kcontrol,
  652. int event)
  653. {
  654. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  655. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  656. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  657. w->name, event);
  658. switch (event) {
  659. case SND_SOC_DAPM_PRE_PMU:
  660. wcd938x_rx_clk_enable(component);
  661. wcd938x->ear_rx_path =
  662. snd_soc_component_read(
  663. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  664. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  665. snd_soc_component_update_bits(component,
  666. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  667. snd_soc_component_update_bits(component,
  668. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  669. snd_soc_component_update_bits(component,
  670. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  671. snd_soc_component_update_bits(component,
  672. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  673. } else {
  674. snd_soc_component_update_bits(component,
  675. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  676. snd_soc_component_update_bits(component,
  677. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  678. if (wcd938x->comp1_enable)
  679. snd_soc_component_update_bits(component,
  680. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  681. 0x02, 0x02);
  682. }
  683. /* 5 msec delay as per HW requirement */
  684. usleep_range(5000, 5010);
  685. if (wcd938x->flyback_cur_det_disable == 0)
  686. snd_soc_component_update_bits(component,
  687. WCD938X_FLYBACK_EN,
  688. 0x04, 0x00);
  689. wcd938x->flyback_cur_det_disable++;
  690. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  691. WCD_CLSH_EVENT_PRE_DAC,
  692. WCD_CLSH_STATE_EAR,
  693. wcd938x->hph_mode);
  694. break;
  695. case SND_SOC_DAPM_POST_PMD:
  696. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  697. snd_soc_component_update_bits(component,
  698. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  699. snd_soc_component_update_bits(component,
  700. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  701. } else {
  702. snd_soc_component_update_bits(component,
  703. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  704. snd_soc_component_update_bits(component,
  705. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  706. if (wcd938x->comp1_enable)
  707. snd_soc_component_update_bits(component,
  708. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  709. 0x02, 0x00);
  710. }
  711. snd_soc_component_update_bits(component,
  712. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  713. snd_soc_component_update_bits(component,
  714. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  715. break;
  716. };
  717. return 0;
  718. }
  719. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  720. struct snd_kcontrol *kcontrol,
  721. int event)
  722. {
  723. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  724. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  725. int ret = 0;
  726. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  727. w->name, event);
  728. switch (event) {
  729. case SND_SOC_DAPM_PRE_PMU:
  730. wcd938x_rx_clk_enable(component);
  731. snd_soc_component_update_bits(component,
  732. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  733. snd_soc_component_update_bits(component,
  734. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  735. snd_soc_component_update_bits(component,
  736. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  737. if (wcd938x->flyback_cur_det_disable == 0)
  738. snd_soc_component_update_bits(component,
  739. WCD938X_FLYBACK_EN,
  740. 0x04, 0x00);
  741. wcd938x->flyback_cur_det_disable++;
  742. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  743. WCD_CLSH_EVENT_PRE_DAC,
  744. WCD_CLSH_STATE_AUX,
  745. wcd938x->hph_mode);
  746. break;
  747. case SND_SOC_DAPM_POST_PMD:
  748. snd_soc_component_update_bits(component,
  749. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  750. break;
  751. };
  752. return ret;
  753. }
  754. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  755. struct snd_kcontrol *kcontrol,
  756. int event)
  757. {
  758. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  759. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  760. int ret = 0;
  761. int hph_mode = wcd938x->hph_mode;
  762. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  763. w->name, event);
  764. switch (event) {
  765. case SND_SOC_DAPM_PRE_PMU:
  766. if (wcd938x->ldoh)
  767. snd_soc_component_update_bits(component,
  768. WCD938X_LDOH_MODE,
  769. 0x80, 0x80);
  770. if (wcd938x->update_wcd_event)
  771. wcd938x->update_wcd_event(wcd938x->handle,
  772. SLV_BOLERO_EVT_RX_MUTE,
  773. (WCD_RX2 << 0x10 | 0x1));
  774. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  775. wcd938x->rx_swr_dev->dev_num,
  776. true);
  777. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  778. WCD_CLSH_EVENT_PRE_DAC,
  779. WCD_CLSH_STATE_HPHR,
  780. hph_mode);
  781. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  782. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  783. hph_mode == CLS_H_ULP) {
  784. snd_soc_component_update_bits(component,
  785. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  786. }
  787. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  788. 0x10, 0x10);
  789. wcd_clsh_set_hph_mode(component, hph_mode);
  790. /* 100 usec delay as per HW requirement */
  791. usleep_range(100, 110);
  792. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  793. snd_soc_component_update_bits(component,
  794. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x03);
  795. break;
  796. case SND_SOC_DAPM_POST_PMU:
  797. /*
  798. * 7ms sleep is required if compander is enabled as per
  799. * HW requirement. If compander is disabled, then
  800. * 20ms delay is required.
  801. */
  802. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  803. if (!wcd938x->comp2_enable)
  804. usleep_range(20000, 20100);
  805. else
  806. usleep_range(7000, 7100);
  807. if (hph_mode == CLS_H_LP ||
  808. hph_mode == CLS_H_LOHIFI ||
  809. hph_mode == CLS_H_ULP)
  810. snd_soc_component_update_bits(component,
  811. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  812. 0x00);
  813. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  814. }
  815. snd_soc_component_update_bits(component,
  816. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  817. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  818. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  819. snd_soc_component_update_bits(component,
  820. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  821. if (wcd938x->update_wcd_event)
  822. wcd938x->update_wcd_event(wcd938x->handle,
  823. SLV_BOLERO_EVT_RX_MUTE,
  824. (WCD_RX2 << 0x10));
  825. wcd_enable_irq(&wcd938x->irq_info,
  826. WCD938X_IRQ_HPHR_PDM_WD_INT);
  827. break;
  828. case SND_SOC_DAPM_PRE_PMD:
  829. if (wcd938x->update_wcd_event)
  830. wcd938x->update_wcd_event(wcd938x->handle,
  831. SLV_BOLERO_EVT_RX_MUTE,
  832. (WCD_RX2 << 0x10 | 0x1));
  833. wcd_disable_irq(&wcd938x->irq_info,
  834. WCD938X_IRQ_HPHR_PDM_WD_INT);
  835. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  836. wcd938x->update_wcd_event(wcd938x->handle,
  837. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  838. (WCD_RX2 << 0x10));
  839. /*
  840. * 7ms sleep is required if compander is enabled as per
  841. * HW requirement. If compander is disabled, then
  842. * 20ms delay is required.
  843. */
  844. if (!wcd938x->comp2_enable)
  845. usleep_range(20000, 20100);
  846. else
  847. usleep_range(7000, 7100);
  848. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  849. 0x40, 0x00);
  850. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  851. WCD_EVENT_PRE_HPHR_PA_OFF,
  852. &wcd938x->mbhc->wcd_mbhc);
  853. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  854. break;
  855. case SND_SOC_DAPM_POST_PMD:
  856. /*
  857. * 7ms sleep is required if compander is enabled as per
  858. * HW requirement. If compander is disabled, then
  859. * 20ms delay is required.
  860. */
  861. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  862. if (!wcd938x->comp2_enable)
  863. usleep_range(20000, 20100);
  864. else
  865. usleep_range(7000, 7100);
  866. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  867. }
  868. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  869. WCD_EVENT_POST_HPHR_PA_OFF,
  870. &wcd938x->mbhc->wcd_mbhc);
  871. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  872. 0x10, 0x00);
  873. snd_soc_component_update_bits(component,
  874. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
  875. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  876. WCD_CLSH_EVENT_POST_PA,
  877. WCD_CLSH_STATE_HPHR,
  878. hph_mode);
  879. if (wcd938x->ldoh)
  880. snd_soc_component_update_bits(component,
  881. WCD938X_LDOH_MODE,
  882. 0x80, 0x00);
  883. break;
  884. };
  885. return ret;
  886. }
  887. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  888. struct snd_kcontrol *kcontrol,
  889. int event)
  890. {
  891. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  892. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  893. int ret = 0;
  894. int hph_mode = wcd938x->hph_mode;
  895. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  896. w->name, event);
  897. switch (event) {
  898. case SND_SOC_DAPM_PRE_PMU:
  899. if (wcd938x->ldoh)
  900. snd_soc_component_update_bits(component,
  901. WCD938X_LDOH_MODE,
  902. 0x80, 0x80);
  903. if (wcd938x->update_wcd_event)
  904. wcd938x->update_wcd_event(wcd938x->handle,
  905. SLV_BOLERO_EVT_RX_MUTE,
  906. (WCD_RX1 << 0x10 | 0x01));
  907. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  908. wcd938x->rx_swr_dev->dev_num,
  909. true);
  910. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  911. WCD_CLSH_EVENT_PRE_DAC,
  912. WCD_CLSH_STATE_HPHL,
  913. hph_mode);
  914. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  915. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  916. hph_mode == CLS_H_ULP) {
  917. snd_soc_component_update_bits(component,
  918. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  919. }
  920. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  921. 0x20, 0x20);
  922. wcd_clsh_set_hph_mode(component, hph_mode);
  923. /* 100 usec delay as per HW requirement */
  924. usleep_range(100, 110);
  925. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  926. snd_soc_component_update_bits(component,
  927. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
  928. break;
  929. case SND_SOC_DAPM_POST_PMU:
  930. /*
  931. * 7ms sleep is required if compander is enabled as per
  932. * HW requirement. If compander is disabled, then
  933. * 20ms delay is required.
  934. */
  935. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  936. if (!wcd938x->comp1_enable)
  937. usleep_range(20000, 20100);
  938. else
  939. usleep_range(7000, 7100);
  940. if (hph_mode == CLS_H_LP ||
  941. hph_mode == CLS_H_LOHIFI ||
  942. hph_mode == CLS_H_ULP)
  943. snd_soc_component_update_bits(component,
  944. WCD938X_HPH_REFBUFF_LP_CTL,
  945. 0x01, 0x00);
  946. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  947. }
  948. snd_soc_component_update_bits(component,
  949. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  950. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  951. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  952. snd_soc_component_update_bits(component,
  953. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  954. if (wcd938x->update_wcd_event)
  955. wcd938x->update_wcd_event(wcd938x->handle,
  956. SLV_BOLERO_EVT_RX_MUTE,
  957. (WCD_RX1 << 0x10));
  958. wcd_enable_irq(&wcd938x->irq_info,
  959. WCD938X_IRQ_HPHL_PDM_WD_INT);
  960. break;
  961. case SND_SOC_DAPM_PRE_PMD:
  962. if (wcd938x->update_wcd_event)
  963. wcd938x->update_wcd_event(wcd938x->handle,
  964. SLV_BOLERO_EVT_RX_MUTE,
  965. (WCD_RX1 << 0x10 | 0x1));
  966. wcd_disable_irq(&wcd938x->irq_info,
  967. WCD938X_IRQ_HPHL_PDM_WD_INT);
  968. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  969. wcd938x->update_wcd_event(wcd938x->handle,
  970. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  971. (WCD_RX1 << 0x10));
  972. /*
  973. * 7ms sleep is required if compander is enabled as per
  974. * HW requirement. If compander is disabled, then
  975. * 20ms delay is required.
  976. */
  977. if (!wcd938x->comp1_enable)
  978. usleep_range(20000, 20100);
  979. else
  980. usleep_range(7000, 7100);
  981. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  982. 0x80, 0x00);
  983. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  984. WCD_EVENT_PRE_HPHL_PA_OFF,
  985. &wcd938x->mbhc->wcd_mbhc);
  986. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  987. break;
  988. case SND_SOC_DAPM_POST_PMD:
  989. /*
  990. * 7ms sleep is required if compander is enabled as per
  991. * HW requirement. If compander is disabled, then
  992. * 20ms delay is required.
  993. */
  994. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  995. if (!wcd938x->comp1_enable)
  996. usleep_range(21000, 21100);
  997. else
  998. usleep_range(7000, 7100);
  999. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  1000. }
  1001. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1002. WCD_EVENT_POST_HPHL_PA_OFF,
  1003. &wcd938x->mbhc->wcd_mbhc);
  1004. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1005. 0x20, 0x00);
  1006. snd_soc_component_update_bits(component,
  1007. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
  1008. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1009. WCD_CLSH_EVENT_POST_PA,
  1010. WCD_CLSH_STATE_HPHL,
  1011. hph_mode);
  1012. if (wcd938x->ldoh)
  1013. snd_soc_component_update_bits(component,
  1014. WCD938X_LDOH_MODE,
  1015. 0x80, 0x00);
  1016. break;
  1017. };
  1018. return ret;
  1019. }
  1020. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1021. struct snd_kcontrol *kcontrol,
  1022. int event)
  1023. {
  1024. struct snd_soc_component *component =
  1025. snd_soc_dapm_to_component(w->dapm);
  1026. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1027. int hph_mode = wcd938x->hph_mode;
  1028. int ret = 0;
  1029. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1030. w->name, event);
  1031. switch (event) {
  1032. case SND_SOC_DAPM_PRE_PMU:
  1033. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1034. wcd938x->rx_swr_dev->dev_num,
  1035. true);
  1036. snd_soc_component_update_bits(component,
  1037. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x01);
  1038. break;
  1039. case SND_SOC_DAPM_POST_PMU:
  1040. /* 1 msec delay as per HW requirement */
  1041. usleep_range(1000, 1010);
  1042. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1043. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1044. snd_soc_component_update_bits(component,
  1045. WCD938X_ANA_RX_SUPPLIES,
  1046. 0x02, 0x02);
  1047. if (wcd938x->update_wcd_event)
  1048. wcd938x->update_wcd_event(wcd938x->handle,
  1049. SLV_BOLERO_EVT_RX_MUTE,
  1050. (WCD_RX3 << 0x10));
  1051. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  1052. break;
  1053. case SND_SOC_DAPM_PRE_PMD:
  1054. wcd_disable_irq(&wcd938x->irq_info,
  1055. WCD938X_IRQ_AUX_PDM_WD_INT);
  1056. if (wcd938x->update_wcd_event)
  1057. wcd938x->update_wcd_event(wcd938x->handle,
  1058. SLV_BOLERO_EVT_RX_MUTE,
  1059. (WCD_RX3 << 0x10 | 0x1));
  1060. break;
  1061. case SND_SOC_DAPM_POST_PMD:
  1062. /* 1 msec delay as per HW requirement */
  1063. usleep_range(1000, 1010);
  1064. snd_soc_component_update_bits(component,
  1065. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x00);
  1066. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1067. WCD_CLSH_EVENT_POST_PA,
  1068. WCD_CLSH_STATE_AUX,
  1069. hph_mode);
  1070. wcd938x->flyback_cur_det_disable--;
  1071. if (wcd938x->flyback_cur_det_disable == 0)
  1072. snd_soc_component_update_bits(component,
  1073. WCD938X_FLYBACK_EN,
  1074. 0x04, 0x04);
  1075. break;
  1076. };
  1077. return ret;
  1078. }
  1079. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1080. struct snd_kcontrol *kcontrol,
  1081. int event)
  1082. {
  1083. struct snd_soc_component *component =
  1084. snd_soc_dapm_to_component(w->dapm);
  1085. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1086. int hph_mode = wcd938x->hph_mode;
  1087. int ret = 0;
  1088. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1089. w->name, event);
  1090. switch (event) {
  1091. case SND_SOC_DAPM_PRE_PMU:
  1092. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1093. wcd938x->rx_swr_dev->dev_num,
  1094. true);
  1095. /*
  1096. * Enable watchdog interrupt for HPHL or AUX
  1097. * depending on mux value
  1098. */
  1099. wcd938x->ear_rx_path =
  1100. snd_soc_component_read(
  1101. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1102. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1103. snd_soc_component_update_bits(component,
  1104. WCD938X_DIGITAL_PDM_WD_CTL2,
  1105. 0x01, 0x01);
  1106. else
  1107. snd_soc_component_update_bits(component,
  1108. WCD938X_DIGITAL_PDM_WD_CTL0,
  1109. 0x07, 0x03);
  1110. if (!wcd938x->comp1_enable)
  1111. snd_soc_component_update_bits(component,
  1112. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1113. break;
  1114. case SND_SOC_DAPM_POST_PMU:
  1115. /* 6 msec delay as per HW requirement */
  1116. usleep_range(6000, 6010);
  1117. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1118. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1119. snd_soc_component_update_bits(component,
  1120. WCD938X_ANA_RX_SUPPLIES,
  1121. 0x02, 0x02);
  1122. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1123. if (wcd938x->update_wcd_event)
  1124. wcd938x->update_wcd_event(wcd938x->handle,
  1125. SLV_BOLERO_EVT_RX_MUTE,
  1126. (WCD_RX3 << 0x10));
  1127. wcd_enable_irq(&wcd938x->irq_info,
  1128. WCD938X_IRQ_AUX_PDM_WD_INT);
  1129. } else {
  1130. if (wcd938x->update_wcd_event)
  1131. wcd938x->update_wcd_event(wcd938x->handle,
  1132. SLV_BOLERO_EVT_RX_MUTE,
  1133. (WCD_RX1 << 0x10));
  1134. wcd_enable_irq(&wcd938x->irq_info,
  1135. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1136. }
  1137. break;
  1138. case SND_SOC_DAPM_PRE_PMD:
  1139. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1140. wcd_disable_irq(&wcd938x->irq_info,
  1141. WCD938X_IRQ_AUX_PDM_WD_INT);
  1142. if (wcd938x->update_wcd_event)
  1143. wcd938x->update_wcd_event(wcd938x->handle,
  1144. SLV_BOLERO_EVT_RX_MUTE,
  1145. (WCD_RX3 << 0x10 | 0x1));
  1146. } else {
  1147. wcd_disable_irq(&wcd938x->irq_info,
  1148. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1149. if (wcd938x->update_wcd_event)
  1150. wcd938x->update_wcd_event(wcd938x->handle,
  1151. SLV_BOLERO_EVT_RX_MUTE,
  1152. (WCD_RX1 << 0x10 | 0x1));
  1153. }
  1154. break;
  1155. case SND_SOC_DAPM_POST_PMD:
  1156. if (!wcd938x->comp1_enable)
  1157. snd_soc_component_update_bits(component,
  1158. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1159. /* 7 msec delay as per HW requirement */
  1160. usleep_range(7000, 7010);
  1161. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1162. snd_soc_component_update_bits(component,
  1163. WCD938X_DIGITAL_PDM_WD_CTL2,
  1164. 0x01, 0x00);
  1165. else
  1166. snd_soc_component_update_bits(component,
  1167. WCD938X_DIGITAL_PDM_WD_CTL0,
  1168. 0x07, 0x00);
  1169. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1170. WCD_CLSH_EVENT_POST_PA,
  1171. WCD_CLSH_STATE_EAR,
  1172. hph_mode);
  1173. wcd938x->flyback_cur_det_disable--;
  1174. if (wcd938x->flyback_cur_det_disable == 0)
  1175. snd_soc_component_update_bits(component,
  1176. WCD938X_FLYBACK_EN,
  1177. 0x04, 0x04);
  1178. break;
  1179. };
  1180. return ret;
  1181. }
  1182. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1183. struct snd_kcontrol *kcontrol,
  1184. int event)
  1185. {
  1186. struct snd_soc_component *component =
  1187. snd_soc_dapm_to_component(w->dapm);
  1188. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1189. int mode = wcd938x->hph_mode;
  1190. int ret = 0;
  1191. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1192. w->name, event);
  1193. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1194. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1195. wcd938x_rx_connect_port(component, CLSH,
  1196. SND_SOC_DAPM_EVENT_ON(event));
  1197. }
  1198. if (SND_SOC_DAPM_EVENT_OFF(event))
  1199. ret = swr_slvdev_datapath_control(
  1200. wcd938x->rx_swr_dev,
  1201. wcd938x->rx_swr_dev->dev_num,
  1202. false);
  1203. return ret;
  1204. }
  1205. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1206. struct snd_kcontrol *kcontrol,
  1207. int event)
  1208. {
  1209. struct snd_soc_component *component =
  1210. snd_soc_dapm_to_component(w->dapm);
  1211. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1212. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1213. w->name, event);
  1214. switch (event) {
  1215. case SND_SOC_DAPM_PRE_PMU:
  1216. wcd938x_rx_connect_port(component, HPH_L, true);
  1217. if (wcd938x->comp1_enable)
  1218. wcd938x_rx_connect_port(component, COMP_L, true);
  1219. break;
  1220. case SND_SOC_DAPM_POST_PMD:
  1221. wcd938x_rx_connect_port(component, HPH_L, false);
  1222. if (wcd938x->comp1_enable)
  1223. wcd938x_rx_connect_port(component, COMP_L, false);
  1224. wcd938x_rx_clk_disable(component);
  1225. snd_soc_component_update_bits(component,
  1226. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1227. 0x01, 0x00);
  1228. break;
  1229. };
  1230. return 0;
  1231. }
  1232. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1233. struct snd_kcontrol *kcontrol, int event)
  1234. {
  1235. struct snd_soc_component *component =
  1236. snd_soc_dapm_to_component(w->dapm);
  1237. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1238. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1239. w->name, event);
  1240. switch (event) {
  1241. case SND_SOC_DAPM_PRE_PMU:
  1242. wcd938x_rx_connect_port(component, HPH_R, true);
  1243. if (wcd938x->comp2_enable)
  1244. wcd938x_rx_connect_port(component, COMP_R, true);
  1245. break;
  1246. case SND_SOC_DAPM_POST_PMD:
  1247. wcd938x_rx_connect_port(component, HPH_R, false);
  1248. if (wcd938x->comp2_enable)
  1249. wcd938x_rx_connect_port(component, COMP_R, false);
  1250. wcd938x_rx_clk_disable(component);
  1251. snd_soc_component_update_bits(component,
  1252. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1253. 0x02, 0x00);
  1254. break;
  1255. };
  1256. return 0;
  1257. }
  1258. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1259. struct snd_kcontrol *kcontrol,
  1260. int event)
  1261. {
  1262. struct snd_soc_component *component =
  1263. snd_soc_dapm_to_component(w->dapm);
  1264. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1265. w->name, event);
  1266. switch (event) {
  1267. case SND_SOC_DAPM_PRE_PMU:
  1268. wcd938x_rx_connect_port(component, LO, true);
  1269. break;
  1270. case SND_SOC_DAPM_POST_PMD:
  1271. wcd938x_rx_connect_port(component, LO, false);
  1272. /* 6 msec delay as per HW requirement */
  1273. usleep_range(6000, 6010);
  1274. wcd938x_rx_clk_disable(component);
  1275. snd_soc_component_update_bits(component,
  1276. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1277. break;
  1278. }
  1279. return 0;
  1280. }
  1281. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1282. struct snd_kcontrol *kcontrol,
  1283. int event)
  1284. {
  1285. struct snd_soc_component *component =
  1286. snd_soc_dapm_to_component(w->dapm);
  1287. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1288. u16 dmic_clk_reg, dmic_clk_en_reg;
  1289. s32 *dmic_clk_cnt;
  1290. u8 dmic_ctl_shift = 0;
  1291. u8 dmic_clk_shift = 0;
  1292. u8 dmic_clk_mask = 0;
  1293. u16 dmic2_left_en = 0;
  1294. int ret = 0;
  1295. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1296. w->name, event);
  1297. switch (w->shift) {
  1298. case 0:
  1299. case 1:
  1300. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1301. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1302. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1303. dmic_clk_mask = 0x0F;
  1304. dmic_clk_shift = 0x00;
  1305. dmic_ctl_shift = 0x00;
  1306. break;
  1307. case 2:
  1308. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1309. case 3:
  1310. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1311. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1312. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1313. dmic_clk_mask = 0xF0;
  1314. dmic_clk_shift = 0x04;
  1315. dmic_ctl_shift = 0x01;
  1316. break;
  1317. case 4:
  1318. case 5:
  1319. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1320. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1321. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1322. dmic_clk_mask = 0x0F;
  1323. dmic_clk_shift = 0x00;
  1324. dmic_ctl_shift = 0x02;
  1325. break;
  1326. case 6:
  1327. case 7:
  1328. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1329. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1330. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1331. dmic_clk_mask = 0xF0;
  1332. dmic_clk_shift = 0x04;
  1333. dmic_ctl_shift = 0x03;
  1334. break;
  1335. default:
  1336. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1337. __func__);
  1338. return -EINVAL;
  1339. };
  1340. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1341. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1342. switch (event) {
  1343. case SND_SOC_DAPM_PRE_PMU:
  1344. snd_soc_component_update_bits(component,
  1345. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1346. (0x01 << dmic_ctl_shift), 0x00);
  1347. /* 250us sleep as per HW requirement */
  1348. usleep_range(250, 260);
  1349. if (dmic2_left_en)
  1350. snd_soc_component_update_bits(component,
  1351. dmic2_left_en, 0x80, 0x80);
  1352. /* Setting DMIC clock rate to 2.4MHz */
  1353. snd_soc_component_update_bits(component,
  1354. dmic_clk_reg, dmic_clk_mask,
  1355. (0x03 << dmic_clk_shift));
  1356. snd_soc_component_update_bits(component,
  1357. dmic_clk_en_reg, 0x08, 0x08);
  1358. /* enable clock scaling */
  1359. snd_soc_component_update_bits(component,
  1360. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1361. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1362. wcd938x->tx_swr_dev->dev_num,
  1363. true);
  1364. break;
  1365. case SND_SOC_DAPM_POST_PMD:
  1366. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1367. false);
  1368. snd_soc_component_update_bits(component,
  1369. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1370. (0x01 << dmic_ctl_shift),
  1371. (0x01 << dmic_ctl_shift));
  1372. if (dmic2_left_en)
  1373. snd_soc_component_update_bits(component,
  1374. dmic2_left_en, 0x80, 0x00);
  1375. snd_soc_component_update_bits(component,
  1376. dmic_clk_en_reg, 0x08, 0x00);
  1377. break;
  1378. };
  1379. return ret;
  1380. }
  1381. /*
  1382. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1383. * @micb_mv: micbias in mv
  1384. *
  1385. * return register value converted
  1386. */
  1387. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1388. {
  1389. /* min micbias voltage is 1V and maximum is 2.85V */
  1390. if (micb_mv < 1000 || micb_mv > 2850) {
  1391. pr_err("%s: unsupported micbias voltage\n", __func__);
  1392. return -EINVAL;
  1393. }
  1394. return (micb_mv - 1000) / 50;
  1395. }
  1396. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1397. /*
  1398. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1399. * @component: handle to snd_soc_component *
  1400. * @req_volt: micbias voltage to be set
  1401. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1402. *
  1403. * return 0 if adjustment is success or error code in case of failure
  1404. */
  1405. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1406. int req_volt, int micb_num)
  1407. {
  1408. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1409. int cur_vout_ctl, req_vout_ctl;
  1410. int micb_reg, micb_val, micb_en;
  1411. int ret = 0;
  1412. switch (micb_num) {
  1413. case MIC_BIAS_1:
  1414. micb_reg = WCD938X_ANA_MICB1;
  1415. break;
  1416. case MIC_BIAS_2:
  1417. micb_reg = WCD938X_ANA_MICB2;
  1418. break;
  1419. case MIC_BIAS_3:
  1420. micb_reg = WCD938X_ANA_MICB3;
  1421. break;
  1422. case MIC_BIAS_4:
  1423. micb_reg = WCD938X_ANA_MICB4;
  1424. break;
  1425. default:
  1426. return -EINVAL;
  1427. }
  1428. mutex_lock(&wcd938x->micb_lock);
  1429. /*
  1430. * If requested micbias voltage is same as current micbias
  1431. * voltage, then just return. Otherwise, adjust voltage as
  1432. * per requested value. If micbias is already enabled, then
  1433. * to avoid slow micbias ramp-up or down enable pull-up
  1434. * momentarily, change the micbias value and then re-enable
  1435. * micbias.
  1436. */
  1437. micb_val = snd_soc_component_read(component, micb_reg);
  1438. micb_en = (micb_val & 0xC0) >> 6;
  1439. cur_vout_ctl = micb_val & 0x3F;
  1440. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1441. if (req_vout_ctl < 0) {
  1442. ret = -EINVAL;
  1443. goto exit;
  1444. }
  1445. if (cur_vout_ctl == req_vout_ctl) {
  1446. ret = 0;
  1447. goto exit;
  1448. }
  1449. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1450. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1451. req_volt, micb_en);
  1452. if (micb_en == 0x1)
  1453. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1454. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1455. if (micb_en == 0x1) {
  1456. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1457. /*
  1458. * Add 2ms delay as per HW requirement after enabling
  1459. * micbias
  1460. */
  1461. usleep_range(2000, 2100);
  1462. }
  1463. exit:
  1464. mutex_unlock(&wcd938x->micb_lock);
  1465. return ret;
  1466. }
  1467. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1468. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1469. struct snd_kcontrol *kcontrol,
  1470. int event)
  1471. {
  1472. struct snd_soc_component *component =
  1473. snd_soc_dapm_to_component(w->dapm);
  1474. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1475. int ret = 0;
  1476. int bank = 0;
  1477. u8 mode = 0;
  1478. int i = 0;
  1479. int rate = 0;
  1480. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1481. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1482. /* power mode is applicable only to analog mics */
  1483. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1484. /* Get channel rate */
  1485. rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift - ADC1]);
  1486. }
  1487. switch (event) {
  1488. case SND_SOC_DAPM_PRE_PMU:
  1489. /* Check AMIC2 is connected to ADC2 to take an action on BCS */
  1490. if (w->shift == ADC2 && !(snd_soc_component_read(component,
  1491. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1492. if (!wcd938x->bcs_dis) {
  1493. wcd938x_tx_connect_port(component, MBHC,
  1494. SWR_CLK_RATE_4P8MHZ, true);
  1495. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1496. }
  1497. }
  1498. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1499. set_bit(w->shift - ADC1, &wcd938x->status_mask);
  1500. wcd938x_tx_connect_port(component, w->shift, rate,
  1501. true);
  1502. } else {
  1503. wcd938x_tx_connect_port(component, w->shift,
  1504. SWR_CLK_RATE_2P4MHZ, true);
  1505. }
  1506. break;
  1507. case SND_SOC_DAPM_POST_PMD:
  1508. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1509. if (strnstr(w->name, "ADC1", sizeof("ADC1"))) {
  1510. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1511. clear_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  1512. } else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) {
  1513. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1514. clear_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  1515. } else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) {
  1516. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1517. clear_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  1518. } else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) {
  1519. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1520. clear_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  1521. }
  1522. }
  1523. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1524. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1525. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1526. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1527. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1528. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1529. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1530. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1531. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1532. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1533. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1534. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1535. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1536. if (mode != 0) {
  1537. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1538. if (mode & (1 << i)) {
  1539. i++;
  1540. break;
  1541. }
  1542. }
  1543. }
  1544. rate = wcd938x_get_clk_rate(i);
  1545. if (wcd938x->adc_count) {
  1546. rate = (wcd938x->adc_count * rate);
  1547. if (rate > SWR_CLK_RATE_9P6MHZ)
  1548. rate = SWR_CLK_RATE_9P6MHZ;
  1549. }
  1550. wcd938x_set_swr_clk_rate(component, rate, bank);
  1551. }
  1552. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1553. wcd938x->tx_swr_dev->dev_num,
  1554. false);
  1555. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1556. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1557. break;
  1558. };
  1559. return ret;
  1560. }
  1561. static int wcd938x_get_adc_mode(int val)
  1562. {
  1563. int ret = 0;
  1564. switch (val) {
  1565. case ADC_MODE_INVALID:
  1566. ret = ADC_MODE_VAL_NORMAL;
  1567. break;
  1568. case ADC_MODE_HIFI:
  1569. ret = ADC_MODE_VAL_HIFI;
  1570. break;
  1571. case ADC_MODE_LO_HIF:
  1572. ret = ADC_MODE_VAL_LO_HIF;
  1573. break;
  1574. case ADC_MODE_NORMAL:
  1575. ret = ADC_MODE_VAL_NORMAL;
  1576. break;
  1577. case ADC_MODE_LP:
  1578. ret = ADC_MODE_VAL_LP;
  1579. break;
  1580. case ADC_MODE_ULP1:
  1581. ret = ADC_MODE_VAL_ULP1;
  1582. break;
  1583. case ADC_MODE_ULP2:
  1584. ret = ADC_MODE_VAL_ULP2;
  1585. break;
  1586. default:
  1587. ret = -EINVAL;
  1588. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1589. break;
  1590. }
  1591. return ret;
  1592. }
  1593. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1594. int channel, int mode)
  1595. {
  1596. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1597. int ret = 0;
  1598. switch (channel) {
  1599. case 0:
  1600. reg = WCD938X_ANA_TX_CH2;
  1601. mask = 0x40;
  1602. break;
  1603. case 1:
  1604. reg = WCD938X_ANA_TX_CH2;
  1605. mask = 0x20;
  1606. break;
  1607. case 2:
  1608. reg = WCD938X_ANA_TX_CH4;
  1609. mask = 0x40;
  1610. break;
  1611. case 3:
  1612. reg = WCD938X_ANA_TX_CH4;
  1613. mask = 0x20;
  1614. break;
  1615. default:
  1616. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1617. ret = -EINVAL;
  1618. break;
  1619. }
  1620. if (!mode)
  1621. val = 0x00;
  1622. else
  1623. val = mask;
  1624. if (!ret)
  1625. snd_soc_component_update_bits(component, reg, mask, val);
  1626. return ret;
  1627. }
  1628. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1629. struct snd_kcontrol *kcontrol,
  1630. int event){
  1631. struct snd_soc_component *component =
  1632. snd_soc_dapm_to_component(w->dapm);
  1633. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1634. int clk_rate = 0, ret = 0;
  1635. int mode = 0, i = 0, bank = 0;
  1636. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1637. w->name, event);
  1638. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1639. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1640. switch (event) {
  1641. case SND_SOC_DAPM_PRE_PMU:
  1642. wcd938x->adc_count++;
  1643. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1644. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1645. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1646. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1647. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1648. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1649. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1650. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1651. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1652. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1653. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1654. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1655. if (mode != 0) {
  1656. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1657. if (mode & (1 << i)) {
  1658. i++;
  1659. break;
  1660. }
  1661. }
  1662. }
  1663. clk_rate = wcd938x_get_clk_rate(i);
  1664. /* clk_rate depends on number of paths getting enabled */
  1665. clk_rate = (wcd938x->adc_count * clk_rate);
  1666. if (clk_rate > SWR_CLK_RATE_9P6MHZ)
  1667. clk_rate = SWR_CLK_RATE_9P6MHZ;
  1668. wcd938x_set_swr_clk_rate(component, clk_rate, bank);
  1669. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1670. wcd938x->tx_swr_dev->dev_num,
  1671. true);
  1672. wcd938x_set_swr_clk_rate(component, clk_rate, !bank);
  1673. break;
  1674. case SND_SOC_DAPM_POST_PMD:
  1675. wcd938x->adc_count--;
  1676. if (wcd938x->adc_count < 0)
  1677. wcd938x->adc_count = 0;
  1678. wcd938x_tx_connect_port(component, ADC1 + w->shift, 0, false);
  1679. if (w->shift + ADC1 == ADC2 &&
  1680. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1681. wcd938x_tx_connect_port(component, MBHC, 0,
  1682. false);
  1683. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1684. }
  1685. break;
  1686. };
  1687. return ret;
  1688. }
  1689. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1690. bool bcs_disable)
  1691. {
  1692. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1693. if (wcd938x->update_wcd_event) {
  1694. if (bcs_disable)
  1695. wcd938x->update_wcd_event(wcd938x->handle,
  1696. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1697. else
  1698. wcd938x->update_wcd_event(wcd938x->handle,
  1699. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1700. }
  1701. }
  1702. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1703. struct snd_kcontrol *kcontrol, int event)
  1704. {
  1705. struct snd_soc_component *component =
  1706. snd_soc_dapm_to_component(w->dapm);
  1707. struct wcd938x_priv *wcd938x =
  1708. snd_soc_component_get_drvdata(component);
  1709. int ret = 0;
  1710. u8 mode = 0;
  1711. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1712. w->name, event);
  1713. switch (event) {
  1714. case SND_SOC_DAPM_PRE_PMU:
  1715. snd_soc_component_update_bits(component,
  1716. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1717. snd_soc_component_update_bits(component,
  1718. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1719. snd_soc_component_update_bits(component,
  1720. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1721. snd_soc_component_update_bits(component,
  1722. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1723. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1724. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1725. if (mode < 0) {
  1726. dev_info(component->dev,
  1727. "%s: invalid mode, setting to normal mode\n",
  1728. __func__);
  1729. mode = ADC_MODE_VAL_NORMAL;
  1730. }
  1731. switch (w->shift) {
  1732. case 0:
  1733. snd_soc_component_update_bits(component,
  1734. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1735. mode);
  1736. snd_soc_component_update_bits(component,
  1737. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1738. break;
  1739. case 1:
  1740. snd_soc_component_update_bits(component,
  1741. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1742. mode << 4);
  1743. snd_soc_component_update_bits(component,
  1744. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1745. break;
  1746. case 2:
  1747. snd_soc_component_update_bits(component,
  1748. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1749. mode);
  1750. snd_soc_component_update_bits(component,
  1751. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1752. break;
  1753. case 3:
  1754. snd_soc_component_update_bits(component,
  1755. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1756. mode << 4);
  1757. snd_soc_component_update_bits(component,
  1758. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1759. break;
  1760. default:
  1761. break;
  1762. }
  1763. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1764. break;
  1765. case SND_SOC_DAPM_POST_PMD:
  1766. switch (w->shift) {
  1767. case 0:
  1768. snd_soc_component_update_bits(component,
  1769. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1770. 0x00);
  1771. snd_soc_component_update_bits(component,
  1772. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1773. break;
  1774. case 1:
  1775. snd_soc_component_update_bits(component,
  1776. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1777. 0x00);
  1778. snd_soc_component_update_bits(component,
  1779. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1780. break;
  1781. case 2:
  1782. snd_soc_component_update_bits(component,
  1783. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1784. 0x00);
  1785. snd_soc_component_update_bits(component,
  1786. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1787. break;
  1788. case 3:
  1789. snd_soc_component_update_bits(component,
  1790. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1791. 0x00);
  1792. snd_soc_component_update_bits(component,
  1793. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1794. break;
  1795. default:
  1796. break;
  1797. }
  1798. if (wcd938x->adc_count == 0) {
  1799. snd_soc_component_update_bits(component,
  1800. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1801. snd_soc_component_update_bits(component,
  1802. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1803. }
  1804. break;
  1805. };
  1806. return ret;
  1807. }
  1808. int wcd938x_micbias_control(struct snd_soc_component *component,
  1809. int micb_num, int req, bool is_dapm)
  1810. {
  1811. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1812. int micb_index = micb_num - 1;
  1813. u16 micb_reg;
  1814. int pre_off_event = 0, post_off_event = 0;
  1815. int post_on_event = 0, post_dapm_off = 0;
  1816. int post_dapm_on = 0;
  1817. int ret = 0;
  1818. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1819. dev_err(component->dev,
  1820. "%s: Invalid micbias index, micb_ind:%d\n",
  1821. __func__, micb_index);
  1822. return -EINVAL;
  1823. }
  1824. if (NULL == wcd938x) {
  1825. dev_err(component->dev,
  1826. "%s: wcd938x private data is NULL\n", __func__);
  1827. return -EINVAL;
  1828. }
  1829. switch (micb_num) {
  1830. case MIC_BIAS_1:
  1831. micb_reg = WCD938X_ANA_MICB1;
  1832. break;
  1833. case MIC_BIAS_2:
  1834. micb_reg = WCD938X_ANA_MICB2;
  1835. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1836. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1837. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1838. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1839. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1840. break;
  1841. case MIC_BIAS_3:
  1842. micb_reg = WCD938X_ANA_MICB3;
  1843. break;
  1844. case MIC_BIAS_4:
  1845. micb_reg = WCD938X_ANA_MICB4;
  1846. break;
  1847. default:
  1848. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1849. __func__, micb_num);
  1850. return -EINVAL;
  1851. };
  1852. mutex_lock(&wcd938x->micb_lock);
  1853. switch (req) {
  1854. case MICB_PULLUP_ENABLE:
  1855. if (!wcd938x->dev_up) {
  1856. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1857. __func__, req);
  1858. ret = -ENODEV;
  1859. goto done;
  1860. }
  1861. wcd938x->pullup_ref[micb_index]++;
  1862. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1863. (wcd938x->micb_ref[micb_index] == 0))
  1864. snd_soc_component_update_bits(component, micb_reg,
  1865. 0xC0, 0x80);
  1866. break;
  1867. case MICB_PULLUP_DISABLE:
  1868. if (wcd938x->pullup_ref[micb_index] > 0)
  1869. wcd938x->pullup_ref[micb_index]--;
  1870. if (!wcd938x->dev_up) {
  1871. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1872. __func__, req);
  1873. ret = -ENODEV;
  1874. goto done;
  1875. }
  1876. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1877. (wcd938x->micb_ref[micb_index] == 0))
  1878. snd_soc_component_update_bits(component, micb_reg,
  1879. 0xC0, 0x00);
  1880. break;
  1881. case MICB_ENABLE:
  1882. if (!wcd938x->dev_up) {
  1883. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1884. __func__, req);
  1885. ret = -ENODEV;
  1886. goto done;
  1887. }
  1888. wcd938x->micb_ref[micb_index]++;
  1889. if (wcd938x->micb_ref[micb_index] == 1) {
  1890. snd_soc_component_update_bits(component,
  1891. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1892. snd_soc_component_update_bits(component,
  1893. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1894. snd_soc_component_update_bits(component,
  1895. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1896. snd_soc_component_update_bits(component,
  1897. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1898. snd_soc_component_update_bits(component,
  1899. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1900. snd_soc_component_update_bits(component,
  1901. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1902. snd_soc_component_update_bits(component,
  1903. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1904. snd_soc_component_update_bits(component,
  1905. micb_reg, 0xC0, 0x40);
  1906. if (post_on_event)
  1907. blocking_notifier_call_chain(
  1908. &wcd938x->mbhc->notifier,
  1909. post_on_event,
  1910. &wcd938x->mbhc->wcd_mbhc);
  1911. }
  1912. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1913. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1914. post_dapm_on,
  1915. &wcd938x->mbhc->wcd_mbhc);
  1916. break;
  1917. case MICB_DISABLE:
  1918. if (wcd938x->micb_ref[micb_index] > 0)
  1919. wcd938x->micb_ref[micb_index]--;
  1920. if (!wcd938x->dev_up) {
  1921. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1922. __func__, req);
  1923. ret = -ENODEV;
  1924. goto done;
  1925. }
  1926. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1927. (wcd938x->pullup_ref[micb_index] > 0))
  1928. snd_soc_component_update_bits(component, micb_reg,
  1929. 0xC0, 0x80);
  1930. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1931. (wcd938x->pullup_ref[micb_index] == 0)) {
  1932. if (pre_off_event && wcd938x->mbhc)
  1933. blocking_notifier_call_chain(
  1934. &wcd938x->mbhc->notifier,
  1935. pre_off_event,
  1936. &wcd938x->mbhc->wcd_mbhc);
  1937. snd_soc_component_update_bits(component, micb_reg,
  1938. 0xC0, 0x00);
  1939. if (post_off_event && wcd938x->mbhc)
  1940. blocking_notifier_call_chain(
  1941. &wcd938x->mbhc->notifier,
  1942. post_off_event,
  1943. &wcd938x->mbhc->wcd_mbhc);
  1944. }
  1945. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1946. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1947. post_dapm_off,
  1948. &wcd938x->mbhc->wcd_mbhc);
  1949. break;
  1950. };
  1951. dev_dbg(component->dev,
  1952. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1953. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1954. wcd938x->pullup_ref[micb_index]);
  1955. done:
  1956. mutex_unlock(&wcd938x->micb_lock);
  1957. return ret;
  1958. }
  1959. EXPORT_SYMBOL(wcd938x_micbias_control);
  1960. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1961. {
  1962. int ret = 0;
  1963. uint8_t devnum = 0;
  1964. int num_retry = NUM_ATTEMPTS;
  1965. do {
  1966. /* retry after 1ms */
  1967. usleep_range(1000, 1010);
  1968. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1969. } while (ret && --num_retry);
  1970. if (ret)
  1971. dev_err(&swr_dev->dev,
  1972. "%s get devnum %d for dev addr %llx failed\n",
  1973. __func__, devnum, swr_dev->addr);
  1974. swr_dev->dev_num = devnum;
  1975. return 0;
  1976. }
  1977. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1978. struct wcd_mbhc_config *mbhc_cfg)
  1979. {
  1980. if (mbhc_cfg->enable_usbc_analog) {
  1981. if (!(snd_soc_component_read(component, WCD938X_ANA_MBHC_MECH)
  1982. & 0x20))
  1983. return true;
  1984. }
  1985. return false;
  1986. }
  1987. int wcd938x_swr_dmic_register_notifier(struct snd_soc_component *component,
  1988. struct notifier_block *nblock,
  1989. bool enable)
  1990. {
  1991. struct wcd938x_priv *wcd938x_priv;
  1992. if(NULL == component) {
  1993. pr_err("%s: wcd938x component is NULL\n", __func__);
  1994. return -EINVAL;
  1995. }
  1996. wcd938x_priv = snd_soc_component_get_drvdata(component);
  1997. wcd938x_priv->notify_swr_dmic = enable;
  1998. if (enable)
  1999. return blocking_notifier_chain_register(&wcd938x_priv->notifier,
  2000. nblock);
  2001. else
  2002. return blocking_notifier_chain_unregister(
  2003. &wcd938x_priv->notifier, nblock);
  2004. }
  2005. EXPORT_SYMBOL(wcd938x_swr_dmic_register_notifier);
  2006. static int wcd938x_event_notify(struct notifier_block *block,
  2007. unsigned long val,
  2008. void *data)
  2009. {
  2010. u16 event = (val & 0xffff);
  2011. int ret = 0;
  2012. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  2013. struct snd_soc_component *component = wcd938x->component;
  2014. struct wcd_mbhc *mbhc;
  2015. switch (event) {
  2016. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2017. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  2018. snd_soc_component_update_bits(component,
  2019. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  2020. set_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  2021. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  2022. }
  2023. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  2024. snd_soc_component_update_bits(component,
  2025. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  2026. set_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  2027. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  2028. }
  2029. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  2030. snd_soc_component_update_bits(component,
  2031. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  2032. set_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  2033. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  2034. }
  2035. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  2036. snd_soc_component_update_bits(component,
  2037. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  2038. set_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  2039. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  2040. }
  2041. break;
  2042. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2043. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  2044. 0xC0, 0x00);
  2045. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  2046. 0x80, 0x00);
  2047. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  2048. 0x80, 0x00);
  2049. break;
  2050. case BOLERO_SLV_EVT_SSR_DOWN:
  2051. wcd938x->dev_up = false;
  2052. if(wcd938x->notify_swr_dmic)
  2053. blocking_notifier_call_chain(&wcd938x->notifier,
  2054. WCD938X_EVT_SSR_DOWN,
  2055. NULL);
  2056. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true;
  2057. mbhc = &wcd938x->mbhc->wcd_mbhc;
  2058. wcd938x->usbc_hs_status = get_usbc_hs_status(component,
  2059. mbhc->mbhc_cfg);
  2060. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  2061. wcd938x_reset_low(wcd938x->dev);
  2062. break;
  2063. case BOLERO_SLV_EVT_SSR_UP:
  2064. wcd938x_reset(wcd938x->dev);
  2065. /* allow reset to take effect */
  2066. usleep_range(10000, 10010);
  2067. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  2068. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  2069. wcd938x_init_reg(component);
  2070. regcache_mark_dirty(wcd938x->regmap);
  2071. regcache_sync(wcd938x->regmap);
  2072. /* Initialize MBHC module */
  2073. mbhc = &wcd938x->mbhc->wcd_mbhc;
  2074. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  2075. if (ret) {
  2076. dev_err(component->dev, "%s: mbhc initialization failed\n",
  2077. __func__);
  2078. } else {
  2079. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2080. }
  2081. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = false;
  2082. wcd938x->dev_up = true;
  2083. if(wcd938x->notify_swr_dmic)
  2084. blocking_notifier_call_chain(&wcd938x->notifier,
  2085. WCD938X_EVT_SSR_UP,
  2086. NULL);
  2087. if (wcd938x->usbc_hs_status)
  2088. mdelay(500);
  2089. break;
  2090. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2091. snd_soc_component_update_bits(component,
  2092. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  2093. ((val >> 0x10) << 0x01));
  2094. break;
  2095. default:
  2096. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2097. break;
  2098. }
  2099. return 0;
  2100. }
  2101. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2102. int event)
  2103. {
  2104. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2105. int micb_num;
  2106. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2107. __func__, w->name, event);
  2108. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  2109. micb_num = MIC_BIAS_1;
  2110. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  2111. micb_num = MIC_BIAS_2;
  2112. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  2113. micb_num = MIC_BIAS_3;
  2114. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  2115. micb_num = MIC_BIAS_4;
  2116. else
  2117. return -EINVAL;
  2118. switch (event) {
  2119. case SND_SOC_DAPM_PRE_PMU:
  2120. wcd938x_micbias_control(component, micb_num,
  2121. MICB_ENABLE, true);
  2122. break;
  2123. case SND_SOC_DAPM_POST_PMU:
  2124. /* 1 msec delay as per HW requirement */
  2125. usleep_range(1000, 1100);
  2126. break;
  2127. case SND_SOC_DAPM_POST_PMD:
  2128. wcd938x_micbias_control(component, micb_num,
  2129. MICB_DISABLE, true);
  2130. break;
  2131. };
  2132. return 0;
  2133. }
  2134. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2135. struct snd_kcontrol *kcontrol,
  2136. int event)
  2137. {
  2138. return __wcd938x_codec_enable_micbias(w, event);
  2139. }
  2140. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2141. int event)
  2142. {
  2143. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2144. int micb_num;
  2145. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2146. __func__, w->name, event);
  2147. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  2148. micb_num = MIC_BIAS_1;
  2149. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  2150. micb_num = MIC_BIAS_2;
  2151. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  2152. micb_num = MIC_BIAS_3;
  2153. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  2154. micb_num = MIC_BIAS_4;
  2155. else
  2156. return -EINVAL;
  2157. switch (event) {
  2158. case SND_SOC_DAPM_PRE_PMU:
  2159. wcd938x_micbias_control(component, micb_num,
  2160. MICB_PULLUP_ENABLE, true);
  2161. break;
  2162. case SND_SOC_DAPM_POST_PMU:
  2163. /* 1 msec delay as per HW requirement */
  2164. usleep_range(1000, 1100);
  2165. break;
  2166. case SND_SOC_DAPM_POST_PMD:
  2167. wcd938x_micbias_control(component, micb_num,
  2168. MICB_PULLUP_DISABLE, true);
  2169. break;
  2170. };
  2171. return 0;
  2172. }
  2173. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2174. struct snd_kcontrol *kcontrol,
  2175. int event)
  2176. {
  2177. return __wcd938x_codec_enable_micbias_pullup(w, event);
  2178. }
  2179. static int wcd938x_wakeup(void *handle, bool enable)
  2180. {
  2181. struct wcd938x_priv *priv;
  2182. int ret = 0;
  2183. if (!handle) {
  2184. pr_err("%s: NULL handle\n", __func__);
  2185. return -EINVAL;
  2186. }
  2187. priv = (struct wcd938x_priv *)handle;
  2188. if (!priv->tx_swr_dev) {
  2189. pr_err("%s: tx swr dev is NULL\n", __func__);
  2190. return -EINVAL;
  2191. }
  2192. mutex_lock(&priv->wakeup_lock);
  2193. if (enable)
  2194. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2195. else
  2196. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2197. mutex_unlock(&priv->wakeup_lock);
  2198. return ret;
  2199. }
  2200. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2201. struct snd_kcontrol *kcontrol,
  2202. int event)
  2203. {
  2204. int ret = 0;
  2205. struct snd_soc_component *component =
  2206. snd_soc_dapm_to_component(w->dapm);
  2207. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2208. switch (event) {
  2209. case SND_SOC_DAPM_PRE_PMU:
  2210. wcd938x_wakeup(wcd938x, true);
  2211. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2212. wcd938x_wakeup(wcd938x, false);
  2213. break;
  2214. case SND_SOC_DAPM_POST_PMD:
  2215. wcd938x_wakeup(wcd938x, true);
  2216. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2217. wcd938x_wakeup(wcd938x, false);
  2218. break;
  2219. }
  2220. return ret;
  2221. }
  2222. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2223. int micb_num, int req)
  2224. {
  2225. int micb_index = micb_num - 1;
  2226. u16 micb_reg;
  2227. if (NULL == wcd938x) {
  2228. pr_err("%s: wcd938x private data is NULL\n", __func__);
  2229. return -EINVAL;
  2230. }
  2231. switch (micb_num) {
  2232. case MIC_BIAS_1:
  2233. micb_reg = WCD938X_ANA_MICB1;
  2234. break;
  2235. case MIC_BIAS_2:
  2236. micb_reg = WCD938X_ANA_MICB2;
  2237. break;
  2238. case MIC_BIAS_3:
  2239. micb_reg = WCD938X_ANA_MICB3;
  2240. break;
  2241. case MIC_BIAS_4:
  2242. micb_reg = WCD938X_ANA_MICB4;
  2243. break;
  2244. default:
  2245. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2246. return -EINVAL;
  2247. };
  2248. pr_debug("%s: req: %d micb_num: %d micb_ref: %d pullup_ref: %d\n",
  2249. __func__, req, micb_num, wcd938x->micb_ref[micb_index],
  2250. wcd938x->pullup_ref[micb_index]);
  2251. mutex_lock(&wcd938x->micb_lock);
  2252. switch (req) {
  2253. case MICB_ENABLE:
  2254. wcd938x->micb_ref[micb_index]++;
  2255. if (wcd938x->micb_ref[micb_index] == 1) {
  2256. regmap_update_bits(wcd938x->regmap,
  2257. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2258. regmap_update_bits(wcd938x->regmap,
  2259. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2260. regmap_update_bits(wcd938x->regmap,
  2261. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2262. regmap_update_bits(wcd938x->regmap,
  2263. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2264. regmap_update_bits(wcd938x->regmap,
  2265. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2266. regmap_update_bits(wcd938x->regmap,
  2267. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2268. regmap_update_bits(wcd938x->regmap,
  2269. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2270. regmap_update_bits(wcd938x->regmap,
  2271. micb_reg, 0xC0, 0x40);
  2272. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2273. }
  2274. break;
  2275. case MICB_PULLUP_ENABLE:
  2276. wcd938x->pullup_ref[micb_index]++;
  2277. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2278. (wcd938x->micb_ref[micb_index] == 0))
  2279. regmap_update_bits(wcd938x->regmap, micb_reg,
  2280. 0xC0, 0x80);
  2281. break;
  2282. case MICB_PULLUP_DISABLE:
  2283. if (wcd938x->pullup_ref[micb_index] > 0)
  2284. wcd938x->pullup_ref[micb_index]--;
  2285. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2286. (wcd938x->micb_ref[micb_index] == 0))
  2287. regmap_update_bits(wcd938x->regmap, micb_reg,
  2288. 0xC0, 0x00);
  2289. break;
  2290. case MICB_DISABLE:
  2291. if (wcd938x->micb_ref[micb_index] > 0)
  2292. wcd938x->micb_ref[micb_index]--;
  2293. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2294. (wcd938x->pullup_ref[micb_index] > 0))
  2295. regmap_update_bits(wcd938x->regmap, micb_reg,
  2296. 0xC0, 0x80);
  2297. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2298. (wcd938x->pullup_ref[micb_index] == 0))
  2299. regmap_update_bits(wcd938x->regmap, micb_reg,
  2300. 0xC0, 0x00);
  2301. break;
  2302. };
  2303. mutex_unlock(&wcd938x->micb_lock);
  2304. return 0;
  2305. }
  2306. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2307. int event, int micb_num)
  2308. {
  2309. struct wcd938x_priv *wcd938x_priv = NULL;
  2310. int ret = 0;
  2311. int micb_index = micb_num - 1;
  2312. if(NULL == component) {
  2313. pr_err("%s: wcd938x component is NULL\n", __func__);
  2314. return -EINVAL;
  2315. }
  2316. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2317. pr_err("%s: invalid event: %d\n", __func__, event);
  2318. return -EINVAL;
  2319. }
  2320. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2321. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2322. return -EINVAL;
  2323. }
  2324. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2325. if (!wcd938x_priv->dev_up) {
  2326. if ((wcd938x_priv->pullup_ref[micb_index] > 0) &&
  2327. (event == SND_SOC_DAPM_POST_PMD)) {
  2328. wcd938x_priv->pullup_ref[micb_index]--;
  2329. ret = -ENODEV;
  2330. goto done;
  2331. }
  2332. }
  2333. switch (event) {
  2334. case SND_SOC_DAPM_PRE_PMU:
  2335. wcd938x_wakeup(wcd938x_priv, true);
  2336. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2337. wcd938x_wakeup(wcd938x_priv, false);
  2338. break;
  2339. case SND_SOC_DAPM_POST_PMD:
  2340. wcd938x_wakeup(wcd938x_priv, true);
  2341. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2342. wcd938x_wakeup(wcd938x_priv, false);
  2343. break;
  2344. }
  2345. done:
  2346. return ret;
  2347. }
  2348. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2349. static inline int wcd938x_tx_path_get(const char *wname,
  2350. unsigned int *path_num)
  2351. {
  2352. int ret = 0;
  2353. char *widget_name = NULL;
  2354. char *w_name = NULL;
  2355. char *path_num_char = NULL;
  2356. char *path_name = NULL;
  2357. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2358. if (!widget_name)
  2359. return -EINVAL;
  2360. w_name = widget_name;
  2361. path_name = strsep(&widget_name, " ");
  2362. if (!path_name) {
  2363. pr_err("%s: Invalid widget name = %s\n",
  2364. __func__, widget_name);
  2365. ret = -EINVAL;
  2366. goto err;
  2367. }
  2368. path_num_char = strpbrk(path_name, "0123");
  2369. if (!path_num_char) {
  2370. pr_err("%s: tx path index not found\n",
  2371. __func__);
  2372. ret = -EINVAL;
  2373. goto err;
  2374. }
  2375. ret = kstrtouint(path_num_char, 10, path_num);
  2376. if (ret < 0)
  2377. pr_err("%s: Invalid tx path = %s\n",
  2378. __func__, w_name);
  2379. err:
  2380. kfree(w_name);
  2381. return ret;
  2382. }
  2383. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2384. struct snd_ctl_elem_value *ucontrol)
  2385. {
  2386. struct snd_soc_component *component =
  2387. snd_soc_kcontrol_component(kcontrol);
  2388. struct wcd938x_priv *wcd938x = NULL;
  2389. int ret = 0;
  2390. unsigned int path = 0;
  2391. if (!component)
  2392. return -EINVAL;
  2393. wcd938x = snd_soc_component_get_drvdata(component);
  2394. if (!wcd938x)
  2395. return -EINVAL;
  2396. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2397. if (ret < 0)
  2398. return ret;
  2399. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2400. return 0;
  2401. }
  2402. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2403. struct snd_ctl_elem_value *ucontrol)
  2404. {
  2405. struct snd_soc_component *component =
  2406. snd_soc_kcontrol_component(kcontrol);
  2407. struct wcd938x_priv *wcd938x = NULL;
  2408. u32 mode_val;
  2409. unsigned int path = 0;
  2410. int ret = 0;
  2411. if (!component)
  2412. return -EINVAL;
  2413. wcd938x = snd_soc_component_get_drvdata(component);
  2414. if (!wcd938x)
  2415. return -EINVAL;
  2416. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2417. if (ret)
  2418. return ret;
  2419. mode_val = ucontrol->value.enumerated.item[0];
  2420. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2421. wcd938x->tx_mode[path] = mode_val;
  2422. return 0;
  2423. }
  2424. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2425. struct snd_ctl_elem_value *ucontrol)
  2426. {
  2427. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2428. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2429. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2430. return 0;
  2431. }
  2432. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2433. struct snd_ctl_elem_value *ucontrol)
  2434. {
  2435. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2436. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2437. u32 mode_val;
  2438. mode_val = ucontrol->value.enumerated.item[0];
  2439. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2440. if (wcd938x->variant == WCD9380) {
  2441. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2442. dev_info(component->dev,
  2443. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2444. __func__);
  2445. mode_val = CLS_H_ULP;
  2446. }
  2447. }
  2448. if (mode_val == CLS_H_NORMAL) {
  2449. dev_info(component->dev,
  2450. "%s:Invalid HPH Mode, default to class_AB\n",
  2451. __func__);
  2452. mode_val = CLS_H_ULP;
  2453. }
  2454. wcd938x->hph_mode = mode_val;
  2455. return 0;
  2456. }
  2457. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2458. struct snd_ctl_elem_value *ucontrol)
  2459. {
  2460. u8 ear_pa_gain = 0;
  2461. struct snd_soc_component *component =
  2462. snd_soc_kcontrol_component(kcontrol);
  2463. ear_pa_gain = snd_soc_component_read(component,
  2464. WCD938X_ANA_EAR_COMPANDER_CTL);
  2465. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2466. ucontrol->value.integer.value[0] = ear_pa_gain;
  2467. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2468. ear_pa_gain);
  2469. return 0;
  2470. }
  2471. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2472. struct snd_ctl_elem_value *ucontrol)
  2473. {
  2474. u8 ear_pa_gain = 0;
  2475. struct snd_soc_component *component =
  2476. snd_soc_kcontrol_component(kcontrol);
  2477. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2478. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2479. __func__, ucontrol->value.integer.value[0]);
  2480. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2481. if (!wcd938x->comp1_enable) {
  2482. snd_soc_component_update_bits(component,
  2483. WCD938X_ANA_EAR_COMPANDER_CTL,
  2484. 0x7C, ear_pa_gain);
  2485. }
  2486. return 0;
  2487. }
  2488. /* wcd938x_codec_get_dev_num - returns swr device number
  2489. * @component: Codec instance
  2490. *
  2491. * Return: swr device number on success or negative error
  2492. * code on failure.
  2493. */
  2494. int wcd938x_codec_get_dev_num(struct snd_soc_component *component)
  2495. {
  2496. struct wcd938x_priv *wcd938x;
  2497. if (!component)
  2498. return -EINVAL;
  2499. wcd938x = snd_soc_component_get_drvdata(component);
  2500. if (!wcd938x || !wcd938x->rx_swr_dev) {
  2501. pr_err("%s: wcd938x component is NULL\n", __func__);
  2502. return -EINVAL;
  2503. }
  2504. return wcd938x->rx_swr_dev->dev_num;
  2505. }
  2506. EXPORT_SYMBOL(wcd938x_codec_get_dev_num);
  2507. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2508. struct snd_ctl_elem_value *ucontrol)
  2509. {
  2510. struct snd_soc_component *component =
  2511. snd_soc_kcontrol_component(kcontrol);
  2512. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2513. bool hphr;
  2514. struct soc_multi_mixer_control *mc;
  2515. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2516. hphr = mc->shift;
  2517. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2518. wcd938x->comp1_enable;
  2519. return 0;
  2520. }
  2521. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2522. struct snd_ctl_elem_value *ucontrol)
  2523. {
  2524. struct snd_soc_component *component =
  2525. snd_soc_kcontrol_component(kcontrol);
  2526. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2527. int value = ucontrol->value.integer.value[0];
  2528. bool hphr;
  2529. struct soc_multi_mixer_control *mc;
  2530. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2531. hphr = mc->shift;
  2532. if (hphr)
  2533. wcd938x->comp2_enable = value;
  2534. else
  2535. wcd938x->comp1_enable = value;
  2536. return 0;
  2537. }
  2538. static int wcd938x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2539. struct snd_kcontrol *kcontrol,
  2540. int event)
  2541. {
  2542. struct snd_soc_component *component =
  2543. snd_soc_dapm_to_component(w->dapm);
  2544. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2545. struct wcd938x_pdata *pdata = NULL;
  2546. int ret = 0;
  2547. pdata = dev_get_platdata(wcd938x->dev);
  2548. if (!pdata) {
  2549. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2550. return -EINVAL;
  2551. }
  2552. if (!msm_cdc_is_ondemand_supply(wcd938x->dev,
  2553. wcd938x->supplies,
  2554. pdata->regulator,
  2555. pdata->num_supplies,
  2556. "cdc-vdd-buck"))
  2557. return 0;
  2558. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2559. w->name, event);
  2560. switch (event) {
  2561. case SND_SOC_DAPM_PRE_PMU:
  2562. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  2563. dev_dbg(component->dev,
  2564. "%s: buck already in enabled state\n",
  2565. __func__);
  2566. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2567. return 0;
  2568. }
  2569. ret = msm_cdc_enable_ondemand_supply(wcd938x->dev,
  2570. wcd938x->supplies,
  2571. pdata->regulator,
  2572. pdata->num_supplies,
  2573. "cdc-vdd-buck");
  2574. if (ret == -EINVAL) {
  2575. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2576. __func__);
  2577. return ret;
  2578. }
  2579. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2580. /*
  2581. * 200us sleep is required after LDO is enabled as per
  2582. * HW requirement
  2583. */
  2584. usleep_range(200, 250);
  2585. break;
  2586. case SND_SOC_DAPM_POST_PMD:
  2587. set_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2588. break;
  2589. }
  2590. return 0;
  2591. }
  2592. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2593. struct snd_ctl_elem_value *ucontrol)
  2594. {
  2595. struct snd_soc_component *component =
  2596. snd_soc_kcontrol_component(kcontrol);
  2597. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2598. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2599. return 0;
  2600. }
  2601. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2602. struct snd_ctl_elem_value *ucontrol)
  2603. {
  2604. struct snd_soc_component *component =
  2605. snd_soc_kcontrol_component(kcontrol);
  2606. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2607. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2608. return 0;
  2609. }
  2610. const char * const tx_master_ch_text[] = {
  2611. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2612. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2613. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2614. "SWRM_PCM_IN",
  2615. };
  2616. const struct soc_enum tx_master_ch_enum =
  2617. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2618. tx_master_ch_text);
  2619. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2620. {
  2621. u8 ch_type = 0;
  2622. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2623. ch_type = ADC1;
  2624. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2625. ch_type = ADC2;
  2626. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2627. ch_type = ADC3;
  2628. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2629. ch_type = ADC4;
  2630. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2631. ch_type = DMIC0;
  2632. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2633. ch_type = DMIC1;
  2634. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2635. ch_type = MBHC;
  2636. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2637. ch_type = DMIC2;
  2638. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2639. ch_type = DMIC3;
  2640. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2641. ch_type = DMIC4;
  2642. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2643. ch_type = DMIC5;
  2644. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2645. ch_type = DMIC6;
  2646. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2647. ch_type = DMIC7;
  2648. else
  2649. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2650. if (ch_type)
  2651. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2652. else
  2653. *ch_idx = -EINVAL;
  2654. }
  2655. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2656. struct snd_ctl_elem_value *ucontrol)
  2657. {
  2658. struct snd_soc_component *component =
  2659. snd_soc_kcontrol_component(kcontrol);
  2660. struct wcd938x_priv *wcd938x = NULL;
  2661. int slave_ch_idx = -EINVAL;
  2662. if (component == NULL)
  2663. return -EINVAL;
  2664. wcd938x = snd_soc_component_get_drvdata(component);
  2665. if (wcd938x == NULL)
  2666. return -EINVAL;
  2667. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2668. if (slave_ch_idx < 0 || slave_ch_idx >= WCD938X_MAX_SLAVE_CH_TYPES)
  2669. return -EINVAL;
  2670. ucontrol->value.integer.value[0] = wcd938x_slave_get_master_ch_val(
  2671. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2672. return 0;
  2673. }
  2674. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2675. struct snd_ctl_elem_value *ucontrol)
  2676. {
  2677. struct snd_soc_component *component =
  2678. snd_soc_kcontrol_component(kcontrol);
  2679. struct wcd938x_priv *wcd938x = NULL;
  2680. int slave_ch_idx = -EINVAL, idx = 0;
  2681. if (component == NULL)
  2682. return -EINVAL;
  2683. wcd938x = snd_soc_component_get_drvdata(component);
  2684. if (wcd938x == NULL)
  2685. return -EINVAL;
  2686. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2687. if (slave_ch_idx < 0 || slave_ch_idx >= WCD938X_MAX_SLAVE_CH_TYPES)
  2688. return -EINVAL;
  2689. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2690. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2691. __func__, ucontrol->value.enumerated.item[0]);
  2692. idx = ucontrol->value.enumerated.item[0];
  2693. if (idx < 0 || idx >= ARRAY_SIZE(swr_master_ch_map))
  2694. return -EINVAL;
  2695. wcd938x->tx_master_ch_map[slave_ch_idx] = wcd938x_slave_get_master_ch(idx);
  2696. return 0;
  2697. }
  2698. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2699. struct snd_ctl_elem_value *ucontrol)
  2700. {
  2701. struct snd_soc_component *component =
  2702. snd_soc_kcontrol_component(kcontrol);
  2703. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2704. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2705. return 0;
  2706. }
  2707. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2708. struct snd_ctl_elem_value *ucontrol)
  2709. {
  2710. struct snd_soc_component *component =
  2711. snd_soc_kcontrol_component(kcontrol);
  2712. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2713. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2714. return 0;
  2715. }
  2716. static const char * const tx_mode_mux_text_wcd9380[] = {
  2717. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2718. };
  2719. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2720. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2721. tx_mode_mux_text_wcd9380);
  2722. static const char * const tx_mode_mux_text[] = {
  2723. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2724. "ADC_ULP1", "ADC_ULP2",
  2725. };
  2726. static const struct soc_enum tx_mode_mux_enum =
  2727. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2728. tx_mode_mux_text);
  2729. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2730. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2731. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2732. "CLS_AB_LOHIFI",
  2733. };
  2734. static const char * const wcd938x_ear_pa_gain_text[] = {
  2735. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2736. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2737. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2738. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2739. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2740. };
  2741. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2742. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2743. rx_hph_mode_mux_text_wcd9380);
  2744. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2745. wcd938x_ear_pa_gain_text);
  2746. static const char * const rx_hph_mode_mux_text[] = {
  2747. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2748. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2749. };
  2750. static const struct soc_enum rx_hph_mode_mux_enum =
  2751. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2752. rx_hph_mode_mux_text);
  2753. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2754. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2755. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2756. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2757. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2758. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2759. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2760. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2761. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2762. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2763. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2764. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2765. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2766. };
  2767. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2768. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2769. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2770. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2771. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2772. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2773. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2774. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2775. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2776. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2777. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2778. };
  2779. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2780. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2781. wcd938x_get_compander, wcd938x_set_compander),
  2782. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2783. wcd938x_get_compander, wcd938x_set_compander),
  2784. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2785. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2786. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2787. wcd938x_bcs_get, wcd938x_bcs_put),
  2788. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2789. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2790. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2791. analog_gain),
  2792. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2793. analog_gain),
  2794. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2795. analog_gain),
  2796. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2797. analog_gain),
  2798. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2799. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2800. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2801. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2802. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2803. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2804. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2805. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2806. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2807. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2808. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2809. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2810. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2811. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2812. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2813. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2814. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2815. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2816. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2817. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2818. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2819. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2820. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2821. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2822. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2823. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2824. };
  2825. static const struct snd_kcontrol_new adc1_switch[] = {
  2826. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2827. };
  2828. static const struct snd_kcontrol_new adc2_switch[] = {
  2829. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2830. };
  2831. static const struct snd_kcontrol_new adc3_switch[] = {
  2832. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2833. };
  2834. static const struct snd_kcontrol_new adc4_switch[] = {
  2835. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2836. };
  2837. static const struct snd_kcontrol_new amic1_switch[] = {
  2838. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2839. };
  2840. static const struct snd_kcontrol_new amic2_switch[] = {
  2841. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2842. };
  2843. static const struct snd_kcontrol_new amic3_switch[] = {
  2844. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2845. };
  2846. static const struct snd_kcontrol_new amic4_switch[] = {
  2847. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2848. };
  2849. static const struct snd_kcontrol_new amic5_switch[] = {
  2850. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2851. };
  2852. static const struct snd_kcontrol_new amic6_switch[] = {
  2853. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2854. };
  2855. static const struct snd_kcontrol_new amic7_switch[] = {
  2856. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2857. };
  2858. static const struct snd_kcontrol_new va_amic1_switch[] = {
  2859. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2860. };
  2861. static const struct snd_kcontrol_new va_amic2_switch[] = {
  2862. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2863. };
  2864. static const struct snd_kcontrol_new va_amic3_switch[] = {
  2865. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2866. };
  2867. static const struct snd_kcontrol_new va_amic4_switch[] = {
  2868. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2869. };
  2870. static const struct snd_kcontrol_new va_amic5_switch[] = {
  2871. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2872. };
  2873. static const struct snd_kcontrol_new va_amic6_switch[] = {
  2874. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2875. };
  2876. static const struct snd_kcontrol_new va_amic7_switch[] = {
  2877. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2878. };
  2879. static const struct snd_kcontrol_new dmic1_switch[] = {
  2880. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2881. };
  2882. static const struct snd_kcontrol_new dmic2_switch[] = {
  2883. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2884. };
  2885. static const struct snd_kcontrol_new dmic3_switch[] = {
  2886. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2887. };
  2888. static const struct snd_kcontrol_new dmic4_switch[] = {
  2889. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2890. };
  2891. static const struct snd_kcontrol_new dmic5_switch[] = {
  2892. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2893. };
  2894. static const struct snd_kcontrol_new dmic6_switch[] = {
  2895. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2896. };
  2897. static const struct snd_kcontrol_new dmic7_switch[] = {
  2898. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2899. };
  2900. static const struct snd_kcontrol_new dmic8_switch[] = {
  2901. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2902. };
  2903. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2904. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2905. };
  2906. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2907. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2908. };
  2909. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2910. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2911. };
  2912. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2913. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2914. };
  2915. static const char * const adc2_mux_text[] = {
  2916. "INP2", "INP3"
  2917. };
  2918. static const struct soc_enum adc2_enum =
  2919. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2920. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2921. static const struct snd_kcontrol_new tx_adc2_mux =
  2922. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2923. static const char * const adc3_mux_text[] = {
  2924. "INP4", "INP6"
  2925. };
  2926. static const struct soc_enum adc3_enum =
  2927. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2928. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2929. static const struct snd_kcontrol_new tx_adc3_mux =
  2930. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2931. static const char * const adc4_mux_text[] = {
  2932. "INP5", "INP7"
  2933. };
  2934. static const struct soc_enum adc4_enum =
  2935. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2936. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2937. static const struct snd_kcontrol_new tx_adc4_mux =
  2938. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2939. static const char * const rdac3_mux_text[] = {
  2940. "RX1", "RX3"
  2941. };
  2942. static const char * const hdr12_mux_text[] = {
  2943. "NO_HDR12", "HDR12"
  2944. };
  2945. static const struct soc_enum hdr12_enum =
  2946. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2947. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2948. static const struct snd_kcontrol_new tx_hdr12_mux =
  2949. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2950. static const char * const hdr34_mux_text[] = {
  2951. "NO_HDR34", "HDR34"
  2952. };
  2953. static const struct soc_enum hdr34_enum =
  2954. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2955. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2956. static const struct snd_kcontrol_new tx_hdr34_mux =
  2957. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2958. static const struct soc_enum rdac3_enum =
  2959. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2960. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2961. static const struct snd_kcontrol_new rx_rdac3_mux =
  2962. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2963. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2964. /*input widgets*/
  2965. SND_SOC_DAPM_INPUT("AMIC1"),
  2966. SND_SOC_DAPM_INPUT("AMIC2"),
  2967. SND_SOC_DAPM_INPUT("AMIC3"),
  2968. SND_SOC_DAPM_INPUT("AMIC4"),
  2969. SND_SOC_DAPM_INPUT("AMIC5"),
  2970. SND_SOC_DAPM_INPUT("AMIC6"),
  2971. SND_SOC_DAPM_INPUT("AMIC7"),
  2972. SND_SOC_DAPM_INPUT("VA AMIC1"),
  2973. SND_SOC_DAPM_INPUT("VA AMIC2"),
  2974. SND_SOC_DAPM_INPUT("VA AMIC3"),
  2975. SND_SOC_DAPM_INPUT("VA AMIC4"),
  2976. SND_SOC_DAPM_INPUT("VA AMIC5"),
  2977. SND_SOC_DAPM_INPUT("VA AMIC6"),
  2978. SND_SOC_DAPM_INPUT("VA AMIC7"),
  2979. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2980. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2981. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2982. /*
  2983. * These dummy widgets are null connected to WCD938x dapm input and
  2984. * output widgets which are not actual path endpoints. This ensures
  2985. * dapm doesnt set these dapm input and output widgets as endpoints.
  2986. */
  2987. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2988. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2989. /*tx widgets*/
  2990. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2991. wcd938x_codec_enable_adc,
  2992. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2993. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2994. wcd938x_codec_enable_adc,
  2995. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2996. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2997. wcd938x_codec_enable_adc,
  2998. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2999. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  3000. wcd938x_codec_enable_adc,
  3001. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3002. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  3003. wcd938x_codec_enable_dmic,
  3004. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3005. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  3006. wcd938x_codec_enable_dmic,
  3007. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3008. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  3009. wcd938x_codec_enable_dmic,
  3010. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3011. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  3012. wcd938x_codec_enable_dmic,
  3013. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3014. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  3015. wcd938x_codec_enable_dmic,
  3016. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3017. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  3018. wcd938x_codec_enable_dmic,
  3019. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3020. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  3021. wcd938x_codec_enable_dmic,
  3022. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3023. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  3024. wcd938x_codec_enable_dmic,
  3025. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3026. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  3027. NULL, 0, wcd938x_enable_req,
  3028. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3029. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  3030. NULL, 0, wcd938x_enable_req,
  3031. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3032. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  3033. NULL, 0, wcd938x_enable_req,
  3034. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3035. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  3036. NULL, 0, wcd938x_enable_req,
  3037. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3038. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3039. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  3040. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3041. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3042. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  3043. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3044. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3045. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  3046. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3047. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3048. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  3049. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3050. SND_SOC_DAPM_MIXER_E("AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3051. amic5_switch, ARRAY_SIZE(amic5_switch), NULL,
  3052. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3053. SND_SOC_DAPM_MIXER_E("AMIC6_MIXER", SND_SOC_NOPM, 0, 0,
  3054. amic6_switch, ARRAY_SIZE(amic6_switch), NULL,
  3055. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3056. SND_SOC_DAPM_MIXER_E("AMIC7_MIXER", SND_SOC_NOPM, 0, 0,
  3057. amic7_switch, ARRAY_SIZE(amic7_switch), NULL,
  3058. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3059. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3060. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  3061. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3062. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3063. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  3064. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3065. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3066. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  3067. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3068. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3069. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3070. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3071. SND_SOC_DAPM_MIXER_E("VA_AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3072. va_amic5_switch, ARRAY_SIZE(va_amic5_switch), NULL,
  3073. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3074. SND_SOC_DAPM_MIXER_E("VA_AMIC6_MIXER", SND_SOC_NOPM, 0, 0,
  3075. va_amic6_switch, ARRAY_SIZE(va_amic6_switch), NULL,
  3076. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3077. SND_SOC_DAPM_MIXER_E("VA_AMIC7_MIXER", SND_SOC_NOPM, 0, 0,
  3078. va_amic7_switch, ARRAY_SIZE(va_amic7_switch), NULL,
  3079. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3080. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  3081. &tx_adc2_mux),
  3082. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  3083. &tx_adc3_mux),
  3084. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  3085. &tx_adc4_mux),
  3086. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  3087. &tx_hdr12_mux),
  3088. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  3089. &tx_hdr34_mux),
  3090. /*tx mixers*/
  3091. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  3092. adc1_switch, ARRAY_SIZE(adc1_switch),
  3093. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3094. SND_SOC_DAPM_POST_PMD),
  3095. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  3096. adc2_switch, ARRAY_SIZE(adc2_switch),
  3097. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3098. SND_SOC_DAPM_POST_PMD),
  3099. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  3100. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  3101. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3102. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  3103. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  3104. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3105. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3106. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3107. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3108. SND_SOC_DAPM_POST_PMD),
  3109. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3110. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3111. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3112. SND_SOC_DAPM_POST_PMD),
  3113. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3114. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3115. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3116. SND_SOC_DAPM_POST_PMD),
  3117. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3118. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3119. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3120. SND_SOC_DAPM_POST_PMD),
  3121. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3122. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3123. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3124. SND_SOC_DAPM_POST_PMD),
  3125. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3126. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3127. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3128. SND_SOC_DAPM_POST_PMD),
  3129. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  3130. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  3131. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3132. SND_SOC_DAPM_POST_PMD),
  3133. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  3134. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  3135. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3136. SND_SOC_DAPM_POST_PMD),
  3137. /* micbias widgets*/
  3138. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3139. wcd938x_codec_enable_micbias,
  3140. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3141. SND_SOC_DAPM_POST_PMD),
  3142. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3143. wcd938x_codec_enable_micbias,
  3144. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3145. SND_SOC_DAPM_POST_PMD),
  3146. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3147. wcd938x_codec_enable_micbias,
  3148. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3149. SND_SOC_DAPM_POST_PMD),
  3150. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3151. wcd938x_codec_enable_micbias,
  3152. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3153. SND_SOC_DAPM_POST_PMD),
  3154. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  3155. wcd938x_codec_force_enable_micbias,
  3156. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3157. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  3158. wcd938x_codec_force_enable_micbias,
  3159. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3160. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  3161. wcd938x_codec_force_enable_micbias,
  3162. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3163. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  3164. wcd938x_codec_force_enable_micbias,
  3165. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3166. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  3167. wcd938x_codec_enable_vdd_buck,
  3168. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3169. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  3170. wcd938x_enable_clsh,
  3171. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3172. /*rx widgets*/
  3173. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  3174. wcd938x_codec_enable_ear_pa,
  3175. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3176. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3177. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  3178. wcd938x_codec_enable_aux_pa,
  3179. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3180. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3181. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  3182. wcd938x_codec_enable_hphl_pa,
  3183. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3184. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3185. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  3186. wcd938x_codec_enable_hphr_pa,
  3187. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3188. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3189. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3190. wcd938x_codec_hphl_dac_event,
  3191. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3192. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3193. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3194. wcd938x_codec_hphr_dac_event,
  3195. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3196. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3197. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  3198. wcd938x_codec_ear_dac_event,
  3199. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3200. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3201. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  3202. wcd938x_codec_aux_dac_event,
  3203. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3204. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3205. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  3206. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  3207. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  3208. SND_SOC_DAPM_POST_PMD),
  3209. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  3210. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  3211. SND_SOC_DAPM_POST_PMD),
  3212. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  3213. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  3214. SND_SOC_DAPM_POST_PMD),
  3215. /* rx mixer widgets*/
  3216. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  3217. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  3218. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  3219. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  3220. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3221. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3222. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3223. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3224. /*output widgets tx*/
  3225. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  3226. /*output widgets rx*/
  3227. SND_SOC_DAPM_OUTPUT("EAR"),
  3228. SND_SOC_DAPM_OUTPUT("AUX"),
  3229. SND_SOC_DAPM_OUTPUT("HPHL"),
  3230. SND_SOC_DAPM_OUTPUT("HPHR"),
  3231. /* micbias pull up widgets*/
  3232. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3233. wcd938x_codec_enable_micbias_pullup,
  3234. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3235. SND_SOC_DAPM_POST_PMD),
  3236. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3237. wcd938x_codec_enable_micbias_pullup,
  3238. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3239. SND_SOC_DAPM_POST_PMD),
  3240. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3241. wcd938x_codec_enable_micbias_pullup,
  3242. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3243. SND_SOC_DAPM_POST_PMD),
  3244. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3245. wcd938x_codec_enable_micbias_pullup,
  3246. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3247. SND_SOC_DAPM_POST_PMD),
  3248. };
  3249. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  3250. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3251. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  3252. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  3253. {"ADC1 REQ", NULL, "ADC1"},
  3254. {"ADC1", NULL, "AMIC1_MIXER"},
  3255. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3256. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3257. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3258. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  3259. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  3260. {"ADC2 REQ", NULL, "ADC2"},
  3261. {"ADC2", NULL, "HDR12 MUX"},
  3262. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  3263. {"HDR12 MUX", "HDR12", "AMIC1_MIXER"},
  3264. {"ADC2 MUX", "INP3", "AMIC3_MIXER"},
  3265. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3266. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3267. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3268. {"ADC2 MUX", "INP2", "AMIC2_MIXER"},
  3269. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3270. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3271. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3272. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  3273. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  3274. {"ADC3 REQ", NULL, "ADC3"},
  3275. {"ADC3", NULL, "HDR34 MUX"},
  3276. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  3277. {"HDR34 MUX", "HDR34", "AMIC5_MIXER"},
  3278. {"ADC3 MUX", "INP4", "AMIC4_MIXER"},
  3279. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3280. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3281. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3282. {"ADC3 MUX", "INP6", "AMIC6_MIXER"},
  3283. {"AMIC6_MIXER", "Switch", "AMIC6"},
  3284. {"AMIC6_MIXER", NULL, "VA_AMIC6_MIXER"},
  3285. {"VA_AMIC6_MIXER", "Switch", "VA AMIC6"},
  3286. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  3287. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  3288. {"ADC4 REQ", NULL, "ADC4"},
  3289. {"ADC4", NULL, "ADC4 MUX"},
  3290. {"ADC4 MUX", "INP5", "AMIC5_MIXER"},
  3291. {"AMIC5_MIXER", "Switch", "AMIC5"},
  3292. {"AMIC5_MIXER", NULL, "VA_AMIC5_MIXER"},
  3293. {"VA_AMIC5_MIXER", "Switch", "VA AMIC5"},
  3294. {"ADC4 MUX", "INP7", "AMIC7_MIXER"},
  3295. {"AMIC7_MIXER", "Switch", "AMIC7"},
  3296. {"AMIC7_MIXER", NULL, "VA_AMIC7_MIXER"},
  3297. {"VA_AMIC7_MIXER", "Switch", "VA AMIC7"},
  3298. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  3299. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3300. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  3301. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3302. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  3303. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3304. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  3305. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3306. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  3307. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3308. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  3309. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3310. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  3311. {"DMIC7_MIXER", "Switch", "DMIC7"},
  3312. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  3313. {"DMIC8_MIXER", "Switch", "DMIC8"},
  3314. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  3315. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3316. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3317. {"RX1", NULL, "IN1_HPHL"},
  3318. {"RDAC1", NULL, "RX1"},
  3319. {"HPHL_RDAC", "Switch", "RDAC1"},
  3320. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3321. {"HPHL", NULL, "HPHL PGA"},
  3322. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  3323. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3324. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3325. {"RX2", NULL, "IN2_HPHR"},
  3326. {"RDAC2", NULL, "RX2"},
  3327. {"HPHR_RDAC", "Switch", "RDAC2"},
  3328. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3329. {"HPHR", NULL, "HPHR PGA"},
  3330. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  3331. {"IN3_AUX", NULL, "VDD_BUCK"},
  3332. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3333. {"RX3", NULL, "IN3_AUX"},
  3334. {"RDAC4", NULL, "RX3"},
  3335. {"AUX_RDAC", "Switch", "RDAC4"},
  3336. {"AUX PGA", NULL, "AUX_RDAC"},
  3337. {"AUX", NULL, "AUX PGA"},
  3338. {"RDAC3_MUX", "RX3", "RX3"},
  3339. {"RDAC3_MUX", "RX1", "RX1"},
  3340. {"RDAC3", NULL, "RDAC3_MUX"},
  3341. {"EAR_RDAC", "Switch", "RDAC3"},
  3342. {"EAR PGA", NULL, "EAR_RDAC"},
  3343. {"EAR", NULL, "EAR PGA"},
  3344. };
  3345. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  3346. void *file_private_data,
  3347. struct file *file,
  3348. char __user *buf, size_t count,
  3349. loff_t pos)
  3350. {
  3351. struct wcd938x_priv *priv;
  3352. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  3353. int len = 0;
  3354. priv = (struct wcd938x_priv *) entry->private_data;
  3355. if (!priv) {
  3356. pr_err("%s: wcd938x priv is null\n", __func__);
  3357. return -EINVAL;
  3358. }
  3359. switch (priv->version) {
  3360. case WCD938X_VERSION_1_0:
  3361. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  3362. break;
  3363. default:
  3364. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3365. }
  3366. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3367. }
  3368. static struct snd_info_entry_ops wcd938x_info_ops = {
  3369. .read = wcd938x_version_read,
  3370. };
  3371. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  3372. void *file_private_data,
  3373. struct file *file,
  3374. char __user *buf, size_t count,
  3375. loff_t pos)
  3376. {
  3377. struct wcd938x_priv *priv;
  3378. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  3379. int len = 0;
  3380. priv = (struct wcd938x_priv *) entry->private_data;
  3381. if (!priv) {
  3382. pr_err("%s: wcd938x priv is null\n", __func__);
  3383. return -EINVAL;
  3384. }
  3385. switch (priv->variant) {
  3386. case WCD9380:
  3387. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  3388. break;
  3389. case WCD9385:
  3390. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  3391. break;
  3392. default:
  3393. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3394. }
  3395. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3396. }
  3397. static struct snd_info_entry_ops wcd938x_variant_ops = {
  3398. .read = wcd938x_variant_read,
  3399. };
  3400. /*
  3401. * wcd938x_get_codec_variant
  3402. * @component: component instance
  3403. *
  3404. * Return: codec variant or -EINVAL in error.
  3405. */
  3406. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  3407. {
  3408. struct wcd938x_priv *priv = NULL;
  3409. if (!component)
  3410. return -EINVAL;
  3411. priv = snd_soc_component_get_drvdata(component);
  3412. if (!priv) {
  3413. dev_err(component->dev,
  3414. "%s:wcd938x not probed\n", __func__);
  3415. return 0;
  3416. }
  3417. return priv->variant;
  3418. }
  3419. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3420. /*
  3421. * wcd938x_info_create_codec_entry - creates wcd938x module
  3422. * @codec_root: The parent directory
  3423. * @component: component instance
  3424. *
  3425. * Creates wcd938x module, variant and version entry under the given
  3426. * parent directory.
  3427. *
  3428. * Return: 0 on success or negative error code on failure.
  3429. */
  3430. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3431. struct snd_soc_component *component)
  3432. {
  3433. struct snd_info_entry *version_entry;
  3434. struct snd_info_entry *variant_entry;
  3435. struct wcd938x_priv *priv;
  3436. struct snd_soc_card *card;
  3437. if (!codec_root || !component)
  3438. return -EINVAL;
  3439. priv = snd_soc_component_get_drvdata(component);
  3440. if (priv->entry) {
  3441. dev_dbg(priv->dev,
  3442. "%s:wcd938x module already created\n", __func__);
  3443. return 0;
  3444. }
  3445. card = component->card;
  3446. priv->entry = snd_info_create_module_entry(codec_root->module,
  3447. "wcd938x", codec_root);
  3448. if (!priv->entry) {
  3449. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3450. __func__);
  3451. return -ENOMEM;
  3452. }
  3453. priv->entry->mode = S_IFDIR | 0555;
  3454. if (snd_info_register(priv->entry) < 0) {
  3455. snd_info_free_entry(priv->entry);
  3456. return -ENOMEM;
  3457. }
  3458. version_entry = snd_info_create_card_entry(card->snd_card,
  3459. "version",
  3460. priv->entry);
  3461. if (!version_entry) {
  3462. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3463. __func__);
  3464. snd_info_free_entry(priv->entry);
  3465. return -ENOMEM;
  3466. }
  3467. version_entry->private_data = priv;
  3468. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3469. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3470. version_entry->c.ops = &wcd938x_info_ops;
  3471. if (snd_info_register(version_entry) < 0) {
  3472. snd_info_free_entry(version_entry);
  3473. snd_info_free_entry(priv->entry);
  3474. return -ENOMEM;
  3475. }
  3476. priv->version_entry = version_entry;
  3477. variant_entry = snd_info_create_card_entry(card->snd_card,
  3478. "variant",
  3479. priv->entry);
  3480. if (!variant_entry) {
  3481. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3482. __func__);
  3483. snd_info_free_entry(version_entry);
  3484. snd_info_free_entry(priv->entry);
  3485. return -ENOMEM;
  3486. }
  3487. variant_entry->private_data = priv;
  3488. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3489. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3490. variant_entry->c.ops = &wcd938x_variant_ops;
  3491. if (snd_info_register(variant_entry) < 0) {
  3492. snd_info_free_entry(variant_entry);
  3493. snd_info_free_entry(version_entry);
  3494. snd_info_free_entry(priv->entry);
  3495. return -ENOMEM;
  3496. }
  3497. priv->variant_entry = variant_entry;
  3498. return 0;
  3499. }
  3500. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3501. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3502. struct wcd938x_pdata *pdata)
  3503. {
  3504. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3505. int rc = 0;
  3506. if (!pdata) {
  3507. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3508. return -ENODEV;
  3509. }
  3510. /* set micbias voltage */
  3511. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3512. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3513. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3514. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3515. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3516. vout_ctl_4 < 0) {
  3517. rc = -EINVAL;
  3518. goto done;
  3519. }
  3520. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3521. vout_ctl_1);
  3522. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3523. vout_ctl_2);
  3524. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3525. vout_ctl_3);
  3526. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3527. vout_ctl_4);
  3528. done:
  3529. return rc;
  3530. }
  3531. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3532. {
  3533. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3534. struct snd_soc_dapm_context *dapm =
  3535. snd_soc_component_get_dapm(component);
  3536. int variant;
  3537. int ret = -EINVAL;
  3538. dev_info(component->dev, "%s()\n", __func__);
  3539. wcd938x = snd_soc_component_get_drvdata(component);
  3540. if (!wcd938x)
  3541. return -EINVAL;
  3542. wcd938x->component = component;
  3543. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3544. devm_regmap_qti_debugfs_register(&wcd938x->tx_swr_dev->dev, wcd938x->regmap);
  3545. variant = (snd_soc_component_read(component,
  3546. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3547. wcd938x->variant = variant;
  3548. wcd938x->fw_data = devm_kzalloc(component->dev,
  3549. sizeof(*(wcd938x->fw_data)),
  3550. GFP_KERNEL);
  3551. if (!wcd938x->fw_data) {
  3552. dev_err(component->dev, "Failed to allocate fw_data\n");
  3553. ret = -ENOMEM;
  3554. goto err;
  3555. }
  3556. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3557. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3558. WCD9XXX_CODEC_HWDEP_NODE, component);
  3559. if (ret < 0) {
  3560. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3561. goto err_hwdep;
  3562. }
  3563. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3564. if (ret) {
  3565. pr_err("%s: mbhc initialization failed\n", __func__);
  3566. goto err_hwdep;
  3567. }
  3568. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Playback");
  3569. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Capture");
  3570. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3571. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3572. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3573. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3574. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3575. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3576. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3577. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3578. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3579. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3580. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3581. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC5");
  3582. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC6");
  3583. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC7");
  3584. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3585. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3586. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3587. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3588. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3589. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3590. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3591. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3592. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  3593. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  3594. snd_soc_dapm_sync(dapm);
  3595. wcd_cls_h_init(&wcd938x->clsh_info);
  3596. wcd938x_init_reg(component);
  3597. if (wcd938x->variant == WCD9380) {
  3598. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3599. ARRAY_SIZE(wcd9380_snd_controls));
  3600. if (ret < 0) {
  3601. dev_err(component->dev,
  3602. "%s: Failed to add snd ctrls for variant: %d\n",
  3603. __func__, wcd938x->variant);
  3604. goto err_hwdep;
  3605. }
  3606. }
  3607. if (wcd938x->variant == WCD9385) {
  3608. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3609. ARRAY_SIZE(wcd9385_snd_controls));
  3610. if (ret < 0) {
  3611. dev_err(component->dev,
  3612. "%s: Failed to add snd ctrls for variant: %d\n",
  3613. __func__, wcd938x->variant);
  3614. goto err_hwdep;
  3615. }
  3616. }
  3617. wcd938x->version = WCD938X_VERSION_1_0;
  3618. /* Register event notifier */
  3619. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3620. if (wcd938x->register_notifier) {
  3621. ret = wcd938x->register_notifier(wcd938x->handle,
  3622. &wcd938x->nblock,
  3623. true);
  3624. if (ret) {
  3625. dev_err(component->dev,
  3626. "%s: Failed to register notifier %d\n",
  3627. __func__, ret);
  3628. return ret;
  3629. }
  3630. }
  3631. return ret;
  3632. err_hwdep:
  3633. wcd938x->fw_data = NULL;
  3634. err:
  3635. return ret;
  3636. }
  3637. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3638. {
  3639. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3640. if (!wcd938x) {
  3641. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3642. __func__);
  3643. return;
  3644. }
  3645. if (wcd938x->register_notifier)
  3646. wcd938x->register_notifier(wcd938x->handle,
  3647. &wcd938x->nblock,
  3648. false);
  3649. }
  3650. static int wcd938x_soc_codec_suspend(struct snd_soc_component *component)
  3651. {
  3652. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3653. if (!wcd938x)
  3654. return 0;
  3655. wcd938x->dapm_bias_off = true;
  3656. return 0;
  3657. }
  3658. static int wcd938x_soc_codec_resume(struct snd_soc_component *component)
  3659. {
  3660. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3661. if (!wcd938x)
  3662. return 0;
  3663. wcd938x->dapm_bias_off = false;
  3664. return 0;
  3665. }
  3666. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3667. .name = WCD938X_DRV_NAME,
  3668. .probe = wcd938x_soc_codec_probe,
  3669. .remove = wcd938x_soc_codec_remove,
  3670. .controls = wcd938x_snd_controls,
  3671. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3672. .dapm_widgets = wcd938x_dapm_widgets,
  3673. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3674. .dapm_routes = wcd938x_audio_map,
  3675. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3676. .suspend = wcd938x_soc_codec_suspend,
  3677. .resume = wcd938x_soc_codec_resume,
  3678. };
  3679. static int wcd938x_reset(struct device *dev)
  3680. {
  3681. struct wcd938x_priv *wcd938x = NULL;
  3682. int rc = 0;
  3683. int value = 0;
  3684. if (!dev)
  3685. return -ENODEV;
  3686. wcd938x = dev_get_drvdata(dev);
  3687. if (!wcd938x)
  3688. return -EINVAL;
  3689. if (!wcd938x->rst_np) {
  3690. dev_err(dev, "%s: reset gpio device node not specified\n",
  3691. __func__);
  3692. return -EINVAL;
  3693. }
  3694. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3695. if (value > 0)
  3696. return 0;
  3697. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3698. if (rc) {
  3699. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3700. __func__);
  3701. return rc;
  3702. }
  3703. /* 20us sleep required after pulling the reset gpio to LOW */
  3704. usleep_range(20, 30);
  3705. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3706. if (rc) {
  3707. dev_err(dev, "%s: wcd active state request fail!\n",
  3708. __func__);
  3709. return rc;
  3710. }
  3711. /* 20us sleep required after pulling the reset gpio to HIGH */
  3712. usleep_range(20, 30);
  3713. return rc;
  3714. }
  3715. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3716. u32 *val)
  3717. {
  3718. int rc = 0;
  3719. rc = of_property_read_u32(dev->of_node, name, val);
  3720. if (rc)
  3721. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3722. __func__, name, dev->of_node->full_name);
  3723. return rc;
  3724. }
  3725. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3726. struct wcd938x_micbias_setting *mb)
  3727. {
  3728. u32 prop_val = 0;
  3729. int rc = 0;
  3730. /* MB1 */
  3731. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3732. NULL)) {
  3733. rc = wcd938x_read_of_property_u32(dev,
  3734. "qcom,cdc-micbias1-mv",
  3735. &prop_val);
  3736. if (!rc)
  3737. mb->micb1_mv = prop_val;
  3738. } else {
  3739. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3740. __func__);
  3741. }
  3742. /* MB2 */
  3743. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3744. NULL)) {
  3745. rc = wcd938x_read_of_property_u32(dev,
  3746. "qcom,cdc-micbias2-mv",
  3747. &prop_val);
  3748. if (!rc)
  3749. mb->micb2_mv = prop_val;
  3750. } else {
  3751. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3752. __func__);
  3753. }
  3754. /* MB3 */
  3755. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3756. NULL)) {
  3757. rc = wcd938x_read_of_property_u32(dev,
  3758. "qcom,cdc-micbias3-mv",
  3759. &prop_val);
  3760. if (!rc)
  3761. mb->micb3_mv = prop_val;
  3762. } else {
  3763. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3764. __func__);
  3765. }
  3766. /* MB4 */
  3767. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3768. NULL)) {
  3769. rc = wcd938x_read_of_property_u32(dev,
  3770. "qcom,cdc-micbias4-mv",
  3771. &prop_val);
  3772. if (!rc)
  3773. mb->micb4_mv = prop_val;
  3774. } else {
  3775. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3776. __func__);
  3777. }
  3778. }
  3779. static int wcd938x_reset_low(struct device *dev)
  3780. {
  3781. struct wcd938x_priv *wcd938x = NULL;
  3782. int rc = 0;
  3783. if (!dev)
  3784. return -ENODEV;
  3785. wcd938x = dev_get_drvdata(dev);
  3786. if (!wcd938x)
  3787. return -EINVAL;
  3788. if (!wcd938x->rst_np) {
  3789. dev_err(dev, "%s: reset gpio device node not specified\n",
  3790. __func__);
  3791. return -EINVAL;
  3792. }
  3793. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3794. if (rc) {
  3795. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3796. __func__);
  3797. return rc;
  3798. }
  3799. /* 20us sleep required after pulling the reset gpio to LOW */
  3800. usleep_range(20, 30);
  3801. return rc;
  3802. }
  3803. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3804. {
  3805. struct wcd938x_pdata *pdata = NULL;
  3806. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3807. GFP_KERNEL);
  3808. if (!pdata)
  3809. return NULL;
  3810. pdata->rst_np = of_parse_phandle(dev->of_node,
  3811. "qcom,wcd-rst-gpio-node", 0);
  3812. if (!pdata->rst_np) {
  3813. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3814. __func__, "qcom,wcd-rst-gpio-node",
  3815. dev->of_node->full_name);
  3816. return NULL;
  3817. }
  3818. /* Parse power supplies */
  3819. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3820. &pdata->num_supplies);
  3821. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3822. dev_err(dev, "%s: no power supplies defined for codec\n",
  3823. __func__);
  3824. return NULL;
  3825. }
  3826. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3827. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3828. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3829. return pdata;
  3830. }
  3831. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3832. {
  3833. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3834. __func__, irq);
  3835. return IRQ_HANDLED;
  3836. }
  3837. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3838. {
  3839. .name = "wcd938x_cdc",
  3840. .playback = {
  3841. .stream_name = "WCD938X_AIF Playback",
  3842. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3843. .formats = WCD938X_FORMATS,
  3844. .rate_max = 384000,
  3845. .rate_min = 8000,
  3846. .channels_min = 1,
  3847. .channels_max = 4,
  3848. },
  3849. .capture = {
  3850. .stream_name = "WCD938X_AIF Capture",
  3851. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3852. .formats = WCD938X_FORMATS,
  3853. .rate_max = 384000,
  3854. .rate_min = 8000,
  3855. .channels_min = 1,
  3856. .channels_max = 4,
  3857. },
  3858. },
  3859. };
  3860. static int wcd938x_bind(struct device *dev)
  3861. {
  3862. int ret = 0, i = 0;
  3863. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3864. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3865. /*
  3866. * Add 5msec delay to provide sufficient time for
  3867. * soundwire auto enumeration of slave devices as
  3868. * as per HW requirement.
  3869. */
  3870. usleep_range(5000, 5010);
  3871. ret = component_bind_all(dev, wcd938x);
  3872. if (ret) {
  3873. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3874. __func__, ret);
  3875. return ret;
  3876. }
  3877. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3878. if (!wcd938x->rx_swr_dev) {
  3879. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3880. __func__);
  3881. ret = -ENODEV;
  3882. goto err;
  3883. }
  3884. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3885. if (!wcd938x->tx_swr_dev) {
  3886. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3887. __func__);
  3888. ret = -ENODEV;
  3889. goto err;
  3890. }
  3891. swr_init_port_params(wcd938x->tx_swr_dev, SWR_NUM_PORTS,
  3892. wcd938x->swr_tx_port_params);
  3893. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3894. &wcd938x_regmap_config);
  3895. if (!wcd938x->regmap) {
  3896. dev_err(dev, "%s: Regmap init failed\n",
  3897. __func__);
  3898. goto err;
  3899. }
  3900. /* Set all interupts as edge triggered */
  3901. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3902. regmap_write(wcd938x->regmap,
  3903. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3904. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3905. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3906. wcd938x->irq_info.codec_name = "WCD938X";
  3907. wcd938x->irq_info.regmap = wcd938x->regmap;
  3908. wcd938x->irq_info.dev = dev;
  3909. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3910. if (ret) {
  3911. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3912. __func__, ret);
  3913. goto err;
  3914. }
  3915. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3916. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3917. if (ret < 0) {
  3918. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3919. goto err_irq;
  3920. }
  3921. /* Request for watchdog interrupt */
  3922. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3923. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3924. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3925. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3926. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3927. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3928. /* Disable watchdog interrupt for HPH and AUX */
  3929. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3930. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3931. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3932. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3933. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3934. if (ret) {
  3935. dev_err(dev, "%s: Codec registration failed\n",
  3936. __func__);
  3937. goto err_irq;
  3938. }
  3939. wcd938x->dev_up = true;
  3940. return ret;
  3941. err_irq:
  3942. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3943. err:
  3944. component_unbind_all(dev, wcd938x);
  3945. return ret;
  3946. }
  3947. static void wcd938x_unbind(struct device *dev)
  3948. {
  3949. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3950. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3951. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3952. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3953. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3954. snd_soc_unregister_component(dev);
  3955. component_unbind_all(dev, wcd938x);
  3956. }
  3957. static const struct of_device_id wcd938x_dt_match[] = {
  3958. { .compatible = "qcom,wcd938x-codec", .data = "wcd938x"},
  3959. {}
  3960. };
  3961. static const struct component_master_ops wcd938x_comp_ops = {
  3962. .bind = wcd938x_bind,
  3963. .unbind = wcd938x_unbind,
  3964. };
  3965. static int wcd938x_compare_of(struct device *dev, void *data)
  3966. {
  3967. return dev->of_node == data;
  3968. }
  3969. static void wcd938x_release_of(struct device *dev, void *data)
  3970. {
  3971. of_node_put(data);
  3972. }
  3973. static int wcd938x_add_slave_components(struct device *dev,
  3974. struct component_match **matchptr)
  3975. {
  3976. struct device_node *np, *rx_node, *tx_node;
  3977. np = dev->of_node;
  3978. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3979. if (!rx_node) {
  3980. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3981. return -ENODEV;
  3982. }
  3983. of_node_get(rx_node);
  3984. component_match_add_release(dev, matchptr,
  3985. wcd938x_release_of,
  3986. wcd938x_compare_of,
  3987. rx_node);
  3988. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3989. if (!tx_node) {
  3990. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3991. return -ENODEV;
  3992. }
  3993. of_node_get(tx_node);
  3994. component_match_add_release(dev, matchptr,
  3995. wcd938x_release_of,
  3996. wcd938x_compare_of,
  3997. tx_node);
  3998. return 0;
  3999. }
  4000. static int wcd938x_probe(struct platform_device *pdev)
  4001. {
  4002. struct component_match *match = NULL;
  4003. struct wcd938x_priv *wcd938x = NULL;
  4004. struct wcd938x_pdata *pdata = NULL;
  4005. struct wcd_ctrl_platform_data *plat_data = NULL;
  4006. struct device *dev = &pdev->dev;
  4007. int ret;
  4008. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  4009. GFP_KERNEL);
  4010. if (!wcd938x)
  4011. return -ENOMEM;
  4012. dev_set_drvdata(dev, wcd938x);
  4013. wcd938x->dev = dev;
  4014. pdata = wcd938x_populate_dt_data(dev);
  4015. if (!pdata) {
  4016. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  4017. return -EINVAL;
  4018. }
  4019. dev->platform_data = pdata;
  4020. wcd938x->rst_np = pdata->rst_np;
  4021. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  4022. pdata->regulator, pdata->num_supplies);
  4023. if (!wcd938x->supplies) {
  4024. dev_err(dev, "%s: Cannot init wcd supplies\n",
  4025. __func__);
  4026. return ret;
  4027. }
  4028. plat_data = dev_get_platdata(dev->parent);
  4029. if (!plat_data) {
  4030. dev_err(dev, "%s: platform data from parent is NULL\n",
  4031. __func__);
  4032. return -EINVAL;
  4033. }
  4034. wcd938x->handle = (void *)plat_data->handle;
  4035. if (!wcd938x->handle) {
  4036. dev_err(dev, "%s: handle is NULL\n", __func__);
  4037. return -EINVAL;
  4038. }
  4039. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  4040. if (!wcd938x->update_wcd_event) {
  4041. dev_err(dev, "%s: update_wcd_event api is null!\n",
  4042. __func__);
  4043. return -EINVAL;
  4044. }
  4045. wcd938x->register_notifier = plat_data->register_notifier;
  4046. if (!wcd938x->register_notifier) {
  4047. dev_err(dev, "%s: register_notifier api is null!\n",
  4048. __func__);
  4049. return -EINVAL;
  4050. }
  4051. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  4052. pdata->regulator,
  4053. pdata->num_supplies);
  4054. if (ret) {
  4055. dev_err(dev, "%s: wcd static supply enable failed!\n",
  4056. __func__);
  4057. return ret;
  4058. }
  4059. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  4060. CODEC_RX);
  4061. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  4062. CODEC_TX);
  4063. if (ret) {
  4064. dev_err(dev, "Failed to read port mapping\n");
  4065. goto err;
  4066. }
  4067. ret = wcd938x_parse_port_params(dev, "qcom,swr-tx-port-params",
  4068. CODEC_TX);
  4069. if (ret) {
  4070. dev_err(dev, "Failed to read port params\n");
  4071. goto err;
  4072. }
  4073. mutex_init(&wcd938x->wakeup_lock);
  4074. mutex_init(&wcd938x->micb_lock);
  4075. ret = wcd938x_add_slave_components(dev, &match);
  4076. if (ret)
  4077. goto err_lock_init;
  4078. wcd938x_reset(dev);
  4079. wcd938x->wakeup = wcd938x_wakeup;
  4080. return component_master_add_with_match(dev,
  4081. &wcd938x_comp_ops, match);
  4082. err_lock_init:
  4083. mutex_destroy(&wcd938x->micb_lock);
  4084. mutex_destroy(&wcd938x->wakeup_lock);
  4085. err:
  4086. return ret;
  4087. }
  4088. static int wcd938x_remove(struct platform_device *pdev)
  4089. {
  4090. struct wcd938x_priv *wcd938x = NULL;
  4091. wcd938x = platform_get_drvdata(pdev);
  4092. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  4093. mutex_destroy(&wcd938x->micb_lock);
  4094. mutex_destroy(&wcd938x->wakeup_lock);
  4095. dev_set_drvdata(&pdev->dev, NULL);
  4096. return 0;
  4097. }
  4098. #ifdef CONFIG_PM_SLEEP
  4099. static int wcd938x_suspend(struct device *dev)
  4100. {
  4101. struct wcd938x_priv *wcd938x = NULL;
  4102. int ret = 0;
  4103. struct wcd938x_pdata *pdata = NULL;
  4104. if (!dev)
  4105. return -ENODEV;
  4106. wcd938x = dev_get_drvdata(dev);
  4107. if (!wcd938x)
  4108. return -EINVAL;
  4109. pdata = dev_get_platdata(wcd938x->dev);
  4110. if (!pdata) {
  4111. dev_err(dev, "%s: pdata is NULL\n", __func__);
  4112. return -EINVAL;
  4113. }
  4114. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  4115. ret = msm_cdc_disable_ondemand_supply(wcd938x->dev,
  4116. wcd938x->supplies,
  4117. pdata->regulator,
  4118. pdata->num_supplies,
  4119. "cdc-vdd-buck");
  4120. if (ret == -EINVAL) {
  4121. dev_err(dev, "%s: vdd buck is not disabled\n",
  4122. __func__);
  4123. return 0;
  4124. }
  4125. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  4126. }
  4127. if (wcd938x->dapm_bias_off) {
  4128. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  4129. wcd938x->supplies,
  4130. pdata->regulator,
  4131. pdata->num_supplies,
  4132. true);
  4133. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  4134. }
  4135. return 0;
  4136. }
  4137. static int wcd938x_resume(struct device *dev)
  4138. {
  4139. struct wcd938x_priv *wcd938x = NULL;
  4140. struct wcd938x_pdata *pdata = NULL;
  4141. if (!dev)
  4142. return -ENODEV;
  4143. wcd938x = dev_get_drvdata(dev);
  4144. if (!wcd938x)
  4145. return -EINVAL;
  4146. pdata = dev_get_platdata(wcd938x->dev);
  4147. if (!pdata) {
  4148. dev_err(dev, "%s: pdata is NULL\n", __func__);
  4149. return -EINVAL;
  4150. }
  4151. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask)) {
  4152. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  4153. wcd938x->supplies,
  4154. pdata->regulator,
  4155. pdata->num_supplies,
  4156. false);
  4157. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  4158. }
  4159. return 0;
  4160. }
  4161. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  4162. .suspend_late = wcd938x_suspend,
  4163. .resume_early = wcd938x_resume,
  4164. };
  4165. #endif
  4166. static struct platform_driver wcd938x_codec_driver = {
  4167. .probe = wcd938x_probe,
  4168. .remove = wcd938x_remove,
  4169. .driver = {
  4170. .name = "wcd938x_codec",
  4171. .owner = THIS_MODULE,
  4172. .of_match_table = of_match_ptr(wcd938x_dt_match),
  4173. #ifdef CONFIG_PM_SLEEP
  4174. .pm = &wcd938x_dev_pm_ops,
  4175. #endif
  4176. .suppress_bind_attrs = true,
  4177. },
  4178. };
  4179. module_platform_driver(wcd938x_codec_driver);
  4180. MODULE_DESCRIPTION("WCD938X Codec driver");
  4181. MODULE_LICENSE("GPL v2");