dp_tx.c 115 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "enet.h"
  33. #include "dp_internal.h"
  34. #ifdef FEATURE_WDS
  35. #include "dp_txrx_wds.h"
  36. #endif
  37. #define DP_TX_QUEUE_MASK 0x3
  38. /* TODO Add support in TSO */
  39. #define DP_DESC_NUM_FRAG(x) 0
  40. /* disable TQM_BYPASS */
  41. #define TQM_BYPASS_WAR 0
  42. /* invalid peer id for reinject*/
  43. #define DP_INVALID_PEER 0XFFFE
  44. /*mapping between hal encrypt type and cdp_sec_type*/
  45. #define MAX_CDP_SEC_TYPE 12
  46. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  47. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  48. HAL_TX_ENCRYPT_TYPE_WEP_128,
  49. HAL_TX_ENCRYPT_TYPE_WEP_104,
  50. HAL_TX_ENCRYPT_TYPE_WEP_40,
  51. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  52. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  53. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  54. HAL_TX_ENCRYPT_TYPE_WAPI,
  55. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  56. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  57. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  58. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  59. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  60. #include "dp_tx_capture.h"
  61. #endif
  62. /**
  63. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  64. * @vdev: DP Virtual device handle
  65. * @nbuf: Buffer pointer
  66. * @queue: queue ids container for nbuf
  67. *
  68. * TX packet queue has 2 instances, software descriptors id and dma ring id
  69. * Based on tx feature and hardware configuration queue id combination
  70. * could be different.
  71. * For example -
  72. * With XPS enabled,all TX descriptor pools and dma ring are assigned
  73. * per cpu id
  74. * With no XPS,lock based resource protection, Descriptor pool ids are
  75. * different for each vdev, dma ring id will be same as single pdev id
  76. *
  77. * Return: None
  78. */
  79. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  80. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  81. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  82. {
  83. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  84. queue->desc_pool_id = queue_offset;
  85. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  87. "%s, pool_id:%d ring_id: %d",
  88. __func__, queue->desc_pool_id, queue->ring_id);
  89. return;
  90. }
  91. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  92. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  93. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  94. {
  95. /* get flow id */
  96. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  97. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  98. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  99. "%s, pool_id:%d ring_id: %d",
  100. __func__, queue->desc_pool_id, queue->ring_id);
  101. return;
  102. }
  103. #endif
  104. #if defined(FEATURE_TSO)
  105. /**
  106. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  107. *
  108. * @soc - core txrx main context
  109. * @seg_desc - tso segment descriptor
  110. * @num_seg_desc - tso number segment descriptor
  111. */
  112. static void dp_tx_tso_unmap_segment(
  113. struct dp_soc *soc,
  114. struct qdf_tso_seg_elem_t *seg_desc,
  115. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  116. {
  117. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  118. if (qdf_unlikely(!seg_desc)) {
  119. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  120. __func__, __LINE__);
  121. qdf_assert(0);
  122. } else if (qdf_unlikely(!num_seg_desc)) {
  123. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  124. __func__, __LINE__);
  125. qdf_assert(0);
  126. } else {
  127. bool is_last_seg;
  128. /* no tso segment left to do dma unmap */
  129. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  130. return;
  131. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  132. true : false;
  133. qdf_nbuf_unmap_tso_segment(soc->osdev,
  134. seg_desc, is_last_seg);
  135. num_seg_desc->num_seg.tso_cmn_num_seg--;
  136. }
  137. }
  138. /**
  139. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  140. * back to the freelist
  141. *
  142. * @soc - soc device handle
  143. * @tx_desc - Tx software descriptor
  144. */
  145. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  146. struct dp_tx_desc_s *tx_desc)
  147. {
  148. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  149. if (qdf_unlikely(!tx_desc->tso_desc)) {
  150. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  151. "%s %d TSO desc is NULL!",
  152. __func__, __LINE__);
  153. qdf_assert(0);
  154. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  155. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  156. "%s %d TSO num desc is NULL!",
  157. __func__, __LINE__);
  158. qdf_assert(0);
  159. } else {
  160. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  161. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  162. /* Add the tso num segment into the free list */
  163. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  164. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  165. tx_desc->tso_num_desc);
  166. tx_desc->tso_num_desc = NULL;
  167. }
  168. /* Add the tso segment into the free list*/
  169. dp_tx_tso_desc_free(soc,
  170. tx_desc->pool_id, tx_desc->tso_desc);
  171. tx_desc->tso_desc = NULL;
  172. }
  173. }
  174. #else
  175. static void dp_tx_tso_unmap_segment(
  176. struct dp_soc *soc,
  177. struct qdf_tso_seg_elem_t *seg_desc,
  178. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  179. {
  180. }
  181. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  182. struct dp_tx_desc_s *tx_desc)
  183. {
  184. }
  185. #endif
  186. /**
  187. * dp_tx_desc_release() - Release Tx Descriptor
  188. * @tx_desc : Tx Descriptor
  189. * @desc_pool_id: Descriptor Pool ID
  190. *
  191. * Deallocate all resources attached to Tx descriptor and free the Tx
  192. * descriptor.
  193. *
  194. * Return:
  195. */
  196. static void
  197. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  198. {
  199. struct dp_pdev *pdev = tx_desc->pdev;
  200. struct dp_soc *soc;
  201. uint8_t comp_status = 0;
  202. qdf_assert(pdev);
  203. soc = pdev->soc;
  204. if (tx_desc->frm_type == dp_tx_frm_tso)
  205. dp_tx_tso_desc_release(soc, tx_desc);
  206. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  207. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  208. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  209. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  210. qdf_atomic_dec(&pdev->num_tx_outstanding);
  211. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  212. qdf_atomic_dec(&pdev->num_tx_exception);
  213. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  214. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  215. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  216. soc->hal_soc);
  217. else
  218. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  219. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  220. "Tx Completion Release desc %d status %d outstanding %d",
  221. tx_desc->id, comp_status,
  222. qdf_atomic_read(&pdev->num_tx_outstanding));
  223. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  224. return;
  225. }
  226. /**
  227. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  228. * @vdev: DP vdev Handle
  229. * @nbuf: skb
  230. * @msdu_info: msdu_info required to create HTT metadata
  231. *
  232. * Prepares and fills HTT metadata in the frame pre-header for special frames
  233. * that should be transmitted using varying transmit parameters.
  234. * There are 2 VDEV modes that currently needs this special metadata -
  235. * 1) Mesh Mode
  236. * 2) DSRC Mode
  237. *
  238. * Return: HTT metadata size
  239. *
  240. */
  241. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  242. struct dp_tx_msdu_info_s *msdu_info)
  243. {
  244. uint32_t *meta_data = msdu_info->meta_data;
  245. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  246. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  247. uint8_t htt_desc_size;
  248. /* Size rounded of multiple of 8 bytes */
  249. uint8_t htt_desc_size_aligned;
  250. uint8_t *hdr = NULL;
  251. /*
  252. * Metadata - HTT MSDU Extension header
  253. */
  254. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  255. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  256. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer) {
  257. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  258. htt_desc_size_aligned)) {
  259. DP_STATS_INC(vdev,
  260. tx_i.dropped.headroom_insufficient, 1);
  261. return 0;
  262. }
  263. /* Fill and add HTT metaheader */
  264. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  265. if (!hdr) {
  266. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  267. "Error in filling HTT metadata");
  268. return 0;
  269. }
  270. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  271. } else if (vdev->opmode == wlan_op_mode_ocb) {
  272. /* Todo - Add support for DSRC */
  273. }
  274. return htt_desc_size_aligned;
  275. }
  276. /**
  277. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  278. * @tso_seg: TSO segment to process
  279. * @ext_desc: Pointer to MSDU extension descriptor
  280. *
  281. * Return: void
  282. */
  283. #if defined(FEATURE_TSO)
  284. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  285. void *ext_desc)
  286. {
  287. uint8_t num_frag;
  288. uint32_t tso_flags;
  289. /*
  290. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  291. * tcp_flag_mask
  292. *
  293. * Checksum enable flags are set in TCL descriptor and not in Extension
  294. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  295. */
  296. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  297. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  298. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  299. tso_seg->tso_flags.ip_len);
  300. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  301. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  302. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  303. uint32_t lo = 0;
  304. uint32_t hi = 0;
  305. qdf_dmaaddr_to_32s(
  306. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  307. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  308. tso_seg->tso_frags[num_frag].length);
  309. }
  310. return;
  311. }
  312. #else
  313. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  314. void *ext_desc)
  315. {
  316. return;
  317. }
  318. #endif
  319. #if defined(FEATURE_TSO)
  320. /**
  321. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  322. * allocated and free them
  323. *
  324. * @soc: soc handle
  325. * @free_seg: list of tso segments
  326. * @msdu_info: msdu descriptor
  327. *
  328. * Return - void
  329. */
  330. static void dp_tx_free_tso_seg_list(
  331. struct dp_soc *soc,
  332. struct qdf_tso_seg_elem_t *free_seg,
  333. struct dp_tx_msdu_info_s *msdu_info)
  334. {
  335. struct qdf_tso_seg_elem_t *next_seg;
  336. while (free_seg) {
  337. next_seg = free_seg->next;
  338. dp_tx_tso_desc_free(soc,
  339. msdu_info->tx_queue.desc_pool_id,
  340. free_seg);
  341. free_seg = next_seg;
  342. }
  343. }
  344. /**
  345. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  346. * allocated and free them
  347. *
  348. * @soc: soc handle
  349. * @free_num_seg: list of tso number segments
  350. * @msdu_info: msdu descriptor
  351. * Return - void
  352. */
  353. static void dp_tx_free_tso_num_seg_list(
  354. struct dp_soc *soc,
  355. struct qdf_tso_num_seg_elem_t *free_num_seg,
  356. struct dp_tx_msdu_info_s *msdu_info)
  357. {
  358. struct qdf_tso_num_seg_elem_t *next_num_seg;
  359. while (free_num_seg) {
  360. next_num_seg = free_num_seg->next;
  361. dp_tso_num_seg_free(soc,
  362. msdu_info->tx_queue.desc_pool_id,
  363. free_num_seg);
  364. free_num_seg = next_num_seg;
  365. }
  366. }
  367. /**
  368. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  369. * do dma unmap for each segment
  370. *
  371. * @soc: soc handle
  372. * @free_seg: list of tso segments
  373. * @num_seg_desc: tso number segment descriptor
  374. *
  375. * Return - void
  376. */
  377. static void dp_tx_unmap_tso_seg_list(
  378. struct dp_soc *soc,
  379. struct qdf_tso_seg_elem_t *free_seg,
  380. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  381. {
  382. struct qdf_tso_seg_elem_t *next_seg;
  383. if (qdf_unlikely(!num_seg_desc)) {
  384. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  385. return;
  386. }
  387. while (free_seg) {
  388. next_seg = free_seg->next;
  389. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  390. free_seg = next_seg;
  391. }
  392. }
  393. /**
  394. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  395. * free the tso segments descriptor and
  396. * tso num segments descriptor
  397. *
  398. * @soc: soc handle
  399. * @msdu_info: msdu descriptor
  400. * @tso_seg_unmap: flag to show if dma unmap is necessary
  401. *
  402. * Return - void
  403. */
  404. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  405. struct dp_tx_msdu_info_s *msdu_info,
  406. bool tso_seg_unmap)
  407. {
  408. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  409. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  410. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  411. tso_info->tso_num_seg_list;
  412. /* do dma unmap for each segment */
  413. if (tso_seg_unmap)
  414. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  415. /* free all tso number segment descriptor though looks only have 1 */
  416. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  417. /* free all tso segment descriptor */
  418. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  419. }
  420. /**
  421. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  422. * @vdev: virtual device handle
  423. * @msdu: network buffer
  424. * @msdu_info: meta data associated with the msdu
  425. *
  426. * Return: QDF_STATUS_SUCCESS success
  427. */
  428. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  429. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  430. {
  431. struct qdf_tso_seg_elem_t *tso_seg;
  432. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  433. struct dp_soc *soc = vdev->pdev->soc;
  434. struct qdf_tso_info_t *tso_info;
  435. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  436. tso_info = &msdu_info->u.tso_info;
  437. tso_info->curr_seg = NULL;
  438. tso_info->tso_seg_list = NULL;
  439. tso_info->num_segs = num_seg;
  440. msdu_info->frm_type = dp_tx_frm_tso;
  441. tso_info->tso_num_seg_list = NULL;
  442. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  443. while (num_seg) {
  444. tso_seg = dp_tx_tso_desc_alloc(
  445. soc, msdu_info->tx_queue.desc_pool_id);
  446. if (tso_seg) {
  447. tso_seg->next = tso_info->tso_seg_list;
  448. tso_info->tso_seg_list = tso_seg;
  449. num_seg--;
  450. } else {
  451. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  452. __func__);
  453. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  454. return QDF_STATUS_E_NOMEM;
  455. }
  456. }
  457. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  458. tso_num_seg = dp_tso_num_seg_alloc(soc,
  459. msdu_info->tx_queue.desc_pool_id);
  460. if (tso_num_seg) {
  461. tso_num_seg->next = tso_info->tso_num_seg_list;
  462. tso_info->tso_num_seg_list = tso_num_seg;
  463. } else {
  464. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  465. __func__);
  466. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  467. return QDF_STATUS_E_NOMEM;
  468. }
  469. msdu_info->num_seg =
  470. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  471. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  472. msdu_info->num_seg);
  473. if (!(msdu_info->num_seg)) {
  474. /*
  475. * Free allocated TSO seg desc and number seg desc,
  476. * do unmap for segments if dma map has done.
  477. */
  478. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  479. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  480. return QDF_STATUS_E_INVAL;
  481. }
  482. tso_info->curr_seg = tso_info->tso_seg_list;
  483. return QDF_STATUS_SUCCESS;
  484. }
  485. #else
  486. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  487. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  488. {
  489. return QDF_STATUS_E_NOMEM;
  490. }
  491. #endif
  492. /**
  493. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  494. * @vdev: DP Vdev handle
  495. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  496. * @desc_pool_id: Descriptor Pool ID
  497. *
  498. * Return:
  499. */
  500. static
  501. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  502. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  503. {
  504. uint8_t i;
  505. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  506. struct dp_tx_seg_info_s *seg_info;
  507. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  508. struct dp_soc *soc = vdev->pdev->soc;
  509. /* Allocate an extension descriptor */
  510. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  511. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  512. if (!msdu_ext_desc) {
  513. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  514. return NULL;
  515. }
  516. if (msdu_info->exception_fw &&
  517. qdf_unlikely(vdev->mesh_vdev)) {
  518. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  519. &msdu_info->meta_data[0],
  520. sizeof(struct htt_tx_msdu_desc_ext2_t));
  521. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  522. }
  523. switch (msdu_info->frm_type) {
  524. case dp_tx_frm_sg:
  525. case dp_tx_frm_me:
  526. case dp_tx_frm_raw:
  527. seg_info = msdu_info->u.sg_info.curr_seg;
  528. /* Update the buffer pointers in MSDU Extension Descriptor */
  529. for (i = 0; i < seg_info->frag_cnt; i++) {
  530. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  531. seg_info->frags[i].paddr_lo,
  532. seg_info->frags[i].paddr_hi,
  533. seg_info->frags[i].len);
  534. }
  535. break;
  536. case dp_tx_frm_tso:
  537. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  538. &cached_ext_desc[0]);
  539. break;
  540. default:
  541. break;
  542. }
  543. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  544. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  545. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  546. msdu_ext_desc->vaddr);
  547. return msdu_ext_desc;
  548. }
  549. /**
  550. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  551. *
  552. * @skb: skb to be traced
  553. * @msdu_id: msdu_id of the packet
  554. * @vdev_id: vdev_id of the packet
  555. *
  556. * Return: None
  557. */
  558. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  559. uint8_t vdev_id)
  560. {
  561. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  562. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  563. DPTRACE(qdf_dp_trace_ptr(skb,
  564. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  565. QDF_TRACE_DEFAULT_PDEV_ID,
  566. qdf_nbuf_data_addr(skb),
  567. sizeof(qdf_nbuf_data(skb)),
  568. msdu_id, vdev_id));
  569. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  570. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  571. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  572. msdu_id, QDF_TX));
  573. }
  574. #ifdef QCA_512M_CONFIG
  575. /**
  576. * dp_tx_pdev_pflow_control - Check if allocated tx descriptors reached max
  577. * tx descriptor configured value
  578. * @vdev: DP vdev handle
  579. *
  580. * Return: true if allocated tx descriptors reached max configured value, else
  581. * false.
  582. */
  583. static inline bool
  584. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  585. {
  586. struct dp_pdev *pdev = vdev->pdev;
  587. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  588. pdev->num_tx_allowed) {
  589. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  590. "%s: queued packets are more than max tx, drop the frame",
  591. __func__);
  592. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  593. return true;
  594. }
  595. return false;
  596. }
  597. #else
  598. static inline bool
  599. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  600. {
  601. return false;
  602. }
  603. #endif
  604. /**
  605. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  606. * @vdev: DP vdev handle
  607. * @nbuf: skb
  608. * @desc_pool_id: Descriptor pool ID
  609. * @meta_data: Metadata to the fw
  610. * @tx_exc_metadata: Handle that holds exception path metadata
  611. * Allocate and prepare Tx descriptor with msdu information.
  612. *
  613. * Return: Pointer to Tx Descriptor on success,
  614. * NULL on failure
  615. */
  616. static
  617. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  618. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  619. struct dp_tx_msdu_info_s *msdu_info,
  620. struct cdp_tx_exception_metadata *tx_exc_metadata)
  621. {
  622. uint8_t align_pad;
  623. uint8_t is_exception = 0;
  624. uint8_t htt_hdr_size;
  625. qdf_ether_header_t *eh;
  626. struct dp_tx_desc_s *tx_desc;
  627. struct dp_pdev *pdev = vdev->pdev;
  628. struct dp_soc *soc = pdev->soc;
  629. if (dp_tx_pdev_pflow_control(vdev))
  630. return NULL;
  631. /* Allocate software Tx descriptor */
  632. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  633. if (qdf_unlikely(!tx_desc)) {
  634. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  635. return NULL;
  636. }
  637. /* Flow control/Congestion Control counters */
  638. qdf_atomic_inc(&pdev->num_tx_outstanding);
  639. /* Initialize the SW tx descriptor */
  640. tx_desc->nbuf = nbuf;
  641. tx_desc->frm_type = dp_tx_frm_std;
  642. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  643. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  644. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  645. tx_desc->vdev = vdev;
  646. tx_desc->pdev = pdev;
  647. tx_desc->msdu_ext_desc = NULL;
  648. tx_desc->pkt_offset = 0;
  649. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  650. /*
  651. * For special modes (vdev_type == ocb or mesh), data frames should be
  652. * transmitted using varying transmit parameters (tx spec) which include
  653. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  654. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  655. * These frames are sent as exception packets to firmware.
  656. *
  657. * HW requirement is that metadata should always point to a
  658. * 8-byte aligned address. So we add alignment pad to start of buffer.
  659. * HTT Metadata should be ensured to be multiple of 8-bytes,
  660. * to get 8-byte aligned start address along with align_pad added
  661. *
  662. * |-----------------------------|
  663. * | |
  664. * |-----------------------------| <-----Buffer Pointer Address given
  665. * | | ^ in HW descriptor (aligned)
  666. * | HTT Metadata | |
  667. * | | |
  668. * | | | Packet Offset given in descriptor
  669. * | | |
  670. * |-----------------------------| |
  671. * | Alignment Pad | v
  672. * |-----------------------------| <----- Actual buffer start address
  673. * | SKB Data | (Unaligned)
  674. * | |
  675. * | |
  676. * | |
  677. * | |
  678. * | |
  679. * |-----------------------------|
  680. */
  681. if (qdf_unlikely((msdu_info->exception_fw)) ||
  682. (vdev->opmode == wlan_op_mode_ocb) ||
  683. (tx_exc_metadata &&
  684. tx_exc_metadata->is_tx_sniffer)) {
  685. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  686. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  687. DP_STATS_INC(vdev,
  688. tx_i.dropped.headroom_insufficient, 1);
  689. goto failure;
  690. }
  691. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  692. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  693. "qdf_nbuf_push_head failed");
  694. goto failure;
  695. }
  696. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  697. msdu_info);
  698. if (htt_hdr_size == 0)
  699. goto failure;
  700. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  701. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  702. is_exception = 1;
  703. }
  704. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  705. qdf_nbuf_map(soc->osdev, nbuf,
  706. QDF_DMA_TO_DEVICE))) {
  707. /* Handle failure */
  708. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  709. "qdf_nbuf_map failed");
  710. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  711. goto failure;
  712. }
  713. if (qdf_unlikely(vdev->nawds_enabled)) {
  714. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  715. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  716. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  717. is_exception = 1;
  718. }
  719. }
  720. #if !TQM_BYPASS_WAR
  721. if (is_exception || tx_exc_metadata)
  722. #endif
  723. {
  724. /* Temporary WAR due to TQM VP issues */
  725. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  726. qdf_atomic_inc(&pdev->num_tx_exception);
  727. }
  728. return tx_desc;
  729. failure:
  730. dp_tx_desc_release(tx_desc, desc_pool_id);
  731. return NULL;
  732. }
  733. /**
  734. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  735. * @vdev: DP vdev handle
  736. * @nbuf: skb
  737. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  738. * @desc_pool_id : Descriptor Pool ID
  739. *
  740. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  741. * information. For frames wth fragments, allocate and prepare
  742. * an MSDU extension descriptor
  743. *
  744. * Return: Pointer to Tx Descriptor on success,
  745. * NULL on failure
  746. */
  747. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  748. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  749. uint8_t desc_pool_id)
  750. {
  751. struct dp_tx_desc_s *tx_desc;
  752. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  753. struct dp_pdev *pdev = vdev->pdev;
  754. struct dp_soc *soc = pdev->soc;
  755. if (dp_tx_pdev_pflow_control(vdev))
  756. return NULL;
  757. /* Allocate software Tx descriptor */
  758. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  759. if (!tx_desc) {
  760. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  761. return NULL;
  762. }
  763. /* Flow control/Congestion Control counters */
  764. qdf_atomic_inc(&pdev->num_tx_outstanding);
  765. /* Initialize the SW tx descriptor */
  766. tx_desc->nbuf = nbuf;
  767. tx_desc->frm_type = msdu_info->frm_type;
  768. tx_desc->tx_encap_type = vdev->tx_encap_type;
  769. tx_desc->vdev = vdev;
  770. tx_desc->pdev = pdev;
  771. tx_desc->pkt_offset = 0;
  772. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  773. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  774. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  775. /* Handle scattered frames - TSO/SG/ME */
  776. /* Allocate and prepare an extension descriptor for scattered frames */
  777. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  778. if (!msdu_ext_desc) {
  779. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  780. "%s Tx Extension Descriptor Alloc Fail",
  781. __func__);
  782. goto failure;
  783. }
  784. #if TQM_BYPASS_WAR
  785. /* Temporary WAR due to TQM VP issues */
  786. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  787. qdf_atomic_inc(&pdev->num_tx_exception);
  788. #endif
  789. if (qdf_unlikely(msdu_info->exception_fw))
  790. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  791. tx_desc->msdu_ext_desc = msdu_ext_desc;
  792. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  793. return tx_desc;
  794. failure:
  795. dp_tx_desc_release(tx_desc, desc_pool_id);
  796. return NULL;
  797. }
  798. /**
  799. * dp_tx_prepare_raw() - Prepare RAW packet TX
  800. * @vdev: DP vdev handle
  801. * @nbuf: buffer pointer
  802. * @seg_info: Pointer to Segment info Descriptor to be prepared
  803. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  804. * descriptor
  805. *
  806. * Return:
  807. */
  808. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  809. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  810. {
  811. qdf_nbuf_t curr_nbuf = NULL;
  812. uint16_t total_len = 0;
  813. qdf_dma_addr_t paddr;
  814. int32_t i;
  815. int32_t mapped_buf_num = 0;
  816. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  817. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  818. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  819. /* Continue only if frames are of DATA type */
  820. if (!DP_FRAME_IS_DATA(qos_wh)) {
  821. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  822. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  823. "Pkt. recd is of not data type");
  824. goto error;
  825. }
  826. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  827. if (vdev->raw_mode_war &&
  828. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  829. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  830. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  831. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  832. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  833. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  834. QDF_DMA_TO_DEVICE)) {
  835. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  836. "%s dma map error ", __func__);
  837. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  838. mapped_buf_num = i;
  839. goto error;
  840. }
  841. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  842. seg_info->frags[i].paddr_lo = paddr;
  843. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  844. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  845. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  846. total_len += qdf_nbuf_len(curr_nbuf);
  847. }
  848. seg_info->frag_cnt = i;
  849. seg_info->total_len = total_len;
  850. seg_info->next = NULL;
  851. sg_info->curr_seg = seg_info;
  852. msdu_info->frm_type = dp_tx_frm_raw;
  853. msdu_info->num_seg = 1;
  854. return nbuf;
  855. error:
  856. i = 0;
  857. while (nbuf) {
  858. curr_nbuf = nbuf;
  859. if (i < mapped_buf_num) {
  860. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  861. i++;
  862. }
  863. nbuf = qdf_nbuf_next(nbuf);
  864. qdf_nbuf_free(curr_nbuf);
  865. }
  866. return NULL;
  867. }
  868. /**
  869. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  870. * @soc: DP Soc Handle
  871. * @vdev: DP vdev handle
  872. * @tx_desc: Tx Descriptor Handle
  873. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  874. * @fw_metadata: Metadata to send to Target Firmware along with frame
  875. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  876. * @tx_exc_metadata: Handle that holds exception path meta data
  877. *
  878. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  879. * from software Tx descriptor
  880. *
  881. * Return:
  882. */
  883. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  884. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  885. uint16_t fw_metadata, uint8_t ring_id,
  886. struct cdp_tx_exception_metadata
  887. *tx_exc_metadata)
  888. {
  889. uint8_t type;
  890. uint16_t length;
  891. void *hal_tx_desc, *hal_tx_desc_cached;
  892. qdf_dma_addr_t dma_addr;
  893. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  894. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  895. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  896. tx_exc_metadata->sec_type : vdev->sec_type);
  897. /* Return Buffer Manager ID */
  898. uint8_t bm_id = ring_id;
  899. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  900. hal_tx_desc_cached = (void *) cached_desc;
  901. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  902. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  903. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  904. type = HAL_TX_BUF_TYPE_EXT_DESC;
  905. dma_addr = tx_desc->msdu_ext_desc->paddr;
  906. } else {
  907. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  908. type = HAL_TX_BUF_TYPE_BUFFER;
  909. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  910. }
  911. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  912. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  913. dma_addr, bm_id, tx_desc->id,
  914. type, soc->hal_soc);
  915. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  916. return QDF_STATUS_E_RESOURCES;
  917. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  918. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  919. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  920. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  921. vdev->pdev->lmac_id);
  922. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  923. vdev->search_type);
  924. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  925. vdev->bss_ast_hash);
  926. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  927. vdev->dscp_tid_map_id);
  928. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  929. sec_type_map[sec_type]);
  930. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  931. length, type, (uint64_t)dma_addr,
  932. tx_desc->pkt_offset, tx_desc->id);
  933. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  934. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  935. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  936. vdev->hal_desc_addr_search_flags);
  937. /* verify checksum offload configuration*/
  938. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  939. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  940. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  941. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  942. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  943. }
  944. if (tid != HTT_TX_EXT_TID_INVALID)
  945. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  946. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  947. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  948. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  949. /* Sync cached descriptor with HW */
  950. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  951. if (!hal_tx_desc) {
  952. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  953. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  954. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  955. return QDF_STATUS_E_RESOURCES;
  956. }
  957. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  958. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  959. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  960. return QDF_STATUS_SUCCESS;
  961. }
  962. /**
  963. * dp_cce_classify() - Classify the frame based on CCE rules
  964. * @vdev: DP vdev handle
  965. * @nbuf: skb
  966. *
  967. * Classify frames based on CCE rules
  968. * Return: bool( true if classified,
  969. * else false)
  970. */
  971. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  972. {
  973. qdf_ether_header_t *eh = NULL;
  974. uint16_t ether_type;
  975. qdf_llc_t *llcHdr;
  976. qdf_nbuf_t nbuf_clone = NULL;
  977. qdf_dot3_qosframe_t *qos_wh = NULL;
  978. /* for mesh packets don't do any classification */
  979. if (qdf_unlikely(vdev->mesh_vdev))
  980. return false;
  981. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  982. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  983. ether_type = eh->ether_type;
  984. llcHdr = (qdf_llc_t *)(nbuf->data +
  985. sizeof(qdf_ether_header_t));
  986. } else {
  987. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  988. /* For encrypted packets don't do any classification */
  989. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  990. return false;
  991. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  992. if (qdf_unlikely(
  993. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  994. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  995. ether_type = *(uint16_t *)(nbuf->data
  996. + QDF_IEEE80211_4ADDR_HDR_LEN
  997. + sizeof(qdf_llc_t)
  998. - sizeof(ether_type));
  999. llcHdr = (qdf_llc_t *)(nbuf->data +
  1000. QDF_IEEE80211_4ADDR_HDR_LEN);
  1001. } else {
  1002. ether_type = *(uint16_t *)(nbuf->data
  1003. + QDF_IEEE80211_3ADDR_HDR_LEN
  1004. + sizeof(qdf_llc_t)
  1005. - sizeof(ether_type));
  1006. llcHdr = (qdf_llc_t *)(nbuf->data +
  1007. QDF_IEEE80211_3ADDR_HDR_LEN);
  1008. }
  1009. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1010. && (ether_type ==
  1011. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1012. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1013. return true;
  1014. }
  1015. }
  1016. return false;
  1017. }
  1018. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1019. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1020. sizeof(*llcHdr));
  1021. nbuf_clone = qdf_nbuf_clone(nbuf);
  1022. if (qdf_unlikely(nbuf_clone)) {
  1023. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1024. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1025. qdf_nbuf_pull_head(nbuf_clone,
  1026. sizeof(qdf_net_vlanhdr_t));
  1027. }
  1028. }
  1029. } else {
  1030. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1031. nbuf_clone = qdf_nbuf_clone(nbuf);
  1032. if (qdf_unlikely(nbuf_clone)) {
  1033. qdf_nbuf_pull_head(nbuf_clone,
  1034. sizeof(qdf_net_vlanhdr_t));
  1035. }
  1036. }
  1037. }
  1038. if (qdf_unlikely(nbuf_clone))
  1039. nbuf = nbuf_clone;
  1040. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1041. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1042. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1043. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1044. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1045. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1046. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1047. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1048. if (qdf_unlikely(nbuf_clone))
  1049. qdf_nbuf_free(nbuf_clone);
  1050. return true;
  1051. }
  1052. if (qdf_unlikely(nbuf_clone))
  1053. qdf_nbuf_free(nbuf_clone);
  1054. return false;
  1055. }
  1056. /**
  1057. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1058. * @vdev: DP vdev handle
  1059. * @nbuf: skb
  1060. *
  1061. * Extract the DSCP or PCP information from frame and map into TID value.
  1062. *
  1063. * Return: void
  1064. */
  1065. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1066. struct dp_tx_msdu_info_s *msdu_info)
  1067. {
  1068. uint8_t tos = 0, dscp_tid_override = 0;
  1069. uint8_t *hdr_ptr, *L3datap;
  1070. uint8_t is_mcast = 0;
  1071. qdf_ether_header_t *eh = NULL;
  1072. qdf_ethervlan_header_t *evh = NULL;
  1073. uint16_t ether_type;
  1074. qdf_llc_t *llcHdr;
  1075. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1076. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1077. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1078. eh = (qdf_ether_header_t *)nbuf->data;
  1079. hdr_ptr = eh->ether_dhost;
  1080. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1081. } else {
  1082. qdf_dot3_qosframe_t *qos_wh =
  1083. (qdf_dot3_qosframe_t *) nbuf->data;
  1084. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1085. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1086. return;
  1087. }
  1088. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1089. ether_type = eh->ether_type;
  1090. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1091. /*
  1092. * Check if packet is dot3 or eth2 type.
  1093. */
  1094. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1095. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1096. sizeof(*llcHdr));
  1097. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1098. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1099. sizeof(*llcHdr);
  1100. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1101. + sizeof(*llcHdr) +
  1102. sizeof(qdf_net_vlanhdr_t));
  1103. } else {
  1104. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1105. sizeof(*llcHdr);
  1106. }
  1107. } else {
  1108. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1109. evh = (qdf_ethervlan_header_t *) eh;
  1110. ether_type = evh->ether_type;
  1111. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1112. }
  1113. }
  1114. /*
  1115. * Find priority from IP TOS DSCP field
  1116. */
  1117. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1118. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1119. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1120. /* Only for unicast frames */
  1121. if (!is_mcast) {
  1122. /* send it on VO queue */
  1123. msdu_info->tid = DP_VO_TID;
  1124. }
  1125. } else {
  1126. /*
  1127. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1128. * from TOS byte.
  1129. */
  1130. tos = ip->ip_tos;
  1131. dscp_tid_override = 1;
  1132. }
  1133. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1134. /* TODO
  1135. * use flowlabel
  1136. *igmpmld cases to be handled in phase 2
  1137. */
  1138. unsigned long ver_pri_flowlabel;
  1139. unsigned long pri;
  1140. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1141. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1142. DP_IPV6_PRIORITY_SHIFT;
  1143. tos = pri;
  1144. dscp_tid_override = 1;
  1145. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1146. msdu_info->tid = DP_VO_TID;
  1147. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1148. /* Only for unicast frames */
  1149. if (!is_mcast) {
  1150. /* send ucast arp on VO queue */
  1151. msdu_info->tid = DP_VO_TID;
  1152. }
  1153. }
  1154. /*
  1155. * Assign all MCAST packets to BE
  1156. */
  1157. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1158. if (is_mcast) {
  1159. tos = 0;
  1160. dscp_tid_override = 1;
  1161. }
  1162. }
  1163. if (dscp_tid_override == 1) {
  1164. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1165. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1166. }
  1167. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1168. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1169. return;
  1170. }
  1171. /**
  1172. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1173. * @vdev: DP vdev handle
  1174. * @nbuf: skb
  1175. *
  1176. * Software based TID classification is required when more than 2 DSCP-TID
  1177. * mapping tables are needed.
  1178. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1179. *
  1180. * Return: void
  1181. */
  1182. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1183. struct dp_tx_msdu_info_s *msdu_info)
  1184. {
  1185. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1186. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1187. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1188. return;
  1189. /* for mesh packets don't do any classification */
  1190. if (qdf_unlikely(vdev->mesh_vdev))
  1191. return;
  1192. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1193. }
  1194. #ifdef FEATURE_WLAN_TDLS
  1195. /**
  1196. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1197. * @tx_desc: TX descriptor
  1198. *
  1199. * Return: None
  1200. */
  1201. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1202. {
  1203. if (tx_desc->vdev) {
  1204. if (tx_desc->vdev->is_tdls_frame) {
  1205. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1206. tx_desc->vdev->is_tdls_frame = false;
  1207. }
  1208. }
  1209. }
  1210. /**
  1211. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1212. * @tx_desc: TX descriptor
  1213. * @vdev: datapath vdev handle
  1214. *
  1215. * Return: None
  1216. */
  1217. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1218. struct dp_vdev *vdev)
  1219. {
  1220. struct hal_tx_completion_status ts = {0};
  1221. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1222. if (qdf_unlikely(!vdev)) {
  1223. dp_err("vdev is null!");
  1224. return;
  1225. }
  1226. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1227. if (vdev->tx_non_std_data_callback.func) {
  1228. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1229. vdev->tx_non_std_data_callback.func(
  1230. vdev->tx_non_std_data_callback.ctxt,
  1231. nbuf, ts.status);
  1232. return;
  1233. }
  1234. }
  1235. #else
  1236. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1237. {
  1238. }
  1239. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1240. struct dp_vdev *vdev)
  1241. {
  1242. }
  1243. #endif
  1244. /**
  1245. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1246. * @vdev: DP vdev handle
  1247. * @nbuf: skb
  1248. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1249. * @meta_data: Metadata to the fw
  1250. * @tx_q: Tx queue to be used for this Tx frame
  1251. * @peer_id: peer_id of the peer in case of NAWDS frames
  1252. * @tx_exc_metadata: Handle that holds exception path metadata
  1253. *
  1254. * Return: NULL on success,
  1255. * nbuf when it fails to send
  1256. */
  1257. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1258. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1259. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1260. {
  1261. struct dp_pdev *pdev = vdev->pdev;
  1262. struct dp_soc *soc = pdev->soc;
  1263. struct dp_tx_desc_s *tx_desc;
  1264. QDF_STATUS status;
  1265. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1266. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1267. uint16_t htt_tcl_metadata = 0;
  1268. uint8_t tid = msdu_info->tid;
  1269. struct cdp_tid_tx_stats *tid_stats = NULL;
  1270. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1271. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1272. msdu_info, tx_exc_metadata);
  1273. if (!tx_desc) {
  1274. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1275. vdev, tx_q->desc_pool_id);
  1276. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1277. tid_stats = &pdev->stats.tid_stats.
  1278. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1279. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1280. return nbuf;
  1281. }
  1282. if (qdf_unlikely(soc->cce_disable)) {
  1283. if (dp_cce_classify(vdev, nbuf) == true) {
  1284. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1285. tid = DP_VO_TID;
  1286. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1287. }
  1288. }
  1289. dp_tx_update_tdls_flags(tx_desc);
  1290. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1291. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1292. "%s %d : HAL RING Access Failed -- %pK",
  1293. __func__, __LINE__, hal_srng);
  1294. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1295. tid_stats = &pdev->stats.tid_stats.
  1296. tid_tx_stats[tx_q->ring_id][tid];
  1297. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1298. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1299. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1300. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1301. goto fail_return;
  1302. }
  1303. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1304. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1305. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1306. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1307. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1308. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1309. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1310. peer_id);
  1311. } else
  1312. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1313. if (msdu_info->exception_fw) {
  1314. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1315. }
  1316. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1317. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1318. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1319. if (status != QDF_STATUS_SUCCESS) {
  1320. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1321. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1322. __func__, tx_desc, tx_q->ring_id);
  1323. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1324. tid_stats = &pdev->stats.tid_stats.
  1325. tid_tx_stats[tx_q->ring_id][tid];
  1326. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1327. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1328. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1329. goto fail_return;
  1330. }
  1331. nbuf = NULL;
  1332. fail_return:
  1333. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1334. hal_srng_access_end(soc->hal_soc, hal_srng);
  1335. hif_pm_runtime_put(soc->hif_handle);
  1336. } else {
  1337. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1338. }
  1339. return nbuf;
  1340. }
  1341. /**
  1342. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1343. * @vdev: DP vdev handle
  1344. * @nbuf: skb
  1345. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1346. *
  1347. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1348. *
  1349. * Return: NULL on success,
  1350. * nbuf when it fails to send
  1351. */
  1352. #if QDF_LOCK_STATS
  1353. static noinline
  1354. #else
  1355. static
  1356. #endif
  1357. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1358. struct dp_tx_msdu_info_s *msdu_info)
  1359. {
  1360. uint8_t i;
  1361. struct dp_pdev *pdev = vdev->pdev;
  1362. struct dp_soc *soc = pdev->soc;
  1363. struct dp_tx_desc_s *tx_desc;
  1364. bool is_cce_classified = false;
  1365. QDF_STATUS status;
  1366. uint16_t htt_tcl_metadata = 0;
  1367. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1368. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1369. struct cdp_tid_tx_stats *tid_stats = NULL;
  1370. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1371. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1372. "%s %d : HAL RING Access Failed -- %pK",
  1373. __func__, __LINE__, hal_srng);
  1374. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1375. tid_stats = &pdev->stats.tid_stats.
  1376. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1377. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1378. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1379. return nbuf;
  1380. }
  1381. if (qdf_unlikely(soc->cce_disable)) {
  1382. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1383. if (is_cce_classified) {
  1384. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1385. msdu_info->tid = DP_VO_TID;
  1386. }
  1387. }
  1388. if (msdu_info->frm_type == dp_tx_frm_me)
  1389. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1390. i = 0;
  1391. /* Print statement to track i and num_seg */
  1392. /*
  1393. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1394. * descriptors using information in msdu_info
  1395. */
  1396. while (i < msdu_info->num_seg) {
  1397. /*
  1398. * Setup Tx descriptor for an MSDU, and MSDU extension
  1399. * descriptor
  1400. */
  1401. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1402. tx_q->desc_pool_id);
  1403. if (!tx_desc) {
  1404. if (msdu_info->frm_type == dp_tx_frm_me) {
  1405. dp_tx_me_free_buf(pdev,
  1406. (void *)(msdu_info->u.sg_info
  1407. .curr_seg->frags[0].vaddr));
  1408. }
  1409. goto done;
  1410. }
  1411. if (msdu_info->frm_type == dp_tx_frm_me) {
  1412. tx_desc->me_buffer =
  1413. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1414. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1415. }
  1416. if (is_cce_classified)
  1417. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1418. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1419. if (msdu_info->exception_fw) {
  1420. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1421. }
  1422. /*
  1423. * Enqueue the Tx MSDU descriptor to HW for transmit
  1424. */
  1425. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1426. htt_tcl_metadata, tx_q->ring_id, NULL);
  1427. if (status != QDF_STATUS_SUCCESS) {
  1428. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1429. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1430. __func__, tx_desc, tx_q->ring_id);
  1431. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1432. tid_stats = &pdev->stats.tid_stats.
  1433. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1434. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1435. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1436. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1437. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1438. goto done;
  1439. }
  1440. /*
  1441. * TODO
  1442. * if tso_info structure can be modified to have curr_seg
  1443. * as first element, following 2 blocks of code (for TSO and SG)
  1444. * can be combined into 1
  1445. */
  1446. /*
  1447. * For frames with multiple segments (TSO, ME), jump to next
  1448. * segment.
  1449. */
  1450. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1451. if (msdu_info->u.tso_info.curr_seg->next) {
  1452. msdu_info->u.tso_info.curr_seg =
  1453. msdu_info->u.tso_info.curr_seg->next;
  1454. /*
  1455. * If this is a jumbo nbuf, then increment the number of
  1456. * nbuf users for each additional segment of the msdu.
  1457. * This will ensure that the skb is freed only after
  1458. * receiving tx completion for all segments of an nbuf
  1459. */
  1460. qdf_nbuf_inc_users(nbuf);
  1461. /* Check with MCL if this is needed */
  1462. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1463. }
  1464. }
  1465. /*
  1466. * For Multicast-Unicast converted packets,
  1467. * each converted frame (for a client) is represented as
  1468. * 1 segment
  1469. */
  1470. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1471. (msdu_info->frm_type == dp_tx_frm_me)) {
  1472. if (msdu_info->u.sg_info.curr_seg->next) {
  1473. msdu_info->u.sg_info.curr_seg =
  1474. msdu_info->u.sg_info.curr_seg->next;
  1475. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1476. }
  1477. }
  1478. i++;
  1479. }
  1480. nbuf = NULL;
  1481. done:
  1482. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1483. hal_srng_access_end(soc->hal_soc, hal_srng);
  1484. hif_pm_runtime_put(soc->hif_handle);
  1485. } else {
  1486. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1487. }
  1488. return nbuf;
  1489. }
  1490. /**
  1491. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1492. * for SG frames
  1493. * @vdev: DP vdev handle
  1494. * @nbuf: skb
  1495. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1496. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1497. *
  1498. * Return: NULL on success,
  1499. * nbuf when it fails to send
  1500. */
  1501. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1502. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1503. {
  1504. uint32_t cur_frag, nr_frags;
  1505. qdf_dma_addr_t paddr;
  1506. struct dp_tx_sg_info_s *sg_info;
  1507. sg_info = &msdu_info->u.sg_info;
  1508. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1509. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1510. QDF_DMA_TO_DEVICE)) {
  1511. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1512. "dma map error");
  1513. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1514. qdf_nbuf_free(nbuf);
  1515. return NULL;
  1516. }
  1517. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1518. seg_info->frags[0].paddr_lo = paddr;
  1519. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1520. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1521. seg_info->frags[0].vaddr = (void *) nbuf;
  1522. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1523. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1524. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1525. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1526. "frag dma map error");
  1527. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1528. qdf_nbuf_free(nbuf);
  1529. return NULL;
  1530. }
  1531. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1532. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1533. seg_info->frags[cur_frag + 1].paddr_hi =
  1534. ((uint64_t) paddr) >> 32;
  1535. seg_info->frags[cur_frag + 1].len =
  1536. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1537. }
  1538. seg_info->frag_cnt = (cur_frag + 1);
  1539. seg_info->total_len = qdf_nbuf_len(nbuf);
  1540. seg_info->next = NULL;
  1541. sg_info->curr_seg = seg_info;
  1542. msdu_info->frm_type = dp_tx_frm_sg;
  1543. msdu_info->num_seg = 1;
  1544. return nbuf;
  1545. }
  1546. /**
  1547. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1548. * @vdev: DP vdev handle
  1549. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1550. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1551. *
  1552. * Return: NULL on failure,
  1553. * nbuf when extracted successfully
  1554. */
  1555. static
  1556. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1557. struct dp_tx_msdu_info_s *msdu_info,
  1558. uint16_t ppdu_cookie)
  1559. {
  1560. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1561. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1562. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1563. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1564. (msdu_info->meta_data[5], 1);
  1565. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1566. (msdu_info->meta_data[5], 1);
  1567. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1568. (msdu_info->meta_data[6], ppdu_cookie);
  1569. msdu_info->exception_fw = 1;
  1570. msdu_info->is_tx_sniffer = 1;
  1571. }
  1572. #ifdef MESH_MODE_SUPPORT
  1573. /**
  1574. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1575. and prepare msdu_info for mesh frames.
  1576. * @vdev: DP vdev handle
  1577. * @nbuf: skb
  1578. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1579. *
  1580. * Return: NULL on failure,
  1581. * nbuf when extracted successfully
  1582. */
  1583. static
  1584. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1585. struct dp_tx_msdu_info_s *msdu_info)
  1586. {
  1587. struct meta_hdr_s *mhdr;
  1588. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1589. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1590. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1591. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1592. msdu_info->exception_fw = 0;
  1593. goto remove_meta_hdr;
  1594. }
  1595. msdu_info->exception_fw = 1;
  1596. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1597. meta_data->host_tx_desc_pool = 1;
  1598. meta_data->update_peer_cache = 1;
  1599. meta_data->learning_frame = 1;
  1600. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1601. meta_data->power = mhdr->power;
  1602. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1603. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1604. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1605. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1606. meta_data->dyn_bw = 1;
  1607. meta_data->valid_pwr = 1;
  1608. meta_data->valid_mcs_mask = 1;
  1609. meta_data->valid_nss_mask = 1;
  1610. meta_data->valid_preamble_type = 1;
  1611. meta_data->valid_retries = 1;
  1612. meta_data->valid_bw_info = 1;
  1613. }
  1614. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1615. meta_data->encrypt_type = 0;
  1616. meta_data->valid_encrypt_type = 1;
  1617. meta_data->learning_frame = 0;
  1618. }
  1619. meta_data->valid_key_flags = 1;
  1620. meta_data->key_flags = (mhdr->keyix & 0x3);
  1621. remove_meta_hdr:
  1622. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1623. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1624. "qdf_nbuf_pull_head failed");
  1625. qdf_nbuf_free(nbuf);
  1626. return NULL;
  1627. }
  1628. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1629. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1630. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1631. " tid %d to_fw %d",
  1632. __func__, msdu_info->meta_data[0],
  1633. msdu_info->meta_data[1],
  1634. msdu_info->meta_data[2],
  1635. msdu_info->meta_data[3],
  1636. msdu_info->meta_data[4],
  1637. msdu_info->meta_data[5],
  1638. msdu_info->tid, msdu_info->exception_fw);
  1639. return nbuf;
  1640. }
  1641. #else
  1642. static
  1643. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1644. struct dp_tx_msdu_info_s *msdu_info)
  1645. {
  1646. return nbuf;
  1647. }
  1648. #endif
  1649. /**
  1650. * dp_check_exc_metadata() - Checks if parameters are valid
  1651. * @tx_exc - holds all exception path parameters
  1652. *
  1653. * Returns true when all the parameters are valid else false
  1654. *
  1655. */
  1656. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1657. {
  1658. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1659. HTT_INVALID_TID);
  1660. bool invalid_encap_type = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1661. HTT_INVALID_TID);
  1662. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1663. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1664. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1665. tx_exc->ppdu_cookie == 0);
  1666. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1667. invalid_cookie) {
  1668. return false;
  1669. }
  1670. return true;
  1671. }
  1672. /**
  1673. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1674. * @vap_dev: DP vdev handle
  1675. * @nbuf: skb
  1676. * @tx_exc_metadata: Handle that holds exception path meta data
  1677. *
  1678. * Entry point for Core Tx layer (DP_TX) invoked from
  1679. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1680. *
  1681. * Return: NULL on success,
  1682. * nbuf when it fails to send
  1683. */
  1684. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1685. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1686. {
  1687. qdf_ether_header_t *eh = NULL;
  1688. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1689. struct dp_tx_msdu_info_s msdu_info;
  1690. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1691. if (!tx_exc_metadata)
  1692. goto fail;
  1693. msdu_info.tid = tx_exc_metadata->tid;
  1694. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1695. dp_verbose_debug("skb %pM", nbuf->data);
  1696. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1697. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1698. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1699. "Invalid parameters in exception path");
  1700. goto fail;
  1701. }
  1702. /* Basic sanity checks for unsupported packets */
  1703. /* MESH mode */
  1704. if (qdf_unlikely(vdev->mesh_vdev)) {
  1705. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1706. "Mesh mode is not supported in exception path");
  1707. goto fail;
  1708. }
  1709. /* TSO or SG */
  1710. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1711. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1712. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1713. "TSO and SG are not supported in exception path");
  1714. goto fail;
  1715. }
  1716. /* RAW */
  1717. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1718. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1719. "Raw frame is not supported in exception path");
  1720. goto fail;
  1721. }
  1722. /* Mcast enhancement*/
  1723. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1724. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1725. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1726. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1727. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1728. }
  1729. }
  1730. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1731. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1732. qdf_nbuf_len(nbuf));
  1733. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1734. tx_exc_metadata->ppdu_cookie);
  1735. }
  1736. /*
  1737. * Get HW Queue to use for this frame.
  1738. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1739. * dedicated for data and 1 for command.
  1740. * "queue_id" maps to one hardware ring.
  1741. * With each ring, we also associate a unique Tx descriptor pool
  1742. * to minimize lock contention for these resources.
  1743. */
  1744. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1745. /* Single linear frame */
  1746. /*
  1747. * If nbuf is a simple linear frame, use send_single function to
  1748. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1749. * SRNG. There is no need to setup a MSDU extension descriptor.
  1750. */
  1751. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1752. tx_exc_metadata->peer_id, tx_exc_metadata);
  1753. return nbuf;
  1754. fail:
  1755. dp_verbose_debug("pkt send failed");
  1756. return nbuf;
  1757. }
  1758. /**
  1759. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1760. * @vap_dev: DP vdev handle
  1761. * @nbuf: skb
  1762. *
  1763. * Entry point for Core Tx layer (DP_TX) invoked from
  1764. * hard_start_xmit in OSIF/HDD
  1765. *
  1766. * Return: NULL on success,
  1767. * nbuf when it fails to send
  1768. */
  1769. #ifdef MESH_MODE_SUPPORT
  1770. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1771. {
  1772. struct meta_hdr_s *mhdr;
  1773. qdf_nbuf_t nbuf_mesh = NULL;
  1774. qdf_nbuf_t nbuf_clone = NULL;
  1775. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1776. uint8_t no_enc_frame = 0;
  1777. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1778. if (!nbuf_mesh) {
  1779. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1780. "qdf_nbuf_unshare failed");
  1781. return nbuf;
  1782. }
  1783. nbuf = nbuf_mesh;
  1784. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1785. if ((vdev->sec_type != cdp_sec_type_none) &&
  1786. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1787. no_enc_frame = 1;
  1788. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1789. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1790. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1791. !no_enc_frame) {
  1792. nbuf_clone = qdf_nbuf_clone(nbuf);
  1793. if (!nbuf_clone) {
  1794. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1795. "qdf_nbuf_clone failed");
  1796. return nbuf;
  1797. }
  1798. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1799. }
  1800. if (nbuf_clone) {
  1801. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1802. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1803. } else {
  1804. qdf_nbuf_free(nbuf_clone);
  1805. }
  1806. }
  1807. if (no_enc_frame)
  1808. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1809. else
  1810. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1811. nbuf = dp_tx_send(vap_dev, nbuf);
  1812. if ((!nbuf) && no_enc_frame) {
  1813. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1814. }
  1815. return nbuf;
  1816. }
  1817. #else
  1818. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1819. {
  1820. return dp_tx_send(vap_dev, nbuf);
  1821. }
  1822. #endif
  1823. /**
  1824. * dp_tx_send() - Transmit a frame on a given VAP
  1825. * @vap_dev: DP vdev handle
  1826. * @nbuf: skb
  1827. *
  1828. * Entry point for Core Tx layer (DP_TX) invoked from
  1829. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1830. * cases
  1831. *
  1832. * Return: NULL on success,
  1833. * nbuf when it fails to send
  1834. */
  1835. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1836. {
  1837. qdf_ether_header_t *eh = NULL;
  1838. struct dp_tx_msdu_info_s msdu_info;
  1839. struct dp_tx_seg_info_s seg_info;
  1840. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1841. uint16_t peer_id = HTT_INVALID_PEER;
  1842. qdf_nbuf_t nbuf_mesh = NULL;
  1843. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1844. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1845. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1846. dp_verbose_debug("skb %pM", nbuf->data);
  1847. /*
  1848. * Set Default Host TID value to invalid TID
  1849. * (TID override disabled)
  1850. */
  1851. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1852. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1853. if (qdf_unlikely(vdev->mesh_vdev)) {
  1854. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1855. &msdu_info);
  1856. if (!nbuf_mesh) {
  1857. dp_verbose_debug("Extracting mesh metadata failed");
  1858. return nbuf;
  1859. }
  1860. nbuf = nbuf_mesh;
  1861. }
  1862. /*
  1863. * Get HW Queue to use for this frame.
  1864. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1865. * dedicated for data and 1 for command.
  1866. * "queue_id" maps to one hardware ring.
  1867. * With each ring, we also associate a unique Tx descriptor pool
  1868. * to minimize lock contention for these resources.
  1869. */
  1870. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1871. /*
  1872. * TCL H/W supports 2 DSCP-TID mapping tables.
  1873. * Table 1 - Default DSCP-TID mapping table
  1874. * Table 2 - 1 DSCP-TID override table
  1875. *
  1876. * If we need a different DSCP-TID mapping for this vap,
  1877. * call tid_classify to extract DSCP/ToS from frame and
  1878. * map to a TID and store in msdu_info. This is later used
  1879. * to fill in TCL Input descriptor (per-packet TID override).
  1880. */
  1881. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1882. /*
  1883. * Classify the frame and call corresponding
  1884. * "prepare" function which extracts the segment (TSO)
  1885. * and fragmentation information (for TSO , SG, ME, or Raw)
  1886. * into MSDU_INFO structure which is later used to fill
  1887. * SW and HW descriptors.
  1888. */
  1889. if (qdf_nbuf_is_tso(nbuf)) {
  1890. dp_verbose_debug("TSO frame %pK", vdev);
  1891. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1892. qdf_nbuf_len(nbuf));
  1893. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1894. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1895. qdf_nbuf_len(nbuf));
  1896. return nbuf;
  1897. }
  1898. goto send_multiple;
  1899. }
  1900. /* SG */
  1901. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1902. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1903. if (!nbuf)
  1904. return NULL;
  1905. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1906. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1907. qdf_nbuf_len(nbuf));
  1908. goto send_multiple;
  1909. }
  1910. #ifdef ATH_SUPPORT_IQUE
  1911. /* Mcast to Ucast Conversion*/
  1912. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1913. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1914. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1915. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1916. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1917. DP_STATS_INC_PKT(vdev,
  1918. tx_i.mcast_en.mcast_pkt, 1,
  1919. qdf_nbuf_len(nbuf));
  1920. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1921. QDF_STATUS_SUCCESS) {
  1922. return NULL;
  1923. }
  1924. }
  1925. }
  1926. #endif
  1927. /* RAW */
  1928. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1929. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1930. if (!nbuf)
  1931. return NULL;
  1932. dp_verbose_debug("Raw frame %pK", vdev);
  1933. goto send_multiple;
  1934. }
  1935. /* Single linear frame */
  1936. /*
  1937. * If nbuf is a simple linear frame, use send_single function to
  1938. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1939. * SRNG. There is no need to setup a MSDU extension descriptor.
  1940. */
  1941. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1942. return nbuf;
  1943. send_multiple:
  1944. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1945. return nbuf;
  1946. }
  1947. /**
  1948. * dp_tx_reinject_handler() - Tx Reinject Handler
  1949. * @tx_desc: software descriptor head pointer
  1950. * @status : Tx completion status from HTT descriptor
  1951. *
  1952. * This function reinjects frames back to Target.
  1953. * Todo - Host queue needs to be added
  1954. *
  1955. * Return: none
  1956. */
  1957. static
  1958. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1959. {
  1960. struct dp_vdev *vdev;
  1961. struct dp_peer *peer = NULL;
  1962. uint32_t peer_id = HTT_INVALID_PEER;
  1963. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1964. qdf_nbuf_t nbuf_copy = NULL;
  1965. struct dp_tx_msdu_info_s msdu_info;
  1966. struct dp_peer *sa_peer = NULL;
  1967. struct dp_ast_entry *ast_entry = NULL;
  1968. struct dp_soc *soc = NULL;
  1969. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1970. #ifdef WDS_VENDOR_EXTENSION
  1971. int is_mcast = 0, is_ucast = 0;
  1972. int num_peers_3addr = 0;
  1973. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  1974. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1975. #endif
  1976. vdev = tx_desc->vdev;
  1977. soc = vdev->pdev->soc;
  1978. qdf_assert(vdev);
  1979. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1980. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1981. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1982. "%s Tx reinject path", __func__);
  1983. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1984. qdf_nbuf_len(tx_desc->nbuf));
  1985. qdf_spin_lock_bh(&(soc->ast_lock));
  1986. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1987. (soc,
  1988. (uint8_t *)(eh->ether_shost),
  1989. vdev->pdev->pdev_id);
  1990. if (ast_entry)
  1991. sa_peer = ast_entry->peer;
  1992. qdf_spin_unlock_bh(&(soc->ast_lock));
  1993. #ifdef WDS_VENDOR_EXTENSION
  1994. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1995. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1996. } else {
  1997. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1998. }
  1999. is_ucast = !is_mcast;
  2000. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2001. if (peer->bss_peer)
  2002. continue;
  2003. /* Detect wds peers that use 3-addr framing for mcast.
  2004. * if there are any, the bss_peer is used to send the
  2005. * the mcast frame using 3-addr format. all wds enabled
  2006. * peers that use 4-addr framing for mcast frames will
  2007. * be duplicated and sent as 4-addr frames below.
  2008. */
  2009. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2010. num_peers_3addr = 1;
  2011. break;
  2012. }
  2013. }
  2014. #endif
  2015. if (qdf_unlikely(vdev->mesh_vdev)) {
  2016. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2017. } else {
  2018. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2019. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2020. #ifdef WDS_VENDOR_EXTENSION
  2021. /*
  2022. * . if 3-addr STA, then send on BSS Peer
  2023. * . if Peer WDS enabled and accept 4-addr mcast,
  2024. * send mcast on that peer only
  2025. * . if Peer WDS enabled and accept 4-addr ucast,
  2026. * send ucast on that peer only
  2027. */
  2028. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2029. (peer->wds_enabled &&
  2030. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2031. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2032. #else
  2033. ((peer->bss_peer &&
  2034. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2035. peer->nawds_enabled)) {
  2036. #endif
  2037. peer_id = DP_INVALID_PEER;
  2038. if (peer->nawds_enabled) {
  2039. peer_id = peer->peer_ids[0];
  2040. if (sa_peer == peer) {
  2041. QDF_TRACE(
  2042. QDF_MODULE_ID_DP,
  2043. QDF_TRACE_LEVEL_DEBUG,
  2044. " %s: multicast packet",
  2045. __func__);
  2046. DP_STATS_INC(peer,
  2047. tx.nawds_mcast_drop, 1);
  2048. continue;
  2049. }
  2050. }
  2051. nbuf_copy = qdf_nbuf_copy(nbuf);
  2052. if (!nbuf_copy) {
  2053. QDF_TRACE(QDF_MODULE_ID_DP,
  2054. QDF_TRACE_LEVEL_DEBUG,
  2055. FL("nbuf copy failed"));
  2056. break;
  2057. }
  2058. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2059. nbuf_copy,
  2060. &msdu_info,
  2061. peer_id,
  2062. NULL);
  2063. if (nbuf_copy) {
  2064. QDF_TRACE(QDF_MODULE_ID_DP,
  2065. QDF_TRACE_LEVEL_DEBUG,
  2066. FL("pkt send failed"));
  2067. qdf_nbuf_free(nbuf_copy);
  2068. } else {
  2069. if (peer_id != DP_INVALID_PEER)
  2070. DP_STATS_INC_PKT(peer,
  2071. tx.nawds_mcast,
  2072. 1, qdf_nbuf_len(nbuf));
  2073. }
  2074. }
  2075. }
  2076. }
  2077. if (vdev->nawds_enabled) {
  2078. peer_id = DP_INVALID_PEER;
  2079. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2080. 1, qdf_nbuf_len(nbuf));
  2081. nbuf = dp_tx_send_msdu_single(vdev,
  2082. nbuf,
  2083. &msdu_info,
  2084. peer_id, NULL);
  2085. if (nbuf) {
  2086. QDF_TRACE(QDF_MODULE_ID_DP,
  2087. QDF_TRACE_LEVEL_DEBUG,
  2088. FL("pkt send failed"));
  2089. qdf_nbuf_free(nbuf);
  2090. }
  2091. } else
  2092. qdf_nbuf_free(nbuf);
  2093. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2094. }
  2095. /**
  2096. * dp_tx_inspect_handler() - Tx Inspect Handler
  2097. * @tx_desc: software descriptor head pointer
  2098. * @status : Tx completion status from HTT descriptor
  2099. *
  2100. * Handles Tx frames sent back to Host for inspection
  2101. * (ProxyARP)
  2102. *
  2103. * Return: none
  2104. */
  2105. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2106. {
  2107. struct dp_soc *soc;
  2108. struct dp_pdev *pdev = tx_desc->pdev;
  2109. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2110. "%s Tx inspect path",
  2111. __func__);
  2112. qdf_assert(pdev);
  2113. soc = pdev->soc;
  2114. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2115. qdf_nbuf_len(tx_desc->nbuf));
  2116. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2117. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2118. }
  2119. #ifdef FEATURE_PERPKT_INFO
  2120. /**
  2121. * dp_get_completion_indication_for_stack() - send completion to stack
  2122. * @soc : dp_soc handle
  2123. * @pdev: dp_pdev handle
  2124. * @peer: dp peer handle
  2125. * @ts: transmit completion status structure
  2126. * @netbuf: Buffer pointer for free
  2127. *
  2128. * This function is used for indication whether buffer needs to be
  2129. * sent to stack for freeing or not
  2130. */
  2131. QDF_STATUS
  2132. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2133. struct dp_pdev *pdev,
  2134. struct dp_peer *peer,
  2135. struct hal_tx_completion_status *ts,
  2136. qdf_nbuf_t netbuf,
  2137. uint64_t time_latency)
  2138. {
  2139. struct tx_capture_hdr *ppdu_hdr;
  2140. uint16_t peer_id = ts->peer_id;
  2141. uint32_t ppdu_id = ts->ppdu_id;
  2142. uint8_t first_msdu = ts->first_msdu;
  2143. uint8_t last_msdu = ts->last_msdu;
  2144. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2145. !pdev->latency_capture_enable))
  2146. return QDF_STATUS_E_NOSUPPORT;
  2147. if (!peer) {
  2148. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2149. FL("Peer Invalid"));
  2150. return QDF_STATUS_E_INVAL;
  2151. }
  2152. if (pdev->mcopy_mode) {
  2153. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2154. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2155. return QDF_STATUS_E_INVAL;
  2156. }
  2157. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2158. pdev->m_copy_id.tx_peer_id = peer_id;
  2159. }
  2160. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2161. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2162. FL("No headroom"));
  2163. return QDF_STATUS_E_NOMEM;
  2164. }
  2165. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2166. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2167. QDF_MAC_ADDR_SIZE);
  2168. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2169. QDF_MAC_ADDR_SIZE);
  2170. ppdu_hdr->ppdu_id = ppdu_id;
  2171. ppdu_hdr->peer_id = peer_id;
  2172. ppdu_hdr->first_msdu = first_msdu;
  2173. ppdu_hdr->last_msdu = last_msdu;
  2174. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2175. ppdu_hdr->tsf = ts->tsf;
  2176. ppdu_hdr->time_latency = time_latency;
  2177. }
  2178. return QDF_STATUS_SUCCESS;
  2179. }
  2180. /**
  2181. * dp_send_completion_to_stack() - send completion to stack
  2182. * @soc : dp_soc handle
  2183. * @pdev: dp_pdev handle
  2184. * @peer_id: peer_id of the peer for which completion came
  2185. * @ppdu_id: ppdu_id
  2186. * @netbuf: Buffer pointer for free
  2187. *
  2188. * This function is used to send completion to stack
  2189. * to free buffer
  2190. */
  2191. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2192. uint16_t peer_id, uint32_t ppdu_id,
  2193. qdf_nbuf_t netbuf)
  2194. {
  2195. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2196. netbuf, peer_id,
  2197. WDI_NO_VAL, pdev->pdev_id);
  2198. }
  2199. #else
  2200. static QDF_STATUS
  2201. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2202. struct dp_pdev *pdev,
  2203. struct dp_peer *peer,
  2204. struct hal_tx_completion_status *ts,
  2205. qdf_nbuf_t netbuf,
  2206. uint64_t time_latency)
  2207. {
  2208. return QDF_STATUS_E_NOSUPPORT;
  2209. }
  2210. static void
  2211. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2212. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2213. {
  2214. }
  2215. #endif
  2216. /**
  2217. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2218. * @soc: Soc handle
  2219. * @desc: software Tx descriptor to be processed
  2220. *
  2221. * Return: none
  2222. */
  2223. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2224. struct dp_tx_desc_s *desc)
  2225. {
  2226. struct dp_vdev *vdev = desc->vdev;
  2227. qdf_nbuf_t nbuf = desc->nbuf;
  2228. /* nbuf already freed in vdev detach path */
  2229. if (!nbuf)
  2230. return;
  2231. /* If it is TDLS mgmt, don't unmap or free the frame */
  2232. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2233. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2234. /* 0 : MSDU buffer, 1 : MLE */
  2235. if (desc->msdu_ext_desc) {
  2236. /* TSO free */
  2237. if (hal_tx_ext_desc_get_tso_enable(
  2238. desc->msdu_ext_desc->vaddr)) {
  2239. /* unmap eash TSO seg before free the nbuf */
  2240. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2241. desc->tso_num_desc);
  2242. qdf_nbuf_free(nbuf);
  2243. return;
  2244. }
  2245. }
  2246. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2247. if (qdf_unlikely(!vdev)) {
  2248. qdf_nbuf_free(nbuf);
  2249. return;
  2250. }
  2251. if (qdf_likely(!vdev->mesh_vdev))
  2252. qdf_nbuf_free(nbuf);
  2253. else {
  2254. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2255. qdf_nbuf_free(nbuf);
  2256. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2257. } else
  2258. vdev->osif_tx_free_ext((nbuf));
  2259. }
  2260. }
  2261. #ifdef MESH_MODE_SUPPORT
  2262. /**
  2263. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2264. * in mesh meta header
  2265. * @tx_desc: software descriptor head pointer
  2266. * @ts: pointer to tx completion stats
  2267. * Return: none
  2268. */
  2269. static
  2270. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2271. struct hal_tx_completion_status *ts)
  2272. {
  2273. struct meta_hdr_s *mhdr;
  2274. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2275. if (!tx_desc->msdu_ext_desc) {
  2276. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2277. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2278. "netbuf %pK offset %d",
  2279. netbuf, tx_desc->pkt_offset);
  2280. return;
  2281. }
  2282. }
  2283. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2284. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2285. "netbuf %pK offset %lu", netbuf,
  2286. sizeof(struct meta_hdr_s));
  2287. return;
  2288. }
  2289. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2290. mhdr->rssi = ts->ack_frame_rssi;
  2291. mhdr->channel = tx_desc->pdev->operating_channel;
  2292. }
  2293. #else
  2294. static
  2295. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2296. struct hal_tx_completion_status *ts)
  2297. {
  2298. }
  2299. #endif
  2300. /**
  2301. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2302. * to pass in correct fields
  2303. *
  2304. * @vdev: pdev handle
  2305. * @tx_desc: tx descriptor
  2306. * @tid: tid value
  2307. * @ring_id: TCL or WBM ring number for transmit path
  2308. * Return: none
  2309. */
  2310. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2311. struct dp_tx_desc_s *tx_desc,
  2312. uint8_t tid, uint8_t ring_id)
  2313. {
  2314. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2315. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2316. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2317. return;
  2318. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2319. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2320. timestamp_hw_enqueue = tx_desc->timestamp;
  2321. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2322. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2323. timestamp_hw_enqueue);
  2324. interframe_delay = (uint32_t)(timestamp_ingress -
  2325. vdev->prev_tx_enq_tstamp);
  2326. /*
  2327. * Delay in software enqueue
  2328. */
  2329. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2330. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2331. /*
  2332. * Delay between packet enqueued to HW and Tx completion
  2333. */
  2334. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2335. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2336. /*
  2337. * Update interframe delay stats calculated at hardstart receive point.
  2338. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2339. * interframe delay will not be calculate correctly for 1st frame.
  2340. * On the other side, this will help in avoiding extra per packet check
  2341. * of !vdev->prev_tx_enq_tstamp.
  2342. */
  2343. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2344. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2345. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2346. }
  2347. /**
  2348. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2349. * per wbm ring
  2350. *
  2351. * @tx_desc: software descriptor head pointer
  2352. * @ts: Tx completion status
  2353. * @peer: peer handle
  2354. * @ring_id: ring number
  2355. *
  2356. * Return: None
  2357. */
  2358. static inline void
  2359. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2360. struct hal_tx_completion_status *ts,
  2361. struct dp_peer *peer, uint8_t ring_id)
  2362. {
  2363. struct dp_pdev *pdev = peer->vdev->pdev;
  2364. struct dp_soc *soc = NULL;
  2365. uint8_t mcs, pkt_type;
  2366. uint8_t tid = ts->tid;
  2367. uint32_t length;
  2368. struct cdp_tid_tx_stats *tid_stats;
  2369. if (!pdev)
  2370. return;
  2371. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2372. tid = CDP_MAX_DATA_TIDS - 1;
  2373. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2374. soc = pdev->soc;
  2375. mcs = ts->mcs;
  2376. pkt_type = ts->pkt_type;
  2377. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2378. dp_err("Release source is not from TQM");
  2379. return;
  2380. }
  2381. length = qdf_nbuf_len(tx_desc->nbuf);
  2382. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2383. if (qdf_unlikely(pdev->delay_stats_flag))
  2384. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2385. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2386. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2387. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2388. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2389. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2390. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2391. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2392. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2393. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2394. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2395. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2396. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2397. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2398. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2399. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2400. tid_stats->comp_fail_cnt++;
  2401. return;
  2402. }
  2403. tid_stats->success_cnt++;
  2404. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2405. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2406. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2407. /*
  2408. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2409. * Return from here if HTT PPDU events are enabled.
  2410. */
  2411. if (!(soc->process_tx_status))
  2412. return;
  2413. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2414. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2415. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2416. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2417. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2418. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2419. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2420. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2421. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2422. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2423. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2424. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2425. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2426. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2427. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2428. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2429. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2430. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2431. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2432. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2433. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2434. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2435. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2436. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2437. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2438. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2439. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2440. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2441. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2442. &peer->stats, ts->peer_id,
  2443. UPDATE_PEER_STATS, pdev->pdev_id);
  2444. #endif
  2445. }
  2446. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2447. /**
  2448. * dp_tx_flow_pool_lock() - take flow pool lock
  2449. * @soc: core txrx main context
  2450. * @tx_desc: tx desc
  2451. *
  2452. * Return: None
  2453. */
  2454. static inline
  2455. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2456. struct dp_tx_desc_s *tx_desc)
  2457. {
  2458. struct dp_tx_desc_pool_s *pool;
  2459. uint8_t desc_pool_id;
  2460. desc_pool_id = tx_desc->pool_id;
  2461. pool = &soc->tx_desc[desc_pool_id];
  2462. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2463. }
  2464. /**
  2465. * dp_tx_flow_pool_unlock() - release flow pool lock
  2466. * @soc: core txrx main context
  2467. * @tx_desc: tx desc
  2468. *
  2469. * Return: None
  2470. */
  2471. static inline
  2472. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2473. struct dp_tx_desc_s *tx_desc)
  2474. {
  2475. struct dp_tx_desc_pool_s *pool;
  2476. uint8_t desc_pool_id;
  2477. desc_pool_id = tx_desc->pool_id;
  2478. pool = &soc->tx_desc[desc_pool_id];
  2479. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2480. }
  2481. #else
  2482. static inline
  2483. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2484. {
  2485. }
  2486. static inline
  2487. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2488. {
  2489. }
  2490. #endif
  2491. /**
  2492. * dp_tx_notify_completion() - Notify tx completion for this desc
  2493. * @soc: core txrx main context
  2494. * @tx_desc: tx desc
  2495. * @netbuf: buffer
  2496. *
  2497. * Return: none
  2498. */
  2499. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2500. struct dp_tx_desc_s *tx_desc,
  2501. qdf_nbuf_t netbuf)
  2502. {
  2503. void *osif_dev;
  2504. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2505. qdf_assert(tx_desc);
  2506. dp_tx_flow_pool_lock(soc, tx_desc);
  2507. if (!tx_desc->vdev ||
  2508. !tx_desc->vdev->osif_vdev) {
  2509. dp_tx_flow_pool_unlock(soc, tx_desc);
  2510. return;
  2511. }
  2512. osif_dev = tx_desc->vdev->osif_vdev;
  2513. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2514. dp_tx_flow_pool_unlock(soc, tx_desc);
  2515. if (tx_compl_cbk)
  2516. tx_compl_cbk(netbuf, osif_dev);
  2517. }
  2518. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2519. * @pdev: pdev handle
  2520. * @tid: tid value
  2521. * @txdesc_ts: timestamp from txdesc
  2522. * @ppdu_id: ppdu id
  2523. *
  2524. * Return: none
  2525. */
  2526. #ifdef FEATURE_PERPKT_INFO
  2527. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2528. struct dp_peer *peer,
  2529. uint8_t tid,
  2530. uint64_t txdesc_ts,
  2531. uint32_t ppdu_id)
  2532. {
  2533. uint64_t delta_ms;
  2534. struct cdp_tx_sojourn_stats *sojourn_stats;
  2535. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2536. return;
  2537. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2538. tid >= CDP_DATA_TID_MAX))
  2539. return;
  2540. if (qdf_unlikely(!pdev->sojourn_buf))
  2541. return;
  2542. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2543. qdf_nbuf_data(pdev->sojourn_buf);
  2544. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2545. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2546. txdesc_ts;
  2547. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2548. delta_ms);
  2549. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2550. sojourn_stats->num_msdus[tid] = 1;
  2551. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2552. peer->avg_sojourn_msdu[tid].internal;
  2553. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2554. pdev->sojourn_buf, HTT_INVALID_PEER,
  2555. WDI_NO_VAL, pdev->pdev_id);
  2556. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2557. sojourn_stats->num_msdus[tid] = 0;
  2558. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2559. }
  2560. #else
  2561. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2562. uint8_t tid,
  2563. uint64_t txdesc_ts,
  2564. uint32_t ppdu_id)
  2565. {
  2566. }
  2567. #endif
  2568. /**
  2569. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2570. * @soc: DP Soc handle
  2571. * @tx_desc: software Tx descriptor
  2572. * @ts : Tx completion status from HAL/HTT descriptor
  2573. *
  2574. * Return: none
  2575. */
  2576. static inline void
  2577. dp_tx_comp_process_desc(struct dp_soc *soc,
  2578. struct dp_tx_desc_s *desc,
  2579. struct hal_tx_completion_status *ts,
  2580. struct dp_peer *peer)
  2581. {
  2582. uint64_t time_latency = 0;
  2583. /*
  2584. * m_copy/tx_capture modes are not supported for
  2585. * scatter gather packets
  2586. */
  2587. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2588. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2589. desc->timestamp);
  2590. }
  2591. if (!(desc->msdu_ext_desc)) {
  2592. if (QDF_STATUS_SUCCESS ==
  2593. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2594. return;
  2595. }
  2596. if (QDF_STATUS_SUCCESS ==
  2597. dp_get_completion_indication_for_stack(soc,
  2598. desc->pdev,
  2599. peer, ts,
  2600. desc->nbuf,
  2601. time_latency)) {
  2602. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2603. QDF_DMA_TO_DEVICE);
  2604. dp_send_completion_to_stack(soc,
  2605. desc->pdev,
  2606. ts->peer_id,
  2607. ts->ppdu_id,
  2608. desc->nbuf);
  2609. return;
  2610. }
  2611. }
  2612. dp_tx_comp_free_buf(soc, desc);
  2613. }
  2614. /**
  2615. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2616. * @tx_desc: software descriptor head pointer
  2617. * @ts: Tx completion status
  2618. * @peer: peer handle
  2619. * @ring_id: ring number
  2620. *
  2621. * Return: none
  2622. */
  2623. static inline
  2624. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2625. struct hal_tx_completion_status *ts,
  2626. struct dp_peer *peer, uint8_t ring_id)
  2627. {
  2628. uint32_t length;
  2629. qdf_ether_header_t *eh;
  2630. struct dp_soc *soc = NULL;
  2631. struct dp_vdev *vdev = tx_desc->vdev;
  2632. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2633. if (!vdev || !nbuf) {
  2634. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2635. "invalid tx descriptor. vdev or nbuf NULL");
  2636. goto out;
  2637. }
  2638. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2639. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2640. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2641. QDF_TRACE_DEFAULT_PDEV_ID,
  2642. qdf_nbuf_data_addr(nbuf),
  2643. sizeof(qdf_nbuf_data(nbuf)),
  2644. tx_desc->id,
  2645. ts->status));
  2646. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2647. "-------------------- \n"
  2648. "Tx Completion Stats: \n"
  2649. "-------------------- \n"
  2650. "ack_frame_rssi = %d \n"
  2651. "first_msdu = %d \n"
  2652. "last_msdu = %d \n"
  2653. "msdu_part_of_amsdu = %d \n"
  2654. "rate_stats valid = %d \n"
  2655. "bw = %d \n"
  2656. "pkt_type = %d \n"
  2657. "stbc = %d \n"
  2658. "ldpc = %d \n"
  2659. "sgi = %d \n"
  2660. "mcs = %d \n"
  2661. "ofdma = %d \n"
  2662. "tones_in_ru = %d \n"
  2663. "tsf = %d \n"
  2664. "ppdu_id = %d \n"
  2665. "transmit_cnt = %d \n"
  2666. "tid = %d \n"
  2667. "peer_id = %d\n",
  2668. ts->ack_frame_rssi, ts->first_msdu,
  2669. ts->last_msdu, ts->msdu_part_of_amsdu,
  2670. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2671. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2672. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2673. ts->transmit_cnt, ts->tid, ts->peer_id);
  2674. soc = vdev->pdev->soc;
  2675. /* Update SoC level stats */
  2676. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2677. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2678. /* Update per-packet stats for mesh mode */
  2679. if (qdf_unlikely(vdev->mesh_vdev) &&
  2680. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2681. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2682. length = qdf_nbuf_len(nbuf);
  2683. /* Update peer level stats */
  2684. if (!peer) {
  2685. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2686. "peer is null or deletion in progress");
  2687. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2688. goto out;
  2689. }
  2690. if (qdf_likely(!peer->bss_peer)) {
  2691. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2692. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2693. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2694. } else {
  2695. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2696. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2697. if ((peer->vdev->tx_encap_type ==
  2698. htt_cmn_pkt_type_ethernet) &&
  2699. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2700. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2701. }
  2702. }
  2703. }
  2704. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2705. #ifdef QCA_SUPPORT_RDK_STATS
  2706. if (soc->wlanstats_enabled)
  2707. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2708. tx_desc->timestamp,
  2709. ts->ppdu_id);
  2710. #endif
  2711. out:
  2712. return;
  2713. }
  2714. /**
  2715. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2716. * @soc: core txrx main context
  2717. * @comp_head: software descriptor head pointer
  2718. * @ring_id: ring number
  2719. *
  2720. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2721. * and release the software descriptors after processing is complete
  2722. *
  2723. * Return: none
  2724. */
  2725. static void
  2726. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2727. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2728. {
  2729. struct dp_tx_desc_s *desc;
  2730. struct dp_tx_desc_s *next;
  2731. struct hal_tx_completion_status ts = {0};
  2732. struct dp_peer *peer;
  2733. qdf_nbuf_t netbuf;
  2734. desc = comp_head;
  2735. while (desc) {
  2736. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2737. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2738. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2739. netbuf = desc->nbuf;
  2740. /* check tx complete notification */
  2741. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2742. dp_tx_notify_completion(soc, desc, netbuf);
  2743. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2744. if (peer)
  2745. dp_peer_unref_del_find_by_id(peer);
  2746. next = desc->next;
  2747. dp_tx_desc_release(desc, desc->pool_id);
  2748. desc = next;
  2749. }
  2750. }
  2751. /**
  2752. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2753. * @tx_desc: software descriptor head pointer
  2754. * @status : Tx completion status from HTT descriptor
  2755. * @ring_id: ring number
  2756. *
  2757. * This function will process HTT Tx indication messages from Target
  2758. *
  2759. * Return: none
  2760. */
  2761. static
  2762. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2763. uint8_t ring_id)
  2764. {
  2765. uint8_t tx_status;
  2766. struct dp_pdev *pdev;
  2767. struct dp_vdev *vdev;
  2768. struct dp_soc *soc;
  2769. struct hal_tx_completion_status ts = {0};
  2770. uint32_t *htt_desc = (uint32_t *)status;
  2771. struct dp_peer *peer;
  2772. struct cdp_tid_tx_stats *tid_stats = NULL;
  2773. qdf_assert(tx_desc->pdev);
  2774. pdev = tx_desc->pdev;
  2775. vdev = tx_desc->vdev;
  2776. soc = pdev->soc;
  2777. if (!vdev)
  2778. return;
  2779. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2780. switch (tx_status) {
  2781. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2782. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2783. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2784. {
  2785. uint8_t tid;
  2786. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2787. ts.peer_id =
  2788. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2789. htt_desc[2]);
  2790. ts.tid =
  2791. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2792. htt_desc[2]);
  2793. } else {
  2794. ts.peer_id = HTT_INVALID_PEER;
  2795. ts.tid = HTT_INVALID_TID;
  2796. }
  2797. ts.ppdu_id =
  2798. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2799. htt_desc[1]);
  2800. ts.ack_frame_rssi =
  2801. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2802. htt_desc[1]);
  2803. ts.first_msdu = 1;
  2804. ts.last_msdu = 1;
  2805. tid = ts.tid;
  2806. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2807. tid = CDP_MAX_DATA_TIDS - 1;
  2808. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2809. if (qdf_unlikely(pdev->delay_stats_flag))
  2810. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2811. if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
  2812. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2813. tid_stats->comp_fail_cnt++;
  2814. } else {
  2815. tid_stats->success_cnt++;
  2816. }
  2817. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2818. if (qdf_likely(peer))
  2819. dp_peer_unref_del_find_by_id(peer);
  2820. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2821. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2822. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2823. break;
  2824. }
  2825. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2826. {
  2827. dp_tx_reinject_handler(tx_desc, status);
  2828. break;
  2829. }
  2830. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2831. {
  2832. dp_tx_inspect_handler(tx_desc, status);
  2833. break;
  2834. }
  2835. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2836. {
  2837. dp_tx_mec_handler(vdev, status);
  2838. break;
  2839. }
  2840. default:
  2841. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2842. "%s Invalid HTT tx_status %d\n",
  2843. __func__, tx_status);
  2844. break;
  2845. }
  2846. }
  2847. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2848. static inline
  2849. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2850. {
  2851. bool limit_hit = false;
  2852. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2853. limit_hit =
  2854. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2855. if (limit_hit)
  2856. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2857. return limit_hit;
  2858. }
  2859. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2860. {
  2861. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2862. }
  2863. #else
  2864. static inline
  2865. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2866. {
  2867. return false;
  2868. }
  2869. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2870. {
  2871. return false;
  2872. }
  2873. #endif
  2874. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2875. void *hal_srng, uint8_t ring_id, uint32_t quota)
  2876. {
  2877. void *tx_comp_hal_desc;
  2878. uint8_t buffer_src;
  2879. uint8_t pool_id;
  2880. uint32_t tx_desc_id;
  2881. struct dp_tx_desc_s *tx_desc = NULL;
  2882. struct dp_tx_desc_s *head_desc = NULL;
  2883. struct dp_tx_desc_s *tail_desc = NULL;
  2884. uint32_t num_processed = 0;
  2885. uint32_t count = 0;
  2886. bool force_break = false;
  2887. DP_HIST_INIT();
  2888. more_data:
  2889. /* Re-initialize local variables to be re-used */
  2890. head_desc = NULL;
  2891. tail_desc = NULL;
  2892. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2893. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2894. "%s %d : HAL RING Access Failed -- %pK",
  2895. __func__, __LINE__, hal_srng);
  2896. return 0;
  2897. }
  2898. /* Find head descriptor from completion ring */
  2899. while (qdf_likely(tx_comp_hal_desc =
  2900. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2901. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2902. /* If this buffer was not released by TQM or FW, then it is not
  2903. * Tx completion indication, assert */
  2904. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2905. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2906. QDF_TRACE(QDF_MODULE_ID_DP,
  2907. QDF_TRACE_LEVEL_FATAL,
  2908. "Tx comp release_src != TQM | FW but from %d",
  2909. buffer_src);
  2910. hal_dump_comp_desc(tx_comp_hal_desc);
  2911. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  2912. qdf_assert_always(0);
  2913. }
  2914. /* Get descriptor id */
  2915. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2916. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2917. DP_TX_DESC_ID_POOL_OS;
  2918. /* Find Tx descriptor */
  2919. tx_desc = dp_tx_desc_find(soc, pool_id,
  2920. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2921. DP_TX_DESC_ID_PAGE_OS,
  2922. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2923. DP_TX_DESC_ID_OFFSET_OS);
  2924. /*
  2925. * If the descriptor is already freed in vdev_detach,
  2926. * continue to next descriptor
  2927. */
  2928. if (!tx_desc->vdev && !tx_desc->flags) {
  2929. QDF_TRACE(QDF_MODULE_ID_DP,
  2930. QDF_TRACE_LEVEL_INFO,
  2931. "Descriptor freed in vdev_detach %d",
  2932. tx_desc_id);
  2933. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2934. count++;
  2935. continue;
  2936. }
  2937. /*
  2938. * If the release source is FW, process the HTT status
  2939. */
  2940. if (qdf_unlikely(buffer_src ==
  2941. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2942. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2943. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2944. htt_tx_status);
  2945. dp_tx_process_htt_completion(tx_desc,
  2946. htt_tx_status, ring_id);
  2947. } else {
  2948. /* Pool id is not matching. Error */
  2949. if (tx_desc->pool_id != pool_id) {
  2950. QDF_TRACE(QDF_MODULE_ID_DP,
  2951. QDF_TRACE_LEVEL_FATAL,
  2952. "Tx Comp pool id %d not matched %d",
  2953. pool_id, tx_desc->pool_id);
  2954. qdf_assert_always(0);
  2955. }
  2956. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2957. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2958. QDF_TRACE(QDF_MODULE_ID_DP,
  2959. QDF_TRACE_LEVEL_FATAL,
  2960. "Txdesc invalid, flgs = %x,id = %d",
  2961. tx_desc->flags, tx_desc_id);
  2962. qdf_assert_always(0);
  2963. }
  2964. /* First ring descriptor on the cycle */
  2965. if (!head_desc) {
  2966. head_desc = tx_desc;
  2967. tail_desc = tx_desc;
  2968. }
  2969. tail_desc->next = tx_desc;
  2970. tx_desc->next = NULL;
  2971. tail_desc = tx_desc;
  2972. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  2973. /* Collect hw completion contents */
  2974. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2975. &tx_desc->comp, 1);
  2976. }
  2977. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2978. /*
  2979. * Processed packet count is more than given quota
  2980. * stop to processing
  2981. */
  2982. if (num_processed >= quota) {
  2983. force_break = true;
  2984. break;
  2985. }
  2986. count++;
  2987. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  2988. break;
  2989. }
  2990. hal_srng_access_end(soc->hal_soc, hal_srng);
  2991. /* Process the reaped descriptors */
  2992. if (head_desc)
  2993. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  2994. if (dp_tx_comp_enable_eol_data_check(soc)) {
  2995. if (!force_break &&
  2996. hal_srng_dst_peek_sync_locked(soc, hal_srng)) {
  2997. DP_STATS_INC(soc, tx.hp_oos2, 1);
  2998. if (!hif_exec_should_yield(soc->hif_handle,
  2999. int_ctx->dp_intr_id))
  3000. goto more_data;
  3001. }
  3002. }
  3003. DP_TX_HIST_STATS_PER_PDEV();
  3004. return num_processed;
  3005. }
  3006. #ifdef FEATURE_WLAN_TDLS
  3007. /**
  3008. * dp_tx_non_std() - Allow the control-path SW to send data frames
  3009. *
  3010. * @data_vdev - which vdev should transmit the tx data frames
  3011. * @tx_spec - what non-standard handling to apply to the tx data frames
  3012. * @msdu_list - NULL-terminated list of tx MSDUs
  3013. *
  3014. * Return: NULL on success,
  3015. * nbuf when it fails to send
  3016. */
  3017. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  3018. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3019. {
  3020. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3021. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3022. vdev->is_tdls_frame = true;
  3023. return dp_tx_send(vdev_handle, msdu_list);
  3024. }
  3025. #endif
  3026. /**
  3027. * dp_tx_vdev_attach() - attach vdev to dp tx
  3028. * @vdev: virtual device instance
  3029. *
  3030. * Return: QDF_STATUS_SUCCESS: success
  3031. * QDF_STATUS_E_RESOURCES: Error return
  3032. */
  3033. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3034. {
  3035. /*
  3036. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3037. */
  3038. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3039. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3040. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3041. vdev->vdev_id);
  3042. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3043. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3044. /*
  3045. * Set HTT Extension Valid bit to 0 by default
  3046. */
  3047. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3048. dp_tx_vdev_update_search_flags(vdev);
  3049. return QDF_STATUS_SUCCESS;
  3050. }
  3051. #ifndef FEATURE_WDS
  3052. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3053. {
  3054. return false;
  3055. }
  3056. #endif
  3057. /**
  3058. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3059. * @vdev: virtual device instance
  3060. *
  3061. * Return: void
  3062. *
  3063. */
  3064. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3065. {
  3066. struct dp_soc *soc = vdev->pdev->soc;
  3067. /*
  3068. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3069. * for TDLS link
  3070. *
  3071. * Enable AddrY (SA based search) only for non-WDS STA and
  3072. * ProxySTA VAP (in HKv1) modes.
  3073. *
  3074. * In all other VAP modes, only DA based search should be
  3075. * enabled
  3076. */
  3077. if (vdev->opmode == wlan_op_mode_sta &&
  3078. vdev->tdls_link_connected)
  3079. vdev->hal_desc_addr_search_flags =
  3080. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3081. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3082. !dp_tx_da_search_override(vdev))
  3083. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3084. else
  3085. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3086. /* Set search type only when peer map v2 messaging is enabled
  3087. * as we will have the search index (AST hash) only when v2 is
  3088. * enabled
  3089. */
  3090. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3091. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3092. else
  3093. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3094. }
  3095. static inline bool
  3096. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3097. struct dp_vdev *vdev,
  3098. struct dp_tx_desc_s *tx_desc)
  3099. {
  3100. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3101. return false;
  3102. /*
  3103. * if vdev is given, then only check whether desc
  3104. * vdev match. if vdev is NULL, then check whether
  3105. * desc pdev match.
  3106. */
  3107. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3108. }
  3109. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3110. /**
  3111. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3112. *
  3113. * @soc: Handle to DP SoC structure
  3114. * @tx_desc: pointer of one TX desc
  3115. * @desc_pool_id: TX Desc pool id
  3116. */
  3117. static inline void
  3118. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3119. uint8_t desc_pool_id)
  3120. {
  3121. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3122. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3123. tx_desc->vdev = NULL;
  3124. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3125. }
  3126. /**
  3127. * dp_tx_desc_flush() - release resources associated
  3128. * to TX Desc
  3129. *
  3130. * @dp_pdev: Handle to DP pdev structure
  3131. * @vdev: virtual device instance
  3132. * NULL: no specific Vdev is required and check all allcated TX desc
  3133. * on this pdev.
  3134. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3135. *
  3136. * @force_free:
  3137. * true: flush the TX desc.
  3138. * false: only reset the Vdev in each allocated TX desc
  3139. * that associated to current Vdev.
  3140. *
  3141. * This function will go through the TX desc pool to flush
  3142. * the outstanding TX data or reset Vdev to NULL in associated TX
  3143. * Desc.
  3144. */
  3145. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3146. struct dp_vdev *vdev,
  3147. bool force_free)
  3148. {
  3149. uint8_t i;
  3150. uint32_t j;
  3151. uint32_t num_desc, page_id, offset;
  3152. uint16_t num_desc_per_page;
  3153. struct dp_soc *soc = pdev->soc;
  3154. struct dp_tx_desc_s *tx_desc = NULL;
  3155. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3156. if (!vdev && !force_free) {
  3157. dp_err("Reset TX desc vdev, Vdev param is required!");
  3158. return;
  3159. }
  3160. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3161. tx_desc_pool = &soc->tx_desc[i];
  3162. if (!(tx_desc_pool->pool_size) ||
  3163. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3164. !(tx_desc_pool->desc_pages.cacheable_pages))
  3165. continue;
  3166. num_desc = tx_desc_pool->pool_size;
  3167. num_desc_per_page =
  3168. tx_desc_pool->desc_pages.num_element_per_page;
  3169. for (j = 0; j < num_desc; j++) {
  3170. page_id = j / num_desc_per_page;
  3171. offset = j % num_desc_per_page;
  3172. if (qdf_unlikely(!(tx_desc_pool->
  3173. desc_pages.cacheable_pages)))
  3174. break;
  3175. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3176. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3177. /*
  3178. * Free TX desc if force free is
  3179. * required, otherwise only reset vdev
  3180. * in this TX desc.
  3181. */
  3182. if (force_free) {
  3183. dp_tx_comp_free_buf(soc, tx_desc);
  3184. dp_tx_desc_release(tx_desc, i);
  3185. } else {
  3186. dp_tx_desc_reset_vdev(soc, tx_desc,
  3187. i);
  3188. }
  3189. }
  3190. }
  3191. }
  3192. }
  3193. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3194. static inline void
  3195. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3196. uint8_t desc_pool_id)
  3197. {
  3198. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3199. tx_desc->vdev = NULL;
  3200. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3201. }
  3202. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3203. struct dp_vdev *vdev,
  3204. bool force_free)
  3205. {
  3206. uint8_t i, num_pool;
  3207. uint32_t j;
  3208. uint32_t num_desc, page_id, offset;
  3209. uint16_t num_desc_per_page;
  3210. struct dp_soc *soc = pdev->soc;
  3211. struct dp_tx_desc_s *tx_desc = NULL;
  3212. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3213. if (!vdev && !force_free) {
  3214. dp_err("Reset TX desc vdev, Vdev param is required!");
  3215. return;
  3216. }
  3217. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3218. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3219. for (i = 0; i < num_pool; i++) {
  3220. tx_desc_pool = &soc->tx_desc[i];
  3221. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3222. continue;
  3223. num_desc_per_page =
  3224. tx_desc_pool->desc_pages.num_element_per_page;
  3225. for (j = 0; j < num_desc; j++) {
  3226. page_id = j / num_desc_per_page;
  3227. offset = j % num_desc_per_page;
  3228. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3229. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3230. if (force_free) {
  3231. dp_tx_comp_free_buf(soc, tx_desc);
  3232. dp_tx_desc_release(tx_desc, i);
  3233. } else {
  3234. dp_tx_desc_reset_vdev(soc, tx_desc,
  3235. i);
  3236. }
  3237. }
  3238. }
  3239. }
  3240. }
  3241. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3242. /**
  3243. * dp_tx_vdev_detach() - detach vdev from dp tx
  3244. * @vdev: virtual device instance
  3245. *
  3246. * Return: QDF_STATUS_SUCCESS: success
  3247. * QDF_STATUS_E_RESOURCES: Error return
  3248. */
  3249. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3250. {
  3251. struct dp_pdev *pdev = vdev->pdev;
  3252. /* Reset TX desc associated to this Vdev as NULL */
  3253. dp_tx_desc_flush(pdev, vdev, false);
  3254. return QDF_STATUS_SUCCESS;
  3255. }
  3256. /**
  3257. * dp_tx_pdev_attach() - attach pdev to dp tx
  3258. * @pdev: physical device instance
  3259. *
  3260. * Return: QDF_STATUS_SUCCESS: success
  3261. * QDF_STATUS_E_RESOURCES: Error return
  3262. */
  3263. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3264. {
  3265. struct dp_soc *soc = pdev->soc;
  3266. /* Initialize Flow control counters */
  3267. qdf_atomic_init(&pdev->num_tx_exception);
  3268. qdf_atomic_init(&pdev->num_tx_outstanding);
  3269. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3270. /* Initialize descriptors in TCL Ring */
  3271. hal_tx_init_data_ring(soc->hal_soc,
  3272. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3273. }
  3274. return QDF_STATUS_SUCCESS;
  3275. }
  3276. /**
  3277. * dp_tx_pdev_detach() - detach pdev from dp tx
  3278. * @pdev: physical device instance
  3279. *
  3280. * Return: QDF_STATUS_SUCCESS: success
  3281. * QDF_STATUS_E_RESOURCES: Error return
  3282. */
  3283. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3284. {
  3285. /* flush TX outstanding data per pdev */
  3286. dp_tx_desc_flush(pdev, NULL, true);
  3287. dp_tx_me_exit(pdev);
  3288. return QDF_STATUS_SUCCESS;
  3289. }
  3290. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3291. /* Pools will be allocated dynamically */
  3292. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3293. int num_desc)
  3294. {
  3295. uint8_t i;
  3296. for (i = 0; i < num_pool; i++) {
  3297. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3298. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3299. }
  3300. return 0;
  3301. }
  3302. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3303. {
  3304. uint8_t i;
  3305. for (i = 0; i < num_pool; i++)
  3306. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3307. }
  3308. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3309. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3310. int num_desc)
  3311. {
  3312. uint8_t i;
  3313. /* Allocate software Tx descriptor pools */
  3314. for (i = 0; i < num_pool; i++) {
  3315. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3316. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3317. "%s Tx Desc Pool alloc %d failed %pK",
  3318. __func__, i, soc);
  3319. return ENOMEM;
  3320. }
  3321. }
  3322. return 0;
  3323. }
  3324. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3325. {
  3326. uint8_t i;
  3327. for (i = 0; i < num_pool; i++) {
  3328. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3329. if (dp_tx_desc_pool_free(soc, i)) {
  3330. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3331. "%s Tx Desc Pool Free failed", __func__);
  3332. }
  3333. }
  3334. }
  3335. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3336. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3337. /**
  3338. * dp_tso_attach_wifi3() - TSO attach handler
  3339. * @txrx_soc: Opaque Dp handle
  3340. *
  3341. * Reserve TSO descriptor buffers
  3342. *
  3343. * Return: QDF_STATUS_E_FAILURE on failure or
  3344. * QDF_STATUS_SUCCESS on success
  3345. */
  3346. static
  3347. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3348. {
  3349. return dp_tso_soc_attach(txrx_soc);
  3350. }
  3351. /**
  3352. * dp_tso_detach_wifi3() - TSO Detach handler
  3353. * @txrx_soc: Opaque Dp handle
  3354. *
  3355. * Deallocate TSO descriptor buffers
  3356. *
  3357. * Return: QDF_STATUS_E_FAILURE on failure or
  3358. * QDF_STATUS_SUCCESS on success
  3359. */
  3360. static
  3361. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3362. {
  3363. return dp_tso_soc_detach(txrx_soc);
  3364. }
  3365. #else
  3366. static
  3367. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3368. {
  3369. return QDF_STATUS_SUCCESS;
  3370. }
  3371. static
  3372. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3373. {
  3374. return QDF_STATUS_SUCCESS;
  3375. }
  3376. #endif
  3377. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3378. {
  3379. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3380. uint8_t i;
  3381. uint8_t num_pool;
  3382. uint32_t num_desc;
  3383. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3384. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3385. for (i = 0; i < num_pool; i++)
  3386. dp_tx_tso_desc_pool_free(soc, i);
  3387. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3388. __func__, num_pool, num_desc);
  3389. for (i = 0; i < num_pool; i++)
  3390. dp_tx_tso_num_seg_pool_free(soc, i);
  3391. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3392. __func__, num_pool, num_desc);
  3393. return QDF_STATUS_SUCCESS;
  3394. }
  3395. /**
  3396. * dp_tso_attach() - TSO attach handler
  3397. * @txrx_soc: Opaque Dp handle
  3398. *
  3399. * Reserve TSO descriptor buffers
  3400. *
  3401. * Return: QDF_STATUS_E_FAILURE on failure or
  3402. * QDF_STATUS_SUCCESS on success
  3403. */
  3404. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3405. {
  3406. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3407. uint8_t i;
  3408. uint8_t num_pool;
  3409. uint32_t num_desc;
  3410. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3411. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3412. for (i = 0; i < num_pool; i++) {
  3413. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3414. dp_err("TSO Desc Pool alloc %d failed %pK",
  3415. i, soc);
  3416. return QDF_STATUS_E_FAILURE;
  3417. }
  3418. }
  3419. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3420. __func__, num_pool, num_desc);
  3421. for (i = 0; i < num_pool; i++) {
  3422. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3423. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3424. i, soc);
  3425. return QDF_STATUS_E_FAILURE;
  3426. }
  3427. }
  3428. return QDF_STATUS_SUCCESS;
  3429. }
  3430. /**
  3431. * dp_tx_soc_detach() - detach soc from dp tx
  3432. * @soc: core txrx main context
  3433. *
  3434. * This function will detach dp tx into main device context
  3435. * will free dp tx resource and initialize resources
  3436. *
  3437. * Return: QDF_STATUS_SUCCESS: success
  3438. * QDF_STATUS_E_RESOURCES: Error return
  3439. */
  3440. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3441. {
  3442. uint8_t num_pool;
  3443. uint16_t num_desc;
  3444. uint16_t num_ext_desc;
  3445. uint8_t i;
  3446. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3447. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3448. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3449. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3450. dp_tx_flow_control_deinit(soc);
  3451. dp_tx_delete_static_pools(soc, num_pool);
  3452. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3453. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3454. __func__, num_pool, num_desc);
  3455. for (i = 0; i < num_pool; i++) {
  3456. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3457. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3458. "%s Tx Ext Desc Pool Free failed",
  3459. __func__);
  3460. return QDF_STATUS_E_RESOURCES;
  3461. }
  3462. }
  3463. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3464. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3465. __func__, num_pool, num_ext_desc);
  3466. status = dp_tso_detach_wifi3(soc);
  3467. if (status != QDF_STATUS_SUCCESS)
  3468. return status;
  3469. return QDF_STATUS_SUCCESS;
  3470. }
  3471. /**
  3472. * dp_tx_soc_attach() - attach soc to dp tx
  3473. * @soc: core txrx main context
  3474. *
  3475. * This function will attach dp tx into main device context
  3476. * will allocate dp tx resource and initialize resources
  3477. *
  3478. * Return: QDF_STATUS_SUCCESS: success
  3479. * QDF_STATUS_E_RESOURCES: Error return
  3480. */
  3481. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3482. {
  3483. uint8_t i;
  3484. uint8_t num_pool;
  3485. uint32_t num_desc;
  3486. uint32_t num_ext_desc;
  3487. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3488. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3489. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3490. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3491. if (num_pool > MAX_TXDESC_POOLS)
  3492. goto fail;
  3493. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3494. goto fail;
  3495. dp_tx_flow_control_init(soc);
  3496. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3497. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3498. __func__, num_pool, num_desc);
  3499. /* Allocate extension tx descriptor pools */
  3500. for (i = 0; i < num_pool; i++) {
  3501. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3502. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3503. "MSDU Ext Desc Pool alloc %d failed %pK",
  3504. i, soc);
  3505. goto fail;
  3506. }
  3507. }
  3508. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3509. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3510. __func__, num_pool, num_ext_desc);
  3511. status = dp_tso_attach_wifi3((void *)soc);
  3512. if (status != QDF_STATUS_SUCCESS)
  3513. goto fail;
  3514. /* Initialize descriptors in TCL Rings */
  3515. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3516. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3517. hal_tx_init_data_ring(soc->hal_soc,
  3518. soc->tcl_data_ring[i].hal_srng);
  3519. }
  3520. }
  3521. /*
  3522. * todo - Add a runtime config option to enable this.
  3523. */
  3524. /*
  3525. * Due to multiple issues on NPR EMU, enable it selectively
  3526. * only for NPR EMU, should be removed, once NPR platforms
  3527. * are stable.
  3528. */
  3529. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3530. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3531. "%s HAL Tx init Success", __func__);
  3532. return QDF_STATUS_SUCCESS;
  3533. fail:
  3534. /* Detach will take care of freeing only allocated resources */
  3535. dp_tx_soc_detach(soc);
  3536. return QDF_STATUS_E_RESOURCES;
  3537. }
  3538. /*
  3539. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3540. * pdev: pointer to DP PDEV structure
  3541. * seg_info_head: Pointer to the head of list
  3542. *
  3543. * return: void
  3544. */
  3545. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3546. struct dp_tx_seg_info_s *seg_info_head)
  3547. {
  3548. struct dp_tx_me_buf_t *mc_uc_buf;
  3549. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3550. qdf_nbuf_t nbuf = NULL;
  3551. uint64_t phy_addr;
  3552. while (seg_info_head) {
  3553. nbuf = seg_info_head->nbuf;
  3554. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3555. seg_info_head->frags[0].vaddr;
  3556. phy_addr = seg_info_head->frags[0].paddr_hi;
  3557. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3558. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3559. phy_addr,
  3560. QDF_DMA_TO_DEVICE , QDF_MAC_ADDR_SIZE);
  3561. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3562. qdf_nbuf_free(nbuf);
  3563. seg_info_new = seg_info_head;
  3564. seg_info_head = seg_info_head->next;
  3565. qdf_mem_free(seg_info_new);
  3566. }
  3567. }
  3568. /**
  3569. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3570. * @vdev: DP VDEV handle
  3571. * @nbuf: Multicast nbuf
  3572. * @newmac: Table of the clients to which packets have to be sent
  3573. * @new_mac_cnt: No of clients
  3574. *
  3575. * return: no of converted packets
  3576. */
  3577. uint16_t
  3578. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3579. uint8_t newmac[][QDF_MAC_ADDR_SIZE], uint8_t new_mac_cnt)
  3580. {
  3581. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3582. struct dp_pdev *pdev = vdev->pdev;
  3583. qdf_ether_header_t *eh;
  3584. uint8_t *data;
  3585. uint16_t len;
  3586. /* reference to frame dst addr */
  3587. uint8_t *dstmac;
  3588. /* copy of original frame src addr */
  3589. uint8_t srcmac[QDF_MAC_ADDR_SIZE];
  3590. /* local index into newmac */
  3591. uint8_t new_mac_idx = 0;
  3592. struct dp_tx_me_buf_t *mc_uc_buf;
  3593. qdf_nbuf_t nbuf_clone;
  3594. struct dp_tx_msdu_info_s msdu_info;
  3595. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3596. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3597. struct dp_tx_seg_info_s *seg_info_new;
  3598. qdf_dma_addr_t paddr_data;
  3599. qdf_dma_addr_t paddr_mcbuf = 0;
  3600. uint8_t empty_entry_mac[QDF_MAC_ADDR_SIZE] = {0};
  3601. QDF_STATUS status;
  3602. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3603. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3604. eh = (qdf_ether_header_t *)nbuf;
  3605. qdf_mem_copy(srcmac, eh->ether_shost, QDF_MAC_ADDR_SIZE);
  3606. len = qdf_nbuf_len(nbuf);
  3607. data = qdf_nbuf_data(nbuf);
  3608. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3609. QDF_DMA_TO_DEVICE);
  3610. if (status) {
  3611. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3612. "Mapping failure Error:%d", status);
  3613. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3614. qdf_nbuf_free(nbuf);
  3615. return 1;
  3616. }
  3617. paddr_data = qdf_nbuf_mapped_paddr_get(nbuf) + QDF_MAC_ADDR_SIZE;
  3618. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3619. dstmac = newmac[new_mac_idx];
  3620. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3621. "added mac addr (%pM)", dstmac);
  3622. /* Check for NULL Mac Address */
  3623. if (!qdf_mem_cmp(dstmac, empty_entry_mac, QDF_MAC_ADDR_SIZE))
  3624. continue;
  3625. /* frame to self mac. skip */
  3626. if (!qdf_mem_cmp(dstmac, srcmac, QDF_MAC_ADDR_SIZE))
  3627. continue;
  3628. /*
  3629. * TODO: optimize to avoid malloc in per-packet path
  3630. * For eg. seg_pool can be made part of vdev structure
  3631. */
  3632. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3633. if (!seg_info_new) {
  3634. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3635. "alloc failed");
  3636. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3637. goto fail_seg_alloc;
  3638. }
  3639. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3640. if (!mc_uc_buf)
  3641. goto fail_buf_alloc;
  3642. /*
  3643. * TODO: Check if we need to clone the nbuf
  3644. * Or can we just use the reference for all cases
  3645. */
  3646. if (new_mac_idx < (new_mac_cnt - 1)) {
  3647. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3648. if (!nbuf_clone) {
  3649. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3650. goto fail_clone;
  3651. }
  3652. } else {
  3653. /*
  3654. * Update the ref
  3655. * to account for frame sent without cloning
  3656. */
  3657. qdf_nbuf_ref(nbuf);
  3658. nbuf_clone = nbuf;
  3659. }
  3660. qdf_mem_copy(mc_uc_buf->data, dstmac, QDF_MAC_ADDR_SIZE);
  3661. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3662. QDF_DMA_TO_DEVICE, QDF_MAC_ADDR_SIZE,
  3663. &paddr_mcbuf);
  3664. if (status) {
  3665. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3666. "Mapping failure Error:%d", status);
  3667. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3668. goto fail_map;
  3669. }
  3670. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3671. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3672. seg_info_new->frags[0].paddr_hi =
  3673. (uint16_t)((uint64_t)paddr_mcbuf >> 32);
  3674. seg_info_new->frags[0].len = QDF_MAC_ADDR_SIZE;
  3675. /*preparing data fragment*/
  3676. seg_info_new->frags[1].vaddr =
  3677. qdf_nbuf_data(nbuf) + QDF_MAC_ADDR_SIZE;
  3678. seg_info_new->frags[1].paddr_lo = (uint32_t)paddr_data;
  3679. seg_info_new->frags[1].paddr_hi =
  3680. (uint16_t)(((uint64_t)paddr_data) >> 32);
  3681. seg_info_new->frags[1].len = len - QDF_MAC_ADDR_SIZE;
  3682. seg_info_new->nbuf = nbuf_clone;
  3683. seg_info_new->frag_cnt = 2;
  3684. seg_info_new->total_len = len;
  3685. seg_info_new->next = NULL;
  3686. if (!seg_info_head)
  3687. seg_info_head = seg_info_new;
  3688. else
  3689. seg_info_tail->next = seg_info_new;
  3690. seg_info_tail = seg_info_new;
  3691. }
  3692. if (!seg_info_head) {
  3693. goto free_return;
  3694. }
  3695. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3696. msdu_info.num_seg = new_mac_cnt;
  3697. msdu_info.frm_type = dp_tx_frm_me;
  3698. msdu_info.tid = HTT_INVALID_TID;
  3699. if (qdf_unlikely(vdev->mcast_enhancement_en > 0) &&
  3700. qdf_unlikely(pdev->hmmc_tid_override_en))
  3701. msdu_info.tid = pdev->hmmc_tid;
  3702. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3703. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3704. while (seg_info_head->next) {
  3705. seg_info_new = seg_info_head;
  3706. seg_info_head = seg_info_head->next;
  3707. qdf_mem_free(seg_info_new);
  3708. }
  3709. qdf_mem_free(seg_info_head);
  3710. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3711. qdf_nbuf_free(nbuf);
  3712. return new_mac_cnt;
  3713. fail_map:
  3714. qdf_nbuf_free(nbuf_clone);
  3715. fail_clone:
  3716. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3717. fail_buf_alloc:
  3718. qdf_mem_free(seg_info_new);
  3719. fail_seg_alloc:
  3720. dp_tx_me_mem_free(pdev, seg_info_head);
  3721. free_return:
  3722. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3723. qdf_nbuf_free(nbuf);
  3724. return 1;
  3725. }