cam_mem_mgr.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/types.h>
  7. #include <linux/mutex.h>
  8. #include <linux/slab.h>
  9. #include <linux/dma-buf.h>
  10. #include <linux/version.h>
  11. #include <linux/debugfs.h>
  12. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  13. #include <linux/mem-buf.h>
  14. #include <soc/qcom/secure_buffer.h>
  15. #endif
  16. #include "cam_compat.h"
  17. #include "cam_req_mgr_util.h"
  18. #include "cam_mem_mgr.h"
  19. #include "cam_smmu_api.h"
  20. #include "cam_debug_util.h"
  21. #include "cam_trace.h"
  22. #include "cam_common_util.h"
  23. #define CAM_MEM_SHARED_BUFFER_PAD_4K (4 * 1024)
  24. static struct cam_mem_table tbl;
  25. static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED);
  26. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  27. static void cam_mem_mgr_put_dma_heaps(void);
  28. static int cam_mem_mgr_get_dma_heaps(void);
  29. #endif
  30. static unsigned long cam_mem_mgr_mini_dump_cb(void *dst, unsigned long len)
  31. {
  32. struct cam_mem_table_mini_dump *md;
  33. if (!dst) {
  34. CAM_ERR(CAM_MEM, "Invalid params");
  35. return 0;
  36. }
  37. if (len < sizeof(*md)) {
  38. CAM_ERR(CAM_MEM, "Insufficient length %u", len);
  39. return 0;
  40. }
  41. md = (struct cam_mem_table_mini_dump *)dst;
  42. memcpy(md->bufq, tbl.bufq, CAM_MEM_BUFQ_MAX * sizeof(struct cam_mem_buf_queue));
  43. md->dbg_buf_idx = tbl.dbg_buf_idx;
  44. md->alloc_profile_enable = tbl.alloc_profile_enable;
  45. md->force_cache_allocs = tbl.force_cache_allocs;
  46. md->need_shared_buffer_padding = tbl.need_shared_buffer_padding;
  47. return sizeof(*md);
  48. }
  49. static void cam_mem_mgr_print_tbl(void)
  50. {
  51. int i;
  52. uint64_t ms, hrs, min, sec;
  53. struct timespec64 current_ts;
  54. CAM_GET_TIMESTAMP(current_ts);
  55. CAM_CONVERT_TIMESTAMP_FORMAT(current_ts, hrs, min, sec, ms);
  56. CAM_INFO(CAM_MEM, "***%llu:%llu:%llu:%llu Mem mgr table dump***",
  57. hrs, min, sec, ms);
  58. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  59. if (tbl.bufq[i].active) {
  60. CAM_CONVERT_TIMESTAMP_FORMAT((tbl.bufq[i].timestamp), hrs, min, sec, ms);
  61. CAM_INFO(CAM_MEM,
  62. "%llu:%llu:%llu:%llu idx %d fd %d i_ino %lu size %llu",
  63. hrs, min, sec, ms, i, tbl.bufq[i].fd, tbl.bufq[i].i_ino,
  64. tbl.bufq[i].len);
  65. }
  66. }
  67. }
  68. static int cam_mem_util_get_dma_dir(uint32_t flags)
  69. {
  70. int rc = -EINVAL;
  71. if (flags & CAM_MEM_FLAG_HW_READ_ONLY)
  72. rc = DMA_TO_DEVICE;
  73. else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY)
  74. rc = DMA_FROM_DEVICE;
  75. else if (flags & CAM_MEM_FLAG_HW_READ_WRITE)
  76. rc = DMA_BIDIRECTIONAL;
  77. else if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  78. rc = DMA_BIDIRECTIONAL;
  79. return rc;
  80. }
  81. static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
  82. uintptr_t *vaddr,
  83. size_t *len)
  84. {
  85. int rc = 0;
  86. void *addr;
  87. /*
  88. * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access()
  89. * need to be called in pair to avoid stability issue.
  90. */
  91. rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  92. if (rc) {
  93. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  94. return rc;
  95. }
  96. addr = dma_buf_vmap(dmabuf);
  97. if (!addr) {
  98. CAM_ERR(CAM_MEM, "kernel map fail");
  99. *vaddr = 0;
  100. *len = 0;
  101. rc = -ENOSPC;
  102. goto fail;
  103. }
  104. *vaddr = (uint64_t)addr;
  105. *len = dmabuf->size;
  106. return 0;
  107. fail:
  108. dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  109. return rc;
  110. }
  111. static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf,
  112. uint64_t vaddr)
  113. {
  114. int rc = 0;
  115. if (!dmabuf || !vaddr) {
  116. CAM_ERR(CAM_MEM, "Invalid input args %pK %llX", dmabuf, vaddr);
  117. return -EINVAL;
  118. }
  119. dma_buf_vunmap(dmabuf, (void *)vaddr);
  120. /*
  121. * dma_buf_begin_cpu_access() and
  122. * dma_buf_end_cpu_access() need to be called in pair
  123. * to avoid stability issue.
  124. */
  125. rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  126. if (rc) {
  127. CAM_ERR(CAM_MEM, "Failed in end cpu access, dmabuf=%pK",
  128. dmabuf);
  129. return rc;
  130. }
  131. return rc;
  132. }
  133. static int cam_mem_mgr_create_debug_fs(void)
  134. {
  135. int rc = 0;
  136. struct dentry *dbgfileptr = NULL;
  137. dbgfileptr = debugfs_create_dir("camera_memmgr", NULL);
  138. if (!dbgfileptr) {
  139. CAM_ERR(CAM_MEM,"DebugFS could not create directory!");
  140. rc = -ENOENT;
  141. goto end;
  142. }
  143. /* Store parent inode for cleanup in caller */
  144. tbl.dentry = dbgfileptr;
  145. dbgfileptr = debugfs_create_bool("alloc_profile_enable", 0644,
  146. tbl.dentry, &tbl.alloc_profile_enable);
  147. if (IS_ERR(dbgfileptr)) {
  148. if (PTR_ERR(dbgfileptr) == -ENODEV)
  149. CAM_WARN(CAM_MEM, "DebugFS not enabled in kernel!");
  150. else
  151. rc = PTR_ERR(dbgfileptr);
  152. }
  153. end:
  154. return rc;
  155. }
  156. int cam_mem_mgr_init(void)
  157. {
  158. int i;
  159. int bitmap_size;
  160. int rc = 0;
  161. memset(tbl.bufq, 0, sizeof(tbl.bufq));
  162. if (cam_smmu_need_force_alloc_cached(&tbl.force_cache_allocs)) {
  163. CAM_ERR(CAM_MEM, "Error in getting force cache alloc flag");
  164. return -EINVAL;
  165. }
  166. tbl.need_shared_buffer_padding = cam_smmu_need_shared_buffer_padding();
  167. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  168. rc = cam_mem_mgr_get_dma_heaps();
  169. if (rc) {
  170. CAM_ERR(CAM_MEM, "Failed in getting dma heaps rc=%d", rc);
  171. return rc;
  172. }
  173. #endif
  174. bitmap_size = BITS_TO_LONGS(CAM_MEM_BUFQ_MAX) * sizeof(long);
  175. tbl.bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  176. if (!tbl.bitmap) {
  177. rc = -ENOMEM;
  178. goto put_heaps;
  179. }
  180. tbl.bits = bitmap_size * BITS_PER_BYTE;
  181. bitmap_zero(tbl.bitmap, tbl.bits);
  182. /* We need to reserve slot 0 because 0 is invalid */
  183. set_bit(0, tbl.bitmap);
  184. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  185. tbl.bufq[i].fd = -1;
  186. tbl.bufq[i].buf_handle = -1;
  187. }
  188. mutex_init(&tbl.m_lock);
  189. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED);
  190. cam_mem_mgr_create_debug_fs();
  191. cam_common_register_mini_dump_cb(cam_mem_mgr_mini_dump_cb,
  192. "cam_mem");
  193. return 0;
  194. put_heaps:
  195. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  196. cam_mem_mgr_put_dma_heaps();
  197. #endif
  198. return rc;
  199. }
  200. static int32_t cam_mem_get_slot(void)
  201. {
  202. int32_t idx;
  203. mutex_lock(&tbl.m_lock);
  204. idx = find_first_zero_bit(tbl.bitmap, tbl.bits);
  205. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  206. mutex_unlock(&tbl.m_lock);
  207. return -ENOMEM;
  208. }
  209. set_bit(idx, tbl.bitmap);
  210. tbl.bufq[idx].active = true;
  211. CAM_GET_TIMESTAMP((tbl.bufq[idx].timestamp));
  212. mutex_init(&tbl.bufq[idx].q_lock);
  213. mutex_unlock(&tbl.m_lock);
  214. return idx;
  215. }
  216. static void cam_mem_put_slot(int32_t idx)
  217. {
  218. mutex_lock(&tbl.m_lock);
  219. mutex_lock(&tbl.bufq[idx].q_lock);
  220. tbl.bufq[idx].active = false;
  221. tbl.bufq[idx].is_internal = false;
  222. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  223. mutex_unlock(&tbl.bufq[idx].q_lock);
  224. mutex_destroy(&tbl.bufq[idx].q_lock);
  225. clear_bit(idx, tbl.bitmap);
  226. mutex_unlock(&tbl.m_lock);
  227. }
  228. int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle,
  229. dma_addr_t *iova_ptr, size_t *len_ptr, uint32_t *flags)
  230. {
  231. int rc = 0, idx;
  232. *len_ptr = 0;
  233. if (!atomic_read(&cam_mem_mgr_state)) {
  234. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  235. return -EINVAL;
  236. }
  237. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  238. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  239. return -ENOENT;
  240. if (!tbl.bufq[idx].active) {
  241. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  242. idx);
  243. return -EAGAIN;
  244. }
  245. mutex_lock(&tbl.bufq[idx].q_lock);
  246. if (buf_handle != tbl.bufq[idx].buf_handle) {
  247. rc = -EINVAL;
  248. goto handle_mismatch;
  249. }
  250. if (CAM_MEM_MGR_IS_SECURE_HDL(buf_handle))
  251. rc = cam_smmu_get_stage2_iova(mmu_handle, tbl.bufq[idx].fd, tbl.bufq[idx].dma_buf,
  252. iova_ptr, len_ptr);
  253. else
  254. rc = cam_smmu_get_iova(mmu_handle, tbl.bufq[idx].fd, tbl.bufq[idx].dma_buf,
  255. iova_ptr, len_ptr);
  256. if (rc) {
  257. CAM_ERR(CAM_MEM,
  258. "fail to map buf_hdl:0x%x, mmu_hdl: 0x%x for fd:%d i_ino:%lu",
  259. buf_handle, mmu_handle, tbl.bufq[idx].fd, tbl.bufq[idx].i_ino);
  260. goto handle_mismatch;
  261. }
  262. if (flags)
  263. *flags = tbl.bufq[idx].flags;
  264. CAM_DBG(CAM_MEM,
  265. "handle:0x%x fd:%d i_ino:%lu iova_ptr:0x%llx len_ptr:%llu",
  266. mmu_handle, tbl.bufq[idx].fd, tbl.bufq[idx].i_ino, iova_ptr, *len_ptr);
  267. handle_mismatch:
  268. mutex_unlock(&tbl.bufq[idx].q_lock);
  269. return rc;
  270. }
  271. EXPORT_SYMBOL(cam_mem_get_io_buf);
  272. int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len)
  273. {
  274. int idx;
  275. if (!atomic_read(&cam_mem_mgr_state)) {
  276. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  277. return -EINVAL;
  278. }
  279. if (!buf_handle || !vaddr_ptr || !len)
  280. return -EINVAL;
  281. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  282. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  283. return -EINVAL;
  284. if (!tbl.bufq[idx].active) {
  285. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  286. idx);
  287. return -EPERM;
  288. }
  289. if (buf_handle != tbl.bufq[idx].buf_handle)
  290. return -EINVAL;
  291. if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS))
  292. return -EINVAL;
  293. if (tbl.bufq[idx].kmdvaddr) {
  294. *vaddr_ptr = tbl.bufq[idx].kmdvaddr;
  295. *len = tbl.bufq[idx].len;
  296. } else {
  297. CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle",
  298. buf_handle);
  299. return -EINVAL;
  300. }
  301. return 0;
  302. }
  303. EXPORT_SYMBOL(cam_mem_get_cpu_buf);
  304. int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd)
  305. {
  306. int rc = 0, idx;
  307. uint32_t cache_dir;
  308. unsigned long dmabuf_flag = 0;
  309. if (!atomic_read(&cam_mem_mgr_state)) {
  310. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  311. return -EINVAL;
  312. }
  313. if (!cmd)
  314. return -EINVAL;
  315. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  316. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  317. return -EINVAL;
  318. mutex_lock(&tbl.bufq[idx].q_lock);
  319. if (!tbl.bufq[idx].active) {
  320. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  321. idx);
  322. rc = -EINVAL;
  323. goto end;
  324. }
  325. if (cmd->buf_handle != tbl.bufq[idx].buf_handle) {
  326. rc = -EINVAL;
  327. goto end;
  328. }
  329. rc = dma_buf_get_flags(tbl.bufq[idx].dma_buf, &dmabuf_flag);
  330. if (rc) {
  331. CAM_ERR(CAM_MEM, "cache get flags failed %d", rc);
  332. goto end;
  333. }
  334. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  335. CAM_DBG(CAM_MEM, "Calling dmap buf APIs for cache operations");
  336. cache_dir = DMA_BIDIRECTIONAL;
  337. #else
  338. if (dmabuf_flag & ION_FLAG_CACHED) {
  339. switch (cmd->mem_cache_ops) {
  340. case CAM_MEM_CLEAN_CACHE:
  341. cache_dir = DMA_TO_DEVICE;
  342. break;
  343. case CAM_MEM_INV_CACHE:
  344. cache_dir = DMA_FROM_DEVICE;
  345. break;
  346. case CAM_MEM_CLEAN_INV_CACHE:
  347. cache_dir = DMA_BIDIRECTIONAL;
  348. break;
  349. default:
  350. CAM_ERR(CAM_MEM,
  351. "invalid cache ops :%d", cmd->mem_cache_ops);
  352. rc = -EINVAL;
  353. goto end;
  354. }
  355. } else {
  356. CAM_DBG(CAM_MEM, "BUF is not cached");
  357. goto end;
  358. }
  359. #endif
  360. rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf,
  361. (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ?
  362. DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
  363. if (rc) {
  364. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  365. goto end;
  366. }
  367. rc = dma_buf_end_cpu_access(tbl.bufq[idx].dma_buf,
  368. cache_dir);
  369. if (rc) {
  370. CAM_ERR(CAM_MEM, "dma end access failed rc=%d", rc);
  371. goto end;
  372. }
  373. end:
  374. mutex_unlock(&tbl.bufq[idx].q_lock);
  375. return rc;
  376. }
  377. EXPORT_SYMBOL(cam_mem_mgr_cache_ops);
  378. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  379. #define CAM_MAX_VMIDS 4
  380. static void cam_mem_mgr_put_dma_heaps(void)
  381. {
  382. CAM_DBG(CAM_MEM, "Releasing DMA Buf heaps usage");
  383. }
  384. static int cam_mem_mgr_get_dma_heaps(void)
  385. {
  386. int rc = 0;
  387. tbl.system_heap = NULL;
  388. tbl.system_uncached_heap = NULL;
  389. tbl.camera_heap = NULL;
  390. tbl.camera_uncached_heap = NULL;
  391. tbl.secure_display_heap = NULL;
  392. tbl.system_heap = dma_heap_find("qcom,system");
  393. if (IS_ERR_OR_NULL(tbl.system_heap)) {
  394. rc = PTR_ERR(tbl.system_heap);
  395. CAM_ERR(CAM_MEM, "qcom system heap not found, rc=%d", rc);
  396. tbl.system_heap = NULL;
  397. goto put_heaps;
  398. }
  399. tbl.system_uncached_heap = dma_heap_find("qcom,system-uncached");
  400. if (IS_ERR_OR_NULL(tbl.system_uncached_heap)) {
  401. if (tbl.force_cache_allocs) {
  402. /* optional, we anyway do not use uncached */
  403. CAM_DBG(CAM_MEM,
  404. "qcom system-uncached heap not found, err=%d",
  405. PTR_ERR(tbl.system_uncached_heap));
  406. tbl.system_uncached_heap = NULL;
  407. } else {
  408. /* fatal, must need uncached heaps */
  409. rc = PTR_ERR(tbl.system_uncached_heap);
  410. CAM_ERR(CAM_MEM,
  411. "qcom system-uncached heap not found, rc=%d",
  412. rc);
  413. tbl.system_uncached_heap = NULL;
  414. goto put_heaps;
  415. }
  416. }
  417. tbl.secure_display_heap = dma_heap_find("qcom,display");
  418. if (IS_ERR_OR_NULL(tbl.secure_display_heap)) {
  419. rc = PTR_ERR(tbl.secure_display_heap);
  420. CAM_ERR(CAM_MEM, "qcom,display heap not found, rc=%d",
  421. rc);
  422. tbl.secure_display_heap = NULL;
  423. goto put_heaps;
  424. }
  425. tbl.camera_heap = dma_heap_find("qcom,camera");
  426. if (IS_ERR_OR_NULL(tbl.camera_heap)) {
  427. /* optional heap, not a fatal error */
  428. CAM_DBG(CAM_MEM, "qcom camera heap not found, err=%d",
  429. PTR_ERR(tbl.camera_heap));
  430. tbl.camera_heap = NULL;
  431. }
  432. tbl.camera_uncached_heap = dma_heap_find("qcom,camera-uncached");
  433. if (IS_ERR_OR_NULL(tbl.camera_uncached_heap)) {
  434. /* optional heap, not a fatal error */
  435. CAM_DBG(CAM_MEM, "qcom camera heap not found, err=%d",
  436. PTR_ERR(tbl.camera_uncached_heap));
  437. tbl.camera_uncached_heap = NULL;
  438. }
  439. CAM_INFO(CAM_MEM,
  440. "Heaps : system=%pK, system_uncached=%pK, camera=%pK, camera-uncached=%pK, secure_display=%pK",
  441. tbl.system_heap, tbl.system_uncached_heap,
  442. tbl.camera_heap, tbl.camera_uncached_heap,
  443. tbl.secure_display_heap);
  444. return 0;
  445. put_heaps:
  446. cam_mem_mgr_put_dma_heaps();
  447. return rc;
  448. }
  449. static int cam_mem_util_get_dma_buf(size_t len,
  450. unsigned int cam_flags,
  451. struct dma_buf **buf,
  452. unsigned long *i_ino)
  453. {
  454. int rc = 0;
  455. struct dma_heap *heap;
  456. struct dma_heap *try_heap = NULL;
  457. struct timespec64 ts1, ts2;
  458. long microsec = 0;
  459. bool use_cached_heap = false;
  460. struct mem_buf_lend_kernel_arg arg;
  461. int vmids[CAM_MAX_VMIDS];
  462. int perms[CAM_MAX_VMIDS];
  463. int num_vmids = 0;
  464. if (!buf) {
  465. CAM_ERR(CAM_MEM, "Invalid params");
  466. return -EINVAL;
  467. }
  468. if (tbl.alloc_profile_enable)
  469. CAM_GET_TIMESTAMP(ts1);
  470. if ((cam_flags & CAM_MEM_FLAG_CACHE) ||
  471. (tbl.force_cache_allocs &&
  472. (!(cam_flags & CAM_MEM_FLAG_PROTECTED_MODE)))) {
  473. CAM_DBG(CAM_MEM,
  474. "Using CACHED heap, cam_flags=0x%x, force_cache_allocs=%d",
  475. cam_flags, tbl.force_cache_allocs);
  476. use_cached_heap = true;
  477. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  478. use_cached_heap = true;
  479. CAM_DBG(CAM_MEM,
  480. "Using CACHED heap for secure, cam_flags=0x%x, force_cache_allocs=%d",
  481. cam_flags, tbl.force_cache_allocs);
  482. } else {
  483. use_cached_heap = false;
  484. CAM_ERR(CAM_MEM,
  485. "Using UNCACHED heap not supported, cam_flags=0x%x, force_cache_allocs=%d",
  486. cam_flags, tbl.force_cache_allocs);
  487. /*
  488. * Need a better handling based on whether dma-buf-heaps support
  489. * uncached heaps or not. For now, assume not supported.
  490. */
  491. return -EINVAL;
  492. }
  493. if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  494. heap = tbl.secure_display_heap;
  495. vmids[num_vmids] = VMID_CP_CAMERA;
  496. perms[num_vmids] = PERM_READ | PERM_WRITE;
  497. num_vmids++;
  498. if (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT) {
  499. CAM_DBG(CAM_MEM, "Secure mode CDSP flags");
  500. vmids[num_vmids] = VMID_CP_CDSP;
  501. perms[num_vmids] = PERM_READ | PERM_WRITE;
  502. num_vmids++;
  503. }
  504. } else if (cam_flags & CAM_MEM_FLAG_EVA_NOPIXEL) {
  505. heap = tbl.secure_display_heap;
  506. vmids[num_vmids] = VMID_CP_NON_PIXEL;
  507. perms[num_vmids] = PERM_READ | PERM_WRITE;
  508. num_vmids++;
  509. } else if (use_cached_heap) {
  510. try_heap = tbl.camera_heap;
  511. heap = tbl.system_heap;
  512. } else {
  513. try_heap = tbl.camera_uncached_heap;
  514. heap = tbl.system_uncached_heap;
  515. }
  516. CAM_DBG(CAM_MEM, "Using heaps : try=%pK, heap=%pK", try_heap, heap);
  517. *buf = NULL;
  518. if (!try_heap && !heap) {
  519. CAM_ERR(CAM_MEM,
  520. "No heap available for allocation, cant allocate");
  521. return -EINVAL;
  522. }
  523. if (try_heap) {
  524. *buf = dma_heap_buffer_alloc(try_heap, len, O_RDWR, 0);
  525. if (IS_ERR(*buf)) {
  526. CAM_WARN(CAM_MEM,
  527. "Failed in allocating from try heap, heap=%pK, len=%zu, err=%d",
  528. try_heap, len, PTR_ERR(*buf));
  529. *buf = NULL;
  530. }
  531. }
  532. if (*buf == NULL) {
  533. *buf = dma_heap_buffer_alloc(heap, len, O_RDWR, 0);
  534. if (IS_ERR(*buf)) {
  535. rc = PTR_ERR(*buf);
  536. CAM_ERR(CAM_MEM,
  537. "Failed in allocating from heap, heap=%pK, len=%zu, err=%d",
  538. heap, len, rc);
  539. *buf = NULL;
  540. return rc;
  541. }
  542. }
  543. *i_ino = file_inode((*buf)->file)->i_ino;
  544. if ((cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) ||
  545. (cam_flags & CAM_MEM_FLAG_EVA_NOPIXEL)) {
  546. if (num_vmids >= CAM_MAX_VMIDS) {
  547. CAM_ERR(CAM_MEM, "Insufficient array size for vmids %d", num_vmids);
  548. rc = -EINVAL;
  549. goto end;
  550. }
  551. arg.nr_acl_entries = num_vmids;
  552. arg.vmids = vmids;
  553. arg.perms = perms;
  554. rc = mem_buf_lend(*buf, &arg);
  555. if (rc) {
  556. CAM_ERR(CAM_MEM,
  557. "Failed in buf lend rc=%d, buf=%pK, vmids [0]=0x%x, [1]=0x%x, [2]=0x%x",
  558. rc, *buf, vmids[0], vmids[1], vmids[2]);
  559. goto end;
  560. }
  561. }
  562. CAM_DBG(CAM_MEM, "Allocate success, len=%zu, *buf=%pK, i_ino=%lu", len, *buf, *i_ino);
  563. if (tbl.alloc_profile_enable) {
  564. CAM_GET_TIMESTAMP(ts2);
  565. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  566. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  567. len, microsec);
  568. }
  569. return rc;
  570. end:
  571. dma_buf_put(*buf);
  572. return rc;
  573. }
  574. #else
  575. static int cam_mem_util_get_dma_buf(size_t len,
  576. unsigned int cam_flags,
  577. struct dma_buf **buf,
  578. unsigned long *i_ino)
  579. {
  580. int rc = 0;
  581. unsigned int heap_id;
  582. int32_t ion_flag = 0;
  583. struct timespec64 ts1, ts2;
  584. long microsec = 0;
  585. if (!buf) {
  586. CAM_ERR(CAM_MEM, "Invalid params");
  587. return -EINVAL;
  588. }
  589. if (tbl.alloc_profile_enable)
  590. CAM_GET_TIMESTAMP(ts1);
  591. if ((cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) &&
  592. (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT)) {
  593. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  594. ion_flag |=
  595. ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP;
  596. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  597. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  598. ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA;
  599. } else {
  600. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  601. ION_HEAP(ION_CAMERA_HEAP_ID);
  602. }
  603. if (cam_flags & CAM_MEM_FLAG_CACHE)
  604. ion_flag |= ION_FLAG_CACHED;
  605. else
  606. ion_flag &= ~ION_FLAG_CACHED;
  607. if (tbl.force_cache_allocs && (!(ion_flag & ION_FLAG_SECURE)))
  608. ion_flag |= ION_FLAG_CACHED;
  609. *buf = ion_alloc(len, heap_id, ion_flag);
  610. if (IS_ERR_OR_NULL(*buf))
  611. return -ENOMEM;
  612. *i_ino = file_inode((*buf)->file)->i_ino;
  613. if (tbl.alloc_profile_enable) {
  614. CAM_GET_TIMESTAMP(ts2);
  615. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  616. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  617. len, microsec);
  618. }
  619. return rc;
  620. }
  621. #endif
  622. static int cam_mem_util_buffer_alloc(size_t len, uint32_t flags,
  623. struct dma_buf **dmabuf,
  624. int *fd,
  625. unsigned long *i_ino)
  626. {
  627. int rc;
  628. struct dma_buf *temp_dmabuf = NULL;
  629. rc = cam_mem_util_get_dma_buf(len, flags, dmabuf, i_ino);
  630. if (rc) {
  631. CAM_ERR(CAM_MEM,
  632. "Error allocating dma buf : len=%llu, flags=0x%x",
  633. len, flags);
  634. return rc;
  635. }
  636. *fd = dma_buf_fd(*dmabuf, O_CLOEXEC);
  637. if (*fd < 0) {
  638. CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd);
  639. rc = -EINVAL;
  640. goto put_buf;
  641. }
  642. CAM_DBG(CAM_MEM, "Alloc success : len=%zu, *dmabuf=%pK, fd=%d, i_ino=%lu",
  643. len, *dmabuf, *fd, *i_ino);
  644. /*
  645. * increment the ref count so that ref count becomes 2 here
  646. * when we close fd, refcount becomes 1 and when we do
  647. * dmap_put_buf, ref count becomes 0 and memory will be freed.
  648. */
  649. temp_dmabuf = dma_buf_get(*fd);
  650. if (IS_ERR_OR_NULL(temp_dmabuf)) {
  651. rc = PTR_ERR(temp_dmabuf);
  652. CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d, i_ino=%lu, rc=%d", *fd, *i_ino, rc);
  653. goto put_buf;
  654. }
  655. return rc;
  656. put_buf:
  657. dma_buf_put(*dmabuf);
  658. return rc;
  659. }
  660. static int cam_mem_util_check_alloc_flags(struct cam_mem_mgr_alloc_cmd *cmd)
  661. {
  662. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  663. CAM_ERR(CAM_MEM, "Num of mmu hdl exceeded maximum(%d)",
  664. CAM_MEM_MMU_MAX_HANDLE);
  665. return -EINVAL;
  666. }
  667. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  668. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  669. CAM_ERR(CAM_MEM, "Kernel mapping in secure mode not allowed");
  670. return -EINVAL;
  671. }
  672. if ((cmd->flags & CAM_MEM_FLAG_EVA_NOPIXEL) &&
  673. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE ||
  674. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS)){
  675. CAM_ERR(CAM_MEM,
  676. "Kernel mapping and secure mode not allowed in no pixel mode");
  677. return -EINVAL;
  678. }
  679. return 0;
  680. }
  681. static int cam_mem_util_check_map_flags(struct cam_mem_mgr_map_cmd *cmd)
  682. {
  683. if (!cmd->flags) {
  684. CAM_ERR(CAM_MEM, "Invalid flags");
  685. return -EINVAL;
  686. }
  687. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  688. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  689. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  690. return -EINVAL;
  691. }
  692. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  693. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  694. CAM_ERR(CAM_MEM,
  695. "Kernel mapping in secure mode not allowed, flags=0x%x",
  696. cmd->flags);
  697. return -EINVAL;
  698. }
  699. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  700. CAM_ERR(CAM_MEM,
  701. "Shared memory buffers are not allowed to be mapped");
  702. return -EINVAL;
  703. }
  704. return 0;
  705. }
  706. static int cam_mem_util_map_hw_va(uint32_t flags,
  707. int32_t *mmu_hdls,
  708. int32_t num_hdls,
  709. int fd,
  710. struct dma_buf *dmabuf,
  711. dma_addr_t *hw_vaddr,
  712. size_t *len,
  713. enum cam_smmu_region_id region,
  714. bool is_internal)
  715. {
  716. int i;
  717. int rc = -1;
  718. int dir = cam_mem_util_get_dma_dir(flags);
  719. bool dis_delayed_unmap = false;
  720. if (dir < 0) {
  721. CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir);
  722. return dir;
  723. }
  724. if (flags & CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP)
  725. dis_delayed_unmap = true;
  726. CAM_DBG(CAM_MEM,
  727. "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d",
  728. fd, flags, dir, num_hdls);
  729. for (i = 0; i < num_hdls; i++) {
  730. /* If 36-bit enabled, check for ICP cmd buffers and map them within the shared region */
  731. if (cam_smmu_is_expanded_memory() &&
  732. cam_smmu_supports_shared_region(mmu_hdls[i]) &&
  733. (flags & CAM_MEM_FLAG_CMD_BUF_TYPE))
  734. region = CAM_SMMU_REGION_SHARED;
  735. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  736. rc = cam_smmu_map_stage2_iova(mmu_hdls[i], fd, dmabuf, dir, hw_vaddr, len);
  737. else
  738. rc = cam_smmu_map_user_iova(mmu_hdls[i], fd, dmabuf, dis_delayed_unmap, dir,
  739. hw_vaddr, len, region, is_internal);
  740. if (rc) {
  741. CAM_ERR(CAM_MEM,
  742. "Failed %s map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, rc=%d",
  743. (flags & CAM_MEM_FLAG_PROTECTED_MODE) ? "" : "secured",
  744. i, fd, dir, mmu_hdls[i], rc);
  745. goto multi_map_fail;
  746. }
  747. }
  748. return rc;
  749. multi_map_fail:
  750. for (--i; i>= 0; i--) {
  751. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  752. cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd, dmabuf);
  753. else
  754. cam_smmu_unmap_user_iova(mmu_hdls[i], fd, dmabuf, CAM_SMMU_REGION_IO);
  755. }
  756. return rc;
  757. }
  758. int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd)
  759. {
  760. int rc;
  761. int32_t idx;
  762. struct dma_buf *dmabuf = NULL;
  763. int fd = -1;
  764. dma_addr_t hw_vaddr = 0;
  765. size_t len;
  766. uintptr_t kvaddr = 0;
  767. size_t klen;
  768. unsigned long i_ino = 0;
  769. if (!atomic_read(&cam_mem_mgr_state)) {
  770. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  771. return -EINVAL;
  772. }
  773. if (!cmd) {
  774. CAM_ERR(CAM_MEM, " Invalid argument");
  775. return -EINVAL;
  776. }
  777. len = cmd->len;
  778. if (tbl.need_shared_buffer_padding &&
  779. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)) {
  780. len += CAM_MEM_SHARED_BUFFER_PAD_4K;
  781. CAM_DBG(CAM_MEM, "Pad 4k size, actual %llu, allocating %zu",
  782. cmd->len, len);
  783. }
  784. rc = cam_mem_util_check_alloc_flags(cmd);
  785. if (rc) {
  786. CAM_ERR(CAM_MEM, "Invalid flags: flags = 0x%X, rc=%d",
  787. cmd->flags, rc);
  788. return rc;
  789. }
  790. rc = cam_mem_util_buffer_alloc(len, cmd->flags, &dmabuf, &fd, &i_ino);
  791. if (rc) {
  792. CAM_ERR(CAM_MEM,
  793. "Ion Alloc failed, len=%llu, align=%llu, flags=0x%x, num_hdl=%d",
  794. len, cmd->align, cmd->flags, cmd->num_hdl);
  795. cam_mem_mgr_print_tbl();
  796. return rc;
  797. }
  798. if (!dmabuf) {
  799. CAM_ERR(CAM_MEM,
  800. "Ion Alloc return NULL dmabuf! fd=%d, i_ino=%lu, len=%d", fd, i_ino, len);
  801. cam_mem_mgr_print_tbl();
  802. return rc;
  803. }
  804. idx = cam_mem_get_slot();
  805. if (idx < 0) {
  806. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  807. rc = -ENOMEM;
  808. goto slot_fail;
  809. }
  810. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  811. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  812. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  813. enum cam_smmu_region_id region;
  814. if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  815. region = CAM_SMMU_REGION_IO;
  816. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  817. region = CAM_SMMU_REGION_SHARED;
  818. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  819. region = CAM_SMMU_REGION_IO;
  820. rc = cam_mem_util_map_hw_va(cmd->flags,
  821. cmd->mmu_hdls,
  822. cmd->num_hdl,
  823. fd,
  824. dmabuf,
  825. &hw_vaddr,
  826. &len,
  827. region,
  828. true);
  829. if (rc) {
  830. CAM_ERR(CAM_MEM,
  831. "Failed in map_hw_va len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d",
  832. len, cmd->flags,
  833. fd, region, cmd->num_hdl, rc);
  834. if (rc == -EALREADY) {
  835. if ((size_t)dmabuf->size != len)
  836. rc = -EBADR;
  837. cam_mem_mgr_print_tbl();
  838. }
  839. goto map_hw_fail;
  840. }
  841. }
  842. mutex_lock(&tbl.bufq[idx].q_lock);
  843. tbl.bufq[idx].fd = fd;
  844. tbl.bufq[idx].i_ino = i_ino;
  845. tbl.bufq[idx].dma_buf = NULL;
  846. tbl.bufq[idx].flags = cmd->flags;
  847. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd);
  848. tbl.bufq[idx].is_internal = true;
  849. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  850. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  851. if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  852. rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen);
  853. if (rc) {
  854. CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d",
  855. dmabuf, rc);
  856. goto map_kernel_fail;
  857. }
  858. }
  859. if (cmd->flags & CAM_MEM_FLAG_KMD_DEBUG_FLAG)
  860. tbl.dbg_buf_idx = idx;
  861. tbl.bufq[idx].kmdvaddr = kvaddr;
  862. tbl.bufq[idx].vaddr = hw_vaddr;
  863. tbl.bufq[idx].dma_buf = dmabuf;
  864. tbl.bufq[idx].len = len;
  865. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  866. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  867. sizeof(int32_t) * cmd->num_hdl);
  868. tbl.bufq[idx].is_imported = false;
  869. mutex_unlock(&tbl.bufq[idx].q_lock);
  870. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  871. cmd->out.fd = tbl.bufq[idx].fd;
  872. cmd->out.vaddr = 0;
  873. CAM_DBG(CAM_MEM,
  874. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu, i_ino=%lu",
  875. cmd->out.fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  876. tbl.bufq[idx].len, tbl.bufq[idx].i_ino);
  877. return rc;
  878. map_kernel_fail:
  879. mutex_unlock(&tbl.bufq[idx].q_lock);
  880. map_hw_fail:
  881. cam_mem_put_slot(idx);
  882. slot_fail:
  883. dma_buf_put(dmabuf);
  884. return rc;
  885. }
  886. static bool cam_mem_util_is_map_internal(int32_t fd, unsigned i_ino)
  887. {
  888. uint32_t i;
  889. bool is_internal = false;
  890. mutex_lock(&tbl.m_lock);
  891. for_each_set_bit(i, tbl.bitmap, tbl.bits) {
  892. if ((tbl.bufq[i].fd == fd) && (tbl.bufq[i].i_ino == i_ino)) {
  893. is_internal = tbl.bufq[i].is_internal;
  894. break;
  895. }
  896. }
  897. mutex_unlock(&tbl.m_lock);
  898. return is_internal;
  899. }
  900. int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd)
  901. {
  902. int32_t idx;
  903. int rc;
  904. struct dma_buf *dmabuf;
  905. dma_addr_t hw_vaddr = 0;
  906. size_t len = 0;
  907. bool is_internal = false;
  908. unsigned long i_ino;
  909. if (!atomic_read(&cam_mem_mgr_state)) {
  910. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  911. return -EINVAL;
  912. }
  913. if (!cmd || (cmd->fd < 0)) {
  914. CAM_ERR(CAM_MEM, "Invalid argument");
  915. return -EINVAL;
  916. }
  917. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  918. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  919. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  920. return -EINVAL;
  921. }
  922. rc = cam_mem_util_check_map_flags(cmd);
  923. if (rc) {
  924. CAM_ERR(CAM_MEM, "Invalid flags: flags = %X", cmd->flags);
  925. return rc;
  926. }
  927. dmabuf = dma_buf_get(cmd->fd);
  928. if (IS_ERR_OR_NULL((void *)(dmabuf))) {
  929. CAM_ERR(CAM_MEM, "Failed to import dma_buf fd");
  930. return -EINVAL;
  931. }
  932. i_ino = file_inode(dmabuf->file)->i_ino;
  933. is_internal = cam_mem_util_is_map_internal(cmd->fd, i_ino);
  934. idx = cam_mem_get_slot();
  935. if (idx < 0) {
  936. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d, fd=%d",
  937. idx, cmd->fd);
  938. rc = -ENOMEM;
  939. goto slot_fail;
  940. }
  941. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  942. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  943. rc = cam_mem_util_map_hw_va(cmd->flags,
  944. cmd->mmu_hdls,
  945. cmd->num_hdl,
  946. cmd->fd,
  947. dmabuf,
  948. &hw_vaddr,
  949. &len,
  950. CAM_SMMU_REGION_IO,
  951. is_internal);
  952. if (rc) {
  953. CAM_ERR(CAM_MEM,
  954. "Failed in map_hw_va, flags=0x%x, fd=%d, len=%llu, region=%d, num_hdl=%d, rc=%d",
  955. cmd->flags, cmd->fd, len,
  956. CAM_SMMU_REGION_IO, cmd->num_hdl, rc);
  957. if (rc == -EALREADY) {
  958. if ((size_t)dmabuf->size != len) {
  959. rc = -EBADR;
  960. cam_mem_mgr_print_tbl();
  961. }
  962. }
  963. goto map_fail;
  964. }
  965. }
  966. mutex_lock(&tbl.bufq[idx].q_lock);
  967. tbl.bufq[idx].fd = cmd->fd;
  968. tbl.bufq[idx].i_ino = i_ino;
  969. tbl.bufq[idx].dma_buf = NULL;
  970. tbl.bufq[idx].flags = cmd->flags;
  971. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, cmd->fd);
  972. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  973. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  974. tbl.bufq[idx].kmdvaddr = 0;
  975. if (cmd->num_hdl > 0)
  976. tbl.bufq[idx].vaddr = hw_vaddr;
  977. else
  978. tbl.bufq[idx].vaddr = 0;
  979. tbl.bufq[idx].dma_buf = dmabuf;
  980. tbl.bufq[idx].len = len;
  981. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  982. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  983. sizeof(int32_t) * cmd->num_hdl);
  984. tbl.bufq[idx].is_imported = true;
  985. tbl.bufq[idx].is_internal = is_internal;
  986. mutex_unlock(&tbl.bufq[idx].q_lock);
  987. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  988. cmd->out.vaddr = 0;
  989. cmd->out.size = (uint32_t)len;
  990. CAM_DBG(CAM_MEM,
  991. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu, i_ino=%lu",
  992. cmd->fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  993. tbl.bufq[idx].len, tbl.bufq[idx].i_ino);
  994. return rc;
  995. map_fail:
  996. cam_mem_put_slot(idx);
  997. slot_fail:
  998. dma_buf_put(dmabuf);
  999. return rc;
  1000. }
  1001. static int cam_mem_util_unmap_hw_va(int32_t idx,
  1002. enum cam_smmu_region_id region,
  1003. enum cam_smmu_mapping_client client)
  1004. {
  1005. int i;
  1006. uint32_t flags;
  1007. int32_t *mmu_hdls;
  1008. int num_hdls;
  1009. int fd;
  1010. struct dma_buf *dma_buf;
  1011. unsigned long i_ino;
  1012. int rc = 0;
  1013. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1014. CAM_ERR(CAM_MEM, "Incorrect index");
  1015. return -EINVAL;
  1016. }
  1017. flags = tbl.bufq[idx].flags;
  1018. mmu_hdls = tbl.bufq[idx].hdls;
  1019. num_hdls = tbl.bufq[idx].num_hdl;
  1020. fd = tbl.bufq[idx].fd;
  1021. dma_buf = tbl.bufq[idx].dma_buf;
  1022. i_ino = tbl.bufq[idx].i_ino;
  1023. CAM_DBG(CAM_MEM,
  1024. "unmap_hw_va : idx=%d, fd=%x, i_ino=%lu flags=0x%x, num_hdls=%d, client=%d",
  1025. idx, fd, i_ino, flags, num_hdls, client);
  1026. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  1027. for (i = 0; i < num_hdls; i++) {
  1028. rc = cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd, dma_buf);
  1029. if (rc < 0) {
  1030. CAM_ERR(CAM_MEM,
  1031. "Failed in secure unmap, i=%d, fd=%d, i_ino=%lu, mmu_hdl=%d, rc=%d",
  1032. i, fd, i_ino, mmu_hdls[i], rc);
  1033. goto unmap_end;
  1034. }
  1035. }
  1036. } else {
  1037. for (i = 0; i < num_hdls; i++) {
  1038. if (client == CAM_SMMU_MAPPING_USER) {
  1039. rc = cam_smmu_unmap_user_iova(mmu_hdls[i],
  1040. fd, dma_buf, region);
  1041. } else if (client == CAM_SMMU_MAPPING_KERNEL) {
  1042. rc = cam_smmu_unmap_kernel_iova(mmu_hdls[i],
  1043. tbl.bufq[idx].dma_buf, region);
  1044. } else {
  1045. CAM_ERR(CAM_MEM,
  1046. "invalid caller for unmapping : %d",
  1047. client);
  1048. rc = -EINVAL;
  1049. }
  1050. if (rc < 0) {
  1051. CAM_ERR(CAM_MEM,
  1052. "Failed in unmap, i=%d, fd=%d, i_ino=%lu, mmu_hdl=%d, region=%d, rc=%d",
  1053. i, fd, i_ino, mmu_hdls[i], region, rc);
  1054. goto unmap_end;
  1055. }
  1056. }
  1057. }
  1058. return rc;
  1059. unmap_end:
  1060. CAM_ERR(CAM_MEM, "unmapping failed");
  1061. return rc;
  1062. }
  1063. static void cam_mem_mgr_unmap_active_buf(int idx)
  1064. {
  1065. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1066. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  1067. region = CAM_SMMU_REGION_SHARED;
  1068. else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1069. region = CAM_SMMU_REGION_IO;
  1070. cam_mem_util_unmap_hw_va(idx, region, CAM_SMMU_MAPPING_USER);
  1071. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)
  1072. cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  1073. tbl.bufq[idx].kmdvaddr);
  1074. }
  1075. static int cam_mem_mgr_cleanup_table(void)
  1076. {
  1077. int i;
  1078. mutex_lock(&tbl.m_lock);
  1079. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  1080. if (!tbl.bufq[i].active) {
  1081. CAM_DBG(CAM_MEM,
  1082. "Buffer inactive at idx=%d, continuing", i);
  1083. continue;
  1084. } else {
  1085. CAM_DBG(CAM_MEM,
  1086. "Active buffer at idx=%d, possible leak needs unmapping",
  1087. i);
  1088. cam_mem_mgr_unmap_active_buf(i);
  1089. }
  1090. mutex_lock(&tbl.bufq[i].q_lock);
  1091. if (tbl.bufq[i].dma_buf) {
  1092. dma_buf_put(tbl.bufq[i].dma_buf);
  1093. tbl.bufq[i].dma_buf = NULL;
  1094. }
  1095. tbl.bufq[i].fd = -1;
  1096. tbl.bufq[i].i_ino = 0;
  1097. tbl.bufq[i].flags = 0;
  1098. tbl.bufq[i].buf_handle = -1;
  1099. tbl.bufq[i].vaddr = 0;
  1100. tbl.bufq[i].len = 0;
  1101. memset(tbl.bufq[i].hdls, 0,
  1102. sizeof(int32_t) * tbl.bufq[i].num_hdl);
  1103. tbl.bufq[i].num_hdl = 0;
  1104. tbl.bufq[i].dma_buf = NULL;
  1105. tbl.bufq[i].active = false;
  1106. tbl.bufq[i].is_internal = false;
  1107. mutex_unlock(&tbl.bufq[i].q_lock);
  1108. mutex_destroy(&tbl.bufq[i].q_lock);
  1109. }
  1110. bitmap_zero(tbl.bitmap, tbl.bits);
  1111. /* We need to reserve slot 0 because 0 is invalid */
  1112. set_bit(0, tbl.bitmap);
  1113. mutex_unlock(&tbl.m_lock);
  1114. return 0;
  1115. }
  1116. void cam_mem_mgr_deinit(void)
  1117. {
  1118. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED);
  1119. cam_mem_mgr_cleanup_table();
  1120. debugfs_remove_recursive(tbl.dentry);
  1121. mutex_lock(&tbl.m_lock);
  1122. bitmap_zero(tbl.bitmap, tbl.bits);
  1123. kfree(tbl.bitmap);
  1124. tbl.bitmap = NULL;
  1125. tbl.dbg_buf_idx = -1;
  1126. mutex_unlock(&tbl.m_lock);
  1127. mutex_destroy(&tbl.m_lock);
  1128. }
  1129. static int cam_mem_util_unmap(int32_t idx,
  1130. enum cam_smmu_mapping_client client)
  1131. {
  1132. int rc = 0;
  1133. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1134. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1135. CAM_ERR(CAM_MEM, "Incorrect index");
  1136. return -EINVAL;
  1137. }
  1138. CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx);
  1139. mutex_lock(&tbl.m_lock);
  1140. if ((!tbl.bufq[idx].active) &&
  1141. (tbl.bufq[idx].vaddr) == 0) {
  1142. CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  1143. idx);
  1144. mutex_unlock(&tbl.m_lock);
  1145. return 0;
  1146. }
  1147. /* Deactivate the buffer queue to prevent multiple unmap */
  1148. mutex_lock(&tbl.bufq[idx].q_lock);
  1149. tbl.bufq[idx].active = false;
  1150. tbl.bufq[idx].vaddr = 0;
  1151. mutex_unlock(&tbl.bufq[idx].q_lock);
  1152. mutex_unlock(&tbl.m_lock);
  1153. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) {
  1154. if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) {
  1155. rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  1156. tbl.bufq[idx].kmdvaddr);
  1157. if (rc)
  1158. CAM_ERR(CAM_MEM,
  1159. "Failed, dmabuf=%pK, kmdvaddr=%pK",
  1160. tbl.bufq[idx].dma_buf,
  1161. (void *) tbl.bufq[idx].kmdvaddr);
  1162. }
  1163. }
  1164. /* SHARED flag gets precedence, all other flags after it */
  1165. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1166. region = CAM_SMMU_REGION_SHARED;
  1167. } else {
  1168. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1169. region = CAM_SMMU_REGION_IO;
  1170. }
  1171. if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  1172. (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  1173. (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  1174. if (cam_mem_util_unmap_hw_va(idx, region, client))
  1175. CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK",
  1176. tbl.bufq[idx].dma_buf);
  1177. /*
  1178. * Workaround as smmu driver doing put_buf without get_buf for kernel mappings
  1179. * Setting NULL here so that we dont call dma_buf_pt again below
  1180. */
  1181. if (client == CAM_SMMU_MAPPING_KERNEL)
  1182. tbl.bufq[idx].dma_buf = NULL;
  1183. }
  1184. mutex_lock(&tbl.m_lock);
  1185. mutex_lock(&tbl.bufq[idx].q_lock);
  1186. tbl.bufq[idx].flags = 0;
  1187. tbl.bufq[idx].buf_handle = -1;
  1188. memset(tbl.bufq[idx].hdls, 0,
  1189. sizeof(int32_t) * CAM_MEM_MMU_MAX_HANDLE);
  1190. CAM_DBG(CAM_MEM,
  1191. "Ion buf at idx = %d freeing fd = %d, imported %d, dma_buf %pK, i_ino %lu",
  1192. idx, tbl.bufq[idx].fd, tbl.bufq[idx].is_imported, tbl.bufq[idx].dma_buf,
  1193. tbl.bufq[idx].i_ino);
  1194. if (tbl.bufq[idx].dma_buf)
  1195. dma_buf_put(tbl.bufq[idx].dma_buf);
  1196. tbl.bufq[idx].fd = -1;
  1197. tbl.bufq[idx].i_ino = 0;
  1198. tbl.bufq[idx].dma_buf = NULL;
  1199. tbl.bufq[idx].is_imported = false;
  1200. tbl.bufq[idx].is_internal = false;
  1201. tbl.bufq[idx].len = 0;
  1202. tbl.bufq[idx].num_hdl = 0;
  1203. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  1204. mutex_unlock(&tbl.bufq[idx].q_lock);
  1205. mutex_destroy(&tbl.bufq[idx].q_lock);
  1206. clear_bit(idx, tbl.bitmap);
  1207. mutex_unlock(&tbl.m_lock);
  1208. return rc;
  1209. }
  1210. int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd)
  1211. {
  1212. int idx;
  1213. int rc;
  1214. if (!atomic_read(&cam_mem_mgr_state)) {
  1215. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1216. return -EINVAL;
  1217. }
  1218. if (!cmd) {
  1219. CAM_ERR(CAM_MEM, "Invalid argument");
  1220. return -EINVAL;
  1221. }
  1222. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  1223. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1224. CAM_ERR(CAM_MEM, "Incorrect index %d extracted from mem handle",
  1225. idx);
  1226. return -EINVAL;
  1227. }
  1228. if (!tbl.bufq[idx].active) {
  1229. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1230. return -EINVAL;
  1231. }
  1232. if (tbl.bufq[idx].buf_handle != cmd->buf_handle) {
  1233. CAM_ERR(CAM_MEM,
  1234. "Released buf handle %d not matching within table %d, idx=%d",
  1235. cmd->buf_handle, tbl.bufq[idx].buf_handle, idx);
  1236. return -EINVAL;
  1237. }
  1238. CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx);
  1239. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER);
  1240. return rc;
  1241. }
  1242. int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp,
  1243. struct cam_mem_mgr_memory_desc *out)
  1244. {
  1245. struct dma_buf *buf = NULL;
  1246. int ion_fd = -1;
  1247. int rc = 0;
  1248. uintptr_t kvaddr;
  1249. dma_addr_t iova = 0;
  1250. size_t request_len = 0;
  1251. uint32_t mem_handle;
  1252. int32_t idx;
  1253. int32_t smmu_hdl = 0;
  1254. int32_t num_hdl = 0;
  1255. unsigned long i_ino = 0;
  1256. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1257. if (!atomic_read(&cam_mem_mgr_state)) {
  1258. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1259. return -EINVAL;
  1260. }
  1261. if (!inp || !out) {
  1262. CAM_ERR(CAM_MEM, "Invalid params");
  1263. return -EINVAL;
  1264. }
  1265. if (!(inp->flags & CAM_MEM_FLAG_HW_READ_WRITE ||
  1266. inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS ||
  1267. inp->flags & CAM_MEM_FLAG_CACHE)) {
  1268. CAM_ERR(CAM_MEM, "Invalid flags for request mem");
  1269. return -EINVAL;
  1270. }
  1271. rc = cam_mem_util_get_dma_buf(inp->size, inp->flags, &buf, &i_ino);
  1272. if (rc) {
  1273. CAM_ERR(CAM_MEM, "ION alloc failed for shared buffer");
  1274. goto ion_fail;
  1275. } else if (!buf) {
  1276. CAM_ERR(CAM_MEM, "ION alloc returned NULL buffer");
  1277. goto ion_fail;
  1278. } else {
  1279. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1280. }
  1281. /*
  1282. * we are mapping kva always here,
  1283. * update flags so that we do unmap properly
  1284. */
  1285. inp->flags |= CAM_MEM_FLAG_KMD_ACCESS;
  1286. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1287. if (rc) {
  1288. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1289. goto map_fail;
  1290. }
  1291. if (!inp->smmu_hdl) {
  1292. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1293. rc = -EINVAL;
  1294. goto smmu_fail;
  1295. }
  1296. /* SHARED flag gets precedence, all other flags after it */
  1297. if (inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1298. region = CAM_SMMU_REGION_SHARED;
  1299. } else {
  1300. if (inp->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1301. region = CAM_SMMU_REGION_IO;
  1302. }
  1303. rc = cam_smmu_map_kernel_iova(inp->smmu_hdl,
  1304. buf,
  1305. CAM_SMMU_MAP_RW,
  1306. &iova,
  1307. &request_len,
  1308. region);
  1309. if (rc < 0) {
  1310. CAM_ERR(CAM_MEM, "SMMU mapping failed");
  1311. goto smmu_fail;
  1312. }
  1313. smmu_hdl = inp->smmu_hdl;
  1314. num_hdl = 1;
  1315. idx = cam_mem_get_slot();
  1316. if (idx < 0) {
  1317. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1318. rc = -ENOMEM;
  1319. goto slot_fail;
  1320. }
  1321. mutex_lock(&tbl.bufq[idx].q_lock);
  1322. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1323. tbl.bufq[idx].dma_buf = buf;
  1324. tbl.bufq[idx].fd = -1;
  1325. tbl.bufq[idx].i_ino = i_ino;
  1326. tbl.bufq[idx].flags = inp->flags;
  1327. tbl.bufq[idx].buf_handle = mem_handle;
  1328. tbl.bufq[idx].kmdvaddr = kvaddr;
  1329. tbl.bufq[idx].vaddr = iova;
  1330. tbl.bufq[idx].len = inp->size;
  1331. tbl.bufq[idx].num_hdl = num_hdl;
  1332. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1333. sizeof(int32_t));
  1334. tbl.bufq[idx].is_imported = false;
  1335. mutex_unlock(&tbl.bufq[idx].q_lock);
  1336. out->kva = kvaddr;
  1337. out->iova = (uint32_t)iova;
  1338. out->smmu_hdl = smmu_hdl;
  1339. out->mem_handle = mem_handle;
  1340. out->len = inp->size;
  1341. out->region = region;
  1342. CAM_DBG(CAM_MEM, "idx=%d, dmabuf=%pK, i_ino=%lu, flags=0x%x, mem_handle=0x%x",
  1343. idx, buf, i_ino, inp->flags, mem_handle);
  1344. return rc;
  1345. slot_fail:
  1346. cam_smmu_unmap_kernel_iova(inp->smmu_hdl,
  1347. buf, region);
  1348. smmu_fail:
  1349. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1350. map_fail:
  1351. dma_buf_put(buf);
  1352. ion_fail:
  1353. return rc;
  1354. }
  1355. EXPORT_SYMBOL(cam_mem_mgr_request_mem);
  1356. int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp)
  1357. {
  1358. int32_t idx;
  1359. int rc;
  1360. if (!atomic_read(&cam_mem_mgr_state)) {
  1361. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1362. return -EINVAL;
  1363. }
  1364. if (!inp) {
  1365. CAM_ERR(CAM_MEM, "Invalid argument");
  1366. return -EINVAL;
  1367. }
  1368. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1369. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1370. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1371. return -EINVAL;
  1372. }
  1373. if (!tbl.bufq[idx].active) {
  1374. if (tbl.bufq[idx].vaddr == 0) {
  1375. CAM_ERR(CAM_MEM, "buffer is released already");
  1376. return 0;
  1377. }
  1378. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1379. return -EINVAL;
  1380. }
  1381. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1382. CAM_ERR(CAM_MEM,
  1383. "Released buf handle not matching within table");
  1384. return -EINVAL;
  1385. }
  1386. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1387. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1388. return rc;
  1389. }
  1390. EXPORT_SYMBOL(cam_mem_mgr_release_mem);
  1391. int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp,
  1392. enum cam_smmu_region_id region,
  1393. struct cam_mem_mgr_memory_desc *out)
  1394. {
  1395. struct dma_buf *buf = NULL;
  1396. int rc = 0;
  1397. int ion_fd = -1;
  1398. dma_addr_t iova = 0;
  1399. size_t request_len = 0;
  1400. uint32_t mem_handle;
  1401. int32_t idx;
  1402. int32_t smmu_hdl = 0;
  1403. int32_t num_hdl = 0;
  1404. uintptr_t kvaddr = 0;
  1405. unsigned long i_ino = 0;
  1406. if (!atomic_read(&cam_mem_mgr_state)) {
  1407. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1408. return -EINVAL;
  1409. }
  1410. if (!inp || !out) {
  1411. CAM_ERR(CAM_MEM, "Invalid param(s)");
  1412. return -EINVAL;
  1413. }
  1414. if (!inp->smmu_hdl) {
  1415. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1416. return -EINVAL;
  1417. }
  1418. if ((region != CAM_SMMU_REGION_SECHEAP) &&
  1419. (region != CAM_SMMU_REGION_FWUNCACHED)) {
  1420. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1421. return -EINVAL;
  1422. }
  1423. rc = cam_mem_util_get_dma_buf(inp->size, 0, &buf, &i_ino);
  1424. if (rc) {
  1425. CAM_ERR(CAM_MEM, "ION alloc failed for sec heap buffer");
  1426. goto ion_fail;
  1427. } else if (!buf) {
  1428. CAM_ERR(CAM_MEM, "ION alloc returned NULL buffer");
  1429. goto ion_fail;
  1430. } else {
  1431. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1432. }
  1433. if (inp->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  1434. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1435. if (rc) {
  1436. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1437. goto kmap_fail;
  1438. }
  1439. }
  1440. rc = cam_smmu_reserve_buf_region(region,
  1441. inp->smmu_hdl, buf, &iova, &request_len);
  1442. if (rc) {
  1443. CAM_ERR(CAM_MEM, "Reserving secondary heap failed");
  1444. goto smmu_fail;
  1445. }
  1446. smmu_hdl = inp->smmu_hdl;
  1447. num_hdl = 1;
  1448. idx = cam_mem_get_slot();
  1449. if (idx < 0) {
  1450. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1451. rc = -ENOMEM;
  1452. goto slot_fail;
  1453. }
  1454. mutex_lock(&tbl.bufq[idx].q_lock);
  1455. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1456. tbl.bufq[idx].fd = -1;
  1457. tbl.bufq[idx].i_ino = i_ino;
  1458. tbl.bufq[idx].dma_buf = buf;
  1459. tbl.bufq[idx].flags = inp->flags;
  1460. tbl.bufq[idx].buf_handle = mem_handle;
  1461. tbl.bufq[idx].kmdvaddr = kvaddr;
  1462. tbl.bufq[idx].vaddr = iova;
  1463. tbl.bufq[idx].len = request_len;
  1464. tbl.bufq[idx].num_hdl = num_hdl;
  1465. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1466. sizeof(int32_t));
  1467. tbl.bufq[idx].is_imported = false;
  1468. mutex_unlock(&tbl.bufq[idx].q_lock);
  1469. out->kva = kvaddr;
  1470. out->iova = (uint32_t)iova;
  1471. out->smmu_hdl = smmu_hdl;
  1472. out->mem_handle = mem_handle;
  1473. out->len = request_len;
  1474. out->region = region;
  1475. return rc;
  1476. slot_fail:
  1477. cam_smmu_release_buf_region(region, smmu_hdl);
  1478. smmu_fail:
  1479. if (region == CAM_SMMU_REGION_FWUNCACHED)
  1480. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1481. kmap_fail:
  1482. dma_buf_put(buf);
  1483. ion_fail:
  1484. return rc;
  1485. }
  1486. EXPORT_SYMBOL(cam_mem_mgr_reserve_memory_region);
  1487. int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp)
  1488. {
  1489. int32_t idx;
  1490. int rc;
  1491. int32_t smmu_hdl;
  1492. if (!atomic_read(&cam_mem_mgr_state)) {
  1493. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1494. return -EINVAL;
  1495. }
  1496. if (!inp) {
  1497. CAM_ERR(CAM_MEM, "Invalid argument");
  1498. return -EINVAL;
  1499. }
  1500. if ((inp->region != CAM_SMMU_REGION_SECHEAP) &&
  1501. (inp->region != CAM_SMMU_REGION_FWUNCACHED)) {
  1502. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1503. return -EINVAL;
  1504. }
  1505. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1506. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1507. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1508. return -EINVAL;
  1509. }
  1510. if (!tbl.bufq[idx].active) {
  1511. if (tbl.bufq[idx].vaddr == 0) {
  1512. CAM_ERR(CAM_MEM, "buffer is released already");
  1513. return 0;
  1514. }
  1515. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1516. return -EINVAL;
  1517. }
  1518. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1519. CAM_ERR(CAM_MEM,
  1520. "Released buf handle not matching within table");
  1521. return -EINVAL;
  1522. }
  1523. if (tbl.bufq[idx].num_hdl != 1) {
  1524. CAM_ERR(CAM_MEM,
  1525. "Sec heap region should have only one smmu hdl");
  1526. return -ENODEV;
  1527. }
  1528. memcpy(&smmu_hdl, tbl.bufq[idx].hdls,
  1529. sizeof(int32_t));
  1530. if (inp->smmu_hdl != smmu_hdl) {
  1531. CAM_ERR(CAM_MEM,
  1532. "Passed SMMU handle doesn't match with internal hdl");
  1533. return -ENODEV;
  1534. }
  1535. rc = cam_smmu_release_buf_region(inp->region, inp->smmu_hdl);
  1536. if (rc) {
  1537. CAM_ERR(CAM_MEM,
  1538. "Sec heap region release failed");
  1539. return -ENODEV;
  1540. }
  1541. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1542. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1543. if (rc)
  1544. CAM_ERR(CAM_MEM, "unmapping secondary heap failed");
  1545. return rc;
  1546. }
  1547. EXPORT_SYMBOL(cam_mem_mgr_free_memory_region);
  1548. #ifndef CONFIG_CAM_PRESIL
  1549. struct dma_buf * cam_mem_mgr_get_dma_buf(int fd)
  1550. {
  1551. return NULL;
  1552. }
  1553. int cam_mem_mgr_send_all_buffers_to_presil(int32_t iommu_hdl)
  1554. {
  1555. return 0;
  1556. }
  1557. int cam_mem_mgr_send_buffer_to_presil(int32_t iommu_hdl, int32_t buf_handle)
  1558. {
  1559. return 0;
  1560. }
  1561. int cam_mem_mgr_retrieve_buffer_from_presil(int32_t buf_handle,
  1562. uint32_t buf_size,
  1563. uint32_t offset,
  1564. int32_t iommu_hdl)
  1565. {
  1566. return 0;
  1567. }
  1568. #endif