hal_api_mon.h 14 KB

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  1. /*
  2. * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_API_MON_H_
  19. #define _HAL_API_MON_H_
  20. #include "qdf_types.h"
  21. #include "hal_internal.h"
  22. #include <target_type.h>
  23. #define HAL_RX_PHY_DATA_RADAR 0x01
  24. #define HAL_SU_MU_CODING_LDPC 0x01
  25. #define HAL_RX_FCS_LEN (4)
  26. #define KEY_EXTIV 0x20
  27. #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000
  28. #define HAL_RX_USER_TLV32_TYPE_LSB 1
  29. #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE
  30. #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000
  31. #define HAL_RX_USER_TLV32_LEN_LSB 10
  32. #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00
  33. #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000
  34. #define HAL_RX_USER_TLV32_USERID_LSB 26
  35. #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000
  36. #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1)
  37. #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask))
  38. #define HAL_RX_TLV32_HDR_SIZE 4
  39. #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \
  40. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  41. HAL_RX_USER_TLV32_TYPE_MASK) >> \
  42. HAL_RX_USER_TLV32_TYPE_LSB)
  43. #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \
  44. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  45. HAL_RX_USER_TLV32_LEN_MASK) >> \
  46. HAL_RX_USER_TLV32_LEN_LSB)
  47. #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \
  48. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  49. HAL_RX_USER_TLV32_USERID_MASK) >> \
  50. HAL_RX_USER_TLV32_USERID_LSB)
  51. #define HAL_TLV_STATUS_PPDU_NOT_DONE 0
  52. #define HAL_TLV_STATUS_PPDU_DONE 1
  53. #define HAL_TLV_STATUS_BUF_DONE 2
  54. #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3
  55. #define HAL_TLV_STATUS_PPDU_START 4
  56. #define HAL_TLV_STATUS_HEADER 5
  57. #define HAL_TLV_STATUS_MPDU_END 6
  58. #define HAL_TLV_STATUS_MSDU_START 7
  59. #define HAL_TLV_STATUS_MSDU_END 8
  60. #define HAL_MAX_UL_MU_USERS 8
  61. #define HAL_RX_PKT_TYPE_11A 0
  62. #define HAL_RX_PKT_TYPE_11B 1
  63. #define HAL_RX_PKT_TYPE_11N 2
  64. #define HAL_RX_PKT_TYPE_11AC 3
  65. #define HAL_RX_PKT_TYPE_11AX 4
  66. #define HAL_RX_RECEPTION_TYPE_SU 0
  67. #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1
  68. #define HAL_RX_RECEPTION_TYPE_OFDMA 2
  69. #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3
  70. /* Multiply rate by 2 to avoid float point
  71. * and get rate in units of 500kbps
  72. */
  73. #define HAL_11B_RATE_0MCS 11*2
  74. #define HAL_11B_RATE_1MCS 5.5*2
  75. #define HAL_11B_RATE_2MCS 2*2
  76. #define HAL_11B_RATE_3MCS 1*2
  77. #define HAL_11B_RATE_4MCS 11*2
  78. #define HAL_11B_RATE_5MCS 5.5*2
  79. #define HAL_11B_RATE_6MCS 2*2
  80. #define HAL_11A_RATE_0MCS 48*2
  81. #define HAL_11A_RATE_1MCS 24*2
  82. #define HAL_11A_RATE_2MCS 12*2
  83. #define HAL_11A_RATE_3MCS 6*2
  84. #define HAL_11A_RATE_4MCS 54*2
  85. #define HAL_11A_RATE_5MCS 36*2
  86. #define HAL_11A_RATE_6MCS 18*2
  87. #define HAL_11A_RATE_7MCS 9*2
  88. #define HAL_LEGACY_MCS0 0
  89. #define HAL_LEGACY_MCS1 1
  90. #define HAL_LEGACY_MCS2 2
  91. #define HAL_LEGACY_MCS3 3
  92. #define HAL_LEGACY_MCS4 4
  93. #define HAL_LEGACY_MCS5 5
  94. #define HAL_LEGACY_MCS6 6
  95. #define HAL_LEGACY_MCS7 7
  96. #define HE_GI_0_8 0
  97. #define HE_GI_0_4 1
  98. #define HE_GI_1_6 2
  99. #define HE_GI_3_2 3
  100. #define HT_SGI_PRESENT 0x80
  101. #define HE_LTF_1_X 0
  102. #define HE_LTF_2_X 1
  103. #define HE_LTF_4_X 2
  104. #define HE_LTF_UNKNOWN 3
  105. #define VHT_SIG_SU_NSS_MASK 0x7
  106. #define HT_SIG_SU_NSS_SHIFT 0x3
  107. #define HAL_TID_INVALID 31
  108. #define HAL_AST_IDX_INVALID 0xFFFF
  109. #ifdef GET_MSDU_AGGREGATION
  110. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\
  111. {\
  112. struct rx_msdu_end *rx_msdu_end;\
  113. bool first_msdu, last_msdu; \
  114. rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\
  115. first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\
  116. last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\
  117. if (first_msdu && last_msdu)\
  118. rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\
  119. else\
  120. rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \
  121. } \
  122. #else
  123. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)
  124. #endif
  125. enum {
  126. DP_PPDU_STATUS_START,
  127. DP_PPDU_STATUS_DONE,
  128. };
  129. static inline
  130. uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void)
  131. {
  132. /* return the HW_RX_DESC size */
  133. return sizeof(struct rx_pkt_tlvs);
  134. }
  135. static inline
  136. uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data)
  137. {
  138. return data;
  139. }
  140. static inline
  141. uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr)
  142. {
  143. struct rx_attention *rx_attn;
  144. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  145. rx_attn = &rx_desc->attn_tlv.rx_attn;
  146. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR);
  147. }
  148. static inline
  149. uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr)
  150. {
  151. struct rx_attention *rx_attn;
  152. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  153. rx_attn = &rx_desc->attn_tlv.rx_attn;
  154. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR);
  155. }
  156. /*
  157. * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU
  158. * start TLV of Hardware TLV descriptor
  159. * @hw_desc_addr: Hardware desciptor address
  160. *
  161. * Return: bool: if TLV tag match
  162. */
  163. static inline
  164. bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr)
  165. {
  166. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  167. uint32_t tlv_tag;
  168. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(
  169. &rx_desc->mpdu_start_tlv);
  170. return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
  171. }
  172. static inline
  173. uint32_t HAL_RX_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr)
  174. {
  175. struct rx_mpdu_info *rx_mpdu_info;
  176. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  177. rx_mpdu_info =
  178. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  179. return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
  180. }
  181. /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */
  182. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  183. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  184. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \
  185. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \
  186. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB))
  187. #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \
  188. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  189. (((struct reo_entrance_ring *)reo_ent_desc) \
  190. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  191. #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \
  192. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  193. (((struct reo_entrance_ring *)reo_ent_desc) \
  194. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  195. #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \
  196. (HAL_RX_BUF_COOKIE_GET(& \
  197. (((struct reo_entrance_ring *)reo_ent_desc) \
  198. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  199. /**
  200. * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and
  201. * cookie from the REO entrance ring element
  202. *
  203. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  204. * the current descriptor
  205. * @ buf_info: structure to return the buffer information
  206. * @ msdu_cnt: pointer to msdu count in MPDU
  207. * Return: void
  208. */
  209. static inline
  210. void hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
  211. struct hal_buf_info *buf_info,
  212. void **pp_buf_addr_info,
  213. uint32_t *msdu_cnt
  214. )
  215. {
  216. struct reo_entrance_ring *reo_ent_ring =
  217. (struct reo_entrance_ring *)rx_desc;
  218. struct buffer_addr_info *buf_addr_info;
  219. struct rx_mpdu_desc_info *rx_mpdu_desc_info_details;
  220. uint32_t loop_cnt;
  221. rx_mpdu_desc_info_details =
  222. &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
  223. *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details,
  224. RX_MPDU_DESC_INFO_0, MSDU_COUNT);
  225. loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT);
  226. buf_addr_info =
  227. &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info;
  228. buf_info->paddr =
  229. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  230. ((uint64_t)
  231. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  232. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  233. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  234. "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d",
  235. __func__, __LINE__, reo_ent_ring, buf_addr_info,
  236. (unsigned long long)buf_info->paddr, loop_cnt);
  237. *pp_buf_addr_info = (void *)buf_addr_info;
  238. }
  239. static inline
  240. void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
  241. struct hal_buf_info *buf_info, void **pp_buf_addr_info)
  242. {
  243. struct rx_msdu_link *msdu_link =
  244. (struct rx_msdu_link *)rx_msdu_link_desc;
  245. struct buffer_addr_info *buf_addr_info;
  246. buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info;
  247. buf_info->paddr =
  248. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  249. ((uint64_t)
  250. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  251. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  252. *pp_buf_addr_info = (void *)buf_addr_info;
  253. }
  254. /**
  255. * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
  256. *
  257. * @ soc : HAL version of the SOC pointer
  258. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  259. * @ buf_addr_info : void pointer to the buffer_addr_info
  260. *
  261. * Return: void
  262. */
  263. static inline void hal_rx_mon_msdu_link_desc_set(struct hal_soc *soc,
  264. void *src_srng_desc, void *buf_addr_info)
  265. {
  266. struct buffer_addr_info *wbm_srng_buffer_addr_info =
  267. (struct buffer_addr_info *)src_srng_desc;
  268. uint64_t paddr;
  269. struct buffer_addr_info *p_buffer_addr_info =
  270. (struct buffer_addr_info *)buf_addr_info;
  271. paddr =
  272. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  273. ((uint64_t)
  274. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  275. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  276. "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx",
  277. __func__, __LINE__, src_srng_desc, (unsigned long long)paddr,
  278. (unsigned long long)p_buffer_addr_info->sw_buffer_cookie);
  279. /* Structure copy !!! */
  280. *wbm_srng_buffer_addr_info =
  281. *((struct buffer_addr_info *)buf_addr_info);
  282. }
  283. static inline
  284. uint32 hal_get_rx_msdu_link_desc_size(void)
  285. {
  286. return sizeof(struct rx_msdu_link);
  287. }
  288. enum {
  289. HAL_PKT_TYPE_OFDM = 0,
  290. HAL_PKT_TYPE_CCK,
  291. HAL_PKT_TYPE_HT,
  292. HAL_PKT_TYPE_VHT,
  293. HAL_PKT_TYPE_HE,
  294. };
  295. enum {
  296. HAL_SGI_0_8_US,
  297. HAL_SGI_0_4_US,
  298. HAL_SGI_1_6_US,
  299. HAL_SGI_3_2_US,
  300. };
  301. enum {
  302. HAL_FULL_RX_BW_20,
  303. HAL_FULL_RX_BW_40,
  304. HAL_FULL_RX_BW_80,
  305. HAL_FULL_RX_BW_160,
  306. };
  307. enum {
  308. HAL_RX_TYPE_SU,
  309. HAL_RX_TYPE_MU_MIMO,
  310. HAL_RX_TYPE_MU_OFDMA,
  311. HAL_RX_TYPE_MU_OFDMA_MIMO,
  312. };
  313. /**
  314. * enum
  315. * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL
  316. * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL
  317. */
  318. enum {
  319. HAL_RX_MON_PPDU_START = 0,
  320. HAL_RX_MON_PPDU_END,
  321. };
  322. struct hal_rx_ppdu_common_info {
  323. uint32_t ppdu_id;
  324. uint32_t ppdu_timestamp;
  325. uint32_t mpdu_cnt_fcs_ok;
  326. uint32_t mpdu_cnt_fcs_err;
  327. };
  328. struct hal_rx_msdu_payload_info {
  329. uint8_t *first_msdu_payload;
  330. uint32_t payload_len;
  331. };
  332. /**
  333. * struct hal_rx_nac_info - struct for neighbour info
  334. * @fc_valid: flag indicate if it has valid frame control information
  335. * @to_ds_flag: flag indicate to_ds bit
  336. * @mac_addr2_valid: flag indicate if mac_addr2 is valid
  337. * @mac_addr2: mac address2 in wh
  338. */
  339. struct hal_rx_nac_info {
  340. uint8_t fc_valid;
  341. uint8_t to_ds_flag;
  342. uint8_t mac_addr2_valid;
  343. uint8_t mac_addr2[QDF_MAC_ADDR_SIZE];
  344. };
  345. struct hal_rx_ppdu_info {
  346. struct hal_rx_ppdu_common_info com_info;
  347. struct mon_rx_status rx_status;
  348. struct mon_rx_user_status rx_user_status[HAL_MAX_UL_MU_USERS];
  349. struct hal_rx_msdu_payload_info msdu_info;
  350. struct hal_rx_nac_info nac_info;
  351. /* status ring PPDU start and end state */
  352. uint32_t rx_state;
  353. /* MU user id for status ring TLV */
  354. uint32_t user_id;
  355. /* MPDU/MSDU truncated to 128 bytes header start addr in status skb */
  356. unsigned char *data;
  357. /* MPDU/MSDU truncated to 128 bytes header real length */
  358. uint32_t hdr_len;
  359. /* MPDU FCS error */
  360. bool fcs_err;
  361. };
  362. static inline uint32_t
  363. hal_get_rx_status_buf_size(void) {
  364. /* RX status buffer size is hard coded for now */
  365. return 2048;
  366. }
  367. static inline uint8_t*
  368. hal_rx_status_get_next_tlv(uint8_t *rx_tlv) {
  369. uint32_t tlv_len, tlv_tag;
  370. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
  371. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  372. /* The actual length of PPDU_END is the combined length of many PHY
  373. * TLVs that follow. Skip the TLV header and
  374. * rx_rxpcu_classification_overview that follows the header to get to
  375. * next TLV.
  376. */
  377. if (tlv_tag == WIFIRX_PPDU_END_E)
  378. tlv_len = sizeof(struct rx_rxpcu_classification_overview);
  379. return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len +
  380. HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3)));
  381. }
  382. /**
  383. * hal_rx_proc_phyrx_other_receive_info_tlv()
  384. * - process other receive info TLV
  385. * @rx_tlv_hdr: pointer to TLV header
  386. * @ppdu_info: pointer to ppdu_info
  387. *
  388. * Return: None
  389. */
  390. static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc,
  391. void *rx_tlv_hdr,
  392. struct hal_rx_ppdu_info
  393. *ppdu_info)
  394. {
  395. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr,
  396. (void *)ppdu_info);
  397. }
  398. /**
  399. * hal_rx_status_get_tlv_info() - process receive info TLV
  400. * @rx_tlv_hdr: pointer to TLV header
  401. * @ppdu_info: pointer to ppdu_info
  402. *
  403. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  404. */
  405. static inline uint32_t
  406. hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info,
  407. struct hal_soc *hal_soc)
  408. {
  409. return hal_soc->ops->hal_rx_status_get_tlv_info(rx_tlv_hdr,
  410. ppdu_info, hal_soc);
  411. }
  412. static inline
  413. uint32_t hal_get_rx_status_done_tlv_size(void *hal_soc)
  414. {
  415. return HAL_RX_TLV32_HDR_SIZE;
  416. }
  417. static inline QDF_STATUS
  418. hal_get_rx_status_done(uint8_t *rx_tlv)
  419. {
  420. uint32_t tlv_tag;
  421. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  422. if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E)
  423. return QDF_STATUS_SUCCESS;
  424. else
  425. return QDF_STATUS_E_EMPTY;
  426. }
  427. static inline QDF_STATUS
  428. hal_clear_rx_status_done(uint8_t *rx_tlv)
  429. {
  430. *(uint32_t *)rx_tlv = 0;
  431. return QDF_STATUS_SUCCESS;
  432. }
  433. #endif