dp_be.c 55 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #ifdef WIFI_MONITOR_SUPPORT
  26. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  27. #include "dp_mon_2.0.h"
  28. #endif
  29. #include "dp_mon.h"
  30. #endif
  31. #include <hal_be_api.h>
  32. /* Generic AST entry aging timer value */
  33. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  34. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  35. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  36. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  37. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  38. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  39. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  40. #ifdef QCA_WIFI_KIWI_V2
  41. {3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
  42. {4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
  43. #else
  44. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  45. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  46. #endif
  47. };
  48. #else
  49. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  50. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  51. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  52. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  53. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  54. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  55. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  56. };
  57. #endif
  58. #ifdef WLAN_SUPPORT_PPEDS
  59. static void dp_ppeds_rings_status(struct dp_soc *soc)
  60. {
  61. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  62. dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE);
  63. dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL);
  64. }
  65. #endif
  66. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  67. {
  68. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  69. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  70. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  71. /* this is used only when dmac mode is enabled */
  72. soc->num_rx_refill_buf_rings = 1;
  73. soc->wlan_cfg_ctx->notify_frame_support =
  74. DP_MARK_NOTIFY_FRAME_SUPPORT;
  75. }
  76. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  77. {
  78. switch (context_type) {
  79. case DP_CONTEXT_TYPE_SOC:
  80. return sizeof(struct dp_soc_be);
  81. case DP_CONTEXT_TYPE_PDEV:
  82. return sizeof(struct dp_pdev_be);
  83. case DP_CONTEXT_TYPE_VDEV:
  84. return sizeof(struct dp_vdev_be);
  85. case DP_CONTEXT_TYPE_PEER:
  86. return sizeof(struct dp_peer_be);
  87. default:
  88. return 0;
  89. }
  90. }
  91. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  92. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  93. /**
  94. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  95. per wbm2sw ring
  96. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  97. *
  98. * Return: None
  99. */
  100. static inline
  101. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  102. {
  103. cc_cfg->wbm2sw6_cc_en = 1;
  104. cc_cfg->wbm2sw5_cc_en = 1;
  105. cc_cfg->wbm2sw4_cc_en = 1;
  106. cc_cfg->wbm2sw3_cc_en = 1;
  107. cc_cfg->wbm2sw2_cc_en = 1;
  108. /* disable wbm2sw1 hw cc as it's for FW */
  109. cc_cfg->wbm2sw1_cc_en = 0;
  110. cc_cfg->wbm2sw0_cc_en = 1;
  111. cc_cfg->wbm2fw_cc_en = 0;
  112. }
  113. #else
  114. static inline
  115. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  116. {
  117. cc_cfg->wbm2sw6_cc_en = 1;
  118. cc_cfg->wbm2sw5_cc_en = 1;
  119. cc_cfg->wbm2sw4_cc_en = 1;
  120. cc_cfg->wbm2sw3_cc_en = 1;
  121. cc_cfg->wbm2sw2_cc_en = 1;
  122. cc_cfg->wbm2sw1_cc_en = 1;
  123. cc_cfg->wbm2sw0_cc_en = 1;
  124. cc_cfg->wbm2fw_cc_en = 0;
  125. }
  126. #endif
  127. #if defined(WLAN_SUPPORT_RX_FISA)
  128. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  129. {
  130. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  131. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  132. /* get CMEM for cookie conversion */
  133. if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
  134. dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
  135. return QDF_STATUS_E_NOMEM;
  136. }
  137. soc->fst_cmem_size = DP_CMEM_FST_SIZE;
  138. soc->fst_cmem_base = soc->cmem_base +
  139. (soc->cmem_total_size - soc->cmem_avail_size);
  140. soc->cmem_avail_size -= soc->fst_cmem_size;
  141. dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
  142. soc->fst_cmem_base, soc->fst_cmem_size);
  143. return QDF_STATUS_SUCCESS;
  144. }
  145. #else /* !WLAN_SUPPORT_RX_FISA */
  146. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  147. {
  148. return QDF_STATUS_SUCCESS;
  149. }
  150. #endif
  151. /**
  152. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  153. conversion register
  154. * @soc: SOC handle
  155. * @is_4k_align: page address 4k alignd
  156. *
  157. * Return: None
  158. */
  159. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  160. bool is_4k_align)
  161. {
  162. struct hal_hw_cc_config cc_cfg = { 0 };
  163. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  164. if (soc->cdp_soc.ol_ops->get_con_mode &&
  165. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  166. return;
  167. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  168. dp_info("INI skip HW CC register setting");
  169. return;
  170. }
  171. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  172. cc_cfg.cc_global_en = true;
  173. cc_cfg.page_4k_align = is_4k_align;
  174. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  175. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  176. /* 36th bit should be 1 then HW know this is CMEM address */
  177. cc_cfg.lut_base_addr_39_32 = 0x10;
  178. cc_cfg.error_path_cookie_conv_en = true;
  179. cc_cfg.release_path_cookie_conv_en = true;
  180. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  181. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  182. }
  183. /**
  184. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  185. * @hal_soc_hdl: HAL SOC handle
  186. * @offset: CMEM address
  187. * @value: value to write
  188. *
  189. * Return: None.
  190. */
  191. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  192. uint32_t offset,
  193. uint32_t value)
  194. {
  195. hal_cmem_write(hal_soc_hdl, offset, value);
  196. }
  197. /**
  198. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  199. HW cookie conversion
  200. * @soc: SOC handle
  201. * @cc_ctx: cookie conversion context pointer
  202. *
  203. * Return: 0 in case of success, else error value
  204. */
  205. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  206. {
  207. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  208. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  209. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  210. /* get CMEM for cookie conversion */
  211. if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
  212. dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
  213. return QDF_STATUS_E_RESOURCES;
  214. }
  215. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  216. DP_CC_MEM_OFFSET_IN_CMEM);
  217. soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
  218. dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
  219. be_soc->cc_cmem_base, soc->cmem_avail_size);
  220. return QDF_STATUS_SUCCESS;
  221. }
  222. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  223. uint8_t for_feature)
  224. {
  225. QDF_STATUS status = QDF_STATUS_E_NOMEM;
  226. switch (for_feature) {
  227. case COOKIE_CONVERSION:
  228. status = dp_hw_cc_cmem_addr_init(soc);
  229. break;
  230. case FISA_FST:
  231. status = dp_fisa_fst_cmem_addr_init(soc);
  232. break;
  233. default:
  234. dp_err("Invalid CMEM request");
  235. }
  236. return status;
  237. }
  238. #else
  239. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  240. bool is_4k_align) {}
  241. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  242. uint32_t offset,
  243. uint32_t value)
  244. { }
  245. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  246. {
  247. return QDF_STATUS_SUCCESS;
  248. }
  249. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  250. uint8_t for_feature)
  251. {
  252. return QDF_STATUS_SUCCESS;
  253. }
  254. #endif
  255. QDF_STATUS
  256. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  257. struct dp_hw_cookie_conversion_t *cc_ctx,
  258. uint32_t num_descs,
  259. enum dp_desc_type desc_type,
  260. uint8_t desc_pool_id)
  261. {
  262. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  263. uint32_t num_spt_pages, i = 0;
  264. struct dp_spt_page_desc *spt_desc;
  265. struct qdf_mem_dma_page_t *dma_page;
  266. uint8_t chip_id;
  267. /* estimate how many SPT DDR pages needed */
  268. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  269. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  270. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  271. dp_info("num_spt_pages needed %d", num_spt_pages);
  272. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  273. &cc_ctx->page_pool, qdf_page_size,
  274. num_spt_pages, 0, false);
  275. if (!cc_ctx->page_pool.dma_pages) {
  276. dp_err("spt ddr pages allocation failed");
  277. return QDF_STATUS_E_RESOURCES;
  278. }
  279. cc_ctx->page_desc_base = qdf_mem_malloc(
  280. num_spt_pages * sizeof(struct dp_spt_page_desc));
  281. if (!cc_ctx->page_desc_base) {
  282. dp_err("spt page descs allocation failed");
  283. goto fail_0;
  284. }
  285. chip_id = dp_mlo_get_chip_id(soc);
  286. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  287. desc_type);
  288. /* initial page desc */
  289. spt_desc = cc_ctx->page_desc_base;
  290. dma_page = cc_ctx->page_pool.dma_pages;
  291. while (i < num_spt_pages) {
  292. /* check if page address 4K aligned */
  293. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  294. dp_err("non-4k aligned pages addr %pK",
  295. (void *)dma_page[i].page_p_addr);
  296. goto fail_1;
  297. }
  298. spt_desc[i].page_v_addr =
  299. dma_page[i].page_v_addr_start;
  300. spt_desc[i].page_p_addr =
  301. dma_page[i].page_p_addr;
  302. i++;
  303. }
  304. cc_ctx->total_page_num = num_spt_pages;
  305. qdf_spinlock_create(&cc_ctx->cc_lock);
  306. return QDF_STATUS_SUCCESS;
  307. fail_1:
  308. qdf_mem_free(cc_ctx->page_desc_base);
  309. fail_0:
  310. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  311. &cc_ctx->page_pool, 0, false);
  312. return QDF_STATUS_E_FAILURE;
  313. }
  314. QDF_STATUS
  315. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  316. struct dp_hw_cookie_conversion_t *cc_ctx)
  317. {
  318. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  319. qdf_mem_free(cc_ctx->page_desc_base);
  320. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  321. &cc_ctx->page_pool, 0, false);
  322. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  323. return QDF_STATUS_SUCCESS;
  324. }
  325. QDF_STATUS
  326. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  327. struct dp_hw_cookie_conversion_t *cc_ctx)
  328. {
  329. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  330. uint32_t i = 0;
  331. struct dp_spt_page_desc *spt_desc;
  332. uint32_t ppt_index;
  333. uint32_t ppt_id_start;
  334. if (!cc_ctx->total_page_num) {
  335. dp_err("total page num is 0");
  336. return QDF_STATUS_E_INVAL;
  337. }
  338. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  339. spt_desc = cc_ctx->page_desc_base;
  340. while (i < cc_ctx->total_page_num) {
  341. /* write page PA to CMEM */
  342. dp_hw_cc_cmem_write(soc->hal_soc,
  343. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  344. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  345. (spt_desc[i].page_p_addr >>
  346. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  347. ppt_index = ppt_id_start + i;
  348. if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
  349. qdf_assert_always(0);
  350. spt_desc[i].ppt_index = ppt_index;
  351. be_soc->page_desc_base[ppt_index].page_v_addr =
  352. spt_desc[i].page_v_addr;
  353. i++;
  354. }
  355. return QDF_STATUS_SUCCESS;
  356. }
  357. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  358. QDF_STATUS
  359. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  360. struct dp_hw_cookie_conversion_t *cc_ctx)
  361. {
  362. uint32_t ppt_index;
  363. struct dp_spt_page_desc *spt_desc;
  364. int i = 0;
  365. spt_desc = cc_ctx->page_desc_base;
  366. while (i < cc_ctx->total_page_num) {
  367. ppt_index = spt_desc[i].ppt_index;
  368. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  369. i++;
  370. }
  371. return QDF_STATUS_SUCCESS;
  372. }
  373. #else
  374. QDF_STATUS
  375. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  376. struct dp_hw_cookie_conversion_t *cc_ctx)
  377. {
  378. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  379. uint32_t ppt_index;
  380. struct dp_spt_page_desc *spt_desc;
  381. int i = 0;
  382. spt_desc = cc_ctx->page_desc_base;
  383. while (i < cc_ctx->total_page_num) {
  384. /* reset PA in CMEM to NULL */
  385. dp_hw_cc_cmem_write(soc->hal_soc,
  386. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  387. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  388. 0);
  389. ppt_index = spt_desc[i].ppt_index;
  390. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  391. i++;
  392. }
  393. return QDF_STATUS_SUCCESS;
  394. }
  395. #endif
  396. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  397. {
  398. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  399. int i = 0;
  400. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  401. dp_hw_cookie_conversion_detach(be_soc,
  402. &be_soc->tx_cc_ctx[i]);
  403. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  404. dp_hw_cookie_conversion_detach(be_soc,
  405. &be_soc->rx_cc_ctx[i]);
  406. qdf_mem_free(be_soc->page_desc_base);
  407. be_soc->page_desc_base = NULL;
  408. return QDF_STATUS_SUCCESS;
  409. }
  410. #ifdef WLAN_MLO_MULTI_CHIP
  411. #ifdef WLAN_MCAST_MLO
  412. static inline void
  413. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  414. {
  415. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  416. be_vdev->mcast_primary = false;
  417. be_vdev->seq_num = 0;
  418. dp_tx_mcast_mlo_reinject_routing_set(soc,
  419. (void *)&be_vdev->mcast_primary);
  420. if (vdev->opmode == wlan_op_mode_ap) {
  421. if (vdev->mlo_vdev)
  422. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  423. vdev->vdev_id,
  424. HAL_TX_MCAST_CTRL_DROP);
  425. else
  426. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  427. vdev->vdev_id,
  428. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  429. }
  430. }
  431. static inline void
  432. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  433. {
  434. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  435. be_vdev->seq_num = 0;
  436. be_vdev->mcast_primary = false;
  437. vdev->mlo_vdev = false;
  438. }
  439. #else
  440. static inline void
  441. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  442. {
  443. }
  444. static inline void
  445. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  446. {
  447. }
  448. #endif
  449. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  450. {
  451. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  452. qdf_mem_set(be_vdev->partner_vdev_list,
  453. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  454. CDP_INVALID_VDEV_ID);
  455. }
  456. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  457. struct cdp_lro_hash_config *lro_hash)
  458. {
  459. dp_mlo_get_rx_hash_key(soc, lro_hash);
  460. }
  461. #else
  462. static inline void
  463. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  464. {
  465. }
  466. static inline void
  467. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  468. {
  469. }
  470. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  471. {
  472. }
  473. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  474. struct cdp_lro_hash_config *lro_hash)
  475. {
  476. dp_get_rx_hash_key_bytes(lro_hash);
  477. }
  478. #endif
  479. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  480. struct cdp_soc_attach_params *params)
  481. {
  482. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  483. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  484. uint32_t max_tx_rx_desc_num, num_spt_pages;
  485. uint32_t num_entries;
  486. int i = 0;
  487. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  488. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS;
  489. /* estimate how many SPT DDR pages needed */
  490. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  491. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  492. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  493. be_soc->page_desc_base = qdf_mem_malloc(
  494. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  495. if (!be_soc->page_desc_base) {
  496. dp_err("spt page descs allocation failed");
  497. return QDF_STATUS_E_NOMEM;
  498. }
  499. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  500. qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
  501. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  502. goto fail;
  503. dp_soc_mlo_fill_params(soc, params);
  504. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  505. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  506. qdf_status =
  507. dp_hw_cookie_conversion_attach(be_soc,
  508. &be_soc->tx_cc_ctx[i],
  509. num_entries,
  510. DP_TX_DESC_TYPE, i);
  511. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  512. goto fail;
  513. }
  514. qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
  515. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  516. goto fail;
  517. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  518. num_entries =
  519. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  520. qdf_status =
  521. dp_hw_cookie_conversion_attach(be_soc,
  522. &be_soc->rx_cc_ctx[i],
  523. num_entries,
  524. DP_RX_DESC_BUF_TYPE, i);
  525. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  526. goto fail;
  527. }
  528. return qdf_status;
  529. fail:
  530. dp_soc_detach_be(soc);
  531. return qdf_status;
  532. }
  533. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  534. {
  535. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  536. int i = 0;
  537. dp_tx_deinit_bank_profiles(be_soc);
  538. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  539. dp_hw_cookie_conversion_deinit(be_soc,
  540. &be_soc->tx_cc_ctx[i]);
  541. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  542. dp_hw_cookie_conversion_deinit(be_soc,
  543. &be_soc->rx_cc_ctx[i]);
  544. return QDF_STATUS_SUCCESS;
  545. }
  546. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  547. {
  548. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  549. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  550. int i = 0;
  551. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  552. qdf_status =
  553. dp_hw_cookie_conversion_init(be_soc,
  554. &be_soc->tx_cc_ctx[i]);
  555. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  556. goto fail;
  557. }
  558. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  559. qdf_status =
  560. dp_hw_cookie_conversion_init(be_soc,
  561. &be_soc->rx_cc_ctx[i]);
  562. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  563. goto fail;
  564. }
  565. /* route vdev_id mismatch notification via FW completion */
  566. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  567. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  568. qdf_status = dp_tx_init_bank_profiles(be_soc);
  569. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  570. goto fail;
  571. /* write WBM/REO cookie conversion CFG register */
  572. dp_cc_reg_cfg_init(soc, true);
  573. return qdf_status;
  574. fail:
  575. dp_soc_deinit_be(soc);
  576. return qdf_status;
  577. }
  578. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  579. struct cdp_pdev_attach_params *params)
  580. {
  581. dp_pdev_mlo_fill_params(pdev, params);
  582. dp_mlo_update_link_to_pdev_map(pdev->soc, pdev);
  583. return QDF_STATUS_SUCCESS;
  584. }
  585. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  586. {
  587. dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
  588. return QDF_STATUS_SUCCESS;
  589. }
  590. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  591. {
  592. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  593. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  594. struct dp_pdev *pdev = vdev->pdev;
  595. if (vdev->opmode == wlan_op_mode_monitor)
  596. return QDF_STATUS_SUCCESS;
  597. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  598. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  599. vdev->bank_id = be_vdev->bank_id;
  600. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  601. QDF_BUG(0);
  602. return QDF_STATUS_E_FAULT;
  603. }
  604. if (vdev->opmode == wlan_op_mode_sta) {
  605. if (soc->cdp_soc.ol_ops->set_mec_timer)
  606. soc->cdp_soc.ol_ops->set_mec_timer(
  607. soc->ctrl_psoc,
  608. vdev->vdev_id,
  609. DP_AST_AGING_TIMER_DEFAULT_MS);
  610. if (pdev->isolation)
  611. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  612. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  613. else
  614. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  615. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  616. }
  617. dp_mlo_mcast_init(soc, vdev);
  618. dp_mlo_init_ptnr_list(vdev);
  619. return QDF_STATUS_SUCCESS;
  620. }
  621. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  622. {
  623. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  624. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  625. if (vdev->opmode == wlan_op_mode_monitor)
  626. return QDF_STATUS_SUCCESS;
  627. if (vdev->opmode == wlan_op_mode_ap)
  628. dp_mlo_mcast_deinit(soc, vdev);
  629. dp_tx_put_bank_profile(be_soc, be_vdev);
  630. dp_clr_mlo_ptnr_list(soc, vdev);
  631. return QDF_STATUS_SUCCESS;
  632. }
  633. qdf_size_t dp_get_soc_context_size_be(void)
  634. {
  635. return sizeof(struct dp_soc_be);
  636. }
  637. #ifdef NO_RX_PKT_HDR_TLV
  638. /**
  639. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  640. * @soc: Common DP soc handle
  641. *
  642. * Return: QDF_STATUS
  643. */
  644. static QDF_STATUS
  645. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  646. {
  647. int i;
  648. int mac_id;
  649. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  650. struct dp_srng *rx_mac_srng;
  651. QDF_STATUS status = QDF_STATUS_SUCCESS;
  652. /*
  653. * In Beryllium chipset msdu_start, mpdu_end
  654. * and rx_attn are part of msdu_end/mpdu_start
  655. */
  656. htt_tlv_filter.msdu_start = 0;
  657. htt_tlv_filter.mpdu_end = 0;
  658. htt_tlv_filter.attention = 0;
  659. htt_tlv_filter.mpdu_start = 1;
  660. htt_tlv_filter.msdu_end = 1;
  661. htt_tlv_filter.packet = 1;
  662. htt_tlv_filter.packet_header = 0;
  663. htt_tlv_filter.ppdu_start = 0;
  664. htt_tlv_filter.ppdu_end = 0;
  665. htt_tlv_filter.ppdu_end_user_stats = 0;
  666. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  667. htt_tlv_filter.ppdu_end_status_done = 0;
  668. htt_tlv_filter.enable_fp = 1;
  669. htt_tlv_filter.enable_md = 0;
  670. htt_tlv_filter.enable_md = 0;
  671. htt_tlv_filter.enable_mo = 0;
  672. htt_tlv_filter.fp_mgmt_filter = 0;
  673. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  674. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  675. FILTER_DATA_MCAST |
  676. FILTER_DATA_DATA);
  677. htt_tlv_filter.mo_mgmt_filter = 0;
  678. htt_tlv_filter.mo_ctrl_filter = 0;
  679. htt_tlv_filter.mo_data_filter = 0;
  680. htt_tlv_filter.md_data_filter = 0;
  681. htt_tlv_filter.offset_valid = true;
  682. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  683. htt_tlv_filter.rx_mpdu_end_offset = 0;
  684. htt_tlv_filter.rx_msdu_start_offset = 0;
  685. htt_tlv_filter.rx_attn_offset = 0;
  686. /*
  687. * For monitor mode, the packet hdr tlv is enabled later during
  688. * filter update
  689. */
  690. if (soc->cdp_soc.ol_ops->get_con_mode &&
  691. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  692. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  693. else
  694. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  695. /*Not subscribing rx_pkt_header*/
  696. htt_tlv_filter.rx_header_offset = 0;
  697. htt_tlv_filter.rx_mpdu_start_offset =
  698. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  699. htt_tlv_filter.rx_msdu_end_offset =
  700. hal_rx_msdu_end_offset_get(soc->hal_soc);
  701. for (i = 0; i < MAX_PDEV_CNT; i++) {
  702. struct dp_pdev *pdev = soc->pdev_list[i];
  703. if (!pdev)
  704. continue;
  705. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  706. int mac_for_pdev =
  707. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  708. /*
  709. * Obtain lmac id from pdev to access the LMAC ring
  710. * in soc context
  711. */
  712. int lmac_id =
  713. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  714. pdev->pdev_id);
  715. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  716. if (!rx_mac_srng->hal_srng)
  717. continue;
  718. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  719. rx_mac_srng->hal_srng,
  720. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  721. &htt_tlv_filter);
  722. }
  723. }
  724. return status;
  725. }
  726. #else
  727. /**
  728. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  729. * @soc: Common DP soc handle
  730. *
  731. * Return: QDF_STATUS
  732. */
  733. static QDF_STATUS
  734. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  735. {
  736. int i;
  737. int mac_id;
  738. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  739. struct dp_srng *rx_mac_srng;
  740. QDF_STATUS status = QDF_STATUS_SUCCESS;
  741. /*
  742. * In Beryllium chipset msdu_start, mpdu_end
  743. * and rx_attn are part of msdu_end/mpdu_start
  744. */
  745. htt_tlv_filter.msdu_start = 0;
  746. htt_tlv_filter.mpdu_end = 0;
  747. htt_tlv_filter.attention = 0;
  748. htt_tlv_filter.mpdu_start = 1;
  749. htt_tlv_filter.msdu_end = 1;
  750. htt_tlv_filter.packet = 1;
  751. htt_tlv_filter.packet_header = 1;
  752. htt_tlv_filter.ppdu_start = 0;
  753. htt_tlv_filter.ppdu_end = 0;
  754. htt_tlv_filter.ppdu_end_user_stats = 0;
  755. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  756. htt_tlv_filter.ppdu_end_status_done = 0;
  757. htt_tlv_filter.enable_fp = 1;
  758. htt_tlv_filter.enable_md = 0;
  759. htt_tlv_filter.enable_md = 0;
  760. htt_tlv_filter.enable_mo = 0;
  761. htt_tlv_filter.fp_mgmt_filter = 0;
  762. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  763. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  764. FILTER_DATA_MCAST |
  765. FILTER_DATA_DATA);
  766. htt_tlv_filter.mo_mgmt_filter = 0;
  767. htt_tlv_filter.mo_ctrl_filter = 0;
  768. htt_tlv_filter.mo_data_filter = 0;
  769. htt_tlv_filter.md_data_filter = 0;
  770. htt_tlv_filter.offset_valid = true;
  771. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  772. htt_tlv_filter.rx_mpdu_end_offset = 0;
  773. htt_tlv_filter.rx_msdu_start_offset = 0;
  774. htt_tlv_filter.rx_attn_offset = 0;
  775. /*
  776. * For monitor mode, the packet hdr tlv is enabled later during
  777. * filter update
  778. */
  779. if (soc->cdp_soc.ol_ops->get_con_mode &&
  780. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  781. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  782. else
  783. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  784. htt_tlv_filter.rx_header_offset =
  785. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  786. htt_tlv_filter.rx_mpdu_start_offset =
  787. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  788. htt_tlv_filter.rx_msdu_end_offset =
  789. hal_rx_msdu_end_offset_get(soc->hal_soc);
  790. dp_info("TLV subscription\n"
  791. "msdu_start %d, mpdu_end %d, attention %d"
  792. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  793. "TLV offsets\n"
  794. "msdu_start %d, mpdu_end %d, attention %d"
  795. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  796. htt_tlv_filter.msdu_start,
  797. htt_tlv_filter.mpdu_end,
  798. htt_tlv_filter.attention,
  799. htt_tlv_filter.mpdu_start,
  800. htt_tlv_filter.msdu_end,
  801. htt_tlv_filter.packet_header,
  802. htt_tlv_filter.packet,
  803. htt_tlv_filter.rx_msdu_start_offset,
  804. htt_tlv_filter.rx_mpdu_end_offset,
  805. htt_tlv_filter.rx_attn_offset,
  806. htt_tlv_filter.rx_mpdu_start_offset,
  807. htt_tlv_filter.rx_msdu_end_offset,
  808. htt_tlv_filter.rx_header_offset,
  809. htt_tlv_filter.rx_packet_offset);
  810. for (i = 0; i < MAX_PDEV_CNT; i++) {
  811. struct dp_pdev *pdev = soc->pdev_list[i];
  812. if (!pdev)
  813. continue;
  814. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  815. int mac_for_pdev =
  816. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  817. /*
  818. * Obtain lmac id from pdev to access the LMAC ring
  819. * in soc context
  820. */
  821. int lmac_id =
  822. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  823. pdev->pdev_id);
  824. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  825. if (!rx_mac_srng->hal_srng)
  826. continue;
  827. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  828. rx_mac_srng->hal_srng,
  829. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  830. &htt_tlv_filter);
  831. }
  832. }
  833. return status;
  834. }
  835. #endif
  836. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  837. /**
  838. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  839. * near-full IRQs.
  840. * @soc: Datapath SoC handle
  841. * @int_ctx: Interrupt context
  842. * @dp_budget: Budget of the work that can be done in the bottom half
  843. *
  844. * Return: work done in the handler
  845. */
  846. static uint32_t
  847. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  848. uint32_t dp_budget)
  849. {
  850. int ring = 0;
  851. int budget = dp_budget;
  852. uint32_t work_done = 0;
  853. uint32_t remaining_quota = dp_budget;
  854. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  855. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  856. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  857. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  858. int rx_near_full_mask = rx_near_full_grp_1_mask |
  859. rx_near_full_grp_2_mask;
  860. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  861. rx_near_full_mask,
  862. tx_ring_near_full_mask);
  863. if (rx_near_full_mask) {
  864. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  865. if (!(rx_near_full_mask & (1 << ring)))
  866. continue;
  867. work_done = dp_rx_nf_process(int_ctx,
  868. soc->reo_dest_ring[ring].hal_srng,
  869. ring, remaining_quota);
  870. if (work_done) {
  871. intr_stats->num_rx_ring_near_full_masks[ring]++;
  872. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  873. rx_near_full_mask, ring,
  874. work_done,
  875. budget);
  876. budget -= work_done;
  877. if (budget <= 0)
  878. goto budget_done;
  879. remaining_quota = budget;
  880. }
  881. }
  882. }
  883. if (tx_ring_near_full_mask) {
  884. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  885. if (!(tx_ring_near_full_mask & (1 << ring)))
  886. continue;
  887. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  888. soc->tx_comp_ring[ring].hal_srng,
  889. ring, remaining_quota);
  890. if (work_done) {
  891. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  892. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  893. tx_ring_near_full_mask, ring,
  894. work_done, budget);
  895. budget -= work_done;
  896. if (budget <= 0)
  897. break;
  898. remaining_quota = budget;
  899. }
  900. }
  901. }
  902. intr_stats->num_near_full_masks++;
  903. budget_done:
  904. return dp_budget - budget;
  905. }
  906. /**
  907. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  908. * state and set the reap_limit appropriately
  909. * as per the near full state
  910. * @soc: Datapath soc handle
  911. * @dp_srng: Datapath handle for SRNG
  912. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  913. * the srng near-full state
  914. *
  915. * Return: 1, if the srng is in near-full state
  916. * 0, if the srng is not in near-full state
  917. */
  918. static int
  919. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  920. struct dp_srng *dp_srng,
  921. int *max_reap_limit)
  922. {
  923. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  924. }
  925. /**
  926. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  927. * near full IRQ handling operations.
  928. * @arch_ops: arch ops handle
  929. *
  930. * Return: none
  931. */
  932. static inline void
  933. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  934. {
  935. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  936. arch_ops->dp_srng_test_and_update_nf_params =
  937. dp_srng_test_and_update_nf_params_be;
  938. }
  939. #else
  940. static inline void
  941. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  942. {
  943. }
  944. #endif
  945. #ifdef WLAN_SUPPORT_PPEDS
  946. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  947. {
  948. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  949. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  950. soc_cfg_ctx = soc->wlan_cfg_ctx;
  951. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  952. return;
  953. dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0);
  954. wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned,
  955. be_soc->ppe_release_ring.alloc_size,
  956. soc->ctrl_psoc,
  957. WLAN_MD_DP_SRNG_PPE_RELEASE,
  958. "ppe_release_ring");
  959. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  960. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  961. be_soc->ppe2tcl_ring.alloc_size,
  962. soc->ctrl_psoc,
  963. WLAN_MD_DP_SRNG_PPE2TCL,
  964. "ppe2tcl_ring");
  965. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  966. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  967. be_soc->reo2ppe_ring.alloc_size,
  968. soc->ctrl_psoc,
  969. WLAN_MD_DP_SRNG_REO2PPE,
  970. "reo2ppe_ring");
  971. }
  972. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  973. {
  974. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  975. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  976. soc_cfg_ctx = soc->wlan_cfg_ctx;
  977. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  978. return;
  979. dp_srng_free(soc, &be_soc->ppe_release_ring);
  980. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  981. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  982. }
  983. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  984. {
  985. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  986. uint32_t entries;
  987. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  988. soc_cfg_ctx = soc->wlan_cfg_ctx;
  989. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  990. return QDF_STATUS_SUCCESS;
  991. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  992. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  993. entries, 0)) {
  994. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  995. goto fail;
  996. }
  997. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  998. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  999. entries, 0)) {
  1000. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  1001. goto fail;
  1002. }
  1003. entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx);
  1004. if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE,
  1005. entries, 0)) {
  1006. dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc);
  1007. goto fail;
  1008. }
  1009. return QDF_STATUS_SUCCESS;
  1010. fail:
  1011. dp_soc_ppe_srng_free(soc);
  1012. return QDF_STATUS_E_NOMEM;
  1013. }
  1014. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  1015. {
  1016. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1017. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1018. hal_soc_handle_t hal_soc = soc->hal_soc;
  1019. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1020. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  1021. return QDF_STATUS_SUCCESS;
  1022. if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) {
  1023. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  1024. goto fail;
  1025. }
  1026. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1027. be_soc->reo2ppe_ring.alloc_size,
  1028. soc->ctrl_psoc,
  1029. WLAN_MD_DP_SRNG_REO2PPE,
  1030. "reo2ppe_ring");
  1031. hal_reo_config_reo2ppe_dest_info(hal_soc);
  1032. if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) {
  1033. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  1034. goto fail;
  1035. }
  1036. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1037. be_soc->ppe2tcl_ring.alloc_size,
  1038. soc->ctrl_psoc,
  1039. WLAN_MD_DP_SRNG_PPE2TCL,
  1040. "ppe2tcl_ring");
  1041. if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) {
  1042. dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc);
  1043. goto fail;
  1044. }
  1045. wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned,
  1046. be_soc->ppe_release_ring.alloc_size,
  1047. soc->ctrl_psoc,
  1048. WLAN_MD_DP_SRNG_PPE_RELEASE,
  1049. "ppe_release_ring");
  1050. return QDF_STATUS_SUCCESS;
  1051. fail:
  1052. dp_soc_ppe_srng_deinit(soc);
  1053. return QDF_STATUS_E_NOMEM;
  1054. }
  1055. #else
  1056. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  1057. {
  1058. }
  1059. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  1060. {
  1061. }
  1062. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  1063. {
  1064. return QDF_STATUS_SUCCESS;
  1065. }
  1066. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  1067. {
  1068. return QDF_STATUS_SUCCESS;
  1069. }
  1070. #endif
  1071. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1072. {
  1073. uint32_t i;
  1074. dp_soc_ppe_srng_deinit(soc);
  1075. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1076. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1077. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1078. RXDMA_BUF, 0);
  1079. }
  1080. }
  1081. }
  1082. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1083. {
  1084. uint32_t i;
  1085. dp_soc_ppe_srng_free(soc);
  1086. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1087. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1088. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1089. }
  1090. }
  1091. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1092. {
  1093. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1094. uint32_t ring_size;
  1095. uint32_t i;
  1096. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1097. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1098. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1099. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1100. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1101. RXDMA_BUF, ring_size, 0)) {
  1102. dp_err("%pK: dp_srng_alloc failed refill ring",
  1103. soc);
  1104. goto fail;
  1105. }
  1106. }
  1107. }
  1108. if (dp_soc_ppe_srng_alloc(soc)) {
  1109. dp_err("%pK: ppe rings alloc failed",
  1110. soc);
  1111. goto fail;
  1112. }
  1113. return QDF_STATUS_SUCCESS;
  1114. fail:
  1115. dp_soc_srng_free_be(soc);
  1116. return QDF_STATUS_E_NOMEM;
  1117. }
  1118. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1119. {
  1120. int i = 0;
  1121. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1122. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1123. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1124. RXDMA_BUF, 0, 0)) {
  1125. dp_err("%pK: dp_srng_init failed refill ring",
  1126. soc);
  1127. goto fail;
  1128. }
  1129. }
  1130. }
  1131. if (dp_soc_ppe_srng_init(soc)) {
  1132. dp_err("%pK: ppe rings init failed",
  1133. soc);
  1134. goto fail;
  1135. }
  1136. return QDF_STATUS_SUCCESS;
  1137. fail:
  1138. dp_soc_srng_deinit_be(soc);
  1139. return QDF_STATUS_E_NOMEM;
  1140. }
  1141. #ifdef WLAN_FEATURE_11BE_MLO
  1142. static inline unsigned
  1143. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1144. union dp_align_mac_addr *mac_addr)
  1145. {
  1146. uint32_t index;
  1147. index =
  1148. mac_addr->align2.bytes_ab ^
  1149. mac_addr->align2.bytes_cd ^
  1150. mac_addr->align2.bytes_ef;
  1151. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1152. index &= mld_hash_obj->mld_peer_hash.mask;
  1153. return index;
  1154. }
  1155. QDF_STATUS
  1156. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1157. int hash_elems)
  1158. {
  1159. int i, log2;
  1160. if (!mld_hash_obj)
  1161. return QDF_STATUS_E_FAILURE;
  1162. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1163. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1164. log2 = dp_log2_ceil(hash_elems);
  1165. hash_elems = 1 << log2;
  1166. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1167. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1168. /* allocate an array of TAILQ peer object lists */
  1169. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1170. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1171. if (!mld_hash_obj->mld_peer_hash.bins)
  1172. return QDF_STATUS_E_NOMEM;
  1173. for (i = 0; i < hash_elems; i++)
  1174. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1175. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1176. return QDF_STATUS_SUCCESS;
  1177. }
  1178. void
  1179. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1180. {
  1181. if (!mld_hash_obj)
  1182. return;
  1183. if (mld_hash_obj->mld_peer_hash.bins) {
  1184. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1185. mld_hash_obj->mld_peer_hash.bins = NULL;
  1186. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1187. }
  1188. }
  1189. #ifdef WLAN_MLO_MULTI_CHIP
  1190. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1191. {
  1192. /* In case of MULTI chip MLO peer hash table when MLO global object
  1193. * is created, avoid from SOC attach path
  1194. */
  1195. return QDF_STATUS_SUCCESS;
  1196. }
  1197. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1198. {
  1199. }
  1200. #else
  1201. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1202. {
  1203. dp_mld_peer_hash_obj_t mld_hash_obj;
  1204. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1205. if (!mld_hash_obj)
  1206. return QDF_STATUS_E_FAILURE;
  1207. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1208. }
  1209. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1210. {
  1211. dp_mld_peer_hash_obj_t mld_hash_obj;
  1212. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1213. if (!mld_hash_obj)
  1214. return;
  1215. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1216. }
  1217. #endif
  1218. static struct dp_peer *
  1219. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1220. uint8_t *peer_mac_addr,
  1221. int mac_addr_is_aligned,
  1222. enum dp_mod_id mod_id,
  1223. uint8_t vdev_id)
  1224. {
  1225. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1226. uint32_t index;
  1227. struct dp_peer *peer;
  1228. struct dp_vdev *vdev;
  1229. dp_mld_peer_hash_obj_t mld_hash_obj;
  1230. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1231. if (!mld_hash_obj)
  1232. return NULL;
  1233. if (!mld_hash_obj->mld_peer_hash.bins)
  1234. return NULL;
  1235. if (mac_addr_is_aligned) {
  1236. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1237. } else {
  1238. qdf_mem_copy(
  1239. &local_mac_addr_aligned.raw[0],
  1240. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1241. mac_addr = &local_mac_addr_aligned;
  1242. }
  1243. if (vdev_id != DP_VDEV_ALL) {
  1244. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1245. if (!vdev) {
  1246. dp_err("vdev is null\n");
  1247. return NULL;
  1248. }
  1249. } else {
  1250. vdev = NULL;
  1251. }
  1252. /* search mld peer table if no link peer for given mac address */
  1253. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1254. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1255. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1256. hash_list_elem) {
  1257. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1258. if ((vdev_id == DP_VDEV_ALL) || (
  1259. dp_peer_find_mac_addr_cmp(
  1260. &peer->vdev->mld_mac_addr,
  1261. &vdev->mld_mac_addr) == 0)) {
  1262. /* take peer reference before returning */
  1263. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1264. QDF_STATUS_SUCCESS)
  1265. peer = NULL;
  1266. if (vdev)
  1267. dp_vdev_unref_delete(soc, vdev, mod_id);
  1268. qdf_spin_unlock_bh(
  1269. &mld_hash_obj->mld_peer_hash_lock);
  1270. return peer;
  1271. }
  1272. }
  1273. }
  1274. if (vdev)
  1275. dp_vdev_unref_delete(soc, vdev, mod_id);
  1276. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1277. return NULL; /* failure */
  1278. }
  1279. static void
  1280. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1281. {
  1282. uint32_t index;
  1283. struct dp_peer *tmppeer = NULL;
  1284. int found = 0;
  1285. dp_mld_peer_hash_obj_t mld_hash_obj;
  1286. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1287. if (!mld_hash_obj)
  1288. return;
  1289. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1290. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1291. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1292. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1293. hash_list_elem) {
  1294. if (tmppeer == peer) {
  1295. found = 1;
  1296. break;
  1297. }
  1298. }
  1299. QDF_ASSERT(found);
  1300. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1301. hash_list_elem);
  1302. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1303. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1304. }
  1305. static void
  1306. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1307. {
  1308. uint32_t index;
  1309. dp_mld_peer_hash_obj_t mld_hash_obj;
  1310. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1311. if (!mld_hash_obj)
  1312. return;
  1313. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1314. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1315. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1316. DP_MOD_ID_CONFIG))) {
  1317. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1318. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1319. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1320. return;
  1321. }
  1322. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1323. hash_list_elem);
  1324. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1325. }
  1326. void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
  1327. {
  1328. uint32_t index;
  1329. struct dp_peer *peer;
  1330. dp_mld_peer_hash_obj_t mld_hash_obj;
  1331. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1332. if (!mld_hash_obj)
  1333. return;
  1334. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1335. for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
  1336. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1337. hash_list_elem) {
  1338. dp_print_peer_ast_entries(soc, peer, NULL);
  1339. }
  1340. }
  1341. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1342. }
  1343. #endif
  1344. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1345. static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
  1346. struct dp_vdev *vdev)
  1347. {
  1348. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1349. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1350. hal_soc_handle_t hal_soc = soc->hal_soc;
  1351. uint8_t vdev_id = vdev->vdev_id;
  1352. if (vdev->opmode == wlan_op_mode_sta) {
  1353. if (vdev->pdev->isolation)
  1354. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1355. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1356. else
  1357. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1358. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  1359. } else if (vdev->opmode == wlan_op_mode_ap) {
  1360. if (vdev->mlo_vdev) {
  1361. if (be_vdev->mcast_primary) {
  1362. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1363. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1364. hal_tx_vdev_mcast_ctrl_set(hal_soc,
  1365. vdev_id + 128,
  1366. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1367. dp_mcast_mlo_iter_ptnr_soc(be_soc,
  1368. dp_tx_mcast_mlo_reinject_routing_set,
  1369. (void *)&be_vdev->mcast_primary);
  1370. } else {
  1371. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1372. HAL_TX_MCAST_CTRL_DROP);
  1373. }
  1374. } else {
  1375. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  1376. vdev_id,
  1377. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1378. }
  1379. }
  1380. }
  1381. static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
  1382. {
  1383. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1384. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1385. union hal_tx_bank_config *bank_config;
  1386. if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
  1387. return;
  1388. bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
  1389. hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
  1390. be_vdev->bank_id);
  1391. }
  1392. #endif
  1393. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1394. defined(WLAN_MCAST_MLO)
  1395. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1396. struct dp_vdev_be *be_vdev,
  1397. cdp_config_param_type val)
  1398. {
  1399. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1400. be_vdev->vdev.pdev->soc);
  1401. hal_soc_handle_t hal_soc = be_vdev->vdev.pdev->soc->hal_soc;
  1402. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  1403. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1404. if (be_vdev->mcast_primary) {
  1405. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1406. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1407. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id + 128,
  1408. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1409. dp_mcast_mlo_iter_ptnr_soc(be_soc,
  1410. dp_tx_mcast_mlo_reinject_routing_set,
  1411. (void *)&be_vdev->mcast_primary);
  1412. } else {
  1413. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1414. HAL_TX_MCAST_CTRL_DROP);
  1415. }
  1416. }
  1417. #else
  1418. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1419. struct dp_vdev_be *be_vdev,
  1420. cdp_config_param_type val)
  1421. {
  1422. }
  1423. #endif
  1424. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1425. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1426. uint8_t tx_ring_id,
  1427. uint8_t bm_id)
  1428. {
  1429. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1430. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1431. bm_id);
  1432. }
  1433. #else
  1434. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1435. uint8_t tx_ring_id,
  1436. uint8_t bm_id)
  1437. {
  1438. }
  1439. #endif
  1440. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  1441. struct dp_vdev *vdev,
  1442. enum cdp_vdev_param_type param,
  1443. cdp_config_param_type val)
  1444. {
  1445. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1446. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1447. switch (param) {
  1448. case CDP_TX_ENCAP_TYPE:
  1449. case CDP_UPDATE_DSCP_TO_TID_MAP:
  1450. case CDP_UPDATE_TDLS_FLAGS:
  1451. dp_tx_update_bank_profile(be_soc, be_vdev);
  1452. break;
  1453. case CDP_ENABLE_CIPHER:
  1454. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  1455. dp_tx_update_bank_profile(be_soc, be_vdev);
  1456. break;
  1457. case CDP_SET_MCAST_VDEV:
  1458. dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val);
  1459. break;
  1460. default:
  1461. dp_warn("invalid param %d", param);
  1462. break;
  1463. }
  1464. return QDF_STATUS_SUCCESS;
  1465. }
  1466. #ifdef WLAN_FEATURE_11BE_MLO
  1467. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  1468. static inline void
  1469. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1470. {
  1471. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  1472. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  1473. /*
  1474. * Double the peers since we use ML indication bit
  1475. * alongwith peer_id to find peers.
  1476. */
  1477. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  1478. }
  1479. #else
  1480. static inline void
  1481. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1482. {
  1483. soc->max_peer_id =
  1484. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  1485. }
  1486. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  1487. #else
  1488. static inline void
  1489. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1490. {
  1491. soc->max_peer_id = soc->max_peers;
  1492. }
  1493. #endif /* WLAN_FEATURE_11BE_MLO */
  1494. static void dp_peer_map_detach_be(struct dp_soc *soc)
  1495. {
  1496. if (soc->host_ast_db_enable)
  1497. dp_peer_ast_hash_detach(soc);
  1498. }
  1499. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  1500. {
  1501. QDF_STATUS status;
  1502. if (soc->host_ast_db_enable) {
  1503. status = dp_peer_ast_hash_attach(soc);
  1504. if (QDF_IS_STATUS_ERROR(status))
  1505. return status;
  1506. }
  1507. dp_soc_max_peer_id_set(soc);
  1508. return QDF_STATUS_SUCCESS;
  1509. }
  1510. static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
  1511. uint8_t *dest_mac,
  1512. uint8_t vdev_id)
  1513. {
  1514. struct dp_peer *peer = NULL;
  1515. struct dp_peer *tgt_peer = NULL;
  1516. struct dp_ast_entry *ast_entry = NULL;
  1517. uint16_t peer_id;
  1518. qdf_spin_lock_bh(&soc->ast_lock);
  1519. ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac);
  1520. if (!ast_entry) {
  1521. qdf_spin_unlock_bh(&soc->ast_lock);
  1522. dp_err("NULL ast entry");
  1523. return NULL;
  1524. }
  1525. peer_id = ast_entry->peer_id;
  1526. qdf_spin_unlock_bh(&soc->ast_lock);
  1527. if (peer_id == HTT_INVALID_PEER)
  1528. return NULL;
  1529. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF);
  1530. if (!peer) {
  1531. dp_err("NULL peer for peer_id:%d", peer_id);
  1532. return NULL;
  1533. }
  1534. tgt_peer = dp_get_tgt_peer_from_peer(peer);
  1535. /*
  1536. * Once tgt_peer is obtained,
  1537. * release the ref taken for original peer.
  1538. */
  1539. dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF);
  1540. dp_peer_unref_delete(peer, DP_MOD_ID_SAWF);
  1541. return tgt_peer;
  1542. }
  1543. #ifdef WLAN_FEATURE_11BE_MLO
  1544. #ifdef WLAN_MCAST_MLO
  1545. static inline void
  1546. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1547. {
  1548. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  1549. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  1550. }
  1551. #else /* WLAN_MCAST_MLO */
  1552. static inline void
  1553. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1554. {
  1555. }
  1556. #endif /* WLAN_MCAST_MLO */
  1557. #ifdef WLAN_MLO_MULTI_CHIP
  1558. static inline void
  1559. dp_initialize_arch_ops_be_mlo_ptnr_chip(struct dp_arch_ops *arch_ops)
  1560. {
  1561. arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
  1562. arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
  1563. }
  1564. #else
  1565. static inline void
  1566. dp_initialize_arch_ops_be_mlo_ptnr_chip(struct dp_arch_ops *arch_ops)
  1567. {
  1568. }
  1569. #endif
  1570. static inline void
  1571. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1572. {
  1573. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  1574. dp_initialize_arch_ops_be_mlo_ptnr_chip(arch_ops);
  1575. arch_ops->mlo_peer_find_hash_detach =
  1576. dp_mlo_peer_find_hash_detach_wrapper;
  1577. arch_ops->mlo_peer_find_hash_attach =
  1578. dp_mlo_peer_find_hash_attach_wrapper;
  1579. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  1580. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  1581. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  1582. }
  1583. #else /* WLAN_FEATURE_11BE_MLO */
  1584. static inline void
  1585. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1586. {
  1587. }
  1588. #endif /* WLAN_FEATURE_11BE_MLO */
  1589. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  1590. #define DP_LMAC_PEER_ID_MSB_LEGACY 2
  1591. #define DP_LMAC_PEER_ID_MSB_MLO 3
  1592. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1593. struct cdp_peer_setup_info *setup_info,
  1594. enum cdp_host_reo_dest_ring *reo_dest,
  1595. bool *hash_based,
  1596. uint8_t *lmac_peer_id_msb)
  1597. {
  1598. struct dp_soc *soc = vdev->pdev->soc;
  1599. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1600. if (!be_soc->mlo_enabled)
  1601. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  1602. hash_based);
  1603. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  1604. *reo_dest = vdev->pdev->reo_dest;
  1605. /* Not a ML link peer use non-mlo */
  1606. if (!setup_info) {
  1607. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  1608. return;
  1609. }
  1610. /* For STA ML VAP we do not have num links info at this point
  1611. * use MLO case always
  1612. */
  1613. if (vdev->opmode == wlan_op_mode_sta) {
  1614. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  1615. return;
  1616. }
  1617. /* For AP ML VAP consider the peer as ML only it associates with
  1618. * multiple links
  1619. */
  1620. if (setup_info->num_links == 1) {
  1621. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  1622. return;
  1623. }
  1624. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  1625. }
  1626. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1627. uint32_t *remap0,
  1628. uint32_t *remap1,
  1629. uint32_t *remap2)
  1630. {
  1631. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1632. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  1633. uint32_t reo_mlo_config =
  1634. wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
  1635. if (!be_soc->mlo_enabled)
  1636. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1637. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  1638. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
  1639. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  1640. return true;
  1641. }
  1642. #else
  1643. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1644. struct cdp_peer_setup_info *setup_info,
  1645. enum cdp_host_reo_dest_ring *reo_dest,
  1646. bool *hash_based,
  1647. uint8_t *lmac_peer_id_msb)
  1648. {
  1649. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  1650. }
  1651. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1652. uint32_t *remap0,
  1653. uint32_t *remap1,
  1654. uint32_t *remap2)
  1655. {
  1656. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1657. }
  1658. #endif
  1659. #ifdef IPA_OFFLOAD
  1660. static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc)
  1661. {
  1662. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1663. return be_soc->ipa_bank_id;
  1664. }
  1665. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  1666. {
  1667. arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be;
  1668. }
  1669. #else /* !IPA_OFFLOAD */
  1670. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  1671. {
  1672. }
  1673. #endif /* IPA_OFFLOAD */
  1674. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  1675. {
  1676. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1677. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  1678. arch_ops->dp_rx_process = dp_rx_process_be;
  1679. arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
  1680. arch_ops->tx_comp_get_params_from_hal_desc =
  1681. dp_tx_comp_get_params_from_hal_desc_be;
  1682. arch_ops->dp_tx_process_htt_completion =
  1683. dp_tx_process_htt_completion_be;
  1684. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  1685. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  1686. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  1687. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  1688. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  1689. dp_wbm_get_rx_desc_from_hal_desc_be;
  1690. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
  1691. #endif
  1692. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  1693. #ifdef WIFI_MONITOR_SUPPORT
  1694. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  1695. #endif
  1696. arch_ops->dp_rx_desc_cookie_2_va =
  1697. dp_rx_desc_cookie_2_va_be;
  1698. arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
  1699. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  1700. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  1701. arch_ops->txrx_soc_init = dp_soc_init_be;
  1702. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  1703. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  1704. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  1705. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  1706. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  1707. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  1708. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  1709. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  1710. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  1711. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  1712. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  1713. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  1714. arch_ops->dp_rx_peer_metadata_peer_id_get =
  1715. dp_rx_peer_metadata_peer_id_get_be;
  1716. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  1717. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  1718. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  1719. dp_initialize_arch_ops_be_mlo(arch_ops);
  1720. arch_ops->dp_peer_rx_reorder_queue_setup =
  1721. dp_peer_rx_reorder_queue_setup_be;
  1722. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  1723. arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
  1724. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1725. arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
  1726. arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
  1727. dp_reconfig_tx_vdev_mcast_ctrl_be;
  1728. arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
  1729. #endif
  1730. #ifdef WLAN_SUPPORT_PPEDS
  1731. arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status;
  1732. #else
  1733. arch_ops->dp_txrx_ppeds_rings_status = NULL;
  1734. #endif
  1735. dp_init_near_full_arch_ops_be(arch_ops);
  1736. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
  1737. arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
  1738. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  1739. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  1740. dp_initialize_arch_ops_be_ipa(arch_ops);
  1741. }