main.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #ifndef _CNSS_MAIN_H
  7. #define _CNSS_MAIN_H
  8. #if IS_ENABLED(CONFIG_ARM) || IS_ENABLED(CONFIG_ARM64)
  9. #include <asm/arch_timer.h>
  10. #endif
  11. #if IS_ENABLED(CONFIG_ESOC)
  12. #include <linux/esoc_client.h>
  13. #endif
  14. #include <linux/etherdevice.h>
  15. #include <linux/firmware.h>
  16. #if IS_ENABLED(CONFIG_INTERCONNECT)
  17. #include <linux/interconnect.h>
  18. #endif
  19. #include <linux/mailbox_client.h>
  20. #include <linux/pm_qos.h>
  21. #include <linux/of.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/time64.h>
  24. #if IS_ENABLED(CONFIG_MSM_QMP)
  25. #include <linux/mailbox/qmp.h>
  26. #endif
  27. #ifdef CONFIG_CNSS_OUT_OF_TREE
  28. #include "cnss2.h"
  29. #else
  30. #include <net/cnss2.h>
  31. #endif
  32. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2) || IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  33. #include <soc/qcom/memory_dump.h>
  34. #endif
  35. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART) || \
  36. IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  37. #include <soc/qcom/qcom_ramdump.h>
  38. #endif
  39. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  40. #include <soc/qcom/subsystem_notif.h>
  41. #include <soc/qcom/subsystem_restart.h>
  42. #endif
  43. #include <linux/iommu.h>
  44. #include "qmi.h"
  45. #include "cnss_prealloc.h"
  46. #include "cnss_common.h"
  47. #define MAX_NO_OF_MAC_ADDR 4
  48. #define QMI_WLFW_MAX_TIMESTAMP_LEN 32
  49. #define QMI_WLFW_MAX_BUILD_ID_LEN 128
  50. #define CNSS_RDDM_TIMEOUT_MS 20000
  51. #define RECOVERY_TIMEOUT 60000
  52. #define WLAN_WD_TIMEOUT_MS 60000
  53. #define WLAN_COLD_BOOT_CAL_TIMEOUT 60000
  54. #define WLAN_MISSION_MODE_TIMEOUT 30000
  55. #define TIME_CLOCK_FREQ_HZ 19200000
  56. #define CNSS_RAMDUMP_MAGIC 0x574C414E
  57. #define CNSS_RAMDUMP_VERSION 0
  58. #define MAX_FIRMWARE_NAME_LEN 40
  59. #define FW_V1_NUMBER 1
  60. #define FW_V2_NUMBER 2
  61. #ifdef CONFIG_CNSS_SUPPORT_DUAL_DEV
  62. #define POWER_ON_RETRY_MAX_TIMES 2
  63. #else
  64. #define POWER_ON_RETRY_MAX_TIMES 4
  65. #endif
  66. #define POWER_ON_RETRY_DELAY_MS 500
  67. #define CNSS_FS_NAME "cnss"
  68. #define CNSS_FS_NAME_SIZE 15
  69. #define CNSS_DEVICE_NAME_SIZE 16
  70. #define QRTR_NODE_FW_ID_BASE 7
  71. #define POWER_ON_RETRY_DELAY_MS 500
  72. #define WLFW_MAX_HANG_EVENT_DATA_SIZE 384
  73. #define CNSS_EVENT_SYNC BIT(0)
  74. #define CNSS_EVENT_UNINTERRUPTIBLE BIT(1)
  75. #define CNSS_EVENT_UNKILLABLE BIT(2)
  76. #define CNSS_EVENT_SYNC_UNINTERRUPTIBLE (CNSS_EVENT_SYNC | \
  77. CNSS_EVENT_UNINTERRUPTIBLE)
  78. #define CNSS_EVENT_SYNC_UNKILLABLE (CNSS_EVENT_SYNC | CNSS_EVENT_UNKILLABLE)
  79. #define QMI_WLFW_MAX_TME_OPT_FILE_NUM 3
  80. #define TME_OEM_FUSE_FILE_NAME "peach_sec.dat"
  81. #define TME_RPR_FILE_NAME "peach_rpr.bin"
  82. #define TME_DPR_FILE_NAME "peach_dpr.bin"
  83. enum cnss_dt_type {
  84. CNSS_DTT_LEGACY = 0,
  85. CNSS_DTT_CONVERGED = 1,
  86. CNSS_DTT_MULTIEXCHG = 2
  87. };
  88. enum cnss_dev_bus_type {
  89. CNSS_BUS_NONE = -1,
  90. CNSS_BUS_PCI,
  91. CNSS_BUS_MAX
  92. };
  93. struct cnss_vreg_cfg {
  94. const char *name;
  95. u32 min_uv;
  96. u32 max_uv;
  97. u32 load_ua;
  98. u32 delay_us;
  99. u32 need_unvote;
  100. };
  101. struct cnss_vreg_info {
  102. struct list_head list;
  103. struct regulator *reg;
  104. struct cnss_vreg_cfg cfg;
  105. u32 enabled;
  106. };
  107. enum cnss_vreg_type {
  108. CNSS_VREG_PRIM,
  109. };
  110. struct cnss_clk_cfg {
  111. const char *name;
  112. u32 freq;
  113. u32 required;
  114. };
  115. struct cnss_clk_info {
  116. struct list_head list;
  117. struct clk *clk;
  118. struct cnss_clk_cfg cfg;
  119. u32 enabled;
  120. };
  121. struct cnss_pinctrl_info {
  122. struct pinctrl *pinctrl;
  123. struct pinctrl_state *bootstrap_active;
  124. struct pinctrl_state *sol_default;
  125. struct pinctrl_state *wlan_en_active;
  126. struct pinctrl_state *wlan_en_sleep;
  127. struct pinctrl_state *sw_ctrl;
  128. struct pinctrl_state *sw_ctrl_wl_cx;
  129. int bt_en_gpio;
  130. int wlan_en_gpio;
  131. int xo_clk_gpio; /*qca6490 only */
  132. int sw_ctrl_gpio;
  133. int wlan_sw_ctrl_gpio;
  134. };
  135. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  136. struct cnss_subsys_info {
  137. struct subsys_device *subsys_device;
  138. struct subsys_desc subsys_desc;
  139. void *subsys_handle;
  140. };
  141. #endif
  142. struct cnss_ramdump_info {
  143. void *ramdump_dev;
  144. unsigned long ramdump_size;
  145. void *ramdump_va;
  146. phys_addr_t ramdump_pa;
  147. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  148. struct msm_dump_data dump_data;
  149. #endif
  150. };
  151. struct cnss_dump_seg {
  152. unsigned long address;
  153. void *v_address;
  154. unsigned long size;
  155. u32 type;
  156. };
  157. struct cnss_dump_data {
  158. u32 version;
  159. u32 magic;
  160. char name[32];
  161. phys_addr_t paddr;
  162. int nentries;
  163. u32 seg_version;
  164. };
  165. struct cnss_ramdump_info_v2 {
  166. void *ramdump_dev;
  167. unsigned long ramdump_size;
  168. void *dump_data_vaddr;
  169. u8 dump_data_valid;
  170. struct cnss_dump_data dump_data;
  171. };
  172. #if IS_ENABLED(CONFIG_ESOC)
  173. struct cnss_esoc_info {
  174. struct esoc_desc *esoc_desc;
  175. u8 notify_modem_status;
  176. void *modem_notify_handler;
  177. int modem_current_status;
  178. };
  179. #endif
  180. #if IS_ENABLED(CONFIG_INTERCONNECT)
  181. /**
  182. * struct cnss_bus_bw_cfg - Interconnect vote data
  183. * @avg_bw: Vote for average bandwidth
  184. * @peak_bw: Vote for peak bandwidth
  185. */
  186. struct cnss_bus_bw_cfg {
  187. u32 avg_bw;
  188. u32 peak_bw;
  189. };
  190. /* Number of bw votes (avg, peak) entries that ICC requires */
  191. #define CNSS_ICC_VOTE_MAX 2
  192. /**
  193. * struct cnss_bus_bw_info - Bus bandwidth config for interconnect path
  194. * @list: Kernel linked list
  195. * @icc_name: Name of interconnect path as defined in Device tree
  196. * @icc_path: Interconnect path data structure
  197. * @cfg_table: Interconnect vote data for average and peak bandwidth
  198. */
  199. struct cnss_bus_bw_info {
  200. struct list_head list;
  201. const char *icc_name;
  202. struct icc_path *icc_path;
  203. struct cnss_bus_bw_cfg *cfg_table;
  204. };
  205. #endif
  206. /**
  207. * struct cnss_interconnect_cfg - CNSS platform interconnect config
  208. * @list_head: List of interconnect path bandwidth configs
  209. * @path_count: Count of interconnect path configured in device tree
  210. * @current_bw_vote: WLAN driver provided bandwidth vote
  211. * @bus_bw_cfg_count: Number of bandwidth configs for voting. It is the array
  212. * size of struct cnss_bus_bw_info.cfg_table
  213. */
  214. struct cnss_interconnect_cfg {
  215. struct list_head list_head;
  216. u32 path_count;
  217. int current_bw_vote;
  218. u32 bus_bw_cfg_count;
  219. };
  220. struct cnss_fw_mem {
  221. size_t size;
  222. void *va;
  223. phys_addr_t pa;
  224. u8 valid;
  225. u32 type;
  226. unsigned long attrs;
  227. };
  228. struct wlfw_rf_chip_info {
  229. u32 chip_id;
  230. u32 chip_family;
  231. };
  232. struct wlfw_rf_board_info {
  233. u32 board_id;
  234. };
  235. struct wlfw_soc_info {
  236. u32 soc_id;
  237. };
  238. struct wlfw_fw_version_info {
  239. u32 fw_version;
  240. char fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN + 1];
  241. };
  242. enum cnss_mem_type {
  243. CNSS_MEM_TYPE_MSA,
  244. CNSS_MEM_TYPE_DDR,
  245. CNSS_MEM_BDF,
  246. CNSS_MEM_M3,
  247. CNSS_MEM_CAL_V01,
  248. CNSS_MEM_DPD_V01,
  249. CNSS_MEM_AUX,
  250. };
  251. enum cnss_fw_dump_type {
  252. CNSS_FW_IMAGE,
  253. CNSS_FW_RDDM,
  254. CNSS_FW_REMOTE_HEAP,
  255. CNSS_FW_CAL,
  256. CNSS_FW_DUMP_TYPE_MAX,
  257. };
  258. struct cnss_dump_entry {
  259. int type;
  260. u32 entry_start;
  261. u32 entry_num;
  262. };
  263. struct cnss_dump_meta_info {
  264. u32 magic;
  265. u32 version;
  266. u32 chipset;
  267. u32 total_entries;
  268. struct cnss_dump_entry entry[CNSS_FW_DUMP_TYPE_MAX];
  269. };
  270. struct cnss_host_dump_meta_info {
  271. u32 magic;
  272. u32 version;
  273. u32 chipset;
  274. u32 total_entries;
  275. struct cnss_dump_entry entry[CNSS_HOST_DUMP_TYPE_MAX];
  276. };
  277. enum cnss_driver_event_type {
  278. CNSS_DRIVER_EVENT_SERVER_ARRIVE,
  279. CNSS_DRIVER_EVENT_SERVER_EXIT,
  280. CNSS_DRIVER_EVENT_REQUEST_MEM,
  281. CNSS_DRIVER_EVENT_FW_MEM_READY,
  282. CNSS_DRIVER_EVENT_FW_READY,
  283. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  284. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  285. CNSS_DRIVER_EVENT_REGISTER_DRIVER,
  286. CNSS_DRIVER_EVENT_UNREGISTER_DRIVER,
  287. CNSS_DRIVER_EVENT_RECOVERY,
  288. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  289. CNSS_DRIVER_EVENT_POWER_UP,
  290. CNSS_DRIVER_EVENT_POWER_DOWN,
  291. CNSS_DRIVER_EVENT_IDLE_RESTART,
  292. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  293. CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND,
  294. CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND,
  295. CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
  296. CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE,
  297. CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
  298. CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
  299. CNSS_DRIVER_EVENT_MAX,
  300. };
  301. enum cnss_driver_state {
  302. CNSS_QMI_WLFW_CONNECTED = 0,
  303. CNSS_FW_MEM_READY,
  304. CNSS_FW_READY,
  305. CNSS_IN_COLD_BOOT_CAL,
  306. CNSS_DRIVER_LOADING,
  307. CNSS_DRIVER_UNLOADING = 5,
  308. CNSS_DRIVER_IDLE_RESTART,
  309. CNSS_DRIVER_IDLE_SHUTDOWN,
  310. CNSS_DRIVER_PROBED,
  311. CNSS_DRIVER_RECOVERY,
  312. CNSS_FW_BOOT_RECOVERY = 10,
  313. CNSS_DEV_ERR_NOTIFY,
  314. CNSS_DRIVER_DEBUG,
  315. CNSS_COEX_CONNECTED,
  316. CNSS_IMS_CONNECTED,
  317. CNSS_IN_SUSPEND_RESUME = 15,
  318. CNSS_IN_REBOOT,
  319. CNSS_COLD_BOOT_CAL_DONE,
  320. CNSS_IN_PANIC,
  321. CNSS_QMI_DEL_SERVER,
  322. CNSS_QMI_DMS_CONNECTED = 20,
  323. CNSS_DAEMON_CONNECTED,
  324. CNSS_PCI_PROBE_DONE,
  325. CNSS_DRIVER_REGISTER,
  326. CNSS_WLAN_HW_DISABLED,
  327. CNSS_FS_READY = 25,
  328. CNSS_DRIVER_REGISTERED,
  329. CNSS_DMS_DEL_SERVER,
  330. CNSS_POWER_OFF,
  331. };
  332. struct cnss_recovery_data {
  333. enum cnss_recovery_reason reason;
  334. };
  335. enum cnss_pins {
  336. CNSS_WLAN_EN,
  337. CNSS_PCIE_TXP,
  338. CNSS_PCIE_TXN,
  339. CNSS_PCIE_RXP,
  340. CNSS_PCIE_RXN,
  341. CNSS_PCIE_REFCLKP,
  342. CNSS_PCIE_REFCLKN,
  343. CNSS_PCIE_RST,
  344. CNSS_PCIE_WAKE,
  345. };
  346. struct cnss_pin_connect_result {
  347. u32 fw_pwr_pin_result;
  348. u32 fw_phy_io_pin_result;
  349. u32 fw_rf_pin_result;
  350. u32 host_pin_result;
  351. };
  352. enum cnss_debug_quirks {
  353. LINK_DOWN_SELF_RECOVERY,
  354. SKIP_DEVICE_BOOT,
  355. USE_CORE_ONLY_FW,
  356. SKIP_RECOVERY,
  357. QMI_BYPASS,
  358. ENABLE_WALTEST,
  359. ENABLE_PCI_LINK_DOWN_PANIC,
  360. FBC_BYPASS,
  361. ENABLE_DAEMON_SUPPORT,
  362. DISABLE_DRV,
  363. DISABLE_IO_COHERENCY,
  364. IGNORE_PCI_LINK_FAILURE,
  365. DISABLE_TIME_SYNC,
  366. FORCE_ONE_MSI,
  367. QUIRK_MAX_VALUE
  368. };
  369. enum cnss_bdf_type {
  370. CNSS_BDF_BIN,
  371. CNSS_BDF_ELF,
  372. CNSS_BDF_REGDB = 4,
  373. CNSS_BDF_HDS = 6,
  374. };
  375. enum cnss_cal_status {
  376. CNSS_CAL_DONE,
  377. CNSS_CAL_TIMEOUT,
  378. CNSS_CAL_FAILURE,
  379. };
  380. struct cnss_cal_info {
  381. enum cnss_cal_status cal_status;
  382. };
  383. /**
  384. * enum cnss_time_sync_period_vote - to get per vote time sync period
  385. * @TIME_SYNC_VOTE_WLAN: WLAN Driver vote
  386. * @TIME_SYNC_VOTE_CNSS: sys config vote
  387. * @TIME_SYNC_VOTE_MAX
  388. */
  389. enum cnss_time_sync_period_vote {
  390. TIME_SYNC_VOTE_WLAN,
  391. TIME_SYNC_VOTE_CNSS,
  392. TIME_SYNC_VOTE_MAX,
  393. };
  394. struct cnss_control_params {
  395. unsigned long quirks;
  396. unsigned int mhi_timeout;
  397. unsigned int mhi_m2_timeout;
  398. unsigned int qmi_timeout;
  399. unsigned int bdf_type;
  400. unsigned int time_sync_period;
  401. unsigned int time_sync_period_vote[TIME_SYNC_VOTE_MAX];
  402. };
  403. struct cnss_tcs_info {
  404. resource_size_t cmd_base_addr;
  405. void __iomem *cmd_base_addr_io;
  406. };
  407. struct cnss_cpr_info {
  408. resource_size_t tcs_cmd_data_addr;
  409. void __iomem *tcs_cmd_data_addr_io;
  410. u32 cpr_pmic_addr;
  411. u32 voltage;
  412. };
  413. enum cnss_ce_index {
  414. CNSS_CE_00,
  415. CNSS_CE_01,
  416. CNSS_CE_02,
  417. CNSS_CE_03,
  418. CNSS_CE_04,
  419. CNSS_CE_05,
  420. CNSS_CE_06,
  421. CNSS_CE_07,
  422. CNSS_CE_08,
  423. CNSS_CE_09,
  424. CNSS_CE_10,
  425. CNSS_CE_11,
  426. CNSS_CE_COMMON,
  427. };
  428. struct cnss_dms_data {
  429. u32 mac_valid;
  430. u8 mac[QMI_WLFW_MAC_ADDR_SIZE_V01];
  431. };
  432. enum cnss_timeout_type {
  433. CNSS_TIMEOUT_QMI,
  434. CNSS_TIMEOUT_POWER_UP,
  435. CNSS_TIMEOUT_IDLE_RESTART,
  436. CNSS_TIMEOUT_CALIBRATION,
  437. CNSS_TIMEOUT_WLAN_WATCHDOG,
  438. CNSS_TIMEOUT_RDDM,
  439. CNSS_TIMEOUT_RECOVERY,
  440. CNSS_TIMEOUT_DAEMON_CONNECTION,
  441. };
  442. struct cnss_sol_gpio {
  443. int dev_sol_gpio;
  444. int dev_sol_irq;
  445. u32 dev_sol_counter;
  446. int host_sol_gpio;
  447. };
  448. struct cnss_thermal_cdev {
  449. struct list_head tcdev_list;
  450. int tcdev_id;
  451. unsigned long curr_thermal_state;
  452. unsigned long max_thermal_state;
  453. struct device_node *dev_node;
  454. struct thermal_cooling_device *tcdev;
  455. };
  456. struct cnss_plat_data {
  457. struct platform_device *plat_dev;
  458. void *bus_priv;
  459. enum cnss_dev_bus_type bus_type;
  460. struct list_head vreg_list;
  461. struct list_head clk_list;
  462. struct cnss_pinctrl_info pinctrl_info;
  463. struct cnss_sol_gpio sol_gpio;
  464. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  465. struct cnss_subsys_info subsys_info;
  466. #endif
  467. struct cnss_ramdump_info ramdump_info;
  468. struct cnss_ramdump_info_v2 ramdump_info_v2;
  469. #if IS_ENABLED(CONFIG_ESOC)
  470. struct cnss_esoc_info esoc_info;
  471. #endif
  472. struct cnss_interconnect_cfg icc;
  473. struct notifier_block modem_nb;
  474. struct notifier_block reboot_nb;
  475. struct notifier_block panic_nb;
  476. struct cnss_platform_cap cap;
  477. struct pm_qos_request qos_request;
  478. struct cnss_device_version device_version;
  479. u32 rc_num;
  480. unsigned long device_id;
  481. enum cnss_driver_status driver_status;
  482. u32 recovery_count;
  483. u8 recovery_enabled;
  484. u8 recovery_pcss_enabled;
  485. u8 hds_enabled;
  486. unsigned long driver_state;
  487. struct list_head event_list;
  488. struct list_head cnss_tcdev_list;
  489. struct mutex tcdev_lock; /* mutex for cooling devices list access */
  490. spinlock_t event_lock; /* spinlock for driver work event handling */
  491. struct work_struct event_work;
  492. struct workqueue_struct *event_wq;
  493. struct work_struct recovery_work;
  494. struct delayed_work wlan_reg_driver_work;
  495. struct qmi_handle qmi_wlfw;
  496. struct qmi_handle qmi_dms;
  497. struct wlfw_rf_chip_info chip_info;
  498. struct wlfw_rf_board_info board_info;
  499. struct wlfw_soc_info soc_info;
  500. struct wlfw_fw_version_info fw_version_info;
  501. struct cnss_dev_mem_info dev_mem_info[CNSS_MAX_DEV_MEM_NUM];
  502. char fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN + 1];
  503. u32 otp_version;
  504. u32 fw_mem_seg_len;
  505. struct cnss_fw_mem fw_mem[QMI_WLFW_MAX_NUM_MEM_SEG_V01];
  506. struct cnss_fw_mem m3_mem;
  507. struct cnss_fw_mem tme_lite_mem;
  508. struct cnss_fw_mem tme_opt_file_mem[QMI_WLFW_MAX_TME_OPT_FILE_NUM];
  509. struct cnss_fw_mem *cal_mem;
  510. struct cnss_fw_mem aux_mem;
  511. u64 cal_time;
  512. bool cbc_file_download;
  513. u32 cal_file_size;
  514. struct completion daemon_connected;
  515. u32 qdss_mem_seg_len;
  516. struct cnss_fw_mem qdss_mem[QMI_WLFW_MAX_NUM_MEM_SEG_V01];
  517. u32 *qdss_reg;
  518. struct cnss_pin_connect_result pin_result;
  519. struct dentry *root_dentry;
  520. atomic_t pm_count;
  521. struct timer_list fw_boot_timer;
  522. struct completion power_up_complete;
  523. struct completion cal_complete;
  524. struct mutex dev_lock; /* mutex for register access through debugfs */
  525. struct mutex driver_ops_lock; /* mutex for external driver ops */
  526. struct cnss_wlan_driver *driver_ops;
  527. u32 supported_link_speed;
  528. u32 device_freq_hz;
  529. u32 diag_reg_read_addr;
  530. u32 diag_reg_read_mem_type;
  531. u32 diag_reg_read_len;
  532. u8 *diag_reg_read_buf;
  533. u8 cal_done;
  534. u8 powered_on;
  535. u8 use_fw_path_with_prefix;
  536. char firmware_name[MAX_FIRMWARE_NAME_LEN];
  537. char fw_fallback_name[MAX_FIRMWARE_NAME_LEN];
  538. #ifndef CONFIG_DISABLE_CNSS_SRAM_DUMP
  539. u8 *sram_dump;
  540. #endif
  541. struct completion rddm_complete;
  542. struct completion recovery_complete;
  543. struct cnss_control_params ctrl_params;
  544. struct cnss_cpr_info cpr_info;
  545. u64 antenna;
  546. u64 grant;
  547. struct qmi_handle coex_qmi;
  548. struct qmi_handle ims_qmi;
  549. struct qmi_txn txn;
  550. struct wakeup_source *recovery_ws;
  551. u64 dynamic_feature;
  552. void *get_info_cb_ctx;
  553. int (*get_info_cb)(void *ctx, void *event, int event_len);
  554. void *get_driver_async_data_ctx;
  555. int (*get_driver_async_data_cb)(void *ctx, uint16_t type, void *event, int event_len);
  556. bool cbc_enabled;
  557. u8 use_pm_domain;
  558. u8 use_nv_mac;
  559. u8 set_wlaon_pwr_ctrl;
  560. struct cnss_tcs_info tcs_info;
  561. bool fw_pcie_gen_switch;
  562. bool fw_aux_uc_support;
  563. u64 fw_caps;
  564. u8 pcie_gen_speed;
  565. struct iommu_domain *audio_iommu_domain;
  566. bool is_audio_shared_iommu_group;
  567. struct cnss_dms_data dms;
  568. int power_up_error;
  569. u32 hw_trc_override;
  570. u8 charger_mode;
  571. struct mbox_client mbox_client_data;
  572. struct mbox_chan *mbox_chan;
  573. struct qmp *qmp;
  574. const char *vreg_ol_cpr, *vreg_ipa;
  575. const char **pdc_init_table, **vreg_pdc_map, **pmu_vreg_map;
  576. int pdc_init_table_len, vreg_pdc_map_len, pmu_vreg_map_len;
  577. bool adsp_pc_enabled;
  578. u64 feature_list;
  579. u32 dt_type;
  580. struct kobject *wifi_kobj;
  581. u16 hang_event_data_len;
  582. u32 hang_data_addr_offset;
  583. /* bitmap to detect FEM combination */
  584. u8 hwid_bitmap;
  585. uint32_t num_shadow_regs_v3;
  586. bool sec_peri_feature_disable;
  587. struct device_node *dev_node;
  588. char device_name[CNSS_DEVICE_NAME_SIZE];
  589. u32 plat_idx;
  590. bool enumerate_done;
  591. int qrtr_node_id;
  592. unsigned int wlfw_service_instance_id;
  593. const char *pld_bus_ops_name;
  594. u32 on_chip_pmic_devices_count;
  595. u32 *on_chip_pmic_board_ids;
  596. bool no_bwscale;
  597. bool sleep_clk;
  598. struct wlchip_serial_id_v01 serial_id;
  599. };
  600. #if IS_ENABLED(CONFIG_ARCH_QCOM)
  601. static inline u64 cnss_get_host_timestamp(struct cnss_plat_data *plat_priv)
  602. {
  603. u64 ticks = __arch_counter_get_cntvct();
  604. do_div(ticks, TIME_CLOCK_FREQ_HZ / 100000);
  605. return ticks * 10;
  606. }
  607. #else
  608. static inline u64 cnss_get_host_timestamp(struct cnss_plat_data *plat_priv)
  609. {
  610. struct timespec64 ts;
  611. ktime_get_ts64(&ts);
  612. return (ts.tv_sec * 1000000) + (ts.tv_nsec / 1000);
  613. }
  614. #endif
  615. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv);
  616. int cnss_wlan_hw_enable(void);
  617. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev);
  618. struct cnss_plat_data *cnss_get_first_plat_priv(struct platform_device *plat_dev);
  619. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv);
  620. void cnss_pm_relax(struct cnss_plat_data *plat_priv);
  621. struct cnss_plat_data *cnss_get_plat_priv_by_rc_num(int rc_num);
  622. int cnss_get_max_plat_env_count(void);
  623. struct cnss_plat_data *cnss_get_plat_env(int index);
  624. void cnss_get_qrtr_info(struct cnss_plat_data *plat_priv);
  625. void cnss_get_sleep_clk_supported(struct cnss_plat_data *plat_priv);
  626. void cnss_get_bwscal_info(struct cnss_plat_data *plat_priv);
  627. bool cnss_is_dual_wlan_enabled(void);
  628. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  629. enum cnss_driver_event_type type,
  630. u32 flags, void *data);
  631. int cnss_get_vreg_type(struct cnss_plat_data *plat_priv,
  632. enum cnss_vreg_type type);
  633. void cnss_put_vreg_type(struct cnss_plat_data *plat_priv,
  634. enum cnss_vreg_type type);
  635. int cnss_vreg_on_type(struct cnss_plat_data *plat_priv,
  636. enum cnss_vreg_type type);
  637. int cnss_vreg_off_type(struct cnss_plat_data *plat_priv,
  638. enum cnss_vreg_type type);
  639. int cnss_get_clk(struct cnss_plat_data *plat_priv);
  640. void cnss_put_clk(struct cnss_plat_data *plat_priv);
  641. int cnss_vreg_unvote_type(struct cnss_plat_data *plat_priv,
  642. enum cnss_vreg_type type);
  643. int cnss_get_pinctrl(struct cnss_plat_data *plat_priv);
  644. int cnss_get_wlan_sw_ctrl(struct cnss_plat_data *plat_priv);
  645. int cnss_power_on_device(struct cnss_plat_data *plat_priv, bool reset);
  646. void cnss_power_off_device(struct cnss_plat_data *plat_priv);
  647. bool cnss_is_device_powered_on(struct cnss_plat_data *plat_priv);
  648. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv);
  649. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv);
  650. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv);
  651. int cnss_init_dev_sol_irq(struct cnss_plat_data *plat_priv);
  652. int cnss_deinit_dev_sol_irq(struct cnss_plat_data *plat_priv);
  653. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value);
  654. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv);
  655. int cnss_register_subsys(struct cnss_plat_data *plat_priv);
  656. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv);
  657. int cnss_register_ramdump(struct cnss_plat_data *plat_priv);
  658. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv);
  659. int cnss_do_ramdump(struct cnss_plat_data *plat_priv);
  660. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv);
  661. int cnss_do_host_ramdump(struct cnss_plat_data *plat_priv,
  662. struct cnss_ssr_driver_dump_entry *ssr_entry,
  663. size_t num_entries_loaded);
  664. void cnss_set_pin_connect_status(struct cnss_plat_data *plat_priv);
  665. int cnss_get_cpr_info(struct cnss_plat_data *plat_priv);
  666. int cnss_update_cpr_info(struct cnss_plat_data *plat_priv);
  667. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  668. phys_addr_t *pa, unsigned long attrs);
  669. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  670. enum cnss_fw_dump_type type, int seg_no,
  671. void *va, phys_addr_t pa, size_t size);
  672. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  673. enum cnss_fw_dump_type type, int seg_no,
  674. void *va, phys_addr_t pa, size_t size);
  675. int cnss_enable_int_pow_amp_vreg(struct cnss_plat_data *plat_priv);
  676. int cnss_get_tcs_info(struct cnss_plat_data *plat_priv);
  677. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  678. enum cnss_timeout_type);
  679. int cnss_aop_interface_init(struct cnss_plat_data *plat_priv);
  680. void cnss_aop_interface_deinit(struct cnss_plat_data *plat_priv);
  681. int cnss_aop_pdc_reconfig(struct cnss_plat_data *plat_priv);
  682. int cnss_aop_send_msg(struct cnss_plat_data *plat_priv, char *msg);
  683. void cnss_power_misc_params_init(struct cnss_plat_data *plat_priv);
  684. int cnss_aop_ol_cpr_cfg_setup(struct cnss_plat_data *plat_priv,
  685. struct wlfw_pmu_cfg_v01 *fw_pmu_cfg);
  686. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  687. const struct firmware **fw_entry,
  688. const char *filename);
  689. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  690. enum cnss_feature_v01 feature);
  691. int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
  692. enum cnss_feature_v01 feature);
  693. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  694. u64 *feature_list);
  695. int cnss_get_input_gpio_value(struct cnss_plat_data *plat_priv, int gpio_num);
  696. bool cnss_check_driver_loading_allowed(void);
  697. int cnss_dev_specific_power_on(struct cnss_plat_data *plat_priv);
  698. void cnss_recovery_handler(struct cnss_plat_data *plat_priv);
  699. size_t cnss_get_platform_name(struct cnss_plat_data *plat_priv,
  700. char *buf, const size_t buf_len);
  701. int cnss_iommu_map(struct iommu_domain *domain, unsigned long iova,
  702. phys_addr_t paddr, size_t size, int prot);
  703. #endif /* _CNSS_MAIN_H */