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samsung-sm8650
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android_kernel_samsung_sm8650-modules
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android_kernel_...
/
asoc
/
codecs
/
wsa884x
/
wsa884x-reg-masks.h

wsa884x-reg-masks.h 8.8 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef WSA884X_REG_MASKS_H
    7. 

  7. #define WSA884X_REG_MASKS_H
    8. 

  8. #include <linux/regmap.h>
    9. 

  9. #include <linux/device.h>
    10. 

  10. #include "wsa884x-registers.h"
    11. 

  11. 

  12. /*
    13. 

  13.  * Use in conjunction with wsa884x-reg-shifts.c for field values.
    14. 

  14.  * field_value = (register_value & field_mask) >> field_shift
    15. 

  15.  */
    16. 

  16. 

  17. #define FIELD_MASK(register_name, field_name) \
    18. 

  18. 	WSA884X_##register_name##_##field_name##_MASK
    19. 

  19. 

  20. /* WSA884X_VSENSE1 Fields: */
    21. 

  21. #define WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK                              0xe0
    22. 

  22. #define WSA884X_VSENSE1_VSENSE_AMP_IQ_CTL_1_MASK                         0x10
    23. 

  23. #define WSA884X_VSENSE1_IDLE_MODE_CTL_MASK                               0x0c
    24. 

  24. #define WSA884X_VSENSE1_VOCM_AMP_CTL_MASK                                0x03
    25. 

  25. /* WSA884X_ADC_2 Fields: */
    26. 

  26. #define WSA884X_ADC_2_ATEST_SEL_CAL_REF_MASK                             0x80
    27. 

  27. #define WSA884X_ADC_2_ISNS_LOAD_STORED_MASK                              0x40
    28. 

  28. #define WSA884X_ADC_2_EN_DET_MASK                                        0x20
    29. 

  29. #define WSA884X_ADC_2_EN_ATEST_REF_MASK                                  0x10
    30. 

  30. #define WSA884X_ADC_2_EN_ATEST_INT_MASK                                  0x0e
    31. 

  31. #define WSA884X_ADC_2_D_ADC_REG_EN_MASK                                  0x01
    32. 

  32. /* WSA884X_ADC_7 Fields: */
    33. 

  33. #define WSA884X_ADC_7_CLAMPON_MASK                                       0x80
    34. 

  34. #define WSA884X_ADC_7_CAL_LOOP_TRIM_MASK                                 0x70
    35. 

  35. #define WSA884X_ADC_7_REG_TRIM_EN_MASK                                   0x08
    36. 

  36. #define WSA884X_ADC_7_EN_AZ_REG_MASK                                     0x04
    37. 

  37. #define WSA884X_ADC_7_EN_SAR_REG_MASK                                    0x02
    38. 

  38. #define WSA884X_ADC_7_EN_SW_CURRENT_REG_MASK                             0x01
    39. 

  39. /* WSA884X_BOP_DEGLITCH_CTL Fields: */
    40. 

  40. #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK               0x1e
    41. 

  41. #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK                    0x01
    42. 

  42. /* WSA884X_CDC_SPK_DSM_A2_0 Fields: */
    43. 

  43. #define WSA884X_CDC_SPK_DSM_A2_0_COEF_A2_MASK                            0xff
    44. 

  44. /* WSA884X_CDC_SPK_DSM_A2_1 Fields: */
    45. 

  45. #define WSA884X_CDC_SPK_DSM_A2_1_COEF_A2_MASK                            0x0f
    46. 

  46. /* WSA884X_CDC_SPK_DSM_A3_0 Fields: */
    47. 

  47. #define WSA884X_CDC_SPK_DSM_A3_0_COEF_A3_MASK                            0xff
    48. 

  48. /* WSA884X_CDC_SPK_DSM_A3_1 Fields: */
    49. 

  49. #define WSA884X_CDC_SPK_DSM_A3_1_COEF_A3_MASK                            0x07
    50. 

  50. /* WSA884X_CDC_SPK_DSM_A4_0 Fields: */
    51. 

  51. #define WSA884X_CDC_SPK_DSM_A4_0_COEF_A4_MASK                            0xff
    52. 

  52. /* WSA884X_CDC_SPK_DSM_A5_0 Fields: */
    53. 

  53. #define WSA884X_CDC_SPK_DSM_A5_0_COEF_A5_MASK                            0xff
    54. 

  54. /* WSA884X_CDC_SPK_DSM_A6_0 Fields: */
    55. 

  55. #define WSA884X_CDC_SPK_DSM_A6_0_COEF_A6_MASK                            0xff
    56. 

  56. /* WSA884X_CDC_SPK_DSM_A7_0 Fields: */
    57. 

  57. #define WSA884X_CDC_SPK_DSM_A7_0_COEF_A7_MASK                            0xff
    58. 

  58. /* WSA884X_CDC_SPK_DSM_C_0 Fields: */
    59. 

  59. #define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK                             0xf0
    60. 

  60. #define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK                             0x0f
    61. 

  61. /* WSA884X_CDC_SPK_DSM_C_2 Fields: */
    62. 

  62. #define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK                             0xf0
    63. 

  63. #define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_MASK                             0x0f
    64. 

  64. /* WSA884X_CDC_SPK_DSM_C_3 Fields: */
    65. 

  65. #define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK                             0x3f
    66. 

  66. /* WSA884X_CDC_SPK_DSM_R1 Fields: */
    67. 

  67. #define WSA884X_CDC_SPK_DSM_R1_SAT_LIMIT_R1_MASK                         0xff
    68. 

  68. /* WSA884X_CDC_SPK_DSM_R2 Fields: */
    69. 

  69. #define WSA884X_CDC_SPK_DSM_R2_SAT_LIMIT_R2_MASK                         0xff
    70. 

  70. /* WSA884X_CDC_SPK_DSM_R3 Fields: */
    71. 

  71. #define WSA884X_CDC_SPK_DSM_R3_SAT_LIMIT_R3_MASK                         0xff
    72. 

  72. /* WSA884X_CDC_SPK_DSM_R4 Fields: */
    73. 

  73. #define WSA884X_CDC_SPK_DSM_R4_SAT_LIMIT_R4_MASK                         0xff
    74. 

  74. /* WSA884X_CDC_SPK_DSM_R5 Fields: */
    75. 

  75. #define WSA884X_CDC_SPK_DSM_R5_SAT_LIMIT_R5_MASK                         0xff
    76. 

  76. /* WSA884X_CDC_SPK_DSM_R6 Fields: */
    77. 

  77. #define WSA884X_CDC_SPK_DSM_R6_SAT_LIMIT_R6_MASK                         0xff
    78. 

  78. /* WSA884X_CDC_SPK_DSM_R7 Fields: */
    79. 

  79. #define WSA884X_CDC_SPK_DSM_R7_SAT_LIMIT_R7_MASK                         0xff
    80. 

  80. /* WSA884X_DRE_CTL_0 Fields: */
    81. 

  81. #define WSA884X_DRE_CTL_0_PROG_DELAY_MASK                                0xf0
    82. 

  82. #define WSA884X_DRE_CTL_0_OFFSET_MASK                                    0x07
    83. 

  83. /* WSA884X_GAIN_RAMPING_MIN Fields: */
    84. 

  84. #define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK                           0x1f
    85. 

  85. /* WSA884X_CLSH_SOFT_MAX Fields: */
    86. 

  86. #define WSA884X_CLSH_SOFT_MAX_SOFT_MAX_MASK                              0xff
    87. 

  87. /* WSA884X_CLSH_VTH1 Fields: */
    88. 

  88. #define WSA884X_CLSH_VTH1_CLSH_VTH1_MASK                                 0xff
    89. 

  89. /* WSA884X_CLSH_VTH10 Fields: */
    90. 

  90. #define WSA884X_CLSH_VTH10_CLSH_VTH10_MASK                               0xff
    91. 

  91. /* WSA884X_CLSH_VTH11 Fields: */
    92. 

  92. #define WSA884X_CLSH_VTH11_CLSH_VTH11_MASK                               0xff
    93. 

  93. /* WSA884X_CLSH_VTH12 Fields: */
    94. 

  94. #define WSA884X_CLSH_VTH12_CLSH_VTH12_MASK                               0xff
    95. 

  95. /* WSA884X_CLSH_VTH13 Fields: */
    96. 

  96. #define WSA884X_CLSH_VTH13_CLSH_VTH13_MASK                               0xff
    97. 

  97. /* WSA884X_CLSH_VTH14 Fields: */
    98. 

  98. #define WSA884X_CLSH_VTH14_CLSH_VTH14_MASK                               0xff
    99. 

  99. /* WSA884X_CLSH_VTH15 Fields: */
    100. 

  100. #define WSA884X_CLSH_VTH15_CLSH_VTH15_MASK                               0xff
    101. 

  101. /* WSA884X_ANA_WO_CTL_0 Fields: */
    102. 

  102. #define WSA884X_ANA_WO_CTL_0_VPHX_SYS_EN_MASK                            0xc0
    103. 

  103. #define WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK                            0x3c
    104. 

  104. #define WSA884X_ANA_WO_CTL_0_PA_MIN_GAIN_BYP_MASK                        0x02
    105. 

  105. #define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK                        0x01
    106. 

  106. /* WSA884X_ANA_WO_CTL_1 Fields: */
    107. 

  107. #define WSA884X_ANA_WO_CTL_1_BOOST_SHARE_EN_MASK                         0x08
    108. 

  108. #define WSA884X_ANA_WO_CTL_1_EXT_VDDSPK_EN_MASK                          0x07
    109. 

  109. /* WSA884X_DRE_CTL_1 Fields: */
    110. 

  110. #define WSA884X_DRE_CTL_1_CSR_GAIN_MASK                                  0x3e
    111. 

  111. #define WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK                               0x01
    112. 

  112. /* WSA884X_VBAT_THRM_FLT_CTL Fields: */
    113. 

  113. #define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_MASK                     0xe0
    114. 

  114. #define WSA884X_VBAT_THRM_FLT_CTL_THRM_FLT_EN_MASK                       0x10
    115. 

  115. #define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK                     0x0e
    116. 

  116. #define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_MASK                       0x01
    117. 

  117. /* WSA884X_PDM_WD_CTL Fields: */
    118. 

  118. #define WSA884X_PDM_WD_CTL_HOLD_OFF_MASK                                 0x04
    119. 

  119. #define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_MASK                             0x02
    120. 

  120. #define WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK                                0x01
    121. 

  121. /* WSA884X_PA_FSM_BYP_CTL Fields: */
    122. 

  122. #define WSA884X_PA_FSM_BYP_CTL_PA_FSM_BYP_MASK                           0x01
    123. 

  123. /* WSA884X_TADC_VALUE_CTL Fields: */
    124. 

  124. #define WSA884X_TADC_VALUE_CTL_VBAT_VALUE_RD_EN_MASK                     0x02
    125. 

  125. #define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK                     0x01
    126. 

  126. /* WSA884X_PA_FSM_BYP0 Fields: */
    127. 

  127. #define WSA884X_PA_FSM_BYP0_TSADC_EN_MASK                                0x80
    128. 

  128. #define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_MASK                            0x40
    129. 

  129. #define WSA884X_PA_FSM_BYP0_D_UNMUTE_MASK                                0x20
    130. 

  130. #define WSA884X_PA_FSM_BYP0_PA_EN_MASK                                   0x10
    131. 

  131. #define WSA884X_PA_FSM_BYP0_BOOST_EN_MASK                                0x08
    132. 

  132. #define WSA884X_PA_FSM_BYP0_BG_EN_MASK                                   0x04
    133. 

  133. #define WSA884X_PA_FSM_BYP0_CLK_WD_EN_MASK                               0x02
    134. 

  134. #define WSA884X_PA_FSM_BYP0_DC_CAL_EN_MASK                               0x01
    135. 

  135. /* WSA884X_PA_FSM_BYP1 Fields: */
    136. 

  136. #define WSA884X_PA_FSM_BYP1_NG_MODE_MASK                                 0xc0
    137. 

  137. #define WSA884X_PA_FSM_BYP1_PWRSAV_CTL_MASK                              0x20
    138. 

  138. #define WSA884X_PA_FSM_BYP1_RAMP_DOWN_MASK                               0x10
    139. 

  139. #define WSA884X_PA_FSM_BYP1_RAMP_UP_MASK                                 0x08
    140. 

  140. #define WSA884X_PA_FSM_BYP1_BLEEDER_EN_MASK                              0x04
    141. 

  141. #define WSA884X_PA_FSM_BYP1_PA_MAIN_EN_MASK                              0x02
    142. 

  142. #define WSA884X_PA_FSM_BYP1_PA_AUX_EN_MASK                               0x01
    143. 

  143. /* WSA884X_PA_FSM_EN Fields: */
    144. 

  144. #define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK                              0x01
    145. 

  145. /* WSA884X_OTP_REG_0 Fields: */
    146. 

  146. #define WSA884X_OTP_REG_0_WSA884X_ID_MASK                                0x0f
    147. 

  147. /* WSA884X_CHIP_ID0 Fields: */
    148. 

  148. #define WSA884X_CHIP_ID0_BYTE_0_MASK                                     0xff
    149. 

  149. /* WSA884X_CHIP_ID1 Fields: */
    150. 

  150. #define WSA884X_CHIP_ID1_BYTE_1_MASK                                     0xff
    151. 

  151. /* WSA884X_CHIP_ID2 Fields: */
    152. 

  152. #define WSA884X_CHIP_ID2_BYTE_2_MASK                                     0xff
    153. 

  153. /* WSA884X_CHIP_ID3 Fields: */
    154. 

  154. #define WSA884X_CHIP_ID3_BYTE_3_MASK                                     0xff
    155. 

  155. 

  156. #endif /* WSA884X_REG_MASKS_H */
    157.