hal_5332.c 67 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
  16. */
  17. #include "qdf_types.h"
  18. #include "qdf_util.h"
  19. #include "qdf_mem.h"
  20. #include "qdf_nbuf.h"
  21. #include "qdf_module.h"
  22. #include "target_type.h"
  23. #include "wcss_version.h"
  24. #include "hal_be_hw_headers.h"
  25. #include "hal_internal.h"
  26. #include "hal_api.h"
  27. #include "hal_flow.h"
  28. #include "rx_flow_search_entry.h"
  29. #include "hal_rx_flow_info.h"
  30. #include "hal_be_api.h"
  31. #include "tcl_entrance_from_ppe_ring.h"
  32. #include "sw_monitor_ring.h"
  33. #include "wcss_seq_hwioreg_umac.h"
  34. #include "wfss_ce_reg_seq_hwioreg.h"
  35. #include <uniform_reo_status_header.h>
  36. #include <wbm_release_ring_tx.h>
  37. #include <phyrx_location.h>
  38. #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \
  39. defined(WLAN_PKT_CAPTURE_RX_2_0)
  40. #include <mon_ingress_ring.h>
  41. #include <mon_destination_ring.h>
  42. #endif
  43. #include "rx_reo_queue_1k.h"
  44. #include <hal_be_rx.h>
  45. #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
  46. RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
  47. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  48. RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  49. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  50. RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  51. #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  52. RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  53. #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
  54. REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
  55. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
  56. STATUS_HEADER_REO_STATUS_NUMBER
  57. #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
  58. STATUS_HEADER_TIMESTAMP
  59. #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
  60. RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
  61. #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
  62. RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
  63. #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  64. TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
  65. #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
  66. TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
  67. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
  68. TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET
  69. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
  70. BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB
  71. #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
  72. BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK
  73. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
  74. BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB
  75. #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
  76. BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK
  77. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
  78. BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB
  79. #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
  80. BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK
  81. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
  82. BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB
  83. #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
  84. BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK
  85. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
  86. TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB
  87. #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
  88. TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK
  89. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
  90. WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
  91. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
  92. WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
  93. #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
  94. WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
  95. #if defined(WLAN_PKT_CAPTURE_TX_2_0) || defined(WLAN_PKT_CAPTURE_RX_2_0)
  96. #include "hal_be_api_mon.h"
  97. #endif
  98. #define CMEM_REG_BASE 0x00100000
  99. /* For Berryllium sw2rxdma ring size increased to 20 bits */
  100. #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF
  101. #include "hal_5332_rx.h"
  102. #include "hal_5332_tx.h"
  103. #include "hal_be_rx_tlv.h"
  104. #include <hal_be_generic_api.h>
  105. /**
  106. * hal_read_pmm_scratch_reg_5332() - API to read PMM Scratch register
  107. *
  108. * @soc: HAL soc
  109. * @reg_enum: Enum of the scratch register
  110. *
  111. * Return: uint32_t
  112. */
  113. static inline
  114. uint32_t hal_read_pmm_scratch_reg_5332(struct hal_soc *soc,
  115. enum hal_scratch_reg_enum reg_enum)
  116. {
  117. uint32_t val = 0;
  118. pld_reg_read(soc->qdf_dev->dev, (reg_enum * 4), &val,
  119. soc->dev_base_addr_pmm);
  120. return val;
  121. }
  122. /**
  123. * hal_get_tsf2_scratch_reg_qca5332() - API to read tsf2 scratch register
  124. *
  125. * @hal_soc_hdl: HAL soc context
  126. * @mac_id: mac id
  127. * @value: Pointer to update tsf2 value
  128. *
  129. * Return: void
  130. */
  131. static void hal_get_tsf2_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl,
  132. uint8_t mac_id, uint64_t *value)
  133. {
  134. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  135. uint32_t offset_lo, offset_hi;
  136. enum hal_scratch_reg_enum enum_lo, enum_hi;
  137. hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi);
  138. offset_lo = hal_read_pmm_scratch_reg_5332(soc,
  139. enum_lo);
  140. offset_hi = hal_read_pmm_scratch_reg_5332(soc,
  141. enum_hi);
  142. *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
  143. }
  144. /**
  145. * hal_get_tqm_scratch_reg_qca5332() - API to read tqm scratch register
  146. *
  147. * @hal_soc_hdl: HAL soc context
  148. * @value: Pointer to update tqm value
  149. *
  150. * Return: void
  151. */
  152. static void hal_get_tqm_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl,
  153. uint64_t *value)
  154. {
  155. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  156. uint32_t offset_lo, offset_hi;
  157. offset_lo = hal_read_pmm_scratch_reg_5332(soc,
  158. PMM_TQM_CLOCK_OFFSET_LO_US);
  159. offset_hi = hal_read_pmm_scratch_reg_5332(soc,
  160. PMM_TQM_CLOCK_OFFSET_HI_US);
  161. *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
  162. }
  163. #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
  164. #define HAL_PPE_VP_ENTRIES_MAX 32
  165. /**
  166. * hal_get_link_desc_size_5332() - API to get the link desc size
  167. *
  168. * Return: uint32_t
  169. */
  170. static uint32_t hal_get_link_desc_size_5332(void)
  171. {
  172. return LINK_DESC_SIZE;
  173. }
  174. /**
  175. * hal_rx_get_tlv_5332() - API to get the tlv
  176. *
  177. * @rx_tlv: TLV data extracted from the rx packet
  178. * Return: uint8_t
  179. */
  180. static uint8_t hal_rx_get_tlv_5332(void *rx_tlv)
  181. {
  182. return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH);
  183. }
  184. /**
  185. * hal_rx_wbm_err_msdu_continuation_get_5332() - API to check if WBM
  186. * msdu continuation bit is set
  187. *
  188. * @wbm_desc: wbm release ring descriptor
  189. *
  190. * Return: true if msdu continuation bit is set.
  191. */
  192. uint8_t hal_rx_wbm_err_msdu_continuation_get_5332(void *wbm_desc)
  193. {
  194. uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) +
  195. WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET);
  196. return (comp_desc &
  197. WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >>
  198. WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB;
  199. }
  200. /**
  201. * hal_rx_proc_phyrx_other_receive_info_tlv_5332() - API to get tlv info
  202. * @rx_tlv_hdr: start address of rx_pkt_tlvs
  203. * @ppdu_info_hdl: PPDU info handle to fill
  204. *
  205. * Return: uint32_t
  206. */
  207. static inline
  208. void hal_rx_proc_phyrx_other_receive_info_tlv_5332(void *rx_tlv_hdr,
  209. void *ppdu_info_hdl)
  210. {
  211. uint32_t tlv_tag, tlv_len;
  212. uint32_t temp_len, other_tlv_len, other_tlv_tag;
  213. void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  214. void *other_tlv_hdr = NULL;
  215. void *other_tlv = NULL;
  216. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  217. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  218. temp_len = 0;
  219. other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
  220. other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
  221. other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
  222. temp_len += other_tlv_len;
  223. other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  224. switch (other_tlv_tag) {
  225. default:
  226. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  227. "%s unhandled TLV type: %d, TLV len:%d",
  228. __func__, other_tlv_tag, other_tlv_len);
  229. break;
  230. }
  231. }
  232. #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
  233. static inline
  234. void hal_rx_get_bb_info_5332(void *rx_tlv, void *ppdu_info_hdl)
  235. {
  236. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  237. ppdu_info->cfr_info.bb_captured_channel =
  238. HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
  239. ppdu_info->cfr_info.bb_captured_timeout =
  240. HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
  241. ppdu_info->cfr_info.bb_captured_reason =
  242. HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
  243. }
  244. static inline
  245. void hal_rx_get_rtt_info_5332(void *rx_tlv, void *ppdu_info_hdl)
  246. {
  247. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  248. ppdu_info->cfr_info.rx_location_info_valid =
  249. HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  250. RX_LOCATION_INFO_VALID);
  251. ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
  252. HAL_RX_GET_64(rx_tlv,
  253. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  254. RTT_CHE_BUFFER_POINTER_LOW32);
  255. ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
  256. HAL_RX_GET_64(rx_tlv,
  257. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  258. RTT_CHE_BUFFER_POINTER_HIGH8);
  259. ppdu_info->cfr_info.chan_capture_status =
  260. HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv);
  261. ppdu_info->cfr_info.rx_start_ts =
  262. HAL_RX_GET_64(rx_tlv,
  263. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  264. RX_START_TS);
  265. ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
  266. HAL_RX_GET_64(rx_tlv,
  267. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  268. RTT_CFO_MEASUREMENT);
  269. ppdu_info->cfr_info.agc_gain_info0 =
  270. HAL_RX_GET_64(rx_tlv,
  271. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  272. GAIN_CHAIN0);
  273. ppdu_info->cfr_info.agc_gain_info0 |=
  274. (((uint32_t)HAL_RX_GET_64(rx_tlv,
  275. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  276. GAIN_CHAIN1)) << 16);
  277. ppdu_info->cfr_info.agc_gain_info1 =
  278. HAL_RX_GET_64(rx_tlv,
  279. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  280. GAIN_CHAIN2);
  281. ppdu_info->cfr_info.agc_gain_info1 |=
  282. (((uint32_t)HAL_RX_GET_64(rx_tlv,
  283. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  284. GAIN_CHAIN3)) << 16);
  285. ppdu_info->cfr_info.agc_gain_info2 = 0;
  286. ppdu_info->cfr_info.agc_gain_info3 = 0;
  287. ppdu_info->cfr_info.mcs_rate =
  288. HAL_RX_GET_64(rx_tlv,
  289. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  290. RTT_MCS_RATE);
  291. ppdu_info->cfr_info.gi_type =
  292. HAL_RX_GET_64(rx_tlv,
  293. PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
  294. RTT_GI_TYPE);
  295. }
  296. #endif
  297. #ifdef CONFIG_WORD_BASED_TLV
  298. /**
  299. * hal_rx_dump_mpdu_start_tlv_5332() - dump RX mpdu_start TLV in structured
  300. * human readable format.
  301. * @mpdustart: pointer the rx_attention TLV in pkt.
  302. * @dbg_level: log level.
  303. *
  304. * Return: void
  305. */
  306. static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart,
  307. uint8_t dbg_level)
  308. {
  309. struct rx_mpdu_start_compact *mpdu_info =
  310. (struct rx_mpdu_start_compact *)mpdustart;
  311. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  312. "rx_mpdu_start tlv (1/5) - "
  313. "rx_reo_queue_desc_addr_39_32 :%x"
  314. "receive_queue_number:%x "
  315. "pre_delim_err_warning:%x "
  316. "first_delim_err:%x "
  317. "pn_31_0:%x "
  318. "pn_63_32:%x "
  319. "pn_95_64:%x ",
  320. mpdu_info->rx_reo_queue_desc_addr_39_32,
  321. mpdu_info->receive_queue_number,
  322. mpdu_info->pre_delim_err_warning,
  323. mpdu_info->first_delim_err,
  324. mpdu_info->pn_31_0,
  325. mpdu_info->pn_63_32,
  326. mpdu_info->pn_95_64);
  327. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  328. "rx_mpdu_start tlv (2/5) - "
  329. "ast_index:%x "
  330. "sw_peer_id:%x "
  331. "mpdu_frame_control_valid:%x "
  332. "mpdu_duration_valid:%x "
  333. "mac_addr_ad1_valid:%x "
  334. "mac_addr_ad2_valid:%x "
  335. "mac_addr_ad3_valid:%x "
  336. "mac_addr_ad4_valid:%x "
  337. "mpdu_sequence_control_valid :%x"
  338. "mpdu_qos_control_valid:%x "
  339. "mpdu_ht_control_valid:%x "
  340. "frame_encryption_info_valid :%x",
  341. mpdu_info->ast_index,
  342. mpdu_info->sw_peer_id,
  343. mpdu_info->mpdu_frame_control_valid,
  344. mpdu_info->mpdu_duration_valid,
  345. mpdu_info->mac_addr_ad1_valid,
  346. mpdu_info->mac_addr_ad2_valid,
  347. mpdu_info->mac_addr_ad3_valid,
  348. mpdu_info->mac_addr_ad4_valid,
  349. mpdu_info->mpdu_sequence_control_valid,
  350. mpdu_info->mpdu_qos_control_valid,
  351. mpdu_info->mpdu_ht_control_valid,
  352. mpdu_info->frame_encryption_info_valid);
  353. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  354. "rx_mpdu_start tlv (3/5) - "
  355. "mpdu_fragment_number:%x "
  356. "more_fragment_flag:%x "
  357. "fr_ds:%x "
  358. "to_ds:%x "
  359. "encrypted:%x "
  360. "mpdu_retry:%x "
  361. "mpdu_sequence_number:%x ",
  362. mpdu_info->mpdu_fragment_number,
  363. mpdu_info->more_fragment_flag,
  364. mpdu_info->fr_ds,
  365. mpdu_info->to_ds,
  366. mpdu_info->encrypted,
  367. mpdu_info->mpdu_retry,
  368. mpdu_info->mpdu_sequence_number);
  369. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  370. "rx_mpdu_start tlv (4/5) - "
  371. "mpdu_frame_control_field:%x "
  372. "mpdu_duration_field:%x ",
  373. mpdu_info->mpdu_frame_control_field,
  374. mpdu_info->mpdu_duration_field);
  375. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  376. "rx_mpdu_start tlv (5/5) - "
  377. "mac_addr_ad1_31_0:%x "
  378. "mac_addr_ad1_47_32:%x "
  379. "mac_addr_ad2_15_0:%x "
  380. "mac_addr_ad2_47_16:%x "
  381. "mac_addr_ad3_31_0:%x "
  382. "mac_addr_ad3_47_32:%x "
  383. "mpdu_sequence_control_field :%x",
  384. mpdu_info->mac_addr_ad1_31_0,
  385. mpdu_info->mac_addr_ad1_47_32,
  386. mpdu_info->mac_addr_ad2_15_0,
  387. mpdu_info->mac_addr_ad2_47_16,
  388. mpdu_info->mac_addr_ad3_31_0,
  389. mpdu_info->mac_addr_ad3_47_32,
  390. mpdu_info->mpdu_sequence_control_field);
  391. }
  392. /**
  393. * hal_rx_dump_msdu_end_tlv_5332() - dump RX msdu_end TLV in structured
  394. * human readable format.
  395. * @msduend: pointer the msdu_end TLV in pkt.
  396. * @dbg_level: log level.
  397. *
  398. * Return: void
  399. */
  400. static void hal_rx_dump_msdu_end_tlv_5332(void *msduend,
  401. uint8_t dbg_level)
  402. {
  403. struct rx_msdu_end_compact *msdu_end =
  404. (struct rx_msdu_end_compact *)msduend;
  405. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  406. "rx_msdu_end tlv - "
  407. "key_id_octet: %d "
  408. "tcp_udp_chksum: %d "
  409. "sa_idx_timeout: %d "
  410. "da_idx_timeout: %d "
  411. "msdu_limit_error: %d "
  412. "flow_idx_timeout: %d "
  413. "flow_idx_invalid: %d "
  414. "wifi_parser_error: %d "
  415. "sa_is_valid: %d "
  416. "da_is_valid: %d "
  417. "da_is_mcbc: %d "
  418. "tkip_mic_err: %d "
  419. "l3_header_padding: %d "
  420. "first_msdu: %d "
  421. "last_msdu: %d "
  422. "sa_idx: %d "
  423. "msdu_drop: %d "
  424. "reo_destination_indication: %d "
  425. "flow_idx: %d "
  426. "fse_metadata: %d "
  427. "cce_metadata: %d "
  428. "sa_sw_peer_id: %d ",
  429. msdu_end->key_id_octet,
  430. msdu_end->tcp_udp_chksum,
  431. msdu_end->sa_idx_timeout,
  432. msdu_end->da_idx_timeout,
  433. msdu_end->msdu_limit_error,
  434. msdu_end->flow_idx_timeout,
  435. msdu_end->flow_idx_invalid,
  436. msdu_end->wifi_parser_error,
  437. msdu_end->sa_is_valid,
  438. msdu_end->da_is_valid,
  439. msdu_end->da_is_mcbc,
  440. msdu_end->tkip_mic_err,
  441. msdu_end->l3_header_padding,
  442. msdu_end->first_msdu,
  443. msdu_end->last_msdu,
  444. msdu_end->sa_idx,
  445. msdu_end->msdu_drop,
  446. msdu_end->reo_destination_indication,
  447. msdu_end->flow_idx,
  448. msdu_end->fse_metadata,
  449. msdu_end->cce_metadata,
  450. msdu_end->sa_sw_peer_id);
  451. }
  452. #else
  453. static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart,
  454. uint8_t dbg_level)
  455. {
  456. struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
  457. struct rx_mpdu_info *mpdu_info =
  458. (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
  459. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  460. "rx_mpdu_start tlv (1/5) - "
  461. "rx_reo_queue_desc_addr_31_0 :%x"
  462. "rx_reo_queue_desc_addr_39_32 :%x"
  463. "receive_queue_number:%x "
  464. "pre_delim_err_warning:%x "
  465. "first_delim_err:%x "
  466. "reserved_2a:%x "
  467. "pn_31_0:%x "
  468. "pn_63_32:%x "
  469. "pn_95_64:%x "
  470. "pn_127_96:%x "
  471. "epd_en:%x "
  472. "all_frames_shall_be_encrypted :%x"
  473. "encrypt_type:%x "
  474. "wep_key_width_for_variable_key :%x"
  475. "mesh_sta:%x "
  476. "bssid_hit:%x "
  477. "bssid_number:%x "
  478. "tid:%x "
  479. "reserved_7a:%x ",
  480. mpdu_info->rx_reo_queue_desc_addr_31_0,
  481. mpdu_info->rx_reo_queue_desc_addr_39_32,
  482. mpdu_info->receive_queue_number,
  483. mpdu_info->pre_delim_err_warning,
  484. mpdu_info->first_delim_err,
  485. mpdu_info->reserved_2a,
  486. mpdu_info->pn_31_0,
  487. mpdu_info->pn_63_32,
  488. mpdu_info->pn_95_64,
  489. mpdu_info->pn_127_96,
  490. mpdu_info->epd_en,
  491. mpdu_info->all_frames_shall_be_encrypted,
  492. mpdu_info->encrypt_type,
  493. mpdu_info->wep_key_width_for_variable_key,
  494. mpdu_info->mesh_sta,
  495. mpdu_info->bssid_hit,
  496. mpdu_info->bssid_number,
  497. mpdu_info->tid,
  498. mpdu_info->reserved_7a);
  499. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  500. "rx_mpdu_start tlv (2/5) - "
  501. "ast_index:%x "
  502. "sw_peer_id:%x "
  503. "mpdu_frame_control_valid:%x "
  504. "mpdu_duration_valid:%x "
  505. "mac_addr_ad1_valid:%x "
  506. "mac_addr_ad2_valid:%x "
  507. "mac_addr_ad3_valid:%x "
  508. "mac_addr_ad4_valid:%x "
  509. "mpdu_sequence_control_valid :%x"
  510. "mpdu_qos_control_valid:%x "
  511. "mpdu_ht_control_valid:%x "
  512. "frame_encryption_info_valid :%x",
  513. mpdu_info->ast_index,
  514. mpdu_info->sw_peer_id,
  515. mpdu_info->mpdu_frame_control_valid,
  516. mpdu_info->mpdu_duration_valid,
  517. mpdu_info->mac_addr_ad1_valid,
  518. mpdu_info->mac_addr_ad2_valid,
  519. mpdu_info->mac_addr_ad3_valid,
  520. mpdu_info->mac_addr_ad4_valid,
  521. mpdu_info->mpdu_sequence_control_valid,
  522. mpdu_info->mpdu_qos_control_valid,
  523. mpdu_info->mpdu_ht_control_valid,
  524. mpdu_info->frame_encryption_info_valid);
  525. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  526. "rx_mpdu_start tlv (3/5) - "
  527. "mpdu_fragment_number:%x "
  528. "more_fragment_flag:%x "
  529. "reserved_11a:%x "
  530. "fr_ds:%x "
  531. "to_ds:%x "
  532. "encrypted:%x "
  533. "mpdu_retry:%x "
  534. "mpdu_sequence_number:%x ",
  535. mpdu_info->mpdu_fragment_number,
  536. mpdu_info->more_fragment_flag,
  537. mpdu_info->reserved_11a,
  538. mpdu_info->fr_ds,
  539. mpdu_info->to_ds,
  540. mpdu_info->encrypted,
  541. mpdu_info->mpdu_retry,
  542. mpdu_info->mpdu_sequence_number);
  543. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  544. "rx_mpdu_start tlv (4/5) - "
  545. "mpdu_frame_control_field:%x "
  546. "mpdu_duration_field:%x ",
  547. mpdu_info->mpdu_frame_control_field,
  548. mpdu_info->mpdu_duration_field);
  549. QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
  550. "rx_mpdu_start tlv (5/5) - "
  551. "mac_addr_ad1_31_0:%x "
  552. "mac_addr_ad1_47_32:%x "
  553. "mac_addr_ad2_15_0:%x "
  554. "mac_addr_ad2_47_16:%x "
  555. "mac_addr_ad3_31_0:%x "
  556. "mac_addr_ad3_47_32:%x "
  557. "mpdu_sequence_control_field :%x"
  558. "mac_addr_ad4_31_0:%x "
  559. "mac_addr_ad4_47_32:%x "
  560. "mpdu_qos_control_field:%x ",
  561. mpdu_info->mac_addr_ad1_31_0,
  562. mpdu_info->mac_addr_ad1_47_32,
  563. mpdu_info->mac_addr_ad2_15_0,
  564. mpdu_info->mac_addr_ad2_47_16,
  565. mpdu_info->mac_addr_ad3_31_0,
  566. mpdu_info->mac_addr_ad3_47_32,
  567. mpdu_info->mpdu_sequence_control_field,
  568. mpdu_info->mac_addr_ad4_31_0,
  569. mpdu_info->mac_addr_ad4_47_32,
  570. mpdu_info->mpdu_qos_control_field);
  571. }
  572. static void hal_rx_dump_msdu_end_tlv_5332(void *msduend,
  573. uint8_t dbg_level)
  574. {
  575. struct rx_msdu_end *msdu_end =
  576. (struct rx_msdu_end *)msduend;
  577. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  578. "rx_msdu_end tlv - "
  579. "key_id_octet: %d "
  580. "cce_super_rule: %d "
  581. "cce_classify_not_done_truncat: %d "
  582. "cce_classify_not_done_cce_dis: %d "
  583. "rule_indication_31_0: %d "
  584. "tcp_udp_chksum: %d "
  585. "sa_idx_timeout: %d "
  586. "da_idx_timeout: %d "
  587. "msdu_limit_error: %d "
  588. "flow_idx_timeout: %d "
  589. "flow_idx_invalid: %d "
  590. "wifi_parser_error: %d "
  591. "sa_is_valid: %d "
  592. "da_is_valid: %d "
  593. "da_is_mcbc: %d "
  594. "tkip_mic_err: %d "
  595. "l3_header_padding: %d "
  596. "first_msdu: %d "
  597. "last_msdu: %d "
  598. "sa_idx: %d "
  599. "msdu_drop: %d "
  600. "reo_destination_indication: %d "
  601. "flow_idx: %d "
  602. "fse_metadata: %d "
  603. "cce_metadata: %d "
  604. "sa_sw_peer_id: %d ",
  605. msdu_end->key_id_octet,
  606. msdu_end->cce_super_rule,
  607. msdu_end->cce_classify_not_done_truncate,
  608. msdu_end->cce_classify_not_done_cce_dis,
  609. msdu_end->rule_indication_31_0,
  610. msdu_end->tcp_udp_chksum,
  611. msdu_end->sa_idx_timeout,
  612. msdu_end->da_idx_timeout,
  613. msdu_end->msdu_limit_error,
  614. msdu_end->flow_idx_timeout,
  615. msdu_end->flow_idx_invalid,
  616. msdu_end->wifi_parser_error,
  617. msdu_end->sa_is_valid,
  618. msdu_end->da_is_valid,
  619. msdu_end->da_is_mcbc,
  620. msdu_end->tkip_mic_err,
  621. msdu_end->l3_header_padding,
  622. msdu_end->first_msdu,
  623. msdu_end->last_msdu,
  624. msdu_end->sa_idx,
  625. msdu_end->msdu_drop,
  626. msdu_end->reo_destination_indication,
  627. msdu_end->flow_idx,
  628. msdu_end->fse_metadata,
  629. msdu_end->cce_metadata,
  630. msdu_end->sa_sw_peer_id);
  631. }
  632. #endif
  633. /**
  634. * hal_reo_status_get_header_5332() - Process reo desc info
  635. * @ring_desc: Pointer to reo descriptor
  636. * @b: tlv type info
  637. * @h1: Pointer to hal_reo_status_header where info to be stored
  638. *
  639. * Return: none.
  640. *
  641. */
  642. static void hal_reo_status_get_header_5332(hal_ring_desc_t ring_desc,
  643. int b, void *h1)
  644. {
  645. uint64_t *d = (uint64_t *)ring_desc;
  646. uint64_t val1 = 0;
  647. struct hal_reo_status_header *h =
  648. (struct hal_reo_status_header *)h1;
  649. /* Offsets of descriptor fields defined in HW headers start
  650. * from the field after TLV header
  651. */
  652. d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
  653. switch (b) {
  654. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  655. val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  656. STATUS_HEADER_REO_STATUS_NUMBER)];
  657. break;
  658. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  659. val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
  660. STATUS_HEADER_REO_STATUS_NUMBER)];
  661. break;
  662. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  663. val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  664. STATUS_HEADER_REO_STATUS_NUMBER)];
  665. break;
  666. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  667. val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
  668. STATUS_HEADER_REO_STATUS_NUMBER)];
  669. break;
  670. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  671. val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  672. STATUS_HEADER_REO_STATUS_NUMBER)];
  673. break;
  674. case HAL_REO_DESC_THRES_STATUS_TLV:
  675. val1 =
  676. d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  677. STATUS_HEADER_REO_STATUS_NUMBER)];
  678. break;
  679. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  680. val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
  681. STATUS_HEADER_REO_STATUS_NUMBER)];
  682. break;
  683. default:
  684. qdf_nofl_err("ERROR: Unknown tlv\n");
  685. break;
  686. }
  687. h->cmd_num =
  688. HAL_GET_FIELD(
  689. UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER,
  690. val1);
  691. h->exec_time =
  692. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
  693. CMD_EXECUTION_TIME, val1);
  694. h->status =
  695. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
  696. REO_CMD_EXECUTION_STATUS, val1);
  697. switch (b) {
  698. case HAL_REO_QUEUE_STATS_STATUS_TLV:
  699. val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
  700. STATUS_HEADER_TIMESTAMP)];
  701. break;
  702. case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
  703. val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
  704. STATUS_HEADER_TIMESTAMP)];
  705. break;
  706. case HAL_REO_FLUSH_CACHE_STATUS_TLV:
  707. val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
  708. STATUS_HEADER_TIMESTAMP)];
  709. break;
  710. case HAL_REO_UNBLK_CACHE_STATUS_TLV:
  711. val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
  712. STATUS_HEADER_TIMESTAMP)];
  713. break;
  714. case HAL_REO_TIMOUT_LIST_STATUS_TLV:
  715. val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
  716. STATUS_HEADER_TIMESTAMP)];
  717. break;
  718. case HAL_REO_DESC_THRES_STATUS_TLV:
  719. val1 =
  720. d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
  721. STATUS_HEADER_TIMESTAMP)];
  722. break;
  723. case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
  724. val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
  725. STATUS_HEADER_TIMESTAMP)];
  726. break;
  727. default:
  728. qdf_nofl_err("ERROR: Unknown tlv\n");
  729. break;
  730. }
  731. h->tstamp =
  732. HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1);
  733. }
  734. static
  735. void *hal_rx_msdu0_buffer_addr_lsb_5332(void *link_desc_va)
  736. {
  737. return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
  738. }
  739. static
  740. void *hal_rx_msdu_desc_info_ptr_get_5332(void *msdu0)
  741. {
  742. return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
  743. }
  744. static
  745. void *hal_ent_mpdu_desc_info_5332(void *ent_ring_desc)
  746. {
  747. return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
  748. }
  749. static
  750. void *hal_dst_mpdu_desc_info_5332(void *dst_ring_desc)
  751. {
  752. return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
  753. }
  754. /**
  755. * hal_reo_config_5332() - Set reo config parameters
  756. * @soc: hal soc handle
  757. * @reg_val: value to be set
  758. * @reo_params: reo parameters
  759. *
  760. * Return: void
  761. */
  762. static void
  763. hal_reo_config_5332(struct hal_soc *soc,
  764. uint32_t reg_val,
  765. struct hal_reo_params *reo_params)
  766. {
  767. HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
  768. }
  769. /**
  770. * hal_rx_msdu_desc_info_get_ptr_5332() - Get msdu desc info ptr
  771. * @msdu_details_ptr: Pointer to msdu_details_ptr
  772. *
  773. * Return: Pointer to rx_msdu_desc_info structure.
  774. *
  775. */
  776. static void *hal_rx_msdu_desc_info_get_ptr_5332(void *msdu_details_ptr)
  777. {
  778. return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
  779. }
  780. /**
  781. * hal_rx_link_desc_msdu0_ptr_5332() - Get pointer to rx_msdu details
  782. * @link_desc: Pointer to link desc
  783. *
  784. * Return: Pointer to rx_msdu_details structure
  785. *
  786. */
  787. static void *hal_rx_link_desc_msdu0_ptr_5332(void *link_desc)
  788. {
  789. return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
  790. }
  791. /**
  792. * hal_get_window_address_5332() - Function to get hp/tp address
  793. * @hal_soc: Pointer to hal_soc
  794. * @addr: address offset of register
  795. *
  796. * Return: modified address offset of register
  797. */
  798. static inline qdf_iomem_t hal_get_window_address_5332(struct hal_soc *hal_soc,
  799. qdf_iomem_t addr)
  800. {
  801. uint32_t offset = addr - hal_soc->dev_base_addr;
  802. qdf_iomem_t new_offset;
  803. /*
  804. * Check if offset lies within CE register range(0x740000)
  805. * or UMAC/DP register range (0x00A00000).
  806. * If offset lies within CE register range, map it
  807. * into CE region.
  808. */
  809. if (offset < 0xA00000) {
  810. offset = offset - CE_CFG_WFSS_CE_REG_BASE;
  811. new_offset = (hal_soc->dev_base_addr_ce + offset);
  812. return new_offset;
  813. } else {
  814. /*
  815. * If offset lies within DP register range,
  816. * return the address as such
  817. */
  818. return addr;
  819. }
  820. }
  821. static
  822. void hal_compute_reo_remap_ix2_ix3_5332(uint32_t *ring, uint32_t num_rings,
  823. uint32_t *remap1, uint32_t *remap2)
  824. {
  825. switch (num_rings) {
  826. case 1:
  827. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  828. HAL_REO_REMAP_IX2(ring[0], 17) |
  829. HAL_REO_REMAP_IX2(ring[0], 18) |
  830. HAL_REO_REMAP_IX2(ring[0], 19) |
  831. HAL_REO_REMAP_IX2(ring[0], 20) |
  832. HAL_REO_REMAP_IX2(ring[0], 21) |
  833. HAL_REO_REMAP_IX2(ring[0], 22) |
  834. HAL_REO_REMAP_IX2(ring[0], 23);
  835. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  836. HAL_REO_REMAP_IX3(ring[0], 25) |
  837. HAL_REO_REMAP_IX3(ring[0], 26) |
  838. HAL_REO_REMAP_IX3(ring[0], 27) |
  839. HAL_REO_REMAP_IX3(ring[0], 28) |
  840. HAL_REO_REMAP_IX3(ring[0], 29) |
  841. HAL_REO_REMAP_IX3(ring[0], 30) |
  842. HAL_REO_REMAP_IX3(ring[0], 31);
  843. break;
  844. case 2:
  845. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  846. HAL_REO_REMAP_IX2(ring[0], 17) |
  847. HAL_REO_REMAP_IX2(ring[1], 18) |
  848. HAL_REO_REMAP_IX2(ring[1], 19) |
  849. HAL_REO_REMAP_IX2(ring[0], 20) |
  850. HAL_REO_REMAP_IX2(ring[0], 21) |
  851. HAL_REO_REMAP_IX2(ring[1], 22) |
  852. HAL_REO_REMAP_IX2(ring[1], 23);
  853. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  854. HAL_REO_REMAP_IX3(ring[0], 25) |
  855. HAL_REO_REMAP_IX3(ring[1], 26) |
  856. HAL_REO_REMAP_IX3(ring[1], 27) |
  857. HAL_REO_REMAP_IX3(ring[0], 28) |
  858. HAL_REO_REMAP_IX3(ring[0], 29) |
  859. HAL_REO_REMAP_IX3(ring[1], 30) |
  860. HAL_REO_REMAP_IX3(ring[1], 31);
  861. break;
  862. case 3:
  863. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  864. HAL_REO_REMAP_IX2(ring[1], 17) |
  865. HAL_REO_REMAP_IX2(ring[2], 18) |
  866. HAL_REO_REMAP_IX2(ring[0], 19) |
  867. HAL_REO_REMAP_IX2(ring[1], 20) |
  868. HAL_REO_REMAP_IX2(ring[2], 21) |
  869. HAL_REO_REMAP_IX2(ring[0], 22) |
  870. HAL_REO_REMAP_IX2(ring[1], 23);
  871. *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
  872. HAL_REO_REMAP_IX3(ring[0], 25) |
  873. HAL_REO_REMAP_IX3(ring[1], 26) |
  874. HAL_REO_REMAP_IX3(ring[2], 27) |
  875. HAL_REO_REMAP_IX3(ring[0], 28) |
  876. HAL_REO_REMAP_IX3(ring[1], 29) |
  877. HAL_REO_REMAP_IX3(ring[2], 30) |
  878. HAL_REO_REMAP_IX3(ring[0], 31);
  879. break;
  880. case 4:
  881. *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
  882. HAL_REO_REMAP_IX2(ring[1], 17) |
  883. HAL_REO_REMAP_IX2(ring[2], 18) |
  884. HAL_REO_REMAP_IX2(ring[3], 19) |
  885. HAL_REO_REMAP_IX2(ring[0], 20) |
  886. HAL_REO_REMAP_IX2(ring[1], 21) |
  887. HAL_REO_REMAP_IX2(ring[2], 22) |
  888. HAL_REO_REMAP_IX2(ring[3], 23);
  889. *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
  890. HAL_REO_REMAP_IX3(ring[1], 25) |
  891. HAL_REO_REMAP_IX3(ring[2], 26) |
  892. HAL_REO_REMAP_IX3(ring[3], 27) |
  893. HAL_REO_REMAP_IX3(ring[0], 28) |
  894. HAL_REO_REMAP_IX3(ring[1], 29) |
  895. HAL_REO_REMAP_IX3(ring[2], 30) |
  896. HAL_REO_REMAP_IX3(ring[3], 31);
  897. break;
  898. }
  899. }
  900. /**
  901. * hal_rx_flow_setup_fse_5332() - Setup a flow search entry in HW FST
  902. * @rx_fst: Pointer to the Rx Flow Search Table
  903. * @table_offset: offset into the table where the flow is to be setup
  904. * @rx_flow: Flow Parameters
  905. *
  906. * Return: Success/Failure
  907. */
  908. static void *
  909. hal_rx_flow_setup_fse_5332(uint8_t *rx_fst, uint32_t table_offset,
  910. uint8_t *rx_flow)
  911. {
  912. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  913. struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
  914. uint8_t *fse;
  915. bool fse_valid;
  916. if (table_offset >= fst->max_entries) {
  917. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  918. "HAL FSE table offset %u exceeds max entries %u",
  919. table_offset, fst->max_entries);
  920. return NULL;
  921. }
  922. fse = (uint8_t *)fst->base_vaddr +
  923. (table_offset * HAL_RX_FST_ENTRY_SIZE);
  924. fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  925. if (fse_valid) {
  926. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  927. "HAL FSE %pK already valid", fse);
  928. return NULL;
  929. }
  930. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) =
  931. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96,
  932. qdf_htonl(flow->tuple_info.src_ip_127_96));
  933. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) =
  934. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64,
  935. qdf_htonl(flow->tuple_info.src_ip_95_64));
  936. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) =
  937. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32,
  938. qdf_htonl(flow->tuple_info.src_ip_63_32));
  939. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) =
  940. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0,
  941. qdf_htonl(flow->tuple_info.src_ip_31_0));
  942. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) =
  943. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96,
  944. qdf_htonl(flow->tuple_info.dest_ip_127_96));
  945. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) =
  946. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64,
  947. qdf_htonl(flow->tuple_info.dest_ip_95_64));
  948. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) =
  949. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32,
  950. qdf_htonl(flow->tuple_info.dest_ip_63_32));
  951. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) =
  952. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0,
  953. qdf_htonl(flow->tuple_info.dest_ip_31_0));
  954. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT);
  955. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |=
  956. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT,
  957. (flow->tuple_info.dest_port));
  958. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT);
  959. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |=
  960. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT,
  961. (flow->tuple_info.src_port));
  962. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL);
  963. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |=
  964. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL,
  965. flow->tuple_info.l4_protocol);
  966. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER);
  967. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |=
  968. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER,
  969. flow->reo_destination_handler);
  970. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  971. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |=
  972. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1);
  973. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA);
  974. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) =
  975. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA,
  976. flow->fse_metadata);
  977. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION);
  978. HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |=
  979. HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY,
  980. REO_DESTINATION_INDICATION,
  981. flow->reo_destination_indication);
  982. /* Reset all the other fields in FSE */
  983. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9);
  984. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP);
  985. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT);
  986. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT);
  987. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP);
  988. return fse;
  989. }
  990. /**
  991. * hal_rx_dump_pkt_hdr_tlv_5332() - dump RX pkt header TLV in hex format
  992. * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt.
  993. * @dbg_level: log level.
  994. *
  995. * Return: void
  996. */
  997. #ifndef NO_RX_PKT_HDR_TLV
  998. static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs,
  999. uint8_t dbg_level)
  1000. {
  1001. struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
  1002. hal_verbose_debug("\n---------------\n"
  1003. "rx_pkt_hdr_tlv\n"
  1004. "---------------\n"
  1005. "phy_ppdu_id 0x%x ",
  1006. pkt_hdr_tlv->phy_ppdu_id);
  1007. hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr,
  1008. sizeof(pkt_hdr_tlv->rx_pkt_hdr));
  1009. }
  1010. #else
  1011. static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs,
  1012. uint8_t dbg_level)
  1013. {
  1014. }
  1015. #endif
  1016. /**
  1017. * hal_rx_dump_pkt_tlvs_5332() - API to print RX Pkt TLVS qca5332
  1018. * @hal_soc_hdl: hal_soc handle
  1019. * @buf: pointer the pkt buffer
  1020. * @dbg_level: log level
  1021. *
  1022. * Return: void
  1023. */
  1024. #ifdef CONFIG_WORD_BASED_TLV
  1025. static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,
  1026. uint8_t *buf, uint8_t dbg_level)
  1027. {
  1028. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1029. struct rx_msdu_end_compact *msdu_end =
  1030. &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1031. struct rx_mpdu_start_compact *mpdu_start =
  1032. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  1033. hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level);
  1034. hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level);
  1035. hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level);
  1036. }
  1037. #else
  1038. static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,
  1039. uint8_t *buf, uint8_t dbg_level)
  1040. {
  1041. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1042. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1043. struct rx_mpdu_start *mpdu_start =
  1044. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  1045. hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level);
  1046. hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level);
  1047. hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level);
  1048. }
  1049. #endif
  1050. #define HAL_NUM_TCL_BANKS_5332 24
  1051. /**
  1052. * hal_cmem_write_5332() - function for CMEM buffer writing
  1053. * @hal_soc_hdl: HAL SOC handle
  1054. * @offset: CMEM address
  1055. * @value: value to write
  1056. *
  1057. * Return: None.
  1058. */
  1059. static void hal_cmem_write_5332(hal_soc_handle_t hal_soc_hdl,
  1060. uint32_t offset,
  1061. uint32_t value)
  1062. {
  1063. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  1064. /* cmem region is ioremapped from CMEM_REG_BASE, hence subtracting
  1065. * that from offset.
  1066. */
  1067. offset = offset - CMEM_REG_BASE;
  1068. pld_reg_write(hal->qdf_dev->dev, offset, value,
  1069. hal->dev_base_addr_cmem);
  1070. }
  1071. /**
  1072. * hal_tx_get_num_tcl_banks_5332() - Get number of banks in target
  1073. *
  1074. * Return: number of bank
  1075. */
  1076. static uint8_t hal_tx_get_num_tcl_banks_5332(void)
  1077. {
  1078. return HAL_NUM_TCL_BANKS_5332;
  1079. }
  1080. static void hal_reo_setup_5332(struct hal_soc *soc, void *reoparams,
  1081. int qref_reset)
  1082. {
  1083. uint32_t reg_val;
  1084. struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
  1085. reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
  1086. REO_REG_REG_BASE));
  1087. hal_reo_config_5332(soc, reg_val, reo_params);
  1088. /* Other ring enable bits and REO_ENABLE will be set by FW */
  1089. /* TODO: Setup destination ring mapping if enabled */
  1090. /* TODO: Error destination ring setting is left to default.
  1091. * Default setting is to send all errors to release ring.
  1092. */
  1093. /* Set the reo descriptor swap bits in case of BIG endian platform */
  1094. hal_setup_reo_swap(soc);
  1095. HAL_REG_WRITE(soc,
  1096. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE),
  1097. HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000);
  1098. HAL_REG_WRITE(soc,
  1099. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE),
  1100. (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
  1101. HAL_REG_WRITE(soc,
  1102. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE),
  1103. (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
  1104. HAL_REG_WRITE(soc,
  1105. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE),
  1106. (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000));
  1107. /*
  1108. * When hash based routing is enabled, routing of the rx packet
  1109. * is done based on the following value: 1 _ _ _ _ The last 4
  1110. * bits are based on hash[3:0]. This means the possible values
  1111. * are 0x10 to 0x1f. This value is used to look-up the
  1112. * ring ID configured in Destination_Ring_Ctrl_IX_* register.
  1113. * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
  1114. * registers need to be configured to set-up the 16 entries to
  1115. * map the hash values to a ring number. There are 3 bits per
  1116. * hash entry – which are mapped as follows:
  1117. * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
  1118. * 7: NOT_USED.
  1119. */
  1120. if (reo_params->rx_hash_enabled) {
  1121. HAL_REG_WRITE(soc,
  1122. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR
  1123. (REO_REG_REG_BASE), reo_params->remap0);
  1124. hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
  1125. HAL_REG_READ(soc,
  1126. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(
  1127. REO_REG_REG_BASE)));
  1128. HAL_REG_WRITE(soc,
  1129. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR
  1130. (REO_REG_REG_BASE), reo_params->remap1);
  1131. hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
  1132. HAL_REG_READ(soc,
  1133. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
  1134. REO_REG_REG_BASE)));
  1135. HAL_REG_WRITE(soc,
  1136. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR
  1137. (REO_REG_REG_BASE), reo_params->remap2);
  1138. hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x",
  1139. HAL_REG_READ(soc,
  1140. HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
  1141. REO_REG_REG_BASE)));
  1142. }
  1143. /* TODO: Check if the following registers shoould be setup by host:
  1144. * AGING_CONTROL
  1145. * HIGH_MEMORY_THRESHOLD
  1146. * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
  1147. * GLOBAL_LINK_DESC_COUNT_CTRL
  1148. */
  1149. soc->reo_qref = *reo_params->reo_qref;
  1150. hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset);
  1151. }
  1152. static uint16_t hal_get_rx_max_ba_window_qca5332(int tid)
  1153. {
  1154. return HAL_RX_BA_WINDOW_1024;
  1155. }
  1156. /**
  1157. * hal_qca5332_get_reo_qdesc_size() - Get the reo queue descriptor size
  1158. * from the give Block-Ack window size
  1159. * @ba_window_size: Block-Ack window size
  1160. * @tid: TID
  1161. *
  1162. * Return: reo queue descriptor size
  1163. */
  1164. static uint32_t hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size, int tid)
  1165. {
  1166. /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for
  1167. * NON_QOS_TID until HW issues are resolved.
  1168. */
  1169. if (tid != HAL_NON_QOS_TID)
  1170. ba_window_size = hal_get_rx_max_ba_window_qca5332(tid);
  1171. /* Return descriptor size corresponding to window size of 2 since
  1172. * we set ba_window_size to 2 while setting up REO descriptors as
  1173. * a WAR to get 2k jump exception aggregates are received without
  1174. * a BA session.
  1175. */
  1176. if (ba_window_size <= 1) {
  1177. if (tid != HAL_NON_QOS_TID)
  1178. return sizeof(struct rx_reo_queue) +
  1179. sizeof(struct rx_reo_queue_ext);
  1180. else
  1181. return sizeof(struct rx_reo_queue);
  1182. }
  1183. if (ba_window_size <= 105)
  1184. return sizeof(struct rx_reo_queue) +
  1185. sizeof(struct rx_reo_queue_ext);
  1186. if (ba_window_size <= 210)
  1187. return sizeof(struct rx_reo_queue) +
  1188. (2 * sizeof(struct rx_reo_queue_ext));
  1189. if (ba_window_size <= 256)
  1190. return sizeof(struct rx_reo_queue) +
  1191. (3 * sizeof(struct rx_reo_queue_ext));
  1192. return sizeof(struct rx_reo_queue) +
  1193. (10 * sizeof(struct rx_reo_queue_ext)) +
  1194. sizeof(struct rx_reo_queue_1k);
  1195. }
  1196. /**
  1197. * hal_rx_tlv_msdu_done_copy_get_5332() - Get msdu done copy bit from rx_tlv
  1198. * @buf: pointer the tx_tlv
  1199. *
  1200. * Return: msdu done copy bit
  1201. */
  1202. static inline uint32_t hal_rx_tlv_msdu_done_copy_get_5332(uint8_t *buf)
  1203. {
  1204. return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf);
  1205. }
  1206. static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc)
  1207. {
  1208. /* init and setup */
  1209. hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
  1210. hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
  1211. hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
  1212. hal_soc->ops->hal_get_window_address = hal_get_window_address_5332;
  1213. hal_soc->ops->hal_cmem_write = hal_cmem_write_5332;
  1214. /* tx */
  1215. hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5332;
  1216. hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5332;
  1217. hal_soc->ops->hal_tx_comp_get_status =
  1218. hal_tx_comp_get_status_generic_be;
  1219. hal_soc->ops->hal_tx_init_cmd_credit_ring =
  1220. hal_tx_init_cmd_credit_ring_5332;
  1221. hal_soc->ops->hal_tx_set_ppe_cmn_cfg = NULL;
  1222. hal_soc->ops->hal_tx_set_ppe_vp_entry = NULL;
  1223. hal_soc->ops->hal_tx_set_ppe_pri2tid = NULL;
  1224. hal_soc->ops->hal_tx_update_ppe_pri2tid = NULL;
  1225. hal_soc->ops->hal_tx_dump_ppe_vp_entry = NULL;
  1226. hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = NULL;
  1227. hal_soc->ops->hal_tx_enable_pri2tid_map = NULL;
  1228. hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg = NULL;
  1229. hal_soc->ops->hal_tx_config_rbm_mapping_be =
  1230. hal_tx_config_rbm_mapping_be_5332;
  1231. /* rx */
  1232. hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be;
  1233. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
  1234. hal_rx_mon_hw_desc_get_mpdu_status_be;
  1235. hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5332;
  1236. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
  1237. hal_rx_proc_phyrx_other_receive_info_tlv_5332;
  1238. hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5332;
  1239. hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
  1240. hal_rx_dump_mpdu_start_tlv_5332;
  1241. hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_5332;
  1242. hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5332;
  1243. hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be;
  1244. hal_soc->ops->hal_rx_msdu_start_reception_type_get =
  1245. hal_rx_tlv_reception_type_get_be;
  1246. hal_soc->ops->hal_rx_msdu_end_da_idx_get =
  1247. hal_rx_msdu_end_da_idx_get_be;
  1248. hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
  1249. hal_rx_msdu_desc_info_get_ptr_5332;
  1250. hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
  1251. hal_rx_link_desc_msdu0_ptr_5332;
  1252. hal_soc->ops->hal_reo_status_get_header =
  1253. hal_reo_status_get_header_5332;
  1254. #ifdef WLAN_PKT_CAPTURE_RX_2_0
  1255. hal_soc->ops->hal_rx_status_get_tlv_info =
  1256. hal_rx_status_get_tlv_info_wrapper_be;
  1257. #endif
  1258. hal_soc->ops->hal_rx_wbm_err_info_get =
  1259. hal_rx_wbm_err_info_get_generic_be;
  1260. hal_soc->ops->hal_tx_set_pcp_tid_map =
  1261. hal_tx_set_pcp_tid_map_generic_be;
  1262. hal_soc->ops->hal_tx_update_pcp_tid_map =
  1263. hal_tx_update_pcp_tid_generic_be;
  1264. hal_soc->ops->hal_tx_set_tidmap_prty =
  1265. hal_tx_update_tidmap_prty_generic_be;
  1266. hal_soc->ops->hal_rx_get_rx_fragment_number =
  1267. hal_rx_get_rx_fragment_number_be,
  1268. hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
  1269. hal_rx_tlv_da_is_mcbc_get_be;
  1270. hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err =
  1271. hal_rx_tlv_is_tkip_mic_err_get_be;
  1272. hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
  1273. hal_rx_tlv_sa_is_valid_get_be;
  1274. hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be;
  1275. hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be;
  1276. hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
  1277. hal_rx_tlv_l3_hdr_padding_get_be;
  1278. hal_soc->ops->hal_rx_encryption_info_valid =
  1279. hal_rx_encryption_info_valid_be;
  1280. hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be;
  1281. hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
  1282. hal_rx_tlv_first_msdu_get_be;
  1283. hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
  1284. hal_rx_tlv_da_is_valid_get_be;
  1285. hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
  1286. hal_rx_tlv_last_msdu_get_be;
  1287. hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
  1288. hal_rx_get_mpdu_mac_ad4_valid_be;
  1289. hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
  1290. hal_rx_mpdu_start_sw_peer_id_get_be;
  1291. hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
  1292. hal_rx_msdu_peer_meta_data_get_be;
  1293. #ifndef CONFIG_WORD_BASED_TLV
  1294. hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be;
  1295. hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
  1296. hal_rx_mpdu_info_ampdu_flag_get_be;
  1297. hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
  1298. hal_rx_hw_desc_get_ppduid_get_be;
  1299. hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
  1300. hal_rx_attn_phy_ppdu_id_get_be;
  1301. hal_soc->ops->hal_rx_get_filter_category =
  1302. hal_rx_get_filter_category_be;
  1303. #endif
  1304. hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be;
  1305. hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be;
  1306. hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be;
  1307. hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
  1308. hal_rx_get_mpdu_frame_control_valid_be;
  1309. hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be;
  1310. hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be;
  1311. hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be;
  1312. hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
  1313. hal_rx_get_mpdu_sequence_control_valid_be;
  1314. hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be;
  1315. hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be;
  1316. hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
  1317. hal_rx_mpdu_start_mpdu_qos_control_valid_get_be;
  1318. hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
  1319. hal_rx_msdu_end_sa_sw_peer_id_get_be;
  1320. hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
  1321. hal_rx_msdu0_buffer_addr_lsb_5332;
  1322. hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
  1323. hal_rx_msdu_desc_info_ptr_get_5332;
  1324. hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5332;
  1325. hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5332;
  1326. hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be;
  1327. hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be;
  1328. hal_soc->ops->hal_rx_get_mac_addr2_valid =
  1329. hal_rx_get_mac_addr2_valid_be;
  1330. hal_soc->ops->hal_reo_config = hal_reo_config_5332;
  1331. hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be;
  1332. hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
  1333. hal_rx_msdu_flow_idx_invalid_be;
  1334. hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
  1335. hal_rx_msdu_flow_idx_timeout_be;
  1336. hal_soc->ops->hal_rx_msdu_fse_metadata_get =
  1337. hal_rx_msdu_fse_metadata_get_be;
  1338. hal_soc->ops->hal_rx_msdu_cce_match_get =
  1339. hal_rx_msdu_cce_match_get_be;
  1340. hal_soc->ops->hal_rx_msdu_cce_metadata_get =
  1341. hal_rx_msdu_cce_metadata_get_be;
  1342. hal_soc->ops->hal_rx_msdu_get_flow_params =
  1343. hal_rx_msdu_get_flow_params_be;
  1344. hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be;
  1345. hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be;
  1346. #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
  1347. hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5332;
  1348. hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5332;
  1349. #else
  1350. hal_soc->ops->hal_rx_get_bb_info = NULL;
  1351. hal_soc->ops->hal_rx_get_rtt_info = NULL;
  1352. #endif
  1353. /* rx - msdu fast path info fields */
  1354. hal_soc->ops->hal_rx_msdu_packet_metadata_get =
  1355. hal_rx_msdu_packet_metadata_get_generic_be;
  1356. hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
  1357. hal_rx_mpdu_start_tlv_tag_valid_be;
  1358. hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
  1359. hal_rx_wbm_err_msdu_continuation_get_5332;
  1360. /* rx - TLV struct offsets */
  1361. hal_soc->ops->hal_rx_msdu_end_offset_get =
  1362. hal_rx_msdu_end_offset_get_generic;
  1363. hal_soc->ops->hal_rx_mpdu_start_offset_get =
  1364. hal_rx_mpdu_start_offset_get_generic;
  1365. #ifndef NO_RX_PKT_HDR_TLV
  1366. hal_soc->ops->hal_rx_pkt_tlv_offset_get =
  1367. hal_rx_pkt_tlv_offset_get_generic;
  1368. #endif
  1369. hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5332;
  1370. hal_soc->ops->hal_rx_flow_get_tuple_info =
  1371. hal_rx_flow_get_tuple_info_be;
  1372. hal_soc->ops->hal_rx_flow_delete_entry =
  1373. hal_rx_flow_delete_entry_be;
  1374. hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be;
  1375. hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
  1376. hal_compute_reo_remap_ix2_ix3_5332;
  1377. hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
  1378. hal_rx_msdu_get_reo_destination_indication_be;
  1379. hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be;
  1380. hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
  1381. hal_rx_msdu_is_wlan_mcast_generic_be;
  1382. hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_5332;
  1383. hal_soc->ops->hal_rx_tlv_decap_format_get =
  1384. hal_rx_tlv_decap_format_get_be;
  1385. #ifdef RECEIVE_OFFLOAD
  1386. hal_soc->ops->hal_rx_tlv_get_offload_info =
  1387. hal_rx_tlv_get_offload_info_be;
  1388. hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be;
  1389. hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be;
  1390. #endif
  1391. hal_soc->ops->hal_rx_tlv_msdu_done_get =
  1392. hal_rx_tlv_msdu_done_copy_get_5332;
  1393. hal_soc->ops->hal_rx_tlv_msdu_len_get =
  1394. hal_rx_msdu_start_msdu_len_get_be;
  1395. hal_soc->ops->hal_rx_get_frame_ctrl_field =
  1396. hal_rx_get_frame_ctrl_field_be;
  1397. hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be;
  1398. hal_soc->ops->hal_rx_tlv_msdu_len_set =
  1399. hal_rx_msdu_start_msdu_len_set_be;
  1400. hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be;
  1401. hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be;
  1402. hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be;
  1403. hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be;
  1404. hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be;
  1405. hal_soc->ops->hal_rx_tlv_decrypt_err_get =
  1406. hal_rx_tlv_decrypt_err_get_be;
  1407. hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be;
  1408. hal_soc->ops->hal_rx_tlv_get_is_decrypted =
  1409. hal_rx_tlv_get_is_decrypted_be;
  1410. hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be;
  1411. hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be;
  1412. hal_soc->ops->hal_rx_priv_info_set_in_tlv =
  1413. hal_rx_priv_info_set_in_tlv_be;
  1414. hal_soc->ops->hal_rx_priv_info_get_from_tlv =
  1415. hal_rx_priv_info_get_from_tlv_be;
  1416. hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be;
  1417. hal_soc->ops->hal_reo_setup = hal_reo_setup_5332;
  1418. #ifdef REO_SHARED_QREF_TABLE_EN
  1419. hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be;
  1420. hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be;
  1421. hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be;
  1422. hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be;
  1423. hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be;
  1424. #endif
  1425. /* Overwrite the default BE ops */
  1426. hal_soc->ops->hal_get_rx_max_ba_window =
  1427. hal_get_rx_max_ba_window_qca5332;
  1428. hal_soc->ops->hal_get_reo_qdesc_size = hal_qca5332_get_reo_qdesc_size;
  1429. /* TX MONITOR */
  1430. #ifdef WLAN_PKT_CAPTURE_TX_2_0
  1431. hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv =
  1432. hal_txmon_is_mon_buf_addr_tlv_generic_be;
  1433. hal_soc->ops->hal_txmon_populate_packet_info =
  1434. hal_txmon_populate_packet_info_generic_be;
  1435. hal_soc->ops->hal_txmon_status_parse_tlv =
  1436. hal_txmon_status_parse_tlv_generic_be;
  1437. hal_soc->ops->hal_txmon_status_get_num_users =
  1438. hal_txmon_status_get_num_users_generic_be;
  1439. #if defined(TX_MONITOR_WORD_MASK)
  1440. hal_soc->ops->hal_txmon_get_word_mask =
  1441. hal_txmon_get_word_mask_qca5332;
  1442. #else
  1443. hal_soc->ops->hal_txmon_get_word_mask =
  1444. hal_txmon_get_word_mask_generic_be;
  1445. #endif /* TX_MONITOR_WORD_MASK */
  1446. #endif /* WLAN_PKT_CAPTURE_TX_2_0 */
  1447. hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
  1448. hal_soc->ops->hal_tx_vdev_mismatch_routing_set =
  1449. hal_tx_vdev_mismatch_routing_set_generic_be;
  1450. hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set =
  1451. hal_tx_mcast_mlo_reinject_routing_set_generic_be;
  1452. hal_soc->ops->hal_get_ba_aging_timeout =
  1453. hal_get_ba_aging_timeout_be_generic;
  1454. hal_soc->ops->hal_setup_link_idle_list =
  1455. hal_setup_link_idle_list_generic_be;
  1456. hal_soc->ops->hal_cookie_conversion_reg_cfg_be =
  1457. hal_cookie_conversion_reg_cfg_generic_be;
  1458. hal_soc->ops->hal_set_ba_aging_timeout =
  1459. hal_set_ba_aging_timeout_be_generic;
  1460. hal_soc->ops->hal_tx_populate_bank_register =
  1461. hal_tx_populate_bank_register_be;
  1462. hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
  1463. hal_tx_vdev_mcast_ctrl_set_be;
  1464. hal_soc->ops->hal_get_tsf2_scratch_reg =
  1465. hal_get_tsf2_scratch_reg_qca5332;
  1466. hal_soc->ops->hal_get_tqm_scratch_reg =
  1467. hal_get_tqm_scratch_reg_qca5332;
  1468. #ifdef CONFIG_WORD_BASED_TLV
  1469. hal_soc->ops->hal_rx_mpdu_start_wmask_get =
  1470. hal_rx_mpdu_start_wmask_get_be;
  1471. hal_soc->ops->hal_rx_msdu_end_wmask_get =
  1472. hal_rx_msdu_end_wmask_get_be;
  1473. #endif
  1474. };
  1475. struct hal_hw_srng_config hw_srng_table_5332[] = {
  1476. /* TODO: max_rings can populated by querying HW capabilities */
  1477. { /* REO_DST */
  1478. .start_ring_id = HAL_SRNG_REO2SW1,
  1479. .max_rings = 8,
  1480. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1481. .lmac_ring = FALSE,
  1482. .ring_dir = HAL_SRNG_DST_RING,
  1483. .reg_start = {
  1484. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
  1485. REO_REG_REG_BASE),
  1486. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
  1487. REO_REG_REG_BASE)
  1488. },
  1489. .reg_size = {
  1490. HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
  1491. HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
  1492. HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
  1493. HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
  1494. },
  1495. .max_size =
  1496. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1497. HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
  1498. },
  1499. { /* REO_EXCEPTION */
  1500. /* Designating REO2SW0 ring as exception ring. This ring is
  1501. * similar to other REO2SW rings though it is named as REO2SW0.
  1502. * Any of theREO2SW rings can be used as exception ring.
  1503. */
  1504. .start_ring_id = HAL_SRNG_REO2SW0,
  1505. .max_rings = 1,
  1506. .entry_size = sizeof(struct reo_destination_ring) >> 2,
  1507. .lmac_ring = FALSE,
  1508. .ring_dir = HAL_SRNG_DST_RING,
  1509. .reg_start = {
  1510. HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(
  1511. REO_REG_REG_BASE),
  1512. HWIO_REO_R2_REO2SW0_RING_HP_ADDR(
  1513. REO_REG_REG_BASE)
  1514. },
  1515. /* Single ring - provide ring size if multiple rings of this
  1516. * type are supported
  1517. */
  1518. .reg_size = {},
  1519. .max_size =
  1520. HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >>
  1521. HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT,
  1522. },
  1523. { /* REO_REINJECT */
  1524. .start_ring_id = HAL_SRNG_SW2REO,
  1525. .max_rings = 4,
  1526. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1527. .lmac_ring = FALSE,
  1528. .ring_dir = HAL_SRNG_SRC_RING,
  1529. .reg_start = {
  1530. HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
  1531. REO_REG_REG_BASE),
  1532. HWIO_REO_R2_SW2REO_RING_HP_ADDR(
  1533. REO_REG_REG_BASE)
  1534. },
  1535. /* Single ring - provide ring size if multiple rings of this
  1536. * type are supported
  1537. */
  1538. .reg_size = {
  1539. HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) -
  1540. HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0),
  1541. HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) -
  1542. HWIO_REO_R2_SW2REO_RING_HP_ADDR(0)
  1543. },
  1544. .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
  1545. HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
  1546. },
  1547. { /* REO_CMD */
  1548. .start_ring_id = HAL_SRNG_REO_CMD,
  1549. .max_rings = 1,
  1550. .entry_size = (sizeof(struct tlv_32_hdr) +
  1551. sizeof(struct reo_get_queue_stats)) >> 2,
  1552. .lmac_ring = FALSE,
  1553. .ring_dir = HAL_SRNG_SRC_RING,
  1554. .reg_start = {
  1555. HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
  1556. REO_REG_REG_BASE),
  1557. HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
  1558. REO_REG_REG_BASE),
  1559. },
  1560. /* Single ring - provide ring size if multiple rings of this
  1561. * type are supported
  1562. */
  1563. .reg_size = {},
  1564. .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
  1565. HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
  1566. },
  1567. { /* REO_STATUS */
  1568. .start_ring_id = HAL_SRNG_REO_STATUS,
  1569. .max_rings = 1,
  1570. .entry_size = (sizeof(struct tlv_32_hdr) +
  1571. sizeof(struct reo_get_queue_stats_status)) >> 2,
  1572. .lmac_ring = FALSE,
  1573. .ring_dir = HAL_SRNG_DST_RING,
  1574. .reg_start = {
  1575. HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
  1576. REO_REG_REG_BASE),
  1577. HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
  1578. REO_REG_REG_BASE),
  1579. },
  1580. /* Single ring - provide ring size if multiple rings of this
  1581. * type are supported
  1582. */
  1583. .reg_size = {},
  1584. .max_size =
  1585. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1586. HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1587. },
  1588. { /* TCL_DATA */
  1589. .start_ring_id = HAL_SRNG_SW2TCL1,
  1590. .max_rings = 6,
  1591. .entry_size = sizeof(struct tcl_data_cmd) >> 2,
  1592. .lmac_ring = FALSE,
  1593. .ring_dir = HAL_SRNG_SRC_RING,
  1594. .reg_start = {
  1595. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
  1596. MAC_TCL_REG_REG_BASE),
  1597. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
  1598. MAC_TCL_REG_REG_BASE),
  1599. },
  1600. .reg_size = {
  1601. HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
  1602. HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
  1603. HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
  1604. HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
  1605. },
  1606. .max_size =
  1607. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1608. HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
  1609. },
  1610. { /* TCL_CMD/CREDIT */
  1611. /* qca8074v2 and qca5332 uses this ring for data commands */
  1612. .start_ring_id = HAL_SRNG_SW2TCL_CMD,
  1613. .max_rings = 1,
  1614. .entry_size = sizeof(struct tcl_data_cmd) >> 2,
  1615. .lmac_ring = FALSE,
  1616. .ring_dir = HAL_SRNG_SRC_RING,
  1617. .reg_start = {
  1618. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
  1619. MAC_TCL_REG_REG_BASE),
  1620. HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
  1621. MAC_TCL_REG_REG_BASE),
  1622. },
  1623. /* Single ring - provide ring size if multiple rings of this
  1624. * type are supported
  1625. */
  1626. .reg_size = {},
  1627. .max_size =
  1628. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
  1629. HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
  1630. },
  1631. { /* TCL_STATUS */
  1632. .start_ring_id = HAL_SRNG_TCL_STATUS,
  1633. .max_rings = 1,
  1634. .entry_size = (sizeof(struct tlv_32_hdr) +
  1635. sizeof(struct tcl_status_ring)) >> 2,
  1636. .lmac_ring = FALSE,
  1637. .ring_dir = HAL_SRNG_DST_RING,
  1638. .reg_start = {
  1639. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
  1640. MAC_TCL_REG_REG_BASE),
  1641. HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
  1642. MAC_TCL_REG_REG_BASE),
  1643. },
  1644. /* Single ring - provide ring size if multiple rings of this
  1645. * type are supported
  1646. */
  1647. .reg_size = {},
  1648. .max_size =
  1649. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
  1650. HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
  1651. },
  1652. { /* CE_SRC */
  1653. .start_ring_id = HAL_SRNG_CE_0_SRC,
  1654. .max_rings = 16,
  1655. .entry_size = sizeof(struct ce_src_desc) >> 2,
  1656. .lmac_ring = FALSE,
  1657. .ring_dir = HAL_SRNG_SRC_RING,
  1658. .reg_start = {
  1659. HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(
  1660. WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
  1661. HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(
  1662. WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
  1663. },
  1664. .reg_size = {
  1665. WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
  1666. WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
  1667. WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
  1668. WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
  1669. },
  1670. .max_size =
  1671. HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >>
  1672. HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT,
  1673. },
  1674. { /* CE_DST */
  1675. .start_ring_id = HAL_SRNG_CE_0_DST,
  1676. .max_rings = 16,
  1677. .entry_size = 8 >> 2,
  1678. /*TODO: entry_size above should actually be
  1679. * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
  1680. * of struct ce_dst_desc in HW header files
  1681. */
  1682. .lmac_ring = FALSE,
  1683. .ring_dir = HAL_SRNG_SRC_RING,
  1684. .reg_start = {
  1685. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
  1686. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
  1687. HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
  1688. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
  1689. },
  1690. .reg_size = {
  1691. WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
  1692. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
  1693. WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
  1694. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
  1695. },
  1696. .max_size =
  1697. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
  1698. HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
  1699. },
  1700. { /* CE_DST_STATUS */
  1701. .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
  1702. .max_rings = 16,
  1703. .entry_size = sizeof(struct ce_stat_desc) >> 2,
  1704. .lmac_ring = FALSE,
  1705. .ring_dir = HAL_SRNG_DST_RING,
  1706. .reg_start = {
  1707. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
  1708. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
  1709. HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
  1710. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
  1711. },
  1712. /* TODO: check destination status ring registers */
  1713. .reg_size = {
  1714. WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
  1715. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
  1716. WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
  1717. WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
  1718. },
  1719. .max_size =
  1720. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
  1721. HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
  1722. },
  1723. { /* WBM_IDLE_LINK */
  1724. .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
  1725. .max_rings = 1,
  1726. .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
  1727. .lmac_ring = FALSE,
  1728. .ring_dir = HAL_SRNG_SRC_RING,
  1729. .reg_start = {
  1730. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
  1731. HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE),
  1732. },
  1733. /* Single ring - provide ring size if multiple rings of this
  1734. * type are supported
  1735. */
  1736. .reg_size = {},
  1737. .max_size =
  1738. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
  1739. HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
  1740. },
  1741. { /* SW2WBM_RELEASE */
  1742. .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
  1743. .max_rings = 1,
  1744. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  1745. .lmac_ring = FALSE,
  1746. .ring_dir = HAL_SRNG_SRC_RING,
  1747. .reg_start = {
  1748. HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
  1749. HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
  1750. },
  1751. /* Single ring - provide ring size if multiple rings of this
  1752. * type are supported
  1753. */
  1754. .reg_size = {},
  1755. .max_size =
  1756. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  1757. HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  1758. },
  1759. { /* WBM2SW_RELEASE */
  1760. .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
  1761. .max_rings = 8,
  1762. .entry_size = sizeof(struct wbm_release_ring) >> 2,
  1763. .lmac_ring = FALSE,
  1764. .ring_dir = HAL_SRNG_DST_RING,
  1765. .reg_start = {
  1766. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
  1767. WBM_REG_REG_BASE),
  1768. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
  1769. WBM_REG_REG_BASE),
  1770. },
  1771. .reg_size = {
  1772. HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(
  1773. WBM_REG_REG_BASE) -
  1774. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
  1775. WBM_REG_REG_BASE),
  1776. HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(
  1777. WBM_REG_REG_BASE) -
  1778. HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
  1779. WBM_REG_REG_BASE),
  1780. },
  1781. .max_size =
  1782. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
  1783. HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
  1784. },
  1785. { /* RXDMA_BUF */
  1786. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
  1787. #ifdef IPA_OFFLOAD
  1788. .max_rings = 3,
  1789. #else
  1790. .max_rings = 3,
  1791. #endif
  1792. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1793. .lmac_ring = TRUE,
  1794. .ring_dir = HAL_SRNG_SRC_RING,
  1795. /* reg_start is not set because LMAC rings are not accessed
  1796. * from host
  1797. */
  1798. .reg_start = {},
  1799. .reg_size = {},
  1800. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1801. },
  1802. { /* RXDMA_DST */
  1803. .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
  1804. .max_rings = 0,
  1805. .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/,
  1806. .lmac_ring = TRUE,
  1807. .ring_dir = HAL_SRNG_DST_RING,
  1808. /* reg_start is not set because LMAC rings are not accessed
  1809. * from host
  1810. */
  1811. .reg_start = {},
  1812. .reg_size = {},
  1813. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1814. },
  1815. #ifdef WLAN_PKT_CAPTURE_RX_2_0
  1816. { /* RXDMA_MONITOR_BUF */
  1817. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
  1818. .max_rings = 1,
  1819. .entry_size = sizeof(struct mon_ingress_ring) >> 2,
  1820. .lmac_ring = TRUE,
  1821. .ring_dir = HAL_SRNG_SRC_RING,
  1822. /* reg_start is not set because LMAC rings are not accessed
  1823. * from host
  1824. */
  1825. .reg_start = {},
  1826. .reg_size = {},
  1827. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  1828. },
  1829. #else
  1830. {},
  1831. #endif
  1832. { /* RXDMA_MONITOR_STATUS */
  1833. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
  1834. .max_rings = 0,
  1835. .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
  1836. .lmac_ring = TRUE,
  1837. .ring_dir = HAL_SRNG_SRC_RING,
  1838. /* reg_start is not set because LMAC rings are not accessed
  1839. * from host
  1840. */
  1841. .reg_start = {},
  1842. .reg_size = {},
  1843. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1844. },
  1845. #ifdef WLAN_PKT_CAPTURE_RX_2_0
  1846. { /* RXDMA_MONITOR_DST */
  1847. .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0,
  1848. .max_rings = 2,
  1849. .entry_size = sizeof(struct mon_destination_ring) >> 2,
  1850. .lmac_ring = TRUE,
  1851. .ring_dir = HAL_SRNG_DST_RING,
  1852. /* reg_start is not set because LMAC rings are not accessed
  1853. * from host
  1854. */
  1855. .reg_start = {},
  1856. .reg_size = {},
  1857. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  1858. },
  1859. #else
  1860. {},
  1861. #endif
  1862. { /* RXDMA_MONITOR_DESC */
  1863. .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
  1864. .max_rings = 0,
  1865. .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/,
  1866. .lmac_ring = TRUE,
  1867. .ring_dir = HAL_SRNG_DST_RING,
  1868. /* reg_start is not set because LMAC rings are not accessed
  1869. * from host
  1870. */
  1871. .reg_start = {},
  1872. .reg_size = {},
  1873. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  1874. },
  1875. { /* DIR_BUF_RX_DMA_SRC */
  1876. .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
  1877. /* one ring for spectral, one ring for cfr and
  1878. * another one ring for txbf cv upload.
  1879. */
  1880. .max_rings = 3,
  1881. .entry_size = 2,
  1882. .lmac_ring = TRUE,
  1883. .ring_dir = HAL_SRNG_SRC_RING,
  1884. /* reg_start is not set because LMAC rings are not accessed
  1885. * from host
  1886. */
  1887. .reg_start = {},
  1888. .reg_size = {},
  1889. .max_size = HAL_RXDMA_MAX_RING_SIZE,
  1890. },
  1891. #ifdef WLAN_FEATURE_CIF_CFR
  1892. { /* WIFI_POS_SRC */
  1893. .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
  1894. .max_rings = 1,
  1895. .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
  1896. .lmac_ring = TRUE,
  1897. .ring_dir = HAL_SRNG_SRC_RING,
  1898. /* reg_start is not set because LMAC rings are not accessed
  1899. * from host
  1900. */
  1901. .reg_start = {},
  1902. .reg_size = {},
  1903. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  1904. },
  1905. #endif
  1906. /* PPE rings are not present in Miami. Added dummy entries to preserve
  1907. * Array Index
  1908. */
  1909. /* REO2PPE */
  1910. {},
  1911. /* PPE2TCL */
  1912. {},
  1913. /* PPE_RELEASE */
  1914. {},
  1915. #ifdef WLAN_PKT_CAPTURE_TX_2_0
  1916. { /* TX_MONITOR_BUF */
  1917. .start_ring_id = HAL_SRNG_SW2TXMON_BUF0,
  1918. .max_rings = 1,
  1919. .entry_size = sizeof(struct mon_ingress_ring) >> 2,
  1920. .lmac_ring = TRUE,
  1921. .ring_dir = HAL_SRNG_SRC_RING,
  1922. /* reg_start is not set because LMAC rings are not accessed
  1923. * from host
  1924. */
  1925. .reg_start = {},
  1926. .reg_size = {},
  1927. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  1928. },
  1929. { /* TX_MONITOR_DST */
  1930. .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0,
  1931. .max_rings = 2,
  1932. .entry_size = sizeof(struct mon_destination_ring) >> 2,
  1933. .lmac_ring = TRUE,
  1934. .ring_dir = HAL_SRNG_DST_RING,
  1935. /* reg_start is not set because LMAC rings are not accessed
  1936. * from host
  1937. */
  1938. .reg_start = {},
  1939. .reg_size = {},
  1940. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  1941. },
  1942. #else
  1943. {},
  1944. {},
  1945. #endif
  1946. { /* SW2RXDMA */
  1947. .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
  1948. .max_rings = 3,
  1949. .entry_size = sizeof(struct reo_entrance_ring) >> 2,
  1950. .lmac_ring = TRUE,
  1951. .ring_dir = HAL_SRNG_SRC_RING,
  1952. /* reg_start is not set because LMAC rings are not accessed
  1953. * from host
  1954. */
  1955. .reg_start = {},
  1956. .reg_size = {},
  1957. .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
  1958. .dmac_cmn_ring = TRUE,
  1959. },
  1960. { /* SW2RXDMA_LINK_RELEASE */ 0},
  1961. };
  1962. /**
  1963. * hal_srng_hw_reg_offset_init_qca5332() - Initialize the HW srng reg offset
  1964. * applicable only for qca5332
  1965. * @hal_soc: HAL Soc handle
  1966. *
  1967. * Return: None
  1968. */
  1969. static inline void hal_srng_hw_reg_offset_init_qca5332(struct hal_soc *hal_soc)
  1970. {
  1971. int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset;
  1972. hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB),
  1973. hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB),
  1974. hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA),
  1975. hw_reg_offset[DST_PRODUCER_INT2_SETUP] =
  1976. REG_OFFSET(DST, PRODUCER_INT2_SETUP);
  1977. }
  1978. /**
  1979. * hal_qca5332_attach() - Attach 5332 target specific hal_soc ops,
  1980. * offset and srng table
  1981. * @hal_soc: hal_soc handle
  1982. *
  1983. * Return: void
  1984. */
  1985. void hal_qca5332_attach(struct hal_soc *hal_soc)
  1986. {
  1987. hal_soc->hw_srng_table = hw_srng_table_5332;
  1988. hal_srng_hw_reg_offset_init_generic(hal_soc);
  1989. hal_srng_hw_reg_offset_init_qca5332(hal_soc);
  1990. hal_hw_txrx_default_ops_attach_be(hal_soc);
  1991. hal_hw_txrx_ops_attach_qca5332(hal_soc);
  1992. hal_soc->dmac_cmn_src_rxbuf_ring = true;
  1993. }