main.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2017-2020, 2021, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef __MAIN_H__
  6. #define __MAIN_H__
  7. #include <linux/irqreturn.h>
  8. #include <linux/kobject.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/ipc_logging.h>
  11. #include <linux/power_supply.h>
  12. #ifdef CONFIG_CNSS_OUT_OF_TREE
  13. #include "icnss2.h"
  14. #else
  15. #include <soc/qcom/icnss2.h>
  16. #endif
  17. #include "wlan_firmware_service_v01.h"
  18. #include <linux/mailbox_client.h>
  19. #define WCN6750_DEVICE_ID 0x6750
  20. #define ADRASTEA_DEVICE_ID 0xabcd
  21. #define THERMAL_NAME_LENGTH 20
  22. #define ICNSS_SMEM_VALUE_MASK 0xFFFFFFFF
  23. #define ICNSS_SMEM_SEQ_NO_POS 16
  24. #define QCA6750_PATH_PREFIX "qca6750/"
  25. #define ADRASTEA_PATH_PREFIX "adrastea/"
  26. #define ICNSS_MAX_FILE_NAME 35
  27. #define ICNSS_PCI_EP_WAKE_OFFSET 4
  28. #define ICNSS_DISABLE_M3_SSR 0
  29. #define ICNSS_ENABLE_M3_SSR 1
  30. #define WLAN_RF_SLATE 0
  31. #define WLAN_RF_APACHE 1
  32. extern uint64_t dynamic_feature_mask;
  33. enum icnss_bdf_type {
  34. ICNSS_BDF_BIN,
  35. ICNSS_BDF_ELF,
  36. ICNSS_BDF_REGDB = 4,
  37. };
  38. struct icnss_control_params {
  39. unsigned long quirks;
  40. unsigned int qmi_timeout;
  41. unsigned int bdf_type;
  42. };
  43. enum icnss_driver_event_type {
  44. ICNSS_DRIVER_EVENT_SERVER_ARRIVE,
  45. ICNSS_DRIVER_EVENT_SERVER_EXIT,
  46. ICNSS_DRIVER_EVENT_FW_READY_IND,
  47. ICNSS_DRIVER_EVENT_REGISTER_DRIVER,
  48. ICNSS_DRIVER_EVENT_UNREGISTER_DRIVER,
  49. ICNSS_DRIVER_EVENT_PD_SERVICE_DOWN,
  50. ICNSS_DRIVER_EVENT_FW_EARLY_CRASH_IND,
  51. ICNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  52. ICNSS_DRIVER_EVENT_IDLE_RESTART,
  53. ICNSS_DRIVER_EVENT_FW_INIT_DONE_IND,
  54. ICNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
  55. ICNSS_DRIVER_EVENT_QDSS_TRACE_SAVE,
  56. ICNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
  57. ICNSS_DRIVER_EVENT_M3_DUMP_UPLOAD_REQ,
  58. ICNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
  59. ICNSS_DRIVER_EVENT_SUBSYS_RESTART_LEVEL,
  60. ICNSS_DRIVER_EVENT_MAX,
  61. };
  62. enum icnss_soc_wake_event_type {
  63. ICNSS_SOC_WAKE_REQUEST_EVENT,
  64. ICNSS_SOC_WAKE_RELEASE_EVENT,
  65. ICNSS_SOC_WAKE_EVENT_MAX,
  66. };
  67. struct icnss_event_server_arrive_data {
  68. unsigned int node;
  69. unsigned int port;
  70. };
  71. struct icnss_event_pd_service_down_data {
  72. bool crashed;
  73. bool fw_rejuvenate;
  74. };
  75. struct icnss_driver_event {
  76. struct list_head list;
  77. enum icnss_driver_event_type type;
  78. bool sync;
  79. struct completion complete;
  80. int ret;
  81. void *data;
  82. };
  83. struct icnss_soc_wake_event {
  84. struct list_head list;
  85. enum icnss_soc_wake_event_type type;
  86. bool sync;
  87. struct completion complete;
  88. int ret;
  89. void *data;
  90. };
  91. enum icnss_driver_state {
  92. ICNSS_WLFW_CONNECTED,
  93. ICNSS_POWER_ON,
  94. ICNSS_FW_READY,
  95. ICNSS_DRIVER_PROBED,
  96. ICNSS_FW_TEST_MODE,
  97. ICNSS_PM_SUSPEND,
  98. ICNSS_PM_SUSPEND_NOIRQ,
  99. ICNSS_SSR_REGISTERED,
  100. ICNSS_PDR_REGISTERED,
  101. ICNSS_PD_RESTART,
  102. ICNSS_WLFW_EXISTS,
  103. ICNSS_SHUTDOWN_DONE,
  104. ICNSS_HOST_TRIGGERED_PDR,
  105. ICNSS_FW_DOWN,
  106. ICNSS_DRIVER_UNLOADING,
  107. ICNSS_REJUVENATE,
  108. ICNSS_MODE_ON,
  109. ICNSS_BLOCK_SHUTDOWN,
  110. ICNSS_PDR,
  111. ICNSS_DEL_SERVER,
  112. ICNSS_COLD_BOOT_CAL,
  113. ICNSS_QMI_DMS_CONNECTED,
  114. };
  115. struct ce_irq_list {
  116. int irq;
  117. irqreturn_t (*handler)(int irq, void *priv);
  118. };
  119. struct icnss_vreg_cfg {
  120. const char *name;
  121. u32 min_uv;
  122. u32 max_uv;
  123. u32 load_ua;
  124. u32 delay_us;
  125. u32 need_unvote;
  126. bool required;
  127. bool is_supported;
  128. };
  129. struct icnss_vreg_info {
  130. struct list_head list;
  131. struct regulator *reg;
  132. struct icnss_vreg_cfg cfg;
  133. u32 enabled;
  134. };
  135. struct icnss_cpr_info {
  136. const char *vreg_ol_cpr;
  137. u32 voltage;
  138. };
  139. enum icnss_vreg_type {
  140. ICNSS_VREG_PRIM,
  141. };
  142. struct icnss_clk_cfg {
  143. const char *name;
  144. u32 freq;
  145. u32 required;
  146. };
  147. struct icnss_battery_level {
  148. int lower_battery_threshold;
  149. int ldo_voltage;
  150. };
  151. struct icnss_clk_info {
  152. struct list_head list;
  153. struct clk *clk;
  154. struct icnss_clk_cfg cfg;
  155. u32 enabled;
  156. };
  157. struct icnss_fw_mem {
  158. size_t size;
  159. void *va;
  160. phys_addr_t pa;
  161. u8 valid;
  162. u32 type;
  163. unsigned long attrs;
  164. };
  165. enum icnss_smp2p_msg_id {
  166. ICNSS_RESET_MSG,
  167. ICNSS_POWER_SAVE_ENTER,
  168. ICNSS_POWER_SAVE_EXIT,
  169. ICNSS_TRIGGER_SSR,
  170. ICNSS_SOC_WAKE_REQ,
  171. ICNSS_SOC_WAKE_REL,
  172. ICNSS_PCI_EP_POWER_SAVE_ENTER,
  173. ICNSS_PCI_EP_POWER_SAVE_EXIT,
  174. };
  175. struct icnss_subsys_restart_level_data {
  176. uint8_t restart_level;
  177. };
  178. struct icnss_stats {
  179. struct {
  180. uint32_t posted;
  181. uint32_t processed;
  182. } events[ICNSS_DRIVER_EVENT_MAX];
  183. struct {
  184. u32 posted;
  185. u32 processed;
  186. } soc_wake_events[ICNSS_SOC_WAKE_EVENT_MAX];
  187. struct {
  188. uint32_t request;
  189. uint32_t free;
  190. uint32_t enable;
  191. uint32_t disable;
  192. } ce_irqs[ICNSS_MAX_IRQ_REGISTRATIONS];
  193. struct {
  194. uint32_t pdr_fw_crash;
  195. uint32_t pdr_host_error;
  196. uint32_t root_pd_crash;
  197. uint32_t root_pd_shutdown;
  198. } recovery;
  199. uint32_t pm_suspend;
  200. uint32_t pm_suspend_err;
  201. uint32_t pm_resume;
  202. uint32_t pm_resume_err;
  203. uint32_t pm_suspend_noirq;
  204. uint32_t pm_suspend_noirq_err;
  205. uint32_t pm_resume_noirq;
  206. uint32_t pm_resume_noirq_err;
  207. uint32_t pm_stay_awake;
  208. uint32_t pm_relax;
  209. uint32_t ind_register_req;
  210. uint32_t ind_register_resp;
  211. uint32_t ind_register_err;
  212. uint32_t msa_info_req;
  213. uint32_t msa_info_resp;
  214. uint32_t msa_info_err;
  215. uint32_t msa_ready_req;
  216. uint32_t msa_ready_resp;
  217. uint32_t msa_ready_err;
  218. uint32_t msa_ready_ind;
  219. uint32_t cap_req;
  220. uint32_t cap_resp;
  221. uint32_t cap_err;
  222. uint32_t pin_connect_result;
  223. uint32_t cfg_req;
  224. uint32_t cfg_resp;
  225. uint32_t cfg_req_err;
  226. uint32_t mode_req;
  227. uint32_t mode_resp;
  228. uint32_t mode_req_err;
  229. uint32_t ini_req;
  230. uint32_t ini_resp;
  231. uint32_t ini_req_err;
  232. u32 rejuvenate_ind;
  233. uint32_t rejuvenate_ack_req;
  234. uint32_t rejuvenate_ack_resp;
  235. uint32_t rejuvenate_ack_err;
  236. uint32_t device_info_req;
  237. uint32_t device_info_resp;
  238. uint32_t device_info_err;
  239. u32 exit_power_save_req;
  240. u32 exit_power_save_resp;
  241. u32 exit_power_save_err;
  242. u32 enter_power_save_req;
  243. u32 enter_power_save_resp;
  244. u32 enter_power_save_err;
  245. u32 soc_wake_req;
  246. u32 soc_wake_resp;
  247. u32 soc_wake_err;
  248. u32 restart_level_req;
  249. u32 restart_level_resp;
  250. u32 restart_level_err;
  251. };
  252. #define WLFW_MAX_TIMESTAMP_LEN 32
  253. #define WLFW_MAX_BUILD_ID_LEN 128
  254. #define WLFW_MAX_NUM_MEMORY_REGIONS 2
  255. #define WLFW_FUNCTION_NAME_LEN 129
  256. #define WLFW_MAX_DATA_SIZE 6144
  257. #define WLFW_MAX_STR_LEN 16
  258. #define WLFW_MAX_NUM_CE 12
  259. #define WLFW_MAX_NUM_SVC 24
  260. #define WLFW_MAX_NUM_SHADOW_REG 24
  261. #define WLFW_MAX_HANG_EVENT_DATA_SIZE 400
  262. struct wlfw_rf_chip_info {
  263. uint32_t chip_id;
  264. uint32_t chip_family;
  265. };
  266. struct wlfw_rf_board_info {
  267. uint32_t board_id;
  268. };
  269. struct wlfw_fw_version_info {
  270. uint32_t fw_version;
  271. char fw_build_timestamp[WLFW_MAX_TIMESTAMP_LEN + 1];
  272. };
  273. struct icnss_mem_region_info {
  274. uint64_t reg_addr;
  275. uint32_t size;
  276. uint8_t secure_flag;
  277. };
  278. struct icnss_msi_user {
  279. char *name;
  280. int num_vectors;
  281. u32 base_vector;
  282. };
  283. struct icnss_msi_config {
  284. int total_vectors;
  285. int total_users;
  286. struct icnss_msi_user *users;
  287. };
  288. struct icnss_thermal_cdev {
  289. struct list_head tcdev_list;
  290. int tcdev_id;
  291. unsigned long curr_thermal_state;
  292. unsigned long max_thermal_state;
  293. struct device_node *dev_node;
  294. struct thermal_cooling_device *tcdev;
  295. };
  296. enum smp2p_out_entry {
  297. ICNSS_SMP2P_OUT_POWER_SAVE,
  298. ICNSS_SMP2P_OUT_SOC_WAKE,
  299. ICNSS_SMP2P_OUT_EP_POWER_SAVE,
  300. ICNSS_SMP2P_OUT_MAX
  301. };
  302. static const char * const icnss_smp2p_str[] = {
  303. [ICNSS_SMP2P_OUT_POWER_SAVE] = "wlan-smp2p-out",
  304. [ICNSS_SMP2P_OUT_SOC_WAKE] = "wlan-soc-wake-smp2p-out",
  305. [ICNSS_SMP2P_OUT_EP_POWER_SAVE] = "wlan-ep-powersave-smp2p-out",
  306. };
  307. struct smp2p_out_info {
  308. unsigned short seq;
  309. unsigned int smem_bit;
  310. struct qcom_smem_state *smem_state;
  311. };
  312. struct icnss_dms_data {
  313. u8 mac_valid;
  314. u8 nv_mac_not_prov;
  315. u8 mac[QMI_WLFW_MAC_ADDR_SIZE_V01];
  316. };
  317. struct icnss_ramdump_info {
  318. int minor;
  319. char name[32];
  320. struct device *dev;
  321. };
  322. struct icnss_priv {
  323. uint32_t magic;
  324. struct platform_device *pdev;
  325. struct icnss_driver_ops *ops;
  326. struct ce_irq_list ce_irq_list[ICNSS_MAX_IRQ_REGISTRATIONS];
  327. struct list_head vreg_list;
  328. struct list_head clk_list;
  329. struct icnss_cpr_info cpr_info;
  330. unsigned long device_id;
  331. struct icnss_msi_config *msi_config;
  332. u32 msi_base_data;
  333. struct icnss_control_params ctrl_params;
  334. u8 cal_done;
  335. u8 use_prefix_path;
  336. u32 ce_irqs[ICNSS_MAX_IRQ_REGISTRATIONS];
  337. u32 srng_irqs[IWCN_MAX_IRQ_REGISTRATIONS];
  338. phys_addr_t mem_base_pa;
  339. void __iomem *mem_base_va;
  340. u32 mem_base_size;
  341. phys_addr_t mhi_state_info_pa;
  342. void __iomem *mhi_state_info_va;
  343. u32 mhi_state_info_size;
  344. struct iommu_domain *iommu_domain;
  345. dma_addr_t smmu_iova_start;
  346. size_t smmu_iova_len;
  347. dma_addr_t smmu_iova_ipa_start;
  348. dma_addr_t smmu_iova_ipa_current;
  349. size_t smmu_iova_ipa_len;
  350. struct qmi_handle qmi;
  351. struct qmi_handle qmi_dms;
  352. struct list_head event_list;
  353. struct list_head soc_wake_msg_list;
  354. spinlock_t event_lock;
  355. spinlock_t soc_wake_msg_lock;
  356. struct work_struct event_work;
  357. struct work_struct fw_recv_msg_work;
  358. struct work_struct soc_wake_msg_work;
  359. struct workqueue_struct *event_wq;
  360. struct workqueue_struct *soc_wake_wq;
  361. phys_addr_t msa_pa;
  362. phys_addr_t msi_addr_pa;
  363. dma_addr_t msi_addr_iova;
  364. uint32_t msa_mem_size;
  365. void *msa_va;
  366. unsigned long state;
  367. struct wlfw_rf_chip_info chip_info;
  368. uint32_t board_id;
  369. uint32_t soc_id;
  370. struct wlfw_fw_version_info fw_version_info;
  371. char fw_build_id[WLFW_MAX_BUILD_ID_LEN + 1];
  372. u32 pwr_pin_result;
  373. u32 phy_io_pin_result;
  374. u32 rf_pin_result;
  375. uint32_t nr_mem_region;
  376. struct icnss_mem_region_info
  377. mem_region[WLFW_MAX_NUM_MEMORY_REGIONS];
  378. struct dentry *root_dentry;
  379. spinlock_t on_off_lock;
  380. struct icnss_stats stats;
  381. void *modem_notify_handler;
  382. void *wpss_notify_handler;
  383. void *wpss_early_notify_handler;
  384. struct notifier_block modem_ssr_nb;
  385. struct notifier_block wpss_ssr_nb;
  386. struct notifier_block wpss_early_ssr_nb;
  387. uint32_t diag_reg_read_addr;
  388. uint32_t diag_reg_read_mem_type;
  389. uint32_t diag_reg_read_len;
  390. uint8_t *diag_reg_read_buf;
  391. atomic_t pm_count;
  392. struct icnss_ramdump_info *msa0_dump_dev;
  393. struct icnss_ramdump_info *m3_dump_phyareg;
  394. struct icnss_ramdump_info *m3_dump_phydbg;
  395. struct icnss_ramdump_info *m3_dump_wmac0reg;
  396. struct icnss_ramdump_info *m3_dump_wcssdbg;
  397. struct icnss_ramdump_info *m3_dump_phyapdmem;
  398. bool force_err_fatal;
  399. bool allow_recursive_recovery;
  400. bool early_crash_ind;
  401. u8 cause_for_rejuvenation;
  402. u8 requesting_sub_system;
  403. u16 line_number;
  404. struct mutex dev_lock;
  405. uint32_t fw_error_fatal_irq;
  406. uint32_t fw_early_crash_irq;
  407. struct smp2p_out_info smp2p_info[ICNSS_SMP2P_OUT_MAX];
  408. struct completion unblock_shutdown;
  409. char function_name[WLFW_FUNCTION_NAME_LEN + 1];
  410. bool is_ssr;
  411. bool smmu_s1_enable;
  412. struct kobject *icnss_kobject;
  413. struct rproc *rproc;
  414. atomic_t is_shutdown;
  415. u32 qdss_mem_seg_len;
  416. struct icnss_fw_mem qdss_mem[QMI_WLFW_MAX_NUM_MEM_SEG_V01];
  417. void *get_info_cb_ctx;
  418. int (*get_info_cb)(void *ctx, void *event, int event_len);
  419. atomic_t soc_wake_ref_count;
  420. phys_addr_t hang_event_data_pa;
  421. void __iomem *hang_event_data_va;
  422. uint16_t hang_event_data_len;
  423. void *hang_event_data;
  424. struct list_head icnss_tcdev_list;
  425. struct mutex tcdev_lock;
  426. bool is_chain1_supported;
  427. bool chain_reg_info_updated;
  428. u32 hw_trc_override;
  429. struct icnss_dms_data dms;
  430. u8 use_nv_mac;
  431. struct pdr_handle *pdr_handle;
  432. struct pdr_service *pdr_service;
  433. bool root_pd_shutdown;
  434. struct mbox_client mbox_client_data;
  435. struct mbox_chan *mbox_chan;
  436. u32 wlan_en_delay_ms;
  437. u32 wlan_en_delay_ms_user;
  438. struct class *icnss_ramdump_class;
  439. dev_t icnss_ramdump_dev;
  440. struct completion smp2p_soc_wake_wait;
  441. uint32_t fw_soc_wake_ack_irq;
  442. char foundry_name;
  443. bool bdf_download_support;
  444. bool psf_supported;
  445. struct notifier_block psf_nb;
  446. struct power_supply *batt_psy;
  447. int last_updated_voltage;
  448. struct work_struct soc_update_work;
  449. struct workqueue_struct *soc_update_wq;
  450. unsigned long device_config;
  451. bool wpss_supported;
  452. bool is_rf_subtype_valid;
  453. u32 rf_subtype;
  454. };
  455. struct icnss_reg_info {
  456. uint32_t mem_type;
  457. uint32_t reg_offset;
  458. uint32_t data_len;
  459. };
  460. void icnss_free_qdss_mem(struct icnss_priv *priv);
  461. char *icnss_driver_event_to_str(enum icnss_driver_event_type type);
  462. int icnss_call_driver_uevent(struct icnss_priv *priv,
  463. enum icnss_uevent uevent, void *data);
  464. int icnss_driver_event_post(struct icnss_priv *priv,
  465. enum icnss_driver_event_type type,
  466. u32 flags, void *data);
  467. void icnss_allow_recursive_recovery(struct device *dev);
  468. void icnss_disallow_recursive_recovery(struct device *dev);
  469. char *icnss_soc_wake_event_to_str(enum icnss_soc_wake_event_type type);
  470. int icnss_soc_wake_event_post(struct icnss_priv *priv,
  471. enum icnss_soc_wake_event_type type,
  472. u32 flags, void *data);
  473. int icnss_get_iova(struct icnss_priv *priv, u64 *addr, u64 *size);
  474. int icnss_get_iova_ipa(struct icnss_priv *priv, u64 *addr, u64 *size);
  475. int icnss_update_cpr_info(struct icnss_priv *priv);
  476. void icnss_add_fw_prefix_name(struct icnss_priv *priv, char *prefix_name,
  477. char *name);
  478. int icnss_aop_mbox_init(struct icnss_priv *priv);
  479. #endif