dp_tx.c 173 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef WLAN_PEER_JITTER
  66. #define DP_AVG_JITTER_WEIGHT_DENOM 4
  67. #define DP_AVG_DELAY_WEIGHT_DENOM 3
  68. #endif
  69. #ifdef QCA_DP_TX_FW_METADATA_V2
  70. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  71. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  78. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  79. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  80. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  81. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  82. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  83. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  84. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  85. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  86. #else
  87. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  88. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  95. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  96. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  97. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  98. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  99. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  100. HTT_TCL_METADATA_TYPE_PEER_BASED
  101. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  102. HTT_TCL_METADATA_TYPE_VDEV_BASED
  103. #endif
  104. /*mapping between hal encrypt type and cdp_sec_type*/
  105. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  106. HAL_TX_ENCRYPT_TYPE_WEP_128,
  107. HAL_TX_ENCRYPT_TYPE_WEP_104,
  108. HAL_TX_ENCRYPT_TYPE_WEP_40,
  109. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  110. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  111. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  112. HAL_TX_ENCRYPT_TYPE_WAPI,
  113. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  114. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  115. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  116. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  117. qdf_export_symbol(sec_type_map);
  118. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  119. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  120. {
  121. enum dp_tx_event_type type;
  122. if (flags & DP_TX_DESC_FLAG_FLUSH)
  123. type = DP_TX_DESC_FLUSH;
  124. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  125. type = DP_TX_COMP_UNMAP_ERR;
  126. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  127. type = DP_TX_COMP_UNMAP;
  128. else
  129. type = DP_TX_DESC_UNMAP;
  130. return type;
  131. }
  132. static inline void
  133. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  134. qdf_nbuf_t skb, uint32_t sw_cookie,
  135. enum dp_tx_event_type type)
  136. {
  137. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  138. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  139. struct dp_tx_desc_event *entry;
  140. uint32_t idx;
  141. uint16_t slot;
  142. switch (type) {
  143. case DP_TX_COMP_UNMAP:
  144. case DP_TX_COMP_UNMAP_ERR:
  145. case DP_TX_COMP_MSDU_EXT:
  146. if (qdf_unlikely(!tx_comp_history->allocated))
  147. return;
  148. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  149. &slot,
  150. DP_TX_COMP_HIST_SLOT_SHIFT,
  151. DP_TX_COMP_HIST_PER_SLOT_MAX,
  152. DP_TX_COMP_HISTORY_SIZE);
  153. entry = &tx_comp_history->entry[slot][idx];
  154. break;
  155. case DP_TX_DESC_MAP:
  156. case DP_TX_DESC_UNMAP:
  157. case DP_TX_DESC_COOKIE:
  158. case DP_TX_DESC_FLUSH:
  159. if (qdf_unlikely(!tx_tcl_history->allocated))
  160. return;
  161. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  162. &slot,
  163. DP_TX_TCL_HIST_SLOT_SHIFT,
  164. DP_TX_TCL_HIST_PER_SLOT_MAX,
  165. DP_TX_TCL_HISTORY_SIZE);
  166. entry = &tx_tcl_history->entry[slot][idx];
  167. break;
  168. default:
  169. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  170. return;
  171. }
  172. entry->skb = skb;
  173. entry->paddr = paddr;
  174. entry->sw_cookie = sw_cookie;
  175. entry->type = type;
  176. entry->ts = qdf_get_log_timestamp();
  177. }
  178. static inline void
  179. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  180. struct qdf_tso_seg_elem_t *tso_seg,
  181. qdf_nbuf_t skb, uint32_t sw_cookie,
  182. enum dp_tx_event_type type)
  183. {
  184. int i;
  185. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  186. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  187. skb, sw_cookie, type);
  188. }
  189. if (!tso_seg->next)
  190. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  191. skb, 0xFFFFFFFF, type);
  192. }
  193. static inline void
  194. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  195. qdf_nbuf_t skb, uint32_t sw_cookie,
  196. enum dp_tx_event_type type)
  197. {
  198. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  199. uint32_t num_segs = tso_info.num_segs;
  200. while (num_segs) {
  201. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  202. curr_seg = curr_seg->next;
  203. num_segs--;
  204. }
  205. }
  206. #else
  207. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  208. {
  209. return DP_TX_DESC_INVAL_EVT;
  210. }
  211. static inline void
  212. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  213. qdf_nbuf_t skb, uint32_t sw_cookie,
  214. enum dp_tx_event_type type)
  215. {
  216. }
  217. static inline void
  218. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  219. struct qdf_tso_seg_elem_t *tso_seg,
  220. qdf_nbuf_t skb, uint32_t sw_cookie,
  221. enum dp_tx_event_type type)
  222. {
  223. }
  224. static inline void
  225. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  226. qdf_nbuf_t skb, uint32_t sw_cookie,
  227. enum dp_tx_event_type type)
  228. {
  229. }
  230. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  231. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  232. /**
  233. * dp_is_tput_high() - Check if throughput is high
  234. *
  235. * @soc - core txrx main context
  236. *
  237. * The current function is based of the RTPM tput policy variable where RTPM is
  238. * avoided based on throughput.
  239. */
  240. static inline int dp_is_tput_high(struct dp_soc *soc)
  241. {
  242. return dp_get_rtpm_tput_policy_requirement(soc);
  243. }
  244. #if defined(FEATURE_TSO)
  245. /**
  246. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  247. *
  248. * @soc - core txrx main context
  249. * @seg_desc - tso segment descriptor
  250. * @num_seg_desc - tso number segment descriptor
  251. */
  252. static void dp_tx_tso_unmap_segment(
  253. struct dp_soc *soc,
  254. struct qdf_tso_seg_elem_t *seg_desc,
  255. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  256. {
  257. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  258. if (qdf_unlikely(!seg_desc)) {
  259. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  260. __func__, __LINE__);
  261. qdf_assert(0);
  262. } else if (qdf_unlikely(!num_seg_desc)) {
  263. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  264. __func__, __LINE__);
  265. qdf_assert(0);
  266. } else {
  267. bool is_last_seg;
  268. /* no tso segment left to do dma unmap */
  269. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  270. return;
  271. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  272. true : false;
  273. qdf_nbuf_unmap_tso_segment(soc->osdev,
  274. seg_desc, is_last_seg);
  275. num_seg_desc->num_seg.tso_cmn_num_seg--;
  276. }
  277. }
  278. /**
  279. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  280. * back to the freelist
  281. *
  282. * @soc - soc device handle
  283. * @tx_desc - Tx software descriptor
  284. */
  285. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  286. struct dp_tx_desc_s *tx_desc)
  287. {
  288. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  289. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  290. dp_tx_err("SO desc is NULL!");
  291. qdf_assert(0);
  292. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  293. dp_tx_err("TSO num desc is NULL!");
  294. qdf_assert(0);
  295. } else {
  296. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  297. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  298. msdu_ext_desc->tso_num_desc;
  299. /* Add the tso num segment into the free list */
  300. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  301. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  302. tx_desc->msdu_ext_desc->
  303. tso_num_desc);
  304. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  305. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  306. }
  307. /* Add the tso segment into the free list*/
  308. dp_tx_tso_desc_free(soc,
  309. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  310. tso_desc);
  311. tx_desc->msdu_ext_desc->tso_desc = NULL;
  312. }
  313. }
  314. #else
  315. static void dp_tx_tso_unmap_segment(
  316. struct dp_soc *soc,
  317. struct qdf_tso_seg_elem_t *seg_desc,
  318. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  319. {
  320. }
  321. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  322. struct dp_tx_desc_s *tx_desc)
  323. {
  324. }
  325. #endif
  326. /**
  327. * dp_tx_desc_release() - Release Tx Descriptor
  328. * @tx_desc : Tx Descriptor
  329. * @desc_pool_id: Descriptor Pool ID
  330. *
  331. * Deallocate all resources attached to Tx descriptor and free the Tx
  332. * descriptor.
  333. *
  334. * Return:
  335. */
  336. void
  337. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  338. {
  339. struct dp_pdev *pdev = tx_desc->pdev;
  340. struct dp_soc *soc;
  341. uint8_t comp_status = 0;
  342. qdf_assert(pdev);
  343. soc = pdev->soc;
  344. dp_tx_outstanding_dec(pdev);
  345. if (tx_desc->msdu_ext_desc) {
  346. if (tx_desc->frm_type == dp_tx_frm_tso)
  347. dp_tx_tso_desc_release(soc, tx_desc);
  348. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  349. dp_tx_me_free_buf(tx_desc->pdev,
  350. tx_desc->msdu_ext_desc->me_buffer);
  351. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  352. }
  353. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  354. qdf_atomic_dec(&soc->num_tx_exception);
  355. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  356. tx_desc->buffer_src)
  357. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  358. soc->hal_soc);
  359. else
  360. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  361. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  362. tx_desc->id, comp_status,
  363. qdf_atomic_read(&pdev->num_tx_outstanding));
  364. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  365. return;
  366. }
  367. /**
  368. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  369. * @vdev: DP vdev Handle
  370. * @nbuf: skb
  371. * @msdu_info: msdu_info required to create HTT metadata
  372. *
  373. * Prepares and fills HTT metadata in the frame pre-header for special frames
  374. * that should be transmitted using varying transmit parameters.
  375. * There are 2 VDEV modes that currently needs this special metadata -
  376. * 1) Mesh Mode
  377. * 2) DSRC Mode
  378. *
  379. * Return: HTT metadata size
  380. *
  381. */
  382. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  383. struct dp_tx_msdu_info_s *msdu_info)
  384. {
  385. uint32_t *meta_data = msdu_info->meta_data;
  386. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  387. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  388. uint8_t htt_desc_size;
  389. /* Size rounded of multiple of 8 bytes */
  390. uint8_t htt_desc_size_aligned;
  391. uint8_t *hdr = NULL;
  392. /*
  393. * Metadata - HTT MSDU Extension header
  394. */
  395. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  396. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  397. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  398. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  399. meta_data[0]) ||
  400. msdu_info->exception_fw) {
  401. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  402. htt_desc_size_aligned)) {
  403. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  404. htt_desc_size_aligned);
  405. if (!nbuf) {
  406. /*
  407. * qdf_nbuf_realloc_headroom won't do skb_clone
  408. * as skb_realloc_headroom does. so, no free is
  409. * needed here.
  410. */
  411. DP_STATS_INC(vdev,
  412. tx_i.dropped.headroom_insufficient,
  413. 1);
  414. qdf_print(" %s[%d] skb_realloc_headroom failed",
  415. __func__, __LINE__);
  416. return 0;
  417. }
  418. }
  419. /* Fill and add HTT metaheader */
  420. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  421. if (!hdr) {
  422. dp_tx_err("Error in filling HTT metadata");
  423. return 0;
  424. }
  425. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  426. } else if (vdev->opmode == wlan_op_mode_ocb) {
  427. /* Todo - Add support for DSRC */
  428. }
  429. return htt_desc_size_aligned;
  430. }
  431. /**
  432. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  433. * @tso_seg: TSO segment to process
  434. * @ext_desc: Pointer to MSDU extension descriptor
  435. *
  436. * Return: void
  437. */
  438. #if defined(FEATURE_TSO)
  439. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  440. void *ext_desc)
  441. {
  442. uint8_t num_frag;
  443. uint32_t tso_flags;
  444. /*
  445. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  446. * tcp_flag_mask
  447. *
  448. * Checksum enable flags are set in TCL descriptor and not in Extension
  449. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  450. */
  451. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  452. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  453. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  454. tso_seg->tso_flags.ip_len);
  455. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  456. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  457. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  458. uint32_t lo = 0;
  459. uint32_t hi = 0;
  460. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  461. (tso_seg->tso_frags[num_frag].length));
  462. qdf_dmaaddr_to_32s(
  463. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  464. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  465. tso_seg->tso_frags[num_frag].length);
  466. }
  467. return;
  468. }
  469. #else
  470. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  471. void *ext_desc)
  472. {
  473. return;
  474. }
  475. #endif
  476. #if defined(FEATURE_TSO)
  477. /**
  478. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  479. * allocated and free them
  480. *
  481. * @soc: soc handle
  482. * @free_seg: list of tso segments
  483. * @msdu_info: msdu descriptor
  484. *
  485. * Return - void
  486. */
  487. static void dp_tx_free_tso_seg_list(
  488. struct dp_soc *soc,
  489. struct qdf_tso_seg_elem_t *free_seg,
  490. struct dp_tx_msdu_info_s *msdu_info)
  491. {
  492. struct qdf_tso_seg_elem_t *next_seg;
  493. while (free_seg) {
  494. next_seg = free_seg->next;
  495. dp_tx_tso_desc_free(soc,
  496. msdu_info->tx_queue.desc_pool_id,
  497. free_seg);
  498. free_seg = next_seg;
  499. }
  500. }
  501. /**
  502. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  503. * allocated and free them
  504. *
  505. * @soc: soc handle
  506. * @free_num_seg: list of tso number segments
  507. * @msdu_info: msdu descriptor
  508. * Return - void
  509. */
  510. static void dp_tx_free_tso_num_seg_list(
  511. struct dp_soc *soc,
  512. struct qdf_tso_num_seg_elem_t *free_num_seg,
  513. struct dp_tx_msdu_info_s *msdu_info)
  514. {
  515. struct qdf_tso_num_seg_elem_t *next_num_seg;
  516. while (free_num_seg) {
  517. next_num_seg = free_num_seg->next;
  518. dp_tso_num_seg_free(soc,
  519. msdu_info->tx_queue.desc_pool_id,
  520. free_num_seg);
  521. free_num_seg = next_num_seg;
  522. }
  523. }
  524. /**
  525. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  526. * do dma unmap for each segment
  527. *
  528. * @soc: soc handle
  529. * @free_seg: list of tso segments
  530. * @num_seg_desc: tso number segment descriptor
  531. *
  532. * Return - void
  533. */
  534. static void dp_tx_unmap_tso_seg_list(
  535. struct dp_soc *soc,
  536. struct qdf_tso_seg_elem_t *free_seg,
  537. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  538. {
  539. struct qdf_tso_seg_elem_t *next_seg;
  540. if (qdf_unlikely(!num_seg_desc)) {
  541. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  542. return;
  543. }
  544. while (free_seg) {
  545. next_seg = free_seg->next;
  546. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  547. free_seg = next_seg;
  548. }
  549. }
  550. #ifdef FEATURE_TSO_STATS
  551. /**
  552. * dp_tso_get_stats_idx: Retrieve the tso packet id
  553. * @pdev - pdev handle
  554. *
  555. * Return: id
  556. */
  557. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  558. {
  559. uint32_t stats_idx;
  560. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  561. % CDP_MAX_TSO_PACKETS);
  562. return stats_idx;
  563. }
  564. #else
  565. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  566. {
  567. return 0;
  568. }
  569. #endif /* FEATURE_TSO_STATS */
  570. /**
  571. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  572. * free the tso segments descriptor and
  573. * tso num segments descriptor
  574. *
  575. * @soc: soc handle
  576. * @msdu_info: msdu descriptor
  577. * @tso_seg_unmap: flag to show if dma unmap is necessary
  578. *
  579. * Return - void
  580. */
  581. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  582. struct dp_tx_msdu_info_s *msdu_info,
  583. bool tso_seg_unmap)
  584. {
  585. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  586. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  587. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  588. tso_info->tso_num_seg_list;
  589. /* do dma unmap for each segment */
  590. if (tso_seg_unmap)
  591. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  592. /* free all tso number segment descriptor though looks only have 1 */
  593. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  594. /* free all tso segment descriptor */
  595. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  596. }
  597. /**
  598. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  599. * @vdev: virtual device handle
  600. * @msdu: network buffer
  601. * @msdu_info: meta data associated with the msdu
  602. *
  603. * Return: QDF_STATUS_SUCCESS success
  604. */
  605. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  606. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  607. {
  608. struct qdf_tso_seg_elem_t *tso_seg;
  609. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  610. struct dp_soc *soc = vdev->pdev->soc;
  611. struct dp_pdev *pdev = vdev->pdev;
  612. struct qdf_tso_info_t *tso_info;
  613. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  614. tso_info = &msdu_info->u.tso_info;
  615. tso_info->curr_seg = NULL;
  616. tso_info->tso_seg_list = NULL;
  617. tso_info->num_segs = num_seg;
  618. msdu_info->frm_type = dp_tx_frm_tso;
  619. tso_info->tso_num_seg_list = NULL;
  620. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  621. while (num_seg) {
  622. tso_seg = dp_tx_tso_desc_alloc(
  623. soc, msdu_info->tx_queue.desc_pool_id);
  624. if (tso_seg) {
  625. tso_seg->next = tso_info->tso_seg_list;
  626. tso_info->tso_seg_list = tso_seg;
  627. num_seg--;
  628. } else {
  629. dp_err_rl("Failed to alloc tso seg desc");
  630. DP_STATS_INC_PKT(vdev->pdev,
  631. tso_stats.tso_no_mem_dropped, 1,
  632. qdf_nbuf_len(msdu));
  633. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  634. return QDF_STATUS_E_NOMEM;
  635. }
  636. }
  637. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  638. tso_num_seg = dp_tso_num_seg_alloc(soc,
  639. msdu_info->tx_queue.desc_pool_id);
  640. if (tso_num_seg) {
  641. tso_num_seg->next = tso_info->tso_num_seg_list;
  642. tso_info->tso_num_seg_list = tso_num_seg;
  643. } else {
  644. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  645. __func__);
  646. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  647. return QDF_STATUS_E_NOMEM;
  648. }
  649. msdu_info->num_seg =
  650. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  651. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  652. msdu_info->num_seg);
  653. if (!(msdu_info->num_seg)) {
  654. /*
  655. * Free allocated TSO seg desc and number seg desc,
  656. * do unmap for segments if dma map has done.
  657. */
  658. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  659. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  660. return QDF_STATUS_E_INVAL;
  661. }
  662. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  663. msdu, 0, DP_TX_DESC_MAP);
  664. tso_info->curr_seg = tso_info->tso_seg_list;
  665. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  666. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  667. msdu, msdu_info->num_seg);
  668. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  669. tso_info->msdu_stats_idx);
  670. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  671. return QDF_STATUS_SUCCESS;
  672. }
  673. #else
  674. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  675. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  676. {
  677. return QDF_STATUS_E_NOMEM;
  678. }
  679. #endif
  680. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  681. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  682. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  683. /**
  684. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  685. * @vdev: DP Vdev handle
  686. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  687. * @desc_pool_id: Descriptor Pool ID
  688. *
  689. * Return:
  690. */
  691. static
  692. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  693. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  694. {
  695. uint8_t i;
  696. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  697. struct dp_tx_seg_info_s *seg_info;
  698. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  699. struct dp_soc *soc = vdev->pdev->soc;
  700. /* Allocate an extension descriptor */
  701. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  702. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  703. if (!msdu_ext_desc) {
  704. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  705. return NULL;
  706. }
  707. if (msdu_info->exception_fw &&
  708. qdf_unlikely(vdev->mesh_vdev)) {
  709. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  710. &msdu_info->meta_data[0],
  711. sizeof(struct htt_tx_msdu_desc_ext2_t));
  712. qdf_atomic_inc(&soc->num_tx_exception);
  713. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  714. }
  715. switch (msdu_info->frm_type) {
  716. case dp_tx_frm_sg:
  717. case dp_tx_frm_me:
  718. case dp_tx_frm_raw:
  719. seg_info = msdu_info->u.sg_info.curr_seg;
  720. /* Update the buffer pointers in MSDU Extension Descriptor */
  721. for (i = 0; i < seg_info->frag_cnt; i++) {
  722. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  723. seg_info->frags[i].paddr_lo,
  724. seg_info->frags[i].paddr_hi,
  725. seg_info->frags[i].len);
  726. }
  727. break;
  728. case dp_tx_frm_tso:
  729. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  730. &cached_ext_desc[0]);
  731. break;
  732. default:
  733. break;
  734. }
  735. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  736. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  737. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  738. msdu_ext_desc->vaddr);
  739. return msdu_ext_desc;
  740. }
  741. /**
  742. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  743. *
  744. * @skb: skb to be traced
  745. * @msdu_id: msdu_id of the packet
  746. * @vdev_id: vdev_id of the packet
  747. *
  748. * Return: None
  749. */
  750. #ifdef DP_DISABLE_TX_PKT_TRACE
  751. static void dp_tx_trace_pkt(struct dp_soc *soc,
  752. qdf_nbuf_t skb, uint16_t msdu_id,
  753. uint8_t vdev_id)
  754. {
  755. }
  756. #else
  757. static void dp_tx_trace_pkt(struct dp_soc *soc,
  758. qdf_nbuf_t skb, uint16_t msdu_id,
  759. uint8_t vdev_id)
  760. {
  761. if (dp_is_tput_high(soc))
  762. return;
  763. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  764. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  765. DPTRACE(qdf_dp_trace_ptr(skb,
  766. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  767. QDF_TRACE_DEFAULT_PDEV_ID,
  768. qdf_nbuf_data_addr(skb),
  769. sizeof(qdf_nbuf_data(skb)),
  770. msdu_id, vdev_id, 0));
  771. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  772. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  773. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  774. msdu_id, QDF_TX));
  775. }
  776. #endif
  777. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  778. /**
  779. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  780. * exception by the upper layer (OS_IF)
  781. * @soc: DP soc handle
  782. * @nbuf: packet to be transmitted
  783. *
  784. * Returns: 1 if the packet is marked as exception,
  785. * 0, if the packet is not marked as exception.
  786. */
  787. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  788. qdf_nbuf_t nbuf)
  789. {
  790. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  791. }
  792. #else
  793. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  794. qdf_nbuf_t nbuf)
  795. {
  796. return 0;
  797. }
  798. #endif
  799. #ifdef DP_TRAFFIC_END_INDICATION
  800. /**
  801. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  802. * as indication to fw to inform that
  803. * data stream has ended
  804. * @vdev: DP vdev handle
  805. * @nbuf: original buffer from network stack
  806. *
  807. * Return: NULL on failure,
  808. * nbuf on success
  809. */
  810. static inline qdf_nbuf_t
  811. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  812. qdf_nbuf_t nbuf)
  813. {
  814. /* Packet length should be enough to copy upto L3 header */
  815. uint8_t end_nbuf_len = 64;
  816. uint8_t htt_desc_size_aligned;
  817. uint8_t htt_desc_size;
  818. qdf_nbuf_t end_nbuf;
  819. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  820. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  821. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  822. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  823. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  824. if (!end_nbuf) {
  825. end_nbuf = qdf_nbuf_alloc(NULL,
  826. (htt_desc_size_aligned +
  827. end_nbuf_len),
  828. htt_desc_size_aligned,
  829. 8, false);
  830. if (!end_nbuf) {
  831. dp_err("Packet allocation failed");
  832. goto out;
  833. }
  834. } else {
  835. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  836. }
  837. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  838. end_nbuf_len);
  839. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  840. return end_nbuf;
  841. }
  842. out:
  843. return NULL;
  844. }
  845. /**
  846. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  847. * via exception path.
  848. * @vdev: DP vdev handle
  849. * @end_nbuf: skb to send as indication
  850. * @msdu_info: msdu_info of original nbuf
  851. * @peer_id: peer id
  852. *
  853. * Return: None
  854. */
  855. static inline void
  856. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  857. qdf_nbuf_t end_nbuf,
  858. struct dp_tx_msdu_info_s *msdu_info,
  859. uint16_t peer_id)
  860. {
  861. struct dp_tx_msdu_info_s e_msdu_info = {0};
  862. qdf_nbuf_t nbuf;
  863. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  864. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  865. e_msdu_info.tx_queue = msdu_info->tx_queue;
  866. e_msdu_info.tid = msdu_info->tid;
  867. e_msdu_info.exception_fw = 1;
  868. desc_ext->host_tx_desc_pool = 1;
  869. desc_ext->traffic_end_indication = 1;
  870. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  871. peer_id, NULL);
  872. if (nbuf) {
  873. dp_err("Traffic end indication packet tx failed");
  874. qdf_nbuf_free(nbuf);
  875. }
  876. }
  877. /**
  878. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  879. * mark it traffic end indication
  880. * packet.
  881. * @tx_desc: Tx descriptor pointer
  882. * @msdu_info: msdu_info structure pointer
  883. *
  884. * Return: None
  885. */
  886. static inline void
  887. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  888. struct dp_tx_msdu_info_s *msdu_info)
  889. {
  890. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  891. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  892. if (qdf_unlikely(desc_ext->traffic_end_indication))
  893. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  894. }
  895. /**
  896. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  897. * freeing which are associated
  898. * with traffic end indication
  899. * flagged descriptor.
  900. * @soc: dp soc handle
  901. * @desc: Tx descriptor pointer
  902. * @nbuf: buffer pointer
  903. *
  904. * Return: True if packet gets enqueued else false
  905. */
  906. static bool
  907. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  908. struct dp_tx_desc_s *desc,
  909. qdf_nbuf_t nbuf)
  910. {
  911. struct dp_vdev *vdev = NULL;
  912. if (qdf_unlikely((desc->flags &
  913. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  914. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  915. DP_MOD_ID_TX_COMP);
  916. if (vdev) {
  917. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  918. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  919. return true;
  920. }
  921. }
  922. return false;
  923. }
  924. /**
  925. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  926. * enable/disable status
  927. * @vdev: dp vdev handle
  928. *
  929. * Return: True if feature is enable else false
  930. */
  931. static inline bool
  932. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  933. {
  934. return qdf_unlikely(vdev->traffic_end_ind_en);
  935. }
  936. static inline qdf_nbuf_t
  937. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  938. struct dp_tx_msdu_info_s *msdu_info,
  939. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  940. {
  941. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  942. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  943. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  944. if (qdf_unlikely(end_nbuf))
  945. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  946. msdu_info, peer_id);
  947. return nbuf;
  948. }
  949. #else
  950. static inline qdf_nbuf_t
  951. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  952. qdf_nbuf_t nbuf)
  953. {
  954. return NULL;
  955. }
  956. static inline void
  957. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  958. qdf_nbuf_t end_nbuf,
  959. struct dp_tx_msdu_info_s *msdu_info,
  960. uint16_t peer_id)
  961. {}
  962. static inline void
  963. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  964. struct dp_tx_msdu_info_s *msdu_info)
  965. {}
  966. static inline bool
  967. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  968. struct dp_tx_desc_s *desc,
  969. qdf_nbuf_t nbuf)
  970. {
  971. return false;
  972. }
  973. static inline bool
  974. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  975. {
  976. return false;
  977. }
  978. static inline qdf_nbuf_t
  979. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  980. struct dp_tx_msdu_info_s *msdu_info,
  981. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  982. {
  983. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  984. }
  985. #endif
  986. /**
  987. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  988. * @vdev: DP vdev handle
  989. * @nbuf: skb
  990. * @desc_pool_id: Descriptor pool ID
  991. * @meta_data: Metadata to the fw
  992. * @tx_exc_metadata: Handle that holds exception path metadata
  993. * Allocate and prepare Tx descriptor with msdu information.
  994. *
  995. * Return: Pointer to Tx Descriptor on success,
  996. * NULL on failure
  997. */
  998. static
  999. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1000. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1001. struct dp_tx_msdu_info_s *msdu_info,
  1002. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1003. {
  1004. uint8_t align_pad;
  1005. uint8_t is_exception = 0;
  1006. uint8_t htt_hdr_size;
  1007. struct dp_tx_desc_s *tx_desc;
  1008. struct dp_pdev *pdev = vdev->pdev;
  1009. struct dp_soc *soc = pdev->soc;
  1010. if (dp_tx_limit_check(vdev))
  1011. return NULL;
  1012. /* Allocate software Tx descriptor */
  1013. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1014. if (qdf_unlikely(!tx_desc)) {
  1015. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1016. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1017. return NULL;
  1018. }
  1019. dp_tx_outstanding_inc(pdev);
  1020. /* Initialize the SW tx descriptor */
  1021. tx_desc->nbuf = nbuf;
  1022. tx_desc->frm_type = dp_tx_frm_std;
  1023. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1024. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1025. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1026. tx_desc->vdev_id = vdev->vdev_id;
  1027. tx_desc->pdev = pdev;
  1028. tx_desc->msdu_ext_desc = NULL;
  1029. tx_desc->pkt_offset = 0;
  1030. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1031. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1032. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1033. if (qdf_unlikely(vdev->multipass_en)) {
  1034. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1035. goto failure;
  1036. }
  1037. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1038. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1039. is_exception = 1;
  1040. /*
  1041. * For special modes (vdev_type == ocb or mesh), data frames should be
  1042. * transmitted using varying transmit parameters (tx spec) which include
  1043. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1044. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1045. * These frames are sent as exception packets to firmware.
  1046. *
  1047. * HW requirement is that metadata should always point to a
  1048. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1049. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1050. * to get 8-byte aligned start address along with align_pad added
  1051. *
  1052. * |-----------------------------|
  1053. * | |
  1054. * |-----------------------------| <-----Buffer Pointer Address given
  1055. * | | ^ in HW descriptor (aligned)
  1056. * | HTT Metadata | |
  1057. * | | |
  1058. * | | | Packet Offset given in descriptor
  1059. * | | |
  1060. * |-----------------------------| |
  1061. * | Alignment Pad | v
  1062. * |-----------------------------| <----- Actual buffer start address
  1063. * | SKB Data | (Unaligned)
  1064. * | |
  1065. * | |
  1066. * | |
  1067. * | |
  1068. * | |
  1069. * |-----------------------------|
  1070. */
  1071. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1072. (vdev->opmode == wlan_op_mode_ocb) ||
  1073. (tx_exc_metadata &&
  1074. tx_exc_metadata->is_tx_sniffer)) {
  1075. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1076. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1077. DP_STATS_INC(vdev,
  1078. tx_i.dropped.headroom_insufficient, 1);
  1079. goto failure;
  1080. }
  1081. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1082. dp_tx_err("qdf_nbuf_push_head failed");
  1083. goto failure;
  1084. }
  1085. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1086. msdu_info);
  1087. if (htt_hdr_size == 0)
  1088. goto failure;
  1089. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1090. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1091. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1092. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1093. msdu_info);
  1094. is_exception = 1;
  1095. tx_desc->length -= tx_desc->pkt_offset;
  1096. }
  1097. #if !TQM_BYPASS_WAR
  1098. if (is_exception || tx_exc_metadata)
  1099. #endif
  1100. {
  1101. /* Temporary WAR due to TQM VP issues */
  1102. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1103. qdf_atomic_inc(&soc->num_tx_exception);
  1104. }
  1105. return tx_desc;
  1106. failure:
  1107. dp_tx_desc_release(tx_desc, desc_pool_id);
  1108. return NULL;
  1109. }
  1110. /**
  1111. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1112. * @vdev: DP vdev handle
  1113. * @nbuf: skb
  1114. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1115. * @desc_pool_id : Descriptor Pool ID
  1116. *
  1117. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1118. * information. For frames with fragments, allocate and prepare
  1119. * an MSDU extension descriptor
  1120. *
  1121. * Return: Pointer to Tx Descriptor on success,
  1122. * NULL on failure
  1123. */
  1124. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1125. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1126. uint8_t desc_pool_id)
  1127. {
  1128. struct dp_tx_desc_s *tx_desc;
  1129. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1130. struct dp_pdev *pdev = vdev->pdev;
  1131. struct dp_soc *soc = pdev->soc;
  1132. if (dp_tx_limit_check(vdev))
  1133. return NULL;
  1134. /* Allocate software Tx descriptor */
  1135. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1136. if (!tx_desc) {
  1137. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1138. return NULL;
  1139. }
  1140. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1141. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1142. dp_tx_outstanding_inc(pdev);
  1143. /* Initialize the SW tx descriptor */
  1144. tx_desc->nbuf = nbuf;
  1145. tx_desc->frm_type = msdu_info->frm_type;
  1146. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1147. tx_desc->vdev_id = vdev->vdev_id;
  1148. tx_desc->pdev = pdev;
  1149. tx_desc->pkt_offset = 0;
  1150. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1151. /* Handle scattered frames - TSO/SG/ME */
  1152. /* Allocate and prepare an extension descriptor for scattered frames */
  1153. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1154. if (!msdu_ext_desc) {
  1155. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1156. goto failure;
  1157. }
  1158. #if TQM_BYPASS_WAR
  1159. /* Temporary WAR due to TQM VP issues */
  1160. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1161. qdf_atomic_inc(&soc->num_tx_exception);
  1162. #endif
  1163. if (qdf_unlikely(msdu_info->exception_fw))
  1164. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1165. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1166. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1167. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1168. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1169. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1170. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1171. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1172. else
  1173. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1174. return tx_desc;
  1175. failure:
  1176. dp_tx_desc_release(tx_desc, desc_pool_id);
  1177. return NULL;
  1178. }
  1179. /**
  1180. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1181. * @vdev: DP vdev handle
  1182. * @nbuf: buffer pointer
  1183. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1184. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1185. * descriptor
  1186. *
  1187. * Return:
  1188. */
  1189. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1190. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1191. {
  1192. qdf_nbuf_t curr_nbuf = NULL;
  1193. uint16_t total_len = 0;
  1194. qdf_dma_addr_t paddr;
  1195. int32_t i;
  1196. int32_t mapped_buf_num = 0;
  1197. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1198. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1199. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1200. /* Continue only if frames are of DATA type */
  1201. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1202. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1203. dp_tx_debug("Pkt. recd is of not data type");
  1204. goto error;
  1205. }
  1206. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1207. if (vdev->raw_mode_war &&
  1208. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1209. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1210. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1211. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1212. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1213. /*
  1214. * Number of nbuf's must not exceed the size of the frags
  1215. * array in seg_info.
  1216. */
  1217. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1218. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1219. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1220. goto error;
  1221. }
  1222. if (QDF_STATUS_SUCCESS !=
  1223. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1224. curr_nbuf,
  1225. QDF_DMA_TO_DEVICE,
  1226. curr_nbuf->len)) {
  1227. dp_tx_err("%s dma map error ", __func__);
  1228. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1229. goto error;
  1230. }
  1231. /* Update the count of mapped nbuf's */
  1232. mapped_buf_num++;
  1233. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1234. seg_info->frags[i].paddr_lo = paddr;
  1235. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1236. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1237. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1238. total_len += qdf_nbuf_len(curr_nbuf);
  1239. }
  1240. seg_info->frag_cnt = i;
  1241. seg_info->total_len = total_len;
  1242. seg_info->next = NULL;
  1243. sg_info->curr_seg = seg_info;
  1244. msdu_info->frm_type = dp_tx_frm_raw;
  1245. msdu_info->num_seg = 1;
  1246. return nbuf;
  1247. error:
  1248. i = 0;
  1249. while (nbuf) {
  1250. curr_nbuf = nbuf;
  1251. if (i < mapped_buf_num) {
  1252. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1253. QDF_DMA_TO_DEVICE,
  1254. curr_nbuf->len);
  1255. i++;
  1256. }
  1257. nbuf = qdf_nbuf_next(nbuf);
  1258. qdf_nbuf_free(curr_nbuf);
  1259. }
  1260. return NULL;
  1261. }
  1262. /**
  1263. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1264. * @soc: DP soc handle
  1265. * @nbuf: Buffer pointer
  1266. *
  1267. * unmap the chain of nbufs that belong to this RAW frame.
  1268. *
  1269. * Return: None
  1270. */
  1271. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1272. qdf_nbuf_t nbuf)
  1273. {
  1274. qdf_nbuf_t cur_nbuf = nbuf;
  1275. do {
  1276. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1277. QDF_DMA_TO_DEVICE,
  1278. cur_nbuf->len);
  1279. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1280. } while (cur_nbuf);
  1281. }
  1282. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1283. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1284. qdf_nbuf_t nbuf)
  1285. {
  1286. qdf_nbuf_t nbuf_local;
  1287. struct dp_vdev *vdev_local = vdev_hdl;
  1288. do {
  1289. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1290. break;
  1291. nbuf_local = nbuf;
  1292. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1293. htt_cmn_pkt_type_raw))
  1294. break;
  1295. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1296. break;
  1297. else if (qdf_nbuf_is_tso((nbuf_local)))
  1298. break;
  1299. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1300. (nbuf_local),
  1301. NULL, 1, 0);
  1302. } while (0);
  1303. }
  1304. #endif
  1305. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1306. /**
  1307. * dp_tx_update_stats() - Update soc level tx stats
  1308. * @soc: DP soc handle
  1309. * @tx_desc: TX descriptor reference
  1310. * @ring_id: TCL ring id
  1311. *
  1312. * Returns: none
  1313. */
  1314. void dp_tx_update_stats(struct dp_soc *soc,
  1315. struct dp_tx_desc_s *tx_desc,
  1316. uint8_t ring_id)
  1317. {
  1318. uint32_t stats_len = 0;
  1319. if (tx_desc->frm_type == dp_tx_frm_tso)
  1320. stats_len = tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1321. else
  1322. stats_len = qdf_nbuf_len(tx_desc->nbuf);
  1323. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1324. }
  1325. int
  1326. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1327. struct dp_tx_desc_s *tx_desc,
  1328. uint8_t tid,
  1329. struct dp_tx_msdu_info_s *msdu_info,
  1330. uint8_t ring_id)
  1331. {
  1332. struct dp_swlm *swlm = &soc->swlm;
  1333. union swlm_data swlm_query_data;
  1334. struct dp_swlm_tcl_data tcl_data;
  1335. QDF_STATUS status;
  1336. int ret;
  1337. if (!swlm->is_enabled)
  1338. return msdu_info->skip_hp_update;
  1339. tcl_data.nbuf = tx_desc->nbuf;
  1340. tcl_data.tid = tid;
  1341. tcl_data.ring_id = ring_id;
  1342. if (tx_desc->frm_type == dp_tx_frm_tso) {
  1343. tcl_data.pkt_len =
  1344. tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1345. } else {
  1346. tcl_data.pkt_len = qdf_nbuf_len(tx_desc->nbuf);
  1347. }
  1348. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1349. swlm_query_data.tcl_data = &tcl_data;
  1350. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1351. if (QDF_IS_STATUS_ERROR(status)) {
  1352. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1353. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1354. return 0;
  1355. }
  1356. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1357. if (ret) {
  1358. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1359. } else {
  1360. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1361. }
  1362. return ret;
  1363. }
  1364. void
  1365. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1366. int coalesce)
  1367. {
  1368. if (coalesce)
  1369. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1370. else
  1371. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1372. }
  1373. static inline void
  1374. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1375. {
  1376. if (((i + 1) < msdu_info->num_seg))
  1377. msdu_info->skip_hp_update = 1;
  1378. else
  1379. msdu_info->skip_hp_update = 0;
  1380. }
  1381. static inline void
  1382. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1383. {
  1384. hal_ring_handle_t hal_ring_hdl =
  1385. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1386. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1387. dp_err("Fillmore: SRNG access start failed");
  1388. return;
  1389. }
  1390. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1391. }
  1392. static inline void
  1393. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1394. QDF_STATUS status,
  1395. struct dp_tx_msdu_info_s *msdu_info)
  1396. {
  1397. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1398. dp_flush_tcp_hp(soc,
  1399. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1400. }
  1401. }
  1402. #else
  1403. static inline void
  1404. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1405. {
  1406. }
  1407. static inline void
  1408. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1409. QDF_STATUS status,
  1410. struct dp_tx_msdu_info_s *msdu_info)
  1411. {
  1412. }
  1413. #endif
  1414. #ifdef FEATURE_RUNTIME_PM
  1415. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1416. {
  1417. int ret;
  1418. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1419. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1420. return ret;
  1421. }
  1422. /**
  1423. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1424. * @soc: Datapath soc handle
  1425. * @hal_ring_hdl: HAL ring handle
  1426. * @coalesce: Coalesce the current write or not
  1427. *
  1428. * Wrapper for HAL ring access end for data transmission for
  1429. * FEATURE_RUNTIME_PM
  1430. *
  1431. * Returns: none
  1432. */
  1433. void
  1434. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1435. hal_ring_handle_t hal_ring_hdl,
  1436. int coalesce)
  1437. {
  1438. int ret;
  1439. /*
  1440. * Avoid runtime get and put APIs under high throughput scenarios.
  1441. */
  1442. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1443. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1444. return;
  1445. }
  1446. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1447. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1448. if (hif_system_pm_state_check(soc->hif_handle) ||
  1449. qdf_unlikely(soc->is_tx_pause)) {
  1450. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1451. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1452. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1453. } else {
  1454. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1455. }
  1456. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1457. } else {
  1458. dp_runtime_get(soc);
  1459. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1460. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1461. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1462. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1463. dp_runtime_put(soc);
  1464. }
  1465. }
  1466. #else
  1467. #ifdef DP_POWER_SAVE
  1468. void
  1469. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1470. hal_ring_handle_t hal_ring_hdl,
  1471. int coalesce)
  1472. {
  1473. if (hif_system_pm_state_check(soc->hif_handle) ||
  1474. qdf_unlikely(soc->is_tx_pause)) {
  1475. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1476. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1477. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1478. } else {
  1479. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1480. }
  1481. }
  1482. #endif
  1483. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1484. {
  1485. return 0;
  1486. }
  1487. #endif
  1488. /**
  1489. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1490. * @vdev: DP vdev handle
  1491. * @nbuf: skb
  1492. *
  1493. * Extract the DSCP or PCP information from frame and map into TID value.
  1494. *
  1495. * Return: void
  1496. */
  1497. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1498. struct dp_tx_msdu_info_s *msdu_info)
  1499. {
  1500. uint8_t tos = 0, dscp_tid_override = 0;
  1501. uint8_t *hdr_ptr, *L3datap;
  1502. uint8_t is_mcast = 0;
  1503. qdf_ether_header_t *eh = NULL;
  1504. qdf_ethervlan_header_t *evh = NULL;
  1505. uint16_t ether_type;
  1506. qdf_llc_t *llcHdr;
  1507. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1508. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1509. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1510. eh = (qdf_ether_header_t *)nbuf->data;
  1511. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1512. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1513. } else {
  1514. qdf_dot3_qosframe_t *qos_wh =
  1515. (qdf_dot3_qosframe_t *) nbuf->data;
  1516. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1517. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1518. return;
  1519. }
  1520. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1521. ether_type = eh->ether_type;
  1522. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1523. /*
  1524. * Check if packet is dot3 or eth2 type.
  1525. */
  1526. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1527. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1528. sizeof(*llcHdr));
  1529. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1530. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1531. sizeof(*llcHdr);
  1532. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1533. + sizeof(*llcHdr) +
  1534. sizeof(qdf_net_vlanhdr_t));
  1535. } else {
  1536. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1537. sizeof(*llcHdr);
  1538. }
  1539. } else {
  1540. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1541. evh = (qdf_ethervlan_header_t *) eh;
  1542. ether_type = evh->ether_type;
  1543. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1544. }
  1545. }
  1546. /*
  1547. * Find priority from IP TOS DSCP field
  1548. */
  1549. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1550. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1551. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1552. /* Only for unicast frames */
  1553. if (!is_mcast) {
  1554. /* send it on VO queue */
  1555. msdu_info->tid = DP_VO_TID;
  1556. }
  1557. } else {
  1558. /*
  1559. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1560. * from TOS byte.
  1561. */
  1562. tos = ip->ip_tos;
  1563. dscp_tid_override = 1;
  1564. }
  1565. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1566. /* TODO
  1567. * use flowlabel
  1568. *igmpmld cases to be handled in phase 2
  1569. */
  1570. unsigned long ver_pri_flowlabel;
  1571. unsigned long pri;
  1572. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1573. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1574. DP_IPV6_PRIORITY_SHIFT;
  1575. tos = pri;
  1576. dscp_tid_override = 1;
  1577. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1578. msdu_info->tid = DP_VO_TID;
  1579. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1580. /* Only for unicast frames */
  1581. if (!is_mcast) {
  1582. /* send ucast arp on VO queue */
  1583. msdu_info->tid = DP_VO_TID;
  1584. }
  1585. }
  1586. /*
  1587. * Assign all MCAST packets to BE
  1588. */
  1589. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1590. if (is_mcast) {
  1591. tos = 0;
  1592. dscp_tid_override = 1;
  1593. }
  1594. }
  1595. if (dscp_tid_override == 1) {
  1596. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1597. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1598. }
  1599. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1600. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1601. return;
  1602. }
  1603. /**
  1604. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1605. * @vdev: DP vdev handle
  1606. * @nbuf: skb
  1607. *
  1608. * Software based TID classification is required when more than 2 DSCP-TID
  1609. * mapping tables are needed.
  1610. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1611. *
  1612. * Return: void
  1613. */
  1614. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1615. struct dp_tx_msdu_info_s *msdu_info)
  1616. {
  1617. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1618. /*
  1619. * skip_sw_tid_classification flag will set in below cases-
  1620. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1621. * 2. hlos_tid_override enabled for vdev
  1622. * 3. mesh mode enabled for vdev
  1623. */
  1624. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1625. /* Update tid in msdu_info from skb priority */
  1626. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1627. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1628. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1629. if (tid == DP_TX_INVALID_QOS_TAG)
  1630. return;
  1631. msdu_info->tid = tid;
  1632. return;
  1633. }
  1634. return;
  1635. }
  1636. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1637. }
  1638. #ifdef FEATURE_WLAN_TDLS
  1639. /**
  1640. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1641. * @soc: datapath SOC
  1642. * @vdev: datapath vdev
  1643. * @tx_desc: TX descriptor
  1644. *
  1645. * Return: None
  1646. */
  1647. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1648. struct dp_vdev *vdev,
  1649. struct dp_tx_desc_s *tx_desc)
  1650. {
  1651. if (vdev) {
  1652. if (vdev->is_tdls_frame) {
  1653. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1654. vdev->is_tdls_frame = false;
  1655. }
  1656. }
  1657. }
  1658. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1659. {
  1660. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1661. switch (soc->arch_id) {
  1662. case CDP_ARCH_TYPE_LI:
  1663. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1664. break;
  1665. case CDP_ARCH_TYPE_BE:
  1666. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1667. break;
  1668. default:
  1669. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1670. QDF_BUG(0);
  1671. }
  1672. return tx_status;
  1673. }
  1674. /**
  1675. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1676. * @soc: dp_soc handle
  1677. * @tx_desc: TX descriptor
  1678. * @vdev: datapath vdev handle
  1679. *
  1680. * Return: None
  1681. */
  1682. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1683. struct dp_tx_desc_s *tx_desc)
  1684. {
  1685. uint8_t tx_status = 0;
  1686. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1687. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1688. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1689. DP_MOD_ID_TDLS);
  1690. if (qdf_unlikely(!vdev)) {
  1691. dp_err_rl("vdev is null!");
  1692. goto error;
  1693. }
  1694. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1695. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1696. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1697. if (vdev->tx_non_std_data_callback.func) {
  1698. qdf_nbuf_set_next(nbuf, NULL);
  1699. vdev->tx_non_std_data_callback.func(
  1700. vdev->tx_non_std_data_callback.ctxt,
  1701. nbuf, tx_status);
  1702. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1703. return;
  1704. } else {
  1705. dp_err_rl("callback func is null");
  1706. }
  1707. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1708. error:
  1709. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1710. qdf_nbuf_free(nbuf);
  1711. }
  1712. /**
  1713. * dp_tx_msdu_single_map() - do nbuf map
  1714. * @vdev: DP vdev handle
  1715. * @tx_desc: DP TX descriptor pointer
  1716. * @nbuf: skb pointer
  1717. *
  1718. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1719. * operation done in other component.
  1720. *
  1721. * Return: QDF_STATUS
  1722. */
  1723. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1724. struct dp_tx_desc_s *tx_desc,
  1725. qdf_nbuf_t nbuf)
  1726. {
  1727. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1728. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1729. nbuf,
  1730. QDF_DMA_TO_DEVICE,
  1731. nbuf->len);
  1732. else
  1733. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1734. QDF_DMA_TO_DEVICE);
  1735. }
  1736. #else
  1737. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1738. struct dp_vdev *vdev,
  1739. struct dp_tx_desc_s *tx_desc)
  1740. {
  1741. }
  1742. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1743. struct dp_tx_desc_s *tx_desc)
  1744. {
  1745. }
  1746. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1747. struct dp_tx_desc_s *tx_desc,
  1748. qdf_nbuf_t nbuf)
  1749. {
  1750. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1751. nbuf,
  1752. QDF_DMA_TO_DEVICE,
  1753. nbuf->len);
  1754. }
  1755. #endif
  1756. static inline
  1757. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1758. struct dp_tx_desc_s *tx_desc,
  1759. qdf_nbuf_t nbuf)
  1760. {
  1761. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1762. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1763. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1764. return 0;
  1765. return qdf_nbuf_mapped_paddr_get(nbuf);
  1766. }
  1767. static inline
  1768. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1769. {
  1770. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1771. desc->nbuf,
  1772. desc->dma_addr,
  1773. QDF_DMA_TO_DEVICE,
  1774. desc->length);
  1775. }
  1776. #ifdef QCA_DP_TX_RMNET_OPTIMIZATION
  1777. static inline bool
  1778. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1779. {
  1780. struct net_device *ingress_dev;
  1781. skb_frag_t *frag;
  1782. uint16_t buf_len = 0;
  1783. uint16_t linear_data_len = 0;
  1784. uint8_t *payload_addr = NULL;
  1785. ingress_dev = dev_get_by_index(dev_net(nbuf->dev), nbuf->skb_iif);
  1786. if ((ingress_dev->priv_flags & IFF_PHONY_HEADROOM)) {
  1787. dev_put(ingress_dev);
  1788. frag = &(skb_shinfo(nbuf)->frags[0]);
  1789. buf_len = skb_frag_size(frag);
  1790. payload_addr = (uint8_t *)skb_frag_address(frag);
  1791. linear_data_len = skb_headlen(nbuf);
  1792. buf_len += linear_data_len;
  1793. payload_addr = payload_addr - linear_data_len;
  1794. memcpy(payload_addr, nbuf->data, linear_data_len);
  1795. msdu_info->frm_type = dp_tx_frm_rmnet;
  1796. msdu_info->buf_len = buf_len;
  1797. msdu_info->payload_addr = payload_addr;
  1798. return true;
  1799. }
  1800. dev_put(ingress_dev);
  1801. return false;
  1802. }
  1803. static inline
  1804. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1805. struct dp_tx_desc_s *tx_desc)
  1806. {
  1807. qdf_dma_addr_t paddr;
  1808. paddr = (qdf_dma_addr_t)qdf_mem_virt_to_phys(msdu_info->payload_addr);
  1809. tx_desc->length = msdu_info->buf_len;
  1810. qdf_nbuf_dma_clean_range((void *)msdu_info->payload_addr,
  1811. (void *)(msdu_info->payload_addr +
  1812. msdu_info->buf_len));
  1813. tx_desc->flags |= DP_TX_DESC_FLAG_RMNET;
  1814. return paddr;
  1815. }
  1816. #else
  1817. static inline bool
  1818. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1819. {
  1820. return false;
  1821. }
  1822. static inline
  1823. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1824. struct dp_tx_desc_s *tx_desc)
  1825. {
  1826. return 0;
  1827. }
  1828. #endif
  1829. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1830. static inline
  1831. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1832. struct dp_tx_desc_s *tx_desc,
  1833. qdf_nbuf_t nbuf)
  1834. {
  1835. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1836. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1837. (void *)(nbuf->data + nbuf->len));
  1838. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1839. } else {
  1840. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1841. }
  1842. }
  1843. static inline
  1844. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1845. struct dp_tx_desc_s *desc)
  1846. {
  1847. if (qdf_unlikely(!(desc->flags &
  1848. (DP_TX_DESC_FLAG_SIMPLE | DP_TX_DESC_FLAG_RMNET))))
  1849. return dp_tx_nbuf_unmap_regular(soc, desc);
  1850. }
  1851. #else
  1852. static inline
  1853. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1854. struct dp_tx_desc_s *tx_desc,
  1855. qdf_nbuf_t nbuf)
  1856. {
  1857. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1858. }
  1859. static inline
  1860. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1861. struct dp_tx_desc_s *desc)
  1862. {
  1863. return dp_tx_nbuf_unmap_regular(soc, desc);
  1864. }
  1865. #endif
  1866. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1867. static inline
  1868. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1869. {
  1870. dp_tx_nbuf_unmap(soc, desc);
  1871. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1872. }
  1873. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1874. {
  1875. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1876. dp_tx_nbuf_unmap(soc, desc);
  1877. }
  1878. #else
  1879. static inline
  1880. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1881. {
  1882. }
  1883. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1884. {
  1885. dp_tx_nbuf_unmap(soc, desc);
  1886. }
  1887. #endif
  1888. #ifdef MESH_MODE_SUPPORT
  1889. /**
  1890. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1891. * @soc: datapath SOC
  1892. * @vdev: datapath vdev
  1893. * @tx_desc: TX descriptor
  1894. *
  1895. * Return: None
  1896. */
  1897. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1898. struct dp_vdev *vdev,
  1899. struct dp_tx_desc_s *tx_desc)
  1900. {
  1901. if (qdf_unlikely(vdev->mesh_vdev))
  1902. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1903. }
  1904. /**
  1905. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1906. * @soc: dp_soc handle
  1907. * @tx_desc: TX descriptor
  1908. * @delayed_free: delay the nbuf free
  1909. *
  1910. * Return: nbuf to be freed late
  1911. */
  1912. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1913. struct dp_tx_desc_s *tx_desc,
  1914. bool delayed_free)
  1915. {
  1916. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1917. struct dp_vdev *vdev = NULL;
  1918. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1919. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1920. if (vdev)
  1921. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1922. if (delayed_free)
  1923. return nbuf;
  1924. qdf_nbuf_free(nbuf);
  1925. } else {
  1926. if (vdev && vdev->osif_tx_free_ext) {
  1927. vdev->osif_tx_free_ext((nbuf));
  1928. } else {
  1929. if (delayed_free)
  1930. return nbuf;
  1931. qdf_nbuf_free(nbuf);
  1932. }
  1933. }
  1934. if (vdev)
  1935. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1936. return NULL;
  1937. }
  1938. #else
  1939. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1940. struct dp_vdev *vdev,
  1941. struct dp_tx_desc_s *tx_desc)
  1942. {
  1943. }
  1944. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1945. struct dp_tx_desc_s *tx_desc,
  1946. bool delayed_free)
  1947. {
  1948. return NULL;
  1949. }
  1950. #endif
  1951. /**
  1952. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1953. * @vdev: DP vdev handle
  1954. * @nbuf: skb
  1955. *
  1956. * Return: 1 if frame needs to be dropped else 0
  1957. */
  1958. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1959. {
  1960. struct dp_pdev *pdev = NULL;
  1961. struct dp_ast_entry *src_ast_entry = NULL;
  1962. struct dp_ast_entry *dst_ast_entry = NULL;
  1963. struct dp_soc *soc = NULL;
  1964. qdf_assert(vdev);
  1965. pdev = vdev->pdev;
  1966. qdf_assert(pdev);
  1967. soc = pdev->soc;
  1968. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1969. (soc, dstmac, vdev->pdev->pdev_id);
  1970. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1971. (soc, srcmac, vdev->pdev->pdev_id);
  1972. if (dst_ast_entry && src_ast_entry) {
  1973. if (dst_ast_entry->peer_id ==
  1974. src_ast_entry->peer_id)
  1975. return 1;
  1976. }
  1977. return 0;
  1978. }
  1979. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1980. defined(WLAN_MCAST_MLO)
  1981. /* MLO peer id for reinject*/
  1982. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1983. /* MLO vdev id inc offset */
  1984. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1985. static inline void
  1986. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1987. {
  1988. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1989. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1990. qdf_atomic_inc(&soc->num_tx_exception);
  1991. }
  1992. }
  1993. static inline void
  1994. dp_tx_update_mcast_param(uint16_t peer_id,
  1995. uint16_t *htt_tcl_metadata,
  1996. struct dp_vdev *vdev,
  1997. struct dp_tx_msdu_info_s *msdu_info)
  1998. {
  1999. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  2000. *htt_tcl_metadata = 0;
  2001. DP_TX_TCL_METADATA_TYPE_SET(
  2002. *htt_tcl_metadata,
  2003. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  2004. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  2005. msdu_info->gsn);
  2006. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  2007. if (qdf_unlikely(vdev->nawds_enabled))
  2008. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  2009. *htt_tcl_metadata, 1);
  2010. } else {
  2011. msdu_info->vdev_id = vdev->vdev_id;
  2012. }
  2013. }
  2014. #else
  2015. static inline void
  2016. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2017. {
  2018. }
  2019. static inline void
  2020. dp_tx_update_mcast_param(uint16_t peer_id,
  2021. uint16_t *htt_tcl_metadata,
  2022. struct dp_vdev *vdev,
  2023. struct dp_tx_msdu_info_s *msdu_info)
  2024. {
  2025. }
  2026. #endif
  2027. #ifdef DP_TX_SW_DROP_STATS_INC
  2028. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2029. qdf_nbuf_t nbuf,
  2030. enum cdp_tx_sw_drop drop_code)
  2031. {
  2032. /* EAPOL Drop stats */
  2033. if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf)) {
  2034. switch (drop_code) {
  2035. case TX_DESC_ERR:
  2036. DP_STATS_INC(pdev, eap_drop_stats.tx_desc_err, 1);
  2037. break;
  2038. case TX_HAL_RING_ACCESS_ERR:
  2039. DP_STATS_INC(pdev,
  2040. eap_drop_stats.tx_hal_ring_access_err, 1);
  2041. break;
  2042. case TX_DMA_MAP_ERR:
  2043. DP_STATS_INC(pdev, eap_drop_stats.tx_dma_map_err, 1);
  2044. break;
  2045. case TX_HW_ENQUEUE:
  2046. DP_STATS_INC(pdev, eap_drop_stats.tx_hw_enqueue, 1);
  2047. break;
  2048. case TX_SW_ENQUEUE:
  2049. DP_STATS_INC(pdev, eap_drop_stats.tx_sw_enqueue, 1);
  2050. break;
  2051. default:
  2052. dp_info_rl("Invalid eapol_drop code: %d", drop_code);
  2053. break;
  2054. }
  2055. }
  2056. }
  2057. #else
  2058. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2059. qdf_nbuf_t nbuf,
  2060. enum cdp_tx_sw_drop drop_code)
  2061. {
  2062. }
  2063. #endif
  2064. /**
  2065. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  2066. * @vdev: DP vdev handle
  2067. * @nbuf: skb
  2068. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  2069. * @meta_data: Metadata to the fw
  2070. * @tx_q: Tx queue to be used for this Tx frame
  2071. * @peer_id: peer_id of the peer in case of NAWDS frames
  2072. * @tx_exc_metadata: Handle that holds exception path metadata
  2073. *
  2074. * Return: NULL on success,
  2075. * nbuf when it fails to send
  2076. */
  2077. qdf_nbuf_t
  2078. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2079. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  2080. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2081. {
  2082. struct dp_pdev *pdev = vdev->pdev;
  2083. struct dp_soc *soc = pdev->soc;
  2084. struct dp_tx_desc_s *tx_desc;
  2085. QDF_STATUS status;
  2086. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  2087. uint16_t htt_tcl_metadata = 0;
  2088. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  2089. uint8_t tid = msdu_info->tid;
  2090. struct cdp_tid_tx_stats *tid_stats = NULL;
  2091. qdf_dma_addr_t paddr;
  2092. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2093. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2094. msdu_info, tx_exc_metadata);
  2095. if (!tx_desc) {
  2096. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2097. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2098. drop_code = TX_DESC_ERR;
  2099. goto fail_return;
  2100. }
  2101. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2102. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2103. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2104. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2105. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2106. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2107. DP_TCL_METADATA_TYPE_PEER_BASED);
  2108. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2109. peer_id);
  2110. dp_tx_bypass_reinjection(soc, tx_desc);
  2111. } else
  2112. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2113. if (msdu_info->exception_fw)
  2114. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2115. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2116. !pdev->enhanced_stats_en);
  2117. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2118. if (qdf_unlikely(msdu_info->frm_type == dp_tx_frm_rmnet))
  2119. paddr = dp_tx_rmnet_nbuf_map(msdu_info, tx_desc);
  2120. else
  2121. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2122. if (!paddr) {
  2123. /* Handle failure */
  2124. dp_err("qdf_nbuf_map failed");
  2125. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2126. drop_code = TX_DMA_MAP_ERR;
  2127. goto release_desc;
  2128. }
  2129. tx_desc->dma_addr = paddr;
  2130. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2131. tx_desc->id, DP_TX_DESC_MAP);
  2132. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2133. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2134. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2135. htt_tcl_metadata,
  2136. tx_exc_metadata, msdu_info);
  2137. if (status != QDF_STATUS_SUCCESS) {
  2138. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2139. tx_desc, tx_q->ring_id);
  2140. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2141. tx_desc->id, DP_TX_DESC_UNMAP);
  2142. dp_tx_nbuf_unmap(soc, tx_desc);
  2143. drop_code = TX_HW_ENQUEUE;
  2144. goto release_desc;
  2145. }
  2146. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2147. return NULL;
  2148. release_desc:
  2149. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2150. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2151. fail_return:
  2152. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2153. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2154. tid_stats = &pdev->stats.tid_stats.
  2155. tid_tx_stats[tx_q->ring_id][tid];
  2156. tid_stats->swdrop_cnt[drop_code]++;
  2157. return nbuf;
  2158. }
  2159. /**
  2160. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2161. * @soc: Soc handle
  2162. * @desc: software Tx descriptor to be processed
  2163. * @delayed_free: defer freeing of nbuf
  2164. *
  2165. * Return: nbuf to be freed later
  2166. */
  2167. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2168. bool delayed_free)
  2169. {
  2170. qdf_nbuf_t nbuf = desc->nbuf;
  2171. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2172. /* nbuf already freed in vdev detach path */
  2173. if (!nbuf)
  2174. return NULL;
  2175. /* If it is TDLS mgmt, don't unmap or free the frame */
  2176. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2177. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2178. return NULL;
  2179. }
  2180. /* 0 : MSDU buffer, 1 : MLE */
  2181. if (desc->msdu_ext_desc) {
  2182. /* TSO free */
  2183. if (hal_tx_ext_desc_get_tso_enable(
  2184. desc->msdu_ext_desc->vaddr)) {
  2185. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2186. desc->id, DP_TX_COMP_MSDU_EXT);
  2187. dp_tx_tso_seg_history_add(soc,
  2188. desc->msdu_ext_desc->tso_desc,
  2189. desc->nbuf, desc->id, type);
  2190. /* unmap eash TSO seg before free the nbuf */
  2191. dp_tx_tso_unmap_segment(soc,
  2192. desc->msdu_ext_desc->tso_desc,
  2193. desc->msdu_ext_desc->
  2194. tso_num_desc);
  2195. goto nbuf_free;
  2196. }
  2197. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2198. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2199. qdf_dma_addr_t iova;
  2200. uint32_t frag_len;
  2201. uint32_t i;
  2202. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2203. QDF_DMA_TO_DEVICE,
  2204. qdf_nbuf_headlen(nbuf));
  2205. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2206. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2207. &iova,
  2208. &frag_len);
  2209. if (!iova || !frag_len)
  2210. break;
  2211. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2212. QDF_DMA_TO_DEVICE);
  2213. }
  2214. goto nbuf_free;
  2215. }
  2216. }
  2217. /* If it's ME frame, dont unmap the cloned nbuf's */
  2218. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2219. goto nbuf_free;
  2220. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2221. dp_tx_unmap(soc, desc);
  2222. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2223. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2224. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2225. return NULL;
  2226. nbuf_free:
  2227. if (delayed_free)
  2228. return nbuf;
  2229. qdf_nbuf_free(nbuf);
  2230. return NULL;
  2231. }
  2232. /**
  2233. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2234. * @soc: DP soc handle
  2235. * @nbuf: skb
  2236. * @msdu_info: MSDU info
  2237. *
  2238. * Return: None
  2239. */
  2240. static inline void
  2241. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2242. struct dp_tx_msdu_info_s *msdu_info)
  2243. {
  2244. uint32_t cur_idx;
  2245. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2246. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2247. qdf_nbuf_headlen(nbuf));
  2248. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2249. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2250. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2251. seg->frags[cur_idx].paddr_hi) << 32),
  2252. seg->frags[cur_idx].len,
  2253. QDF_DMA_TO_DEVICE);
  2254. }
  2255. /**
  2256. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2257. * @vdev: DP vdev handle
  2258. * @nbuf: skb
  2259. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2260. *
  2261. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2262. *
  2263. * Return: NULL on success,
  2264. * nbuf when it fails to send
  2265. */
  2266. #if QDF_LOCK_STATS
  2267. noinline
  2268. #else
  2269. #endif
  2270. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2271. struct dp_tx_msdu_info_s *msdu_info)
  2272. {
  2273. uint32_t i;
  2274. struct dp_pdev *pdev = vdev->pdev;
  2275. struct dp_soc *soc = pdev->soc;
  2276. struct dp_tx_desc_s *tx_desc;
  2277. bool is_cce_classified = false;
  2278. QDF_STATUS status;
  2279. uint16_t htt_tcl_metadata = 0;
  2280. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2281. struct cdp_tid_tx_stats *tid_stats = NULL;
  2282. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2283. if (msdu_info->frm_type == dp_tx_frm_me)
  2284. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2285. i = 0;
  2286. /* Print statement to track i and num_seg */
  2287. /*
  2288. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2289. * descriptors using information in msdu_info
  2290. */
  2291. while (i < msdu_info->num_seg) {
  2292. /*
  2293. * Setup Tx descriptor for an MSDU, and MSDU extension
  2294. * descriptor
  2295. */
  2296. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2297. tx_q->desc_pool_id);
  2298. if (!tx_desc) {
  2299. if (msdu_info->frm_type == dp_tx_frm_me) {
  2300. prep_desc_fail++;
  2301. dp_tx_me_free_buf(pdev,
  2302. (void *)(msdu_info->u.sg_info
  2303. .curr_seg->frags[0].vaddr));
  2304. if (prep_desc_fail == msdu_info->num_seg) {
  2305. /*
  2306. * Unmap is needed only if descriptor
  2307. * preparation failed for all segments.
  2308. */
  2309. qdf_nbuf_unmap(soc->osdev,
  2310. msdu_info->u.sg_info.
  2311. curr_seg->nbuf,
  2312. QDF_DMA_TO_DEVICE);
  2313. }
  2314. /*
  2315. * Free the nbuf for the current segment
  2316. * and make it point to the next in the list.
  2317. * For me, there are as many segments as there
  2318. * are no of clients.
  2319. */
  2320. qdf_nbuf_free(msdu_info->u.sg_info
  2321. .curr_seg->nbuf);
  2322. if (msdu_info->u.sg_info.curr_seg->next) {
  2323. msdu_info->u.sg_info.curr_seg =
  2324. msdu_info->u.sg_info
  2325. .curr_seg->next;
  2326. nbuf = msdu_info->u.sg_info
  2327. .curr_seg->nbuf;
  2328. }
  2329. i++;
  2330. continue;
  2331. }
  2332. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2333. dp_tx_tso_seg_history_add(
  2334. soc,
  2335. msdu_info->u.tso_info.curr_seg,
  2336. nbuf, 0, DP_TX_DESC_UNMAP);
  2337. dp_tx_tso_unmap_segment(soc,
  2338. msdu_info->u.tso_info.
  2339. curr_seg,
  2340. msdu_info->u.tso_info.
  2341. tso_num_seg_list);
  2342. if (msdu_info->u.tso_info.curr_seg->next) {
  2343. msdu_info->u.tso_info.curr_seg =
  2344. msdu_info->u.tso_info.curr_seg->next;
  2345. i++;
  2346. continue;
  2347. }
  2348. }
  2349. if (msdu_info->frm_type == dp_tx_frm_sg)
  2350. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2351. goto done;
  2352. }
  2353. if (msdu_info->frm_type == dp_tx_frm_me) {
  2354. tx_desc->msdu_ext_desc->me_buffer =
  2355. (struct dp_tx_me_buf_t *)msdu_info->
  2356. u.sg_info.curr_seg->frags[0].vaddr;
  2357. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2358. }
  2359. if (is_cce_classified)
  2360. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2361. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2362. if (msdu_info->exception_fw) {
  2363. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2364. }
  2365. dp_tx_is_hp_update_required(i, msdu_info);
  2366. /*
  2367. * For frames with multiple segments (TSO, ME), jump to next
  2368. * segment.
  2369. */
  2370. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2371. if (msdu_info->u.tso_info.curr_seg->next) {
  2372. msdu_info->u.tso_info.curr_seg =
  2373. msdu_info->u.tso_info.curr_seg->next;
  2374. /*
  2375. * If this is a jumbo nbuf, then increment the
  2376. * number of nbuf users for each additional
  2377. * segment of the msdu. This will ensure that
  2378. * the skb is freed only after receiving tx
  2379. * completion for all segments of an nbuf
  2380. */
  2381. qdf_nbuf_inc_users(nbuf);
  2382. /* Check with MCL if this is needed */
  2383. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2384. */
  2385. }
  2386. }
  2387. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2388. &htt_tcl_metadata,
  2389. vdev,
  2390. msdu_info);
  2391. /*
  2392. * Enqueue the Tx MSDU descriptor to HW for transmit
  2393. */
  2394. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2395. htt_tcl_metadata,
  2396. NULL, msdu_info);
  2397. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2398. if (status != QDF_STATUS_SUCCESS) {
  2399. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2400. tx_desc, tx_q->ring_id);
  2401. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2402. tid_stats = &pdev->stats.tid_stats.
  2403. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2404. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2405. if (msdu_info->frm_type == dp_tx_frm_me) {
  2406. hw_enq_fail++;
  2407. if (hw_enq_fail == msdu_info->num_seg) {
  2408. /*
  2409. * Unmap is needed only if enqueue
  2410. * failed for all segments.
  2411. */
  2412. qdf_nbuf_unmap(soc->osdev,
  2413. msdu_info->u.sg_info.
  2414. curr_seg->nbuf,
  2415. QDF_DMA_TO_DEVICE);
  2416. }
  2417. /*
  2418. * Free the nbuf for the current segment
  2419. * and make it point to the next in the list.
  2420. * For me, there are as many segments as there
  2421. * are no of clients.
  2422. */
  2423. qdf_nbuf_free(msdu_info->u.sg_info
  2424. .curr_seg->nbuf);
  2425. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2426. if (msdu_info->u.sg_info.curr_seg->next) {
  2427. msdu_info->u.sg_info.curr_seg =
  2428. msdu_info->u.sg_info
  2429. .curr_seg->next;
  2430. nbuf = msdu_info->u.sg_info
  2431. .curr_seg->nbuf;
  2432. } else
  2433. break;
  2434. i++;
  2435. continue;
  2436. }
  2437. /*
  2438. * For TSO frames, the nbuf users increment done for
  2439. * the current segment has to be reverted, since the
  2440. * hw enqueue for this segment failed
  2441. */
  2442. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2443. msdu_info->u.tso_info.curr_seg) {
  2444. /*
  2445. * unmap and free current,
  2446. * retransmit remaining segments
  2447. */
  2448. dp_tx_comp_free_buf(soc, tx_desc, false);
  2449. i++;
  2450. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2451. continue;
  2452. }
  2453. if (msdu_info->frm_type == dp_tx_frm_sg)
  2454. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2455. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2456. goto done;
  2457. }
  2458. /*
  2459. * TODO
  2460. * if tso_info structure can be modified to have curr_seg
  2461. * as first element, following 2 blocks of code (for TSO and SG)
  2462. * can be combined into 1
  2463. */
  2464. /*
  2465. * For Multicast-Unicast converted packets,
  2466. * each converted frame (for a client) is represented as
  2467. * 1 segment
  2468. */
  2469. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2470. (msdu_info->frm_type == dp_tx_frm_me)) {
  2471. if (msdu_info->u.sg_info.curr_seg->next) {
  2472. msdu_info->u.sg_info.curr_seg =
  2473. msdu_info->u.sg_info.curr_seg->next;
  2474. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2475. } else
  2476. break;
  2477. }
  2478. i++;
  2479. }
  2480. nbuf = NULL;
  2481. done:
  2482. return nbuf;
  2483. }
  2484. /**
  2485. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2486. * for SG frames
  2487. * @vdev: DP vdev handle
  2488. * @nbuf: skb
  2489. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2490. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2491. *
  2492. * Return: NULL on success,
  2493. * nbuf when it fails to send
  2494. */
  2495. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2496. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2497. {
  2498. uint32_t cur_frag, nr_frags, i;
  2499. qdf_dma_addr_t paddr;
  2500. struct dp_tx_sg_info_s *sg_info;
  2501. sg_info = &msdu_info->u.sg_info;
  2502. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2503. if (QDF_STATUS_SUCCESS !=
  2504. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2505. QDF_DMA_TO_DEVICE,
  2506. qdf_nbuf_headlen(nbuf))) {
  2507. dp_tx_err("dma map error");
  2508. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2509. qdf_nbuf_free(nbuf);
  2510. return NULL;
  2511. }
  2512. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2513. seg_info->frags[0].paddr_lo = paddr;
  2514. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2515. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2516. seg_info->frags[0].vaddr = (void *) nbuf;
  2517. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2518. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2519. nbuf, 0,
  2520. QDF_DMA_TO_DEVICE,
  2521. cur_frag)) {
  2522. dp_tx_err("frag dma map error");
  2523. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2524. goto map_err;
  2525. }
  2526. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2527. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2528. seg_info->frags[cur_frag + 1].paddr_hi =
  2529. ((uint64_t) paddr) >> 32;
  2530. seg_info->frags[cur_frag + 1].len =
  2531. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2532. }
  2533. seg_info->frag_cnt = (cur_frag + 1);
  2534. seg_info->total_len = qdf_nbuf_len(nbuf);
  2535. seg_info->next = NULL;
  2536. sg_info->curr_seg = seg_info;
  2537. msdu_info->frm_type = dp_tx_frm_sg;
  2538. msdu_info->num_seg = 1;
  2539. return nbuf;
  2540. map_err:
  2541. /* restore paddr into nbuf before calling unmap */
  2542. qdf_nbuf_mapped_paddr_set(nbuf,
  2543. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2544. ((uint64_t)
  2545. seg_info->frags[0].paddr_hi) << 32));
  2546. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2547. QDF_DMA_TO_DEVICE,
  2548. seg_info->frags[0].len);
  2549. for (i = 1; i <= cur_frag; i++) {
  2550. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2551. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2552. seg_info->frags[i].paddr_hi) << 32),
  2553. seg_info->frags[i].len,
  2554. QDF_DMA_TO_DEVICE);
  2555. }
  2556. qdf_nbuf_free(nbuf);
  2557. return NULL;
  2558. }
  2559. /**
  2560. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2561. * @vdev: DP vdev handle
  2562. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2563. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2564. *
  2565. * Return: NULL on failure,
  2566. * nbuf when extracted successfully
  2567. */
  2568. static
  2569. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2570. struct dp_tx_msdu_info_s *msdu_info,
  2571. uint16_t ppdu_cookie)
  2572. {
  2573. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2574. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2575. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2576. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2577. (msdu_info->meta_data[5], 1);
  2578. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2579. (msdu_info->meta_data[5], 1);
  2580. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2581. (msdu_info->meta_data[6], ppdu_cookie);
  2582. msdu_info->exception_fw = 1;
  2583. msdu_info->is_tx_sniffer = 1;
  2584. }
  2585. #ifdef MESH_MODE_SUPPORT
  2586. /**
  2587. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2588. and prepare msdu_info for mesh frames.
  2589. * @vdev: DP vdev handle
  2590. * @nbuf: skb
  2591. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2592. *
  2593. * Return: NULL on failure,
  2594. * nbuf when extracted successfully
  2595. */
  2596. static
  2597. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2598. struct dp_tx_msdu_info_s *msdu_info)
  2599. {
  2600. struct meta_hdr_s *mhdr;
  2601. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2602. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2603. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2604. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2605. msdu_info->exception_fw = 0;
  2606. goto remove_meta_hdr;
  2607. }
  2608. msdu_info->exception_fw = 1;
  2609. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2610. meta_data->host_tx_desc_pool = 1;
  2611. meta_data->update_peer_cache = 1;
  2612. meta_data->learning_frame = 1;
  2613. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2614. meta_data->power = mhdr->power;
  2615. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2616. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2617. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2618. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2619. meta_data->dyn_bw = 1;
  2620. meta_data->valid_pwr = 1;
  2621. meta_data->valid_mcs_mask = 1;
  2622. meta_data->valid_nss_mask = 1;
  2623. meta_data->valid_preamble_type = 1;
  2624. meta_data->valid_retries = 1;
  2625. meta_data->valid_bw_info = 1;
  2626. }
  2627. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2628. meta_data->encrypt_type = 0;
  2629. meta_data->valid_encrypt_type = 1;
  2630. meta_data->learning_frame = 0;
  2631. }
  2632. meta_data->valid_key_flags = 1;
  2633. meta_data->key_flags = (mhdr->keyix & 0x3);
  2634. remove_meta_hdr:
  2635. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2636. dp_tx_err("qdf_nbuf_pull_head failed");
  2637. qdf_nbuf_free(nbuf);
  2638. return NULL;
  2639. }
  2640. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2641. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2642. " tid %d to_fw %d",
  2643. msdu_info->meta_data[0],
  2644. msdu_info->meta_data[1],
  2645. msdu_info->meta_data[2],
  2646. msdu_info->meta_data[3],
  2647. msdu_info->meta_data[4],
  2648. msdu_info->meta_data[5],
  2649. msdu_info->tid, msdu_info->exception_fw);
  2650. return nbuf;
  2651. }
  2652. #else
  2653. static
  2654. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2655. struct dp_tx_msdu_info_s *msdu_info)
  2656. {
  2657. return nbuf;
  2658. }
  2659. #endif
  2660. /**
  2661. * dp_check_exc_metadata() - Checks if parameters are valid
  2662. * @tx_exc - holds all exception path parameters
  2663. *
  2664. * Returns true when all the parameters are valid else false
  2665. *
  2666. */
  2667. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2668. {
  2669. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2670. HTT_INVALID_TID);
  2671. bool invalid_encap_type =
  2672. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2673. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2674. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2675. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2676. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2677. tx_exc->ppdu_cookie == 0);
  2678. if (tx_exc->is_intrabss_fwd)
  2679. return true;
  2680. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2681. invalid_cookie) {
  2682. return false;
  2683. }
  2684. return true;
  2685. }
  2686. #ifdef ATH_SUPPORT_IQUE
  2687. /**
  2688. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2689. * @vdev: vdev handle
  2690. * @nbuf: skb
  2691. *
  2692. * Return: true on success,
  2693. * false on failure
  2694. */
  2695. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2696. {
  2697. qdf_ether_header_t *eh;
  2698. /* Mcast to Ucast Conversion*/
  2699. if (qdf_likely(!vdev->mcast_enhancement_en))
  2700. return true;
  2701. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2702. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2703. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2704. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2705. qdf_nbuf_set_next(nbuf, NULL);
  2706. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2707. qdf_nbuf_len(nbuf));
  2708. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2709. QDF_STATUS_SUCCESS) {
  2710. return false;
  2711. }
  2712. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2713. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2714. QDF_STATUS_SUCCESS) {
  2715. return false;
  2716. }
  2717. }
  2718. }
  2719. return true;
  2720. }
  2721. #else
  2722. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2723. {
  2724. return true;
  2725. }
  2726. #endif
  2727. /**
  2728. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2729. * @nbuf: qdf_nbuf_t
  2730. * @vdev: struct dp_vdev *
  2731. *
  2732. * Allow packet for processing only if it is for peer client which is
  2733. * connected with same vap. Drop packet if client is connected to
  2734. * different vap.
  2735. *
  2736. * Return: QDF_STATUS
  2737. */
  2738. static inline QDF_STATUS
  2739. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2740. {
  2741. struct dp_ast_entry *dst_ast_entry = NULL;
  2742. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2743. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2744. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2745. return QDF_STATUS_SUCCESS;
  2746. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2747. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2748. eh->ether_dhost,
  2749. vdev->vdev_id);
  2750. /* If there is no ast entry, return failure */
  2751. if (qdf_unlikely(!dst_ast_entry)) {
  2752. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2753. return QDF_STATUS_E_FAILURE;
  2754. }
  2755. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2756. return QDF_STATUS_SUCCESS;
  2757. }
  2758. /**
  2759. * dp_tx_nawds_handler() - NAWDS handler
  2760. *
  2761. * @soc: DP soc handle
  2762. * @vdev_id: id of DP vdev handle
  2763. * @msdu_info: msdu_info required to create HTT metadata
  2764. * @nbuf: skb
  2765. *
  2766. * This API transfers the multicast frames with the peer id
  2767. * on NAWDS enabled peer.
  2768. * Return: none
  2769. */
  2770. static inline
  2771. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2772. struct dp_tx_msdu_info_s *msdu_info,
  2773. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2774. {
  2775. struct dp_peer *peer = NULL;
  2776. qdf_nbuf_t nbuf_clone = NULL;
  2777. uint16_t peer_id = DP_INVALID_PEER;
  2778. struct dp_txrx_peer *txrx_peer;
  2779. /* This check avoids pkt forwarding which is entered
  2780. * in the ast table but still doesn't have valid peerid.
  2781. */
  2782. if (sa_peer_id == HTT_INVALID_PEER)
  2783. return;
  2784. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2785. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2786. txrx_peer = dp_get_txrx_peer(peer);
  2787. if (!txrx_peer)
  2788. continue;
  2789. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2790. peer_id = peer->peer_id;
  2791. if (!dp_peer_is_primary_link_peer(peer))
  2792. continue;
  2793. /* Multicast packets needs to be
  2794. * dropped in case of intra bss forwarding
  2795. */
  2796. if (sa_peer_id == txrx_peer->peer_id) {
  2797. dp_tx_debug("multicast packet");
  2798. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2799. tx.nawds_mcast_drop,
  2800. 1);
  2801. continue;
  2802. }
  2803. nbuf_clone = qdf_nbuf_clone(nbuf);
  2804. if (!nbuf_clone) {
  2805. QDF_TRACE(QDF_MODULE_ID_DP,
  2806. QDF_TRACE_LEVEL_ERROR,
  2807. FL("nbuf clone failed"));
  2808. break;
  2809. }
  2810. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2811. msdu_info, peer_id,
  2812. NULL);
  2813. if (nbuf_clone) {
  2814. dp_tx_debug("pkt send failed");
  2815. qdf_nbuf_free(nbuf_clone);
  2816. } else {
  2817. if (peer_id != DP_INVALID_PEER)
  2818. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2819. tx.nawds_mcast,
  2820. 1, qdf_nbuf_len(nbuf));
  2821. }
  2822. }
  2823. }
  2824. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2825. }
  2826. /**
  2827. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2828. * @soc: DP soc handle
  2829. * @vdev_id: id of DP vdev handle
  2830. * @nbuf: skb
  2831. * @tx_exc_metadata: Handle that holds exception path meta data
  2832. *
  2833. * Entry point for Core Tx layer (DP_TX) invoked from
  2834. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2835. *
  2836. * Return: NULL on success,
  2837. * nbuf when it fails to send
  2838. */
  2839. qdf_nbuf_t
  2840. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2841. qdf_nbuf_t nbuf,
  2842. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2843. {
  2844. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2845. qdf_ether_header_t *eh = NULL;
  2846. struct dp_tx_msdu_info_s msdu_info;
  2847. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2848. DP_MOD_ID_TX_EXCEPTION);
  2849. if (qdf_unlikely(!vdev))
  2850. goto fail;
  2851. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2852. if (!tx_exc_metadata)
  2853. goto fail;
  2854. msdu_info.tid = tx_exc_metadata->tid;
  2855. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2856. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2857. QDF_MAC_ADDR_REF(nbuf->data));
  2858. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2859. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2860. dp_tx_err("Invalid parameters in exception path");
  2861. goto fail;
  2862. }
  2863. /* for peer based metadata check if peer is valid */
  2864. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2865. struct dp_peer *peer = NULL;
  2866. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2867. tx_exc_metadata->peer_id,
  2868. DP_MOD_ID_TX_EXCEPTION);
  2869. if (qdf_unlikely(!peer)) {
  2870. DP_STATS_INC(vdev,
  2871. tx_i.dropped.invalid_peer_id_in_exc_path,
  2872. 1);
  2873. goto fail;
  2874. }
  2875. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2876. }
  2877. /* Basic sanity checks for unsupported packets */
  2878. /* MESH mode */
  2879. if (qdf_unlikely(vdev->mesh_vdev)) {
  2880. dp_tx_err("Mesh mode is not supported in exception path");
  2881. goto fail;
  2882. }
  2883. /*
  2884. * Classify the frame and call corresponding
  2885. * "prepare" function which extracts the segment (TSO)
  2886. * and fragmentation information (for TSO , SG, ME, or Raw)
  2887. * into MSDU_INFO structure which is later used to fill
  2888. * SW and HW descriptors.
  2889. */
  2890. if (qdf_nbuf_is_tso(nbuf)) {
  2891. dp_verbose_debug("TSO frame %pK", vdev);
  2892. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2893. qdf_nbuf_len(nbuf));
  2894. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2895. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2896. qdf_nbuf_len(nbuf));
  2897. goto fail;
  2898. }
  2899. goto send_multiple;
  2900. }
  2901. /* SG */
  2902. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2903. struct dp_tx_seg_info_s seg_info = {0};
  2904. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2905. if (!nbuf)
  2906. goto fail;
  2907. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2908. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2909. qdf_nbuf_len(nbuf));
  2910. goto send_multiple;
  2911. }
  2912. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2913. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2914. qdf_nbuf_len(nbuf));
  2915. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2916. tx_exc_metadata->ppdu_cookie);
  2917. }
  2918. /*
  2919. * Get HW Queue to use for this frame.
  2920. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2921. * dedicated for data and 1 for command.
  2922. * "queue_id" maps to one hardware ring.
  2923. * With each ring, we also associate a unique Tx descriptor pool
  2924. * to minimize lock contention for these resources.
  2925. */
  2926. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2927. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2928. if (qdf_unlikely(vdev->nawds_enabled)) {
  2929. /*
  2930. * This is a multicast packet
  2931. */
  2932. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2933. tx_exc_metadata->peer_id);
  2934. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2935. 1, qdf_nbuf_len(nbuf));
  2936. }
  2937. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2938. DP_INVALID_PEER, NULL);
  2939. } else {
  2940. /*
  2941. * Check exception descriptors
  2942. */
  2943. if (dp_tx_exception_limit_check(vdev))
  2944. goto fail;
  2945. /* Single linear frame */
  2946. /*
  2947. * If nbuf is a simple linear frame, use send_single function to
  2948. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2949. * SRNG. There is no need to setup a MSDU extension descriptor.
  2950. */
  2951. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2952. tx_exc_metadata->peer_id,
  2953. tx_exc_metadata);
  2954. }
  2955. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2956. return nbuf;
  2957. send_multiple:
  2958. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2959. fail:
  2960. if (vdev)
  2961. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2962. dp_verbose_debug("pkt send failed");
  2963. return nbuf;
  2964. }
  2965. /**
  2966. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2967. * in exception path in special case to avoid regular exception path chk.
  2968. * @soc: DP soc handle
  2969. * @vdev_id: id of DP vdev handle
  2970. * @nbuf: skb
  2971. * @tx_exc_metadata: Handle that holds exception path meta data
  2972. *
  2973. * Entry point for Core Tx layer (DP_TX) invoked from
  2974. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2975. *
  2976. * Return: NULL on success,
  2977. * nbuf when it fails to send
  2978. */
  2979. qdf_nbuf_t
  2980. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2981. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2982. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2983. {
  2984. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2985. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2986. DP_MOD_ID_TX_EXCEPTION);
  2987. if (qdf_unlikely(!vdev))
  2988. goto fail;
  2989. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2990. == QDF_STATUS_E_FAILURE)) {
  2991. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2992. goto fail;
  2993. }
  2994. /* Unref count as it will again be taken inside dp_tx_exception */
  2995. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2996. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2997. fail:
  2998. if (vdev)
  2999. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3000. dp_verbose_debug("pkt send failed");
  3001. return nbuf;
  3002. }
  3003. /**
  3004. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  3005. * @soc: DP soc handle
  3006. * @vdev_id: DP vdev handle
  3007. * @nbuf: skb
  3008. *
  3009. * Entry point for Core Tx layer (DP_TX) invoked from
  3010. * hard_start_xmit in OSIF/HDD
  3011. *
  3012. * Return: NULL on success,
  3013. * nbuf when it fails to send
  3014. */
  3015. #ifdef MESH_MODE_SUPPORT
  3016. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3017. qdf_nbuf_t nbuf)
  3018. {
  3019. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3020. struct meta_hdr_s *mhdr;
  3021. qdf_nbuf_t nbuf_mesh = NULL;
  3022. qdf_nbuf_t nbuf_clone = NULL;
  3023. struct dp_vdev *vdev;
  3024. uint8_t no_enc_frame = 0;
  3025. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  3026. if (!nbuf_mesh) {
  3027. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3028. "qdf_nbuf_unshare failed");
  3029. return nbuf;
  3030. }
  3031. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  3032. if (!vdev) {
  3033. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3034. "vdev is NULL for vdev_id %d", vdev_id);
  3035. return nbuf;
  3036. }
  3037. nbuf = nbuf_mesh;
  3038. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  3039. if ((vdev->sec_type != cdp_sec_type_none) &&
  3040. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  3041. no_enc_frame = 1;
  3042. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  3043. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  3044. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  3045. !no_enc_frame) {
  3046. nbuf_clone = qdf_nbuf_clone(nbuf);
  3047. if (!nbuf_clone) {
  3048. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3049. "qdf_nbuf_clone failed");
  3050. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3051. return nbuf;
  3052. }
  3053. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  3054. }
  3055. if (nbuf_clone) {
  3056. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  3057. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3058. } else {
  3059. qdf_nbuf_free(nbuf_clone);
  3060. }
  3061. }
  3062. if (no_enc_frame)
  3063. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  3064. else
  3065. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  3066. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  3067. if ((!nbuf) && no_enc_frame) {
  3068. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3069. }
  3070. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3071. return nbuf;
  3072. }
  3073. #else
  3074. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  3075. qdf_nbuf_t nbuf)
  3076. {
  3077. return dp_tx_send(soc, vdev_id, nbuf);
  3078. }
  3079. #endif
  3080. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  3081. static inline
  3082. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3083. {
  3084. if (nbuf) {
  3085. qdf_prefetch(&nbuf->len);
  3086. qdf_prefetch(&nbuf->data);
  3087. }
  3088. }
  3089. #else
  3090. static inline
  3091. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3092. {
  3093. }
  3094. #endif
  3095. #ifdef DP_UMAC_HW_RESET_SUPPORT
  3096. /*
  3097. * dp_tx_drop() - Drop the frame on a given VAP
  3098. * @soc: DP soc handle
  3099. * @vdev_id: id of DP vdev handle
  3100. * @nbuf: skb
  3101. *
  3102. * Drop all the incoming packets
  3103. *
  3104. * Return: nbuf
  3105. *
  3106. */
  3107. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3108. qdf_nbuf_t nbuf)
  3109. {
  3110. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3111. struct dp_vdev *vdev = NULL;
  3112. vdev = soc->vdev_id_map[vdev_id];
  3113. if (qdf_unlikely(!vdev))
  3114. return nbuf;
  3115. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3116. return nbuf;
  3117. }
  3118. /*
  3119. * dp_tx_exc_drop() - Drop the frame on a given VAP
  3120. * @soc: DP soc handle
  3121. * @vdev_id: id of DP vdev handle
  3122. * @nbuf: skb
  3123. * @tx_exc_metadata: Handle that holds exception path meta data
  3124. *
  3125. * Drop all the incoming packets
  3126. *
  3127. * Return: nbuf
  3128. *
  3129. */
  3130. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3131. qdf_nbuf_t nbuf,
  3132. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3133. {
  3134. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3135. }
  3136. #endif
  3137. /*
  3138. * dp_tx_send() - Transmit a frame on a given VAP
  3139. * @soc: DP soc handle
  3140. * @vdev_id: id of DP vdev handle
  3141. * @nbuf: skb
  3142. *
  3143. * Entry point for Core Tx layer (DP_TX) invoked from
  3144. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  3145. * cases
  3146. *
  3147. * Return: NULL on success,
  3148. * nbuf when it fails to send
  3149. */
  3150. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3151. qdf_nbuf_t nbuf)
  3152. {
  3153. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3154. uint16_t peer_id = HTT_INVALID_PEER;
  3155. /*
  3156. * doing a memzero is causing additional function call overhead
  3157. * so doing static stack clearing
  3158. */
  3159. struct dp_tx_msdu_info_s msdu_info = {0};
  3160. struct dp_vdev *vdev = NULL;
  3161. qdf_nbuf_t end_nbuf = NULL;
  3162. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3163. return nbuf;
  3164. /*
  3165. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3166. * this in per packet path.
  3167. *
  3168. * As in this path vdev memory is already protected with netdev
  3169. * tx lock
  3170. */
  3171. vdev = soc->vdev_id_map[vdev_id];
  3172. if (qdf_unlikely(!vdev))
  3173. return nbuf;
  3174. /*
  3175. * Set Default Host TID value to invalid TID
  3176. * (TID override disabled)
  3177. */
  3178. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3179. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_headlen(nbuf));
  3180. if (qdf_unlikely(vdev->mesh_vdev)) {
  3181. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3182. &msdu_info);
  3183. if (!nbuf_mesh) {
  3184. dp_verbose_debug("Extracting mesh metadata failed");
  3185. return nbuf;
  3186. }
  3187. nbuf = nbuf_mesh;
  3188. }
  3189. /*
  3190. * Get HW Queue to use for this frame.
  3191. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3192. * dedicated for data and 1 for command.
  3193. * "queue_id" maps to one hardware ring.
  3194. * With each ring, we also associate a unique Tx descriptor pool
  3195. * to minimize lock contention for these resources.
  3196. */
  3197. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3198. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3199. 1);
  3200. /*
  3201. * TCL H/W supports 2 DSCP-TID mapping tables.
  3202. * Table 1 - Default DSCP-TID mapping table
  3203. * Table 2 - 1 DSCP-TID override table
  3204. *
  3205. * If we need a different DSCP-TID mapping for this vap,
  3206. * call tid_classify to extract DSCP/ToS from frame and
  3207. * map to a TID and store in msdu_info. This is later used
  3208. * to fill in TCL Input descriptor (per-packet TID override).
  3209. */
  3210. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3211. /*
  3212. * Classify the frame and call corresponding
  3213. * "prepare" function which extracts the segment (TSO)
  3214. * and fragmentation information (for TSO , SG, ME, or Raw)
  3215. * into MSDU_INFO structure which is later used to fill
  3216. * SW and HW descriptors.
  3217. */
  3218. if (qdf_nbuf_is_tso(nbuf)) {
  3219. dp_verbose_debug("TSO frame %pK", vdev);
  3220. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3221. qdf_nbuf_len(nbuf));
  3222. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3223. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3224. qdf_nbuf_len(nbuf));
  3225. return nbuf;
  3226. }
  3227. goto send_multiple;
  3228. }
  3229. /* SG */
  3230. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3231. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3232. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3233. return nbuf;
  3234. } else {
  3235. struct dp_tx_seg_info_s seg_info = {0};
  3236. if (qdf_unlikely(is_nbuf_frm_rmnet(nbuf, &msdu_info)))
  3237. goto send_single;
  3238. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3239. &msdu_info);
  3240. if (!nbuf)
  3241. return NULL;
  3242. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3243. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3244. qdf_nbuf_len(nbuf));
  3245. goto send_multiple;
  3246. }
  3247. }
  3248. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3249. return NULL;
  3250. /* RAW */
  3251. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3252. struct dp_tx_seg_info_s seg_info = {0};
  3253. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3254. if (!nbuf)
  3255. return NULL;
  3256. dp_verbose_debug("Raw frame %pK", vdev);
  3257. goto send_multiple;
  3258. }
  3259. if (qdf_unlikely(vdev->nawds_enabled)) {
  3260. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3261. qdf_nbuf_data(nbuf);
  3262. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3263. uint16_t sa_peer_id = DP_INVALID_PEER;
  3264. if (!soc->ast_offload_support) {
  3265. struct dp_ast_entry *ast_entry = NULL;
  3266. qdf_spin_lock_bh(&soc->ast_lock);
  3267. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3268. (soc,
  3269. (uint8_t *)(eh->ether_shost),
  3270. vdev->pdev->pdev_id);
  3271. if (ast_entry)
  3272. sa_peer_id = ast_entry->peer_id;
  3273. qdf_spin_unlock_bh(&soc->ast_lock);
  3274. }
  3275. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3276. sa_peer_id);
  3277. }
  3278. peer_id = DP_INVALID_PEER;
  3279. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3280. 1, qdf_nbuf_len(nbuf));
  3281. }
  3282. send_single:
  3283. /* Single linear frame */
  3284. /*
  3285. * If nbuf is a simple linear frame, use send_single function to
  3286. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3287. * SRNG. There is no need to setup a MSDU extension descriptor.
  3288. */
  3289. dp_tx_prefetch_nbuf_data(nbuf);
  3290. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3291. peer_id, end_nbuf);
  3292. return nbuf;
  3293. send_multiple:
  3294. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3295. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3296. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3297. return nbuf;
  3298. }
  3299. /**
  3300. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3301. * case to vaoid check in perpkt path.
  3302. * @soc: DP soc handle
  3303. * @vdev_id: id of DP vdev handle
  3304. * @nbuf: skb
  3305. *
  3306. * Entry point for Core Tx layer (DP_TX) invoked from
  3307. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3308. * with special condition to avoid per pkt check in dp_tx_send
  3309. *
  3310. * Return: NULL on success,
  3311. * nbuf when it fails to send
  3312. */
  3313. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3314. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3315. {
  3316. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3317. struct dp_vdev *vdev = NULL;
  3318. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3319. return nbuf;
  3320. /*
  3321. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3322. * this in per packet path.
  3323. *
  3324. * As in this path vdev memory is already protected with netdev
  3325. * tx lock
  3326. */
  3327. vdev = soc->vdev_id_map[vdev_id];
  3328. if (qdf_unlikely(!vdev))
  3329. return nbuf;
  3330. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3331. == QDF_STATUS_E_FAILURE)) {
  3332. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3333. return nbuf;
  3334. }
  3335. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3336. }
  3337. #ifdef UMAC_SUPPORT_PROXY_ARP
  3338. /**
  3339. * dp_tx_proxy_arp() - Tx proxy arp handler
  3340. * @vdev: datapath vdev handle
  3341. * @buf: sk buffer
  3342. *
  3343. * Return: status
  3344. */
  3345. static inline
  3346. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3347. {
  3348. if (vdev->osif_proxy_arp)
  3349. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3350. /*
  3351. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3352. * osif_proxy_arp has a valid function pointer assigned
  3353. * to it
  3354. */
  3355. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3356. return QDF_STATUS_NOT_INITIALIZED;
  3357. }
  3358. #else
  3359. /**
  3360. * dp_tx_proxy_arp() - Tx proxy arp handler
  3361. * @vdev: datapath vdev handle
  3362. * @buf: sk buffer
  3363. *
  3364. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3365. * is not defined.
  3366. *
  3367. * Return: status
  3368. */
  3369. static inline
  3370. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3371. {
  3372. return QDF_STATUS_SUCCESS;
  3373. }
  3374. #endif
  3375. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3376. #ifdef WLAN_MCAST_MLO
  3377. static bool
  3378. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3379. struct dp_tx_desc_s *tx_desc,
  3380. qdf_nbuf_t nbuf,
  3381. uint8_t reinject_reason)
  3382. {
  3383. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3384. if (soc->arch_ops.dp_tx_mcast_handler)
  3385. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3386. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3387. return true;
  3388. }
  3389. return false;
  3390. }
  3391. #else /* WLAN_MCAST_MLO */
  3392. static inline bool
  3393. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3394. struct dp_tx_desc_s *tx_desc,
  3395. qdf_nbuf_t nbuf,
  3396. uint8_t reinject_reason)
  3397. {
  3398. return false;
  3399. }
  3400. #endif /* WLAN_MCAST_MLO */
  3401. #else
  3402. static inline bool
  3403. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3404. struct dp_tx_desc_s *tx_desc,
  3405. qdf_nbuf_t nbuf,
  3406. uint8_t reinject_reason)
  3407. {
  3408. return false;
  3409. }
  3410. #endif
  3411. /**
  3412. * dp_tx_reinject_handler() - Tx Reinject Handler
  3413. * @soc: datapath soc handle
  3414. * @vdev: datapath vdev handle
  3415. * @tx_desc: software descriptor head pointer
  3416. * @status : Tx completion status from HTT descriptor
  3417. * @reinject_reason : reinject reason from HTT descriptor
  3418. *
  3419. * This function reinjects frames back to Target.
  3420. * Todo - Host queue needs to be added
  3421. *
  3422. * Return: none
  3423. */
  3424. void dp_tx_reinject_handler(struct dp_soc *soc,
  3425. struct dp_vdev *vdev,
  3426. struct dp_tx_desc_s *tx_desc,
  3427. uint8_t *status,
  3428. uint8_t reinject_reason)
  3429. {
  3430. struct dp_peer *peer = NULL;
  3431. uint32_t peer_id = HTT_INVALID_PEER;
  3432. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3433. qdf_nbuf_t nbuf_copy = NULL;
  3434. struct dp_tx_msdu_info_s msdu_info;
  3435. #ifdef WDS_VENDOR_EXTENSION
  3436. int is_mcast = 0, is_ucast = 0;
  3437. int num_peers_3addr = 0;
  3438. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3439. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3440. #endif
  3441. struct dp_txrx_peer *txrx_peer;
  3442. qdf_assert(vdev);
  3443. dp_tx_debug("Tx reinject path");
  3444. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3445. qdf_nbuf_len(tx_desc->nbuf));
  3446. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3447. return;
  3448. #ifdef WDS_VENDOR_EXTENSION
  3449. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3450. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3451. } else {
  3452. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3453. }
  3454. is_ucast = !is_mcast;
  3455. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3456. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3457. txrx_peer = dp_get_txrx_peer(peer);
  3458. if (!txrx_peer || txrx_peer->bss_peer)
  3459. continue;
  3460. /* Detect wds peers that use 3-addr framing for mcast.
  3461. * if there are any, the bss_peer is used to send the
  3462. * the mcast frame using 3-addr format. all wds enabled
  3463. * peers that use 4-addr framing for mcast frames will
  3464. * be duplicated and sent as 4-addr frames below.
  3465. */
  3466. if (!txrx_peer->wds_enabled ||
  3467. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3468. num_peers_3addr = 1;
  3469. break;
  3470. }
  3471. }
  3472. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3473. #endif
  3474. if (qdf_unlikely(vdev->mesh_vdev)) {
  3475. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3476. } else {
  3477. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3478. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3479. txrx_peer = dp_get_txrx_peer(peer);
  3480. if (!txrx_peer)
  3481. continue;
  3482. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3483. #ifdef WDS_VENDOR_EXTENSION
  3484. /*
  3485. * . if 3-addr STA, then send on BSS Peer
  3486. * . if Peer WDS enabled and accept 4-addr mcast,
  3487. * send mcast on that peer only
  3488. * . if Peer WDS enabled and accept 4-addr ucast,
  3489. * send ucast on that peer only
  3490. */
  3491. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3492. (txrx_peer->wds_enabled &&
  3493. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3494. (is_ucast &&
  3495. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3496. #else
  3497. (txrx_peer->bss_peer &&
  3498. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3499. #endif
  3500. peer_id = DP_INVALID_PEER;
  3501. nbuf_copy = qdf_nbuf_copy(nbuf);
  3502. if (!nbuf_copy) {
  3503. dp_tx_debug("nbuf copy failed");
  3504. break;
  3505. }
  3506. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3507. dp_tx_get_queue(vdev, nbuf,
  3508. &msdu_info.tx_queue);
  3509. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3510. nbuf_copy,
  3511. &msdu_info,
  3512. peer_id,
  3513. NULL);
  3514. if (nbuf_copy) {
  3515. dp_tx_debug("pkt send failed");
  3516. qdf_nbuf_free(nbuf_copy);
  3517. }
  3518. }
  3519. }
  3520. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3521. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3522. QDF_DMA_TO_DEVICE, nbuf->len);
  3523. qdf_nbuf_free(nbuf);
  3524. }
  3525. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3526. }
  3527. /**
  3528. * dp_tx_inspect_handler() - Tx Inspect Handler
  3529. * @soc: datapath soc handle
  3530. * @vdev: datapath vdev handle
  3531. * @tx_desc: software descriptor head pointer
  3532. * @status : Tx completion status from HTT descriptor
  3533. *
  3534. * Handles Tx frames sent back to Host for inspection
  3535. * (ProxyARP)
  3536. *
  3537. * Return: none
  3538. */
  3539. void dp_tx_inspect_handler(struct dp_soc *soc,
  3540. struct dp_vdev *vdev,
  3541. struct dp_tx_desc_s *tx_desc,
  3542. uint8_t *status)
  3543. {
  3544. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3545. "%s Tx inspect path",
  3546. __func__);
  3547. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3548. qdf_nbuf_len(tx_desc->nbuf));
  3549. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3550. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3551. }
  3552. #ifdef MESH_MODE_SUPPORT
  3553. /**
  3554. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3555. * in mesh meta header
  3556. * @tx_desc: software descriptor head pointer
  3557. * @ts: pointer to tx completion stats
  3558. * Return: none
  3559. */
  3560. static
  3561. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3562. struct hal_tx_completion_status *ts)
  3563. {
  3564. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3565. if (!tx_desc->msdu_ext_desc) {
  3566. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3567. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3568. "netbuf %pK offset %d",
  3569. netbuf, tx_desc->pkt_offset);
  3570. return;
  3571. }
  3572. }
  3573. }
  3574. #else
  3575. static
  3576. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3577. struct hal_tx_completion_status *ts)
  3578. {
  3579. }
  3580. #endif
  3581. #ifdef CONFIG_SAWF
  3582. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3583. struct dp_vdev *vdev,
  3584. struct dp_txrx_peer *txrx_peer,
  3585. struct dp_tx_desc_s *tx_desc,
  3586. struct hal_tx_completion_status *ts,
  3587. uint8_t tid)
  3588. {
  3589. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3590. ts, tid);
  3591. }
  3592. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3593. uint32_t nw_delay,
  3594. uint32_t sw_delay,
  3595. uint32_t hw_delay)
  3596. {
  3597. dp_peer_tid_delay_avg(tx_delay,
  3598. nw_delay,
  3599. sw_delay,
  3600. hw_delay);
  3601. }
  3602. #else
  3603. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3604. struct dp_vdev *vdev,
  3605. struct dp_txrx_peer *txrx_peer,
  3606. struct dp_tx_desc_s *tx_desc,
  3607. struct hal_tx_completion_status *ts,
  3608. uint8_t tid)
  3609. {
  3610. }
  3611. static inline void
  3612. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3613. uint32_t nw_delay, uint32_t sw_delay,
  3614. uint32_t hw_delay)
  3615. {
  3616. }
  3617. #endif
  3618. #ifdef QCA_PEER_EXT_STATS
  3619. #ifdef WLAN_CONFIG_TX_DELAY
  3620. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3621. struct dp_tx_desc_s *tx_desc,
  3622. struct hal_tx_completion_status *ts,
  3623. struct dp_vdev *vdev)
  3624. {
  3625. struct dp_soc *soc = vdev->pdev->soc;
  3626. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3627. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3628. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3629. if (!ts->valid)
  3630. return;
  3631. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3632. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3633. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3634. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3635. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3636. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3637. &fwhw_transmit_delay))
  3638. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3639. fwhw_transmit_delay);
  3640. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3641. fwhw_transmit_delay);
  3642. }
  3643. #else
  3644. /*
  3645. * dp_tx_compute_tid_delay() - Compute per TID delay
  3646. * @stats: Per TID delay stats
  3647. * @tx_desc: Software Tx descriptor
  3648. * @ts: Tx completion status
  3649. * @vdev: vdev
  3650. *
  3651. * Compute the software enqueue and hw enqueue delays and
  3652. * update the respective histograms
  3653. *
  3654. * Return: void
  3655. */
  3656. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3657. struct dp_tx_desc_s *tx_desc,
  3658. struct hal_tx_completion_status *ts,
  3659. struct dp_vdev *vdev)
  3660. {
  3661. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3662. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3663. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3664. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3665. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3666. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3667. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3668. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3669. timestamp_hw_enqueue);
  3670. /*
  3671. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3672. */
  3673. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3674. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3675. }
  3676. #endif
  3677. /*
  3678. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3679. * @txrx_peer: DP peer context
  3680. * @tx_desc: Tx software descriptor
  3681. * @tid: Transmission ID
  3682. * @ring_id: Rx CPU context ID/CPU_ID
  3683. *
  3684. * Update the peer extended stats. These are enhanced other
  3685. * delay stats per msdu level.
  3686. *
  3687. * Return: void
  3688. */
  3689. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3690. struct dp_tx_desc_s *tx_desc,
  3691. struct hal_tx_completion_status *ts,
  3692. uint8_t ring_id)
  3693. {
  3694. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3695. struct dp_soc *soc = NULL;
  3696. struct dp_peer_delay_stats *delay_stats = NULL;
  3697. uint8_t tid;
  3698. soc = pdev->soc;
  3699. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3700. return;
  3701. tid = ts->tid;
  3702. delay_stats = txrx_peer->delay_stats;
  3703. qdf_assert(delay_stats);
  3704. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3705. /*
  3706. * For non-TID packets use the TID 9
  3707. */
  3708. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3709. tid = CDP_MAX_DATA_TIDS - 1;
  3710. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3711. tx_desc, ts, txrx_peer->vdev);
  3712. }
  3713. #else
  3714. static inline
  3715. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3716. struct dp_tx_desc_s *tx_desc,
  3717. struct hal_tx_completion_status *ts,
  3718. uint8_t ring_id)
  3719. {
  3720. }
  3721. #endif
  3722. #ifdef WLAN_PEER_JITTER
  3723. /*
  3724. * dp_tx_jitter_get_avg_jitter() - compute the average jitter
  3725. * @curr_delay: Current delay
  3726. * @prev_Delay: Previous delay
  3727. * @avg_jitter: Average Jitter
  3728. * Return: Newly Computed Average Jitter
  3729. */
  3730. static uint32_t dp_tx_jitter_get_avg_jitter(uint32_t curr_delay,
  3731. uint32_t prev_delay,
  3732. uint32_t avg_jitter)
  3733. {
  3734. uint32_t curr_jitter;
  3735. int32_t jitter_diff;
  3736. curr_jitter = qdf_abs(curr_delay - prev_delay);
  3737. if (!avg_jitter)
  3738. return curr_jitter;
  3739. jitter_diff = curr_jitter - avg_jitter;
  3740. if (jitter_diff < 0)
  3741. avg_jitter = avg_jitter -
  3742. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3743. else
  3744. avg_jitter = avg_jitter +
  3745. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3746. return avg_jitter;
  3747. }
  3748. /*
  3749. * dp_tx_jitter_get_avg_delay() - compute the average delay
  3750. * @curr_delay: Current delay
  3751. * @avg_Delay: Average delay
  3752. * Return: Newly Computed Average Delay
  3753. */
  3754. static uint32_t dp_tx_jitter_get_avg_delay(uint32_t curr_delay,
  3755. uint32_t avg_delay)
  3756. {
  3757. int32_t delay_diff;
  3758. if (!avg_delay)
  3759. return curr_delay;
  3760. delay_diff = curr_delay - avg_delay;
  3761. if (delay_diff < 0)
  3762. avg_delay = avg_delay - (qdf_abs(delay_diff) >>
  3763. DP_AVG_DELAY_WEIGHT_DENOM);
  3764. else
  3765. avg_delay = avg_delay + (qdf_abs(delay_diff) >>
  3766. DP_AVG_DELAY_WEIGHT_DENOM);
  3767. return avg_delay;
  3768. }
  3769. #ifdef WLAN_CONFIG_TX_DELAY
  3770. /*
  3771. * dp_tx_compute_cur_delay() - get the current delay
  3772. * @soc: soc handle
  3773. * @vdev: vdev structure for data path state
  3774. * @ts: Tx completion status
  3775. * @curr_delay: current delay
  3776. * @tx_desc: tx descriptor
  3777. * Return: void
  3778. */
  3779. static
  3780. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3781. struct dp_vdev *vdev,
  3782. struct hal_tx_completion_status *ts,
  3783. uint32_t *curr_delay,
  3784. struct dp_tx_desc_s *tx_desc)
  3785. {
  3786. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3787. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3788. status = soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3789. curr_delay);
  3790. return status;
  3791. }
  3792. #else
  3793. static
  3794. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3795. struct dp_vdev *vdev,
  3796. struct hal_tx_completion_status *ts,
  3797. uint32_t *curr_delay,
  3798. struct dp_tx_desc_s *tx_desc)
  3799. {
  3800. int64_t current_timestamp, timestamp_hw_enqueue;
  3801. current_timestamp = qdf_ktime_to_us(qdf_ktime_real_get());
  3802. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3803. *curr_delay = (uint32_t)(current_timestamp - timestamp_hw_enqueue);
  3804. return QDF_STATUS_SUCCESS;
  3805. }
  3806. #endif
  3807. /* dp_tx_compute_tid_jitter() - compute per tid per ring jitter
  3808. * @jiiter - per tid per ring jitter stats
  3809. * @ts: Tx completion status
  3810. * @vdev - vdev structure for data path state
  3811. * @tx_desc - tx descriptor
  3812. * Return: void
  3813. */
  3814. static void dp_tx_compute_tid_jitter(struct cdp_peer_tid_stats *jitter,
  3815. struct hal_tx_completion_status *ts,
  3816. struct dp_vdev *vdev,
  3817. struct dp_tx_desc_s *tx_desc)
  3818. {
  3819. uint32_t curr_delay, avg_delay, avg_jitter, prev_delay;
  3820. struct dp_soc *soc = vdev->pdev->soc;
  3821. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3822. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3823. jitter->tx_drop += 1;
  3824. return;
  3825. }
  3826. status = dp_tx_compute_cur_delay(soc, vdev, ts, &curr_delay,
  3827. tx_desc);
  3828. if (QDF_IS_STATUS_SUCCESS(status)) {
  3829. avg_delay = jitter->tx_avg_delay;
  3830. avg_jitter = jitter->tx_avg_jitter;
  3831. prev_delay = jitter->tx_prev_delay;
  3832. avg_jitter = dp_tx_jitter_get_avg_jitter(curr_delay,
  3833. prev_delay,
  3834. avg_jitter);
  3835. avg_delay = dp_tx_jitter_get_avg_delay(curr_delay, avg_delay);
  3836. jitter->tx_avg_delay = avg_delay;
  3837. jitter->tx_avg_jitter = avg_jitter;
  3838. jitter->tx_prev_delay = curr_delay;
  3839. jitter->tx_total_success += 1;
  3840. } else if (status == QDF_STATUS_E_FAILURE) {
  3841. jitter->tx_avg_err += 1;
  3842. }
  3843. }
  3844. /* dp_tx_update_peer_jitter_stats() - Update the peer jitter stats
  3845. * @txrx_peer: DP peer context
  3846. * @tx_desc: Tx software descriptor
  3847. * @ts: Tx completion status
  3848. * @ring_id: Rx CPU context ID/CPU_ID
  3849. * Return: void
  3850. */
  3851. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3852. struct dp_tx_desc_s *tx_desc,
  3853. struct hal_tx_completion_status *ts,
  3854. uint8_t ring_id)
  3855. {
  3856. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3857. struct dp_soc *soc = pdev->soc;
  3858. struct cdp_peer_tid_stats *jitter_stats = NULL;
  3859. uint8_t tid;
  3860. struct cdp_peer_tid_stats *rx_tid = NULL;
  3861. if (qdf_likely(!wlan_cfg_is_peer_jitter_stats_enabled(soc->wlan_cfg_ctx)))
  3862. return;
  3863. tid = ts->tid;
  3864. jitter_stats = txrx_peer->jitter_stats;
  3865. qdf_assert_always(jitter_stats);
  3866. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3867. /*
  3868. * For non-TID packets use the TID 9
  3869. */
  3870. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3871. tid = CDP_MAX_DATA_TIDS - 1;
  3872. rx_tid = &jitter_stats[tid * CDP_MAX_TXRX_CTX + ring_id];
  3873. dp_tx_compute_tid_jitter(rx_tid,
  3874. ts, txrx_peer->vdev, tx_desc);
  3875. }
  3876. #else
  3877. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3878. struct dp_tx_desc_s *tx_desc,
  3879. struct hal_tx_completion_status *ts,
  3880. uint8_t ring_id)
  3881. {
  3882. }
  3883. #endif
  3884. #ifdef HW_TX_DELAY_STATS_ENABLE
  3885. /**
  3886. * dp_update_tx_delay_stats() - update the delay stats
  3887. * @vdev: vdev handle
  3888. * @delay: delay in ms or us based on the flag delay_in_us
  3889. * @tid: tid value
  3890. * @mode: type of tx delay mode
  3891. * @ring id: ring number
  3892. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3893. *
  3894. * Return: none
  3895. */
  3896. static inline
  3897. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3898. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3899. {
  3900. struct cdp_tid_tx_stats *tstats =
  3901. &vdev->stats.tid_tx_stats[ring_id][tid];
  3902. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3903. delay_in_us);
  3904. }
  3905. #else
  3906. static inline
  3907. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3908. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3909. {
  3910. struct cdp_tid_tx_stats *tstats =
  3911. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3912. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3913. delay_in_us);
  3914. }
  3915. #endif
  3916. /**
  3917. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3918. * to pass in correct fields
  3919. *
  3920. * @vdev: pdev handle
  3921. * @tx_desc: tx descriptor
  3922. * @tid: tid value
  3923. * @ring_id: TCL or WBM ring number for transmit path
  3924. * Return: none
  3925. */
  3926. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3927. uint8_t tid, uint8_t ring_id)
  3928. {
  3929. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3930. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3931. uint32_t fwhw_transmit_delay_us;
  3932. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3933. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3934. return;
  3935. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3936. fwhw_transmit_delay_us =
  3937. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3938. qdf_ktime_to_us(tx_desc->timestamp);
  3939. /*
  3940. * Delay between packet enqueued to HW and Tx completion in us
  3941. */
  3942. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3943. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3944. ring_id, true);
  3945. /*
  3946. * For MCL, only enqueue to completion delay is required
  3947. * so return if the vdev flag is enabled.
  3948. */
  3949. return;
  3950. }
  3951. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3952. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3953. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3954. timestamp_hw_enqueue);
  3955. /*
  3956. * Delay between packet enqueued to HW and Tx completion in ms
  3957. */
  3958. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3959. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3960. false);
  3961. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3962. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3963. interframe_delay = (uint32_t)(timestamp_ingress -
  3964. vdev->prev_tx_enq_tstamp);
  3965. /*
  3966. * Delay in software enqueue
  3967. */
  3968. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3969. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3970. false);
  3971. /*
  3972. * Update interframe delay stats calculated at hardstart receive point.
  3973. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3974. * interframe delay will not be calculate correctly for 1st frame.
  3975. * On the other side, this will help in avoiding extra per packet check
  3976. * of !vdev->prev_tx_enq_tstamp.
  3977. */
  3978. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3979. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3980. false);
  3981. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3982. }
  3983. #ifdef DISABLE_DP_STATS
  3984. static
  3985. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3986. struct dp_txrx_peer *txrx_peer)
  3987. {
  3988. }
  3989. #else
  3990. static inline void
  3991. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3992. {
  3993. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3994. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3995. if (subtype != QDF_PROTO_INVALID)
  3996. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3997. 1);
  3998. }
  3999. #endif
  4000. #ifndef QCA_ENHANCED_STATS_SUPPORT
  4001. #ifdef DP_PEER_EXTENDED_API
  4002. static inline uint8_t
  4003. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  4004. {
  4005. return txrx_peer->mpdu_retry_threshold;
  4006. }
  4007. #else
  4008. static inline uint8_t
  4009. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  4010. {
  4011. return 0;
  4012. }
  4013. #endif
  4014. /**
  4015. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  4016. *
  4017. * @ts: Tx compltion status
  4018. * @txrx_peer: datapath txrx_peer handle
  4019. *
  4020. * Return: void
  4021. */
  4022. static inline void
  4023. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4024. struct dp_txrx_peer *txrx_peer)
  4025. {
  4026. uint8_t mcs, pkt_type, dst_mcs_idx;
  4027. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  4028. mcs = ts->mcs;
  4029. pkt_type = ts->pkt_type;
  4030. /* do HW to SW pkt type conversion */
  4031. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  4032. hal_2_dp_pkt_type_map[pkt_type]);
  4033. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  4034. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  4035. DP_PEER_EXTD_STATS_INC(txrx_peer,
  4036. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  4037. 1);
  4038. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  4039. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  4040. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  4041. DP_PEER_EXTD_STATS_INC(txrx_peer,
  4042. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  4043. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  4044. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  4045. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  4046. if (ts->first_msdu) {
  4047. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  4048. ts->transmit_cnt > 1);
  4049. if (!retry_threshold)
  4050. return;
  4051. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  4052. qdf_do_div(ts->transmit_cnt,
  4053. retry_threshold),
  4054. ts->transmit_cnt > retry_threshold);
  4055. }
  4056. }
  4057. #else
  4058. static inline void
  4059. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4060. struct dp_txrx_peer *txrx_peer)
  4061. {
  4062. }
  4063. #endif
  4064. /**
  4065. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  4066. * per wbm ring
  4067. *
  4068. * @tx_desc: software descriptor head pointer
  4069. * @ts: Tx completion status
  4070. * @peer: peer handle
  4071. * @ring_id: ring number
  4072. *
  4073. * Return: None
  4074. */
  4075. static inline void
  4076. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  4077. struct hal_tx_completion_status *ts,
  4078. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  4079. {
  4080. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  4081. uint8_t tid = ts->tid;
  4082. uint32_t length;
  4083. struct cdp_tid_tx_stats *tid_stats;
  4084. if (!pdev)
  4085. return;
  4086. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  4087. tid = CDP_MAX_DATA_TIDS - 1;
  4088. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  4089. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  4090. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  4091. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  4092. return;
  4093. }
  4094. length = qdf_nbuf_len(tx_desc->nbuf);
  4095. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4096. if (qdf_unlikely(pdev->delay_stats_flag) ||
  4097. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  4098. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  4099. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  4100. tid_stats->tqm_status_cnt[ts->status]++;
  4101. }
  4102. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  4103. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  4104. ts->transmit_cnt > 1);
  4105. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  4106. 1, ts->transmit_cnt > 2);
  4107. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  4108. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  4109. ts->msdu_part_of_amsdu);
  4110. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  4111. !ts->msdu_part_of_amsdu);
  4112. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  4113. qdf_system_ticks();
  4114. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  4115. return;
  4116. }
  4117. /*
  4118. * tx_failed is ideally supposed to be updated from HTT ppdu
  4119. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  4120. * hw limitation there are no completions for failed cases.
  4121. * Hence updating tx_failed from data path. Please note that
  4122. * if tx_failed is fixed to be from ppdu, then this has to be
  4123. * removed
  4124. */
  4125. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4126. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  4127. ts->transmit_cnt > DP_RETRY_COUNT);
  4128. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  4129. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  4130. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  4131. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  4132. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  4133. length);
  4134. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  4135. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  4136. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  4137. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  4138. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  4139. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  4140. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  4141. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  4142. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  4143. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  4144. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  4145. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4146. tx.dropped.fw_rem_queue_disable, 1);
  4147. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  4148. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4149. tx.dropped.fw_rem_no_match, 1);
  4150. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  4151. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4152. tx.dropped.drop_threshold, 1);
  4153. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  4154. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4155. tx.dropped.drop_link_desc_na, 1);
  4156. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  4157. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4158. tx.dropped.invalid_drop, 1);
  4159. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4160. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4161. tx.dropped.mcast_vdev_drop, 1);
  4162. } else {
  4163. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  4164. }
  4165. }
  4166. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4167. /**
  4168. * dp_tx_flow_pool_lock() - take flow pool lock
  4169. * @soc: core txrx main context
  4170. * @tx_desc: tx desc
  4171. *
  4172. * Return: None
  4173. */
  4174. static inline
  4175. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  4176. struct dp_tx_desc_s *tx_desc)
  4177. {
  4178. struct dp_tx_desc_pool_s *pool;
  4179. uint8_t desc_pool_id;
  4180. desc_pool_id = tx_desc->pool_id;
  4181. pool = &soc->tx_desc[desc_pool_id];
  4182. qdf_spin_lock_bh(&pool->flow_pool_lock);
  4183. }
  4184. /**
  4185. * dp_tx_flow_pool_unlock() - release flow pool lock
  4186. * @soc: core txrx main context
  4187. * @tx_desc: tx desc
  4188. *
  4189. * Return: None
  4190. */
  4191. static inline
  4192. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  4193. struct dp_tx_desc_s *tx_desc)
  4194. {
  4195. struct dp_tx_desc_pool_s *pool;
  4196. uint8_t desc_pool_id;
  4197. desc_pool_id = tx_desc->pool_id;
  4198. pool = &soc->tx_desc[desc_pool_id];
  4199. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  4200. }
  4201. #else
  4202. static inline
  4203. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4204. {
  4205. }
  4206. static inline
  4207. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4208. {
  4209. }
  4210. #endif
  4211. /**
  4212. * dp_tx_notify_completion() - Notify tx completion for this desc
  4213. * @soc: core txrx main context
  4214. * @vdev: datapath vdev handle
  4215. * @tx_desc: tx desc
  4216. * @netbuf: buffer
  4217. * @status: tx status
  4218. *
  4219. * Return: none
  4220. */
  4221. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  4222. struct dp_vdev *vdev,
  4223. struct dp_tx_desc_s *tx_desc,
  4224. qdf_nbuf_t netbuf,
  4225. uint8_t status)
  4226. {
  4227. void *osif_dev;
  4228. ol_txrx_completion_fp tx_compl_cbk = NULL;
  4229. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  4230. qdf_assert(tx_desc);
  4231. if (!vdev ||
  4232. !vdev->osif_vdev) {
  4233. return;
  4234. }
  4235. osif_dev = vdev->osif_vdev;
  4236. tx_compl_cbk = vdev->tx_comp;
  4237. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4238. flag |= BIT(QDF_TX_RX_STATUS_OK);
  4239. if (tx_compl_cbk)
  4240. tx_compl_cbk(netbuf, osif_dev, flag);
  4241. }
  4242. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  4243. * @pdev: pdev handle
  4244. * @tid: tid value
  4245. * @txdesc_ts: timestamp from txdesc
  4246. * @ppdu_id: ppdu id
  4247. *
  4248. * Return: none
  4249. */
  4250. #ifdef FEATURE_PERPKT_INFO
  4251. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4252. struct dp_txrx_peer *txrx_peer,
  4253. uint8_t tid,
  4254. uint64_t txdesc_ts,
  4255. uint32_t ppdu_id)
  4256. {
  4257. uint64_t delta_ms;
  4258. struct cdp_tx_sojourn_stats *sojourn_stats;
  4259. struct dp_peer *primary_link_peer = NULL;
  4260. struct dp_soc *link_peer_soc = NULL;
  4261. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4262. return;
  4263. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4264. tid >= CDP_DATA_TID_MAX))
  4265. return;
  4266. if (qdf_unlikely(!pdev->sojourn_buf))
  4267. return;
  4268. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4269. txrx_peer->peer_id,
  4270. DP_MOD_ID_TX_COMP);
  4271. if (qdf_unlikely(!primary_link_peer))
  4272. return;
  4273. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4274. qdf_nbuf_data(pdev->sojourn_buf);
  4275. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4276. sojourn_stats->cookie = (void *)
  4277. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4278. primary_link_peer);
  4279. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4280. txdesc_ts;
  4281. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4282. delta_ms);
  4283. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4284. sojourn_stats->num_msdus[tid] = 1;
  4285. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4286. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4287. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4288. pdev->sojourn_buf, HTT_INVALID_PEER,
  4289. WDI_NO_VAL, pdev->pdev_id);
  4290. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4291. sojourn_stats->num_msdus[tid] = 0;
  4292. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4293. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4294. }
  4295. #else
  4296. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4297. struct dp_txrx_peer *txrx_peer,
  4298. uint8_t tid,
  4299. uint64_t txdesc_ts,
  4300. uint32_t ppdu_id)
  4301. {
  4302. }
  4303. #endif
  4304. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4305. /**
  4306. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  4307. * @soc: dp_soc handle
  4308. * @desc: Tx Descriptor
  4309. * @ts: HAL Tx completion descriptor contents
  4310. *
  4311. * This function is used to send tx completion to packet capture
  4312. */
  4313. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4314. struct dp_tx_desc_s *desc,
  4315. struct hal_tx_completion_status *ts)
  4316. {
  4317. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4318. desc, ts->peer_id,
  4319. WDI_NO_VAL, desc->pdev->pdev_id);
  4320. }
  4321. #endif
  4322. /**
  4323. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  4324. * @soc: DP Soc handle
  4325. * @tx_desc: software Tx descriptor
  4326. * @ts : Tx completion status from HAL/HTT descriptor
  4327. *
  4328. * Return: none
  4329. */
  4330. void
  4331. dp_tx_comp_process_desc(struct dp_soc *soc,
  4332. struct dp_tx_desc_s *desc,
  4333. struct hal_tx_completion_status *ts,
  4334. struct dp_txrx_peer *txrx_peer)
  4335. {
  4336. uint64_t time_latency = 0;
  4337. uint16_t peer_id = DP_INVALID_PEER_ID;
  4338. /*
  4339. * m_copy/tx_capture modes are not supported for
  4340. * scatter gather packets
  4341. */
  4342. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4343. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4344. qdf_ktime_to_ms(desc->timestamp));
  4345. }
  4346. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4347. if (dp_tx_pkt_tracepoints_enabled())
  4348. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4349. desc->msdu_ext_desc ?
  4350. desc->msdu_ext_desc->tso_desc : NULL,
  4351. qdf_ktime_to_ms(desc->timestamp));
  4352. if (!(desc->msdu_ext_desc)) {
  4353. dp_tx_enh_unmap(soc, desc);
  4354. if (txrx_peer)
  4355. peer_id = txrx_peer->peer_id;
  4356. if (QDF_STATUS_SUCCESS ==
  4357. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4358. return;
  4359. }
  4360. if (QDF_STATUS_SUCCESS ==
  4361. dp_get_completion_indication_for_stack(soc,
  4362. desc->pdev,
  4363. txrx_peer, ts,
  4364. desc->nbuf,
  4365. time_latency)) {
  4366. dp_send_completion_to_stack(soc,
  4367. desc->pdev,
  4368. ts->peer_id,
  4369. ts->ppdu_id,
  4370. desc->nbuf);
  4371. return;
  4372. }
  4373. }
  4374. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4375. dp_tx_comp_free_buf(soc, desc, false);
  4376. }
  4377. #ifdef DISABLE_DP_STATS
  4378. /**
  4379. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4380. * @soc: core txrx main context
  4381. * @tx_desc: tx desc
  4382. * @status: tx status
  4383. *
  4384. * Return: none
  4385. */
  4386. static inline
  4387. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4388. struct dp_vdev *vdev,
  4389. struct dp_tx_desc_s *tx_desc,
  4390. uint8_t status)
  4391. {
  4392. }
  4393. #else
  4394. static inline
  4395. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4396. struct dp_vdev *vdev,
  4397. struct dp_tx_desc_s *tx_desc,
  4398. uint8_t status)
  4399. {
  4400. void *osif_dev;
  4401. ol_txrx_stats_rx_fp stats_cbk;
  4402. uint8_t pkt_type;
  4403. qdf_assert(tx_desc);
  4404. if (!vdev ||
  4405. !vdev->osif_vdev ||
  4406. !vdev->stats_cb)
  4407. return;
  4408. osif_dev = vdev->osif_vdev;
  4409. stats_cbk = vdev->stats_cb;
  4410. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4411. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4412. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4413. &pkt_type);
  4414. }
  4415. #endif
  4416. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4417. QDF_STATUS
  4418. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4419. uint32_t delta_tsf,
  4420. uint32_t *delay_us)
  4421. {
  4422. uint32_t buffer_ts;
  4423. uint32_t delay;
  4424. if (!delay_us)
  4425. return QDF_STATUS_E_INVAL;
  4426. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4427. if (!ts->valid)
  4428. return QDF_STATUS_E_INVAL;
  4429. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4430. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4431. * valid up to 29 bits.
  4432. */
  4433. buffer_ts = ts->buffer_timestamp << 10;
  4434. delay = ts->tsf - buffer_ts - delta_tsf;
  4435. if (qdf_unlikely(delay & 0x80000000)) {
  4436. dp_err_rl("delay = 0x%x (-ve)\n"
  4437. "release_src = %d\n"
  4438. "ppdu_id = 0x%x\n"
  4439. "peer_id = 0x%x\n"
  4440. "tid = 0x%x\n"
  4441. "release_reason = %d\n"
  4442. "tsf = %u (0x%x)\n"
  4443. "buffer_timestamp = %u (0x%x)\n"
  4444. "delta_tsf = %u (0x%x)\n",
  4445. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4446. ts->tid, ts->status, ts->tsf, ts->tsf,
  4447. ts->buffer_timestamp, ts->buffer_timestamp,
  4448. delta_tsf, delta_tsf);
  4449. delay = 0;
  4450. goto end;
  4451. }
  4452. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4453. if (delay > 0x1000000) {
  4454. dp_info_rl("----------------------\n"
  4455. "Tx completion status:\n"
  4456. "----------------------\n"
  4457. "release_src = %d\n"
  4458. "ppdu_id = 0x%x\n"
  4459. "release_reason = %d\n"
  4460. "tsf = %u (0x%x)\n"
  4461. "buffer_timestamp = %u (0x%x)\n"
  4462. "delta_tsf = %u (0x%x)\n",
  4463. ts->release_src, ts->ppdu_id, ts->status,
  4464. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4465. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4466. return QDF_STATUS_E_FAILURE;
  4467. }
  4468. end:
  4469. *delay_us = delay;
  4470. return QDF_STATUS_SUCCESS;
  4471. }
  4472. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4473. uint32_t delta_tsf)
  4474. {
  4475. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4476. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4477. DP_MOD_ID_CDP);
  4478. if (!vdev) {
  4479. dp_err_rl("vdev %d does not exist", vdev_id);
  4480. return;
  4481. }
  4482. vdev->delta_tsf = delta_tsf;
  4483. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4484. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4485. }
  4486. #endif
  4487. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4488. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4489. uint8_t vdev_id, bool enable)
  4490. {
  4491. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4492. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4493. DP_MOD_ID_CDP);
  4494. if (!vdev) {
  4495. dp_err_rl("vdev %d does not exist", vdev_id);
  4496. return QDF_STATUS_E_FAILURE;
  4497. }
  4498. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4499. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4500. return QDF_STATUS_SUCCESS;
  4501. }
  4502. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4503. uint32_t *val)
  4504. {
  4505. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4506. struct dp_vdev *vdev;
  4507. uint32_t delay_accum;
  4508. uint32_t pkts_accum;
  4509. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4510. if (!vdev) {
  4511. dp_err_rl("vdev %d does not exist", vdev_id);
  4512. return QDF_STATUS_E_FAILURE;
  4513. }
  4514. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4515. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4516. return QDF_STATUS_E_FAILURE;
  4517. }
  4518. /* Average uplink delay based on current accumulated values */
  4519. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4520. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4521. *val = delay_accum / pkts_accum;
  4522. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4523. delay_accum, pkts_accum);
  4524. /* Reset accumulated values to 0 */
  4525. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4526. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4527. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4528. return QDF_STATUS_SUCCESS;
  4529. }
  4530. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4531. struct hal_tx_completion_status *ts)
  4532. {
  4533. uint32_t ul_delay;
  4534. if (qdf_unlikely(!vdev)) {
  4535. dp_info_rl("vdev is null or delete in progress");
  4536. return;
  4537. }
  4538. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4539. return;
  4540. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4541. vdev->delta_tsf,
  4542. &ul_delay)))
  4543. return;
  4544. ul_delay /= 1000; /* in unit of ms */
  4545. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4546. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4547. }
  4548. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4549. static inline
  4550. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4551. struct hal_tx_completion_status *ts)
  4552. {
  4553. }
  4554. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4555. /**
  4556. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4557. * @soc: DP soc handle
  4558. * @tx_desc: software descriptor head pointer
  4559. * @ts: Tx completion status
  4560. * @txrx_peer: txrx peer handle
  4561. * @ring_id: ring number
  4562. *
  4563. * Return: none
  4564. */
  4565. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4566. struct dp_tx_desc_s *tx_desc,
  4567. struct hal_tx_completion_status *ts,
  4568. struct dp_txrx_peer *txrx_peer,
  4569. uint8_t ring_id)
  4570. {
  4571. uint32_t length;
  4572. qdf_ether_header_t *eh;
  4573. struct dp_vdev *vdev = NULL;
  4574. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4575. enum qdf_dp_tx_rx_status dp_status;
  4576. if (!nbuf) {
  4577. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4578. goto out;
  4579. }
  4580. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4581. length = qdf_nbuf_len(nbuf);
  4582. dp_status = dp_tx_hw_to_qdf(ts->status);
  4583. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4584. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4585. QDF_TRACE_DEFAULT_PDEV_ID,
  4586. qdf_nbuf_data_addr(nbuf),
  4587. sizeof(qdf_nbuf_data(nbuf)),
  4588. tx_desc->id, ts->status, dp_status));
  4589. dp_tx_comp_debug("-------------------- \n"
  4590. "Tx Completion Stats: \n"
  4591. "-------------------- \n"
  4592. "ack_frame_rssi = %d \n"
  4593. "first_msdu = %d \n"
  4594. "last_msdu = %d \n"
  4595. "msdu_part_of_amsdu = %d \n"
  4596. "rate_stats valid = %d \n"
  4597. "bw = %d \n"
  4598. "pkt_type = %d \n"
  4599. "stbc = %d \n"
  4600. "ldpc = %d \n"
  4601. "sgi = %d \n"
  4602. "mcs = %d \n"
  4603. "ofdma = %d \n"
  4604. "tones_in_ru = %d \n"
  4605. "tsf = %d \n"
  4606. "ppdu_id = %d \n"
  4607. "transmit_cnt = %d \n"
  4608. "tid = %d \n"
  4609. "peer_id = %d\n"
  4610. "tx_status = %d\n",
  4611. ts->ack_frame_rssi, ts->first_msdu,
  4612. ts->last_msdu, ts->msdu_part_of_amsdu,
  4613. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4614. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4615. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4616. ts->transmit_cnt, ts->tid, ts->peer_id,
  4617. ts->status);
  4618. /* Update SoC level stats */
  4619. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4620. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4621. if (!txrx_peer) {
  4622. dp_info_rl("peer is null or deletion in progress");
  4623. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4624. goto out;
  4625. }
  4626. vdev = txrx_peer->vdev;
  4627. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4628. dp_tx_update_uplink_delay(soc, vdev, ts);
  4629. /* check tx complete notification */
  4630. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4631. dp_tx_notify_completion(soc, vdev, tx_desc,
  4632. nbuf, ts->status);
  4633. /* Update per-packet stats for mesh mode */
  4634. if (qdf_unlikely(vdev->mesh_vdev) &&
  4635. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4636. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4637. /* Update peer level stats */
  4638. if (qdf_unlikely(txrx_peer->bss_peer &&
  4639. vdev->opmode == wlan_op_mode_ap)) {
  4640. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4641. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4642. length);
  4643. if (txrx_peer->vdev->tx_encap_type ==
  4644. htt_cmn_pkt_type_ethernet &&
  4645. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4646. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4647. tx.bcast, 1,
  4648. length);
  4649. }
  4650. }
  4651. } else {
  4652. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4653. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4654. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4655. 1, length);
  4656. if (qdf_unlikely(txrx_peer->in_twt)) {
  4657. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4658. tx.tx_success_twt,
  4659. 1, length);
  4660. }
  4661. }
  4662. }
  4663. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4664. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4665. dp_tx_update_peer_jitter_stats(txrx_peer, tx_desc, ts, ring_id);
  4666. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4667. ts, ts->tid);
  4668. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4669. #ifdef QCA_SUPPORT_RDK_STATS
  4670. if (soc->peerstats_enabled)
  4671. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4672. qdf_ktime_to_ms(tx_desc->timestamp),
  4673. ts->ppdu_id);
  4674. #endif
  4675. out:
  4676. return;
  4677. }
  4678. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4679. defined(QCA_ENHANCED_STATS_SUPPORT)
  4680. /*
  4681. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4682. * @txrx_peer: Datapath txrx_peer handle
  4683. * @length: Length of the packet
  4684. * @tx_status: Tx status from TQM/FW
  4685. * @update: enhanced flag value present in dp_pdev
  4686. *
  4687. * Return: none
  4688. */
  4689. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4690. uint32_t length, uint8_t tx_status,
  4691. bool update)
  4692. {
  4693. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4694. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4695. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4696. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4697. }
  4698. }
  4699. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4700. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4701. uint32_t length, uint8_t tx_status,
  4702. bool update)
  4703. {
  4704. if (!txrx_peer->hw_txrx_stats_en) {
  4705. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4706. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4707. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4708. }
  4709. }
  4710. #else
  4711. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4712. uint32_t length, uint8_t tx_status,
  4713. bool update)
  4714. {
  4715. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4716. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4717. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4718. }
  4719. #endif
  4720. /*
  4721. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4722. * @nbuf: skb buffer
  4723. *
  4724. * Return: none
  4725. */
  4726. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4727. static inline
  4728. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4729. {
  4730. qdf_nbuf_t nbuf = NULL;
  4731. if (next)
  4732. nbuf = next->nbuf;
  4733. if (nbuf) {
  4734. /* prefetch skb->next and first few bytes of skb->cb */
  4735. qdf_prefetch(next->shinfo_addr);
  4736. qdf_prefetch(nbuf);
  4737. /* prefetch skb fields present in different cachelines */
  4738. qdf_prefetch(&nbuf->len);
  4739. qdf_prefetch(&nbuf->users);
  4740. }
  4741. }
  4742. #else
  4743. static inline
  4744. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4745. {
  4746. }
  4747. #endif
  4748. /**
  4749. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4750. * @soc: core txrx main context
  4751. * @desc: software descriptor
  4752. *
  4753. * Return: true when packet is reinjected
  4754. */
  4755. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4756. defined(WLAN_MCAST_MLO)
  4757. static inline bool
  4758. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4759. {
  4760. struct dp_vdev *vdev = NULL;
  4761. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4762. if (!soc->arch_ops.dp_tx_mcast_handler)
  4763. return false;
  4764. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4765. DP_MOD_ID_REINJECT);
  4766. if (qdf_unlikely(!vdev)) {
  4767. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4768. desc->id);
  4769. return false;
  4770. }
  4771. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4772. qdf_nbuf_len(desc->nbuf));
  4773. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4774. dp_tx_desc_release(desc, desc->pool_id);
  4775. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4776. return true;
  4777. }
  4778. return false;
  4779. }
  4780. #else
  4781. static inline bool
  4782. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4783. {
  4784. return false;
  4785. }
  4786. #endif
  4787. /**
  4788. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4789. * @soc: core txrx main context
  4790. * @comp_head: software descriptor head pointer
  4791. * @ring_id: ring number
  4792. *
  4793. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4794. * and release the software descriptors after processing is complete
  4795. *
  4796. * Return: none
  4797. */
  4798. static void
  4799. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4800. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4801. {
  4802. struct dp_tx_desc_s *desc;
  4803. struct dp_tx_desc_s *next;
  4804. struct hal_tx_completion_status ts;
  4805. struct dp_txrx_peer *txrx_peer = NULL;
  4806. uint16_t peer_id = DP_INVALID_PEER;
  4807. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4808. desc = comp_head;
  4809. while (desc) {
  4810. next = desc->next;
  4811. dp_tx_prefetch_next_nbuf_data(next);
  4812. if (peer_id != desc->peer_id) {
  4813. if (txrx_peer)
  4814. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4815. DP_MOD_ID_TX_COMP);
  4816. peer_id = desc->peer_id;
  4817. txrx_peer =
  4818. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4819. &txrx_ref_handle,
  4820. DP_MOD_ID_TX_COMP);
  4821. }
  4822. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4823. desc = next;
  4824. continue;
  4825. }
  4826. if (desc->flags & DP_TX_DESC_FLAG_PPEDS) {
  4827. if (qdf_likely(txrx_peer))
  4828. dp_tx_update_peer_basic_stats(txrx_peer,
  4829. desc->length,
  4830. desc->tx_status,
  4831. false);
  4832. qdf_nbuf_free(desc->nbuf);
  4833. dp_ppeds_tx_desc_free(soc, desc);
  4834. desc = next;
  4835. continue;
  4836. }
  4837. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4838. struct dp_pdev *pdev = desc->pdev;
  4839. if (qdf_likely(txrx_peer))
  4840. dp_tx_update_peer_basic_stats(txrx_peer,
  4841. desc->length,
  4842. desc->tx_status,
  4843. false);
  4844. qdf_assert(pdev);
  4845. dp_tx_outstanding_dec(pdev);
  4846. /*
  4847. * Calling a QDF WRAPPER here is creating significant
  4848. * performance impact so avoided the wrapper call here
  4849. */
  4850. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4851. desc->id, DP_TX_COMP_UNMAP);
  4852. dp_tx_nbuf_unmap(soc, desc);
  4853. qdf_nbuf_free_simple(desc->nbuf);
  4854. dp_tx_desc_free(soc, desc, desc->pool_id);
  4855. desc = next;
  4856. continue;
  4857. }
  4858. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4859. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4860. ring_id);
  4861. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4862. dp_tx_desc_release(desc, desc->pool_id);
  4863. desc = next;
  4864. }
  4865. if (txrx_peer)
  4866. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4867. }
  4868. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4869. static inline
  4870. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4871. int max_reap_limit)
  4872. {
  4873. bool limit_hit = false;
  4874. limit_hit =
  4875. (num_reaped >= max_reap_limit) ? true : false;
  4876. if (limit_hit)
  4877. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4878. return limit_hit;
  4879. }
  4880. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4881. {
  4882. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4883. }
  4884. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4885. {
  4886. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4887. return cfg->tx_comp_loop_pkt_limit;
  4888. }
  4889. #else
  4890. static inline
  4891. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4892. int max_reap_limit)
  4893. {
  4894. return false;
  4895. }
  4896. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4897. {
  4898. return false;
  4899. }
  4900. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4901. {
  4902. return 0;
  4903. }
  4904. #endif
  4905. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4906. static inline int
  4907. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4908. int *max_reap_limit)
  4909. {
  4910. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4911. max_reap_limit);
  4912. }
  4913. #else
  4914. static inline int
  4915. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4916. int *max_reap_limit)
  4917. {
  4918. return 0;
  4919. }
  4920. #endif
  4921. #ifdef DP_TX_TRACKING
  4922. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4923. {
  4924. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4925. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4926. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4927. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4928. }
  4929. }
  4930. #endif
  4931. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4932. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4933. uint32_t quota)
  4934. {
  4935. void *tx_comp_hal_desc;
  4936. void *last_prefetched_hw_desc = NULL;
  4937. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4938. hal_soc_handle_t hal_soc;
  4939. uint8_t buffer_src;
  4940. struct dp_tx_desc_s *tx_desc = NULL;
  4941. struct dp_tx_desc_s *head_desc = NULL;
  4942. struct dp_tx_desc_s *tail_desc = NULL;
  4943. uint32_t num_processed = 0;
  4944. uint32_t count;
  4945. uint32_t num_avail_for_reap = 0;
  4946. bool force_break = false;
  4947. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4948. int max_reap_limit, ring_near_full;
  4949. uint32_t num_entries;
  4950. DP_HIST_INIT();
  4951. num_entries = hal_srng_get_num_entries(soc->hal_soc, hal_ring_hdl);
  4952. more_data:
  4953. hal_soc = soc->hal_soc;
  4954. /* Re-initialize local variables to be re-used */
  4955. head_desc = NULL;
  4956. tail_desc = NULL;
  4957. count = 0;
  4958. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4959. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4960. &max_reap_limit);
  4961. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4962. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4963. return 0;
  4964. }
  4965. if (!num_avail_for_reap)
  4966. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc,
  4967. hal_ring_hdl, 0);
  4968. if (num_avail_for_reap >= quota)
  4969. num_avail_for_reap = quota;
  4970. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4971. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  4972. hal_ring_hdl,
  4973. num_avail_for_reap);
  4974. /* Find head descriptor from completion ring */
  4975. while (qdf_likely(num_avail_for_reap--)) {
  4976. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4977. if (qdf_unlikely(!tx_comp_hal_desc))
  4978. break;
  4979. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4980. tx_comp_hal_desc);
  4981. /* If this buffer was not released by TQM or FW, then it is not
  4982. * Tx completion indication, assert */
  4983. if (qdf_unlikely(buffer_src !=
  4984. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4985. (qdf_unlikely(buffer_src !=
  4986. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4987. uint8_t wbm_internal_error;
  4988. dp_err_rl(
  4989. "Tx comp release_src != TQM | FW but from %d",
  4990. buffer_src);
  4991. hal_dump_comp_desc(tx_comp_hal_desc);
  4992. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4993. /* When WBM sees NULL buffer_addr_info in any of
  4994. * ingress rings it sends an error indication,
  4995. * with wbm_internal_error=1, to a specific ring.
  4996. * The WBM2SW ring used to indicate these errors is
  4997. * fixed in HW, and that ring is being used as Tx
  4998. * completion ring. These errors are not related to
  4999. * Tx completions, and should just be ignored
  5000. */
  5001. wbm_internal_error = hal_get_wbm_internal_error(
  5002. hal_soc,
  5003. tx_comp_hal_desc);
  5004. if (wbm_internal_error) {
  5005. dp_err_rl("Tx comp wbm_internal_error!!");
  5006. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  5007. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  5008. buffer_src)
  5009. dp_handle_wbm_internal_error(
  5010. soc,
  5011. tx_comp_hal_desc,
  5012. hal_tx_comp_get_buffer_type(
  5013. tx_comp_hal_desc));
  5014. } else {
  5015. dp_err_rl("Tx comp wbm_internal_error false");
  5016. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  5017. }
  5018. continue;
  5019. }
  5020. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  5021. tx_comp_hal_desc,
  5022. &tx_desc);
  5023. if (!tx_desc) {
  5024. dp_err("unable to retrieve tx_desc!");
  5025. QDF_BUG(0);
  5026. continue;
  5027. }
  5028. tx_desc->buffer_src = buffer_src;
  5029. if (tx_desc->flags & DP_TX_DESC_FLAG_PPEDS)
  5030. goto add_to_pool2;
  5031. /*
  5032. * If the release source is FW, process the HTT status
  5033. */
  5034. if (qdf_unlikely(buffer_src ==
  5035. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  5036. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  5037. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  5038. htt_tx_status);
  5039. /* Collect hw completion contents */
  5040. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5041. &tx_desc->comp, 1);
  5042. soc->arch_ops.dp_tx_process_htt_completion(
  5043. soc,
  5044. tx_desc,
  5045. htt_tx_status,
  5046. ring_id);
  5047. } else {
  5048. tx_desc->tx_status =
  5049. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  5050. tx_desc->buffer_src = buffer_src;
  5051. /*
  5052. * If the fast completion mode is enabled extended
  5053. * metadata from descriptor is not copied
  5054. */
  5055. if (qdf_likely(tx_desc->flags &
  5056. DP_TX_DESC_FLAG_SIMPLE))
  5057. goto add_to_pool;
  5058. /*
  5059. * If the descriptor is already freed in vdev_detach,
  5060. * continue to next descriptor
  5061. */
  5062. if (qdf_unlikely
  5063. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  5064. !tx_desc->flags)) {
  5065. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  5066. tx_desc->id);
  5067. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  5068. dp_tx_desc_check_corruption(tx_desc);
  5069. continue;
  5070. }
  5071. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  5072. dp_tx_comp_info_rl("pdev in down state %d",
  5073. tx_desc->id);
  5074. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  5075. dp_tx_comp_free_buf(soc, tx_desc, false);
  5076. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  5077. goto next_desc;
  5078. }
  5079. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  5080. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  5081. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  5082. tx_desc->flags, tx_desc->id);
  5083. qdf_assert_always(0);
  5084. }
  5085. /* Collect hw completion contents */
  5086. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5087. &tx_desc->comp, 1);
  5088. add_to_pool:
  5089. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  5090. add_to_pool2:
  5091. /* First ring descriptor on the cycle */
  5092. if (!head_desc) {
  5093. head_desc = tx_desc;
  5094. tail_desc = tx_desc;
  5095. }
  5096. tail_desc->next = tx_desc;
  5097. tx_desc->next = NULL;
  5098. tail_desc = tx_desc;
  5099. }
  5100. next_desc:
  5101. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  5102. /*
  5103. * Processed packet count is more than given quota
  5104. * stop to processing
  5105. */
  5106. count++;
  5107. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  5108. num_avail_for_reap,
  5109. hal_ring_hdl,
  5110. &last_prefetched_hw_desc,
  5111. &last_prefetched_sw_desc);
  5112. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  5113. break;
  5114. }
  5115. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  5116. /* Process the reaped descriptors */
  5117. if (head_desc)
  5118. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  5119. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  5120. /*
  5121. * If we are processing in near-full condition, there are 3 scenario
  5122. * 1) Ring entries has reached critical state
  5123. * 2) Ring entries are still near high threshold
  5124. * 3) Ring entries are below the safe level
  5125. *
  5126. * One more loop will move the state to normal processing and yield
  5127. */
  5128. if (ring_near_full)
  5129. goto more_data;
  5130. if (dp_tx_comp_enable_eol_data_check(soc)) {
  5131. if (num_processed >= quota)
  5132. force_break = true;
  5133. if (!force_break &&
  5134. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  5135. hal_ring_hdl)) {
  5136. DP_STATS_INC(soc, tx.hp_oos2, 1);
  5137. if (!hif_exec_should_yield(soc->hif_handle,
  5138. int_ctx->dp_intr_id))
  5139. goto more_data;
  5140. num_avail_for_reap =
  5141. hal_srng_dst_num_valid_locked(soc->hal_soc,
  5142. hal_ring_hdl,
  5143. true);
  5144. if (qdf_unlikely(num_entries &&
  5145. (num_avail_for_reap >=
  5146. num_entries >> 1))) {
  5147. DP_STATS_INC(soc, tx.near_full, 1);
  5148. goto more_data;
  5149. }
  5150. }
  5151. }
  5152. DP_TX_HIST_STATS_PER_PDEV();
  5153. return num_processed;
  5154. }
  5155. #ifdef FEATURE_WLAN_TDLS
  5156. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  5157. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  5158. {
  5159. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  5160. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  5161. DP_MOD_ID_TDLS);
  5162. if (!vdev) {
  5163. dp_err("vdev handle for id %d is NULL", vdev_id);
  5164. return NULL;
  5165. }
  5166. if (tx_spec & OL_TX_SPEC_NO_FREE)
  5167. vdev->is_tdls_frame = true;
  5168. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  5169. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  5170. }
  5171. #endif
  5172. /**
  5173. * dp_tx_vdev_attach() - attach vdev to dp tx
  5174. * @vdev: virtual device instance
  5175. *
  5176. * Return: QDF_STATUS_SUCCESS: success
  5177. * QDF_STATUS_E_RESOURCES: Error return
  5178. */
  5179. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  5180. {
  5181. int pdev_id;
  5182. /*
  5183. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  5184. */
  5185. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  5186. DP_TCL_METADATA_TYPE_VDEV_BASED);
  5187. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  5188. vdev->vdev_id);
  5189. pdev_id =
  5190. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  5191. vdev->pdev->pdev_id);
  5192. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  5193. /*
  5194. * Set HTT Extension Valid bit to 0 by default
  5195. */
  5196. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  5197. dp_tx_vdev_update_search_flags(vdev);
  5198. return QDF_STATUS_SUCCESS;
  5199. }
  5200. #ifndef FEATURE_WDS
  5201. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  5202. {
  5203. return false;
  5204. }
  5205. #endif
  5206. /**
  5207. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  5208. * @vdev: virtual device instance
  5209. *
  5210. * Return: void
  5211. *
  5212. */
  5213. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  5214. {
  5215. struct dp_soc *soc = vdev->pdev->soc;
  5216. /*
  5217. * Enable both AddrY (SA based search) and AddrX (Da based search)
  5218. * for TDLS link
  5219. *
  5220. * Enable AddrY (SA based search) only for non-WDS STA and
  5221. * ProxySTA VAP (in HKv1) modes.
  5222. *
  5223. * In all other VAP modes, only DA based search should be
  5224. * enabled
  5225. */
  5226. if (vdev->opmode == wlan_op_mode_sta &&
  5227. vdev->tdls_link_connected)
  5228. vdev->hal_desc_addr_search_flags =
  5229. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  5230. else if ((vdev->opmode == wlan_op_mode_sta) &&
  5231. !dp_tx_da_search_override(vdev))
  5232. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  5233. else
  5234. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  5235. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  5236. vdev->search_type = soc->sta_mode_search_policy;
  5237. else
  5238. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  5239. }
  5240. static inline bool
  5241. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  5242. struct dp_vdev *vdev,
  5243. struct dp_tx_desc_s *tx_desc)
  5244. {
  5245. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  5246. return false;
  5247. /*
  5248. * if vdev is given, then only check whether desc
  5249. * vdev match. if vdev is NULL, then check whether
  5250. * desc pdev match.
  5251. */
  5252. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  5253. (tx_desc->pdev == pdev);
  5254. }
  5255. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5256. /**
  5257. * dp_tx_desc_flush() - release resources associated
  5258. * to TX Desc
  5259. *
  5260. * @dp_pdev: Handle to DP pdev structure
  5261. * @vdev: virtual device instance
  5262. * NULL: no specific Vdev is required and check all allcated TX desc
  5263. * on this pdev.
  5264. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  5265. *
  5266. * @force_free:
  5267. * true: flush the TX desc.
  5268. * false: only reset the Vdev in each allocated TX desc
  5269. * that associated to current Vdev.
  5270. *
  5271. * This function will go through the TX desc pool to flush
  5272. * the outstanding TX data or reset Vdev to NULL in associated TX
  5273. * Desc.
  5274. */
  5275. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5276. bool force_free)
  5277. {
  5278. uint8_t i;
  5279. uint32_t j;
  5280. uint32_t num_desc, page_id, offset;
  5281. uint16_t num_desc_per_page;
  5282. struct dp_soc *soc = pdev->soc;
  5283. struct dp_tx_desc_s *tx_desc = NULL;
  5284. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5285. if (!vdev && !force_free) {
  5286. dp_err("Reset TX desc vdev, Vdev param is required!");
  5287. return;
  5288. }
  5289. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  5290. tx_desc_pool = &soc->tx_desc[i];
  5291. if (!(tx_desc_pool->pool_size) ||
  5292. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  5293. !(tx_desc_pool->desc_pages.cacheable_pages))
  5294. continue;
  5295. /*
  5296. * Add flow pool lock protection in case pool is freed
  5297. * due to all tx_desc is recycled when handle TX completion.
  5298. * this is not necessary when do force flush as:
  5299. * a. double lock will happen if dp_tx_desc_release is
  5300. * also trying to acquire it.
  5301. * b. dp interrupt has been disabled before do force TX desc
  5302. * flush in dp_pdev_deinit().
  5303. */
  5304. if (!force_free)
  5305. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5306. num_desc = tx_desc_pool->pool_size;
  5307. num_desc_per_page =
  5308. tx_desc_pool->desc_pages.num_element_per_page;
  5309. for (j = 0; j < num_desc; j++) {
  5310. page_id = j / num_desc_per_page;
  5311. offset = j % num_desc_per_page;
  5312. if (qdf_unlikely(!(tx_desc_pool->
  5313. desc_pages.cacheable_pages)))
  5314. break;
  5315. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5316. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5317. /*
  5318. * Free TX desc if force free is
  5319. * required, otherwise only reset vdev
  5320. * in this TX desc.
  5321. */
  5322. if (force_free) {
  5323. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5324. dp_tx_comp_free_buf(soc, tx_desc,
  5325. false);
  5326. dp_tx_desc_release(tx_desc, i);
  5327. } else {
  5328. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5329. }
  5330. }
  5331. }
  5332. if (!force_free)
  5333. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5334. }
  5335. }
  5336. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5337. /**
  5338. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5339. *
  5340. * @soc: Handle to DP soc structure
  5341. * @tx_desc: pointer of one TX desc
  5342. * @desc_pool_id: TX Desc pool id
  5343. */
  5344. static inline void
  5345. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5346. uint8_t desc_pool_id)
  5347. {
  5348. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5349. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5350. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5351. }
  5352. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5353. bool force_free)
  5354. {
  5355. uint8_t i, num_pool;
  5356. uint32_t j;
  5357. uint32_t num_desc, page_id, offset;
  5358. uint16_t num_desc_per_page;
  5359. struct dp_soc *soc = pdev->soc;
  5360. struct dp_tx_desc_s *tx_desc = NULL;
  5361. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5362. if (!vdev && !force_free) {
  5363. dp_err("Reset TX desc vdev, Vdev param is required!");
  5364. return;
  5365. }
  5366. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5367. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5368. for (i = 0; i < num_pool; i++) {
  5369. tx_desc_pool = &soc->tx_desc[i];
  5370. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5371. continue;
  5372. num_desc_per_page =
  5373. tx_desc_pool->desc_pages.num_element_per_page;
  5374. for (j = 0; j < num_desc; j++) {
  5375. page_id = j / num_desc_per_page;
  5376. offset = j % num_desc_per_page;
  5377. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5378. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5379. if (force_free) {
  5380. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5381. dp_tx_comp_free_buf(soc, tx_desc,
  5382. false);
  5383. dp_tx_desc_release(tx_desc, i);
  5384. } else {
  5385. dp_tx_desc_reset_vdev(soc, tx_desc,
  5386. i);
  5387. }
  5388. }
  5389. }
  5390. }
  5391. }
  5392. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5393. /**
  5394. * dp_tx_vdev_detach() - detach vdev from dp tx
  5395. * @vdev: virtual device instance
  5396. *
  5397. * Return: QDF_STATUS_SUCCESS: success
  5398. * QDF_STATUS_E_RESOURCES: Error return
  5399. */
  5400. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5401. {
  5402. struct dp_pdev *pdev = vdev->pdev;
  5403. /* Reset TX desc associated to this Vdev as NULL */
  5404. dp_tx_desc_flush(pdev, vdev, false);
  5405. return QDF_STATUS_SUCCESS;
  5406. }
  5407. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5408. /* Pools will be allocated dynamically */
  5409. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5410. int num_desc)
  5411. {
  5412. uint8_t i;
  5413. for (i = 0; i < num_pool; i++) {
  5414. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5415. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5416. }
  5417. return QDF_STATUS_SUCCESS;
  5418. }
  5419. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5420. uint32_t num_desc)
  5421. {
  5422. return QDF_STATUS_SUCCESS;
  5423. }
  5424. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5425. {
  5426. }
  5427. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5428. {
  5429. uint8_t i;
  5430. for (i = 0; i < num_pool; i++)
  5431. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5432. }
  5433. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5434. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5435. uint32_t num_desc)
  5436. {
  5437. uint8_t i, count;
  5438. /* Allocate software Tx descriptor pools */
  5439. for (i = 0; i < num_pool; i++) {
  5440. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5441. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5442. FL("Tx Desc Pool alloc %d failed %pK"),
  5443. i, soc);
  5444. goto fail;
  5445. }
  5446. }
  5447. return QDF_STATUS_SUCCESS;
  5448. fail:
  5449. for (count = 0; count < i; count++)
  5450. dp_tx_desc_pool_free(soc, count);
  5451. return QDF_STATUS_E_NOMEM;
  5452. }
  5453. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5454. uint32_t num_desc)
  5455. {
  5456. uint8_t i;
  5457. for (i = 0; i < num_pool; i++) {
  5458. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5459. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5460. FL("Tx Desc Pool init %d failed %pK"),
  5461. i, soc);
  5462. return QDF_STATUS_E_NOMEM;
  5463. }
  5464. }
  5465. return QDF_STATUS_SUCCESS;
  5466. }
  5467. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5468. {
  5469. uint8_t i;
  5470. for (i = 0; i < num_pool; i++)
  5471. dp_tx_desc_pool_deinit(soc, i);
  5472. }
  5473. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5474. {
  5475. uint8_t i;
  5476. for (i = 0; i < num_pool; i++)
  5477. dp_tx_desc_pool_free(soc, i);
  5478. }
  5479. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5480. /**
  5481. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5482. * @soc: core txrx main context
  5483. * @num_pool: number of pools
  5484. *
  5485. */
  5486. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5487. {
  5488. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5489. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5490. }
  5491. /**
  5492. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5493. * @soc: core txrx main context
  5494. * @num_pool: number of pools
  5495. *
  5496. */
  5497. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5498. {
  5499. dp_tx_tso_desc_pool_free(soc, num_pool);
  5500. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5501. }
  5502. /**
  5503. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5504. * @soc: core txrx main context
  5505. *
  5506. * This function frees all tx related descriptors as below
  5507. * 1. Regular TX descriptors (static pools)
  5508. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5509. * 3. TSO descriptors
  5510. *
  5511. */
  5512. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5513. {
  5514. uint8_t num_pool;
  5515. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5516. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5517. dp_tx_ext_desc_pool_free(soc, num_pool);
  5518. dp_tx_delete_static_pools(soc, num_pool);
  5519. }
  5520. /**
  5521. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5522. * @soc: core txrx main context
  5523. *
  5524. * This function de-initializes all tx related descriptors as below
  5525. * 1. Regular TX descriptors (static pools)
  5526. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5527. * 3. TSO descriptors
  5528. *
  5529. */
  5530. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5531. {
  5532. uint8_t num_pool;
  5533. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5534. dp_tx_flow_control_deinit(soc);
  5535. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5536. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5537. dp_tx_deinit_static_pools(soc, num_pool);
  5538. }
  5539. /**
  5540. * dp_tso_attach() - TSO attach handler
  5541. * @txrx_soc: Opaque Dp handle
  5542. *
  5543. * Reserve TSO descriptor buffers
  5544. *
  5545. * Return: QDF_STATUS_E_FAILURE on failure or
  5546. * QDF_STATUS_SUCCESS on success
  5547. */
  5548. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5549. uint8_t num_pool,
  5550. uint32_t num_desc)
  5551. {
  5552. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5553. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5554. return QDF_STATUS_E_FAILURE;
  5555. }
  5556. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5557. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5558. num_pool, soc);
  5559. return QDF_STATUS_E_FAILURE;
  5560. }
  5561. return QDF_STATUS_SUCCESS;
  5562. }
  5563. /**
  5564. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5565. * @soc: DP soc handle
  5566. * @num_pool: Number of pools
  5567. * @num_desc: Number of descriptors
  5568. *
  5569. * Initialize TSO descriptor pools
  5570. *
  5571. * Return: QDF_STATUS_E_FAILURE on failure or
  5572. * QDF_STATUS_SUCCESS on success
  5573. */
  5574. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5575. uint8_t num_pool,
  5576. uint32_t num_desc)
  5577. {
  5578. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5579. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5580. return QDF_STATUS_E_FAILURE;
  5581. }
  5582. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5583. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5584. num_pool, soc);
  5585. return QDF_STATUS_E_FAILURE;
  5586. }
  5587. return QDF_STATUS_SUCCESS;
  5588. }
  5589. /**
  5590. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5591. * @soc: core txrx main context
  5592. *
  5593. * This function allocates memory for following descriptor pools
  5594. * 1. regular sw tx descriptor pools (static pools)
  5595. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5596. * 3. TSO descriptor pools
  5597. *
  5598. * Return: QDF_STATUS_SUCCESS: success
  5599. * QDF_STATUS_E_RESOURCES: Error return
  5600. */
  5601. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5602. {
  5603. uint8_t num_pool;
  5604. uint32_t num_desc;
  5605. uint32_t num_ext_desc;
  5606. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5607. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5608. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5609. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5610. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5611. __func__, num_pool, num_desc);
  5612. if ((num_pool > MAX_TXDESC_POOLS) ||
  5613. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5614. goto fail1;
  5615. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5616. goto fail1;
  5617. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5618. goto fail2;
  5619. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5620. return QDF_STATUS_SUCCESS;
  5621. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5622. goto fail3;
  5623. return QDF_STATUS_SUCCESS;
  5624. fail3:
  5625. dp_tx_ext_desc_pool_free(soc, num_pool);
  5626. fail2:
  5627. dp_tx_delete_static_pools(soc, num_pool);
  5628. fail1:
  5629. return QDF_STATUS_E_RESOURCES;
  5630. }
  5631. /**
  5632. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5633. * @soc: core txrx main context
  5634. *
  5635. * This function initializes the following TX descriptor pools
  5636. * 1. regular sw tx descriptor pools (static pools)
  5637. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5638. * 3. TSO descriptor pools
  5639. *
  5640. * Return: QDF_STATUS_SUCCESS: success
  5641. * QDF_STATUS_E_RESOURCES: Error return
  5642. */
  5643. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5644. {
  5645. uint8_t num_pool;
  5646. uint32_t num_desc;
  5647. uint32_t num_ext_desc;
  5648. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5649. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5650. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5651. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5652. goto fail1;
  5653. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5654. goto fail2;
  5655. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5656. return QDF_STATUS_SUCCESS;
  5657. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5658. goto fail3;
  5659. dp_tx_flow_control_init(soc);
  5660. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5661. return QDF_STATUS_SUCCESS;
  5662. fail3:
  5663. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5664. fail2:
  5665. dp_tx_deinit_static_pools(soc, num_pool);
  5666. fail1:
  5667. return QDF_STATUS_E_RESOURCES;
  5668. }
  5669. /**
  5670. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5671. * @txrx_soc: dp soc handle
  5672. *
  5673. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5674. * QDF_STATUS_E_FAILURE
  5675. */
  5676. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5677. {
  5678. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5679. uint8_t num_pool;
  5680. uint32_t num_desc;
  5681. uint32_t num_ext_desc;
  5682. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5683. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5684. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5685. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5686. return QDF_STATUS_E_FAILURE;
  5687. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5688. return QDF_STATUS_E_FAILURE;
  5689. return QDF_STATUS_SUCCESS;
  5690. }
  5691. /**
  5692. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5693. * @txrx_soc: dp soc handle
  5694. *
  5695. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5696. */
  5697. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5698. {
  5699. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5700. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5701. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5702. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5703. return QDF_STATUS_SUCCESS;
  5704. }
  5705. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5706. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5707. enum qdf_pkt_timestamp_index index, uint64_t time,
  5708. qdf_nbuf_t nbuf)
  5709. {
  5710. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5711. uint64_t tsf_time;
  5712. if (vdev->get_tsf_time) {
  5713. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5714. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5715. }
  5716. }
  5717. }
  5718. void dp_pkt_get_timestamp(uint64_t *time)
  5719. {
  5720. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5721. *time = qdf_get_log_timestamp();
  5722. }
  5723. #endif