kona.c 235 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <sound/core.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/info.h>
  22. #include <soc/snd_event.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <soc/swr-common.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include "asoc/msm-cdc-pinctrl.h"
  30. #include "asoc/wcd-mbhc-v2.h"
  31. #include "codecs/wcd938x/wcd938x-mbhc.h"
  32. #include "codecs/wsa881x.h"
  33. #include "codecs/wcd938x/wcd938x.h"
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include <dt-bindings/sound/audio-codec-port-types.h>
  36. #include "codecs/bolero/wsa-macro.h"
  37. #include "kona-port-config.h"
  38. #define DRV_NAME "kona-asoc-snd"
  39. #define __CHIPSET__ "KONA "
  40. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define IS_FRACTIONAL(x) \
  55. ((x == SAMPLING_RATE_11P025KHZ) || (x == SAMPLING_RATE_22P05KHZ) || \
  56. (x == SAMPLING_RATE_44P1KHZ) || (x == SAMPLING_RATE_88P2KHZ) || \
  57. (x == SAMPLING_RATE_176P4KHZ) || (x == SAMPLING_RATE_352P8KHZ))
  58. #define IS_MSM_INTERFACE_MI2S(x) \
  59. ((x == PRIM_MI2S) || (x == SEC_MI2S) || (x == TERT_MI2S))
  60. #define WCD9XXX_MBHC_DEF_RLOADS 5
  61. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  62. #define CODEC_EXT_CLK_RATE 9600000
  63. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  64. #define DEV_NAME_STR_LEN 32
  65. #define WCD_MBHC_HS_V_MAX 1600
  66. #define TDM_CHANNEL_MAX 8
  67. #define DEV_NAME_STR_LEN 32
  68. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  69. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  70. #define WSA8810_NAME_1 "wsa881x.20170211"
  71. #define WSA8810_NAME_2 "wsa881x.20170212"
  72. #define WCN_CDC_SLIM_RX_CH_MAX 2
  73. #define WCN_CDC_SLIM_TX_CH_MAX 2
  74. #define WCN_CDC_SLIM_TX_CH_MAX_LITO 3
  75. enum {
  76. RX_PATH = 0,
  77. TX_PATH,
  78. MAX_PATH,
  79. };
  80. enum {
  81. TDM_0 = 0,
  82. TDM_1,
  83. TDM_2,
  84. TDM_3,
  85. TDM_4,
  86. TDM_5,
  87. TDM_6,
  88. TDM_7,
  89. TDM_PORT_MAX,
  90. };
  91. #define TDM_MAX_SLOTS 8
  92. #define TDM_SLOT_WIDTH_BITS 32
  93. enum {
  94. TDM_PRI = 0,
  95. TDM_SEC,
  96. TDM_TERT,
  97. TDM_QUAT,
  98. TDM_QUIN,
  99. TDM_SEN,
  100. TDM_INTERFACE_MAX,
  101. };
  102. enum {
  103. PRIM_AUX_PCM = 0,
  104. SEC_AUX_PCM,
  105. TERT_AUX_PCM,
  106. QUAT_AUX_PCM,
  107. QUIN_AUX_PCM,
  108. SEN_AUX_PCM,
  109. AUX_PCM_MAX,
  110. };
  111. enum {
  112. PRIM_MI2S = 0,
  113. SEC_MI2S,
  114. TERT_MI2S,
  115. QUAT_MI2S,
  116. QUIN_MI2S,
  117. SEN_MI2S,
  118. MI2S_MAX,
  119. };
  120. enum {
  121. WSA_CDC_DMA_RX_0 = 0,
  122. WSA_CDC_DMA_RX_1,
  123. RX_CDC_DMA_RX_0,
  124. RX_CDC_DMA_RX_1,
  125. RX_CDC_DMA_RX_2,
  126. RX_CDC_DMA_RX_3,
  127. RX_CDC_DMA_RX_5,
  128. CDC_DMA_RX_MAX,
  129. };
  130. enum {
  131. WSA_CDC_DMA_TX_0 = 0,
  132. WSA_CDC_DMA_TX_1,
  133. WSA_CDC_DMA_TX_2,
  134. TX_CDC_DMA_TX_0,
  135. TX_CDC_DMA_TX_3,
  136. TX_CDC_DMA_TX_4,
  137. VA_CDC_DMA_TX_0,
  138. VA_CDC_DMA_TX_1,
  139. VA_CDC_DMA_TX_2,
  140. CDC_DMA_TX_MAX,
  141. };
  142. enum {
  143. SLIM_RX_7 = 0,
  144. SLIM_RX_MAX,
  145. };
  146. enum {
  147. SLIM_TX_7 = 0,
  148. SLIM_TX_8,
  149. SLIM_TX_MAX,
  150. };
  151. enum {
  152. AFE_LOOPBACK_TX_IDX = 0,
  153. AFE_LOOPBACK_TX_IDX_MAX,
  154. };
  155. struct msm_asoc_mach_data {
  156. struct snd_info_entry *codec_root;
  157. int usbc_en2_gpio; /* used by gpio driver API */
  158. int lito_v2_enabled;
  159. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  160. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  161. struct device_node *dmic45_gpio_p; /* used by pinctrl API */
  162. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  163. atomic_t mi2s_gpio_ref_count[MI2S_MAX]; /* used by pinctrl API */
  164. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  165. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  166. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  167. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  168. bool is_afe_config_done;
  169. struct device_node *fsa_handle;
  170. struct clk *lpass_audio_hw_vote;
  171. int core_audio_vote_count;
  172. };
  173. struct tdm_port {
  174. u32 mode;
  175. u32 channel;
  176. };
  177. struct tdm_dev_config {
  178. unsigned int tdm_slot_offset[TDM_MAX_SLOTS];
  179. };
  180. enum {
  181. EXT_DISP_RX_IDX_DP = 0,
  182. EXT_DISP_RX_IDX_DP1,
  183. EXT_DISP_RX_IDX_MAX,
  184. };
  185. struct msm_wsa881x_dev_info {
  186. struct device_node *of_node;
  187. u32 index;
  188. };
  189. struct aux_codec_dev_info {
  190. struct device_node *of_node;
  191. u32 index;
  192. };
  193. struct dev_config {
  194. u32 sample_rate;
  195. u32 bit_format;
  196. u32 channels;
  197. };
  198. /* Default configuration of slimbus channels */
  199. static struct dev_config slim_rx_cfg[] = {
  200. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  201. };
  202. static struct dev_config slim_tx_cfg[] = {
  203. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  204. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  205. };
  206. /* Default configuration of external display BE */
  207. static struct dev_config ext_disp_rx_cfg[] = {
  208. [EXT_DISP_RX_IDX_DP] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  209. [EXT_DISP_RX_IDX_DP1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  210. };
  211. static struct dev_config usb_rx_cfg = {
  212. .sample_rate = SAMPLING_RATE_48KHZ,
  213. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  214. .channels = 2,
  215. };
  216. static struct dev_config usb_tx_cfg = {
  217. .sample_rate = SAMPLING_RATE_48KHZ,
  218. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  219. .channels = 1,
  220. };
  221. static struct dev_config proxy_rx_cfg = {
  222. .sample_rate = SAMPLING_RATE_48KHZ,
  223. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  224. .channels = 2,
  225. };
  226. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  227. {
  228. AFE_API_VERSION_I2S_CONFIG,
  229. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  230. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  231. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  232. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  233. 0,
  234. },
  235. {
  236. AFE_API_VERSION_I2S_CONFIG,
  237. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  238. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  239. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  240. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  241. 0,
  242. },
  243. {
  244. AFE_API_VERSION_I2S_CONFIG,
  245. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  246. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  247. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  248. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  249. 0,
  250. },
  251. {
  252. AFE_API_VERSION_I2S_CONFIG,
  253. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  254. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  255. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  256. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  257. 0,
  258. },
  259. {
  260. AFE_API_VERSION_I2S_CONFIG,
  261. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  262. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  263. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  264. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  265. 0,
  266. },
  267. {
  268. AFE_API_VERSION_I2S_CONFIG,
  269. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  270. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  271. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  272. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  273. 0,
  274. },
  275. };
  276. struct mi2s_conf {
  277. struct mutex lock;
  278. u32 ref_cnt;
  279. u32 msm_is_mi2s_master;
  280. };
  281. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  282. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  283. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  284. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  285. };
  286. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  287. /* Default configuration of TDM channels */
  288. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  289. { /* PRI TDM */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  298. },
  299. { /* SEC TDM */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  308. },
  309. { /* TERT TDM */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  315. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  316. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  317. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  318. },
  319. { /* QUAT TDM */
  320. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  321. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  322. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  323. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  324. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  325. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  326. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  327. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  328. },
  329. { /* QUIN TDM */
  330. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  331. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  332. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  333. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  334. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  335. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  336. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  337. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  338. },
  339. { /* SEN TDM */
  340. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  341. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  342. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  343. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  344. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  345. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  346. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  347. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  348. },
  349. };
  350. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  351. { /* PRI TDM */
  352. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  353. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  354. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  355. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  356. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  357. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  358. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  359. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  360. },
  361. { /* SEC TDM */
  362. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  363. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  364. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  365. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  366. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  367. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  368. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  369. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  370. },
  371. { /* TERT TDM */
  372. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  373. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  374. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  375. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  376. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  377. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  378. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  379. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  380. },
  381. { /* QUAT TDM */
  382. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  383. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  384. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  385. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  386. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  387. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  388. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  389. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  390. },
  391. { /* QUIN TDM */
  392. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  393. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  394. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  395. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  396. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  397. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  398. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  399. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  400. },
  401. { /* SEN TDM */
  402. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  403. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  404. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  405. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  406. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  407. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  408. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  409. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  410. },
  411. };
  412. /* Default configuration of AUX PCM channels */
  413. static struct dev_config aux_pcm_rx_cfg[] = {
  414. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  415. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  416. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  417. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  418. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  419. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  420. };
  421. static struct dev_config aux_pcm_tx_cfg[] = {
  422. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  423. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  424. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  425. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  426. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  427. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  428. };
  429. /* Default configuration of MI2S channels */
  430. static struct dev_config mi2s_rx_cfg[] = {
  431. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  432. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  433. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  434. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  435. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  436. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  437. };
  438. static struct dev_config mi2s_tx_cfg[] = {
  439. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  440. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  441. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  442. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  443. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  444. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  445. };
  446. static struct tdm_dev_config pri_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  447. { /* PRI TDM */
  448. { {0, 4, 0xFFFF} }, /* RX_0 */
  449. { {8, 12, 0xFFFF} }, /* RX_1 */
  450. { {16, 20, 0xFFFF} }, /* RX_2 */
  451. { {24, 28, 0xFFFF} }, /* RX_3 */
  452. { {0xFFFF} }, /* RX_4 */
  453. { {0xFFFF} }, /* RX_5 */
  454. { {0xFFFF} }, /* RX_6 */
  455. { {0xFFFF} }, /* RX_7 */
  456. },
  457. {
  458. { {0, 4, 8, 12, 0xFFFF} }, /* TX_0 */
  459. { {8, 12, 0xFFFF} }, /* TX_1 */
  460. { {16, 20, 0xFFFF} }, /* TX_2 */
  461. { {24, 28, 0xFFFF} }, /* TX_3 */
  462. { {0xFFFF} }, /* TX_4 */
  463. { {0xFFFF} }, /* TX_5 */
  464. { {0xFFFF} }, /* TX_6 */
  465. { {0xFFFF} }, /* TX_7 */
  466. },
  467. };
  468. static struct tdm_dev_config sec_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  469. { /* SEC TDM */
  470. { {0, 4, 0xFFFF} }, /* RX_0 */
  471. { {8, 12, 0xFFFF} }, /* RX_1 */
  472. { {16, 20, 0xFFFF} }, /* RX_2 */
  473. { {24, 28, 0xFFFF} }, /* RX_3 */
  474. { {0xFFFF} }, /* RX_4 */
  475. { {0xFFFF} }, /* RX_5 */
  476. { {0xFFFF} }, /* RX_6 */
  477. { {0xFFFF} }, /* RX_7 */
  478. },
  479. {
  480. { {0, 4, 0xFFFF} }, /* TX_0 */
  481. { {8, 12, 0xFFFF} }, /* TX_1 */
  482. { {16, 20, 0xFFFF} }, /* TX_2 */
  483. { {24, 28, 0xFFFF} }, /* TX_3 */
  484. { {0xFFFF} }, /* TX_4 */
  485. { {0xFFFF} }, /* TX_5 */
  486. { {0xFFFF} }, /* TX_6 */
  487. { {0xFFFF} }, /* TX_7 */
  488. },
  489. };
  490. static struct tdm_dev_config tert_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  491. { /* TERT TDM */
  492. { {0, 4, 0xFFFF} }, /* RX_0 */
  493. { {8, 12, 0xFFFF} }, /* RX_1 */
  494. { {16, 20, 0xFFFF} }, /* RX_2 */
  495. { {24, 28, 0xFFFF} }, /* RX_3 */
  496. { {0xFFFF} }, /* RX_4 */
  497. { {0xFFFF} }, /* RX_5 */
  498. { {0xFFFF} }, /* RX_6 */
  499. { {0xFFFF} }, /* RX_7 */
  500. },
  501. {
  502. { {0, 4, 0xFFFF} }, /* TX_0 */
  503. { {8, 12, 0xFFFF} }, /* TX_1 */
  504. { {16, 20, 0xFFFF} }, /* TX_2 */
  505. { {24, 28, 0xFFFF} }, /* TX_3 */
  506. { {0xFFFF} }, /* TX_4 */
  507. { {0xFFFF} }, /* TX_5 */
  508. { {0xFFFF} }, /* TX_6 */
  509. { {0xFFFF} }, /* TX_7 */
  510. },
  511. };
  512. static struct tdm_dev_config quat_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  513. { /* QUAT TDM */
  514. { {0, 4, 0xFFFF} }, /* RX_0 */
  515. { {8, 12, 0xFFFF} }, /* RX_1 */
  516. { {16, 20, 0xFFFF} }, /* RX_2 */
  517. { {24, 28, 0xFFFF} }, /* RX_3 */
  518. { {0xFFFF} }, /* RX_4 */
  519. { {0xFFFF} }, /* RX_5 */
  520. { {0xFFFF} }, /* RX_6 */
  521. { {0xFFFF} }, /* RX_7 */
  522. },
  523. {
  524. { {0, 4, 0xFFFF} }, /* TX_0 */
  525. { {8, 12, 0xFFFF} }, /* TX_1 */
  526. { {16, 20, 0xFFFF} }, /* TX_2 */
  527. { {24, 28, 0xFFFF} }, /* TX_3 */
  528. { {0xFFFF} }, /* TX_4 */
  529. { {0xFFFF} }, /* TX_5 */
  530. { {0xFFFF} }, /* TX_6 */
  531. { {0xFFFF} }, /* TX_7 */
  532. },
  533. };
  534. static struct tdm_dev_config quin_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  535. { /* QUIN TDM */
  536. { {0, 4, 0xFFFF} }, /* RX_0 */
  537. { {8, 12, 0xFFFF} }, /* RX_1 */
  538. { {16, 20, 0xFFFF} }, /* RX_2 */
  539. { {24, 28, 0xFFFF} }, /* RX_3 */
  540. { {0xFFFF} }, /* RX_4 */
  541. { {0xFFFF} }, /* RX_5 */
  542. { {0xFFFF} }, /* RX_6 */
  543. { {0xFFFF} }, /* RX_7 */
  544. },
  545. {
  546. { {0, 4, 0xFFFF} }, /* TX_0 */
  547. { {8, 12, 0xFFFF} }, /* TX_1 */
  548. { {16, 20, 0xFFFF} }, /* TX_2 */
  549. { {24, 28, 0xFFFF} }, /* TX_3 */
  550. { {0xFFFF} }, /* TX_4 */
  551. { {0xFFFF} }, /* TX_5 */
  552. { {0xFFFF} }, /* TX_6 */
  553. { {0xFFFF} }, /* TX_7 */
  554. },
  555. };
  556. static struct tdm_dev_config sen_tdm_dev_config[MAX_PATH][TDM_PORT_MAX] = {
  557. { /* SEN TDM */
  558. { {0, 4, 0xFFFF} }, /* RX_0 */
  559. { {8, 12, 0xFFFF} }, /* RX_1 */
  560. { {16, 20, 0xFFFF} }, /* RX_2 */
  561. { {24, 28, 0xFFFF} }, /* RX_3 */
  562. { {0xFFFF} }, /* RX_4 */
  563. { {0xFFFF} }, /* RX_5 */
  564. { {0xFFFF} }, /* RX_6 */
  565. { {0xFFFF} }, /* RX_7 */
  566. },
  567. {
  568. { {0, 4, 0xFFFF} }, /* TX_0 */
  569. { {8, 12, 0xFFFF} }, /* TX_1 */
  570. { {16, 20, 0xFFFF} }, /* TX_2 */
  571. { {24, 28, 0xFFFF} }, /* TX_3 */
  572. { {0xFFFF} }, /* TX_4 */
  573. { {0xFFFF} }, /* TX_5 */
  574. { {0xFFFF} }, /* TX_6 */
  575. { {0xFFFF} }, /* TX_7 */
  576. },
  577. };
  578. static void *tdm_cfg[TDM_INTERFACE_MAX] = {
  579. pri_tdm_dev_config,
  580. sec_tdm_dev_config,
  581. tert_tdm_dev_config,
  582. quat_tdm_dev_config,
  583. quin_tdm_dev_config,
  584. sen_tdm_dev_config,
  585. };
  586. /* Default configuration of Codec DMA Interface RX */
  587. static struct dev_config cdc_dma_rx_cfg[] = {
  588. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  589. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  590. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  591. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  592. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  593. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  594. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  595. };
  596. /* Default configuration of Codec DMA Interface TX */
  597. static struct dev_config cdc_dma_tx_cfg[] = {
  598. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  599. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  600. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  601. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  602. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  603. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  604. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  605. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  606. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  607. };
  608. static struct dev_config afe_loopback_tx_cfg[] = {
  609. [AFE_LOOPBACK_TX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  610. };
  611. static int msm_vi_feed_tx_ch = 2;
  612. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  613. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  614. "S32_LE"};
  615. static char const *cdc80_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"};
  616. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  617. "Six", "Seven", "Eight"};
  618. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  619. "KHZ_16", "KHZ_22P05",
  620. "KHZ_32", "KHZ_44P1", "KHZ_48",
  621. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  622. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  623. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  624. "Five", "Six", "Seven",
  625. "Eight"};
  626. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  627. "KHZ_48", "KHZ_176P4",
  628. "KHZ_352P8"};
  629. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  630. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  631. "Five", "Six", "Seven", "Eight"};
  632. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  633. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  634. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  635. "KHZ_48", "KHZ_88P2", "KHZ_96",
  636. "KHZ_176P4", "KHZ_192","KHZ_352P8",
  637. "KHZ_384"};
  638. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  639. "Five", "Six", "Seven",
  640. "Eight"};
  641. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  642. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  643. "Five", "Six", "Seven",
  644. "Eight"};
  645. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  646. "KHZ_16", "KHZ_22P05",
  647. "KHZ_32", "KHZ_44P1", "KHZ_48",
  648. "KHZ_88P2", "KHZ_96",
  649. "KHZ_176P4", "KHZ_192",
  650. "KHZ_352P8", "KHZ_384"};
  651. static char const *cdc80_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  652. "KHZ_16", "KHZ_22P05",
  653. "KHZ_32", "KHZ_44P1", "KHZ_48",
  654. "KHZ_88P2", "KHZ_96",
  655. "KHZ_176P4", "KHZ_192"};
  656. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
  657. "S24_3LE"};
  658. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  659. "KHZ_192", "KHZ_32", "KHZ_44P1",
  660. "KHZ_88P2", "KHZ_176P4"};
  661. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  662. "KHZ_44P1", "KHZ_48",
  663. "KHZ_88P2", "KHZ_96"};
  664. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  665. "KHZ_44P1", "KHZ_48",
  666. "KHZ_88P2", "KHZ_96"};
  667. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  668. "KHZ_44P1", "KHZ_48",
  669. "KHZ_88P2", "KHZ_96"};
  670. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  671. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  672. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  673. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  674. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  675. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  676. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  677. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  678. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  679. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  680. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  681. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  682. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  683. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  684. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  685. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  686. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  687. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  688. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  689. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  690. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  691. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  692. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  693. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  694. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  695. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  696. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  697. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  698. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  699. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  700. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  701. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  702. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  703. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  704. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  705. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  706. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  707. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  708. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  709. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  710. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  711. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  712. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  713. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  714. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  715. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  716. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  717. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  718. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  719. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  720. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  721. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  722. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  723. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  724. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  725. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  726. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  727. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  728. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  729. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  730. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  731. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  732. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  733. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  734. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  735. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  736. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  737. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  738. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  739. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  740. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  741. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  742. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  743. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  744. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  745. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  746. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  747. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  748. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  749. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  750. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  751. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  752. cdc_dma_sample_rate_text);
  753. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  754. cdc_dma_sample_rate_text);
  755. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  756. cdc_dma_sample_rate_text);
  757. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  758. cdc_dma_sample_rate_text);
  759. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  760. cdc_dma_sample_rate_text);
  761. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  762. cdc_dma_sample_rate_text);
  763. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  764. cdc_dma_sample_rate_text);
  765. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  766. cdc_dma_sample_rate_text);
  767. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  768. cdc_dma_sample_rate_text);
  769. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  770. cdc_dma_sample_rate_text);
  771. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  772. cdc_dma_sample_rate_text);
  773. /* WCD9380 */
  774. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_format, cdc80_bit_format_text);
  775. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_format, cdc80_bit_format_text);
  776. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_format, cdc80_bit_format_text);
  777. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_format, cdc80_bit_format_text);
  778. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_format, cdc80_bit_format_text);
  779. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_sample_rate,
  780. cdc80_dma_sample_rate_text);
  781. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_sample_rate,
  782. cdc80_dma_sample_rate_text);
  783. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_sample_rate,
  784. cdc80_dma_sample_rate_text);
  785. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_sample_rate,
  786. cdc80_dma_sample_rate_text);
  787. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_sample_rate,
  788. cdc80_dma_sample_rate_text);
  789. /* WCD9385 */
  790. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_format, bit_format_text);
  791. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_format, bit_format_text);
  792. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_format, bit_format_text);
  793. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_format, bit_format_text);
  794. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_format, bit_format_text);
  795. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_sample_rate,
  796. cdc_dma_sample_rate_text);
  797. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_sample_rate,
  798. cdc_dma_sample_rate_text);
  799. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_sample_rate,
  800. cdc_dma_sample_rate_text);
  801. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_sample_rate,
  802. cdc_dma_sample_rate_text);
  803. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_sample_rate,
  804. cdc_dma_sample_rate_text);
  805. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  806. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  807. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  808. ext_disp_sample_rate_text);
  809. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  810. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  811. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  812. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  813. static bool is_initial_boot;
  814. static bool codec_reg_done;
  815. static struct snd_soc_aux_dev *msm_aux_dev;
  816. static struct snd_soc_codec_conf *msm_codec_conf;
  817. static struct snd_soc_card snd_soc_card_kona_msm;
  818. static int dmic_0_1_gpio_cnt;
  819. static int dmic_2_3_gpio_cnt;
  820. static int dmic_4_5_gpio_cnt;
  821. static void *def_wcd_mbhc_cal(void);
  822. /*
  823. * Need to report LINEIN
  824. * if R/L channel impedance is larger than 5K ohm
  825. */
  826. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  827. .read_fw_bin = false,
  828. .calibration = NULL,
  829. .detect_extn_cable = true,
  830. .mono_stero_detection = false,
  831. .swap_gnd_mic = NULL,
  832. .hs_ext_micbias = true,
  833. .key_code[0] = KEY_MEDIA,
  834. .key_code[1] = KEY_VOICECOMMAND,
  835. .key_code[2] = KEY_VOLUMEUP,
  836. .key_code[3] = KEY_VOLUMEDOWN,
  837. .key_code[4] = 0,
  838. .key_code[5] = 0,
  839. .key_code[6] = 0,
  840. .key_code[7] = 0,
  841. .linein_th = 5000,
  842. .moisture_en = false,
  843. .mbhc_micbias = MIC_BIAS_2,
  844. .anc_micbias = MIC_BIAS_2,
  845. .enable_anc_mic_detect = false,
  846. .moisture_duty_cycle_en = true,
  847. };
  848. static inline int param_is_mask(int p)
  849. {
  850. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  851. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  852. }
  853. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  854. int n)
  855. {
  856. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  857. }
  858. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  859. unsigned int bit)
  860. {
  861. if (bit >= SNDRV_MASK_MAX)
  862. return;
  863. if (param_is_mask(n)) {
  864. struct snd_mask *m = param_to_mask(p, n);
  865. m->bits[0] = 0;
  866. m->bits[1] = 0;
  867. m->bits[bit >> 5] |= (1 << (bit & 31));
  868. }
  869. }
  870. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  871. struct snd_ctl_elem_value *ucontrol)
  872. {
  873. int sample_rate_val = 0;
  874. switch (usb_rx_cfg.sample_rate) {
  875. case SAMPLING_RATE_384KHZ:
  876. sample_rate_val = 12;
  877. break;
  878. case SAMPLING_RATE_352P8KHZ:
  879. sample_rate_val = 11;
  880. break;
  881. case SAMPLING_RATE_192KHZ:
  882. sample_rate_val = 10;
  883. break;
  884. case SAMPLING_RATE_176P4KHZ:
  885. sample_rate_val = 9;
  886. break;
  887. case SAMPLING_RATE_96KHZ:
  888. sample_rate_val = 8;
  889. break;
  890. case SAMPLING_RATE_88P2KHZ:
  891. sample_rate_val = 7;
  892. break;
  893. case SAMPLING_RATE_48KHZ:
  894. sample_rate_val = 6;
  895. break;
  896. case SAMPLING_RATE_44P1KHZ:
  897. sample_rate_val = 5;
  898. break;
  899. case SAMPLING_RATE_32KHZ:
  900. sample_rate_val = 4;
  901. break;
  902. case SAMPLING_RATE_22P05KHZ:
  903. sample_rate_val = 3;
  904. break;
  905. case SAMPLING_RATE_16KHZ:
  906. sample_rate_val = 2;
  907. break;
  908. case SAMPLING_RATE_11P025KHZ:
  909. sample_rate_val = 1;
  910. break;
  911. case SAMPLING_RATE_8KHZ:
  912. default:
  913. sample_rate_val = 0;
  914. break;
  915. }
  916. ucontrol->value.integer.value[0] = sample_rate_val;
  917. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  918. usb_rx_cfg.sample_rate);
  919. return 0;
  920. }
  921. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  922. struct snd_ctl_elem_value *ucontrol)
  923. {
  924. switch (ucontrol->value.integer.value[0]) {
  925. case 12:
  926. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  927. break;
  928. case 11:
  929. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  930. break;
  931. case 10:
  932. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  933. break;
  934. case 9:
  935. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  936. break;
  937. case 8:
  938. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  939. break;
  940. case 7:
  941. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  942. break;
  943. case 6:
  944. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  945. break;
  946. case 5:
  947. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  948. break;
  949. case 4:
  950. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  951. break;
  952. case 3:
  953. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  954. break;
  955. case 2:
  956. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  957. break;
  958. case 1:
  959. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  960. break;
  961. case 0:
  962. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  963. break;
  964. default:
  965. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  966. break;
  967. }
  968. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  969. __func__, ucontrol->value.integer.value[0],
  970. usb_rx_cfg.sample_rate);
  971. return 0;
  972. }
  973. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  974. struct snd_ctl_elem_value *ucontrol)
  975. {
  976. int sample_rate_val = 0;
  977. switch (usb_tx_cfg.sample_rate) {
  978. case SAMPLING_RATE_384KHZ:
  979. sample_rate_val = 12;
  980. break;
  981. case SAMPLING_RATE_352P8KHZ:
  982. sample_rate_val = 11;
  983. break;
  984. case SAMPLING_RATE_192KHZ:
  985. sample_rate_val = 10;
  986. break;
  987. case SAMPLING_RATE_176P4KHZ:
  988. sample_rate_val = 9;
  989. break;
  990. case SAMPLING_RATE_96KHZ:
  991. sample_rate_val = 8;
  992. break;
  993. case SAMPLING_RATE_88P2KHZ:
  994. sample_rate_val = 7;
  995. break;
  996. case SAMPLING_RATE_48KHZ:
  997. sample_rate_val = 6;
  998. break;
  999. case SAMPLING_RATE_44P1KHZ:
  1000. sample_rate_val = 5;
  1001. break;
  1002. case SAMPLING_RATE_32KHZ:
  1003. sample_rate_val = 4;
  1004. break;
  1005. case SAMPLING_RATE_22P05KHZ:
  1006. sample_rate_val = 3;
  1007. break;
  1008. case SAMPLING_RATE_16KHZ:
  1009. sample_rate_val = 2;
  1010. break;
  1011. case SAMPLING_RATE_11P025KHZ:
  1012. sample_rate_val = 1;
  1013. break;
  1014. case SAMPLING_RATE_8KHZ:
  1015. sample_rate_val = 0;
  1016. break;
  1017. default:
  1018. sample_rate_val = 6;
  1019. break;
  1020. }
  1021. ucontrol->value.integer.value[0] = sample_rate_val;
  1022. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1023. usb_tx_cfg.sample_rate);
  1024. return 0;
  1025. }
  1026. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1027. struct snd_ctl_elem_value *ucontrol)
  1028. {
  1029. switch (ucontrol->value.integer.value[0]) {
  1030. case 12:
  1031. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1032. break;
  1033. case 11:
  1034. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1035. break;
  1036. case 10:
  1037. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1038. break;
  1039. case 9:
  1040. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1041. break;
  1042. case 8:
  1043. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1044. break;
  1045. case 7:
  1046. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1047. break;
  1048. case 6:
  1049. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1050. break;
  1051. case 5:
  1052. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1053. break;
  1054. case 4:
  1055. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1056. break;
  1057. case 3:
  1058. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1059. break;
  1060. case 2:
  1061. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1062. break;
  1063. case 1:
  1064. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1065. break;
  1066. case 0:
  1067. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1068. break;
  1069. default:
  1070. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1071. break;
  1072. }
  1073. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1074. __func__, ucontrol->value.integer.value[0],
  1075. usb_tx_cfg.sample_rate);
  1076. return 0;
  1077. }
  1078. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  1079. struct snd_ctl_elem_value *ucontrol)
  1080. {
  1081. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  1082. afe_loopback_tx_cfg[0].channels);
  1083. ucontrol->value.enumerated.item[0] =
  1084. afe_loopback_tx_cfg[0].channels - 1;
  1085. return 0;
  1086. }
  1087. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  1088. struct snd_ctl_elem_value *ucontrol)
  1089. {
  1090. afe_loopback_tx_cfg[0].channels =
  1091. ucontrol->value.enumerated.item[0] + 1;
  1092. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  1093. afe_loopback_tx_cfg[0].channels);
  1094. return 1;
  1095. }
  1096. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1097. struct snd_ctl_elem_value *ucontrol)
  1098. {
  1099. switch (usb_rx_cfg.bit_format) {
  1100. case SNDRV_PCM_FORMAT_S32_LE:
  1101. ucontrol->value.integer.value[0] = 3;
  1102. break;
  1103. case SNDRV_PCM_FORMAT_S24_3LE:
  1104. ucontrol->value.integer.value[0] = 2;
  1105. break;
  1106. case SNDRV_PCM_FORMAT_S24_LE:
  1107. ucontrol->value.integer.value[0] = 1;
  1108. break;
  1109. case SNDRV_PCM_FORMAT_S16_LE:
  1110. default:
  1111. ucontrol->value.integer.value[0] = 0;
  1112. break;
  1113. }
  1114. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1115. __func__, usb_rx_cfg.bit_format,
  1116. ucontrol->value.integer.value[0]);
  1117. return 0;
  1118. }
  1119. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1120. struct snd_ctl_elem_value *ucontrol)
  1121. {
  1122. int rc = 0;
  1123. switch (ucontrol->value.integer.value[0]) {
  1124. case 3:
  1125. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1126. break;
  1127. case 2:
  1128. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1129. break;
  1130. case 1:
  1131. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1132. break;
  1133. case 0:
  1134. default:
  1135. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1136. break;
  1137. }
  1138. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1139. __func__, usb_rx_cfg.bit_format,
  1140. ucontrol->value.integer.value[0]);
  1141. return rc;
  1142. }
  1143. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1144. struct snd_ctl_elem_value *ucontrol)
  1145. {
  1146. switch (usb_tx_cfg.bit_format) {
  1147. case SNDRV_PCM_FORMAT_S32_LE:
  1148. ucontrol->value.integer.value[0] = 3;
  1149. break;
  1150. case SNDRV_PCM_FORMAT_S24_3LE:
  1151. ucontrol->value.integer.value[0] = 2;
  1152. break;
  1153. case SNDRV_PCM_FORMAT_S24_LE:
  1154. ucontrol->value.integer.value[0] = 1;
  1155. break;
  1156. case SNDRV_PCM_FORMAT_S16_LE:
  1157. default:
  1158. ucontrol->value.integer.value[0] = 0;
  1159. break;
  1160. }
  1161. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1162. __func__, usb_tx_cfg.bit_format,
  1163. ucontrol->value.integer.value[0]);
  1164. return 0;
  1165. }
  1166. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1167. struct snd_ctl_elem_value *ucontrol)
  1168. {
  1169. int rc = 0;
  1170. switch (ucontrol->value.integer.value[0]) {
  1171. case 3:
  1172. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1173. break;
  1174. case 2:
  1175. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1176. break;
  1177. case 1:
  1178. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1179. break;
  1180. case 0:
  1181. default:
  1182. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1183. break;
  1184. }
  1185. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1186. __func__, usb_tx_cfg.bit_format,
  1187. ucontrol->value.integer.value[0]);
  1188. return rc;
  1189. }
  1190. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1191. struct snd_ctl_elem_value *ucontrol)
  1192. {
  1193. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1194. usb_rx_cfg.channels);
  1195. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1196. return 0;
  1197. }
  1198. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1199. struct snd_ctl_elem_value *ucontrol)
  1200. {
  1201. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1202. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1203. return 1;
  1204. }
  1205. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1206. struct snd_ctl_elem_value *ucontrol)
  1207. {
  1208. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1209. usb_tx_cfg.channels);
  1210. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1211. return 0;
  1212. }
  1213. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1214. struct snd_ctl_elem_value *ucontrol)
  1215. {
  1216. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1217. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1218. return 1;
  1219. }
  1220. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  1221. struct snd_ctl_elem_value *ucontrol)
  1222. {
  1223. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  1224. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  1225. ucontrol->value.integer.value[0]);
  1226. return 0;
  1227. }
  1228. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1229. struct snd_ctl_elem_value *ucontrol)
  1230. {
  1231. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1232. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1233. return 1;
  1234. }
  1235. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  1236. {
  1237. int idx = 0;
  1238. if (strnstr(kcontrol->id.name, "Display Port RX",
  1239. sizeof("Display Port RX"))) {
  1240. idx = EXT_DISP_RX_IDX_DP;
  1241. } else if (strnstr(kcontrol->id.name, "Display Port1 RX",
  1242. sizeof("Display Port1 RX"))) {
  1243. idx = EXT_DISP_RX_IDX_DP1;
  1244. } else {
  1245. pr_err("%s: unsupported BE: %s\n",
  1246. __func__, kcontrol->id.name);
  1247. idx = -EINVAL;
  1248. }
  1249. return idx;
  1250. }
  1251. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  1252. struct snd_ctl_elem_value *ucontrol)
  1253. {
  1254. int idx = ext_disp_get_port_idx(kcontrol);
  1255. if (idx < 0)
  1256. return idx;
  1257. switch (ext_disp_rx_cfg[idx].bit_format) {
  1258. case SNDRV_PCM_FORMAT_S24_3LE:
  1259. ucontrol->value.integer.value[0] = 2;
  1260. break;
  1261. case SNDRV_PCM_FORMAT_S24_LE:
  1262. ucontrol->value.integer.value[0] = 1;
  1263. break;
  1264. case SNDRV_PCM_FORMAT_S16_LE:
  1265. default:
  1266. ucontrol->value.integer.value[0] = 0;
  1267. break;
  1268. }
  1269. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1270. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1271. ucontrol->value.integer.value[0]);
  1272. return 0;
  1273. }
  1274. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  1275. struct snd_ctl_elem_value *ucontrol)
  1276. {
  1277. int idx = ext_disp_get_port_idx(kcontrol);
  1278. if (idx < 0)
  1279. return idx;
  1280. switch (ucontrol->value.integer.value[0]) {
  1281. case 2:
  1282. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1283. break;
  1284. case 1:
  1285. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1286. break;
  1287. case 0:
  1288. default:
  1289. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1290. break;
  1291. }
  1292. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1293. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1294. ucontrol->value.integer.value[0]);
  1295. return 0;
  1296. }
  1297. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  1298. struct snd_ctl_elem_value *ucontrol)
  1299. {
  1300. int idx = ext_disp_get_port_idx(kcontrol);
  1301. if (idx < 0)
  1302. return idx;
  1303. ucontrol->value.integer.value[0] =
  1304. ext_disp_rx_cfg[idx].channels - 2;
  1305. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1306. idx, ext_disp_rx_cfg[idx].channels);
  1307. return 0;
  1308. }
  1309. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  1310. struct snd_ctl_elem_value *ucontrol)
  1311. {
  1312. int idx = ext_disp_get_port_idx(kcontrol);
  1313. if (idx < 0)
  1314. return idx;
  1315. ext_disp_rx_cfg[idx].channels =
  1316. ucontrol->value.integer.value[0] + 2;
  1317. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1318. idx, ext_disp_rx_cfg[idx].channels);
  1319. return 1;
  1320. }
  1321. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1322. struct snd_ctl_elem_value *ucontrol)
  1323. {
  1324. int sample_rate_val;
  1325. int idx = ext_disp_get_port_idx(kcontrol);
  1326. if (idx < 0)
  1327. return idx;
  1328. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1329. case SAMPLING_RATE_176P4KHZ:
  1330. sample_rate_val = 6;
  1331. break;
  1332. case SAMPLING_RATE_88P2KHZ:
  1333. sample_rate_val = 5;
  1334. break;
  1335. case SAMPLING_RATE_44P1KHZ:
  1336. sample_rate_val = 4;
  1337. break;
  1338. case SAMPLING_RATE_32KHZ:
  1339. sample_rate_val = 3;
  1340. break;
  1341. case SAMPLING_RATE_192KHZ:
  1342. sample_rate_val = 2;
  1343. break;
  1344. case SAMPLING_RATE_96KHZ:
  1345. sample_rate_val = 1;
  1346. break;
  1347. case SAMPLING_RATE_48KHZ:
  1348. default:
  1349. sample_rate_val = 0;
  1350. break;
  1351. }
  1352. ucontrol->value.integer.value[0] = sample_rate_val;
  1353. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1354. idx, ext_disp_rx_cfg[idx].sample_rate);
  1355. return 0;
  1356. }
  1357. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1358. struct snd_ctl_elem_value *ucontrol)
  1359. {
  1360. int idx = ext_disp_get_port_idx(kcontrol);
  1361. if (idx < 0)
  1362. return idx;
  1363. switch (ucontrol->value.integer.value[0]) {
  1364. case 6:
  1365. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
  1366. break;
  1367. case 5:
  1368. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
  1369. break;
  1370. case 4:
  1371. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
  1372. break;
  1373. case 3:
  1374. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
  1375. break;
  1376. case 2:
  1377. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1378. break;
  1379. case 1:
  1380. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1381. break;
  1382. case 0:
  1383. default:
  1384. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1385. break;
  1386. }
  1387. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1388. __func__, ucontrol->value.integer.value[0], idx,
  1389. ext_disp_rx_cfg[idx].sample_rate);
  1390. return 0;
  1391. }
  1392. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1393. struct snd_ctl_elem_value *ucontrol)
  1394. {
  1395. pr_debug("%s: proxy_rx channels = %d\n",
  1396. __func__, proxy_rx_cfg.channels);
  1397. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1398. return 0;
  1399. }
  1400. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1401. struct snd_ctl_elem_value *ucontrol)
  1402. {
  1403. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1404. pr_debug("%s: proxy_rx channels = %d\n",
  1405. __func__, proxy_rx_cfg.channels);
  1406. return 1;
  1407. }
  1408. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1409. struct tdm_port *port)
  1410. {
  1411. if (port) {
  1412. if (strnstr(kcontrol->id.name, "PRI",
  1413. sizeof(kcontrol->id.name))) {
  1414. port->mode = TDM_PRI;
  1415. } else if (strnstr(kcontrol->id.name, "SEC",
  1416. sizeof(kcontrol->id.name))) {
  1417. port->mode = TDM_SEC;
  1418. } else if (strnstr(kcontrol->id.name, "TERT",
  1419. sizeof(kcontrol->id.name))) {
  1420. port->mode = TDM_TERT;
  1421. } else if (strnstr(kcontrol->id.name, "QUAT",
  1422. sizeof(kcontrol->id.name))) {
  1423. port->mode = TDM_QUAT;
  1424. } else if (strnstr(kcontrol->id.name, "QUIN",
  1425. sizeof(kcontrol->id.name))) {
  1426. port->mode = TDM_QUIN;
  1427. } else if (strnstr(kcontrol->id.name, "SEN",
  1428. sizeof(kcontrol->id.name))) {
  1429. port->mode = TDM_SEN;
  1430. } else {
  1431. pr_err("%s: unsupported mode in: %s\n",
  1432. __func__, kcontrol->id.name);
  1433. return -EINVAL;
  1434. }
  1435. if (strnstr(kcontrol->id.name, "RX_0",
  1436. sizeof(kcontrol->id.name)) ||
  1437. strnstr(kcontrol->id.name, "TX_0",
  1438. sizeof(kcontrol->id.name))) {
  1439. port->channel = TDM_0;
  1440. } else if (strnstr(kcontrol->id.name, "RX_1",
  1441. sizeof(kcontrol->id.name)) ||
  1442. strnstr(kcontrol->id.name, "TX_1",
  1443. sizeof(kcontrol->id.name))) {
  1444. port->channel = TDM_1;
  1445. } else if (strnstr(kcontrol->id.name, "RX_2",
  1446. sizeof(kcontrol->id.name)) ||
  1447. strnstr(kcontrol->id.name, "TX_2",
  1448. sizeof(kcontrol->id.name))) {
  1449. port->channel = TDM_2;
  1450. } else if (strnstr(kcontrol->id.name, "RX_3",
  1451. sizeof(kcontrol->id.name)) ||
  1452. strnstr(kcontrol->id.name, "TX_3",
  1453. sizeof(kcontrol->id.name))) {
  1454. port->channel = TDM_3;
  1455. } else if (strnstr(kcontrol->id.name, "RX_4",
  1456. sizeof(kcontrol->id.name)) ||
  1457. strnstr(kcontrol->id.name, "TX_4",
  1458. sizeof(kcontrol->id.name))) {
  1459. port->channel = TDM_4;
  1460. } else if (strnstr(kcontrol->id.name, "RX_5",
  1461. sizeof(kcontrol->id.name)) ||
  1462. strnstr(kcontrol->id.name, "TX_5",
  1463. sizeof(kcontrol->id.name))) {
  1464. port->channel = TDM_5;
  1465. } else if (strnstr(kcontrol->id.name, "RX_6",
  1466. sizeof(kcontrol->id.name)) ||
  1467. strnstr(kcontrol->id.name, "TX_6",
  1468. sizeof(kcontrol->id.name))) {
  1469. port->channel = TDM_6;
  1470. } else if (strnstr(kcontrol->id.name, "RX_7",
  1471. sizeof(kcontrol->id.name)) ||
  1472. strnstr(kcontrol->id.name, "TX_7",
  1473. sizeof(kcontrol->id.name))) {
  1474. port->channel = TDM_7;
  1475. } else {
  1476. pr_err("%s: unsupported channel in: %s\n",
  1477. __func__, kcontrol->id.name);
  1478. return -EINVAL;
  1479. }
  1480. } else {
  1481. return -EINVAL;
  1482. }
  1483. return 0;
  1484. }
  1485. static int tdm_get_sample_rate(int value)
  1486. {
  1487. int sample_rate = 0;
  1488. switch (value) {
  1489. case 0:
  1490. sample_rate = SAMPLING_RATE_8KHZ;
  1491. break;
  1492. case 1:
  1493. sample_rate = SAMPLING_RATE_16KHZ;
  1494. break;
  1495. case 2:
  1496. sample_rate = SAMPLING_RATE_32KHZ;
  1497. break;
  1498. case 3:
  1499. sample_rate = SAMPLING_RATE_48KHZ;
  1500. break;
  1501. case 4:
  1502. sample_rate = SAMPLING_RATE_176P4KHZ;
  1503. break;
  1504. case 5:
  1505. sample_rate = SAMPLING_RATE_352P8KHZ;
  1506. break;
  1507. default:
  1508. sample_rate = SAMPLING_RATE_48KHZ;
  1509. break;
  1510. }
  1511. return sample_rate;
  1512. }
  1513. static int tdm_get_sample_rate_val(int sample_rate)
  1514. {
  1515. int sample_rate_val = 0;
  1516. switch (sample_rate) {
  1517. case SAMPLING_RATE_8KHZ:
  1518. sample_rate_val = 0;
  1519. break;
  1520. case SAMPLING_RATE_16KHZ:
  1521. sample_rate_val = 1;
  1522. break;
  1523. case SAMPLING_RATE_32KHZ:
  1524. sample_rate_val = 2;
  1525. break;
  1526. case SAMPLING_RATE_48KHZ:
  1527. sample_rate_val = 3;
  1528. break;
  1529. case SAMPLING_RATE_176P4KHZ:
  1530. sample_rate_val = 4;
  1531. break;
  1532. case SAMPLING_RATE_352P8KHZ:
  1533. sample_rate_val = 5;
  1534. break;
  1535. default:
  1536. sample_rate_val = 3;
  1537. break;
  1538. }
  1539. return sample_rate_val;
  1540. }
  1541. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1542. struct snd_ctl_elem_value *ucontrol)
  1543. {
  1544. struct tdm_port port;
  1545. int ret = tdm_get_port_idx(kcontrol, &port);
  1546. if (ret) {
  1547. pr_err("%s: unsupported control: %s\n",
  1548. __func__, kcontrol->id.name);
  1549. } else {
  1550. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1551. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1552. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1553. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1554. ucontrol->value.enumerated.item[0]);
  1555. }
  1556. return ret;
  1557. }
  1558. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1559. struct snd_ctl_elem_value *ucontrol)
  1560. {
  1561. struct tdm_port port;
  1562. int ret = tdm_get_port_idx(kcontrol, &port);
  1563. if (ret) {
  1564. pr_err("%s: unsupported control: %s\n",
  1565. __func__, kcontrol->id.name);
  1566. } else {
  1567. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1568. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1569. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1570. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1571. ucontrol->value.enumerated.item[0]);
  1572. }
  1573. return ret;
  1574. }
  1575. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1576. struct snd_ctl_elem_value *ucontrol)
  1577. {
  1578. struct tdm_port port;
  1579. int ret = tdm_get_port_idx(kcontrol, &port);
  1580. if (ret) {
  1581. pr_err("%s: unsupported control: %s\n",
  1582. __func__, kcontrol->id.name);
  1583. } else {
  1584. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1585. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1586. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1587. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1588. ucontrol->value.enumerated.item[0]);
  1589. }
  1590. return ret;
  1591. }
  1592. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1593. struct snd_ctl_elem_value *ucontrol)
  1594. {
  1595. struct tdm_port port;
  1596. int ret = tdm_get_port_idx(kcontrol, &port);
  1597. if (ret) {
  1598. pr_err("%s: unsupported control: %s\n",
  1599. __func__, kcontrol->id.name);
  1600. } else {
  1601. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1602. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1603. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1604. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1605. ucontrol->value.enumerated.item[0]);
  1606. }
  1607. return ret;
  1608. }
  1609. static int tdm_get_format(int value)
  1610. {
  1611. int format = 0;
  1612. switch (value) {
  1613. case 0:
  1614. format = SNDRV_PCM_FORMAT_S16_LE;
  1615. break;
  1616. case 1:
  1617. format = SNDRV_PCM_FORMAT_S24_LE;
  1618. break;
  1619. case 2:
  1620. format = SNDRV_PCM_FORMAT_S32_LE;
  1621. break;
  1622. default:
  1623. format = SNDRV_PCM_FORMAT_S16_LE;
  1624. break;
  1625. }
  1626. return format;
  1627. }
  1628. static int tdm_get_format_val(int format)
  1629. {
  1630. int value = 0;
  1631. switch (format) {
  1632. case SNDRV_PCM_FORMAT_S16_LE:
  1633. value = 0;
  1634. break;
  1635. case SNDRV_PCM_FORMAT_S24_LE:
  1636. value = 1;
  1637. break;
  1638. case SNDRV_PCM_FORMAT_S32_LE:
  1639. value = 2;
  1640. break;
  1641. default:
  1642. value = 0;
  1643. break;
  1644. }
  1645. return value;
  1646. }
  1647. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1648. struct snd_ctl_elem_value *ucontrol)
  1649. {
  1650. struct tdm_port port;
  1651. int ret = tdm_get_port_idx(kcontrol, &port);
  1652. if (ret) {
  1653. pr_err("%s: unsupported control: %s\n",
  1654. __func__, kcontrol->id.name);
  1655. } else {
  1656. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1657. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1658. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1659. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1660. ucontrol->value.enumerated.item[0]);
  1661. }
  1662. return ret;
  1663. }
  1664. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1665. struct snd_ctl_elem_value *ucontrol)
  1666. {
  1667. struct tdm_port port;
  1668. int ret = tdm_get_port_idx(kcontrol, &port);
  1669. if (ret) {
  1670. pr_err("%s: unsupported control: %s\n",
  1671. __func__, kcontrol->id.name);
  1672. } else {
  1673. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1674. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1675. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1676. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1677. ucontrol->value.enumerated.item[0]);
  1678. }
  1679. return ret;
  1680. }
  1681. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1682. struct snd_ctl_elem_value *ucontrol)
  1683. {
  1684. struct tdm_port port;
  1685. int ret = tdm_get_port_idx(kcontrol, &port);
  1686. if (ret) {
  1687. pr_err("%s: unsupported control: %s\n",
  1688. __func__, kcontrol->id.name);
  1689. } else {
  1690. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1691. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1692. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1693. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1694. ucontrol->value.enumerated.item[0]);
  1695. }
  1696. return ret;
  1697. }
  1698. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1699. struct snd_ctl_elem_value *ucontrol)
  1700. {
  1701. struct tdm_port port;
  1702. int ret = tdm_get_port_idx(kcontrol, &port);
  1703. if (ret) {
  1704. pr_err("%s: unsupported control: %s\n",
  1705. __func__, kcontrol->id.name);
  1706. } else {
  1707. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1708. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1709. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1710. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1711. ucontrol->value.enumerated.item[0]);
  1712. }
  1713. return ret;
  1714. }
  1715. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1716. struct snd_ctl_elem_value *ucontrol)
  1717. {
  1718. struct tdm_port port;
  1719. int ret = tdm_get_port_idx(kcontrol, &port);
  1720. if (ret) {
  1721. pr_err("%s: unsupported control: %s\n",
  1722. __func__, kcontrol->id.name);
  1723. } else {
  1724. ucontrol->value.enumerated.item[0] =
  1725. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1726. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1727. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1728. ucontrol->value.enumerated.item[0]);
  1729. }
  1730. return ret;
  1731. }
  1732. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1733. struct snd_ctl_elem_value *ucontrol)
  1734. {
  1735. struct tdm_port port;
  1736. int ret = tdm_get_port_idx(kcontrol, &port);
  1737. if (ret) {
  1738. pr_err("%s: unsupported control: %s\n",
  1739. __func__, kcontrol->id.name);
  1740. } else {
  1741. tdm_rx_cfg[port.mode][port.channel].channels =
  1742. ucontrol->value.enumerated.item[0] + 1;
  1743. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1744. tdm_rx_cfg[port.mode][port.channel].channels,
  1745. ucontrol->value.enumerated.item[0] + 1);
  1746. }
  1747. return ret;
  1748. }
  1749. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1750. struct snd_ctl_elem_value *ucontrol)
  1751. {
  1752. struct tdm_port port;
  1753. int ret = tdm_get_port_idx(kcontrol, &port);
  1754. if (ret) {
  1755. pr_err("%s: unsupported control: %s\n",
  1756. __func__, kcontrol->id.name);
  1757. } else {
  1758. ucontrol->value.enumerated.item[0] =
  1759. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1760. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1761. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1762. ucontrol->value.enumerated.item[0]);
  1763. }
  1764. return ret;
  1765. }
  1766. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1767. struct snd_ctl_elem_value *ucontrol)
  1768. {
  1769. struct tdm_port port;
  1770. int ret = tdm_get_port_idx(kcontrol, &port);
  1771. if (ret) {
  1772. pr_err("%s: unsupported control: %s\n",
  1773. __func__, kcontrol->id.name);
  1774. } else {
  1775. tdm_tx_cfg[port.mode][port.channel].channels =
  1776. ucontrol->value.enumerated.item[0] + 1;
  1777. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1778. tdm_tx_cfg[port.mode][port.channel].channels,
  1779. ucontrol->value.enumerated.item[0] + 1);
  1780. }
  1781. return ret;
  1782. }
  1783. static int tdm_slot_map_put(struct snd_kcontrol *kcontrol,
  1784. struct snd_ctl_elem_value *ucontrol)
  1785. {
  1786. int slot_index = 0;
  1787. int interface = ucontrol->value.integer.value[0];
  1788. int channel = ucontrol->value.integer.value[1];
  1789. unsigned int offset_val = 0;
  1790. unsigned int *slot_offset = NULL;
  1791. struct tdm_dev_config *config = NULL;
  1792. if (interface < 0 || interface >= (TDM_INTERFACE_MAX * MAX_PATH)) {
  1793. pr_err("%s: incorrect interface = %d\n", __func__, interface);
  1794. return -EINVAL;
  1795. }
  1796. if (channel < 0 || channel >= TDM_PORT_MAX) {
  1797. pr_err("%s: incorrect channel = %d\n", __func__, channel);
  1798. return -EINVAL;
  1799. }
  1800. pr_debug("%s: interface = %d, channel = %d\n", __func__,
  1801. interface, channel);
  1802. config = ((struct tdm_dev_config *) tdm_cfg[interface / MAX_PATH]) +
  1803. ((interface % MAX_PATH) * TDM_PORT_MAX) + channel;
  1804. slot_offset = config->tdm_slot_offset;
  1805. for (slot_index = 0; slot_index < TDM_MAX_SLOTS; slot_index++) {
  1806. offset_val = ucontrol->value.integer.value[MAX_PATH +
  1807. slot_index];
  1808. /* Offset value can only be 0, 4, 8, ..28 */
  1809. if (offset_val % 4 == 0 && offset_val <= 28)
  1810. slot_offset[slot_index] = offset_val;
  1811. pr_debug("%s: slot offset[%d] = %d\n", __func__,
  1812. slot_index, slot_offset[slot_index]);
  1813. }
  1814. return 0;
  1815. }
  1816. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1817. {
  1818. int idx = 0;
  1819. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1820. sizeof("PRIM_AUX_PCM"))) {
  1821. idx = PRIM_AUX_PCM;
  1822. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1823. sizeof("SEC_AUX_PCM"))) {
  1824. idx = SEC_AUX_PCM;
  1825. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1826. sizeof("TERT_AUX_PCM"))) {
  1827. idx = TERT_AUX_PCM;
  1828. } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  1829. sizeof("QUAT_AUX_PCM"))) {
  1830. idx = QUAT_AUX_PCM;
  1831. } else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  1832. sizeof("QUIN_AUX_PCM"))) {
  1833. idx = QUIN_AUX_PCM;
  1834. } else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  1835. sizeof("SEN_AUX_PCM"))) {
  1836. idx = SEN_AUX_PCM;
  1837. } else {
  1838. pr_err("%s: unsupported port: %s\n",
  1839. __func__, kcontrol->id.name);
  1840. idx = -EINVAL;
  1841. }
  1842. return idx;
  1843. }
  1844. static int aux_pcm_get_sample_rate(int value)
  1845. {
  1846. int sample_rate = 0;
  1847. switch (value) {
  1848. case 1:
  1849. sample_rate = SAMPLING_RATE_16KHZ;
  1850. break;
  1851. case 0:
  1852. default:
  1853. sample_rate = SAMPLING_RATE_8KHZ;
  1854. break;
  1855. }
  1856. return sample_rate;
  1857. }
  1858. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1859. {
  1860. int sample_rate_val = 0;
  1861. switch (sample_rate) {
  1862. case SAMPLING_RATE_16KHZ:
  1863. sample_rate_val = 1;
  1864. break;
  1865. case SAMPLING_RATE_8KHZ:
  1866. default:
  1867. sample_rate_val = 0;
  1868. break;
  1869. }
  1870. return sample_rate_val;
  1871. }
  1872. static int mi2s_auxpcm_get_format(int value)
  1873. {
  1874. int format = 0;
  1875. switch (value) {
  1876. case 0:
  1877. format = SNDRV_PCM_FORMAT_S16_LE;
  1878. break;
  1879. case 1:
  1880. format = SNDRV_PCM_FORMAT_S24_LE;
  1881. break;
  1882. case 2:
  1883. format = SNDRV_PCM_FORMAT_S24_3LE;
  1884. break;
  1885. case 3:
  1886. format = SNDRV_PCM_FORMAT_S32_LE;
  1887. break;
  1888. default:
  1889. format = SNDRV_PCM_FORMAT_S16_LE;
  1890. break;
  1891. }
  1892. return format;
  1893. }
  1894. static int mi2s_auxpcm_get_format_value(int format)
  1895. {
  1896. int value = 0;
  1897. switch (format) {
  1898. case SNDRV_PCM_FORMAT_S16_LE:
  1899. value = 0;
  1900. break;
  1901. case SNDRV_PCM_FORMAT_S24_LE:
  1902. value = 1;
  1903. break;
  1904. case SNDRV_PCM_FORMAT_S24_3LE:
  1905. value = 2;
  1906. break;
  1907. case SNDRV_PCM_FORMAT_S32_LE:
  1908. value = 3;
  1909. break;
  1910. default:
  1911. value = 0;
  1912. break;
  1913. }
  1914. return value;
  1915. }
  1916. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1917. struct snd_ctl_elem_value *ucontrol)
  1918. {
  1919. int idx = aux_pcm_get_port_idx(kcontrol);
  1920. if (idx < 0)
  1921. return idx;
  1922. ucontrol->value.enumerated.item[0] =
  1923. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1924. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1925. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1926. ucontrol->value.enumerated.item[0]);
  1927. return 0;
  1928. }
  1929. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1930. struct snd_ctl_elem_value *ucontrol)
  1931. {
  1932. int idx = aux_pcm_get_port_idx(kcontrol);
  1933. if (idx < 0)
  1934. return idx;
  1935. aux_pcm_rx_cfg[idx].sample_rate =
  1936. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1937. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1938. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1939. ucontrol->value.enumerated.item[0]);
  1940. return 0;
  1941. }
  1942. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1943. struct snd_ctl_elem_value *ucontrol)
  1944. {
  1945. int idx = aux_pcm_get_port_idx(kcontrol);
  1946. if (idx < 0)
  1947. return idx;
  1948. ucontrol->value.enumerated.item[0] =
  1949. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1950. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1951. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1952. ucontrol->value.enumerated.item[0]);
  1953. return 0;
  1954. }
  1955. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1956. struct snd_ctl_elem_value *ucontrol)
  1957. {
  1958. int idx = aux_pcm_get_port_idx(kcontrol);
  1959. if (idx < 0)
  1960. return idx;
  1961. aux_pcm_tx_cfg[idx].sample_rate =
  1962. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1963. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1964. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1965. ucontrol->value.enumerated.item[0]);
  1966. return 0;
  1967. }
  1968. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1969. struct snd_ctl_elem_value *ucontrol)
  1970. {
  1971. int idx = aux_pcm_get_port_idx(kcontrol);
  1972. if (idx < 0)
  1973. return idx;
  1974. ucontrol->value.enumerated.item[0] =
  1975. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1976. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1977. idx, aux_pcm_rx_cfg[idx].bit_format,
  1978. ucontrol->value.enumerated.item[0]);
  1979. return 0;
  1980. }
  1981. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1982. struct snd_ctl_elem_value *ucontrol)
  1983. {
  1984. int idx = aux_pcm_get_port_idx(kcontrol);
  1985. if (idx < 0)
  1986. return idx;
  1987. aux_pcm_rx_cfg[idx].bit_format =
  1988. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1989. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1990. idx, aux_pcm_rx_cfg[idx].bit_format,
  1991. ucontrol->value.enumerated.item[0]);
  1992. return 0;
  1993. }
  1994. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1995. struct snd_ctl_elem_value *ucontrol)
  1996. {
  1997. int idx = aux_pcm_get_port_idx(kcontrol);
  1998. if (idx < 0)
  1999. return idx;
  2000. ucontrol->value.enumerated.item[0] =
  2001. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2002. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2003. idx, aux_pcm_tx_cfg[idx].bit_format,
  2004. ucontrol->value.enumerated.item[0]);
  2005. return 0;
  2006. }
  2007. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2008. struct snd_ctl_elem_value *ucontrol)
  2009. {
  2010. int idx = aux_pcm_get_port_idx(kcontrol);
  2011. if (idx < 0)
  2012. return idx;
  2013. aux_pcm_tx_cfg[idx].bit_format =
  2014. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2015. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2016. idx, aux_pcm_tx_cfg[idx].bit_format,
  2017. ucontrol->value.enumerated.item[0]);
  2018. return 0;
  2019. }
  2020. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2021. {
  2022. int idx = 0;
  2023. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2024. sizeof("PRIM_MI2S_RX"))) {
  2025. idx = PRIM_MI2S;
  2026. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2027. sizeof("SEC_MI2S_RX"))) {
  2028. idx = SEC_MI2S;
  2029. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2030. sizeof("TERT_MI2S_RX"))) {
  2031. idx = TERT_MI2S;
  2032. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2033. sizeof("QUAT_MI2S_RX"))) {
  2034. idx = QUAT_MI2S;
  2035. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2036. sizeof("QUIN_MI2S_RX"))) {
  2037. idx = QUIN_MI2S;
  2038. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2039. sizeof("SEN_MI2S_RX"))) {
  2040. idx = SEN_MI2S;
  2041. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2042. sizeof("PRIM_MI2S_TX"))) {
  2043. idx = PRIM_MI2S;
  2044. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2045. sizeof("SEC_MI2S_TX"))) {
  2046. idx = SEC_MI2S;
  2047. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2048. sizeof("TERT_MI2S_TX"))) {
  2049. idx = TERT_MI2S;
  2050. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2051. sizeof("QUAT_MI2S_TX"))) {
  2052. idx = QUAT_MI2S;
  2053. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2054. sizeof("QUIN_MI2S_TX"))) {
  2055. idx = QUIN_MI2S;
  2056. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2057. sizeof("SEN_MI2S_TX"))) {
  2058. idx = SEN_MI2S;
  2059. } else {
  2060. pr_err("%s: unsupported channel: %s\n",
  2061. __func__, kcontrol->id.name);
  2062. idx = -EINVAL;
  2063. }
  2064. return idx;
  2065. }
  2066. static int mi2s_get_sample_rate(int value)
  2067. {
  2068. int sample_rate = 0;
  2069. switch (value) {
  2070. case 0:
  2071. sample_rate = SAMPLING_RATE_8KHZ;
  2072. break;
  2073. case 1:
  2074. sample_rate = SAMPLING_RATE_11P025KHZ;
  2075. break;
  2076. case 2:
  2077. sample_rate = SAMPLING_RATE_16KHZ;
  2078. break;
  2079. case 3:
  2080. sample_rate = SAMPLING_RATE_22P05KHZ;
  2081. break;
  2082. case 4:
  2083. sample_rate = SAMPLING_RATE_32KHZ;
  2084. break;
  2085. case 5:
  2086. sample_rate = SAMPLING_RATE_44P1KHZ;
  2087. break;
  2088. case 6:
  2089. sample_rate = SAMPLING_RATE_48KHZ;
  2090. break;
  2091. case 7:
  2092. sample_rate = SAMPLING_RATE_88P2KHZ;
  2093. break;
  2094. case 8:
  2095. sample_rate = SAMPLING_RATE_96KHZ;
  2096. break;
  2097. case 9:
  2098. sample_rate = SAMPLING_RATE_176P4KHZ;
  2099. break;
  2100. case 10:
  2101. sample_rate = SAMPLING_RATE_192KHZ;
  2102. break;
  2103. case 11:
  2104. sample_rate = SAMPLING_RATE_352P8KHZ;
  2105. break;
  2106. case 12:
  2107. sample_rate = SAMPLING_RATE_384KHZ;
  2108. break;
  2109. default:
  2110. sample_rate = SAMPLING_RATE_48KHZ;
  2111. break;
  2112. }
  2113. return sample_rate;
  2114. }
  2115. static int mi2s_get_sample_rate_val(int sample_rate)
  2116. {
  2117. int sample_rate_val = 0;
  2118. switch (sample_rate) {
  2119. case SAMPLING_RATE_8KHZ:
  2120. sample_rate_val = 0;
  2121. break;
  2122. case SAMPLING_RATE_11P025KHZ:
  2123. sample_rate_val = 1;
  2124. break;
  2125. case SAMPLING_RATE_16KHZ:
  2126. sample_rate_val = 2;
  2127. break;
  2128. case SAMPLING_RATE_22P05KHZ:
  2129. sample_rate_val = 3;
  2130. break;
  2131. case SAMPLING_RATE_32KHZ:
  2132. sample_rate_val = 4;
  2133. break;
  2134. case SAMPLING_RATE_44P1KHZ:
  2135. sample_rate_val = 5;
  2136. break;
  2137. case SAMPLING_RATE_48KHZ:
  2138. sample_rate_val = 6;
  2139. break;
  2140. case SAMPLING_RATE_88P2KHZ:
  2141. sample_rate_val = 7;
  2142. break;
  2143. case SAMPLING_RATE_96KHZ:
  2144. sample_rate_val = 8;
  2145. break;
  2146. case SAMPLING_RATE_176P4KHZ:
  2147. sample_rate_val = 9;
  2148. break;
  2149. case SAMPLING_RATE_192KHZ:
  2150. sample_rate_val = 10;
  2151. break;
  2152. case SAMPLING_RATE_352P8KHZ:
  2153. sample_rate_val = 11;
  2154. break;
  2155. case SAMPLING_RATE_384KHZ:
  2156. sample_rate_val = 12;
  2157. break;
  2158. default:
  2159. sample_rate_val = 6;
  2160. break;
  2161. }
  2162. return sample_rate_val;
  2163. }
  2164. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2165. struct snd_ctl_elem_value *ucontrol)
  2166. {
  2167. int idx = mi2s_get_port_idx(kcontrol);
  2168. if (idx < 0)
  2169. return idx;
  2170. ucontrol->value.enumerated.item[0] =
  2171. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2172. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2173. idx, mi2s_rx_cfg[idx].sample_rate,
  2174. ucontrol->value.enumerated.item[0]);
  2175. return 0;
  2176. }
  2177. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2178. struct snd_ctl_elem_value *ucontrol)
  2179. {
  2180. int idx = mi2s_get_port_idx(kcontrol);
  2181. if (idx < 0)
  2182. return idx;
  2183. mi2s_rx_cfg[idx].sample_rate =
  2184. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2185. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2186. idx, mi2s_rx_cfg[idx].sample_rate,
  2187. ucontrol->value.enumerated.item[0]);
  2188. return 0;
  2189. }
  2190. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2191. struct snd_ctl_elem_value *ucontrol)
  2192. {
  2193. int idx = mi2s_get_port_idx(kcontrol);
  2194. if (idx < 0)
  2195. return idx;
  2196. ucontrol->value.enumerated.item[0] =
  2197. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2198. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2199. idx, mi2s_tx_cfg[idx].sample_rate,
  2200. ucontrol->value.enumerated.item[0]);
  2201. return 0;
  2202. }
  2203. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2204. struct snd_ctl_elem_value *ucontrol)
  2205. {
  2206. int idx = mi2s_get_port_idx(kcontrol);
  2207. if (idx < 0)
  2208. return idx;
  2209. mi2s_tx_cfg[idx].sample_rate =
  2210. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2211. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2212. idx, mi2s_tx_cfg[idx].sample_rate,
  2213. ucontrol->value.enumerated.item[0]);
  2214. return 0;
  2215. }
  2216. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2217. struct snd_ctl_elem_value *ucontrol)
  2218. {
  2219. int idx = mi2s_get_port_idx(kcontrol);
  2220. if (idx < 0)
  2221. return idx;
  2222. ucontrol->value.enumerated.item[0] =
  2223. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2224. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2225. idx, mi2s_rx_cfg[idx].bit_format,
  2226. ucontrol->value.enumerated.item[0]);
  2227. return 0;
  2228. }
  2229. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2230. struct snd_ctl_elem_value *ucontrol)
  2231. {
  2232. int idx = mi2s_get_port_idx(kcontrol);
  2233. if (idx < 0)
  2234. return idx;
  2235. mi2s_rx_cfg[idx].bit_format =
  2236. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2237. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2238. idx, mi2s_rx_cfg[idx].bit_format,
  2239. ucontrol->value.enumerated.item[0]);
  2240. return 0;
  2241. }
  2242. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2243. struct snd_ctl_elem_value *ucontrol)
  2244. {
  2245. int idx = mi2s_get_port_idx(kcontrol);
  2246. if (idx < 0)
  2247. return idx;
  2248. ucontrol->value.enumerated.item[0] =
  2249. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2250. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2251. idx, mi2s_tx_cfg[idx].bit_format,
  2252. ucontrol->value.enumerated.item[0]);
  2253. return 0;
  2254. }
  2255. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2256. struct snd_ctl_elem_value *ucontrol)
  2257. {
  2258. int idx = mi2s_get_port_idx(kcontrol);
  2259. if (idx < 0)
  2260. return idx;
  2261. mi2s_tx_cfg[idx].bit_format =
  2262. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2263. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2264. idx, mi2s_tx_cfg[idx].bit_format,
  2265. ucontrol->value.enumerated.item[0]);
  2266. return 0;
  2267. }
  2268. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2269. struct snd_ctl_elem_value *ucontrol)
  2270. {
  2271. int idx = mi2s_get_port_idx(kcontrol);
  2272. if (idx < 0)
  2273. return idx;
  2274. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2275. idx, mi2s_rx_cfg[idx].channels);
  2276. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2277. return 0;
  2278. }
  2279. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2280. struct snd_ctl_elem_value *ucontrol)
  2281. {
  2282. int idx = mi2s_get_port_idx(kcontrol);
  2283. if (idx < 0)
  2284. return idx;
  2285. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2286. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2287. idx, mi2s_rx_cfg[idx].channels);
  2288. return 1;
  2289. }
  2290. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2291. struct snd_ctl_elem_value *ucontrol)
  2292. {
  2293. int idx = mi2s_get_port_idx(kcontrol);
  2294. if (idx < 0)
  2295. return idx;
  2296. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2297. idx, mi2s_tx_cfg[idx].channels);
  2298. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2299. return 0;
  2300. }
  2301. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2302. struct snd_ctl_elem_value *ucontrol)
  2303. {
  2304. int idx = mi2s_get_port_idx(kcontrol);
  2305. if (idx < 0)
  2306. return idx;
  2307. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2308. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2309. idx, mi2s_tx_cfg[idx].channels);
  2310. return 1;
  2311. }
  2312. static int msm_get_port_id(int be_id)
  2313. {
  2314. int afe_port_id = 0;
  2315. switch (be_id) {
  2316. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2317. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2318. break;
  2319. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2320. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2321. break;
  2322. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2323. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2324. break;
  2325. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2326. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2327. break;
  2328. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2329. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2330. break;
  2331. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2332. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2333. break;
  2334. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2335. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2336. break;
  2337. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2338. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2339. break;
  2340. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2341. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  2342. break;
  2343. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2344. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  2345. break;
  2346. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  2347. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  2348. break;
  2349. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  2350. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  2351. break;
  2352. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2353. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  2354. break;
  2355. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2356. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_1;
  2357. break;
  2358. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2359. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_2;
  2360. break;
  2361. default:
  2362. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  2363. afe_port_id = -EINVAL;
  2364. }
  2365. return afe_port_id;
  2366. }
  2367. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2368. {
  2369. u32 bit_per_sample = 0;
  2370. switch (bit_format) {
  2371. case SNDRV_PCM_FORMAT_S32_LE:
  2372. case SNDRV_PCM_FORMAT_S24_3LE:
  2373. case SNDRV_PCM_FORMAT_S24_LE:
  2374. bit_per_sample = 32;
  2375. break;
  2376. case SNDRV_PCM_FORMAT_S16_LE:
  2377. default:
  2378. bit_per_sample = 16;
  2379. break;
  2380. }
  2381. return bit_per_sample;
  2382. }
  2383. static void update_mi2s_clk_val(int dai_id, int stream)
  2384. {
  2385. u32 bit_per_sample = 0;
  2386. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2387. bit_per_sample =
  2388. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2389. mi2s_clk[dai_id].clk_freq_in_hz =
  2390. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2391. } else {
  2392. bit_per_sample =
  2393. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2394. mi2s_clk[dai_id].clk_freq_in_hz =
  2395. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2396. }
  2397. }
  2398. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2399. {
  2400. int ret = 0;
  2401. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2402. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2403. int port_id = 0;
  2404. int index = cpu_dai->id;
  2405. port_id = msm_get_port_id(rtd->dai_link->id);
  2406. if (port_id < 0) {
  2407. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2408. ret = port_id;
  2409. goto err;
  2410. }
  2411. if (enable) {
  2412. update_mi2s_clk_val(index, substream->stream);
  2413. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2414. mi2s_clk[index].clk_freq_in_hz);
  2415. }
  2416. mi2s_clk[index].enable = enable;
  2417. ret = afe_set_lpass_clock_v2(port_id,
  2418. &mi2s_clk[index]);
  2419. if (ret < 0) {
  2420. dev_err(rtd->card->dev,
  2421. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2422. __func__, port_id, ret);
  2423. goto err;
  2424. }
  2425. err:
  2426. return ret;
  2427. }
  2428. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  2429. {
  2430. int idx = 0;
  2431. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  2432. sizeof("WSA_CDC_DMA_RX_0")))
  2433. idx = WSA_CDC_DMA_RX_0;
  2434. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  2435. sizeof("WSA_CDC_DMA_RX_0")))
  2436. idx = WSA_CDC_DMA_RX_1;
  2437. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  2438. sizeof("RX_CDC_DMA_RX_0")))
  2439. idx = RX_CDC_DMA_RX_0;
  2440. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  2441. sizeof("RX_CDC_DMA_RX_1")))
  2442. idx = RX_CDC_DMA_RX_1;
  2443. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  2444. sizeof("RX_CDC_DMA_RX_2")))
  2445. idx = RX_CDC_DMA_RX_2;
  2446. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  2447. sizeof("RX_CDC_DMA_RX_3")))
  2448. idx = RX_CDC_DMA_RX_3;
  2449. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  2450. sizeof("RX_CDC_DMA_RX_5")))
  2451. idx = RX_CDC_DMA_RX_5;
  2452. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  2453. sizeof("WSA_CDC_DMA_TX_0")))
  2454. idx = WSA_CDC_DMA_TX_0;
  2455. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  2456. sizeof("WSA_CDC_DMA_TX_1")))
  2457. idx = WSA_CDC_DMA_TX_1;
  2458. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  2459. sizeof("WSA_CDC_DMA_TX_2")))
  2460. idx = WSA_CDC_DMA_TX_2;
  2461. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  2462. sizeof("TX_CDC_DMA_TX_0")))
  2463. idx = TX_CDC_DMA_TX_0;
  2464. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  2465. sizeof("TX_CDC_DMA_TX_3")))
  2466. idx = TX_CDC_DMA_TX_3;
  2467. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  2468. sizeof("TX_CDC_DMA_TX_4")))
  2469. idx = TX_CDC_DMA_TX_4;
  2470. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  2471. sizeof("VA_CDC_DMA_TX_0")))
  2472. idx = VA_CDC_DMA_TX_0;
  2473. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  2474. sizeof("VA_CDC_DMA_TX_1")))
  2475. idx = VA_CDC_DMA_TX_1;
  2476. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  2477. sizeof("VA_CDC_DMA_TX_2")))
  2478. idx = VA_CDC_DMA_TX_2;
  2479. else {
  2480. pr_err("%s: unsupported channel: %s\n",
  2481. __func__, kcontrol->id.name);
  2482. return -EINVAL;
  2483. }
  2484. return idx;
  2485. }
  2486. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  2487. struct snd_ctl_elem_value *ucontrol)
  2488. {
  2489. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2490. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2491. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2492. return ch_num;
  2493. }
  2494. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2495. cdc_dma_rx_cfg[ch_num].channels - 1);
  2496. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  2497. return 0;
  2498. }
  2499. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  2500. struct snd_ctl_elem_value *ucontrol)
  2501. {
  2502. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2503. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2504. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2505. return ch_num;
  2506. }
  2507. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2508. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2509. cdc_dma_rx_cfg[ch_num].channels);
  2510. return 1;
  2511. }
  2512. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  2513. struct snd_ctl_elem_value *ucontrol)
  2514. {
  2515. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2516. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2517. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2518. return ch_num;
  2519. }
  2520. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  2521. case SNDRV_PCM_FORMAT_S32_LE:
  2522. ucontrol->value.integer.value[0] = 3;
  2523. break;
  2524. case SNDRV_PCM_FORMAT_S24_3LE:
  2525. ucontrol->value.integer.value[0] = 2;
  2526. break;
  2527. case SNDRV_PCM_FORMAT_S24_LE:
  2528. ucontrol->value.integer.value[0] = 1;
  2529. break;
  2530. case SNDRV_PCM_FORMAT_S16_LE:
  2531. default:
  2532. ucontrol->value.integer.value[0] = 0;
  2533. break;
  2534. }
  2535. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2536. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2537. ucontrol->value.integer.value[0]);
  2538. return 0;
  2539. }
  2540. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  2541. struct snd_ctl_elem_value *ucontrol)
  2542. {
  2543. int rc = 0;
  2544. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2545. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2546. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2547. return ch_num;
  2548. }
  2549. switch (ucontrol->value.integer.value[0]) {
  2550. case 3:
  2551. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2552. break;
  2553. case 2:
  2554. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2555. break;
  2556. case 1:
  2557. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2558. break;
  2559. case 0:
  2560. default:
  2561. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2562. break;
  2563. }
  2564. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2565. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2566. ucontrol->value.integer.value[0]);
  2567. return rc;
  2568. }
  2569. static int cdc_dma_get_sample_rate_val(int sample_rate)
  2570. {
  2571. int sample_rate_val = 0;
  2572. switch (sample_rate) {
  2573. case SAMPLING_RATE_8KHZ:
  2574. sample_rate_val = 0;
  2575. break;
  2576. case SAMPLING_RATE_11P025KHZ:
  2577. sample_rate_val = 1;
  2578. break;
  2579. case SAMPLING_RATE_16KHZ:
  2580. sample_rate_val = 2;
  2581. break;
  2582. case SAMPLING_RATE_22P05KHZ:
  2583. sample_rate_val = 3;
  2584. break;
  2585. case SAMPLING_RATE_32KHZ:
  2586. sample_rate_val = 4;
  2587. break;
  2588. case SAMPLING_RATE_44P1KHZ:
  2589. sample_rate_val = 5;
  2590. break;
  2591. case SAMPLING_RATE_48KHZ:
  2592. sample_rate_val = 6;
  2593. break;
  2594. case SAMPLING_RATE_88P2KHZ:
  2595. sample_rate_val = 7;
  2596. break;
  2597. case SAMPLING_RATE_96KHZ:
  2598. sample_rate_val = 8;
  2599. break;
  2600. case SAMPLING_RATE_176P4KHZ:
  2601. sample_rate_val = 9;
  2602. break;
  2603. case SAMPLING_RATE_192KHZ:
  2604. sample_rate_val = 10;
  2605. break;
  2606. case SAMPLING_RATE_352P8KHZ:
  2607. sample_rate_val = 11;
  2608. break;
  2609. case SAMPLING_RATE_384KHZ:
  2610. sample_rate_val = 12;
  2611. break;
  2612. default:
  2613. sample_rate_val = 6;
  2614. break;
  2615. }
  2616. return sample_rate_val;
  2617. }
  2618. static int cdc_dma_get_sample_rate(int value)
  2619. {
  2620. int sample_rate = 0;
  2621. switch (value) {
  2622. case 0:
  2623. sample_rate = SAMPLING_RATE_8KHZ;
  2624. break;
  2625. case 1:
  2626. sample_rate = SAMPLING_RATE_11P025KHZ;
  2627. break;
  2628. case 2:
  2629. sample_rate = SAMPLING_RATE_16KHZ;
  2630. break;
  2631. case 3:
  2632. sample_rate = SAMPLING_RATE_22P05KHZ;
  2633. break;
  2634. case 4:
  2635. sample_rate = SAMPLING_RATE_32KHZ;
  2636. break;
  2637. case 5:
  2638. sample_rate = SAMPLING_RATE_44P1KHZ;
  2639. break;
  2640. case 6:
  2641. sample_rate = SAMPLING_RATE_48KHZ;
  2642. break;
  2643. case 7:
  2644. sample_rate = SAMPLING_RATE_88P2KHZ;
  2645. break;
  2646. case 8:
  2647. sample_rate = SAMPLING_RATE_96KHZ;
  2648. break;
  2649. case 9:
  2650. sample_rate = SAMPLING_RATE_176P4KHZ;
  2651. break;
  2652. case 10:
  2653. sample_rate = SAMPLING_RATE_192KHZ;
  2654. break;
  2655. case 11:
  2656. sample_rate = SAMPLING_RATE_352P8KHZ;
  2657. break;
  2658. case 12:
  2659. sample_rate = SAMPLING_RATE_384KHZ;
  2660. break;
  2661. default:
  2662. sample_rate = SAMPLING_RATE_48KHZ;
  2663. break;
  2664. }
  2665. return sample_rate;
  2666. }
  2667. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2668. struct snd_ctl_elem_value *ucontrol)
  2669. {
  2670. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2671. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2672. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2673. return ch_num;
  2674. }
  2675. ucontrol->value.enumerated.item[0] =
  2676. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2677. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2678. cdc_dma_rx_cfg[ch_num].sample_rate);
  2679. return 0;
  2680. }
  2681. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2682. struct snd_ctl_elem_value *ucontrol)
  2683. {
  2684. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2685. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2686. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2687. return ch_num;
  2688. }
  2689. cdc_dma_rx_cfg[ch_num].sample_rate =
  2690. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2691. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2692. __func__, ucontrol->value.enumerated.item[0],
  2693. cdc_dma_rx_cfg[ch_num].sample_rate);
  2694. return 0;
  2695. }
  2696. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2697. struct snd_ctl_elem_value *ucontrol)
  2698. {
  2699. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2700. if (ch_num < 0) {
  2701. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2702. return ch_num;
  2703. }
  2704. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2705. cdc_dma_tx_cfg[ch_num].channels);
  2706. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2707. return 0;
  2708. }
  2709. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2710. struct snd_ctl_elem_value *ucontrol)
  2711. {
  2712. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2713. if (ch_num < 0) {
  2714. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2715. return ch_num;
  2716. }
  2717. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2718. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2719. cdc_dma_tx_cfg[ch_num].channels);
  2720. return 1;
  2721. }
  2722. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2723. struct snd_ctl_elem_value *ucontrol)
  2724. {
  2725. int sample_rate_val;
  2726. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2727. if (ch_num < 0) {
  2728. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2729. return ch_num;
  2730. }
  2731. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2732. case SAMPLING_RATE_384KHZ:
  2733. sample_rate_val = 12;
  2734. break;
  2735. case SAMPLING_RATE_352P8KHZ:
  2736. sample_rate_val = 11;
  2737. break;
  2738. case SAMPLING_RATE_192KHZ:
  2739. sample_rate_val = 10;
  2740. break;
  2741. case SAMPLING_RATE_176P4KHZ:
  2742. sample_rate_val = 9;
  2743. break;
  2744. case SAMPLING_RATE_96KHZ:
  2745. sample_rate_val = 8;
  2746. break;
  2747. case SAMPLING_RATE_88P2KHZ:
  2748. sample_rate_val = 7;
  2749. break;
  2750. case SAMPLING_RATE_48KHZ:
  2751. sample_rate_val = 6;
  2752. break;
  2753. case SAMPLING_RATE_44P1KHZ:
  2754. sample_rate_val = 5;
  2755. break;
  2756. case SAMPLING_RATE_32KHZ:
  2757. sample_rate_val = 4;
  2758. break;
  2759. case SAMPLING_RATE_22P05KHZ:
  2760. sample_rate_val = 3;
  2761. break;
  2762. case SAMPLING_RATE_16KHZ:
  2763. sample_rate_val = 2;
  2764. break;
  2765. case SAMPLING_RATE_11P025KHZ:
  2766. sample_rate_val = 1;
  2767. break;
  2768. case SAMPLING_RATE_8KHZ:
  2769. sample_rate_val = 0;
  2770. break;
  2771. default:
  2772. sample_rate_val = 6;
  2773. break;
  2774. }
  2775. ucontrol->value.integer.value[0] = sample_rate_val;
  2776. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2777. cdc_dma_tx_cfg[ch_num].sample_rate);
  2778. return 0;
  2779. }
  2780. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2781. struct snd_ctl_elem_value *ucontrol)
  2782. {
  2783. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2784. if (ch_num < 0) {
  2785. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2786. return ch_num;
  2787. }
  2788. switch (ucontrol->value.integer.value[0]) {
  2789. case 12:
  2790. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2791. break;
  2792. case 11:
  2793. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2794. break;
  2795. case 10:
  2796. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2797. break;
  2798. case 9:
  2799. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2800. break;
  2801. case 8:
  2802. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2803. break;
  2804. case 7:
  2805. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2806. break;
  2807. case 6:
  2808. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2809. break;
  2810. case 5:
  2811. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2812. break;
  2813. case 4:
  2814. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2815. break;
  2816. case 3:
  2817. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2818. break;
  2819. case 2:
  2820. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2821. break;
  2822. case 1:
  2823. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2824. break;
  2825. case 0:
  2826. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2827. break;
  2828. default:
  2829. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2830. break;
  2831. }
  2832. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2833. __func__, ucontrol->value.integer.value[0],
  2834. cdc_dma_tx_cfg[ch_num].sample_rate);
  2835. return 0;
  2836. }
  2837. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2838. struct snd_ctl_elem_value *ucontrol)
  2839. {
  2840. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2841. if (ch_num < 0) {
  2842. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2843. return ch_num;
  2844. }
  2845. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2846. case SNDRV_PCM_FORMAT_S32_LE:
  2847. ucontrol->value.integer.value[0] = 3;
  2848. break;
  2849. case SNDRV_PCM_FORMAT_S24_3LE:
  2850. ucontrol->value.integer.value[0] = 2;
  2851. break;
  2852. case SNDRV_PCM_FORMAT_S24_LE:
  2853. ucontrol->value.integer.value[0] = 1;
  2854. break;
  2855. case SNDRV_PCM_FORMAT_S16_LE:
  2856. default:
  2857. ucontrol->value.integer.value[0] = 0;
  2858. break;
  2859. }
  2860. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2861. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2862. ucontrol->value.integer.value[0]);
  2863. return 0;
  2864. }
  2865. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2866. struct snd_ctl_elem_value *ucontrol)
  2867. {
  2868. int rc = 0;
  2869. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2870. if (ch_num < 0) {
  2871. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2872. return ch_num;
  2873. }
  2874. switch (ucontrol->value.integer.value[0]) {
  2875. case 3:
  2876. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2877. break;
  2878. case 2:
  2879. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2880. break;
  2881. case 1:
  2882. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2883. break;
  2884. case 0:
  2885. default:
  2886. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2887. break;
  2888. }
  2889. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2890. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2891. ucontrol->value.integer.value[0]);
  2892. return rc;
  2893. }
  2894. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2895. {
  2896. int idx = 0;
  2897. switch (be_id) {
  2898. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  2899. idx = WSA_CDC_DMA_RX_0;
  2900. break;
  2901. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  2902. idx = WSA_CDC_DMA_TX_0;
  2903. break;
  2904. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  2905. idx = WSA_CDC_DMA_RX_1;
  2906. break;
  2907. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  2908. idx = WSA_CDC_DMA_TX_1;
  2909. break;
  2910. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  2911. idx = WSA_CDC_DMA_TX_2;
  2912. break;
  2913. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2914. idx = RX_CDC_DMA_RX_0;
  2915. break;
  2916. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2917. idx = RX_CDC_DMA_RX_1;
  2918. break;
  2919. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2920. idx = RX_CDC_DMA_RX_2;
  2921. break;
  2922. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2923. idx = RX_CDC_DMA_RX_3;
  2924. break;
  2925. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2926. idx = RX_CDC_DMA_RX_5;
  2927. break;
  2928. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2929. idx = TX_CDC_DMA_TX_0;
  2930. break;
  2931. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2932. idx = TX_CDC_DMA_TX_3;
  2933. break;
  2934. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2935. idx = TX_CDC_DMA_TX_4;
  2936. break;
  2937. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2938. idx = VA_CDC_DMA_TX_0;
  2939. break;
  2940. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2941. idx = VA_CDC_DMA_TX_1;
  2942. break;
  2943. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2944. idx = VA_CDC_DMA_TX_2;
  2945. break;
  2946. default:
  2947. idx = RX_CDC_DMA_RX_0;
  2948. break;
  2949. }
  2950. return idx;
  2951. }
  2952. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2953. struct snd_ctl_elem_value *ucontrol)
  2954. {
  2955. /*
  2956. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2957. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2958. * value.
  2959. */
  2960. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2961. case SAMPLING_RATE_96KHZ:
  2962. ucontrol->value.integer.value[0] = 5;
  2963. break;
  2964. case SAMPLING_RATE_88P2KHZ:
  2965. ucontrol->value.integer.value[0] = 4;
  2966. break;
  2967. case SAMPLING_RATE_48KHZ:
  2968. ucontrol->value.integer.value[0] = 3;
  2969. break;
  2970. case SAMPLING_RATE_44P1KHZ:
  2971. ucontrol->value.integer.value[0] = 2;
  2972. break;
  2973. case SAMPLING_RATE_16KHZ:
  2974. ucontrol->value.integer.value[0] = 1;
  2975. break;
  2976. case SAMPLING_RATE_8KHZ:
  2977. default:
  2978. ucontrol->value.integer.value[0] = 0;
  2979. break;
  2980. }
  2981. pr_debug("%s: sample rate = %d\n", __func__,
  2982. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2983. return 0;
  2984. }
  2985. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2986. struct snd_ctl_elem_value *ucontrol)
  2987. {
  2988. switch (ucontrol->value.integer.value[0]) {
  2989. case 1:
  2990. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2991. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2992. break;
  2993. case 2:
  2994. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2995. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2996. break;
  2997. case 3:
  2998. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2999. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  3000. break;
  3001. case 4:
  3002. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  3003. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  3004. break;
  3005. case 5:
  3006. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  3007. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  3008. break;
  3009. case 0:
  3010. default:
  3011. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  3012. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  3013. break;
  3014. }
  3015. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  3016. __func__,
  3017. slim_rx_cfg[SLIM_RX_7].sample_rate,
  3018. slim_tx_cfg[SLIM_TX_7].sample_rate,
  3019. ucontrol->value.enumerated.item[0]);
  3020. return 0;
  3021. }
  3022. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  3023. struct snd_ctl_elem_value *ucontrol)
  3024. {
  3025. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  3026. case SAMPLING_RATE_96KHZ:
  3027. ucontrol->value.integer.value[0] = 5;
  3028. break;
  3029. case SAMPLING_RATE_88P2KHZ:
  3030. ucontrol->value.integer.value[0] = 4;
  3031. break;
  3032. case SAMPLING_RATE_48KHZ:
  3033. ucontrol->value.integer.value[0] = 3;
  3034. break;
  3035. case SAMPLING_RATE_44P1KHZ:
  3036. ucontrol->value.integer.value[0] = 2;
  3037. break;
  3038. case SAMPLING_RATE_16KHZ:
  3039. ucontrol->value.integer.value[0] = 1;
  3040. break;
  3041. case SAMPLING_RATE_8KHZ:
  3042. default:
  3043. ucontrol->value.integer.value[0] = 0;
  3044. break;
  3045. }
  3046. pr_debug("%s: sample rate rx = %d\n", __func__,
  3047. slim_rx_cfg[SLIM_RX_7].sample_rate);
  3048. return 0;
  3049. }
  3050. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  3051. struct snd_ctl_elem_value *ucontrol)
  3052. {
  3053. switch (ucontrol->value.integer.value[0]) {
  3054. case 1:
  3055. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  3056. break;
  3057. case 2:
  3058. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  3059. break;
  3060. case 3:
  3061. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  3062. break;
  3063. case 4:
  3064. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  3065. break;
  3066. case 5:
  3067. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  3068. break;
  3069. case 0:
  3070. default:
  3071. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  3072. break;
  3073. }
  3074. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  3075. __func__,
  3076. slim_rx_cfg[SLIM_RX_7].sample_rate,
  3077. ucontrol->value.enumerated.item[0]);
  3078. return 0;
  3079. }
  3080. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  3081. struct snd_ctl_elem_value *ucontrol)
  3082. {
  3083. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  3084. case SAMPLING_RATE_96KHZ:
  3085. ucontrol->value.integer.value[0] = 5;
  3086. break;
  3087. case SAMPLING_RATE_88P2KHZ:
  3088. ucontrol->value.integer.value[0] = 4;
  3089. break;
  3090. case SAMPLING_RATE_48KHZ:
  3091. ucontrol->value.integer.value[0] = 3;
  3092. break;
  3093. case SAMPLING_RATE_44P1KHZ:
  3094. ucontrol->value.integer.value[0] = 2;
  3095. break;
  3096. case SAMPLING_RATE_16KHZ:
  3097. ucontrol->value.integer.value[0] = 1;
  3098. break;
  3099. case SAMPLING_RATE_8KHZ:
  3100. default:
  3101. ucontrol->value.integer.value[0] = 0;
  3102. break;
  3103. }
  3104. pr_debug("%s: sample rate tx = %d\n", __func__,
  3105. slim_tx_cfg[SLIM_TX_7].sample_rate);
  3106. return 0;
  3107. }
  3108. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  3109. struct snd_ctl_elem_value *ucontrol)
  3110. {
  3111. switch (ucontrol->value.integer.value[0]) {
  3112. case 1:
  3113. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  3114. break;
  3115. case 2:
  3116. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  3117. break;
  3118. case 3:
  3119. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  3120. break;
  3121. case 4:
  3122. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  3123. break;
  3124. case 5:
  3125. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  3126. break;
  3127. case 0:
  3128. default:
  3129. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  3130. break;
  3131. }
  3132. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  3133. __func__,
  3134. slim_tx_cfg[SLIM_TX_7].sample_rate,
  3135. ucontrol->value.enumerated.item[0]);
  3136. return 0;
  3137. }
  3138. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  3139. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  3140. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3141. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  3142. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3143. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  3144. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3145. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  3146. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3147. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  3148. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3149. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  3150. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3151. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  3152. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3153. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  3154. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3155. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  3156. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3157. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  3158. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3159. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  3160. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3161. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  3162. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3163. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  3164. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3165. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  3166. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3167. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  3168. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3169. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  3170. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3171. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  3172. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3173. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  3174. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3175. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  3176. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3177. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  3178. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3179. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  3180. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3181. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  3182. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3183. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  3184. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3185. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  3186. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3187. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  3188. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3189. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  3190. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3191. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  3192. wsa_cdc_dma_rx_0_sample_rate,
  3193. cdc_dma_rx_sample_rate_get,
  3194. cdc_dma_rx_sample_rate_put),
  3195. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  3196. wsa_cdc_dma_rx_1_sample_rate,
  3197. cdc_dma_rx_sample_rate_get,
  3198. cdc_dma_rx_sample_rate_put),
  3199. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  3200. wsa_cdc_dma_tx_0_sample_rate,
  3201. cdc_dma_tx_sample_rate_get,
  3202. cdc_dma_tx_sample_rate_put),
  3203. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  3204. wsa_cdc_dma_tx_1_sample_rate,
  3205. cdc_dma_tx_sample_rate_get,
  3206. cdc_dma_tx_sample_rate_put),
  3207. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  3208. wsa_cdc_dma_tx_2_sample_rate,
  3209. cdc_dma_tx_sample_rate_get,
  3210. cdc_dma_tx_sample_rate_put),
  3211. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  3212. tx_cdc_dma_tx_0_sample_rate,
  3213. cdc_dma_tx_sample_rate_get,
  3214. cdc_dma_tx_sample_rate_put),
  3215. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  3216. tx_cdc_dma_tx_3_sample_rate,
  3217. cdc_dma_tx_sample_rate_get,
  3218. cdc_dma_tx_sample_rate_put),
  3219. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  3220. tx_cdc_dma_tx_4_sample_rate,
  3221. cdc_dma_tx_sample_rate_get,
  3222. cdc_dma_tx_sample_rate_put),
  3223. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3224. va_cdc_dma_tx_0_sample_rate,
  3225. cdc_dma_tx_sample_rate_get,
  3226. cdc_dma_tx_sample_rate_put),
  3227. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3228. va_cdc_dma_tx_1_sample_rate,
  3229. cdc_dma_tx_sample_rate_get,
  3230. cdc_dma_tx_sample_rate_put),
  3231. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  3232. va_cdc_dma_tx_2_sample_rate,
  3233. cdc_dma_tx_sample_rate_get,
  3234. cdc_dma_tx_sample_rate_put),
  3235. };
  3236. static const struct snd_kcontrol_new msm_int_wcd9380_snd_controls[] = {
  3237. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc80_dma_rx_0_format,
  3238. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3239. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc80_dma_rx_1_format,
  3240. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3241. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc80_dma_rx_2_format,
  3242. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3243. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc80_dma_rx_3_format,
  3244. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3245. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc80_dma_rx_5_format,
  3246. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3247. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  3248. rx_cdc80_dma_rx_0_sample_rate,
  3249. cdc_dma_rx_sample_rate_get,
  3250. cdc_dma_rx_sample_rate_put),
  3251. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  3252. rx_cdc80_dma_rx_1_sample_rate,
  3253. cdc_dma_rx_sample_rate_get,
  3254. cdc_dma_rx_sample_rate_put),
  3255. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  3256. rx_cdc80_dma_rx_2_sample_rate,
  3257. cdc_dma_rx_sample_rate_get,
  3258. cdc_dma_rx_sample_rate_put),
  3259. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  3260. rx_cdc80_dma_rx_3_sample_rate,
  3261. cdc_dma_rx_sample_rate_get,
  3262. cdc_dma_rx_sample_rate_put),
  3263. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  3264. rx_cdc80_dma_rx_5_sample_rate,
  3265. cdc_dma_rx_sample_rate_get,
  3266. cdc_dma_rx_sample_rate_put),
  3267. };
  3268. static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = {
  3269. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc85_dma_rx_0_format,
  3270. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3271. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc85_dma_rx_1_format,
  3272. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3273. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc85_dma_rx_2_format,
  3274. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3275. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc85_dma_rx_3_format,
  3276. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3277. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc85_dma_rx_5_format,
  3278. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3279. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  3280. rx_cdc85_dma_rx_0_sample_rate,
  3281. cdc_dma_rx_sample_rate_get,
  3282. cdc_dma_rx_sample_rate_put),
  3283. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  3284. rx_cdc85_dma_rx_1_sample_rate,
  3285. cdc_dma_rx_sample_rate_get,
  3286. cdc_dma_rx_sample_rate_put),
  3287. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  3288. rx_cdc85_dma_rx_2_sample_rate,
  3289. cdc_dma_rx_sample_rate_get,
  3290. cdc_dma_rx_sample_rate_put),
  3291. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  3292. rx_cdc85_dma_rx_3_sample_rate,
  3293. cdc_dma_rx_sample_rate_get,
  3294. cdc_dma_rx_sample_rate_put),
  3295. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  3296. rx_cdc85_dma_rx_5_sample_rate,
  3297. cdc_dma_rx_sample_rate_get,
  3298. cdc_dma_rx_sample_rate_put),
  3299. };
  3300. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  3301. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3302. usb_audio_rx_sample_rate_get,
  3303. usb_audio_rx_sample_rate_put),
  3304. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3305. usb_audio_tx_sample_rate_get,
  3306. usb_audio_tx_sample_rate_put),
  3307. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3308. tdm_rx_sample_rate_get,
  3309. tdm_rx_sample_rate_put),
  3310. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3311. tdm_rx_sample_rate_get,
  3312. tdm_rx_sample_rate_put),
  3313. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3314. tdm_rx_sample_rate_get,
  3315. tdm_rx_sample_rate_put),
  3316. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3317. tdm_rx_sample_rate_get,
  3318. tdm_rx_sample_rate_put),
  3319. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3320. tdm_rx_sample_rate_get,
  3321. tdm_rx_sample_rate_put),
  3322. SOC_ENUM_EXT("SEN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3323. tdm_rx_sample_rate_get,
  3324. tdm_rx_sample_rate_put),
  3325. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3326. tdm_tx_sample_rate_get,
  3327. tdm_tx_sample_rate_put),
  3328. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3329. tdm_tx_sample_rate_get,
  3330. tdm_tx_sample_rate_put),
  3331. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3332. tdm_tx_sample_rate_get,
  3333. tdm_tx_sample_rate_put),
  3334. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3335. tdm_tx_sample_rate_get,
  3336. tdm_tx_sample_rate_put),
  3337. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3338. tdm_tx_sample_rate_get,
  3339. tdm_tx_sample_rate_put),
  3340. SOC_ENUM_EXT("SEN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3341. tdm_tx_sample_rate_get,
  3342. tdm_tx_sample_rate_put),
  3343. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3344. aux_pcm_rx_sample_rate_get,
  3345. aux_pcm_rx_sample_rate_put),
  3346. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3347. aux_pcm_rx_sample_rate_get,
  3348. aux_pcm_rx_sample_rate_put),
  3349. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3350. aux_pcm_rx_sample_rate_get,
  3351. aux_pcm_rx_sample_rate_put),
  3352. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3353. aux_pcm_rx_sample_rate_get,
  3354. aux_pcm_rx_sample_rate_put),
  3355. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3356. aux_pcm_rx_sample_rate_get,
  3357. aux_pcm_rx_sample_rate_put),
  3358. SOC_ENUM_EXT("SEN_AUX_PCM_RX SampleRate", sen_aux_pcm_rx_sample_rate,
  3359. aux_pcm_rx_sample_rate_get,
  3360. aux_pcm_rx_sample_rate_put),
  3361. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3362. aux_pcm_tx_sample_rate_get,
  3363. aux_pcm_tx_sample_rate_put),
  3364. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3365. aux_pcm_tx_sample_rate_get,
  3366. aux_pcm_tx_sample_rate_put),
  3367. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3368. aux_pcm_tx_sample_rate_get,
  3369. aux_pcm_tx_sample_rate_put),
  3370. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3371. aux_pcm_tx_sample_rate_get,
  3372. aux_pcm_tx_sample_rate_put),
  3373. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3374. aux_pcm_tx_sample_rate_get,
  3375. aux_pcm_tx_sample_rate_put),
  3376. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3377. aux_pcm_tx_sample_rate_get,
  3378. aux_pcm_tx_sample_rate_put),
  3379. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3380. mi2s_rx_sample_rate_get,
  3381. mi2s_rx_sample_rate_put),
  3382. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3383. mi2s_rx_sample_rate_get,
  3384. mi2s_rx_sample_rate_put),
  3385. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3386. mi2s_rx_sample_rate_get,
  3387. mi2s_rx_sample_rate_put),
  3388. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3389. mi2s_rx_sample_rate_get,
  3390. mi2s_rx_sample_rate_put),
  3391. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3392. mi2s_rx_sample_rate_get,
  3393. mi2s_rx_sample_rate_put),
  3394. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3395. mi2s_rx_sample_rate_get,
  3396. mi2s_rx_sample_rate_put),
  3397. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3398. mi2s_tx_sample_rate_get,
  3399. mi2s_tx_sample_rate_put),
  3400. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3401. mi2s_tx_sample_rate_get,
  3402. mi2s_tx_sample_rate_put),
  3403. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3404. mi2s_tx_sample_rate_get,
  3405. mi2s_tx_sample_rate_put),
  3406. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3407. mi2s_tx_sample_rate_get,
  3408. mi2s_tx_sample_rate_put),
  3409. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3410. mi2s_tx_sample_rate_get,
  3411. mi2s_tx_sample_rate_put),
  3412. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3413. mi2s_tx_sample_rate_get,
  3414. mi2s_tx_sample_rate_put),
  3415. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3416. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3417. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3418. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3419. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3420. tdm_rx_format_get,
  3421. tdm_rx_format_put),
  3422. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3423. tdm_rx_format_get,
  3424. tdm_rx_format_put),
  3425. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3426. tdm_rx_format_get,
  3427. tdm_rx_format_put),
  3428. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3429. tdm_rx_format_get,
  3430. tdm_rx_format_put),
  3431. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3432. tdm_rx_format_get,
  3433. tdm_rx_format_put),
  3434. SOC_ENUM_EXT("SEN_TDM_RX_0 Format", tdm_rx_format,
  3435. tdm_rx_format_get,
  3436. tdm_rx_format_put),
  3437. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3438. tdm_tx_format_get,
  3439. tdm_tx_format_put),
  3440. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3441. tdm_tx_format_get,
  3442. tdm_tx_format_put),
  3443. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3444. tdm_tx_format_get,
  3445. tdm_tx_format_put),
  3446. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3447. tdm_tx_format_get,
  3448. tdm_tx_format_put),
  3449. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3450. tdm_tx_format_get,
  3451. tdm_tx_format_put),
  3452. SOC_ENUM_EXT("SEN_TDM_TX_0 Format", tdm_tx_format,
  3453. tdm_tx_format_get,
  3454. tdm_tx_format_put),
  3455. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3456. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3457. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3458. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3459. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3460. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3461. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3462. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3463. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3464. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3465. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3466. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3467. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3468. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3469. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3470. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3471. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3472. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3473. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3474. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3475. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3476. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3477. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3478. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3479. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3480. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3481. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3482. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3483. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3484. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3485. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3486. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3487. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3488. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3489. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3490. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3491. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3492. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3493. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3494. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3495. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3496. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3497. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3498. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3499. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3500. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3501. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3502. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3503. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3504. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3505. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3506. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3507. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3508. proxy_rx_ch_get, proxy_rx_ch_put),
  3509. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3510. tdm_rx_ch_get,
  3511. tdm_rx_ch_put),
  3512. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3513. tdm_rx_ch_get,
  3514. tdm_rx_ch_put),
  3515. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3516. tdm_rx_ch_get,
  3517. tdm_rx_ch_put),
  3518. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3519. tdm_rx_ch_get,
  3520. tdm_rx_ch_put),
  3521. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3522. tdm_rx_ch_get,
  3523. tdm_rx_ch_put),
  3524. SOC_ENUM_EXT("SEN_TDM_RX_0 Channels", tdm_rx_chs,
  3525. tdm_rx_ch_get,
  3526. tdm_rx_ch_put),
  3527. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3528. tdm_tx_ch_get,
  3529. tdm_tx_ch_put),
  3530. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3531. tdm_tx_ch_get,
  3532. tdm_tx_ch_put),
  3533. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3534. tdm_tx_ch_get,
  3535. tdm_tx_ch_put),
  3536. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3537. tdm_tx_ch_get,
  3538. tdm_tx_ch_put),
  3539. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3540. tdm_tx_ch_get,
  3541. tdm_tx_ch_put),
  3542. SOC_ENUM_EXT("SEN_TDM_TX_0 Channels", tdm_tx_chs,
  3543. tdm_tx_ch_get,
  3544. tdm_tx_ch_put),
  3545. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3546. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3547. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3548. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3549. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3550. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3551. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3552. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3553. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3554. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3555. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3556. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3557. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3558. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3559. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3560. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3561. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3562. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3563. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3564. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3565. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3566. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3567. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3568. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3569. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  3570. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  3571. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  3572. ext_disp_rx_format_get, ext_disp_rx_format_put),
  3573. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  3574. ext_disp_rx_sample_rate_get,
  3575. ext_disp_rx_sample_rate_put),
  3576. SOC_ENUM_EXT("Display Port1 RX Channels", ext_disp_rx_chs,
  3577. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  3578. SOC_ENUM_EXT("Display Port1 RX Bit Format", ext_disp_rx_format,
  3579. ext_disp_rx_format_get, ext_disp_rx_format_put),
  3580. SOC_ENUM_EXT("Display Port1 RX SampleRate", ext_disp_rx_sample_rate,
  3581. ext_disp_rx_sample_rate_get,
  3582. ext_disp_rx_sample_rate_put),
  3583. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3584. msm_bt_sample_rate_get,
  3585. msm_bt_sample_rate_put),
  3586. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  3587. msm_bt_sample_rate_rx_get,
  3588. msm_bt_sample_rate_rx_put),
  3589. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  3590. msm_bt_sample_rate_tx_get,
  3591. msm_bt_sample_rate_tx_put),
  3592. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  3593. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  3594. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3595. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3596. SOC_SINGLE_MULTI_EXT("TDM Slot Map", SND_SOC_NOPM, 0, 255, 0,
  3597. TDM_MAX_SLOTS + MAX_PATH, NULL, tdm_slot_map_put),
  3598. };
  3599. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3600. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3601. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3602. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3603. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3604. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3605. aux_pcm_rx_sample_rate_get,
  3606. aux_pcm_rx_sample_rate_put),
  3607. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3608. aux_pcm_tx_sample_rate_get,
  3609. aux_pcm_tx_sample_rate_put),
  3610. };
  3611. static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
  3612. {
  3613. int idx;
  3614. switch (be_id) {
  3615. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3616. idx = EXT_DISP_RX_IDX_DP;
  3617. break;
  3618. case MSM_BACKEND_DAI_DISPLAY_PORT_RX_1:
  3619. idx = EXT_DISP_RX_IDX_DP1;
  3620. break;
  3621. default:
  3622. pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
  3623. idx = -EINVAL;
  3624. break;
  3625. }
  3626. return idx;
  3627. }
  3628. static int kona_send_island_va_config(int32_t be_id)
  3629. {
  3630. int rc = 0;
  3631. int port_id = 0xFFFF;
  3632. port_id = msm_get_port_id(be_id);
  3633. if (port_id < 0) {
  3634. pr_err("%s: Invalid island interface, be_id: %d\n",
  3635. __func__, be_id);
  3636. rc = -EINVAL;
  3637. } else {
  3638. /*
  3639. * send island mode config
  3640. * This should be the first configuration
  3641. */
  3642. rc = afe_send_port_island_mode(port_id);
  3643. if (rc)
  3644. pr_err("%s: afe send island mode failed %d\n",
  3645. __func__, rc);
  3646. }
  3647. return rc;
  3648. }
  3649. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3650. struct snd_pcm_hw_params *params)
  3651. {
  3652. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3653. struct snd_interval *rate = hw_param_interval(params,
  3654. SNDRV_PCM_HW_PARAM_RATE);
  3655. struct snd_interval *channels = hw_param_interval(params,
  3656. SNDRV_PCM_HW_PARAM_CHANNELS);
  3657. int idx = 0, rc = 0;
  3658. pr_debug("%s: dai_id= %d, format = %d, rate = %d\n",
  3659. __func__, dai_link->id, params_format(params),
  3660. params_rate(params));
  3661. switch (dai_link->id) {
  3662. case MSM_BACKEND_DAI_USB_RX:
  3663. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3664. usb_rx_cfg.bit_format);
  3665. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3666. channels->min = channels->max = usb_rx_cfg.channels;
  3667. break;
  3668. case MSM_BACKEND_DAI_USB_TX:
  3669. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3670. usb_tx_cfg.bit_format);
  3671. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3672. channels->min = channels->max = usb_tx_cfg.channels;
  3673. break;
  3674. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3675. case MSM_BACKEND_DAI_DISPLAY_PORT_RX_1:
  3676. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  3677. if (idx < 0) {
  3678. pr_err("%s: Incorrect ext disp idx %d\n",
  3679. __func__, idx);
  3680. rc = idx;
  3681. goto done;
  3682. }
  3683. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3684. ext_disp_rx_cfg[idx].bit_format);
  3685. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  3686. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  3687. break;
  3688. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3689. channels->min = channels->max = proxy_rx_cfg.channels;
  3690. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3691. break;
  3692. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3693. channels->min = channels->max =
  3694. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3695. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3696. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3697. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3698. break;
  3699. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3700. channels->min = channels->max =
  3701. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3702. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3703. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3704. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3705. break;
  3706. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3707. channels->min = channels->max =
  3708. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3709. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3710. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3711. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3712. break;
  3713. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3714. channels->min = channels->max =
  3715. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3716. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3717. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3718. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3719. break;
  3720. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3721. channels->min = channels->max =
  3722. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3723. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3724. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3725. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3726. break;
  3727. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3728. channels->min = channels->max =
  3729. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3730. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3731. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3732. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3733. break;
  3734. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3735. channels->min = channels->max =
  3736. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3737. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3738. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3739. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3740. break;
  3741. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3742. channels->min = channels->max =
  3743. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3744. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3745. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3746. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3747. break;
  3748. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3749. channels->min = channels->max =
  3750. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3751. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3752. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3753. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3754. break;
  3755. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3756. channels->min = channels->max =
  3757. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3758. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3759. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3760. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3761. break;
  3762. case MSM_BACKEND_DAI_SEN_TDM_RX_0:
  3763. channels->min = channels->max =
  3764. tdm_rx_cfg[TDM_SEN][TDM_0].channels;
  3765. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3766. tdm_rx_cfg[TDM_SEN][TDM_0].bit_format);
  3767. rate->min = rate->max = tdm_rx_cfg[TDM_SEN][TDM_0].sample_rate;
  3768. break;
  3769. case MSM_BACKEND_DAI_SEN_TDM_TX_0:
  3770. channels->min = channels->max =
  3771. tdm_tx_cfg[TDM_SEN][TDM_0].channels;
  3772. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3773. tdm_tx_cfg[TDM_SEN][TDM_0].bit_format);
  3774. rate->min = rate->max = tdm_tx_cfg[TDM_SEN][TDM_0].sample_rate;
  3775. break;
  3776. case MSM_BACKEND_DAI_AUXPCM_RX:
  3777. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3778. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3779. rate->min = rate->max =
  3780. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3781. channels->min = channels->max =
  3782. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3783. break;
  3784. case MSM_BACKEND_DAI_AUXPCM_TX:
  3785. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3786. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3787. rate->min = rate->max =
  3788. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3789. channels->min = channels->max =
  3790. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3791. break;
  3792. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3793. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3794. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3795. rate->min = rate->max =
  3796. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3797. channels->min = channels->max =
  3798. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3799. break;
  3800. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3801. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3802. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3803. rate->min = rate->max =
  3804. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3805. channels->min = channels->max =
  3806. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3807. break;
  3808. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3809. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3810. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3811. rate->min = rate->max =
  3812. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3813. channels->min = channels->max =
  3814. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3815. break;
  3816. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3817. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3818. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3819. rate->min = rate->max =
  3820. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3821. channels->min = channels->max =
  3822. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3823. break;
  3824. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3825. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3826. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3827. rate->min = rate->max =
  3828. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3829. channels->min = channels->max =
  3830. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3831. break;
  3832. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3833. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3834. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3835. rate->min = rate->max =
  3836. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3837. channels->min = channels->max =
  3838. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3839. break;
  3840. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3841. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3842. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3843. rate->min = rate->max =
  3844. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3845. channels->min = channels->max =
  3846. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3847. break;
  3848. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3849. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3850. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3851. rate->min = rate->max =
  3852. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3853. channels->min = channels->max =
  3854. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3855. break;
  3856. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3857. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3858. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3859. rate->min = rate->max =
  3860. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3861. channels->min = channels->max =
  3862. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3863. break;
  3864. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3865. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3866. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3867. rate->min = rate->max =
  3868. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3869. channels->min = channels->max =
  3870. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3871. break;
  3872. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3873. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3874. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3875. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3876. channels->min = channels->max =
  3877. mi2s_rx_cfg[PRIM_MI2S].channels;
  3878. break;
  3879. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3880. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3881. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3882. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3883. channels->min = channels->max =
  3884. mi2s_tx_cfg[PRIM_MI2S].channels;
  3885. break;
  3886. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3887. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3888. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3889. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3890. channels->min = channels->max =
  3891. mi2s_rx_cfg[SEC_MI2S].channels;
  3892. break;
  3893. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3894. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3895. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3896. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3897. channels->min = channels->max =
  3898. mi2s_tx_cfg[SEC_MI2S].channels;
  3899. break;
  3900. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3901. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3902. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3903. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3904. channels->min = channels->max =
  3905. mi2s_rx_cfg[TERT_MI2S].channels;
  3906. break;
  3907. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3908. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3909. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3910. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3911. channels->min = channels->max =
  3912. mi2s_tx_cfg[TERT_MI2S].channels;
  3913. break;
  3914. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3915. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3916. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3917. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3918. channels->min = channels->max =
  3919. mi2s_rx_cfg[QUAT_MI2S].channels;
  3920. break;
  3921. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3922. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3923. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3924. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3925. channels->min = channels->max =
  3926. mi2s_tx_cfg[QUAT_MI2S].channels;
  3927. break;
  3928. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3929. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3930. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3931. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3932. channels->min = channels->max =
  3933. mi2s_rx_cfg[QUIN_MI2S].channels;
  3934. break;
  3935. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3936. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3937. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3938. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3939. channels->min = channels->max =
  3940. mi2s_tx_cfg[QUIN_MI2S].channels;
  3941. break;
  3942. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3943. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3944. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3945. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  3946. channels->min = channels->max =
  3947. mi2s_rx_cfg[SEN_MI2S].channels;
  3948. break;
  3949. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  3950. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3951. mi2s_tx_cfg[SEN_MI2S].bit_format);
  3952. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  3953. channels->min = channels->max =
  3954. mi2s_tx_cfg[SEN_MI2S].channels;
  3955. break;
  3956. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3957. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3958. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3959. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3960. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3961. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3962. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3963. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3964. cdc_dma_rx_cfg[idx].bit_format);
  3965. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3966. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3967. break;
  3968. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3969. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3970. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3971. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3972. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3973. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3974. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3975. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3976. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3977. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3978. cdc_dma_tx_cfg[idx].bit_format);
  3979. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3980. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3981. break;
  3982. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3983. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3984. SNDRV_PCM_FORMAT_S32_LE);
  3985. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3986. channels->min = channels->max = msm_vi_feed_tx_ch;
  3987. break;
  3988. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3989. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3990. slim_rx_cfg[SLIM_RX_7].bit_format);
  3991. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3992. channels->min = channels->max =
  3993. slim_rx_cfg[SLIM_RX_7].channels;
  3994. break;
  3995. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3996. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3997. slim_tx_cfg[SLIM_TX_7].bit_format);
  3998. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3999. channels->min = channels->max =
  4000. slim_tx_cfg[SLIM_TX_7].channels;
  4001. break;
  4002. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  4003. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  4004. channels->min = channels->max =
  4005. slim_tx_cfg[SLIM_TX_8].channels;
  4006. break;
  4007. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  4008. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4009. afe_loopback_tx_cfg[idx].bit_format);
  4010. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  4011. channels->min = channels->max =
  4012. afe_loopback_tx_cfg[idx].channels;
  4013. break;
  4014. default:
  4015. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  4016. break;
  4017. }
  4018. done:
  4019. return rc;
  4020. }
  4021. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component, bool active)
  4022. {
  4023. struct snd_soc_card *card = component->card;
  4024. struct msm_asoc_mach_data *pdata =
  4025. snd_soc_card_get_drvdata(card);
  4026. if (!pdata->fsa_handle)
  4027. return false;
  4028. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  4029. }
  4030. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  4031. {
  4032. int value = 0;
  4033. bool ret = false;
  4034. struct snd_soc_card *card;
  4035. struct msm_asoc_mach_data *pdata;
  4036. if (!component) {
  4037. pr_err("%s component is NULL\n", __func__);
  4038. return false;
  4039. }
  4040. card = component->card;
  4041. pdata = snd_soc_card_get_drvdata(card);
  4042. if (!pdata)
  4043. return false;
  4044. if (wcd_mbhc_cfg.enable_usbc_analog)
  4045. return msm_usbc_swap_gnd_mic(component, active);
  4046. /* if usbc is not defined, swap using us_euro_gpio_p */
  4047. if (pdata->us_euro_gpio_p) {
  4048. value = msm_cdc_pinctrl_get_state(
  4049. pdata->us_euro_gpio_p);
  4050. if (value)
  4051. msm_cdc_pinctrl_select_sleep_state(
  4052. pdata->us_euro_gpio_p);
  4053. else
  4054. msm_cdc_pinctrl_select_active_state(
  4055. pdata->us_euro_gpio_p);
  4056. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  4057. __func__, value, !value);
  4058. ret = true;
  4059. }
  4060. return ret;
  4061. }
  4062. static int kona_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4063. struct snd_pcm_hw_params *params)
  4064. {
  4065. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4066. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4067. int ret = 0;
  4068. int slot_width = TDM_SLOT_WIDTH_BITS;
  4069. int channels, slots = TDM_MAX_SLOTS;
  4070. unsigned int slot_mask, rate, clk_freq;
  4071. unsigned int *slot_offset;
  4072. struct tdm_dev_config *config;
  4073. unsigned int path_dir = 0, interface = 0, channel_interface = 0;
  4074. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4075. if (cpu_dai->id < AFE_PORT_ID_TDM_PORT_RANGE_START) {
  4076. pr_err("%s: dai id 0x%x not supported\n",
  4077. __func__, cpu_dai->id);
  4078. return -EINVAL;
  4079. }
  4080. /* RX or TX */
  4081. path_dir = cpu_dai->id % MAX_PATH;
  4082. /* PRI, SEC, TERT, QUAT, QUIN, ... */
  4083. interface = (cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START)
  4084. / (MAX_PATH * TDM_PORT_MAX);
  4085. /* 0, 1, 2, .. 7 */
  4086. channel_interface =
  4087. ((cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START) / MAX_PATH)
  4088. % TDM_PORT_MAX;
  4089. pr_debug("%s: path dir: %u, interface %u, channel interface %u\n",
  4090. __func__, path_dir, interface, channel_interface);
  4091. config = ((struct tdm_dev_config *) tdm_cfg[interface]) +
  4092. (path_dir * TDM_PORT_MAX) + channel_interface;
  4093. slot_offset = config->tdm_slot_offset;
  4094. if (path_dir)
  4095. channels = tdm_tx_cfg[interface][channel_interface].channels;
  4096. else
  4097. channels = tdm_rx_cfg[interface][channel_interface].channels;
  4098. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4099. /*2 slot config - bits 0 and 1 set for the first two slots */
  4100. slot_mask = 0x0000FFFF >> (16 - slots);
  4101. pr_debug("%s: tdm rx slot_width %d slots %d slot_mask %x\n",
  4102. __func__, slot_width, slots, slot_mask);
  4103. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4104. slots, slot_width);
  4105. if (ret < 0) {
  4106. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4107. __func__, ret);
  4108. goto end;
  4109. }
  4110. pr_debug("%s: tdm rx channels: %d\n", __func__, channels);
  4111. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4112. 0, NULL, channels, slot_offset);
  4113. if (ret < 0) {
  4114. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4115. __func__, ret);
  4116. goto end;
  4117. }
  4118. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4119. /*2 slot config - bits 0 and 1 set for the first two slots */
  4120. slot_mask = 0x0000FFFF >> (16 - slots);
  4121. pr_debug("%s: tdm tx slot_width %d slots %d slot_mask %x\n",
  4122. __func__, slot_width, slots, slot_mask);
  4123. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4124. slots, slot_width);
  4125. if (ret < 0) {
  4126. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4127. __func__, ret);
  4128. goto end;
  4129. }
  4130. pr_debug("%s: tdm tx channels: %d\n", __func__, channels);
  4131. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4132. channels, slot_offset, 0, NULL);
  4133. if (ret < 0) {
  4134. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4135. __func__, ret);
  4136. goto end;
  4137. }
  4138. } else {
  4139. ret = -EINVAL;
  4140. pr_err("%s: invalid use case, err:%d\n",
  4141. __func__, ret);
  4142. goto end;
  4143. }
  4144. rate = params_rate(params);
  4145. clk_freq = rate * slot_width * slots;
  4146. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4147. if (ret < 0)
  4148. pr_err("%s: failed to set tdm clk, err:%d\n",
  4149. __func__, ret);
  4150. end:
  4151. return ret;
  4152. }
  4153. static int msm_get_tdm_mode(u32 port_id)
  4154. {
  4155. int tdm_mode;
  4156. switch (port_id) {
  4157. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4158. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4159. tdm_mode = TDM_PRI;
  4160. break;
  4161. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4162. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4163. tdm_mode = TDM_SEC;
  4164. break;
  4165. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4166. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4167. tdm_mode = TDM_TERT;
  4168. break;
  4169. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4170. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4171. tdm_mode = TDM_QUAT;
  4172. break;
  4173. case AFE_PORT_ID_QUINARY_TDM_RX:
  4174. case AFE_PORT_ID_QUINARY_TDM_TX:
  4175. tdm_mode = TDM_QUIN;
  4176. break;
  4177. case AFE_PORT_ID_SENARY_TDM_RX:
  4178. case AFE_PORT_ID_SENARY_TDM_TX:
  4179. tdm_mode = TDM_SEN;
  4180. break;
  4181. default:
  4182. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  4183. tdm_mode = -EINVAL;
  4184. }
  4185. return tdm_mode;
  4186. }
  4187. static int kona_tdm_snd_startup(struct snd_pcm_substream *substream)
  4188. {
  4189. int ret = 0;
  4190. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4191. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4192. struct snd_soc_card *card = rtd->card;
  4193. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4194. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4195. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  4196. ret = -EINVAL;
  4197. pr_err("%s: Invalid TDM interface %d\n",
  4198. __func__, ret);
  4199. return ret;
  4200. }
  4201. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4202. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  4203. == 0) {
  4204. ret = msm_cdc_pinctrl_select_active_state(
  4205. pdata->mi2s_gpio_p[tdm_mode]);
  4206. if (ret) {
  4207. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  4208. __func__, ret);
  4209. goto done;
  4210. }
  4211. }
  4212. atomic_inc(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  4213. }
  4214. done:
  4215. return ret;
  4216. }
  4217. static void kona_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4218. {
  4219. int ret = 0;
  4220. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4221. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4222. struct snd_soc_card *card = rtd->card;
  4223. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4224. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  4225. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  4226. ret = -EINVAL;
  4227. pr_err("%s: Invalid TDM interface %d\n",
  4228. __func__, ret);
  4229. return;
  4230. }
  4231. if (pdata->mi2s_gpio_p[tdm_mode]) {
  4232. atomic_dec(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  4233. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  4234. == 0) {
  4235. ret = msm_cdc_pinctrl_select_sleep_state(
  4236. pdata->mi2s_gpio_p[tdm_mode]);
  4237. if (ret)
  4238. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  4239. __func__, ret);
  4240. }
  4241. }
  4242. }
  4243. static int kona_aux_snd_startup(struct snd_pcm_substream *substream)
  4244. {
  4245. int ret = 0;
  4246. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4247. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4248. struct snd_soc_card *card = rtd->card;
  4249. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4250. u32 aux_mode = cpu_dai->id - 1;
  4251. if (aux_mode >= AUX_PCM_MAX) {
  4252. ret = -EINVAL;
  4253. pr_err("%s: Invalid AUX interface %d\n",
  4254. __func__, ret);
  4255. return ret;
  4256. }
  4257. if (pdata->mi2s_gpio_p[aux_mode]) {
  4258. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  4259. == 0) {
  4260. ret = msm_cdc_pinctrl_select_active_state(
  4261. pdata->mi2s_gpio_p[aux_mode]);
  4262. if (ret) {
  4263. pr_err("%s: AUX GPIO pinctrl set active failed with %d\n",
  4264. __func__, ret);
  4265. goto done;
  4266. }
  4267. }
  4268. atomic_inc(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  4269. }
  4270. done:
  4271. return ret;
  4272. }
  4273. static void kona_aux_snd_shutdown(struct snd_pcm_substream *substream)
  4274. {
  4275. int ret = 0;
  4276. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4277. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4278. struct snd_soc_card *card = rtd->card;
  4279. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4280. u32 aux_mode = cpu_dai->id - 1;
  4281. if (aux_mode >= AUX_PCM_MAX) {
  4282. pr_err("%s: Invalid AUX interface %d\n",
  4283. __func__, ret);
  4284. return;
  4285. }
  4286. if (pdata->mi2s_gpio_p[aux_mode]) {
  4287. atomic_dec(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  4288. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  4289. == 0) {
  4290. ret = msm_cdc_pinctrl_select_sleep_state(
  4291. pdata->mi2s_gpio_p[aux_mode]);
  4292. if (ret)
  4293. pr_err("%s: AUX GPIO pinctrl set sleep failed with %d\n",
  4294. __func__, ret);
  4295. }
  4296. }
  4297. }
  4298. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  4299. {
  4300. int ret = 0;
  4301. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4302. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4303. switch (dai_link->id) {
  4304. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4305. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4306. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4307. ret = kona_send_island_va_config(dai_link->id);
  4308. if (ret)
  4309. pr_err("%s: send island va cfg failed, err: %d\n",
  4310. __func__, ret);
  4311. break;
  4312. }
  4313. return ret;
  4314. }
  4315. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4316. struct snd_pcm_hw_params *params)
  4317. {
  4318. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4319. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4320. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4321. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4322. int ret = 0;
  4323. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4324. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4325. u32 user_set_tx_ch = 0;
  4326. u32 user_set_rx_ch = 0;
  4327. u32 ch_id;
  4328. ret = snd_soc_dai_get_channel_map(codec_dai,
  4329. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4330. &rx_ch_cdc_dma);
  4331. if (ret < 0) {
  4332. pr_err("%s: failed to get codec chan map, err:%d\n",
  4333. __func__, ret);
  4334. goto err;
  4335. }
  4336. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4337. switch (dai_link->id) {
  4338. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4339. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4340. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  4341. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  4342. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  4343. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  4344. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  4345. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  4346. {
  4347. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4348. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4349. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4350. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4351. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4352. user_set_rx_ch, &rx_ch_cdc_dma);
  4353. if (ret < 0) {
  4354. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4355. __func__, ret);
  4356. goto err;
  4357. }
  4358. }
  4359. break;
  4360. }
  4361. } else {
  4362. switch (dai_link->id) {
  4363. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4364. {
  4365. user_set_tx_ch = msm_vi_feed_tx_ch;
  4366. }
  4367. break;
  4368. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4369. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4370. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  4371. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  4372. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  4373. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4374. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4375. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4376. {
  4377. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4378. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4379. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4380. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4381. }
  4382. break;
  4383. }
  4384. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4385. &tx_ch_cdc_dma, 0, 0);
  4386. if (ret < 0) {
  4387. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4388. __func__, ret);
  4389. goto err;
  4390. }
  4391. }
  4392. err:
  4393. return ret;
  4394. }
  4395. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4396. {
  4397. cpumask_t mask;
  4398. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4399. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4400. cpumask_clear(&mask);
  4401. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4402. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4403. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4404. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4405. pm_qos_add_request(&substream->latency_pm_qos_req,
  4406. PM_QOS_CPU_DMA_LATENCY,
  4407. MSM_LL_QOS_VALUE);
  4408. return 0;
  4409. }
  4410. void mi2s_disable_audio_vote(struct snd_pcm_substream *substream)
  4411. {
  4412. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4413. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4414. int index = cpu_dai->id;
  4415. struct snd_soc_card *card = rtd->card;
  4416. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4417. int sample_rate = 0;
  4418. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4419. sample_rate = mi2s_rx_cfg[index].sample_rate;
  4420. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4421. sample_rate = mi2s_tx_cfg[index].sample_rate;
  4422. } else {
  4423. pr_err("%s: invalid stream %d\n", __func__, substream->stream);
  4424. return;
  4425. }
  4426. if (IS_MSM_INTERFACE_MI2S(index) && IS_FRACTIONAL(sample_rate)) {
  4427. if (pdata->lpass_audio_hw_vote != NULL) {
  4428. if (--pdata->core_audio_vote_count == 0) {
  4429. clk_disable_unprepare(
  4430. pdata->lpass_audio_hw_vote);
  4431. } else if (pdata->core_audio_vote_count < 0) {
  4432. pr_err("%s: audio vote mismatch\n", __func__);
  4433. pdata->core_audio_vote_count = 0;
  4434. }
  4435. } else {
  4436. pr_err("%s: Invalid lpass audio hw node\n", __func__);
  4437. }
  4438. }
  4439. }
  4440. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4441. {
  4442. int ret = 0;
  4443. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4444. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4445. int index = cpu_dai->id;
  4446. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4447. struct snd_soc_card *card = rtd->card;
  4448. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4449. int sample_rate = 0;
  4450. dev_dbg(rtd->card->dev,
  4451. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4452. __func__, substream->name, substream->stream,
  4453. cpu_dai->name, cpu_dai->id);
  4454. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4455. ret = -EINVAL;
  4456. dev_err(rtd->card->dev,
  4457. "%s: CPU DAI id (%d) out of range\n",
  4458. __func__, cpu_dai->id);
  4459. goto err;
  4460. }
  4461. /*
  4462. * Mutex protection in case the same MI2S
  4463. * interface using for both TX and RX so
  4464. * that the same clock won't be enable twice.
  4465. */
  4466. mutex_lock(&mi2s_intf_conf[index].lock);
  4467. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4468. sample_rate = mi2s_rx_cfg[index].sample_rate;
  4469. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4470. sample_rate = mi2s_tx_cfg[index].sample_rate;
  4471. } else {
  4472. pr_err("%s: invalid stream %d\n", __func__, substream->stream);
  4473. ret = -EINVAL;
  4474. goto vote_err;
  4475. }
  4476. if (IS_MSM_INTERFACE_MI2S(index) && IS_FRACTIONAL(sample_rate)) {
  4477. if (pdata->lpass_audio_hw_vote == NULL) {
  4478. dev_err(rtd->card->dev, "%s: Invalid lpass audio hw node\n",
  4479. __func__);
  4480. ret = -EINVAL;
  4481. goto vote_err;
  4482. }
  4483. if (pdata->core_audio_vote_count == 0) {
  4484. ret = clk_prepare_enable(pdata->lpass_audio_hw_vote);
  4485. if (ret < 0) {
  4486. dev_err(rtd->card->dev, "%s: audio vote error\n",
  4487. __func__);
  4488. goto vote_err;
  4489. }
  4490. }
  4491. pdata->core_audio_vote_count++;
  4492. }
  4493. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4494. /* Check if msm needs to provide the clock to the interface */
  4495. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4496. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4497. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4498. }
  4499. ret = msm_mi2s_set_sclk(substream, true);
  4500. if (ret < 0) {
  4501. dev_err(rtd->card->dev,
  4502. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4503. __func__, ret);
  4504. goto clean_up;
  4505. }
  4506. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4507. if (ret < 0) {
  4508. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4509. __func__, index, ret);
  4510. goto clk_off;
  4511. }
  4512. if (pdata->mi2s_gpio_p[index]) {
  4513. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4514. == 0) {
  4515. ret = msm_cdc_pinctrl_select_active_state(
  4516. pdata->mi2s_gpio_p[index]);
  4517. if (ret) {
  4518. pr_err("%s: MI2S GPIO pinctrl set active failed with %d\n",
  4519. __func__, ret);
  4520. goto clk_off;
  4521. }
  4522. }
  4523. atomic_inc(&(pdata->mi2s_gpio_ref_count[index]));
  4524. }
  4525. }
  4526. clk_off:
  4527. if (ret < 0)
  4528. msm_mi2s_set_sclk(substream, false);
  4529. clean_up:
  4530. if (ret < 0) {
  4531. mi2s_intf_conf[index].ref_cnt--;
  4532. mi2s_disable_audio_vote(substream);
  4533. }
  4534. vote_err:
  4535. mutex_unlock(&mi2s_intf_conf[index].lock);
  4536. err:
  4537. return ret;
  4538. }
  4539. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4540. {
  4541. int ret = 0;
  4542. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4543. int index = rtd->cpu_dai->id;
  4544. struct snd_soc_card *card = rtd->card;
  4545. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4546. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4547. substream->name, substream->stream);
  4548. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4549. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4550. return;
  4551. }
  4552. mutex_lock(&mi2s_intf_conf[index].lock);
  4553. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4554. if (pdata->mi2s_gpio_p[index]) {
  4555. atomic_dec(&(pdata->mi2s_gpio_ref_count[index]));
  4556. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4557. == 0) {
  4558. ret = msm_cdc_pinctrl_select_sleep_state(
  4559. pdata->mi2s_gpio_p[index]);
  4560. if (ret)
  4561. pr_err("%s: MI2S GPIO pinctrl set sleep failed with %d\n",
  4562. __func__, ret);
  4563. }
  4564. }
  4565. ret = msm_mi2s_set_sclk(substream, false);
  4566. if (ret < 0)
  4567. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4568. __func__, index, ret);
  4569. }
  4570. mi2s_disable_audio_vote(substream);
  4571. mutex_unlock(&mi2s_intf_conf[index].lock);
  4572. }
  4573. static int msm_wcn_hw_params_lito(struct snd_pcm_substream *substream,
  4574. struct snd_pcm_hw_params *params)
  4575. {
  4576. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4577. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4578. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4579. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4580. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO];
  4581. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4582. int ret = 0;
  4583. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4584. codec_dai->name, codec_dai->id);
  4585. ret = snd_soc_dai_get_channel_map(codec_dai,
  4586. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4587. if (ret) {
  4588. dev_err(rtd->dev,
  4589. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4590. __func__, ret);
  4591. goto err;
  4592. }
  4593. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4594. __func__, tx_ch_cnt, dai_link->id);
  4595. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4596. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4597. if (ret)
  4598. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4599. __func__, ret);
  4600. err:
  4601. return ret;
  4602. }
  4603. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4604. struct snd_pcm_hw_params *params)
  4605. {
  4606. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4607. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4608. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4609. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4610. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4611. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4612. int ret = 0;
  4613. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4614. codec_dai->name, codec_dai->id);
  4615. ret = snd_soc_dai_get_channel_map(codec_dai,
  4616. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4617. if (ret) {
  4618. dev_err(rtd->dev,
  4619. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4620. __func__, ret);
  4621. goto err;
  4622. }
  4623. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4624. __func__, tx_ch_cnt, dai_link->id);
  4625. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4626. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4627. if (ret)
  4628. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4629. __func__, ret);
  4630. err:
  4631. return ret;
  4632. }
  4633. static struct snd_soc_ops kona_aux_be_ops = {
  4634. .startup = kona_aux_snd_startup,
  4635. .shutdown = kona_aux_snd_shutdown
  4636. };
  4637. static struct snd_soc_ops kona_tdm_be_ops = {
  4638. .hw_params = kona_tdm_snd_hw_params,
  4639. .startup = kona_tdm_snd_startup,
  4640. .shutdown = kona_tdm_snd_shutdown
  4641. };
  4642. static struct snd_soc_ops msm_mi2s_be_ops = {
  4643. .startup = msm_mi2s_snd_startup,
  4644. .shutdown = msm_mi2s_snd_shutdown,
  4645. };
  4646. static struct snd_soc_ops msm_fe_qos_ops = {
  4647. .prepare = msm_fe_qos_prepare,
  4648. };
  4649. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4650. .startup = msm_snd_cdc_dma_startup,
  4651. .hw_params = msm_snd_cdc_dma_hw_params,
  4652. };
  4653. static struct snd_soc_ops msm_wcn_ops = {
  4654. .hw_params = msm_wcn_hw_params,
  4655. };
  4656. static struct snd_soc_ops msm_wcn_ops_lito = {
  4657. .hw_params = msm_wcn_hw_params_lito,
  4658. };
  4659. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  4660. struct snd_kcontrol *kcontrol, int event)
  4661. {
  4662. struct msm_asoc_mach_data *pdata = NULL;
  4663. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  4664. int ret = 0;
  4665. u32 dmic_idx;
  4666. int *dmic_gpio_cnt;
  4667. struct device_node *dmic_gpio;
  4668. char *wname;
  4669. wname = strpbrk(w->name, "012345");
  4670. if (!wname) {
  4671. dev_err(component->dev, "%s: widget not found\n", __func__);
  4672. return -EINVAL;
  4673. }
  4674. ret = kstrtouint(wname, 10, &dmic_idx);
  4675. if (ret < 0) {
  4676. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  4677. __func__);
  4678. return -EINVAL;
  4679. }
  4680. pdata = snd_soc_card_get_drvdata(component->card);
  4681. switch (dmic_idx) {
  4682. case 0:
  4683. case 1:
  4684. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  4685. dmic_gpio = pdata->dmic01_gpio_p;
  4686. break;
  4687. case 2:
  4688. case 3:
  4689. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  4690. dmic_gpio = pdata->dmic23_gpio_p;
  4691. break;
  4692. case 4:
  4693. case 5:
  4694. dmic_gpio_cnt = &dmic_4_5_gpio_cnt;
  4695. dmic_gpio = pdata->dmic45_gpio_p;
  4696. break;
  4697. default:
  4698. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  4699. __func__);
  4700. return -EINVAL;
  4701. }
  4702. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  4703. __func__, event, dmic_idx, *dmic_gpio_cnt);
  4704. switch (event) {
  4705. case SND_SOC_DAPM_PRE_PMU:
  4706. (*dmic_gpio_cnt)++;
  4707. if (*dmic_gpio_cnt == 1) {
  4708. ret = msm_cdc_pinctrl_select_active_state(
  4709. dmic_gpio);
  4710. if (ret < 0) {
  4711. pr_err("%s: gpio set cannot be activated %sd",
  4712. __func__, "dmic_gpio");
  4713. return ret;
  4714. }
  4715. }
  4716. break;
  4717. case SND_SOC_DAPM_POST_PMD:
  4718. (*dmic_gpio_cnt)--;
  4719. if (*dmic_gpio_cnt == 0) {
  4720. ret = msm_cdc_pinctrl_select_sleep_state(
  4721. dmic_gpio);
  4722. if (ret < 0) {
  4723. pr_err("%s: gpio set cannot be de-activated %sd",
  4724. __func__, "dmic_gpio");
  4725. return ret;
  4726. }
  4727. }
  4728. break;
  4729. default:
  4730. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  4731. return -EINVAL;
  4732. }
  4733. return 0;
  4734. }
  4735. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  4736. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  4737. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  4738. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  4739. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  4740. SND_SOC_DAPM_MIC("Analog Mic5", NULL),
  4741. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  4742. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  4743. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  4744. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  4745. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  4746. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  4747. SND_SOC_DAPM_MIC("Digital Mic6", NULL),
  4748. SND_SOC_DAPM_MIC("Digital Mic7", NULL),
  4749. };
  4750. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4751. {
  4752. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4753. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160};
  4754. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4755. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4756. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4757. }
  4758. static int msm_wcn_init_lito(struct snd_soc_pcm_runtime *rtd)
  4759. {
  4760. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4761. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO] = {159, 160, 161};
  4762. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4763. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4764. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4765. }
  4766. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4767. {
  4768. int ret = -EINVAL;
  4769. struct snd_soc_component *component;
  4770. struct snd_soc_dapm_context *dapm;
  4771. struct snd_card *card;
  4772. struct snd_info_entry *entry;
  4773. struct snd_soc_component *aux_comp;
  4774. struct msm_asoc_mach_data *pdata =
  4775. snd_soc_card_get_drvdata(rtd->card);
  4776. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4777. if (!component) {
  4778. pr_err("%s: could not find component for bolero_codec\n",
  4779. __func__);
  4780. return ret;
  4781. }
  4782. dapm = snd_soc_component_get_dapm(component);
  4783. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  4784. ARRAY_SIZE(msm_int_snd_controls));
  4785. if (ret < 0) {
  4786. pr_err("%s: add_component_controls failed: %d\n",
  4787. __func__, ret);
  4788. return ret;
  4789. }
  4790. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  4791. ARRAY_SIZE(msm_common_snd_controls));
  4792. if (ret < 0) {
  4793. pr_err("%s: add common snd controls failed: %d\n",
  4794. __func__, ret);
  4795. return ret;
  4796. }
  4797. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  4798. ARRAY_SIZE(msm_int_dapm_widgets));
  4799. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4800. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4801. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4802. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4803. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4804. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4805. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4806. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4807. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  4808. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  4809. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4810. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4811. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
  4812. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4813. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4814. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4815. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4816. snd_soc_dapm_sync(dapm);
  4817. /*
  4818. * Send speaker configuration only for WSA8810.
  4819. * Default configuration is for WSA8815.
  4820. */
  4821. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4822. __func__, rtd->card->num_aux_devs);
  4823. if (rtd->card->num_aux_devs &&
  4824. !list_empty(&rtd->card->component_dev_list)) {
  4825. list_for_each_entry(aux_comp,
  4826. &rtd->card->aux_comp_list,
  4827. card_aux_list) {
  4828. if (aux_comp->name != NULL && (
  4829. !strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4830. !strcmp(aux_comp->name, WSA8810_NAME_2))) {
  4831. wsa_macro_set_spkr_mode(component,
  4832. WSA_MACRO_SPKR_MODE_1);
  4833. wsa_macro_set_spkr_gain_offset(component,
  4834. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4835. }
  4836. }
  4837. if (pdata->lito_v2_enabled) {
  4838. /*
  4839. * Enable tx data line3 for saipan version v2 amd
  4840. * write corresponding lpi register.
  4841. */
  4842. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map_v2),
  4843. sm_port_map_v2);
  4844. } else {
  4845. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map),
  4846. sm_port_map);
  4847. }
  4848. }
  4849. card = rtd->card->snd_card;
  4850. if (!pdata->codec_root) {
  4851. entry = snd_info_create_subdir(card->module, "codecs",
  4852. card->proc_root);
  4853. if (!entry) {
  4854. pr_debug("%s: Cannot create codecs module entry\n",
  4855. __func__);
  4856. ret = 0;
  4857. goto err;
  4858. }
  4859. pdata->codec_root = entry;
  4860. }
  4861. bolero_info_create_codec_entry(pdata->codec_root, component);
  4862. bolero_register_wake_irq(component, false);
  4863. codec_reg_done = true;
  4864. return 0;
  4865. err:
  4866. return ret;
  4867. }
  4868. static void *def_wcd_mbhc_cal(void)
  4869. {
  4870. void *wcd_mbhc_cal;
  4871. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  4872. u16 *btn_high;
  4873. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  4874. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  4875. if (!wcd_mbhc_cal)
  4876. return NULL;
  4877. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  4878. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  4879. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  4880. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  4881. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  4882. btn_high[0] = 75;
  4883. btn_high[1] = 150;
  4884. btn_high[2] = 237;
  4885. btn_high[3] = 500;
  4886. btn_high[4] = 500;
  4887. btn_high[5] = 500;
  4888. btn_high[6] = 500;
  4889. btn_high[7] = 500;
  4890. return wcd_mbhc_cal;
  4891. }
  4892. /* Digital audio interface glue - connects codec <---> CPU */
  4893. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4894. /* FrontEnd DAI Links */
  4895. {/* hw:x,0 */
  4896. .name = MSM_DAILINK_NAME(Media1),
  4897. .stream_name = "MultiMedia1",
  4898. .cpu_dai_name = "MultiMedia1",
  4899. .platform_name = "msm-pcm-dsp.0",
  4900. .dynamic = 1,
  4901. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4902. .dpcm_playback = 1,
  4903. .dpcm_capture = 1,
  4904. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4905. SND_SOC_DPCM_TRIGGER_POST},
  4906. .codec_dai_name = "snd-soc-dummy-dai",
  4907. .codec_name = "snd-soc-dummy",
  4908. .ignore_suspend = 1,
  4909. /* this dainlink has playback support */
  4910. .ignore_pmdown_time = 1,
  4911. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4912. },
  4913. {/* hw:x,1 */
  4914. .name = MSM_DAILINK_NAME(Media2),
  4915. .stream_name = "MultiMedia2",
  4916. .cpu_dai_name = "MultiMedia2",
  4917. .platform_name = "msm-pcm-dsp.0",
  4918. .dynamic = 1,
  4919. .dpcm_playback = 1,
  4920. .dpcm_capture = 1,
  4921. .codec_dai_name = "snd-soc-dummy-dai",
  4922. .codec_name = "snd-soc-dummy",
  4923. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4924. SND_SOC_DPCM_TRIGGER_POST},
  4925. .ignore_suspend = 1,
  4926. /* this dainlink has playback support */
  4927. .ignore_pmdown_time = 1,
  4928. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4929. },
  4930. {/* hw:x,2 */
  4931. .name = "VoiceMMode1",
  4932. .stream_name = "VoiceMMode1",
  4933. .cpu_dai_name = "VoiceMMode1",
  4934. .platform_name = "msm-pcm-voice",
  4935. .dynamic = 1,
  4936. .dpcm_playback = 1,
  4937. .dpcm_capture = 1,
  4938. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4939. SND_SOC_DPCM_TRIGGER_POST},
  4940. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4941. .ignore_suspend = 1,
  4942. .ignore_pmdown_time = 1,
  4943. .codec_dai_name = "snd-soc-dummy-dai",
  4944. .codec_name = "snd-soc-dummy",
  4945. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4946. },
  4947. {/* hw:x,3 */
  4948. .name = "MSM VoIP",
  4949. .stream_name = "VoIP",
  4950. .cpu_dai_name = "VoIP",
  4951. .platform_name = "msm-voip-dsp",
  4952. .dynamic = 1,
  4953. .dpcm_playback = 1,
  4954. .dpcm_capture = 1,
  4955. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4956. SND_SOC_DPCM_TRIGGER_POST},
  4957. .codec_dai_name = "snd-soc-dummy-dai",
  4958. .codec_name = "snd-soc-dummy",
  4959. .ignore_suspend = 1,
  4960. /* this dainlink has playback support */
  4961. .ignore_pmdown_time = 1,
  4962. .id = MSM_FRONTEND_DAI_VOIP,
  4963. },
  4964. {/* hw:x,4 */
  4965. .name = MSM_DAILINK_NAME(ULL),
  4966. .stream_name = "MultiMedia3",
  4967. .cpu_dai_name = "MultiMedia3",
  4968. .platform_name = "msm-pcm-dsp.2",
  4969. .dynamic = 1,
  4970. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4971. .dpcm_playback = 1,
  4972. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4973. SND_SOC_DPCM_TRIGGER_POST},
  4974. .codec_dai_name = "snd-soc-dummy-dai",
  4975. .codec_name = "snd-soc-dummy",
  4976. .ignore_suspend = 1,
  4977. /* this dainlink has playback support */
  4978. .ignore_pmdown_time = 1,
  4979. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4980. },
  4981. {/* hw:x,5 */
  4982. .name = "MSM AFE-PCM RX",
  4983. .stream_name = "AFE-PROXY RX",
  4984. .cpu_dai_name = "msm-dai-q6-dev.241",
  4985. .codec_name = "msm-stub-codec.1",
  4986. .codec_dai_name = "msm-stub-rx",
  4987. .platform_name = "msm-pcm-afe",
  4988. .dpcm_playback = 1,
  4989. .ignore_suspend = 1,
  4990. /* this dainlink has playback support */
  4991. .ignore_pmdown_time = 1,
  4992. },
  4993. {/* hw:x,6 */
  4994. .name = "MSM AFE-PCM TX",
  4995. .stream_name = "AFE-PROXY TX",
  4996. .cpu_dai_name = "msm-dai-q6-dev.240",
  4997. .codec_name = "msm-stub-codec.1",
  4998. .codec_dai_name = "msm-stub-tx",
  4999. .platform_name = "msm-pcm-afe",
  5000. .dpcm_capture = 1,
  5001. .ignore_suspend = 1,
  5002. },
  5003. {/* hw:x,7 */
  5004. .name = MSM_DAILINK_NAME(Compress1),
  5005. .stream_name = "Compress1",
  5006. .cpu_dai_name = "MultiMedia4",
  5007. .platform_name = "msm-compress-dsp",
  5008. .dynamic = 1,
  5009. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5010. .dpcm_playback = 1,
  5011. .dpcm_capture = 1,
  5012. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5013. SND_SOC_DPCM_TRIGGER_POST},
  5014. .codec_dai_name = "snd-soc-dummy-dai",
  5015. .codec_name = "snd-soc-dummy",
  5016. .ignore_suspend = 1,
  5017. .ignore_pmdown_time = 1,
  5018. /* this dainlink has playback support */
  5019. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5020. },
  5021. /* Hostless PCM purpose */
  5022. {/* hw:x,8 */
  5023. .name = "AUXPCM Hostless",
  5024. .stream_name = "AUXPCM Hostless",
  5025. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5026. .platform_name = "msm-pcm-hostless",
  5027. .dynamic = 1,
  5028. .dpcm_playback = 1,
  5029. .dpcm_capture = 1,
  5030. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5031. SND_SOC_DPCM_TRIGGER_POST},
  5032. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5033. .ignore_suspend = 1,
  5034. /* this dainlink has playback support */
  5035. .ignore_pmdown_time = 1,
  5036. .codec_dai_name = "snd-soc-dummy-dai",
  5037. .codec_name = "snd-soc-dummy",
  5038. },
  5039. {/* hw:x,9 */
  5040. .name = MSM_DAILINK_NAME(LowLatency),
  5041. .stream_name = "MultiMedia5",
  5042. .cpu_dai_name = "MultiMedia5",
  5043. .platform_name = "msm-pcm-dsp.1",
  5044. .dynamic = 1,
  5045. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5046. .dpcm_playback = 1,
  5047. .dpcm_capture = 1,
  5048. .codec_dai_name = "snd-soc-dummy-dai",
  5049. .codec_name = "snd-soc-dummy",
  5050. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5051. SND_SOC_DPCM_TRIGGER_POST},
  5052. .ignore_suspend = 1,
  5053. /* this dainlink has playback support */
  5054. .ignore_pmdown_time = 1,
  5055. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5056. .ops = &msm_fe_qos_ops,
  5057. },
  5058. {/* hw:x,10 */
  5059. .name = "Listen 1 Audio Service",
  5060. .stream_name = "Listen 1 Audio Service",
  5061. .cpu_dai_name = "LSM1",
  5062. .platform_name = "msm-lsm-client",
  5063. .dynamic = 1,
  5064. .dpcm_capture = 1,
  5065. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5066. SND_SOC_DPCM_TRIGGER_POST },
  5067. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5068. .ignore_suspend = 1,
  5069. .codec_dai_name = "snd-soc-dummy-dai",
  5070. .codec_name = "snd-soc-dummy",
  5071. .id = MSM_FRONTEND_DAI_LSM1,
  5072. },
  5073. /* Multiple Tunnel instances */
  5074. {/* hw:x,11 */
  5075. .name = MSM_DAILINK_NAME(Compress2),
  5076. .stream_name = "Compress2",
  5077. .cpu_dai_name = "MultiMedia7",
  5078. .platform_name = "msm-compress-dsp",
  5079. .dynamic = 1,
  5080. .dpcm_playback = 1,
  5081. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5082. SND_SOC_DPCM_TRIGGER_POST},
  5083. .codec_dai_name = "snd-soc-dummy-dai",
  5084. .codec_name = "snd-soc-dummy",
  5085. .ignore_suspend = 1,
  5086. .ignore_pmdown_time = 1,
  5087. /* this dainlink has playback support */
  5088. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5089. },
  5090. {/* hw:x,12 */
  5091. .name = MSM_DAILINK_NAME(MultiMedia10),
  5092. .stream_name = "MultiMedia10",
  5093. .cpu_dai_name = "MultiMedia10",
  5094. .platform_name = "msm-pcm-dsp.1",
  5095. .dynamic = 1,
  5096. .dpcm_playback = 1,
  5097. .dpcm_capture = 1,
  5098. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5099. SND_SOC_DPCM_TRIGGER_POST},
  5100. .codec_dai_name = "snd-soc-dummy-dai",
  5101. .codec_name = "snd-soc-dummy",
  5102. .ignore_suspend = 1,
  5103. .ignore_pmdown_time = 1,
  5104. /* this dainlink has playback support */
  5105. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5106. },
  5107. {/* hw:x,13 */
  5108. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5109. .stream_name = "MM_NOIRQ",
  5110. .cpu_dai_name = "MultiMedia8",
  5111. .platform_name = "msm-pcm-dsp-noirq",
  5112. .dynamic = 1,
  5113. .dpcm_playback = 1,
  5114. .dpcm_capture = 1,
  5115. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5116. SND_SOC_DPCM_TRIGGER_POST},
  5117. .codec_dai_name = "snd-soc-dummy-dai",
  5118. .codec_name = "snd-soc-dummy",
  5119. .ignore_suspend = 1,
  5120. .ignore_pmdown_time = 1,
  5121. /* this dainlink has playback support */
  5122. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5123. .ops = &msm_fe_qos_ops,
  5124. },
  5125. /* HDMI Hostless */
  5126. {/* hw:x,14 */
  5127. .name = "HDMI_RX_HOSTLESS",
  5128. .stream_name = "HDMI_RX_HOSTLESS",
  5129. .cpu_dai_name = "HDMI_HOSTLESS",
  5130. .platform_name = "msm-pcm-hostless",
  5131. .dynamic = 1,
  5132. .dpcm_playback = 1,
  5133. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5134. SND_SOC_DPCM_TRIGGER_POST},
  5135. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5136. .ignore_suspend = 1,
  5137. .ignore_pmdown_time = 1,
  5138. .codec_dai_name = "snd-soc-dummy-dai",
  5139. .codec_name = "snd-soc-dummy",
  5140. },
  5141. {/* hw:x,15 */
  5142. .name = "VoiceMMode2",
  5143. .stream_name = "VoiceMMode2",
  5144. .cpu_dai_name = "VoiceMMode2",
  5145. .platform_name = "msm-pcm-voice",
  5146. .dynamic = 1,
  5147. .dpcm_playback = 1,
  5148. .dpcm_capture = 1,
  5149. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5150. SND_SOC_DPCM_TRIGGER_POST},
  5151. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5152. .ignore_suspend = 1,
  5153. .ignore_pmdown_time = 1,
  5154. .codec_dai_name = "snd-soc-dummy-dai",
  5155. .codec_name = "snd-soc-dummy",
  5156. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5157. },
  5158. /* LSM FE */
  5159. {/* hw:x,16 */
  5160. .name = "Listen 2 Audio Service",
  5161. .stream_name = "Listen 2 Audio Service",
  5162. .cpu_dai_name = "LSM2",
  5163. .platform_name = "msm-lsm-client",
  5164. .dynamic = 1,
  5165. .dpcm_capture = 1,
  5166. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5167. SND_SOC_DPCM_TRIGGER_POST },
  5168. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5169. .ignore_suspend = 1,
  5170. .codec_dai_name = "snd-soc-dummy-dai",
  5171. .codec_name = "snd-soc-dummy",
  5172. .id = MSM_FRONTEND_DAI_LSM2,
  5173. },
  5174. {/* hw:x,17 */
  5175. .name = "Listen 3 Audio Service",
  5176. .stream_name = "Listen 3 Audio Service",
  5177. .cpu_dai_name = "LSM3",
  5178. .platform_name = "msm-lsm-client",
  5179. .dynamic = 1,
  5180. .dpcm_capture = 1,
  5181. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5182. SND_SOC_DPCM_TRIGGER_POST },
  5183. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5184. .ignore_suspend = 1,
  5185. .codec_dai_name = "snd-soc-dummy-dai",
  5186. .codec_name = "snd-soc-dummy",
  5187. .id = MSM_FRONTEND_DAI_LSM3,
  5188. },
  5189. {/* hw:x,18 */
  5190. .name = "Listen 4 Audio Service",
  5191. .stream_name = "Listen 4 Audio Service",
  5192. .cpu_dai_name = "LSM4",
  5193. .platform_name = "msm-lsm-client",
  5194. .dynamic = 1,
  5195. .dpcm_capture = 1,
  5196. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5197. SND_SOC_DPCM_TRIGGER_POST },
  5198. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5199. .ignore_suspend = 1,
  5200. .codec_dai_name = "snd-soc-dummy-dai",
  5201. .codec_name = "snd-soc-dummy",
  5202. .id = MSM_FRONTEND_DAI_LSM4,
  5203. },
  5204. {/* hw:x,19 */
  5205. .name = "Listen 5 Audio Service",
  5206. .stream_name = "Listen 5 Audio Service",
  5207. .cpu_dai_name = "LSM5",
  5208. .platform_name = "msm-lsm-client",
  5209. .dynamic = 1,
  5210. .dpcm_capture = 1,
  5211. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5212. SND_SOC_DPCM_TRIGGER_POST },
  5213. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5214. .ignore_suspend = 1,
  5215. .codec_dai_name = "snd-soc-dummy-dai",
  5216. .codec_name = "snd-soc-dummy",
  5217. .id = MSM_FRONTEND_DAI_LSM5,
  5218. },
  5219. {/* hw:x,20 */
  5220. .name = "Listen 6 Audio Service",
  5221. .stream_name = "Listen 6 Audio Service",
  5222. .cpu_dai_name = "LSM6",
  5223. .platform_name = "msm-lsm-client",
  5224. .dynamic = 1,
  5225. .dpcm_capture = 1,
  5226. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5227. SND_SOC_DPCM_TRIGGER_POST },
  5228. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5229. .ignore_suspend = 1,
  5230. .codec_dai_name = "snd-soc-dummy-dai",
  5231. .codec_name = "snd-soc-dummy",
  5232. .id = MSM_FRONTEND_DAI_LSM6,
  5233. },
  5234. {/* hw:x,21 */
  5235. .name = "Listen 7 Audio Service",
  5236. .stream_name = "Listen 7 Audio Service",
  5237. .cpu_dai_name = "LSM7",
  5238. .platform_name = "msm-lsm-client",
  5239. .dynamic = 1,
  5240. .dpcm_capture = 1,
  5241. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5242. SND_SOC_DPCM_TRIGGER_POST },
  5243. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5244. .ignore_suspend = 1,
  5245. .codec_dai_name = "snd-soc-dummy-dai",
  5246. .codec_name = "snd-soc-dummy",
  5247. .id = MSM_FRONTEND_DAI_LSM7,
  5248. },
  5249. {/* hw:x,22 */
  5250. .name = "Listen 8 Audio Service",
  5251. .stream_name = "Listen 8 Audio Service",
  5252. .cpu_dai_name = "LSM8",
  5253. .platform_name = "msm-lsm-client",
  5254. .dynamic = 1,
  5255. .dpcm_capture = 1,
  5256. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5257. SND_SOC_DPCM_TRIGGER_POST },
  5258. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5259. .ignore_suspend = 1,
  5260. .codec_dai_name = "snd-soc-dummy-dai",
  5261. .codec_name = "snd-soc-dummy",
  5262. .id = MSM_FRONTEND_DAI_LSM8,
  5263. },
  5264. {/* hw:x,23 */
  5265. .name = MSM_DAILINK_NAME(Media9),
  5266. .stream_name = "MultiMedia9",
  5267. .cpu_dai_name = "MultiMedia9",
  5268. .platform_name = "msm-pcm-dsp.0",
  5269. .dynamic = 1,
  5270. .dpcm_playback = 1,
  5271. .dpcm_capture = 1,
  5272. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5273. SND_SOC_DPCM_TRIGGER_POST},
  5274. .codec_dai_name = "snd-soc-dummy-dai",
  5275. .codec_name = "snd-soc-dummy",
  5276. .ignore_suspend = 1,
  5277. /* this dainlink has playback support */
  5278. .ignore_pmdown_time = 1,
  5279. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5280. },
  5281. {/* hw:x,24 */
  5282. .name = MSM_DAILINK_NAME(Compress4),
  5283. .stream_name = "Compress4",
  5284. .cpu_dai_name = "MultiMedia11",
  5285. .platform_name = "msm-compress-dsp",
  5286. .dynamic = 1,
  5287. .dpcm_playback = 1,
  5288. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5289. SND_SOC_DPCM_TRIGGER_POST},
  5290. .codec_dai_name = "snd-soc-dummy-dai",
  5291. .codec_name = "snd-soc-dummy",
  5292. .ignore_suspend = 1,
  5293. .ignore_pmdown_time = 1,
  5294. /* this dainlink has playback support */
  5295. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5296. },
  5297. {/* hw:x,25 */
  5298. .name = MSM_DAILINK_NAME(Compress5),
  5299. .stream_name = "Compress5",
  5300. .cpu_dai_name = "MultiMedia12",
  5301. .platform_name = "msm-compress-dsp",
  5302. .dynamic = 1,
  5303. .dpcm_playback = 1,
  5304. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5305. SND_SOC_DPCM_TRIGGER_POST},
  5306. .codec_dai_name = "snd-soc-dummy-dai",
  5307. .codec_name = "snd-soc-dummy",
  5308. .ignore_suspend = 1,
  5309. .ignore_pmdown_time = 1,
  5310. /* this dainlink has playback support */
  5311. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5312. },
  5313. {/* hw:x,26 */
  5314. .name = MSM_DAILINK_NAME(Compress6),
  5315. .stream_name = "Compress6",
  5316. .cpu_dai_name = "MultiMedia13",
  5317. .platform_name = "msm-compress-dsp",
  5318. .dynamic = 1,
  5319. .dpcm_playback = 1,
  5320. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5321. SND_SOC_DPCM_TRIGGER_POST},
  5322. .codec_dai_name = "snd-soc-dummy-dai",
  5323. .codec_name = "snd-soc-dummy",
  5324. .ignore_suspend = 1,
  5325. .ignore_pmdown_time = 1,
  5326. /* this dainlink has playback support */
  5327. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5328. },
  5329. {/* hw:x,27 */
  5330. .name = MSM_DAILINK_NAME(Compress7),
  5331. .stream_name = "Compress7",
  5332. .cpu_dai_name = "MultiMedia14",
  5333. .platform_name = "msm-compress-dsp",
  5334. .dynamic = 1,
  5335. .dpcm_playback = 1,
  5336. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5337. SND_SOC_DPCM_TRIGGER_POST},
  5338. .codec_dai_name = "snd-soc-dummy-dai",
  5339. .codec_name = "snd-soc-dummy",
  5340. .ignore_suspend = 1,
  5341. .ignore_pmdown_time = 1,
  5342. /* this dainlink has playback support */
  5343. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5344. },
  5345. {/* hw:x,28 */
  5346. .name = MSM_DAILINK_NAME(Compress8),
  5347. .stream_name = "Compress8",
  5348. .cpu_dai_name = "MultiMedia15",
  5349. .platform_name = "msm-compress-dsp",
  5350. .dynamic = 1,
  5351. .dpcm_playback = 1,
  5352. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5353. SND_SOC_DPCM_TRIGGER_POST},
  5354. .codec_dai_name = "snd-soc-dummy-dai",
  5355. .codec_name = "snd-soc-dummy",
  5356. .ignore_suspend = 1,
  5357. .ignore_pmdown_time = 1,
  5358. /* this dainlink has playback support */
  5359. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5360. },
  5361. {/* hw:x,29 */
  5362. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5363. .stream_name = "MM_NOIRQ_2",
  5364. .cpu_dai_name = "MultiMedia16",
  5365. .platform_name = "msm-pcm-dsp-noirq",
  5366. .dynamic = 1,
  5367. .dpcm_playback = 1,
  5368. .dpcm_capture = 1,
  5369. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5370. SND_SOC_DPCM_TRIGGER_POST},
  5371. .codec_dai_name = "snd-soc-dummy-dai",
  5372. .codec_name = "snd-soc-dummy",
  5373. .ignore_suspend = 1,
  5374. .ignore_pmdown_time = 1,
  5375. /* this dainlink has playback support */
  5376. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5377. .ops = &msm_fe_qos_ops,
  5378. },
  5379. {/* hw:x,30 */
  5380. .name = "CDC_DMA Hostless",
  5381. .stream_name = "CDC_DMA Hostless",
  5382. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5383. .platform_name = "msm-pcm-hostless",
  5384. .dynamic = 1,
  5385. .dpcm_playback = 1,
  5386. .dpcm_capture = 1,
  5387. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5388. SND_SOC_DPCM_TRIGGER_POST},
  5389. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5390. .ignore_suspend = 1,
  5391. /* this dailink has playback support */
  5392. .ignore_pmdown_time = 1,
  5393. .codec_dai_name = "snd-soc-dummy-dai",
  5394. .codec_name = "snd-soc-dummy",
  5395. },
  5396. {/* hw:x,31 */
  5397. .name = "TX3_CDC_DMA Hostless",
  5398. .stream_name = "TX3_CDC_DMA Hostless",
  5399. .cpu_dai_name = "TX3_CDC_DMA_HOSTLESS",
  5400. .platform_name = "msm-pcm-hostless",
  5401. .dynamic = 1,
  5402. .dpcm_capture = 1,
  5403. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5404. SND_SOC_DPCM_TRIGGER_POST},
  5405. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5406. .ignore_suspend = 1,
  5407. .codec_dai_name = "snd-soc-dummy-dai",
  5408. .codec_name = "snd-soc-dummy",
  5409. },
  5410. {/* hw:x,32 */
  5411. .name = "Tertiary MI2S TX_Hostless",
  5412. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  5413. .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
  5414. .platform_name = "msm-pcm-hostless",
  5415. .dynamic = 1,
  5416. .dpcm_capture = 1,
  5417. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5418. SND_SOC_DPCM_TRIGGER_POST},
  5419. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5420. .ignore_suspend = 1,
  5421. .ignore_pmdown_time = 1,
  5422. .codec_dai_name = "snd-soc-dummy-dai",
  5423. .codec_name = "snd-soc-dummy",
  5424. },
  5425. };
  5426. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5427. {/* hw:x,33 */
  5428. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5429. .stream_name = "WSA CDC DMA0 Capture",
  5430. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5431. .platform_name = "msm-pcm-hostless",
  5432. .codec_name = "bolero_codec",
  5433. .codec_dai_name = "wsa_macro_vifeedback",
  5434. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5435. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5436. .ignore_suspend = 1,
  5437. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5438. .ops = &msm_cdc_dma_be_ops,
  5439. },
  5440. };
  5441. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5442. {/* hw:x,34 */
  5443. .name = MSM_DAILINK_NAME(ASM Loopback),
  5444. .stream_name = "MultiMedia6",
  5445. .cpu_dai_name = "MultiMedia6",
  5446. .platform_name = "msm-pcm-loopback",
  5447. .dynamic = 1,
  5448. .dpcm_playback = 1,
  5449. .dpcm_capture = 1,
  5450. .codec_dai_name = "snd-soc-dummy-dai",
  5451. .codec_name = "snd-soc-dummy",
  5452. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5453. SND_SOC_DPCM_TRIGGER_POST},
  5454. .ignore_suspend = 1,
  5455. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5456. .ignore_pmdown_time = 1,
  5457. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5458. },
  5459. {/* hw:x,35 */
  5460. .name = "USB Audio Hostless",
  5461. .stream_name = "USB Audio Hostless",
  5462. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5463. .platform_name = "msm-pcm-hostless",
  5464. .dynamic = 1,
  5465. .dpcm_playback = 1,
  5466. .dpcm_capture = 1,
  5467. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5468. SND_SOC_DPCM_TRIGGER_POST},
  5469. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5470. .ignore_suspend = 1,
  5471. .ignore_pmdown_time = 1,
  5472. .codec_dai_name = "snd-soc-dummy-dai",
  5473. .codec_name = "snd-soc-dummy",
  5474. },
  5475. {/* hw:x,36 */
  5476. .name = "SLIMBUS_7 Hostless",
  5477. .stream_name = "SLIMBUS_7 Hostless",
  5478. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5479. .platform_name = "msm-pcm-hostless",
  5480. .dynamic = 1,
  5481. .dpcm_capture = 1,
  5482. .dpcm_playback = 1,
  5483. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5484. SND_SOC_DPCM_TRIGGER_POST},
  5485. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5486. .ignore_suspend = 1,
  5487. .ignore_pmdown_time = 1,
  5488. .codec_dai_name = "snd-soc-dummy-dai",
  5489. .codec_name = "snd-soc-dummy",
  5490. },
  5491. {/* hw:x,37 */
  5492. .name = "Compress Capture",
  5493. .stream_name = "Compress9",
  5494. .cpu_dai_name = "MultiMedia17",
  5495. .platform_name = "msm-compress-dsp",
  5496. .dynamic = 1,
  5497. .dpcm_capture = 1,
  5498. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5499. SND_SOC_DPCM_TRIGGER_POST},
  5500. .codec_dai_name = "snd-soc-dummy-dai",
  5501. .codec_name = "snd-soc-dummy",
  5502. .ignore_suspend = 1,
  5503. .ignore_pmdown_time = 1,
  5504. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  5505. },
  5506. {/* hw:x,38 */
  5507. .name = "SLIMBUS_8 Hostless",
  5508. .stream_name = "SLIMBUS_8 Hostless",
  5509. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5510. .platform_name = "msm-pcm-hostless",
  5511. .dynamic = 1,
  5512. .dpcm_capture = 1,
  5513. .dpcm_playback = 1,
  5514. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5515. SND_SOC_DPCM_TRIGGER_POST},
  5516. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5517. .ignore_suspend = 1,
  5518. .ignore_pmdown_time = 1,
  5519. .codec_dai_name = "snd-soc-dummy-dai",
  5520. .codec_name = "snd-soc-dummy",
  5521. },
  5522. {/* hw:x,39 */
  5523. .name = LPASS_BE_TX_CDC_DMA_TX_5,
  5524. .stream_name = "TX CDC DMA5 Capture",
  5525. .cpu_dai_name = "msm-dai-cdc-dma-dev.45115",
  5526. .platform_name = "msm-pcm-hostless",
  5527. .codec_name = "bolero_codec",
  5528. .codec_dai_name = "tx_macro_tx3",
  5529. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_5,
  5530. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5531. .ignore_suspend = 1,
  5532. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5533. .ops = &msm_cdc_dma_be_ops,
  5534. },
  5535. };
  5536. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5537. /* Backend AFE DAI Links */
  5538. {
  5539. .name = LPASS_BE_AFE_PCM_RX,
  5540. .stream_name = "AFE Playback",
  5541. .cpu_dai_name = "msm-dai-q6-dev.224",
  5542. .platform_name = "msm-pcm-routing",
  5543. .codec_name = "msm-stub-codec.1",
  5544. .codec_dai_name = "msm-stub-rx",
  5545. .no_pcm = 1,
  5546. .dpcm_playback = 1,
  5547. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5548. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5549. /* this dainlink has playback support */
  5550. .ignore_pmdown_time = 1,
  5551. .ignore_suspend = 1,
  5552. },
  5553. {
  5554. .name = LPASS_BE_AFE_PCM_TX,
  5555. .stream_name = "AFE Capture",
  5556. .cpu_dai_name = "msm-dai-q6-dev.225",
  5557. .platform_name = "msm-pcm-routing",
  5558. .codec_name = "msm-stub-codec.1",
  5559. .codec_dai_name = "msm-stub-tx",
  5560. .no_pcm = 1,
  5561. .dpcm_capture = 1,
  5562. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5563. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5564. .ignore_suspend = 1,
  5565. },
  5566. /* Incall Record Uplink BACK END DAI Link */
  5567. {
  5568. .name = LPASS_BE_INCALL_RECORD_TX,
  5569. .stream_name = "Voice Uplink Capture",
  5570. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5571. .platform_name = "msm-pcm-routing",
  5572. .codec_name = "msm-stub-codec.1",
  5573. .codec_dai_name = "msm-stub-tx",
  5574. .no_pcm = 1,
  5575. .dpcm_capture = 1,
  5576. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5577. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5578. .ignore_suspend = 1,
  5579. },
  5580. /* Incall Record Downlink BACK END DAI Link */
  5581. {
  5582. .name = LPASS_BE_INCALL_RECORD_RX,
  5583. .stream_name = "Voice Downlink Capture",
  5584. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5585. .platform_name = "msm-pcm-routing",
  5586. .codec_name = "msm-stub-codec.1",
  5587. .codec_dai_name = "msm-stub-tx",
  5588. .no_pcm = 1,
  5589. .dpcm_capture = 1,
  5590. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5591. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5592. .ignore_suspend = 1,
  5593. },
  5594. /* Incall Music BACK END DAI Link */
  5595. {
  5596. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5597. .stream_name = "Voice Farend Playback",
  5598. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5599. .platform_name = "msm-pcm-routing",
  5600. .codec_name = "msm-stub-codec.1",
  5601. .codec_dai_name = "msm-stub-rx",
  5602. .no_pcm = 1,
  5603. .dpcm_playback = 1,
  5604. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5605. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5606. .ignore_suspend = 1,
  5607. .ignore_pmdown_time = 1,
  5608. },
  5609. /* Incall Music 2 BACK END DAI Link */
  5610. {
  5611. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5612. .stream_name = "Voice2 Farend Playback",
  5613. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5614. .platform_name = "msm-pcm-routing",
  5615. .codec_name = "msm-stub-codec.1",
  5616. .codec_dai_name = "msm-stub-rx",
  5617. .no_pcm = 1,
  5618. .dpcm_playback = 1,
  5619. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5620. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5621. .ignore_suspend = 1,
  5622. .ignore_pmdown_time = 1,
  5623. },
  5624. {
  5625. .name = LPASS_BE_USB_AUDIO_RX,
  5626. .stream_name = "USB Audio Playback",
  5627. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5628. .platform_name = "msm-pcm-routing",
  5629. .codec_name = "msm-stub-codec.1",
  5630. .codec_dai_name = "msm-stub-rx",
  5631. .dynamic_be = 1,
  5632. .no_pcm = 1,
  5633. .dpcm_playback = 1,
  5634. .id = MSM_BACKEND_DAI_USB_RX,
  5635. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5636. .ignore_pmdown_time = 1,
  5637. .ignore_suspend = 1,
  5638. },
  5639. {
  5640. .name = LPASS_BE_USB_AUDIO_TX,
  5641. .stream_name = "USB Audio Capture",
  5642. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5643. .platform_name = "msm-pcm-routing",
  5644. .codec_name = "msm-stub-codec.1",
  5645. .codec_dai_name = "msm-stub-tx",
  5646. .no_pcm = 1,
  5647. .dpcm_capture = 1,
  5648. .id = MSM_BACKEND_DAI_USB_TX,
  5649. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5650. .ignore_suspend = 1,
  5651. },
  5652. {
  5653. .name = LPASS_BE_PRI_TDM_RX_0,
  5654. .stream_name = "Primary TDM0 Playback",
  5655. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5656. .platform_name = "msm-pcm-routing",
  5657. .codec_name = "msm-stub-codec.1",
  5658. .codec_dai_name = "msm-stub-rx",
  5659. .no_pcm = 1,
  5660. .dpcm_playback = 1,
  5661. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5662. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5663. .ops = &kona_tdm_be_ops,
  5664. .ignore_suspend = 1,
  5665. .ignore_pmdown_time = 1,
  5666. },
  5667. {
  5668. .name = LPASS_BE_PRI_TDM_TX_0,
  5669. .stream_name = "Primary TDM0 Capture",
  5670. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5671. .platform_name = "msm-pcm-routing",
  5672. .codec_name = "msm-stub-codec.1",
  5673. .codec_dai_name = "msm-stub-tx",
  5674. .no_pcm = 1,
  5675. .dpcm_capture = 1,
  5676. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5677. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5678. .ops = &kona_tdm_be_ops,
  5679. .ignore_suspend = 1,
  5680. },
  5681. {
  5682. .name = LPASS_BE_SEC_TDM_RX_0,
  5683. .stream_name = "Secondary TDM0 Playback",
  5684. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5685. .platform_name = "msm-pcm-routing",
  5686. .codec_name = "msm-stub-codec.1",
  5687. .codec_dai_name = "msm-stub-rx",
  5688. .no_pcm = 1,
  5689. .dpcm_playback = 1,
  5690. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5691. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5692. .ops = &kona_tdm_be_ops,
  5693. .ignore_suspend = 1,
  5694. .ignore_pmdown_time = 1,
  5695. },
  5696. {
  5697. .name = LPASS_BE_SEC_TDM_TX_0,
  5698. .stream_name = "Secondary TDM0 Capture",
  5699. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5700. .platform_name = "msm-pcm-routing",
  5701. .codec_name = "msm-stub-codec.1",
  5702. .codec_dai_name = "msm-stub-tx",
  5703. .no_pcm = 1,
  5704. .dpcm_capture = 1,
  5705. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5706. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5707. .ops = &kona_tdm_be_ops,
  5708. .ignore_suspend = 1,
  5709. },
  5710. {
  5711. .name = LPASS_BE_TERT_TDM_RX_0,
  5712. .stream_name = "Tertiary TDM0 Playback",
  5713. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5714. .platform_name = "msm-pcm-routing",
  5715. .codec_name = "msm-stub-codec.1",
  5716. .codec_dai_name = "msm-stub-rx",
  5717. .no_pcm = 1,
  5718. .dpcm_playback = 1,
  5719. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5720. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5721. .ops = &kona_tdm_be_ops,
  5722. .ignore_suspend = 1,
  5723. .ignore_pmdown_time = 1,
  5724. },
  5725. {
  5726. .name = LPASS_BE_TERT_TDM_TX_0,
  5727. .stream_name = "Tertiary TDM0 Capture",
  5728. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5729. .platform_name = "msm-pcm-routing",
  5730. .codec_name = "msm-stub-codec.1",
  5731. .codec_dai_name = "msm-stub-tx",
  5732. .no_pcm = 1,
  5733. .dpcm_capture = 1,
  5734. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5735. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5736. .ops = &kona_tdm_be_ops,
  5737. .ignore_suspend = 1,
  5738. },
  5739. {
  5740. .name = LPASS_BE_QUAT_TDM_RX_0,
  5741. .stream_name = "Quaternary TDM0 Playback",
  5742. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5743. .platform_name = "msm-pcm-routing",
  5744. .codec_name = "msm-stub-codec.1",
  5745. .codec_dai_name = "msm-stub-rx",
  5746. .no_pcm = 1,
  5747. .dpcm_playback = 1,
  5748. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5749. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5750. .ops = &kona_tdm_be_ops,
  5751. .ignore_suspend = 1,
  5752. .ignore_pmdown_time = 1,
  5753. },
  5754. {
  5755. .name = LPASS_BE_QUAT_TDM_TX_0,
  5756. .stream_name = "Quaternary TDM0 Capture",
  5757. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5758. .platform_name = "msm-pcm-routing",
  5759. .codec_name = "msm-stub-codec.1",
  5760. .codec_dai_name = "msm-stub-tx",
  5761. .no_pcm = 1,
  5762. .dpcm_capture = 1,
  5763. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5764. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5765. .ops = &kona_tdm_be_ops,
  5766. .ignore_suspend = 1,
  5767. },
  5768. {
  5769. .name = LPASS_BE_QUIN_TDM_RX_0,
  5770. .stream_name = "Quinary TDM0 Playback",
  5771. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5772. .platform_name = "msm-pcm-routing",
  5773. .codec_name = "msm-stub-codec.1",
  5774. .codec_dai_name = "msm-stub-rx",
  5775. .no_pcm = 1,
  5776. .dpcm_playback = 1,
  5777. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5778. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5779. .ops = &kona_tdm_be_ops,
  5780. .ignore_suspend = 1,
  5781. .ignore_pmdown_time = 1,
  5782. },
  5783. {
  5784. .name = LPASS_BE_QUIN_TDM_TX_0,
  5785. .stream_name = "Quinary TDM0 Capture",
  5786. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5787. .platform_name = "msm-pcm-routing",
  5788. .codec_name = "msm-stub-codec.1",
  5789. .codec_dai_name = "msm-stub-tx",
  5790. .no_pcm = 1,
  5791. .dpcm_capture = 1,
  5792. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5793. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5794. .ops = &kona_tdm_be_ops,
  5795. .ignore_suspend = 1,
  5796. },
  5797. {
  5798. .name = LPASS_BE_SEN_TDM_RX_0,
  5799. .stream_name = "Senary TDM0 Playback",
  5800. .cpu_dai_name = "msm-dai-q6-tdm.36944",
  5801. .platform_name = "msm-pcm-routing",
  5802. .codec_name = "msm-stub-codec.1",
  5803. .codec_dai_name = "msm-stub-rx",
  5804. .no_pcm = 1,
  5805. .dpcm_playback = 1,
  5806. .id = MSM_BACKEND_DAI_SEN_TDM_RX_0,
  5807. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5808. .ops = &kona_tdm_be_ops,
  5809. .ignore_suspend = 1,
  5810. .ignore_pmdown_time = 1,
  5811. },
  5812. {
  5813. .name = LPASS_BE_SEN_TDM_TX_0,
  5814. .stream_name = "Senary TDM0 Capture",
  5815. .cpu_dai_name = "msm-dai-q6-tdm.36945",
  5816. .platform_name = "msm-pcm-routing",
  5817. .codec_name = "msm-stub-codec.1",
  5818. .codec_dai_name = "msm-stub-tx",
  5819. .no_pcm = 1,
  5820. .dpcm_capture = 1,
  5821. .id = MSM_BACKEND_DAI_SEN_TDM_TX_0,
  5822. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5823. .ops = &kona_tdm_be_ops,
  5824. .ignore_suspend = 1,
  5825. },
  5826. };
  5827. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5828. {
  5829. .name = LPASS_BE_SLIMBUS_7_RX,
  5830. .stream_name = "Slimbus7 Playback",
  5831. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5832. .platform_name = "msm-pcm-routing",
  5833. .codec_name = "btfmslim_slave",
  5834. /* BT codec driver determines capabilities based on
  5835. * dai name, bt codecdai name should always contains
  5836. * supported usecase information
  5837. */
  5838. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5839. .no_pcm = 1,
  5840. .dpcm_playback = 1,
  5841. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5842. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5843. .init = &msm_wcn_init,
  5844. .ops = &msm_wcn_ops,
  5845. /* dai link has playback support */
  5846. .ignore_pmdown_time = 1,
  5847. .ignore_suspend = 1,
  5848. },
  5849. {
  5850. .name = LPASS_BE_SLIMBUS_7_TX,
  5851. .stream_name = "Slimbus7 Capture",
  5852. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5853. .platform_name = "msm-pcm-routing",
  5854. .codec_name = "btfmslim_slave",
  5855. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5856. .no_pcm = 1,
  5857. .dpcm_capture = 1,
  5858. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5859. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5860. .ops = &msm_wcn_ops,
  5861. .ignore_suspend = 1,
  5862. },
  5863. };
  5864. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  5865. {
  5866. .name = LPASS_BE_SLIMBUS_7_RX,
  5867. .stream_name = "Slimbus7 Playback",
  5868. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5869. .platform_name = "msm-pcm-routing",
  5870. .codec_name = "btfmslim_slave",
  5871. /* BT codec driver determines capabilities based on
  5872. * dai name, bt codecdai name should always contains
  5873. * supported usecase information
  5874. */
  5875. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5876. .no_pcm = 1,
  5877. .dpcm_playback = 1,
  5878. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5879. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5880. .init = &msm_wcn_init_lito,
  5881. .ops = &msm_wcn_ops_lito,
  5882. /* dai link has playback support */
  5883. .ignore_pmdown_time = 1,
  5884. .ignore_suspend = 1,
  5885. },
  5886. {
  5887. .name = LPASS_BE_SLIMBUS_7_TX,
  5888. .stream_name = "Slimbus7 Capture",
  5889. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5890. .platform_name = "msm-pcm-routing",
  5891. .codec_name = "btfmslim_slave",
  5892. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5893. .no_pcm = 1,
  5894. .dpcm_capture = 1,
  5895. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5896. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5897. .ops = &msm_wcn_ops_lito,
  5898. .ignore_suspend = 1,
  5899. },
  5900. {
  5901. .name = LPASS_BE_SLIMBUS_8_TX,
  5902. .stream_name = "Slimbus8 Capture",
  5903. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5904. .platform_name = "msm-pcm-routing",
  5905. .codec_name = "btfmslim_slave",
  5906. .codec_dai_name = "btfm_fm_slim_tx",
  5907. .no_pcm = 1,
  5908. .dpcm_capture = 1,
  5909. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5910. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5911. .ops = &msm_wcn_ops_lito,
  5912. .ignore_suspend = 1,
  5913. },
  5914. };
  5915. static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
  5916. /* DISP PORT BACK END DAI Link */
  5917. {
  5918. .name = LPASS_BE_DISPLAY_PORT,
  5919. .stream_name = "Display Port Playback",
  5920. .cpu_dai_name = "msm-dai-q6-dp.0",
  5921. .platform_name = "msm-pcm-routing",
  5922. .codec_name = "msm-ext-disp-audio-codec-rx",
  5923. .codec_dai_name = "msm_dp_audio_codec_rx_dai",
  5924. .no_pcm = 1,
  5925. .dpcm_playback = 1,
  5926. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
  5927. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5928. .ignore_pmdown_time = 1,
  5929. .ignore_suspend = 1,
  5930. },
  5931. /* DISP PORT 1 BACK END DAI Link */
  5932. {
  5933. .name = LPASS_BE_DISPLAY_PORT1,
  5934. .stream_name = "Display Port1 Playback",
  5935. .cpu_dai_name = "msm-dai-q6-dp.1",
  5936. .platform_name = "msm-pcm-routing",
  5937. .codec_name = "msm-ext-disp-audio-codec-rx",
  5938. .codec_dai_name = "msm_dp_audio_codec_rx1_dai",
  5939. .no_pcm = 1,
  5940. .dpcm_playback = 1,
  5941. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX_1,
  5942. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5943. .ignore_pmdown_time = 1,
  5944. .ignore_suspend = 1,
  5945. },
  5946. };
  5947. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5948. {
  5949. .name = LPASS_BE_PRI_MI2S_RX,
  5950. .stream_name = "Primary MI2S Playback",
  5951. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5952. .platform_name = "msm-pcm-routing",
  5953. .codec_name = "msm-stub-codec.1",
  5954. .codec_dai_name = "msm-stub-rx",
  5955. .no_pcm = 1,
  5956. .dpcm_playback = 1,
  5957. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5958. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5959. .ops = &msm_mi2s_be_ops,
  5960. .ignore_suspend = 1,
  5961. .ignore_pmdown_time = 1,
  5962. },
  5963. {
  5964. .name = LPASS_BE_PRI_MI2S_TX,
  5965. .stream_name = "Primary MI2S Capture",
  5966. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5967. .platform_name = "msm-pcm-routing",
  5968. .codec_name = "msm-stub-codec.1",
  5969. .codec_dai_name = "msm-stub-tx",
  5970. .no_pcm = 1,
  5971. .dpcm_capture = 1,
  5972. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5973. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5974. .ops = &msm_mi2s_be_ops,
  5975. .ignore_suspend = 1,
  5976. },
  5977. {
  5978. .name = LPASS_BE_SEC_MI2S_RX,
  5979. .stream_name = "Secondary MI2S Playback",
  5980. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5981. .platform_name = "msm-pcm-routing",
  5982. .codec_name = "msm-stub-codec.1",
  5983. .codec_dai_name = "msm-stub-rx",
  5984. .no_pcm = 1,
  5985. .dpcm_playback = 1,
  5986. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5987. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5988. .ops = &msm_mi2s_be_ops,
  5989. .ignore_suspend = 1,
  5990. .ignore_pmdown_time = 1,
  5991. },
  5992. {
  5993. .name = LPASS_BE_SEC_MI2S_TX,
  5994. .stream_name = "Secondary MI2S Capture",
  5995. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5996. .platform_name = "msm-pcm-routing",
  5997. .codec_name = "msm-stub-codec.1",
  5998. .codec_dai_name = "msm-stub-tx",
  5999. .no_pcm = 1,
  6000. .dpcm_capture = 1,
  6001. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6002. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6003. .ops = &msm_mi2s_be_ops,
  6004. .ignore_suspend = 1,
  6005. },
  6006. {
  6007. .name = LPASS_BE_TERT_MI2S_RX,
  6008. .stream_name = "Tertiary MI2S Playback",
  6009. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6010. .platform_name = "msm-pcm-routing",
  6011. .codec_name = "msm-stub-codec.1",
  6012. .codec_dai_name = "msm-stub-rx",
  6013. .no_pcm = 1,
  6014. .dpcm_playback = 1,
  6015. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6016. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6017. .ops = &msm_mi2s_be_ops,
  6018. .ignore_suspend = 1,
  6019. .ignore_pmdown_time = 1,
  6020. },
  6021. {
  6022. .name = LPASS_BE_TERT_MI2S_TX,
  6023. .stream_name = "Tertiary MI2S Capture",
  6024. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6025. .platform_name = "msm-pcm-routing",
  6026. .codec_name = "msm-stub-codec.1",
  6027. .codec_dai_name = "msm-stub-tx",
  6028. .no_pcm = 1,
  6029. .dpcm_capture = 1,
  6030. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6031. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6032. .ops = &msm_mi2s_be_ops,
  6033. .ignore_suspend = 1,
  6034. },
  6035. {
  6036. .name = LPASS_BE_QUAT_MI2S_RX,
  6037. .stream_name = "Quaternary MI2S Playback",
  6038. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6039. .platform_name = "msm-pcm-routing",
  6040. .codec_name = "msm-stub-codec.1",
  6041. .codec_dai_name = "msm-stub-rx",
  6042. .no_pcm = 1,
  6043. .dpcm_playback = 1,
  6044. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6045. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6046. .ops = &msm_mi2s_be_ops,
  6047. .ignore_suspend = 1,
  6048. .ignore_pmdown_time = 1,
  6049. },
  6050. {
  6051. .name = LPASS_BE_QUAT_MI2S_TX,
  6052. .stream_name = "Quaternary MI2S Capture",
  6053. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6054. .platform_name = "msm-pcm-routing",
  6055. .codec_name = "msm-stub-codec.1",
  6056. .codec_dai_name = "msm-stub-tx",
  6057. .no_pcm = 1,
  6058. .dpcm_capture = 1,
  6059. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6060. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6061. .ops = &msm_mi2s_be_ops,
  6062. .ignore_suspend = 1,
  6063. },
  6064. {
  6065. .name = LPASS_BE_QUIN_MI2S_RX,
  6066. .stream_name = "Quinary MI2S Playback",
  6067. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6068. .platform_name = "msm-pcm-routing",
  6069. .codec_name = "msm-stub-codec.1",
  6070. .codec_dai_name = "msm-stub-rx",
  6071. .no_pcm = 1,
  6072. .dpcm_playback = 1,
  6073. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6074. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6075. .ops = &msm_mi2s_be_ops,
  6076. .ignore_suspend = 1,
  6077. .ignore_pmdown_time = 1,
  6078. },
  6079. {
  6080. .name = LPASS_BE_QUIN_MI2S_TX,
  6081. .stream_name = "Quinary MI2S Capture",
  6082. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6083. .platform_name = "msm-pcm-routing",
  6084. .codec_name = "msm-stub-codec.1",
  6085. .codec_dai_name = "msm-stub-tx",
  6086. .no_pcm = 1,
  6087. .dpcm_capture = 1,
  6088. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6089. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6090. .ops = &msm_mi2s_be_ops,
  6091. .ignore_suspend = 1,
  6092. },
  6093. {
  6094. .name = LPASS_BE_SENARY_MI2S_RX,
  6095. .stream_name = "Senary MI2S Playback",
  6096. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  6097. .platform_name = "msm-pcm-routing",
  6098. .codec_name = "msm-stub-codec.1",
  6099. .codec_dai_name = "msm-stub-rx",
  6100. .no_pcm = 1,
  6101. .dpcm_playback = 1,
  6102. .id = MSM_BACKEND_DAI_SENARY_MI2S_RX,
  6103. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6104. .ops = &msm_mi2s_be_ops,
  6105. .ignore_suspend = 1,
  6106. .ignore_pmdown_time = 1,
  6107. },
  6108. {
  6109. .name = LPASS_BE_SENARY_MI2S_TX,
  6110. .stream_name = "Senary MI2S Capture",
  6111. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  6112. .platform_name = "msm-pcm-routing",
  6113. .codec_name = "msm-stub-codec.1",
  6114. .codec_dai_name = "msm-stub-tx",
  6115. .no_pcm = 1,
  6116. .dpcm_capture = 1,
  6117. .id = MSM_BACKEND_DAI_SENARY_MI2S_TX,
  6118. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6119. .ops = &msm_mi2s_be_ops,
  6120. .ignore_suspend = 1,
  6121. },
  6122. };
  6123. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6124. /* Primary AUX PCM Backend DAI Links */
  6125. {
  6126. .name = LPASS_BE_AUXPCM_RX,
  6127. .stream_name = "AUX PCM Playback",
  6128. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6129. .platform_name = "msm-pcm-routing",
  6130. .codec_name = "msm-stub-codec.1",
  6131. .codec_dai_name = "msm-stub-rx",
  6132. .no_pcm = 1,
  6133. .dpcm_playback = 1,
  6134. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6135. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6136. .ops = &kona_aux_be_ops,
  6137. .ignore_pmdown_time = 1,
  6138. .ignore_suspend = 1,
  6139. },
  6140. {
  6141. .name = LPASS_BE_AUXPCM_TX,
  6142. .stream_name = "AUX PCM Capture",
  6143. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6144. .platform_name = "msm-pcm-routing",
  6145. .codec_name = "msm-stub-codec.1",
  6146. .codec_dai_name = "msm-stub-tx",
  6147. .no_pcm = 1,
  6148. .dpcm_capture = 1,
  6149. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6150. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6151. .ops = &kona_aux_be_ops,
  6152. .ignore_suspend = 1,
  6153. },
  6154. /* Secondary AUX PCM Backend DAI Links */
  6155. {
  6156. .name = LPASS_BE_SEC_AUXPCM_RX,
  6157. .stream_name = "Sec AUX PCM Playback",
  6158. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6159. .platform_name = "msm-pcm-routing",
  6160. .codec_name = "msm-stub-codec.1",
  6161. .codec_dai_name = "msm-stub-rx",
  6162. .no_pcm = 1,
  6163. .dpcm_playback = 1,
  6164. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6165. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6166. .ops = &kona_aux_be_ops,
  6167. .ignore_pmdown_time = 1,
  6168. .ignore_suspend = 1,
  6169. },
  6170. {
  6171. .name = LPASS_BE_SEC_AUXPCM_TX,
  6172. .stream_name = "Sec AUX PCM Capture",
  6173. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6174. .platform_name = "msm-pcm-routing",
  6175. .codec_name = "msm-stub-codec.1",
  6176. .codec_dai_name = "msm-stub-tx",
  6177. .no_pcm = 1,
  6178. .dpcm_capture = 1,
  6179. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6180. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6181. .ops = &kona_aux_be_ops,
  6182. .ignore_suspend = 1,
  6183. },
  6184. /* Tertiary AUX PCM Backend DAI Links */
  6185. {
  6186. .name = LPASS_BE_TERT_AUXPCM_RX,
  6187. .stream_name = "Tert AUX PCM Playback",
  6188. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6189. .platform_name = "msm-pcm-routing",
  6190. .codec_name = "msm-stub-codec.1",
  6191. .codec_dai_name = "msm-stub-rx",
  6192. .no_pcm = 1,
  6193. .dpcm_playback = 1,
  6194. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6195. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6196. .ops = &kona_aux_be_ops,
  6197. .ignore_suspend = 1,
  6198. },
  6199. {
  6200. .name = LPASS_BE_TERT_AUXPCM_TX,
  6201. .stream_name = "Tert AUX PCM Capture",
  6202. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6203. .platform_name = "msm-pcm-routing",
  6204. .codec_name = "msm-stub-codec.1",
  6205. .codec_dai_name = "msm-stub-tx",
  6206. .no_pcm = 1,
  6207. .dpcm_capture = 1,
  6208. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6209. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6210. .ops = &kona_aux_be_ops,
  6211. .ignore_suspend = 1,
  6212. },
  6213. /* Quaternary AUX PCM Backend DAI Links */
  6214. {
  6215. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6216. .stream_name = "Quat AUX PCM Playback",
  6217. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6218. .platform_name = "msm-pcm-routing",
  6219. .codec_name = "msm-stub-codec.1",
  6220. .codec_dai_name = "msm-stub-rx",
  6221. .no_pcm = 1,
  6222. .dpcm_playback = 1,
  6223. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6224. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6225. .ops = &kona_aux_be_ops,
  6226. .ignore_suspend = 1,
  6227. },
  6228. {
  6229. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6230. .stream_name = "Quat AUX PCM Capture",
  6231. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6232. .platform_name = "msm-pcm-routing",
  6233. .codec_name = "msm-stub-codec.1",
  6234. .codec_dai_name = "msm-stub-tx",
  6235. .no_pcm = 1,
  6236. .dpcm_capture = 1,
  6237. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6238. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6239. .ops = &kona_aux_be_ops,
  6240. .ignore_suspend = 1,
  6241. },
  6242. /* Quinary AUX PCM Backend DAI Links */
  6243. {
  6244. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6245. .stream_name = "Quin AUX PCM Playback",
  6246. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6247. .platform_name = "msm-pcm-routing",
  6248. .codec_name = "msm-stub-codec.1",
  6249. .codec_dai_name = "msm-stub-rx",
  6250. .no_pcm = 1,
  6251. .dpcm_playback = 1,
  6252. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6253. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6254. .ops = &kona_aux_be_ops,
  6255. .ignore_suspend = 1,
  6256. },
  6257. {
  6258. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6259. .stream_name = "Quin AUX PCM Capture",
  6260. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6261. .platform_name = "msm-pcm-routing",
  6262. .codec_name = "msm-stub-codec.1",
  6263. .codec_dai_name = "msm-stub-tx",
  6264. .no_pcm = 1,
  6265. .dpcm_capture = 1,
  6266. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6267. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6268. .ops = &kona_aux_be_ops,
  6269. .ignore_suspend = 1,
  6270. },
  6271. /* Senary AUX PCM Backend DAI Links */
  6272. {
  6273. .name = LPASS_BE_SEN_AUXPCM_RX,
  6274. .stream_name = "Sen AUX PCM Playback",
  6275. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  6276. .platform_name = "msm-pcm-routing",
  6277. .codec_name = "msm-stub-codec.1",
  6278. .codec_dai_name = "msm-stub-rx",
  6279. .no_pcm = 1,
  6280. .dpcm_playback = 1,
  6281. .id = MSM_BACKEND_DAI_SEN_AUXPCM_RX,
  6282. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6283. .ops = &kona_aux_be_ops,
  6284. .ignore_suspend = 1,
  6285. },
  6286. {
  6287. .name = LPASS_BE_SEN_AUXPCM_TX,
  6288. .stream_name = "Sen AUX PCM Capture",
  6289. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  6290. .platform_name = "msm-pcm-routing",
  6291. .codec_name = "msm-stub-codec.1",
  6292. .codec_dai_name = "msm-stub-tx",
  6293. .no_pcm = 1,
  6294. .dpcm_capture = 1,
  6295. .id = MSM_BACKEND_DAI_SEN_AUXPCM_TX,
  6296. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6297. .ops = &kona_aux_be_ops,
  6298. .ignore_suspend = 1,
  6299. },
  6300. };
  6301. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6302. /* WSA CDC DMA Backend DAI Links */
  6303. {
  6304. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6305. .stream_name = "WSA CDC DMA0 Playback",
  6306. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6307. .platform_name = "msm-pcm-routing",
  6308. .codec_name = "bolero_codec",
  6309. .codec_dai_name = "wsa_macro_rx1",
  6310. .no_pcm = 1,
  6311. .dpcm_playback = 1,
  6312. .init = &msm_int_audrx_init,
  6313. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6314. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6315. .ignore_pmdown_time = 1,
  6316. .ignore_suspend = 1,
  6317. .ops = &msm_cdc_dma_be_ops,
  6318. },
  6319. {
  6320. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6321. .stream_name = "WSA CDC DMA1 Playback",
  6322. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6323. .platform_name = "msm-pcm-routing",
  6324. .codec_name = "bolero_codec",
  6325. .codec_dai_name = "wsa_macro_rx_mix",
  6326. .no_pcm = 1,
  6327. .dpcm_playback = 1,
  6328. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6329. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6330. .ignore_pmdown_time = 1,
  6331. .ignore_suspend = 1,
  6332. .ops = &msm_cdc_dma_be_ops,
  6333. },
  6334. {
  6335. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6336. .stream_name = "WSA CDC DMA1 Capture",
  6337. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6338. .platform_name = "msm-pcm-routing",
  6339. .codec_name = "bolero_codec",
  6340. .codec_dai_name = "wsa_macro_echo",
  6341. .no_pcm = 1,
  6342. .dpcm_capture = 1,
  6343. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6344. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6345. .ignore_suspend = 1,
  6346. .ops = &msm_cdc_dma_be_ops,
  6347. },
  6348. };
  6349. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  6350. /* RX CDC DMA Backend DAI Links */
  6351. {
  6352. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  6353. .stream_name = "RX CDC DMA0 Playback",
  6354. .cpu_dai_name = "msm-dai-cdc-dma-dev.45104",
  6355. .platform_name = "msm-pcm-routing",
  6356. .codec_name = "bolero_codec",
  6357. .codec_dai_name = "rx_macro_rx1",
  6358. .dynamic_be = 1,
  6359. .no_pcm = 1,
  6360. .dpcm_playback = 1,
  6361. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  6362. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6363. .ignore_pmdown_time = 1,
  6364. .ignore_suspend = 1,
  6365. .ops = &msm_cdc_dma_be_ops,
  6366. },
  6367. {
  6368. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  6369. .stream_name = "RX CDC DMA1 Playback",
  6370. .cpu_dai_name = "msm-dai-cdc-dma-dev.45106",
  6371. .platform_name = "msm-pcm-routing",
  6372. .codec_name = "bolero_codec",
  6373. .codec_dai_name = "rx_macro_rx2",
  6374. .dynamic_be = 1,
  6375. .no_pcm = 1,
  6376. .dpcm_playback = 1,
  6377. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  6378. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6379. .ignore_pmdown_time = 1,
  6380. .ignore_suspend = 1,
  6381. .ops = &msm_cdc_dma_be_ops,
  6382. },
  6383. {
  6384. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  6385. .stream_name = "RX CDC DMA2 Playback",
  6386. .cpu_dai_name = "msm-dai-cdc-dma-dev.45108",
  6387. .platform_name = "msm-pcm-routing",
  6388. .codec_name = "bolero_codec",
  6389. .codec_dai_name = "rx_macro_rx3",
  6390. .dynamic_be = 1,
  6391. .no_pcm = 1,
  6392. .dpcm_playback = 1,
  6393. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  6394. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6395. .ignore_pmdown_time = 1,
  6396. .ignore_suspend = 1,
  6397. .ops = &msm_cdc_dma_be_ops,
  6398. },
  6399. {
  6400. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  6401. .stream_name = "RX CDC DMA3 Playback",
  6402. .cpu_dai_name = "msm-dai-cdc-dma-dev.45110",
  6403. .platform_name = "msm-pcm-routing",
  6404. .codec_name = "bolero_codec",
  6405. .codec_dai_name = "rx_macro_rx4",
  6406. .dynamic_be = 1,
  6407. .no_pcm = 1,
  6408. .dpcm_playback = 1,
  6409. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  6410. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6411. .ignore_pmdown_time = 1,
  6412. .ignore_suspend = 1,
  6413. .ops = &msm_cdc_dma_be_ops,
  6414. },
  6415. /* TX CDC DMA Backend DAI Links */
  6416. {
  6417. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  6418. .stream_name = "TX CDC DMA3 Capture",
  6419. .cpu_dai_name = "msm-dai-cdc-dma-dev.45111",
  6420. .platform_name = "msm-pcm-routing",
  6421. .codec_name = "bolero_codec",
  6422. .codec_dai_name = "tx_macro_tx1",
  6423. .no_pcm = 1,
  6424. .dpcm_capture = 1,
  6425. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  6426. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6427. .ignore_suspend = 1,
  6428. .ops = &msm_cdc_dma_be_ops,
  6429. },
  6430. {
  6431. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  6432. .stream_name = "TX CDC DMA4 Capture",
  6433. .cpu_dai_name = "msm-dai-cdc-dma-dev.45113",
  6434. .platform_name = "msm-pcm-routing",
  6435. .codec_name = "bolero_codec",
  6436. .codec_dai_name = "tx_macro_tx2",
  6437. .no_pcm = 1,
  6438. .dpcm_capture = 1,
  6439. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  6440. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6441. .ignore_suspend = 1,
  6442. .ops = &msm_cdc_dma_be_ops,
  6443. },
  6444. };
  6445. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6446. {
  6447. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6448. .stream_name = "VA CDC DMA0 Capture",
  6449. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6450. .platform_name = "msm-pcm-routing",
  6451. .codec_name = "bolero_codec",
  6452. .codec_dai_name = "va_macro_tx1",
  6453. .no_pcm = 1,
  6454. .dpcm_capture = 1,
  6455. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6456. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6457. .ignore_suspend = 1,
  6458. .ops = &msm_cdc_dma_be_ops,
  6459. },
  6460. {
  6461. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6462. .stream_name = "VA CDC DMA1 Capture",
  6463. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6464. .platform_name = "msm-pcm-routing",
  6465. .codec_name = "bolero_codec",
  6466. .codec_dai_name = "va_macro_tx2",
  6467. .no_pcm = 1,
  6468. .dpcm_capture = 1,
  6469. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6470. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6471. .ignore_suspend = 1,
  6472. .ops = &msm_cdc_dma_be_ops,
  6473. },
  6474. {
  6475. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  6476. .stream_name = "VA CDC DMA2 Capture",
  6477. .cpu_dai_name = "msm-dai-cdc-dma-dev.45093",
  6478. .platform_name = "msm-pcm-routing",
  6479. .codec_name = "bolero_codec",
  6480. .codec_dai_name = "va_macro_tx3",
  6481. .no_pcm = 1,
  6482. .dpcm_capture = 1,
  6483. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  6484. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6485. .ignore_suspend = 1,
  6486. .ops = &msm_cdc_dma_be_ops,
  6487. },
  6488. };
  6489. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  6490. {
  6491. .name = LPASS_BE_AFE_LOOPBACK_TX,
  6492. .stream_name = "AFE Loopback Capture",
  6493. .cpu_dai_name = "msm-dai-q6-dev.24577",
  6494. .platform_name = "msm-pcm-routing",
  6495. .codec_name = "msm-stub-codec.1",
  6496. .codec_dai_name = "msm-stub-tx",
  6497. .no_pcm = 1,
  6498. .dpcm_capture = 1,
  6499. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  6500. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6501. .ignore_pmdown_time = 1,
  6502. .ignore_suspend = 1,
  6503. },
  6504. };
  6505. static struct snd_soc_dai_link msm_kona_dai_links[
  6506. ARRAY_SIZE(msm_common_dai_links) +
  6507. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6508. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6509. ARRAY_SIZE(msm_common_be_dai_links) +
  6510. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6511. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6512. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6513. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  6514. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6515. ARRAY_SIZE(ext_disp_be_dai_link) +
  6516. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6517. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  6518. ARRAY_SIZE(msm_wcn_btfm_be_dai_links)];
  6519. static int msm_populate_dai_link_component_of_node(
  6520. struct snd_soc_card *card)
  6521. {
  6522. int i, index, ret = 0;
  6523. struct device *cdev = card->dev;
  6524. struct snd_soc_dai_link *dai_link = card->dai_link;
  6525. struct device_node *np;
  6526. if (!cdev) {
  6527. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  6528. return -ENODEV;
  6529. }
  6530. for (i = 0; i < card->num_links; i++) {
  6531. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6532. continue;
  6533. /* populate platform_of_node for snd card dai links */
  6534. if (dai_link[i].platform_name &&
  6535. !dai_link[i].platform_of_node) {
  6536. index = of_property_match_string(cdev->of_node,
  6537. "asoc-platform-names",
  6538. dai_link[i].platform_name);
  6539. if (index < 0) {
  6540. dev_err(cdev, "%s: No match found for platform name: %s\n",
  6541. __func__, dai_link[i].platform_name);
  6542. ret = index;
  6543. goto err;
  6544. }
  6545. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6546. index);
  6547. if (!np) {
  6548. dev_err(cdev, "%s: retrieving phandle for platform %s, index %d failed\n",
  6549. __func__, dai_link[i].platform_name,
  6550. index);
  6551. ret = -ENODEV;
  6552. goto err;
  6553. }
  6554. dai_link[i].platform_of_node = np;
  6555. dai_link[i].platform_name = NULL;
  6556. }
  6557. /* populate cpu_of_node for snd card dai links */
  6558. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6559. index = of_property_match_string(cdev->of_node,
  6560. "asoc-cpu-names",
  6561. dai_link[i].cpu_dai_name);
  6562. if (index >= 0) {
  6563. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6564. index);
  6565. if (!np) {
  6566. dev_err(cdev, "%s: retrieving phandle for cpu dai %s failed\n",
  6567. __func__,
  6568. dai_link[i].cpu_dai_name);
  6569. ret = -ENODEV;
  6570. goto err;
  6571. }
  6572. dai_link[i].cpu_of_node = np;
  6573. dai_link[i].cpu_dai_name = NULL;
  6574. }
  6575. }
  6576. /* populate codec_of_node for snd card dai links */
  6577. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6578. index = of_property_match_string(cdev->of_node,
  6579. "asoc-codec-names",
  6580. dai_link[i].codec_name);
  6581. if (index < 0)
  6582. continue;
  6583. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6584. index);
  6585. if (!np) {
  6586. dev_err(cdev, "%s: retrieving phandle for codec %s failed\n",
  6587. __func__, dai_link[i].codec_name);
  6588. ret = -ENODEV;
  6589. goto err;
  6590. }
  6591. dai_link[i].codec_of_node = np;
  6592. dai_link[i].codec_name = NULL;
  6593. }
  6594. }
  6595. err:
  6596. return ret;
  6597. }
  6598. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  6599. {
  6600. int ret = -EINVAL;
  6601. struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  6602. if (!component) {
  6603. pr_err("* %s: No match for msm-stub-codec component\n", __func__);
  6604. return ret;
  6605. }
  6606. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  6607. ARRAY_SIZE(msm_snd_controls));
  6608. if (ret < 0) {
  6609. dev_err(component->dev,
  6610. "%s: add_codec_controls failed, err = %d\n",
  6611. __func__, ret);
  6612. return ret;
  6613. }
  6614. return ret;
  6615. }
  6616. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  6617. struct snd_pcm_hw_params *params)
  6618. {
  6619. return 0;
  6620. }
  6621. static struct snd_soc_ops msm_stub_be_ops = {
  6622. .hw_params = msm_snd_stub_hw_params,
  6623. };
  6624. struct snd_soc_card snd_soc_card_stub_msm = {
  6625. .name = "kona-stub-snd-card",
  6626. };
  6627. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6628. /* FrontEnd DAI Links */
  6629. {
  6630. .name = "MSMSTUB Media1",
  6631. .stream_name = "MultiMedia1",
  6632. .cpu_dai_name = "MultiMedia1",
  6633. .platform_name = "msm-pcm-dsp.0",
  6634. .dynamic = 1,
  6635. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6636. .dpcm_playback = 1,
  6637. .dpcm_capture = 1,
  6638. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6639. SND_SOC_DPCM_TRIGGER_POST},
  6640. .codec_dai_name = "snd-soc-dummy-dai",
  6641. .codec_name = "snd-soc-dummy",
  6642. .ignore_suspend = 1,
  6643. /* this dainlink has playback support */
  6644. .ignore_pmdown_time = 1,
  6645. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6646. },
  6647. };
  6648. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6649. /* Backend DAI Links */
  6650. {
  6651. .name = LPASS_BE_AUXPCM_RX,
  6652. .stream_name = "AUX PCM Playback",
  6653. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6654. .platform_name = "msm-pcm-routing",
  6655. .codec_name = "msm-stub-codec.1",
  6656. .codec_dai_name = "msm-stub-rx",
  6657. .no_pcm = 1,
  6658. .dpcm_playback = 1,
  6659. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6660. .init = &msm_audrx_stub_init,
  6661. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6662. .ignore_pmdown_time = 1,
  6663. .ignore_suspend = 1,
  6664. .ops = &msm_stub_be_ops,
  6665. },
  6666. {
  6667. .name = LPASS_BE_AUXPCM_TX,
  6668. .stream_name = "AUX PCM Capture",
  6669. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6670. .platform_name = "msm-pcm-routing",
  6671. .codec_name = "msm-stub-codec.1",
  6672. .codec_dai_name = "msm-stub-tx",
  6673. .no_pcm = 1,
  6674. .dpcm_capture = 1,
  6675. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6676. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6677. .ignore_suspend = 1,
  6678. .ops = &msm_stub_be_ops,
  6679. },
  6680. };
  6681. static struct snd_soc_dai_link msm_stub_dai_links[
  6682. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6683. ARRAY_SIZE(msm_stub_be_dai_links)];
  6684. static const struct of_device_id kona_asoc_machine_of_match[] = {
  6685. { .compatible = "qcom,kona-asoc-snd",
  6686. .data = "codec"},
  6687. { .compatible = "qcom,kona-asoc-snd-stub",
  6688. .data = "stub_codec"},
  6689. {},
  6690. };
  6691. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6692. {
  6693. struct snd_soc_card *card = NULL;
  6694. struct snd_soc_dai_link *dailink = NULL;
  6695. int len_1 = 0;
  6696. int len_2 = 0;
  6697. int total_links = 0;
  6698. int rc = 0;
  6699. u32 mi2s_audio_intf = 0;
  6700. u32 auxpcm_audio_intf = 0;
  6701. u32 val = 0;
  6702. u32 wcn_btfm_intf = 0;
  6703. const struct of_device_id *match;
  6704. match = of_match_node(kona_asoc_machine_of_match, dev->of_node);
  6705. if (!match) {
  6706. dev_err(dev, "%s: No DT match found for sound card\n",
  6707. __func__);
  6708. return NULL;
  6709. }
  6710. if (!strcmp(match->data, "codec")) {
  6711. card = &snd_soc_card_kona_msm;
  6712. memcpy(msm_kona_dai_links + total_links,
  6713. msm_common_dai_links,
  6714. sizeof(msm_common_dai_links));
  6715. total_links += ARRAY_SIZE(msm_common_dai_links);
  6716. memcpy(msm_kona_dai_links + total_links,
  6717. msm_bolero_fe_dai_links,
  6718. sizeof(msm_bolero_fe_dai_links));
  6719. total_links +=
  6720. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6721. memcpy(msm_kona_dai_links + total_links,
  6722. msm_common_misc_fe_dai_links,
  6723. sizeof(msm_common_misc_fe_dai_links));
  6724. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6725. memcpy(msm_kona_dai_links + total_links,
  6726. msm_common_be_dai_links,
  6727. sizeof(msm_common_be_dai_links));
  6728. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6729. memcpy(msm_kona_dai_links + total_links,
  6730. msm_wsa_cdc_dma_be_dai_links,
  6731. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6732. total_links +=
  6733. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6734. memcpy(msm_kona_dai_links + total_links,
  6735. msm_rx_tx_cdc_dma_be_dai_links,
  6736. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  6737. total_links +=
  6738. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
  6739. memcpy(msm_kona_dai_links + total_links,
  6740. msm_va_cdc_dma_be_dai_links,
  6741. sizeof(msm_va_cdc_dma_be_dai_links));
  6742. total_links +=
  6743. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6744. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6745. &mi2s_audio_intf);
  6746. if (rc) {
  6747. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6748. __func__);
  6749. } else {
  6750. if (mi2s_audio_intf) {
  6751. memcpy(msm_kona_dai_links + total_links,
  6752. msm_mi2s_be_dai_links,
  6753. sizeof(msm_mi2s_be_dai_links));
  6754. total_links +=
  6755. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6756. }
  6757. }
  6758. rc = of_property_read_u32(dev->of_node,
  6759. "qcom,auxpcm-audio-intf",
  6760. &auxpcm_audio_intf);
  6761. if (rc) {
  6762. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6763. __func__);
  6764. } else {
  6765. if (auxpcm_audio_intf) {
  6766. memcpy(msm_kona_dai_links + total_links,
  6767. msm_auxpcm_be_dai_links,
  6768. sizeof(msm_auxpcm_be_dai_links));
  6769. total_links +=
  6770. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6771. }
  6772. }
  6773. rc = of_property_read_u32(dev->of_node,
  6774. "qcom,ext-disp-audio-rx", &val);
  6775. if (!rc && val) {
  6776. dev_dbg(dev, "%s(): ext disp audio support present\n",
  6777. __func__);
  6778. memcpy(msm_kona_dai_links + total_links,
  6779. ext_disp_be_dai_link,
  6780. sizeof(ext_disp_be_dai_link));
  6781. total_links += ARRAY_SIZE(ext_disp_be_dai_link);
  6782. }
  6783. rc = of_property_read_u32(dev->of_node, "qcom,wcn-bt", &val);
  6784. if (!rc && val) {
  6785. dev_dbg(dev, "%s(): WCN BT support present\n",
  6786. __func__);
  6787. memcpy(msm_kona_dai_links + total_links,
  6788. msm_wcn_be_dai_links,
  6789. sizeof(msm_wcn_be_dai_links));
  6790. total_links += ARRAY_SIZE(msm_wcn_be_dai_links);
  6791. }
  6792. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  6793. &val);
  6794. if (!rc && val) {
  6795. memcpy(msm_kona_dai_links + total_links,
  6796. msm_afe_rxtx_lb_be_dai_link,
  6797. sizeof(msm_afe_rxtx_lb_be_dai_link));
  6798. total_links +=
  6799. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  6800. }
  6801. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  6802. &wcn_btfm_intf);
  6803. if (rc) {
  6804. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  6805. __func__);
  6806. } else {
  6807. if (wcn_btfm_intf) {
  6808. memcpy(msm_kona_dai_links + total_links,
  6809. msm_wcn_btfm_be_dai_links,
  6810. sizeof(msm_wcn_btfm_be_dai_links));
  6811. total_links +=
  6812. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  6813. }
  6814. }
  6815. dailink = msm_kona_dai_links;
  6816. } else if(!strcmp(match->data, "stub_codec")) {
  6817. card = &snd_soc_card_stub_msm;
  6818. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  6819. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  6820. memcpy(msm_stub_dai_links,
  6821. msm_stub_fe_dai_links,
  6822. sizeof(msm_stub_fe_dai_links));
  6823. memcpy(msm_stub_dai_links + len_1,
  6824. msm_stub_be_dai_links,
  6825. sizeof(msm_stub_be_dai_links));
  6826. dailink = msm_stub_dai_links;
  6827. total_links = len_2;
  6828. }
  6829. if (card) {
  6830. card->dai_link = dailink;
  6831. card->num_links = total_links;
  6832. }
  6833. return card;
  6834. }
  6835. static int msm_wsa881x_init(struct snd_soc_component *component)
  6836. {
  6837. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6838. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6839. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6840. SPKR_L_BOOST, SPKR_L_VI};
  6841. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6842. SPKR_R_BOOST, SPKR_R_VI};
  6843. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6844. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6845. struct msm_asoc_mach_data *pdata;
  6846. struct snd_soc_dapm_context *dapm;
  6847. struct snd_card *card;
  6848. struct snd_info_entry *entry;
  6849. int ret = 0;
  6850. if (!component) {
  6851. pr_err("%s component is NULL\n", __func__);
  6852. return -EINVAL;
  6853. }
  6854. card = component->card->snd_card;
  6855. dapm = snd_soc_component_get_dapm(component);
  6856. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6857. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  6858. __func__, component->name);
  6859. wsa881x_set_channel_map(component, &spkleft_ports[0],
  6860. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6861. &ch_rate[0], &spkleft_port_types[0]);
  6862. if (dapm->component) {
  6863. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6864. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6865. }
  6866. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6867. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  6868. __func__, component->name);
  6869. wsa881x_set_channel_map(component, &spkright_ports[0],
  6870. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6871. &ch_rate[0], &spkright_port_types[0]);
  6872. if (dapm->component) {
  6873. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6874. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6875. }
  6876. } else {
  6877. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  6878. component->name);
  6879. ret = -EINVAL;
  6880. goto err;
  6881. }
  6882. pdata = snd_soc_card_get_drvdata(component->card);
  6883. if (!pdata->codec_root) {
  6884. entry = snd_info_create_subdir(card->module, "codecs",
  6885. card->proc_root);
  6886. if (!entry) {
  6887. pr_err("%s: Cannot create codecs module entry\n",
  6888. __func__);
  6889. ret = 0;
  6890. goto err;
  6891. }
  6892. pdata->codec_root = entry;
  6893. }
  6894. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6895. component);
  6896. err:
  6897. return ret;
  6898. }
  6899. static int msm_aux_codec_init(struct snd_soc_component *component)
  6900. {
  6901. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  6902. int ret = 0;
  6903. int codec_variant = -1;
  6904. void *mbhc_calibration;
  6905. struct snd_info_entry *entry;
  6906. struct snd_card *card = component->card->snd_card;
  6907. struct msm_asoc_mach_data *pdata;
  6908. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  6909. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  6910. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  6911. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  6912. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  6913. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  6914. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  6915. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  6916. snd_soc_dapm_sync(dapm);
  6917. pdata = snd_soc_card_get_drvdata(component->card);
  6918. if (!pdata->codec_root) {
  6919. entry = snd_info_create_subdir(card->module, "codecs",
  6920. card->proc_root);
  6921. if (!entry) {
  6922. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  6923. __func__);
  6924. ret = 0;
  6925. goto mbhc_cfg_cal;
  6926. }
  6927. pdata->codec_root = entry;
  6928. }
  6929. wcd938x_info_create_codec_entry(pdata->codec_root, component);
  6930. codec_variant = wcd938x_get_codec_variant(component);
  6931. dev_dbg(component->dev, "%s: variant %d\n", __func__, codec_variant);
  6932. if (codec_variant == WCD9380)
  6933. ret = snd_soc_add_component_controls(component,
  6934. msm_int_wcd9380_snd_controls,
  6935. ARRAY_SIZE(msm_int_wcd9380_snd_controls));
  6936. else if (codec_variant == WCD9385)
  6937. ret = snd_soc_add_component_controls(component,
  6938. msm_int_wcd9385_snd_controls,
  6939. ARRAY_SIZE(msm_int_wcd9385_snd_controls));
  6940. if (ret < 0) {
  6941. dev_err(component->dev, "%s: add codec specific snd controls failed: %d\n",
  6942. __func__, ret);
  6943. return ret;
  6944. }
  6945. mbhc_cfg_cal:
  6946. mbhc_calibration = def_wcd_mbhc_cal();
  6947. if (!mbhc_calibration)
  6948. return -ENOMEM;
  6949. wcd_mbhc_cfg.calibration = mbhc_calibration;
  6950. ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  6951. if (ret) {
  6952. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  6953. __func__, ret);
  6954. goto err_hs_detect;
  6955. }
  6956. return 0;
  6957. err_hs_detect:
  6958. kfree(mbhc_calibration);
  6959. return ret;
  6960. }
  6961. static int msm_init_aux_dev(struct platform_device *pdev,
  6962. struct snd_soc_card *card)
  6963. {
  6964. struct device_node *wsa_of_node;
  6965. struct device_node *aux_codec_of_node;
  6966. u32 wsa_max_devs;
  6967. u32 wsa_dev_cnt;
  6968. u32 codec_max_aux_devs = 0;
  6969. u32 codec_aux_dev_cnt = 0;
  6970. int i;
  6971. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6972. struct aux_codec_dev_info *aux_cdc_dev_info;
  6973. const char *auxdev_name_prefix[1];
  6974. char *dev_name_str = NULL;
  6975. int found = 0;
  6976. int codecs_found = 0;
  6977. int ret = 0;
  6978. /* Get maximum WSA device count for this platform */
  6979. ret = of_property_read_u32(pdev->dev.of_node,
  6980. "qcom,wsa-max-devs", &wsa_max_devs);
  6981. if (ret) {
  6982. dev_info(&pdev->dev,
  6983. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6984. __func__, pdev->dev.of_node->full_name, ret);
  6985. wsa_max_devs = 0;
  6986. goto codec_aux_dev;
  6987. }
  6988. if (wsa_max_devs == 0) {
  6989. dev_warn(&pdev->dev,
  6990. "%s: Max WSA devices is 0 for this target?\n",
  6991. __func__);
  6992. goto codec_aux_dev;
  6993. }
  6994. /* Get count of WSA device phandles for this platform */
  6995. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6996. "qcom,wsa-devs", NULL);
  6997. if (wsa_dev_cnt == -ENOENT) {
  6998. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6999. __func__);
  7000. goto err;
  7001. } else if (wsa_dev_cnt <= 0) {
  7002. dev_err(&pdev->dev,
  7003. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7004. __func__, wsa_dev_cnt);
  7005. ret = -EINVAL;
  7006. goto err;
  7007. }
  7008. /*
  7009. * Expect total phandles count to be NOT less than maximum possible
  7010. * WSA count. However, if it is less, then assign same value to
  7011. * max count as well.
  7012. */
  7013. if (wsa_dev_cnt < wsa_max_devs) {
  7014. dev_dbg(&pdev->dev,
  7015. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7016. __func__, wsa_max_devs, wsa_dev_cnt);
  7017. wsa_max_devs = wsa_dev_cnt;
  7018. }
  7019. /* Make sure prefix string passed for each WSA device */
  7020. ret = of_property_count_strings(pdev->dev.of_node,
  7021. "qcom,wsa-aux-dev-prefix");
  7022. if (ret != wsa_dev_cnt) {
  7023. dev_err(&pdev->dev,
  7024. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7025. __func__, wsa_dev_cnt, ret);
  7026. ret = -EINVAL;
  7027. goto err;
  7028. }
  7029. /*
  7030. * Alloc mem to store phandle and index info of WSA device, if already
  7031. * registered with ALSA core
  7032. */
  7033. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7034. sizeof(struct msm_wsa881x_dev_info),
  7035. GFP_KERNEL);
  7036. if (!wsa881x_dev_info) {
  7037. ret = -ENOMEM;
  7038. goto err;
  7039. }
  7040. /*
  7041. * search and check whether all WSA devices are already
  7042. * registered with ALSA core or not. If found a node, store
  7043. * the node and the index in a local array of struct for later
  7044. * use.
  7045. */
  7046. for (i = 0; i < wsa_dev_cnt; i++) {
  7047. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7048. "qcom,wsa-devs", i);
  7049. if (unlikely(!wsa_of_node)) {
  7050. /* we should not be here */
  7051. dev_err(&pdev->dev,
  7052. "%s: wsa dev node is not present\n",
  7053. __func__);
  7054. ret = -EINVAL;
  7055. goto err;
  7056. }
  7057. if (soc_find_component(wsa_of_node, NULL)) {
  7058. /* WSA device registered with ALSA core */
  7059. wsa881x_dev_info[found].of_node = wsa_of_node;
  7060. wsa881x_dev_info[found].index = i;
  7061. found++;
  7062. if (found == wsa_max_devs)
  7063. break;
  7064. }
  7065. }
  7066. if (found < wsa_max_devs) {
  7067. dev_dbg(&pdev->dev,
  7068. "%s: failed to find %d components. Found only %d\n",
  7069. __func__, wsa_max_devs, found);
  7070. return -EPROBE_DEFER;
  7071. }
  7072. dev_info(&pdev->dev,
  7073. "%s: found %d wsa881x devices registered with ALSA core\n",
  7074. __func__, found);
  7075. codec_aux_dev:
  7076. /* Get maximum aux codec device count for this platform */
  7077. ret = of_property_read_u32(pdev->dev.of_node,
  7078. "qcom,codec-max-aux-devs",
  7079. &codec_max_aux_devs);
  7080. if (ret) {
  7081. dev_err(&pdev->dev,
  7082. "%s: codec-max-aux-devs property missing in DT %s, ret = %d\n",
  7083. __func__, pdev->dev.of_node->full_name, ret);
  7084. codec_max_aux_devs = 0;
  7085. goto aux_dev_register;
  7086. }
  7087. if (codec_max_aux_devs == 0) {
  7088. dev_dbg(&pdev->dev,
  7089. "%s: Max aux codec devices is 0 for this target?\n",
  7090. __func__);
  7091. goto aux_dev_register;
  7092. }
  7093. /* Get count of aux codec device phandles for this platform */
  7094. codec_aux_dev_cnt = of_count_phandle_with_args(
  7095. pdev->dev.of_node,
  7096. "qcom,codec-aux-devs", NULL);
  7097. if (codec_aux_dev_cnt == -ENOENT) {
  7098. dev_warn(&pdev->dev, "%s: No aux codec defined in DT.\n",
  7099. __func__);
  7100. goto err;
  7101. } else if (codec_aux_dev_cnt <= 0) {
  7102. dev_err(&pdev->dev,
  7103. "%s: Error reading aux codec device from DT, dev_cnt=%d\n",
  7104. __func__, codec_aux_dev_cnt);
  7105. ret = -EINVAL;
  7106. goto err;
  7107. }
  7108. /*
  7109. * Expect total phandles count to be NOT less than maximum possible
  7110. * AUX device count. However, if it is less, then assign same value to
  7111. * max count as well.
  7112. */
  7113. if (codec_aux_dev_cnt < codec_max_aux_devs) {
  7114. dev_dbg(&pdev->dev,
  7115. "%s: codec_max_aux_devs = %d cannot exceed codec_aux_dev_cnt = %d\n",
  7116. __func__, codec_max_aux_devs,
  7117. codec_aux_dev_cnt);
  7118. codec_max_aux_devs = codec_aux_dev_cnt;
  7119. }
  7120. /*
  7121. * Alloc mem to store phandle and index info of aux codec
  7122. * if already registered with ALSA core
  7123. */
  7124. aux_cdc_dev_info = devm_kcalloc(&pdev->dev, codec_aux_dev_cnt,
  7125. sizeof(struct aux_codec_dev_info),
  7126. GFP_KERNEL);
  7127. if (!aux_cdc_dev_info) {
  7128. ret = -ENOMEM;
  7129. goto err;
  7130. }
  7131. /*
  7132. * search and check whether all aux codecs are already
  7133. * registered with ALSA core or not. If found a node, store
  7134. * the node and the index in a local array of struct for later
  7135. * use.
  7136. */
  7137. for (i = 0; i < codec_aux_dev_cnt; i++) {
  7138. aux_codec_of_node = of_parse_phandle(pdev->dev.of_node,
  7139. "qcom,codec-aux-devs", i);
  7140. if (unlikely(!aux_codec_of_node)) {
  7141. /* we should not be here */
  7142. dev_err(&pdev->dev,
  7143. "%s: aux codec dev node is not present\n",
  7144. __func__);
  7145. ret = -EINVAL;
  7146. goto err;
  7147. }
  7148. if (soc_find_component(aux_codec_of_node, NULL)) {
  7149. /* AUX codec registered with ALSA core */
  7150. aux_cdc_dev_info[codecs_found].of_node =
  7151. aux_codec_of_node;
  7152. aux_cdc_dev_info[codecs_found].index = i;
  7153. codecs_found++;
  7154. }
  7155. }
  7156. if (codecs_found < codec_aux_dev_cnt) {
  7157. dev_dbg(&pdev->dev,
  7158. "%s: failed to find %d components. Found only %d\n",
  7159. __func__, codec_aux_dev_cnt, codecs_found);
  7160. return -EPROBE_DEFER;
  7161. }
  7162. dev_info(&pdev->dev,
  7163. "%s: found %d AUX codecs registered with ALSA core\n",
  7164. __func__, codecs_found);
  7165. aux_dev_register:
  7166. card->num_aux_devs = wsa_max_devs + codec_aux_dev_cnt;
  7167. card->num_configs = wsa_max_devs + codec_aux_dev_cnt;
  7168. /* Alloc array of AUX devs struct */
  7169. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7170. sizeof(struct snd_soc_aux_dev),
  7171. GFP_KERNEL);
  7172. if (!msm_aux_dev) {
  7173. ret = -ENOMEM;
  7174. goto err;
  7175. }
  7176. /* Alloc array of codec conf struct */
  7177. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_configs,
  7178. sizeof(struct snd_soc_codec_conf),
  7179. GFP_KERNEL);
  7180. if (!msm_codec_conf) {
  7181. ret = -ENOMEM;
  7182. goto err;
  7183. }
  7184. for (i = 0; i < wsa_max_devs; i++) {
  7185. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7186. GFP_KERNEL);
  7187. if (!dev_name_str) {
  7188. ret = -ENOMEM;
  7189. goto err;
  7190. }
  7191. ret = of_property_read_string_index(pdev->dev.of_node,
  7192. "qcom,wsa-aux-dev-prefix",
  7193. wsa881x_dev_info[i].index,
  7194. auxdev_name_prefix);
  7195. if (ret) {
  7196. dev_err(&pdev->dev,
  7197. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7198. __func__, ret);
  7199. ret = -EINVAL;
  7200. goto err;
  7201. }
  7202. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7203. msm_aux_dev[i].name = dev_name_str;
  7204. msm_aux_dev[i].codec_name = NULL;
  7205. msm_aux_dev[i].codec_of_node =
  7206. wsa881x_dev_info[i].of_node;
  7207. msm_aux_dev[i].init = msm_wsa881x_init;
  7208. msm_codec_conf[i].dev_name = NULL;
  7209. msm_codec_conf[i].name_prefix = auxdev_name_prefix[0];
  7210. msm_codec_conf[i].of_node =
  7211. wsa881x_dev_info[i].of_node;
  7212. }
  7213. for (i = 0; i < codec_aux_dev_cnt; i++) {
  7214. msm_aux_dev[wsa_max_devs + i].name = NULL;
  7215. msm_aux_dev[wsa_max_devs + i].codec_name = NULL;
  7216. msm_aux_dev[wsa_max_devs + i].codec_of_node =
  7217. aux_cdc_dev_info[i].of_node;
  7218. msm_aux_dev[wsa_max_devs + i].init = msm_aux_codec_init;
  7219. msm_codec_conf[wsa_max_devs + i].dev_name = NULL;
  7220. msm_codec_conf[wsa_max_devs + i].name_prefix =
  7221. NULL;
  7222. msm_codec_conf[wsa_max_devs + i].of_node =
  7223. aux_cdc_dev_info[i].of_node;
  7224. }
  7225. card->codec_conf = msm_codec_conf;
  7226. card->aux_dev = msm_aux_dev;
  7227. err:
  7228. return ret;
  7229. }
  7230. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7231. {
  7232. int count = 0;
  7233. u32 mi2s_master_slave[MI2S_MAX];
  7234. int ret = 0;
  7235. for (count = 0; count < MI2S_MAX; count++) {
  7236. mutex_init(&mi2s_intf_conf[count].lock);
  7237. mi2s_intf_conf[count].ref_cnt = 0;
  7238. }
  7239. ret = of_property_read_u32_array(pdev->dev.of_node,
  7240. "qcom,msm-mi2s-master",
  7241. mi2s_master_slave, MI2S_MAX);
  7242. if (ret) {
  7243. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7244. __func__);
  7245. } else {
  7246. for (count = 0; count < MI2S_MAX; count++) {
  7247. mi2s_intf_conf[count].msm_is_mi2s_master =
  7248. mi2s_master_slave[count];
  7249. }
  7250. }
  7251. }
  7252. static void msm_i2s_auxpcm_deinit(void)
  7253. {
  7254. int count = 0;
  7255. for (count = 0; count < MI2S_MAX; count++) {
  7256. mutex_destroy(&mi2s_intf_conf[count].lock);
  7257. mi2s_intf_conf[count].ref_cnt = 0;
  7258. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7259. }
  7260. }
  7261. static int kona_ssr_enable(struct device *dev, void *data)
  7262. {
  7263. struct platform_device *pdev = to_platform_device(dev);
  7264. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7265. int ret = 0;
  7266. if (!card) {
  7267. dev_err(dev, "%s: card is NULL\n", __func__);
  7268. ret = -EINVAL;
  7269. goto err;
  7270. }
  7271. if (!strcmp(card->name, "kona-stub-snd-card")) {
  7272. /* TODO */
  7273. dev_dbg(dev, "%s: TODO \n", __func__);
  7274. }
  7275. snd_soc_card_change_online_state(card, 1);
  7276. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  7277. err:
  7278. return ret;
  7279. }
  7280. static void kona_ssr_disable(struct device *dev, void *data)
  7281. {
  7282. struct platform_device *pdev = to_platform_device(dev);
  7283. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7284. if (!card) {
  7285. dev_err(dev, "%s: card is NULL\n", __func__);
  7286. return;
  7287. }
  7288. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  7289. snd_soc_card_change_online_state(card, 0);
  7290. if (!strcmp(card->name, "kona-stub-snd-card")) {
  7291. /* TODO */
  7292. dev_dbg(dev, "%s: TODO \n", __func__);
  7293. }
  7294. }
  7295. static const struct snd_event_ops kona_ssr_ops = {
  7296. .enable = kona_ssr_enable,
  7297. .disable = kona_ssr_disable,
  7298. };
  7299. static int msm_audio_ssr_compare(struct device *dev, void *data)
  7300. {
  7301. struct device_node *node = data;
  7302. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  7303. __func__, dev->of_node, node);
  7304. return (dev->of_node && dev->of_node == node);
  7305. }
  7306. static int msm_audio_ssr_register(struct device *dev)
  7307. {
  7308. struct device_node *np = dev->of_node;
  7309. struct snd_event_clients *ssr_clients = NULL;
  7310. struct device_node *node = NULL;
  7311. int ret = 0;
  7312. int i = 0;
  7313. for (i = 0; ; i++) {
  7314. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  7315. if (!node)
  7316. break;
  7317. snd_event_mstr_add_client(&ssr_clients,
  7318. msm_audio_ssr_compare, node);
  7319. }
  7320. ret = snd_event_master_register(dev, &kona_ssr_ops,
  7321. ssr_clients, NULL);
  7322. if (!ret)
  7323. snd_event_notify(dev, SND_EVENT_UP);
  7324. return ret;
  7325. }
  7326. static int msm_asoc_machine_probe(struct platform_device *pdev)
  7327. {
  7328. struct snd_soc_card *card = NULL;
  7329. struct msm_asoc_mach_data *pdata = NULL;
  7330. const char *mbhc_audio_jack_type = NULL;
  7331. int ret = 0;
  7332. uint index = 0;
  7333. struct clk *lpass_audio_hw_vote = NULL;
  7334. if (!pdev->dev.of_node) {
  7335. dev_err(&pdev->dev, "%s: No platform supplied from device tree\n", __func__);
  7336. return -EINVAL;
  7337. }
  7338. pdata = devm_kzalloc(&pdev->dev,
  7339. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  7340. if (!pdata)
  7341. return -ENOMEM;
  7342. of_property_read_u32(pdev->dev.of_node,
  7343. "qcom,lito-is-v2-enabled",
  7344. &pdata->lito_v2_enabled);
  7345. card = populate_snd_card_dailinks(&pdev->dev);
  7346. if (!card) {
  7347. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  7348. ret = -EINVAL;
  7349. goto err;
  7350. }
  7351. card->dev = &pdev->dev;
  7352. platform_set_drvdata(pdev, card);
  7353. snd_soc_card_set_drvdata(card, pdata);
  7354. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7355. if (ret) {
  7356. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  7357. __func__, ret);
  7358. goto err;
  7359. }
  7360. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7361. if (ret) {
  7362. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  7363. __func__, ret);
  7364. goto err;
  7365. }
  7366. ret = msm_populate_dai_link_component_of_node(card);
  7367. if (ret) {
  7368. ret = -EPROBE_DEFER;
  7369. goto err;
  7370. }
  7371. ret = msm_init_aux_dev(pdev, card);
  7372. if (ret)
  7373. goto err;
  7374. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7375. if (ret == -EPROBE_DEFER) {
  7376. if (codec_reg_done)
  7377. ret = -EINVAL;
  7378. goto err;
  7379. } else if (ret) {
  7380. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  7381. __func__, ret);
  7382. goto err;
  7383. }
  7384. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  7385. __func__, card->name);
  7386. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7387. "qcom,hph-en1-gpio", 0);
  7388. if (!pdata->hph_en1_gpio_p) {
  7389. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  7390. __func__, "qcom,hph-en1-gpio",
  7391. pdev->dev.of_node->full_name);
  7392. }
  7393. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7394. "qcom,hph-en0-gpio", 0);
  7395. if (!pdata->hph_en0_gpio_p) {
  7396. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  7397. __func__, "qcom,hph-en0-gpio",
  7398. pdev->dev.of_node->full_name);
  7399. }
  7400. ret = of_property_read_string(pdev->dev.of_node,
  7401. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  7402. if (ret) {
  7403. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  7404. __func__, "qcom,mbhc-audio-jack-type",
  7405. pdev->dev.of_node->full_name);
  7406. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  7407. } else {
  7408. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  7409. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  7410. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  7411. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  7412. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  7413. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  7414. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  7415. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  7416. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  7417. } else {
  7418. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  7419. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  7420. }
  7421. }
  7422. /*
  7423. * Parse US-Euro gpio info from DT. Report no error if us-euro
  7424. * entry is not found in DT file as some targets do not support
  7425. * US-Euro detection
  7426. */
  7427. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7428. "qcom,us-euro-gpios", 0);
  7429. if (!pdata->us_euro_gpio_p) {
  7430. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  7431. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  7432. } else {
  7433. dev_dbg(&pdev->dev, "%s detected\n",
  7434. "qcom,us-euro-gpios");
  7435. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  7436. }
  7437. if (wcd_mbhc_cfg.enable_usbc_analog)
  7438. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  7439. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  7440. "fsa4480-i2c-handle", 0);
  7441. if (!pdata->fsa_handle)
  7442. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  7443. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  7444. msm_i2s_auxpcm_init(pdev);
  7445. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7446. "qcom,cdc-dmic01-gpios",
  7447. 0);
  7448. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7449. "qcom,cdc-dmic23-gpios",
  7450. 0);
  7451. pdata->dmic45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7452. "qcom,cdc-dmic45-gpios",
  7453. 0);
  7454. if (pdata->dmic01_gpio_p)
  7455. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic01_gpio_p, false);
  7456. if (pdata->dmic23_gpio_p)
  7457. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic23_gpio_p, false);
  7458. if (pdata->dmic45_gpio_p)
  7459. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic45_gpio_p, false);
  7460. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7461. "qcom,pri-mi2s-gpios", 0);
  7462. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7463. "qcom,sec-mi2s-gpios", 0);
  7464. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7465. "qcom,tert-mi2s-gpios", 0);
  7466. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7467. "qcom,quat-mi2s-gpios", 0);
  7468. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7469. "qcom,quin-mi2s-gpios", 0);
  7470. pdata->mi2s_gpio_p[SEN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7471. "qcom,sen-mi2s-gpios", 0);
  7472. for (index = PRIM_MI2S; index < MI2S_MAX; index++)
  7473. atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0);
  7474. /* Register LPASS audio hw vote */
  7475. lpass_audio_hw_vote = devm_clk_get(&pdev->dev, "lpass_audio_hw_vote");
  7476. if (IS_ERR(lpass_audio_hw_vote)) {
  7477. ret = PTR_ERR(lpass_audio_hw_vote);
  7478. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  7479. __func__, "lpass_audio_hw_vote", ret);
  7480. lpass_audio_hw_vote = NULL;
  7481. ret = 0;
  7482. }
  7483. pdata->lpass_audio_hw_vote = lpass_audio_hw_vote;
  7484. pdata->core_audio_vote_count = 0;
  7485. ret = msm_audio_ssr_register(&pdev->dev);
  7486. if (ret)
  7487. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  7488. __func__, ret);
  7489. is_initial_boot = true;
  7490. return 0;
  7491. err:
  7492. devm_kfree(&pdev->dev, pdata);
  7493. return ret;
  7494. }
  7495. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7496. {
  7497. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7498. snd_event_master_deregister(&pdev->dev);
  7499. snd_soc_unregister_card(card);
  7500. msm_i2s_auxpcm_deinit();
  7501. return 0;
  7502. }
  7503. static struct platform_driver kona_asoc_machine_driver = {
  7504. .driver = {
  7505. .name = DRV_NAME,
  7506. .owner = THIS_MODULE,
  7507. .pm = &snd_soc_pm_ops,
  7508. .of_match_table = kona_asoc_machine_of_match,
  7509. .suppress_bind_attrs = true,
  7510. },
  7511. .probe = msm_asoc_machine_probe,
  7512. .remove = msm_asoc_machine_remove,
  7513. };
  7514. module_platform_driver(kona_asoc_machine_driver);
  7515. MODULE_DESCRIPTION("ALSA SoC msm");
  7516. MODULE_LICENSE("GPL v2");
  7517. MODULE_ALIAS("platform:" DRV_NAME);
  7518. MODULE_DEVICE_TABLE(of, kona_asoc_machine_of_match);