qcs405.c 251 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/clk.h>
  5. #include <linux/delay.h>
  6. #include <linux/gpio.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/i2c.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <sound/core.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/info.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <dsp/q6afe-v2.h>
  25. #include <dsp/q6core.h>
  26. #include <dsp/msm_mdf.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include <asoc/msm-cdc-pinctrl.h>
  30. #include "codecs/wcd9335.h"
  31. #include "codecs/wsa881x.h"
  32. #include "codecs/csra66x0/csra66x0.h"
  33. #include <dt-bindings/sound/audio-codec-port-types.h>
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include "codecs/bolero/wsa-macro.h"
  36. #define DRV_NAME "qcs405-asoc-snd"
  37. #define __CHIPSET__ "QCS405 "
  38. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  39. #define DEV_NAME_STR_LEN 32
  40. #define SAMPLING_RATE_8KHZ 8000
  41. #define SAMPLING_RATE_11P025KHZ 11025
  42. #define SAMPLING_RATE_16KHZ 16000
  43. #define SAMPLING_RATE_22P05KHZ 22050
  44. #define SAMPLING_RATE_32KHZ 32000
  45. #define SAMPLING_RATE_44P1KHZ 44100
  46. #define SAMPLING_RATE_48KHZ 48000
  47. #define SAMPLING_RATE_88P2KHZ 88200
  48. #define SAMPLING_RATE_96KHZ 96000
  49. #define SAMPLING_RATE_176P4KHZ 176400
  50. #define SAMPLING_RATE_192KHZ 192000
  51. #define SAMPLING_RATE_352P8KHZ 352800
  52. #define SAMPLING_RATE_384KHZ 384000
  53. #define SPDIF_TX_CORE_CLK_163_P84_MHZ 163840000
  54. #define TLMM_EAST_SPARE 0x07BA0000
  55. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  56. #define WSA8810_NAME_1 "wsa881x.20170211"
  57. #define WSA8810_NAME_2 "wsa881x.20170212"
  58. #define WCN_CDC_SLIM_RX_CH_MAX 2
  59. #define WCN_CDC_SLIM_TX_CH_MAX 4
  60. #define TDM_CHANNEL_MAX 8
  61. #define BT_SLIM_TX SLIM_TX_9
  62. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  63. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  64. enum {
  65. SLIM_RX_0 = 0,
  66. SLIM_RX_1,
  67. SLIM_RX_2,
  68. SLIM_RX_3,
  69. SLIM_RX_4,
  70. SLIM_RX_5,
  71. SLIM_RX_6,
  72. SLIM_RX_7,
  73. SLIM_RX_MAX,
  74. };
  75. enum {
  76. SLIM_TX_0 = 0,
  77. SLIM_TX_1,
  78. SLIM_TX_2,
  79. SLIM_TX_3,
  80. SLIM_TX_4,
  81. SLIM_TX_5,
  82. SLIM_TX_6,
  83. SLIM_TX_7,
  84. SLIM_TX_8,
  85. SLIM_TX_9,
  86. SLIM_TX_MAX,
  87. };
  88. enum {
  89. PRIM_MI2S = 0,
  90. SEC_MI2S,
  91. TERT_MI2S,
  92. QUAT_MI2S,
  93. QUIN_MI2S,
  94. SEN_MI2S,
  95. MI2S_MAX,
  96. };
  97. enum {
  98. PRIM_AUX_PCM = 0,
  99. SEC_AUX_PCM,
  100. TERT_AUX_PCM,
  101. QUAT_AUX_PCM,
  102. QUIN_AUX_PCM,
  103. SEN_AUX_PCM,
  104. AUX_PCM_MAX,
  105. };
  106. enum {
  107. WSA_CDC_DMA_RX_0 = 0,
  108. WSA_CDC_DMA_RX_1,
  109. CDC_DMA_RX_MAX,
  110. };
  111. enum {
  112. WSA_CDC_DMA_TX_0 = 0,
  113. WSA_CDC_DMA_TX_1,
  114. WSA_CDC_DMA_TX_2,
  115. VA_CDC_DMA_TX_0,
  116. VA_CDC_DMA_TX_1,
  117. CDC_DMA_TX_MAX,
  118. };
  119. enum {
  120. PRIM_SPDIF_RX = 0,
  121. SEC_SPDIF_RX,
  122. SPDIF_RX_MAX,
  123. };
  124. enum {
  125. PRIM_SPDIF_TX = 0,
  126. SEC_SPDIF_TX,
  127. SPDIF_TX_MAX,
  128. };
  129. struct mi2s_conf {
  130. struct mutex lock;
  131. u32 ref_cnt;
  132. u32 msm_is_mi2s_master;
  133. };
  134. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  135. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  136. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  137. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  138. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  139. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT,
  140. Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT
  141. };
  142. struct dev_config {
  143. u32 sample_rate;
  144. u32 bit_format;
  145. u32 channels;
  146. };
  147. struct msm_wsa881x_dev_info {
  148. struct device_node *of_node;
  149. u32 index;
  150. };
  151. struct msm_csra66x0_dev_info {
  152. struct device_node *of_node;
  153. u32 index;
  154. };
  155. struct msm_asoc_mach_data {
  156. struct snd_info_entry *codec_root;
  157. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  158. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  159. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  160. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  161. struct device_node *lineout_booster_gpio_p; /* used by pinctrl API */
  162. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  163. int dmic_01_gpio_cnt;
  164. int dmic_23_gpio_cnt;
  165. int dmic_45_gpio_cnt;
  166. int dmic_67_gpio_cnt;
  167. struct regulator *tdm_micb_supply;
  168. u32 tdm_micb_voltage;
  169. u32 tdm_micb_current;
  170. bool codec_is_csra;
  171. };
  172. struct msm_asoc_wcd93xx_codec {
  173. void* (*get_afe_config_fn)(struct snd_soc_component *component,
  174. enum afe_config_type config_type);
  175. };
  176. static const char *const pin_states[] = {"sleep", "i2s-active",
  177. "tdm-active"};
  178. enum {
  179. TDM_0 = 0,
  180. TDM_1,
  181. TDM_2,
  182. TDM_3,
  183. TDM_4,
  184. TDM_5,
  185. TDM_6,
  186. TDM_7,
  187. TDM_PORT_MAX,
  188. };
  189. enum {
  190. TDM_PRI = 0,
  191. TDM_SEC,
  192. TDM_TERT,
  193. TDM_QUAT,
  194. TDM_QUIN,
  195. TDM_INTERFACE_MAX,
  196. };
  197. struct tdm_port {
  198. u32 mode;
  199. u32 channel;
  200. };
  201. /* TDM default config */
  202. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  203. { /* PRI TDM */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  205. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  206. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  212. },
  213. { /* SEC TDM */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  222. },
  223. { /* TERT TDM */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  232. },
  233. { /* QUAT TDM */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  242. },
  243. { /* QUIN TDM */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  252. }
  253. };
  254. /* TDM default config */
  255. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  256. { /* PRI TDM */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  265. },
  266. { /* SEC TDM */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  275. },
  276. { /* TERT TDM */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  285. },
  286. { /* QUAT TDM */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  295. },
  296. { /* QUIN TDM */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  305. }
  306. };
  307. /* Default configuration of slimbus channels */
  308. static struct dev_config slim_rx_cfg[] = {
  309. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  311. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. };
  318. static struct dev_config slim_tx_cfg[] = {
  319. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  326. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  327. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  328. [SLIM_TX_9] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  329. };
  330. /* Default configuration of Codec DMA Interface Tx */
  331. static struct dev_config cdc_dma_rx_cfg[] = {
  332. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  334. };
  335. /* Default configuration of Codec DMA Interface Rx */
  336. static struct dev_config cdc_dma_tx_cfg[] = {
  337. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  338. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  339. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  340. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  341. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  342. };
  343. static struct dev_config usb_rx_cfg = {
  344. .sample_rate = SAMPLING_RATE_48KHZ,
  345. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  346. .channels = 2,
  347. };
  348. static struct dev_config usb_tx_cfg = {
  349. .sample_rate = SAMPLING_RATE_48KHZ,
  350. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  351. .channels = 1,
  352. };
  353. static struct dev_config proxy_rx_cfg = {
  354. .sample_rate = SAMPLING_RATE_48KHZ,
  355. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  356. .channels = 2,
  357. };
  358. /* Default configuration of MI2S channels */
  359. static struct dev_config mi2s_rx_cfg[] = {
  360. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  361. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  362. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  363. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  364. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  365. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  366. };
  367. /* Default configuration of SPDIF channels */
  368. static struct dev_config spdif_rx_cfg[] = {
  369. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  370. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  371. };
  372. static struct dev_config spdif_tx_cfg[] = {
  373. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  374. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  375. };
  376. static struct dev_config mi2s_tx_cfg[] = {
  377. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  378. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  379. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  380. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  381. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  382. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  383. };
  384. static struct dev_config aux_pcm_rx_cfg[] = {
  385. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  386. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  387. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  388. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  389. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  390. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  391. };
  392. static struct dev_config aux_pcm_tx_cfg[] = {
  393. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  399. };
  400. static struct dev_config afe_lb_tx_cfg = {
  401. .sample_rate = SAMPLING_RATE_48KHZ,
  402. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  403. .channels = 2,
  404. };
  405. static int msm_vi_feed_tx_ch = 2;
  406. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  407. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  408. "Five", "Six", "Seven",
  409. "Eight"};
  410. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  411. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  412. "S32_LE"};
  413. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  414. "KHZ_32", "KHZ_44P1", "KHZ_48",
  415. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  416. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  417. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  418. "KHZ_44P1", "KHZ_48",
  419. "KHZ_88P2", "KHZ_96"};
  420. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  421. "Five", "Six", "Seven",
  422. "Eight"};
  423. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  424. "Six", "Seven", "Eight"};
  425. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  426. "KHZ_16", "KHZ_22P05",
  427. "KHZ_32", "KHZ_44P1", "KHZ_48",
  428. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  429. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  430. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  431. "Five", "Six", "Seven", "Eight"};
  432. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  433. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  434. "KHZ_48", "KHZ_176P4",
  435. "KHZ_352P8"};
  436. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  437. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  438. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  439. "KHZ_48", "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  440. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  441. static const char *const mi2s_ch_text[] = {
  442. "One", "Two", "Three", "Four", "Five", "Six", "Seven",
  443. "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
  444. "Fourteen", "Fifteen", "Sixteen"
  445. };
  446. static const char *const qos_text[] = {"Disable", "Enable"};
  447. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  448. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  449. "Five", "Six", "Seven", "Eight", "Nine", "Ten", "Eleven",
  450. "Twelve", "Thirteen", "Fourteen", "Fifteen", "Sixteen"};
  451. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  452. "KHZ_16", "KHZ_22P05",
  453. "KHZ_32", "KHZ_44P1", "KHZ_48",
  454. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  455. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  456. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  457. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  458. "KHZ_192"};
  459. static const char *spdif_ch_text[] = {"One", "Two"};
  460. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  461. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_sink, bt_sample_rate_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  546. cdc_dma_sample_rate_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  548. cdc_dma_sample_rate_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  550. cdc_dma_sample_rate_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  552. cdc_dma_sample_rate_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  554. cdc_dma_sample_rate_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  556. cdc_dma_sample_rate_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  558. cdc_dma_sample_rate_text);
  559. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  562. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  563. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  564. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  565. static SOC_ENUM_SINGLE_EXT_DECL(afe_lb_tx_chs, cdc_dma_tx_ch_text);
  566. static SOC_ENUM_SINGLE_EXT_DECL(afe_lb_tx_format, bit_format_text);
  567. static SOC_ENUM_SINGLE_EXT_DECL(afe_lb_tx_sample_rate,
  568. cdc_dma_sample_rate_text);
  569. static struct platform_device *spdev;
  570. static bool is_initial_boot;
  571. static bool codec_reg_done;
  572. static struct snd_soc_aux_dev *msm_aux_dev;
  573. static struct snd_soc_codec_conf *msm_codec_conf;
  574. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  575. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  576. int enable, bool dapm);
  577. static int msm_wsa881x_init(struct snd_soc_component *component);
  578. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  579. struct snd_ctl_elem_value *ucontrol);
  580. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  581. {"MIC BIAS1", NULL, "MCLK TX"},
  582. {"MIC BIAS2", NULL, "MCLK TX"},
  583. {"MIC BIAS3", NULL, "MCLK TX"},
  584. {"MIC BIAS4", NULL, "MCLK TX"},
  585. };
  586. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  587. {
  588. AFE_API_VERSION_I2S_CONFIG,
  589. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  590. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  591. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  592. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  593. 0,
  594. },
  595. {
  596. AFE_API_VERSION_I2S_CONFIG,
  597. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  598. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  599. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  600. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  601. 0,
  602. },
  603. {
  604. AFE_API_VERSION_I2S_CONFIG,
  605. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  606. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  607. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  608. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  609. 0,
  610. },
  611. {
  612. AFE_API_VERSION_I2S_CONFIG,
  613. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  614. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  615. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  616. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  617. 0,
  618. },
  619. {
  620. AFE_API_VERSION_I2S_CONFIG,
  621. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  622. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  623. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  624. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  625. 0,
  626. },
  627. {
  628. AFE_API_VERSION_I2S_CONFIG,
  629. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  630. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  631. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  632. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  633. 0,
  634. }
  635. };
  636. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  637. static int msm_island_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  638. {
  639. *port_id = 0xFFFF;
  640. switch (be_id) {
  641. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  642. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  643. break;
  644. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  645. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  646. break;
  647. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  648. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  649. break;
  650. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  651. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  652. break;
  653. default:
  654. return -EINVAL;
  655. }
  656. return 0;
  657. }
  658. static int qcs405_send_island_vad_config(int32_t be_id)
  659. {
  660. int rc = 0;
  661. int port_id = 0xFFFF;
  662. rc = msm_island_vad_get_portid_from_beid(be_id, &port_id);
  663. if (rc) {
  664. pr_debug("%s: Invalid island interface\n", __func__);
  665. } else {
  666. /*
  667. * send island mode config
  668. * This should be the first configuration
  669. */
  670. rc = afe_send_port_island_mode(port_id);
  671. if (rc) {
  672. pr_err("%s: afe send island mode failed %d\n",
  673. __func__, rc);
  674. return rc;
  675. }
  676. rc = afe_send_port_vad_cfg_params(port_id);
  677. if (rc) {
  678. pr_err("%s: afe send vad config failed %d\n",
  679. __func__, rc);
  680. return rc;
  681. }
  682. }
  683. return 0;
  684. }
  685. static int slim_get_sample_rate_val(int sample_rate)
  686. {
  687. int sample_rate_val = 0;
  688. switch (sample_rate) {
  689. case SAMPLING_RATE_8KHZ:
  690. sample_rate_val = 0;
  691. break;
  692. case SAMPLING_RATE_16KHZ:
  693. sample_rate_val = 1;
  694. break;
  695. case SAMPLING_RATE_32KHZ:
  696. sample_rate_val = 2;
  697. break;
  698. case SAMPLING_RATE_44P1KHZ:
  699. sample_rate_val = 3;
  700. break;
  701. case SAMPLING_RATE_48KHZ:
  702. sample_rate_val = 4;
  703. break;
  704. case SAMPLING_RATE_88P2KHZ:
  705. sample_rate_val = 5;
  706. break;
  707. case SAMPLING_RATE_96KHZ:
  708. sample_rate_val = 6;
  709. break;
  710. case SAMPLING_RATE_176P4KHZ:
  711. sample_rate_val = 7;
  712. break;
  713. case SAMPLING_RATE_192KHZ:
  714. sample_rate_val = 8;
  715. break;
  716. case SAMPLING_RATE_352P8KHZ:
  717. sample_rate_val = 9;
  718. break;
  719. case SAMPLING_RATE_384KHZ:
  720. sample_rate_val = 10;
  721. break;
  722. default:
  723. sample_rate_val = 4;
  724. break;
  725. }
  726. return sample_rate_val;
  727. }
  728. static int slim_get_sample_rate(int value)
  729. {
  730. int sample_rate = 0;
  731. switch (value) {
  732. case 0:
  733. sample_rate = SAMPLING_RATE_8KHZ;
  734. break;
  735. case 1:
  736. sample_rate = SAMPLING_RATE_16KHZ;
  737. break;
  738. case 2:
  739. sample_rate = SAMPLING_RATE_32KHZ;
  740. break;
  741. case 3:
  742. sample_rate = SAMPLING_RATE_44P1KHZ;
  743. break;
  744. case 4:
  745. sample_rate = SAMPLING_RATE_48KHZ;
  746. break;
  747. case 5:
  748. sample_rate = SAMPLING_RATE_88P2KHZ;
  749. break;
  750. case 6:
  751. sample_rate = SAMPLING_RATE_96KHZ;
  752. break;
  753. case 7:
  754. sample_rate = SAMPLING_RATE_176P4KHZ;
  755. break;
  756. case 8:
  757. sample_rate = SAMPLING_RATE_192KHZ;
  758. break;
  759. case 9:
  760. sample_rate = SAMPLING_RATE_352P8KHZ;
  761. break;
  762. case 10:
  763. sample_rate = SAMPLING_RATE_384KHZ;
  764. break;
  765. default:
  766. sample_rate = SAMPLING_RATE_48KHZ;
  767. break;
  768. }
  769. return sample_rate;
  770. }
  771. static int slim_get_bit_format_val(int bit_format)
  772. {
  773. int val = 0;
  774. switch (bit_format) {
  775. case SNDRV_PCM_FORMAT_S32_LE:
  776. val = 3;
  777. break;
  778. case SNDRV_PCM_FORMAT_S24_3LE:
  779. val = 2;
  780. break;
  781. case SNDRV_PCM_FORMAT_S24_LE:
  782. val = 1;
  783. break;
  784. case SNDRV_PCM_FORMAT_S16_LE:
  785. default:
  786. val = 0;
  787. break;
  788. }
  789. return val;
  790. }
  791. static int slim_get_bit_format(int val)
  792. {
  793. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  794. switch (val) {
  795. case 0:
  796. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  797. break;
  798. case 1:
  799. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  800. break;
  801. case 2:
  802. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  803. break;
  804. case 3:
  805. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  806. break;
  807. default:
  808. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  809. break;
  810. }
  811. return bit_fmt;
  812. }
  813. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  814. {
  815. int port_id = 0;
  816. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  817. port_id = SLIM_RX_0;
  818. } else if (strnstr(kcontrol->id.name,
  819. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  820. port_id = SLIM_RX_2;
  821. } else if (strnstr(kcontrol->id.name,
  822. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  823. port_id = SLIM_RX_5;
  824. } else if (strnstr(kcontrol->id.name,
  825. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  826. port_id = SLIM_RX_6;
  827. } else if (strnstr(kcontrol->id.name,
  828. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  829. port_id = SLIM_TX_0;
  830. } else if (strnstr(kcontrol->id.name,
  831. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  832. port_id = SLIM_TX_1;
  833. } else {
  834. pr_err("%s: unsupported channel: %s",
  835. __func__, kcontrol->id.name);
  836. return -EINVAL;
  837. }
  838. return port_id;
  839. }
  840. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  841. struct snd_ctl_elem_value *ucontrol)
  842. {
  843. int ch_num = slim_get_port_idx(kcontrol);
  844. if (ch_num < 0)
  845. return ch_num;
  846. ucontrol->value.enumerated.item[0] =
  847. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  848. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  849. ch_num, slim_rx_cfg[ch_num].sample_rate,
  850. ucontrol->value.enumerated.item[0]);
  851. return 0;
  852. }
  853. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  854. struct snd_ctl_elem_value *ucontrol)
  855. {
  856. int ch_num = slim_get_port_idx(kcontrol);
  857. if (ch_num < 0)
  858. return ch_num;
  859. slim_rx_cfg[ch_num].sample_rate =
  860. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  861. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  862. ch_num, slim_rx_cfg[ch_num].sample_rate,
  863. ucontrol->value.enumerated.item[0]);
  864. return 0;
  865. }
  866. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  867. struct snd_ctl_elem_value *ucontrol)
  868. {
  869. int ch_num = slim_get_port_idx(kcontrol);
  870. if (ch_num < 0)
  871. return ch_num;
  872. ucontrol->value.enumerated.item[0] =
  873. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  874. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  875. ch_num, slim_tx_cfg[ch_num].sample_rate,
  876. ucontrol->value.enumerated.item[0]);
  877. return 0;
  878. }
  879. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  880. struct snd_ctl_elem_value *ucontrol)
  881. {
  882. int sample_rate = 0;
  883. int ch_num = slim_get_port_idx(kcontrol);
  884. if (ch_num < 0)
  885. return ch_num;
  886. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  887. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  888. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  889. __func__, sample_rate);
  890. return -EINVAL;
  891. }
  892. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  893. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  894. ch_num, slim_tx_cfg[ch_num].sample_rate,
  895. ucontrol->value.enumerated.item[0]);
  896. return 0;
  897. }
  898. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  899. struct snd_ctl_elem_value *ucontrol)
  900. {
  901. int ch_num = slim_get_port_idx(kcontrol);
  902. if (ch_num < 0)
  903. return ch_num;
  904. ucontrol->value.enumerated.item[0] =
  905. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  906. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  907. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  908. ucontrol->value.enumerated.item[0]);
  909. return 0;
  910. }
  911. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  912. struct snd_ctl_elem_value *ucontrol)
  913. {
  914. int ch_num = slim_get_port_idx(kcontrol);
  915. if (ch_num < 0)
  916. return ch_num;
  917. slim_rx_cfg[ch_num].bit_format =
  918. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  919. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  920. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  921. ucontrol->value.enumerated.item[0]);
  922. return 0;
  923. }
  924. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  925. struct snd_ctl_elem_value *ucontrol)
  926. {
  927. int ch_num = slim_get_port_idx(kcontrol);
  928. if (ch_num < 0)
  929. return ch_num;
  930. ucontrol->value.enumerated.item[0] =
  931. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  932. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  933. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  934. ucontrol->value.enumerated.item[0]);
  935. return 0;
  936. }
  937. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  938. struct snd_ctl_elem_value *ucontrol)
  939. {
  940. int ch_num = slim_get_port_idx(kcontrol);
  941. if (ch_num < 0)
  942. return ch_num;
  943. slim_tx_cfg[ch_num].bit_format =
  944. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  945. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  946. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  947. ucontrol->value.enumerated.item[0]);
  948. return 0;
  949. }
  950. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  951. struct snd_ctl_elem_value *ucontrol)
  952. {
  953. int ch_num = slim_get_port_idx(kcontrol);
  954. if (ch_num < 0)
  955. return ch_num;
  956. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  957. ch_num, slim_rx_cfg[ch_num].channels);
  958. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  959. return 0;
  960. }
  961. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  962. struct snd_ctl_elem_value *ucontrol)
  963. {
  964. int ch_num = slim_get_port_idx(kcontrol);
  965. if (ch_num < 0)
  966. return ch_num;
  967. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  968. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  969. ch_num, slim_rx_cfg[ch_num].channels);
  970. return 1;
  971. }
  972. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  973. struct snd_ctl_elem_value *ucontrol)
  974. {
  975. int ch_num = slim_get_port_idx(kcontrol);
  976. if (ch_num < 0)
  977. return ch_num;
  978. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  979. ch_num, slim_tx_cfg[ch_num].channels);
  980. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  981. return 0;
  982. }
  983. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  984. struct snd_ctl_elem_value *ucontrol)
  985. {
  986. int ch_num = slim_get_port_idx(kcontrol);
  987. if (ch_num < 0)
  988. return ch_num;
  989. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  990. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  991. ch_num, slim_tx_cfg[ch_num].channels);
  992. return 1;
  993. }
  994. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  995. struct snd_ctl_elem_value *ucontrol)
  996. {
  997. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  998. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  999. ucontrol->value.integer.value[0]);
  1000. return 0;
  1001. }
  1002. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1003. struct snd_ctl_elem_value *ucontrol)
  1004. {
  1005. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1006. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1007. return 1;
  1008. }
  1009. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  1010. struct snd_ctl_elem_value *ucontrol)
  1011. {
  1012. /*
  1013. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  1014. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  1015. * value.
  1016. */
  1017. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  1018. case SAMPLING_RATE_96KHZ:
  1019. ucontrol->value.integer.value[0] = 5;
  1020. break;
  1021. case SAMPLING_RATE_88P2KHZ:
  1022. ucontrol->value.integer.value[0] = 4;
  1023. break;
  1024. case SAMPLING_RATE_48KHZ:
  1025. ucontrol->value.integer.value[0] = 3;
  1026. break;
  1027. case SAMPLING_RATE_44P1KHZ:
  1028. ucontrol->value.integer.value[0] = 2;
  1029. break;
  1030. case SAMPLING_RATE_16KHZ:
  1031. ucontrol->value.integer.value[0] = 1;
  1032. break;
  1033. case SAMPLING_RATE_8KHZ:
  1034. default:
  1035. ucontrol->value.integer.value[0] = 0;
  1036. break;
  1037. }
  1038. pr_debug("%s: sample rate = %d", __func__,
  1039. slim_rx_cfg[SLIM_RX_7].sample_rate);
  1040. return 0;
  1041. }
  1042. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  1043. struct snd_ctl_elem_value *ucontrol)
  1044. {
  1045. switch (ucontrol->value.integer.value[0]) {
  1046. case 1:
  1047. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  1048. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  1049. break;
  1050. case 2:
  1051. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  1052. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  1053. break;
  1054. case 3:
  1055. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1056. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1057. break;
  1058. case 4:
  1059. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1060. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1061. break;
  1062. case 5:
  1063. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1064. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1065. break;
  1066. case 0:
  1067. default:
  1068. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1069. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1070. break;
  1071. }
  1072. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1073. __func__,
  1074. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1075. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1076. ucontrol->value.enumerated.item[0]);
  1077. return 0;
  1078. }
  1079. static int msm_bt_sample_rate_sink_get(struct snd_kcontrol *kcontrol,
  1080. struct snd_ctl_elem_value *ucontrol)
  1081. {
  1082. switch (slim_tx_cfg[BT_SLIM_TX].sample_rate) {
  1083. case SAMPLING_RATE_96KHZ:
  1084. ucontrol->value.integer.value[0] = 5;
  1085. break;
  1086. case SAMPLING_RATE_88P2KHZ:
  1087. ucontrol->value.integer.value[0] = 4;
  1088. break;
  1089. case SAMPLING_RATE_48KHZ:
  1090. ucontrol->value.integer.value[0] = 3;
  1091. break;
  1092. case SAMPLING_RATE_44P1KHZ:
  1093. ucontrol->value.integer.value[0] = 2;
  1094. break;
  1095. case SAMPLING_RATE_16KHZ:
  1096. ucontrol->value.integer.value[0] = 1;
  1097. break;
  1098. case SAMPLING_RATE_8KHZ:
  1099. default:
  1100. ucontrol->value.integer.value[0] = 0;
  1101. break;
  1102. }
  1103. pr_debug("%s: sample rate = %d", __func__,
  1104. slim_tx_cfg[BT_SLIM_TX].sample_rate);
  1105. return 0;
  1106. }
  1107. static int msm_bt_sample_rate_sink_put(struct snd_kcontrol *kcontrol,
  1108. struct snd_ctl_elem_value *ucontrol)
  1109. {
  1110. switch (ucontrol->value.integer.value[0]) {
  1111. case 1:
  1112. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_16KHZ;
  1113. break;
  1114. case 2:
  1115. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_44P1KHZ;
  1116. break;
  1117. case 3:
  1118. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_48KHZ;
  1119. break;
  1120. case 4:
  1121. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_88P2KHZ;
  1122. break;
  1123. case 5:
  1124. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_96KHZ;
  1125. break;
  1126. case 0:
  1127. default:
  1128. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_8KHZ;
  1129. break;
  1130. }
  1131. pr_debug("%s: sample rate = %d, value = %d\n",
  1132. __func__,
  1133. slim_tx_cfg[BT_SLIM_TX].sample_rate,
  1134. ucontrol->value.enumerated.item[0]);
  1135. return 0;
  1136. }
  1137. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1138. {
  1139. int idx = 0;
  1140. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1141. sizeof("WSA_CDC_DMA_RX_0")))
  1142. idx = WSA_CDC_DMA_RX_0;
  1143. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1144. sizeof("WSA_CDC_DMA_RX_0")))
  1145. idx = WSA_CDC_DMA_RX_1;
  1146. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1147. sizeof("WSA_CDC_DMA_TX_0")))
  1148. idx = WSA_CDC_DMA_TX_0;
  1149. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1150. sizeof("WSA_CDC_DMA_TX_1")))
  1151. idx = WSA_CDC_DMA_TX_1;
  1152. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1153. sizeof("WSA_CDC_DMA_TX_2")))
  1154. idx = WSA_CDC_DMA_TX_2;
  1155. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1156. sizeof("VA_CDC_DMA_TX_0")))
  1157. idx = VA_CDC_DMA_TX_0;
  1158. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1159. sizeof("VA_CDC_DMA_TX_1")))
  1160. idx = VA_CDC_DMA_TX_1;
  1161. else {
  1162. pr_err("%s: unsupported port: %s\n",
  1163. __func__, kcontrol->id.name);
  1164. return -EINVAL;
  1165. }
  1166. return idx;
  1167. }
  1168. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1169. struct snd_ctl_elem_value *ucontrol)
  1170. {
  1171. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1172. if (ch_num < 0)
  1173. return ch_num;
  1174. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1175. cdc_dma_rx_cfg[ch_num].channels - 1);
  1176. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1177. return 0;
  1178. }
  1179. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1180. struct snd_ctl_elem_value *ucontrol)
  1181. {
  1182. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1183. if (ch_num < 0)
  1184. return ch_num;
  1185. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1186. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1187. cdc_dma_rx_cfg[ch_num].channels);
  1188. return 1;
  1189. }
  1190. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1191. struct snd_ctl_elem_value *ucontrol)
  1192. {
  1193. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1194. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1195. case SNDRV_PCM_FORMAT_S32_LE:
  1196. ucontrol->value.integer.value[0] = 3;
  1197. break;
  1198. case SNDRV_PCM_FORMAT_S24_3LE:
  1199. ucontrol->value.integer.value[0] = 2;
  1200. break;
  1201. case SNDRV_PCM_FORMAT_S24_LE:
  1202. ucontrol->value.integer.value[0] = 1;
  1203. break;
  1204. case SNDRV_PCM_FORMAT_S16_LE:
  1205. default:
  1206. ucontrol->value.integer.value[0] = 0;
  1207. break;
  1208. }
  1209. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1210. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1211. ucontrol->value.integer.value[0]);
  1212. return 0;
  1213. }
  1214. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1215. struct snd_ctl_elem_value *ucontrol)
  1216. {
  1217. int rc = 0;
  1218. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1219. switch (ucontrol->value.integer.value[0]) {
  1220. case 3:
  1221. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1222. break;
  1223. case 2:
  1224. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1225. break;
  1226. case 1:
  1227. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1228. break;
  1229. case 0:
  1230. default:
  1231. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1232. break;
  1233. }
  1234. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1235. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1236. ucontrol->value.integer.value[0]);
  1237. return rc;
  1238. }
  1239. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1240. {
  1241. int sample_rate_val = 0;
  1242. switch (sample_rate) {
  1243. case SAMPLING_RATE_8KHZ:
  1244. sample_rate_val = 0;
  1245. break;
  1246. case SAMPLING_RATE_11P025KHZ:
  1247. sample_rate_val = 1;
  1248. break;
  1249. case SAMPLING_RATE_16KHZ:
  1250. sample_rate_val = 2;
  1251. break;
  1252. case SAMPLING_RATE_22P05KHZ:
  1253. sample_rate_val = 3;
  1254. break;
  1255. case SAMPLING_RATE_32KHZ:
  1256. sample_rate_val = 4;
  1257. break;
  1258. case SAMPLING_RATE_44P1KHZ:
  1259. sample_rate_val = 5;
  1260. break;
  1261. case SAMPLING_RATE_48KHZ:
  1262. sample_rate_val = 6;
  1263. break;
  1264. case SAMPLING_RATE_88P2KHZ:
  1265. sample_rate_val = 7;
  1266. break;
  1267. case SAMPLING_RATE_96KHZ:
  1268. sample_rate_val = 8;
  1269. break;
  1270. case SAMPLING_RATE_176P4KHZ:
  1271. sample_rate_val = 9;
  1272. break;
  1273. case SAMPLING_RATE_192KHZ:
  1274. sample_rate_val = 10;
  1275. break;
  1276. case SAMPLING_RATE_352P8KHZ:
  1277. sample_rate_val = 11;
  1278. break;
  1279. case SAMPLING_RATE_384KHZ:
  1280. sample_rate_val = 12;
  1281. break;
  1282. default:
  1283. sample_rate_val = 6;
  1284. break;
  1285. }
  1286. return sample_rate_val;
  1287. }
  1288. static int cdc_dma_get_sample_rate(int value)
  1289. {
  1290. int sample_rate = 0;
  1291. switch (value) {
  1292. case 0:
  1293. sample_rate = SAMPLING_RATE_8KHZ;
  1294. break;
  1295. case 1:
  1296. sample_rate = SAMPLING_RATE_11P025KHZ;
  1297. break;
  1298. case 2:
  1299. sample_rate = SAMPLING_RATE_16KHZ;
  1300. break;
  1301. case 3:
  1302. sample_rate = SAMPLING_RATE_22P05KHZ;
  1303. break;
  1304. case 4:
  1305. sample_rate = SAMPLING_RATE_32KHZ;
  1306. break;
  1307. case 5:
  1308. sample_rate = SAMPLING_RATE_44P1KHZ;
  1309. break;
  1310. case 6:
  1311. sample_rate = SAMPLING_RATE_48KHZ;
  1312. break;
  1313. case 7:
  1314. sample_rate = SAMPLING_RATE_88P2KHZ;
  1315. break;
  1316. case 8:
  1317. sample_rate = SAMPLING_RATE_96KHZ;
  1318. break;
  1319. case 9:
  1320. sample_rate = SAMPLING_RATE_176P4KHZ;
  1321. break;
  1322. case 10:
  1323. sample_rate = SAMPLING_RATE_192KHZ;
  1324. break;
  1325. case 11:
  1326. sample_rate = SAMPLING_RATE_352P8KHZ;
  1327. break;
  1328. case 12:
  1329. sample_rate = SAMPLING_RATE_384KHZ;
  1330. break;
  1331. default:
  1332. sample_rate = SAMPLING_RATE_48KHZ;
  1333. break;
  1334. }
  1335. return sample_rate;
  1336. }
  1337. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1338. struct snd_ctl_elem_value *ucontrol)
  1339. {
  1340. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1341. if (ch_num < 0)
  1342. return ch_num;
  1343. ucontrol->value.enumerated.item[0] =
  1344. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1345. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1346. cdc_dma_rx_cfg[ch_num].sample_rate);
  1347. return 0;
  1348. }
  1349. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1350. struct snd_ctl_elem_value *ucontrol)
  1351. {
  1352. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1353. if (ch_num < 0)
  1354. return ch_num;
  1355. cdc_dma_rx_cfg[ch_num].sample_rate =
  1356. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1357. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1358. __func__, ucontrol->value.enumerated.item[0],
  1359. cdc_dma_rx_cfg[ch_num].sample_rate);
  1360. return 0;
  1361. }
  1362. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1363. struct snd_ctl_elem_value *ucontrol)
  1364. {
  1365. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1366. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1367. cdc_dma_tx_cfg[ch_num].channels);
  1368. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1369. return 0;
  1370. }
  1371. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1372. struct snd_ctl_elem_value *ucontrol)
  1373. {
  1374. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1375. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1376. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1377. cdc_dma_tx_cfg[ch_num].channels);
  1378. return 1;
  1379. }
  1380. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1381. struct snd_ctl_elem_value *ucontrol)
  1382. {
  1383. int sample_rate_val;
  1384. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1385. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1386. case SAMPLING_RATE_384KHZ:
  1387. sample_rate_val = 12;
  1388. break;
  1389. case SAMPLING_RATE_352P8KHZ:
  1390. sample_rate_val = 11;
  1391. break;
  1392. case SAMPLING_RATE_192KHZ:
  1393. sample_rate_val = 10;
  1394. break;
  1395. case SAMPLING_RATE_176P4KHZ:
  1396. sample_rate_val = 9;
  1397. break;
  1398. case SAMPLING_RATE_96KHZ:
  1399. sample_rate_val = 8;
  1400. break;
  1401. case SAMPLING_RATE_88P2KHZ:
  1402. sample_rate_val = 7;
  1403. break;
  1404. case SAMPLING_RATE_48KHZ:
  1405. sample_rate_val = 6;
  1406. break;
  1407. case SAMPLING_RATE_44P1KHZ:
  1408. sample_rate_val = 5;
  1409. break;
  1410. case SAMPLING_RATE_32KHZ:
  1411. sample_rate_val = 4;
  1412. break;
  1413. case SAMPLING_RATE_22P05KHZ:
  1414. sample_rate_val = 3;
  1415. break;
  1416. case SAMPLING_RATE_16KHZ:
  1417. sample_rate_val = 2;
  1418. break;
  1419. case SAMPLING_RATE_11P025KHZ:
  1420. sample_rate_val = 1;
  1421. break;
  1422. case SAMPLING_RATE_8KHZ:
  1423. sample_rate_val = 0;
  1424. break;
  1425. default:
  1426. sample_rate_val = 6;
  1427. break;
  1428. }
  1429. ucontrol->value.integer.value[0] = sample_rate_val;
  1430. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1431. cdc_dma_tx_cfg[ch_num].sample_rate);
  1432. return 0;
  1433. }
  1434. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1435. struct snd_ctl_elem_value *ucontrol)
  1436. {
  1437. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1438. switch (ucontrol->value.integer.value[0]) {
  1439. case 12:
  1440. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1441. break;
  1442. case 11:
  1443. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1444. break;
  1445. case 10:
  1446. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1447. break;
  1448. case 9:
  1449. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1450. break;
  1451. case 8:
  1452. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1453. break;
  1454. case 7:
  1455. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1456. break;
  1457. case 6:
  1458. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1459. break;
  1460. case 5:
  1461. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1462. break;
  1463. case 4:
  1464. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1465. break;
  1466. case 3:
  1467. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1468. break;
  1469. case 2:
  1470. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1471. break;
  1472. case 1:
  1473. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1474. break;
  1475. case 0:
  1476. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1477. break;
  1478. default:
  1479. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1480. break;
  1481. }
  1482. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1483. __func__, ucontrol->value.integer.value[0],
  1484. cdc_dma_tx_cfg[ch_num].sample_rate);
  1485. return 0;
  1486. }
  1487. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1488. struct snd_ctl_elem_value *ucontrol)
  1489. {
  1490. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1491. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1492. case SNDRV_PCM_FORMAT_S32_LE:
  1493. ucontrol->value.integer.value[0] = 3;
  1494. break;
  1495. case SNDRV_PCM_FORMAT_S24_3LE:
  1496. ucontrol->value.integer.value[0] = 2;
  1497. break;
  1498. case SNDRV_PCM_FORMAT_S24_LE:
  1499. ucontrol->value.integer.value[0] = 1;
  1500. break;
  1501. case SNDRV_PCM_FORMAT_S16_LE:
  1502. default:
  1503. ucontrol->value.integer.value[0] = 0;
  1504. break;
  1505. }
  1506. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1507. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1508. ucontrol->value.integer.value[0]);
  1509. return 0;
  1510. }
  1511. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1512. struct snd_ctl_elem_value *ucontrol)
  1513. {
  1514. int rc = 0;
  1515. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1516. switch (ucontrol->value.integer.value[0]) {
  1517. case 3:
  1518. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1519. break;
  1520. case 2:
  1521. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1522. break;
  1523. case 1:
  1524. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1525. break;
  1526. case 0:
  1527. default:
  1528. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1529. break;
  1530. }
  1531. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1532. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1533. ucontrol->value.integer.value[0]);
  1534. return rc;
  1535. }
  1536. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1537. struct snd_ctl_elem_value *ucontrol)
  1538. {
  1539. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1540. usb_rx_cfg.channels);
  1541. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1542. return 0;
  1543. }
  1544. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1545. struct snd_ctl_elem_value *ucontrol)
  1546. {
  1547. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1548. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1549. return 1;
  1550. }
  1551. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1552. struct snd_ctl_elem_value *ucontrol)
  1553. {
  1554. int sample_rate_val;
  1555. switch (usb_rx_cfg.sample_rate) {
  1556. case SAMPLING_RATE_384KHZ:
  1557. sample_rate_val = 12;
  1558. break;
  1559. case SAMPLING_RATE_352P8KHZ:
  1560. sample_rate_val = 11;
  1561. break;
  1562. case SAMPLING_RATE_192KHZ:
  1563. sample_rate_val = 10;
  1564. break;
  1565. case SAMPLING_RATE_176P4KHZ:
  1566. sample_rate_val = 9;
  1567. break;
  1568. case SAMPLING_RATE_96KHZ:
  1569. sample_rate_val = 8;
  1570. break;
  1571. case SAMPLING_RATE_88P2KHZ:
  1572. sample_rate_val = 7;
  1573. break;
  1574. case SAMPLING_RATE_48KHZ:
  1575. sample_rate_val = 6;
  1576. break;
  1577. case SAMPLING_RATE_44P1KHZ:
  1578. sample_rate_val = 5;
  1579. break;
  1580. case SAMPLING_RATE_32KHZ:
  1581. sample_rate_val = 4;
  1582. break;
  1583. case SAMPLING_RATE_22P05KHZ:
  1584. sample_rate_val = 3;
  1585. break;
  1586. case SAMPLING_RATE_16KHZ:
  1587. sample_rate_val = 2;
  1588. break;
  1589. case SAMPLING_RATE_11P025KHZ:
  1590. sample_rate_val = 1;
  1591. break;
  1592. case SAMPLING_RATE_8KHZ:
  1593. default:
  1594. sample_rate_val = 0;
  1595. break;
  1596. }
  1597. ucontrol->value.integer.value[0] = sample_rate_val;
  1598. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1599. usb_rx_cfg.sample_rate);
  1600. return 0;
  1601. }
  1602. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1603. struct snd_ctl_elem_value *ucontrol)
  1604. {
  1605. switch (ucontrol->value.integer.value[0]) {
  1606. case 12:
  1607. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1608. break;
  1609. case 11:
  1610. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1611. break;
  1612. case 10:
  1613. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1614. break;
  1615. case 9:
  1616. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1617. break;
  1618. case 8:
  1619. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1620. break;
  1621. case 7:
  1622. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1623. break;
  1624. case 6:
  1625. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1626. break;
  1627. case 5:
  1628. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1629. break;
  1630. case 4:
  1631. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1632. break;
  1633. case 3:
  1634. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1635. break;
  1636. case 2:
  1637. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1638. break;
  1639. case 1:
  1640. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1641. break;
  1642. case 0:
  1643. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1644. break;
  1645. default:
  1646. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1647. break;
  1648. }
  1649. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1650. __func__, ucontrol->value.integer.value[0],
  1651. usb_rx_cfg.sample_rate);
  1652. return 0;
  1653. }
  1654. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1655. struct snd_ctl_elem_value *ucontrol)
  1656. {
  1657. switch (usb_rx_cfg.bit_format) {
  1658. case SNDRV_PCM_FORMAT_S32_LE:
  1659. ucontrol->value.integer.value[0] = 3;
  1660. break;
  1661. case SNDRV_PCM_FORMAT_S24_3LE:
  1662. ucontrol->value.integer.value[0] = 2;
  1663. break;
  1664. case SNDRV_PCM_FORMAT_S24_LE:
  1665. ucontrol->value.integer.value[0] = 1;
  1666. break;
  1667. case SNDRV_PCM_FORMAT_S16_LE:
  1668. default:
  1669. ucontrol->value.integer.value[0] = 0;
  1670. break;
  1671. }
  1672. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1673. __func__, usb_rx_cfg.bit_format,
  1674. ucontrol->value.integer.value[0]);
  1675. return 0;
  1676. }
  1677. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1678. struct snd_ctl_elem_value *ucontrol)
  1679. {
  1680. int rc = 0;
  1681. switch (ucontrol->value.integer.value[0]) {
  1682. case 3:
  1683. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1684. break;
  1685. case 2:
  1686. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1687. break;
  1688. case 1:
  1689. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1690. break;
  1691. case 0:
  1692. default:
  1693. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1694. break;
  1695. }
  1696. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1697. __func__, usb_rx_cfg.bit_format,
  1698. ucontrol->value.integer.value[0]);
  1699. return rc;
  1700. }
  1701. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1702. struct snd_ctl_elem_value *ucontrol)
  1703. {
  1704. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1705. usb_tx_cfg.channels);
  1706. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1707. return 0;
  1708. }
  1709. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1710. struct snd_ctl_elem_value *ucontrol)
  1711. {
  1712. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1713. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1714. return 1;
  1715. }
  1716. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1717. struct snd_ctl_elem_value *ucontrol)
  1718. {
  1719. int sample_rate_val;
  1720. switch (usb_tx_cfg.sample_rate) {
  1721. case SAMPLING_RATE_384KHZ:
  1722. sample_rate_val = 12;
  1723. break;
  1724. case SAMPLING_RATE_352P8KHZ:
  1725. sample_rate_val = 11;
  1726. break;
  1727. case SAMPLING_RATE_192KHZ:
  1728. sample_rate_val = 10;
  1729. break;
  1730. case SAMPLING_RATE_176P4KHZ:
  1731. sample_rate_val = 9;
  1732. break;
  1733. case SAMPLING_RATE_96KHZ:
  1734. sample_rate_val = 8;
  1735. break;
  1736. case SAMPLING_RATE_88P2KHZ:
  1737. sample_rate_val = 7;
  1738. break;
  1739. case SAMPLING_RATE_48KHZ:
  1740. sample_rate_val = 6;
  1741. break;
  1742. case SAMPLING_RATE_44P1KHZ:
  1743. sample_rate_val = 5;
  1744. break;
  1745. case SAMPLING_RATE_32KHZ:
  1746. sample_rate_val = 4;
  1747. break;
  1748. case SAMPLING_RATE_22P05KHZ:
  1749. sample_rate_val = 3;
  1750. break;
  1751. case SAMPLING_RATE_16KHZ:
  1752. sample_rate_val = 2;
  1753. break;
  1754. case SAMPLING_RATE_11P025KHZ:
  1755. sample_rate_val = 1;
  1756. break;
  1757. case SAMPLING_RATE_8KHZ:
  1758. sample_rate_val = 0;
  1759. break;
  1760. default:
  1761. sample_rate_val = 6;
  1762. break;
  1763. }
  1764. ucontrol->value.integer.value[0] = sample_rate_val;
  1765. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1766. usb_tx_cfg.sample_rate);
  1767. return 0;
  1768. }
  1769. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1770. struct snd_ctl_elem_value *ucontrol)
  1771. {
  1772. switch (ucontrol->value.integer.value[0]) {
  1773. case 12:
  1774. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1775. break;
  1776. case 11:
  1777. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1778. break;
  1779. case 10:
  1780. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1781. break;
  1782. case 9:
  1783. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1784. break;
  1785. case 8:
  1786. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1787. break;
  1788. case 7:
  1789. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1790. break;
  1791. case 6:
  1792. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1793. break;
  1794. case 5:
  1795. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1796. break;
  1797. case 4:
  1798. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1799. break;
  1800. case 3:
  1801. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1802. break;
  1803. case 2:
  1804. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1805. break;
  1806. case 1:
  1807. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1808. break;
  1809. case 0:
  1810. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1811. break;
  1812. default:
  1813. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1814. break;
  1815. }
  1816. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1817. __func__, ucontrol->value.integer.value[0],
  1818. usb_tx_cfg.sample_rate);
  1819. return 0;
  1820. }
  1821. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1822. struct snd_ctl_elem_value *ucontrol)
  1823. {
  1824. switch (usb_tx_cfg.bit_format) {
  1825. case SNDRV_PCM_FORMAT_S32_LE:
  1826. ucontrol->value.integer.value[0] = 3;
  1827. break;
  1828. case SNDRV_PCM_FORMAT_S24_3LE:
  1829. ucontrol->value.integer.value[0] = 2;
  1830. break;
  1831. case SNDRV_PCM_FORMAT_S24_LE:
  1832. ucontrol->value.integer.value[0] = 1;
  1833. break;
  1834. case SNDRV_PCM_FORMAT_S16_LE:
  1835. default:
  1836. ucontrol->value.integer.value[0] = 0;
  1837. break;
  1838. }
  1839. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1840. __func__, usb_tx_cfg.bit_format,
  1841. ucontrol->value.integer.value[0]);
  1842. return 0;
  1843. }
  1844. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1845. struct snd_ctl_elem_value *ucontrol)
  1846. {
  1847. int rc = 0;
  1848. switch (ucontrol->value.integer.value[0]) {
  1849. case 3:
  1850. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1851. break;
  1852. case 2:
  1853. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1854. break;
  1855. case 1:
  1856. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1857. break;
  1858. case 0:
  1859. default:
  1860. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1861. break;
  1862. }
  1863. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1864. __func__, usb_tx_cfg.bit_format,
  1865. ucontrol->value.integer.value[0]);
  1866. return rc;
  1867. }
  1868. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1869. struct snd_ctl_elem_value *ucontrol)
  1870. {
  1871. pr_debug("%s: proxy_rx channels = %d\n",
  1872. __func__, proxy_rx_cfg.channels);
  1873. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1874. return 0;
  1875. }
  1876. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1877. struct snd_ctl_elem_value *ucontrol)
  1878. {
  1879. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1880. pr_debug("%s: proxy_rx channels = %d\n",
  1881. __func__, proxy_rx_cfg.channels);
  1882. return 1;
  1883. }
  1884. static int tdm_get_sample_rate(int value)
  1885. {
  1886. int sample_rate = 0;
  1887. switch (value) {
  1888. case 0:
  1889. sample_rate = SAMPLING_RATE_8KHZ;
  1890. break;
  1891. case 1:
  1892. sample_rate = SAMPLING_RATE_16KHZ;
  1893. break;
  1894. case 2:
  1895. sample_rate = SAMPLING_RATE_32KHZ;
  1896. break;
  1897. case 3:
  1898. sample_rate = SAMPLING_RATE_48KHZ;
  1899. break;
  1900. case 4:
  1901. sample_rate = SAMPLING_RATE_176P4KHZ;
  1902. break;
  1903. case 5:
  1904. sample_rate = SAMPLING_RATE_352P8KHZ;
  1905. break;
  1906. default:
  1907. sample_rate = SAMPLING_RATE_48KHZ;
  1908. break;
  1909. }
  1910. return sample_rate;
  1911. }
  1912. static int aux_pcm_get_sample_rate(int value)
  1913. {
  1914. int sample_rate;
  1915. switch (value) {
  1916. case 1:
  1917. sample_rate = SAMPLING_RATE_16KHZ;
  1918. break;
  1919. case 0:
  1920. default:
  1921. sample_rate = SAMPLING_RATE_8KHZ;
  1922. break;
  1923. }
  1924. return sample_rate;
  1925. }
  1926. static int tdm_get_sample_rate_val(int sample_rate)
  1927. {
  1928. int sample_rate_val = 0;
  1929. switch (sample_rate) {
  1930. case SAMPLING_RATE_8KHZ:
  1931. sample_rate_val = 0;
  1932. break;
  1933. case SAMPLING_RATE_16KHZ:
  1934. sample_rate_val = 1;
  1935. break;
  1936. case SAMPLING_RATE_32KHZ:
  1937. sample_rate_val = 2;
  1938. break;
  1939. case SAMPLING_RATE_48KHZ:
  1940. sample_rate_val = 3;
  1941. break;
  1942. case SAMPLING_RATE_176P4KHZ:
  1943. sample_rate_val = 4;
  1944. break;
  1945. case SAMPLING_RATE_352P8KHZ:
  1946. sample_rate_val = 5;
  1947. break;
  1948. default:
  1949. sample_rate_val = 3;
  1950. break;
  1951. }
  1952. return sample_rate_val;
  1953. }
  1954. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1955. {
  1956. int sample_rate_val;
  1957. switch (sample_rate) {
  1958. case SAMPLING_RATE_16KHZ:
  1959. sample_rate_val = 1;
  1960. break;
  1961. case SAMPLING_RATE_8KHZ:
  1962. default:
  1963. sample_rate_val = 0;
  1964. break;
  1965. }
  1966. return sample_rate_val;
  1967. }
  1968. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1969. struct tdm_port *port)
  1970. {
  1971. if (port) {
  1972. if (strnstr(kcontrol->id.name, "PRI",
  1973. sizeof(kcontrol->id.name))) {
  1974. port->mode = TDM_PRI;
  1975. } else if (strnstr(kcontrol->id.name, "SEC",
  1976. sizeof(kcontrol->id.name))) {
  1977. port->mode = TDM_SEC;
  1978. } else if (strnstr(kcontrol->id.name, "TERT",
  1979. sizeof(kcontrol->id.name))) {
  1980. port->mode = TDM_TERT;
  1981. } else if (strnstr(kcontrol->id.name, "QUAT",
  1982. sizeof(kcontrol->id.name))) {
  1983. port->mode = TDM_QUAT;
  1984. } else if (strnstr(kcontrol->id.name, "QUIN",
  1985. sizeof(kcontrol->id.name))) {
  1986. port->mode = TDM_QUIN;
  1987. } else {
  1988. pr_err("%s: unsupported mode in: %s",
  1989. __func__, kcontrol->id.name);
  1990. return -EINVAL;
  1991. }
  1992. if (strnstr(kcontrol->id.name, "RX_0",
  1993. sizeof(kcontrol->id.name)) ||
  1994. strnstr(kcontrol->id.name, "TX_0",
  1995. sizeof(kcontrol->id.name))) {
  1996. port->channel = TDM_0;
  1997. } else if (strnstr(kcontrol->id.name, "RX_1",
  1998. sizeof(kcontrol->id.name)) ||
  1999. strnstr(kcontrol->id.name, "TX_1",
  2000. sizeof(kcontrol->id.name))) {
  2001. port->channel = TDM_1;
  2002. } else if (strnstr(kcontrol->id.name, "RX_2",
  2003. sizeof(kcontrol->id.name)) ||
  2004. strnstr(kcontrol->id.name, "TX_2",
  2005. sizeof(kcontrol->id.name))) {
  2006. port->channel = TDM_2;
  2007. } else if (strnstr(kcontrol->id.name, "RX_3",
  2008. sizeof(kcontrol->id.name)) ||
  2009. strnstr(kcontrol->id.name, "TX_3",
  2010. sizeof(kcontrol->id.name))) {
  2011. port->channel = TDM_3;
  2012. } else if (strnstr(kcontrol->id.name, "RX_4",
  2013. sizeof(kcontrol->id.name)) ||
  2014. strnstr(kcontrol->id.name, "TX_4",
  2015. sizeof(kcontrol->id.name))) {
  2016. port->channel = TDM_4;
  2017. } else if (strnstr(kcontrol->id.name, "RX_5",
  2018. sizeof(kcontrol->id.name)) ||
  2019. strnstr(kcontrol->id.name, "TX_5",
  2020. sizeof(kcontrol->id.name))) {
  2021. port->channel = TDM_5;
  2022. } else if (strnstr(kcontrol->id.name, "RX_6",
  2023. sizeof(kcontrol->id.name)) ||
  2024. strnstr(kcontrol->id.name, "TX_6",
  2025. sizeof(kcontrol->id.name))) {
  2026. port->channel = TDM_6;
  2027. } else if (strnstr(kcontrol->id.name, "RX_7",
  2028. sizeof(kcontrol->id.name)) ||
  2029. strnstr(kcontrol->id.name, "TX_7",
  2030. sizeof(kcontrol->id.name))) {
  2031. port->channel = TDM_7;
  2032. } else {
  2033. pr_err("%s: unsupported channel in: %s",
  2034. __func__, kcontrol->id.name);
  2035. return -EINVAL;
  2036. }
  2037. } else
  2038. return -EINVAL;
  2039. return 0;
  2040. }
  2041. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2042. struct snd_ctl_elem_value *ucontrol)
  2043. {
  2044. struct tdm_port port;
  2045. int ret = tdm_get_port_idx(kcontrol, &port);
  2046. if (ret) {
  2047. pr_err("%s: unsupported control: %s",
  2048. __func__, kcontrol->id.name);
  2049. } else {
  2050. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2051. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  2052. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2053. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2054. ucontrol->value.enumerated.item[0]);
  2055. }
  2056. return ret;
  2057. }
  2058. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2059. struct snd_ctl_elem_value *ucontrol)
  2060. {
  2061. struct tdm_port port;
  2062. int ret = tdm_get_port_idx(kcontrol, &port);
  2063. if (ret) {
  2064. pr_err("%s: unsupported control: %s",
  2065. __func__, kcontrol->id.name);
  2066. } else {
  2067. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  2068. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2069. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2070. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2071. ucontrol->value.enumerated.item[0]);
  2072. }
  2073. return ret;
  2074. }
  2075. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2076. struct snd_ctl_elem_value *ucontrol)
  2077. {
  2078. struct tdm_port port;
  2079. int ret = tdm_get_port_idx(kcontrol, &port);
  2080. if (ret) {
  2081. pr_err("%s: unsupported control: %s",
  2082. __func__, kcontrol->id.name);
  2083. } else {
  2084. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2085. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  2086. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2087. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2088. ucontrol->value.enumerated.item[0]);
  2089. }
  2090. return ret;
  2091. }
  2092. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2093. struct snd_ctl_elem_value *ucontrol)
  2094. {
  2095. struct tdm_port port;
  2096. int ret = tdm_get_port_idx(kcontrol, &port);
  2097. if (ret) {
  2098. pr_err("%s: unsupported control: %s",
  2099. __func__, kcontrol->id.name);
  2100. } else {
  2101. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  2102. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2103. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2104. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2105. ucontrol->value.enumerated.item[0]);
  2106. }
  2107. return ret;
  2108. }
  2109. static int tdm_get_format(int value)
  2110. {
  2111. int format = 0;
  2112. switch (value) {
  2113. case 0:
  2114. format = SNDRV_PCM_FORMAT_S16_LE;
  2115. break;
  2116. case 1:
  2117. format = SNDRV_PCM_FORMAT_S24_LE;
  2118. break;
  2119. case 2:
  2120. format = SNDRV_PCM_FORMAT_S32_LE;
  2121. break;
  2122. default:
  2123. format = SNDRV_PCM_FORMAT_S16_LE;
  2124. break;
  2125. }
  2126. return format;
  2127. }
  2128. static int tdm_get_format_val(int format)
  2129. {
  2130. int value = 0;
  2131. switch (format) {
  2132. case SNDRV_PCM_FORMAT_S16_LE:
  2133. value = 0;
  2134. break;
  2135. case SNDRV_PCM_FORMAT_S24_LE:
  2136. value = 1;
  2137. break;
  2138. case SNDRV_PCM_FORMAT_S32_LE:
  2139. value = 2;
  2140. break;
  2141. default:
  2142. value = 0;
  2143. break;
  2144. }
  2145. return value;
  2146. }
  2147. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2148. struct snd_ctl_elem_value *ucontrol)
  2149. {
  2150. struct tdm_port port;
  2151. int ret = tdm_get_port_idx(kcontrol, &port);
  2152. if (ret) {
  2153. pr_err("%s: unsupported control: %s",
  2154. __func__, kcontrol->id.name);
  2155. } else {
  2156. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2157. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2158. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2159. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2160. ucontrol->value.enumerated.item[0]);
  2161. }
  2162. return ret;
  2163. }
  2164. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2165. struct snd_ctl_elem_value *ucontrol)
  2166. {
  2167. struct tdm_port port;
  2168. int ret = tdm_get_port_idx(kcontrol, &port);
  2169. if (ret) {
  2170. pr_err("%s: unsupported control: %s",
  2171. __func__, kcontrol->id.name);
  2172. } else {
  2173. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2174. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2175. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2176. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2177. ucontrol->value.enumerated.item[0]);
  2178. }
  2179. return ret;
  2180. }
  2181. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2182. struct snd_ctl_elem_value *ucontrol)
  2183. {
  2184. struct tdm_port port;
  2185. int ret = tdm_get_port_idx(kcontrol, &port);
  2186. if (ret) {
  2187. pr_err("%s: unsupported control: %s",
  2188. __func__, kcontrol->id.name);
  2189. } else {
  2190. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2191. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2192. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2193. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2194. ucontrol->value.enumerated.item[0]);
  2195. }
  2196. return ret;
  2197. }
  2198. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2199. struct snd_ctl_elem_value *ucontrol)
  2200. {
  2201. struct tdm_port port;
  2202. int ret = tdm_get_port_idx(kcontrol, &port);
  2203. if (ret) {
  2204. pr_err("%s: unsupported control: %s",
  2205. __func__, kcontrol->id.name);
  2206. } else {
  2207. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2208. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2209. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2210. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2211. ucontrol->value.enumerated.item[0]);
  2212. }
  2213. return ret;
  2214. }
  2215. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2216. struct snd_ctl_elem_value *ucontrol)
  2217. {
  2218. struct tdm_port port;
  2219. int ret = tdm_get_port_idx(kcontrol, &port);
  2220. if (ret) {
  2221. pr_err("%s: unsupported control: %s",
  2222. __func__, kcontrol->id.name);
  2223. } else {
  2224. ucontrol->value.enumerated.item[0] =
  2225. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2226. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2227. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2228. ucontrol->value.enumerated.item[0]);
  2229. }
  2230. return ret;
  2231. }
  2232. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2233. struct snd_ctl_elem_value *ucontrol)
  2234. {
  2235. struct tdm_port port;
  2236. int ret = tdm_get_port_idx(kcontrol, &port);
  2237. if (ret) {
  2238. pr_err("%s: unsupported control: %s",
  2239. __func__, kcontrol->id.name);
  2240. } else {
  2241. tdm_rx_cfg[port.mode][port.channel].channels =
  2242. ucontrol->value.enumerated.item[0] + 1;
  2243. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2244. tdm_rx_cfg[port.mode][port.channel].channels,
  2245. ucontrol->value.enumerated.item[0] + 1);
  2246. }
  2247. return ret;
  2248. }
  2249. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2250. struct snd_ctl_elem_value *ucontrol)
  2251. {
  2252. struct tdm_port port;
  2253. int ret = tdm_get_port_idx(kcontrol, &port);
  2254. if (ret) {
  2255. pr_err("%s: unsupported control: %s",
  2256. __func__, kcontrol->id.name);
  2257. } else {
  2258. ucontrol->value.enumerated.item[0] =
  2259. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2260. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2261. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2262. ucontrol->value.enumerated.item[0]);
  2263. }
  2264. return ret;
  2265. }
  2266. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2267. struct snd_ctl_elem_value *ucontrol)
  2268. {
  2269. struct tdm_port port;
  2270. int ret = tdm_get_port_idx(kcontrol, &port);
  2271. if (ret) {
  2272. pr_err("%s: unsupported control: %s",
  2273. __func__, kcontrol->id.name);
  2274. } else {
  2275. tdm_tx_cfg[port.mode][port.channel].channels =
  2276. ucontrol->value.enumerated.item[0] + 1;
  2277. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2278. tdm_tx_cfg[port.mode][port.channel].channels,
  2279. ucontrol->value.enumerated.item[0] + 1);
  2280. }
  2281. return ret;
  2282. }
  2283. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2284. {
  2285. int idx;
  2286. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2287. sizeof("PRIM_AUX_PCM")))
  2288. idx = PRIM_AUX_PCM;
  2289. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2290. sizeof("SEC_AUX_PCM")))
  2291. idx = SEC_AUX_PCM;
  2292. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2293. sizeof("TERT_AUX_PCM")))
  2294. idx = TERT_AUX_PCM;
  2295. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2296. sizeof("QUAT_AUX_PCM")))
  2297. idx = QUAT_AUX_PCM;
  2298. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2299. sizeof("QUIN_AUX_PCM")))
  2300. idx = QUIN_AUX_PCM;
  2301. else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  2302. sizeof("SENN_AUX_PCM")))
  2303. idx = SEN_AUX_PCM;
  2304. else {
  2305. pr_err("%s: unsupported port: %s",
  2306. __func__, kcontrol->id.name);
  2307. idx = -EINVAL;
  2308. }
  2309. return idx;
  2310. }
  2311. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2312. struct snd_ctl_elem_value *ucontrol)
  2313. {
  2314. int idx = aux_pcm_get_port_idx(kcontrol);
  2315. if (idx < 0)
  2316. return idx;
  2317. aux_pcm_rx_cfg[idx].sample_rate =
  2318. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2319. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2320. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2321. ucontrol->value.enumerated.item[0]);
  2322. return 0;
  2323. }
  2324. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2325. struct snd_ctl_elem_value *ucontrol)
  2326. {
  2327. int idx = aux_pcm_get_port_idx(kcontrol);
  2328. if (idx < 0)
  2329. return idx;
  2330. ucontrol->value.enumerated.item[0] =
  2331. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2332. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2333. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2334. ucontrol->value.enumerated.item[0]);
  2335. return 0;
  2336. }
  2337. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2338. struct snd_ctl_elem_value *ucontrol)
  2339. {
  2340. int idx = aux_pcm_get_port_idx(kcontrol);
  2341. if (idx < 0)
  2342. return idx;
  2343. aux_pcm_tx_cfg[idx].sample_rate =
  2344. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2345. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2346. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2347. ucontrol->value.enumerated.item[0]);
  2348. return 0;
  2349. }
  2350. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2351. struct snd_ctl_elem_value *ucontrol)
  2352. {
  2353. int idx = aux_pcm_get_port_idx(kcontrol);
  2354. if (idx < 0)
  2355. return idx;
  2356. ucontrol->value.enumerated.item[0] =
  2357. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2358. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2359. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2360. ucontrol->value.enumerated.item[0]);
  2361. return 0;
  2362. }
  2363. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2364. {
  2365. int idx;
  2366. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2367. sizeof("PRIM_MI2S_RX")))
  2368. idx = PRIM_MI2S;
  2369. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2370. sizeof("SEC_MI2S_RX")))
  2371. idx = SEC_MI2S;
  2372. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2373. sizeof("TERT_MI2S_RX")))
  2374. idx = TERT_MI2S;
  2375. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2376. sizeof("QUAT_MI2S_RX")))
  2377. idx = QUAT_MI2S;
  2378. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2379. sizeof("QUIN_MI2S_RX")))
  2380. idx = QUIN_MI2S;
  2381. else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2382. sizeof("SEN_MI2S_RX")))
  2383. idx = SEN_MI2S;
  2384. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2385. sizeof("PRIM_MI2S_TX")))
  2386. idx = PRIM_MI2S;
  2387. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2388. sizeof("SEC_MI2S_TX")))
  2389. idx = SEC_MI2S;
  2390. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2391. sizeof("TERT_MI2S_TX")))
  2392. idx = TERT_MI2S;
  2393. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2394. sizeof("QUAT_MI2S_TX")))
  2395. idx = QUAT_MI2S;
  2396. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2397. sizeof("QUIN_MI2S_TX")))
  2398. idx = QUIN_MI2S;
  2399. else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2400. sizeof("SEN_MI2S_TX")))
  2401. idx = SEN_MI2S;
  2402. else {
  2403. pr_err("%s: unsupported channel: %s",
  2404. __func__, kcontrol->id.name);
  2405. idx = -EINVAL;
  2406. }
  2407. return idx;
  2408. }
  2409. static int mi2s_get_sample_rate_val(int sample_rate)
  2410. {
  2411. int sample_rate_val;
  2412. switch (sample_rate) {
  2413. case SAMPLING_RATE_8KHZ:
  2414. sample_rate_val = 0;
  2415. break;
  2416. case SAMPLING_RATE_11P025KHZ:
  2417. sample_rate_val = 1;
  2418. break;
  2419. case SAMPLING_RATE_16KHZ:
  2420. sample_rate_val = 2;
  2421. break;
  2422. case SAMPLING_RATE_22P05KHZ:
  2423. sample_rate_val = 3;
  2424. break;
  2425. case SAMPLING_RATE_32KHZ:
  2426. sample_rate_val = 4;
  2427. break;
  2428. case SAMPLING_RATE_44P1KHZ:
  2429. sample_rate_val = 5;
  2430. break;
  2431. case SAMPLING_RATE_48KHZ:
  2432. sample_rate_val = 6;
  2433. break;
  2434. case SAMPLING_RATE_88P2KHZ:
  2435. sample_rate_val = 7;
  2436. break;
  2437. case SAMPLING_RATE_96KHZ:
  2438. sample_rate_val = 8;
  2439. break;
  2440. case SAMPLING_RATE_176P4KHZ:
  2441. sample_rate_val = 9;
  2442. break;
  2443. case SAMPLING_RATE_192KHZ:
  2444. sample_rate_val = 10;
  2445. break;
  2446. case SAMPLING_RATE_352P8KHZ:
  2447. sample_rate_val = 11;
  2448. break;
  2449. case SAMPLING_RATE_384KHZ:
  2450. sample_rate_val = 12;
  2451. break;
  2452. default:
  2453. sample_rate_val = 6;
  2454. break;
  2455. }
  2456. return sample_rate_val;
  2457. }
  2458. static int mi2s_get_sample_rate(int value)
  2459. {
  2460. int sample_rate;
  2461. switch (value) {
  2462. case 0:
  2463. sample_rate = SAMPLING_RATE_8KHZ;
  2464. break;
  2465. case 1:
  2466. sample_rate = SAMPLING_RATE_11P025KHZ;
  2467. break;
  2468. case 2:
  2469. sample_rate = SAMPLING_RATE_16KHZ;
  2470. break;
  2471. case 3:
  2472. sample_rate = SAMPLING_RATE_22P05KHZ;
  2473. break;
  2474. case 4:
  2475. sample_rate = SAMPLING_RATE_32KHZ;
  2476. break;
  2477. case 5:
  2478. sample_rate = SAMPLING_RATE_44P1KHZ;
  2479. break;
  2480. case 6:
  2481. sample_rate = SAMPLING_RATE_48KHZ;
  2482. break;
  2483. case 7:
  2484. sample_rate = SAMPLING_RATE_88P2KHZ;
  2485. break;
  2486. case 8:
  2487. sample_rate = SAMPLING_RATE_96KHZ;
  2488. break;
  2489. case 9:
  2490. sample_rate = SAMPLING_RATE_176P4KHZ;
  2491. break;
  2492. case 10:
  2493. sample_rate = SAMPLING_RATE_192KHZ;
  2494. break;
  2495. case 11:
  2496. sample_rate = SAMPLING_RATE_352P8KHZ;
  2497. break;
  2498. case 12:
  2499. sample_rate = SAMPLING_RATE_384KHZ;
  2500. break;
  2501. default:
  2502. sample_rate = SAMPLING_RATE_48KHZ;
  2503. break;
  2504. }
  2505. return sample_rate;
  2506. }
  2507. static int mi2s_auxpcm_get_format(int value)
  2508. {
  2509. int format;
  2510. switch (value) {
  2511. case 0:
  2512. format = SNDRV_PCM_FORMAT_S16_LE;
  2513. break;
  2514. case 1:
  2515. format = SNDRV_PCM_FORMAT_S24_LE;
  2516. break;
  2517. case 2:
  2518. format = SNDRV_PCM_FORMAT_S24_3LE;
  2519. break;
  2520. case 3:
  2521. format = SNDRV_PCM_FORMAT_S32_LE;
  2522. break;
  2523. default:
  2524. format = SNDRV_PCM_FORMAT_S16_LE;
  2525. break;
  2526. }
  2527. return format;
  2528. }
  2529. static int mi2s_auxpcm_get_format_value(int format)
  2530. {
  2531. int value;
  2532. switch (format) {
  2533. case SNDRV_PCM_FORMAT_S16_LE:
  2534. value = 0;
  2535. break;
  2536. case SNDRV_PCM_FORMAT_S24_LE:
  2537. value = 1;
  2538. break;
  2539. case SNDRV_PCM_FORMAT_S24_3LE:
  2540. value = 2;
  2541. break;
  2542. case SNDRV_PCM_FORMAT_S32_LE:
  2543. value = 3;
  2544. break;
  2545. default:
  2546. value = 0;
  2547. break;
  2548. }
  2549. return value;
  2550. }
  2551. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2552. struct snd_ctl_elem_value *ucontrol)
  2553. {
  2554. int idx = mi2s_get_port_idx(kcontrol);
  2555. if (idx < 0)
  2556. return idx;
  2557. mi2s_rx_cfg[idx].sample_rate =
  2558. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2559. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2560. idx, mi2s_rx_cfg[idx].sample_rate,
  2561. ucontrol->value.enumerated.item[0]);
  2562. return 0;
  2563. }
  2564. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2565. struct snd_ctl_elem_value *ucontrol)
  2566. {
  2567. int idx = mi2s_get_port_idx(kcontrol);
  2568. if (idx < 0)
  2569. return idx;
  2570. ucontrol->value.enumerated.item[0] =
  2571. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2572. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2573. idx, mi2s_rx_cfg[idx].sample_rate,
  2574. ucontrol->value.enumerated.item[0]);
  2575. return 0;
  2576. }
  2577. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2578. struct snd_ctl_elem_value *ucontrol)
  2579. {
  2580. int idx = mi2s_get_port_idx(kcontrol);
  2581. if (idx < 0)
  2582. return idx;
  2583. mi2s_tx_cfg[idx].sample_rate =
  2584. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2585. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2586. idx, mi2s_tx_cfg[idx].sample_rate,
  2587. ucontrol->value.enumerated.item[0]);
  2588. return 0;
  2589. }
  2590. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2591. struct snd_ctl_elem_value *ucontrol)
  2592. {
  2593. int idx = mi2s_get_port_idx(kcontrol);
  2594. if (idx < 0)
  2595. return idx;
  2596. ucontrol->value.enumerated.item[0] =
  2597. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2598. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2599. idx, mi2s_tx_cfg[idx].sample_rate,
  2600. ucontrol->value.enumerated.item[0]);
  2601. return 0;
  2602. }
  2603. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2604. struct snd_ctl_elem_value *ucontrol)
  2605. {
  2606. int idx = mi2s_get_port_idx(kcontrol);
  2607. if (idx < 0)
  2608. return idx;
  2609. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2610. idx, mi2s_rx_cfg[idx].channels);
  2611. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2612. return 0;
  2613. }
  2614. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2615. struct snd_ctl_elem_value *ucontrol)
  2616. {
  2617. int idx = mi2s_get_port_idx(kcontrol);
  2618. if (idx < 0)
  2619. return idx;
  2620. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2621. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2622. idx, mi2s_rx_cfg[idx].channels);
  2623. return 1;
  2624. }
  2625. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2626. struct snd_ctl_elem_value *ucontrol)
  2627. {
  2628. int idx = mi2s_get_port_idx(kcontrol);
  2629. if (idx < 0)
  2630. return idx;
  2631. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2632. idx, mi2s_tx_cfg[idx].channels);
  2633. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2634. return 0;
  2635. }
  2636. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2637. struct snd_ctl_elem_value *ucontrol)
  2638. {
  2639. int idx = mi2s_get_port_idx(kcontrol);
  2640. if (idx < 0)
  2641. return idx;
  2642. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2643. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2644. idx, mi2s_tx_cfg[idx].channels);
  2645. return 1;
  2646. }
  2647. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2648. struct snd_ctl_elem_value *ucontrol)
  2649. {
  2650. int idx = mi2s_get_port_idx(kcontrol);
  2651. if (idx < 0)
  2652. return idx;
  2653. ucontrol->value.enumerated.item[0] =
  2654. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2655. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2656. idx, mi2s_rx_cfg[idx].bit_format,
  2657. ucontrol->value.enumerated.item[0]);
  2658. return 0;
  2659. }
  2660. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2661. struct snd_ctl_elem_value *ucontrol)
  2662. {
  2663. struct msm_asoc_mach_data *pdata = NULL;
  2664. struct snd_soc_component *component = NULL;
  2665. struct snd_soc_card *card = NULL;
  2666. int idx = mi2s_get_port_idx(kcontrol);
  2667. component = snd_soc_kcontrol_component(kcontrol);
  2668. card = kcontrol->private_data;
  2669. pdata = snd_soc_card_get_drvdata(card);
  2670. if (idx < 0)
  2671. return idx;
  2672. /* check for PRIM_MI2S and CSRAx config to allow 24bit BE config only */
  2673. if ((PRIM_MI2S == idx) && (true==pdata->codec_is_csra))
  2674. {
  2675. mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2676. pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
  2677. __func__, idx, mi2s_rx_cfg[idx].bit_format,
  2678. ucontrol->value.enumerated.item[0]);
  2679. } else {
  2680. mi2s_rx_cfg[idx].bit_format =
  2681. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2682. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2683. idx, mi2s_rx_cfg[idx].bit_format,
  2684. ucontrol->value.enumerated.item[0]);
  2685. }
  2686. return 0;
  2687. }
  2688. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2689. struct snd_ctl_elem_value *ucontrol)
  2690. {
  2691. int idx = mi2s_get_port_idx(kcontrol);
  2692. if (idx < 0)
  2693. return idx;
  2694. ucontrol->value.enumerated.item[0] =
  2695. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2696. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2697. idx, mi2s_tx_cfg[idx].bit_format,
  2698. ucontrol->value.enumerated.item[0]);
  2699. return 0;
  2700. }
  2701. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2702. struct snd_ctl_elem_value *ucontrol)
  2703. {
  2704. int idx = mi2s_get_port_idx(kcontrol);
  2705. if (idx < 0)
  2706. return idx;
  2707. mi2s_tx_cfg[idx].bit_format =
  2708. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2709. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2710. idx, mi2s_tx_cfg[idx].bit_format,
  2711. ucontrol->value.enumerated.item[0]);
  2712. return 0;
  2713. }
  2714. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2715. struct snd_ctl_elem_value *ucontrol)
  2716. {
  2717. int idx = aux_pcm_get_port_idx(kcontrol);
  2718. if (idx < 0)
  2719. return idx;
  2720. ucontrol->value.enumerated.item[0] =
  2721. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2722. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2723. idx, aux_pcm_rx_cfg[idx].bit_format,
  2724. ucontrol->value.enumerated.item[0]);
  2725. return 0;
  2726. }
  2727. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2728. struct snd_ctl_elem_value *ucontrol)
  2729. {
  2730. int idx = aux_pcm_get_port_idx(kcontrol);
  2731. if (idx < 0)
  2732. return idx;
  2733. aux_pcm_rx_cfg[idx].bit_format =
  2734. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2735. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2736. idx, aux_pcm_rx_cfg[idx].bit_format,
  2737. ucontrol->value.enumerated.item[0]);
  2738. return 0;
  2739. }
  2740. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2741. struct snd_ctl_elem_value *ucontrol)
  2742. {
  2743. int idx = aux_pcm_get_port_idx(kcontrol);
  2744. if (idx < 0)
  2745. return idx;
  2746. ucontrol->value.enumerated.item[0] =
  2747. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2748. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2749. idx, aux_pcm_tx_cfg[idx].bit_format,
  2750. ucontrol->value.enumerated.item[0]);
  2751. return 0;
  2752. }
  2753. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2754. struct snd_ctl_elem_value *ucontrol)
  2755. {
  2756. int idx = aux_pcm_get_port_idx(kcontrol);
  2757. if (idx < 0)
  2758. return idx;
  2759. aux_pcm_tx_cfg[idx].bit_format =
  2760. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2761. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2762. idx, aux_pcm_tx_cfg[idx].bit_format,
  2763. ucontrol->value.enumerated.item[0]);
  2764. return 0;
  2765. }
  2766. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  2767. {
  2768. int idx;
  2769. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  2770. sizeof("PRIM_SPDIF_RX")))
  2771. idx = PRIM_SPDIF_RX;
  2772. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  2773. sizeof("SEC_SPDIF_RX")))
  2774. idx = SEC_SPDIF_RX;
  2775. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  2776. sizeof("PRIM_SPDIF_TX")))
  2777. idx = PRIM_SPDIF_TX;
  2778. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  2779. sizeof("SEC_SPDIF_TX")))
  2780. idx = SEC_SPDIF_TX;
  2781. else {
  2782. pr_err("%s: unsupported channel: %s",
  2783. __func__, kcontrol->id.name);
  2784. idx = -EINVAL;
  2785. }
  2786. return idx;
  2787. }
  2788. static int spdif_get_sample_rate_val(int sample_rate)
  2789. {
  2790. int sample_rate_val;
  2791. switch (sample_rate) {
  2792. case SAMPLING_RATE_32KHZ:
  2793. sample_rate_val = 0;
  2794. break;
  2795. case SAMPLING_RATE_44P1KHZ:
  2796. sample_rate_val = 1;
  2797. break;
  2798. case SAMPLING_RATE_48KHZ:
  2799. sample_rate_val = 2;
  2800. break;
  2801. case SAMPLING_RATE_88P2KHZ:
  2802. sample_rate_val = 3;
  2803. break;
  2804. case SAMPLING_RATE_96KHZ:
  2805. sample_rate_val = 4;
  2806. break;
  2807. case SAMPLING_RATE_176P4KHZ:
  2808. sample_rate_val = 5;
  2809. break;
  2810. case SAMPLING_RATE_192KHZ:
  2811. sample_rate_val = 6;
  2812. break;
  2813. default:
  2814. sample_rate_val = 2;
  2815. break;
  2816. }
  2817. return sample_rate_val;
  2818. }
  2819. static int spdif_get_sample_rate(int value)
  2820. {
  2821. int sample_rate;
  2822. switch (value) {
  2823. case 0:
  2824. sample_rate = SAMPLING_RATE_32KHZ;
  2825. break;
  2826. case 1:
  2827. sample_rate = SAMPLING_RATE_44P1KHZ;
  2828. break;
  2829. case 2:
  2830. sample_rate = SAMPLING_RATE_48KHZ;
  2831. break;
  2832. case 3:
  2833. sample_rate = SAMPLING_RATE_88P2KHZ;
  2834. break;
  2835. case 4:
  2836. sample_rate = SAMPLING_RATE_96KHZ;
  2837. break;
  2838. case 5:
  2839. sample_rate = SAMPLING_RATE_176P4KHZ;
  2840. break;
  2841. case 6:
  2842. sample_rate = SAMPLING_RATE_192KHZ;
  2843. break;
  2844. default:
  2845. sample_rate = SAMPLING_RATE_48KHZ;
  2846. break;
  2847. }
  2848. return sample_rate;
  2849. }
  2850. static int spdif_get_format(int value)
  2851. {
  2852. int format;
  2853. switch (value) {
  2854. case 0:
  2855. format = SNDRV_PCM_FORMAT_S16_LE;
  2856. break;
  2857. case 1:
  2858. format = SNDRV_PCM_FORMAT_S24_LE;
  2859. break;
  2860. default:
  2861. format = SNDRV_PCM_FORMAT_S16_LE;
  2862. break;
  2863. }
  2864. return format;
  2865. }
  2866. static int spdif_get_format_value(int format)
  2867. {
  2868. int value;
  2869. switch (format) {
  2870. case SNDRV_PCM_FORMAT_S16_LE:
  2871. value = 0;
  2872. break;
  2873. case SNDRV_PCM_FORMAT_S24_LE:
  2874. value = 1;
  2875. break;
  2876. default:
  2877. value = 0;
  2878. break;
  2879. }
  2880. return value;
  2881. }
  2882. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2883. struct snd_ctl_elem_value *ucontrol)
  2884. {
  2885. int idx = spdif_get_port_idx(kcontrol);
  2886. if (idx < 0)
  2887. return idx;
  2888. spdif_rx_cfg[idx].sample_rate =
  2889. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2890. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2891. idx, spdif_rx_cfg[idx].sample_rate,
  2892. ucontrol->value.enumerated.item[0]);
  2893. return 0;
  2894. }
  2895. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2896. struct snd_ctl_elem_value *ucontrol)
  2897. {
  2898. int idx = spdif_get_port_idx(kcontrol);
  2899. if (idx < 0)
  2900. return idx;
  2901. ucontrol->value.enumerated.item[0] =
  2902. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  2903. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2904. idx, spdif_rx_cfg[idx].sample_rate,
  2905. ucontrol->value.enumerated.item[0]);
  2906. return 0;
  2907. }
  2908. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2909. struct snd_ctl_elem_value *ucontrol)
  2910. {
  2911. int idx = spdif_get_port_idx(kcontrol);
  2912. if (idx < 0)
  2913. return idx;
  2914. spdif_tx_cfg[idx].sample_rate =
  2915. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2916. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2917. idx, spdif_tx_cfg[idx].sample_rate,
  2918. ucontrol->value.enumerated.item[0]);
  2919. return 0;
  2920. }
  2921. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2922. struct snd_ctl_elem_value *ucontrol)
  2923. {
  2924. int idx = spdif_get_port_idx(kcontrol);
  2925. if (idx < 0)
  2926. return idx;
  2927. ucontrol->value.enumerated.item[0] =
  2928. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  2929. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2930. idx, spdif_tx_cfg[idx].sample_rate,
  2931. ucontrol->value.enumerated.item[0]);
  2932. return 0;
  2933. }
  2934. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  2935. struct snd_ctl_elem_value *ucontrol)
  2936. {
  2937. int idx = spdif_get_port_idx(kcontrol);
  2938. if (idx < 0)
  2939. return idx;
  2940. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2941. idx, spdif_rx_cfg[idx].channels);
  2942. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  2943. return 0;
  2944. }
  2945. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  2946. struct snd_ctl_elem_value *ucontrol)
  2947. {
  2948. int idx = spdif_get_port_idx(kcontrol);
  2949. if (idx < 0)
  2950. return idx;
  2951. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2952. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  2953. idx, spdif_rx_cfg[idx].channels);
  2954. return 1;
  2955. }
  2956. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  2957. struct snd_ctl_elem_value *ucontrol)
  2958. {
  2959. int idx = spdif_get_port_idx(kcontrol);
  2960. if (idx < 0)
  2961. return idx;
  2962. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2963. idx, spdif_tx_cfg[idx].channels);
  2964. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  2965. return 0;
  2966. }
  2967. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  2968. struct snd_ctl_elem_value *ucontrol)
  2969. {
  2970. int idx = spdif_get_port_idx(kcontrol);
  2971. if (idx < 0)
  2972. return idx;
  2973. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2974. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  2975. idx, spdif_tx_cfg[idx].channels);
  2976. return 1;
  2977. }
  2978. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  2979. struct snd_ctl_elem_value *ucontrol)
  2980. {
  2981. int idx = spdif_get_port_idx(kcontrol);
  2982. if (idx < 0)
  2983. return idx;
  2984. ucontrol->value.enumerated.item[0] =
  2985. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  2986. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2987. idx, spdif_rx_cfg[idx].bit_format,
  2988. ucontrol->value.enumerated.item[0]);
  2989. return 0;
  2990. }
  2991. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  2992. struct snd_ctl_elem_value *ucontrol)
  2993. {
  2994. int idx = spdif_get_port_idx(kcontrol);
  2995. if (idx < 0)
  2996. return idx;
  2997. spdif_rx_cfg[idx].bit_format =
  2998. spdif_get_format(ucontrol->value.enumerated.item[0]);
  2999. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  3000. idx, spdif_rx_cfg[idx].bit_format,
  3001. ucontrol->value.enumerated.item[0]);
  3002. return 0;
  3003. }
  3004. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  3005. struct snd_ctl_elem_value *ucontrol)
  3006. {
  3007. int idx = spdif_get_port_idx(kcontrol);
  3008. if (idx < 0)
  3009. return idx;
  3010. ucontrol->value.enumerated.item[0] =
  3011. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  3012. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  3013. idx, spdif_tx_cfg[idx].bit_format,
  3014. ucontrol->value.enumerated.item[0]);
  3015. return 0;
  3016. }
  3017. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  3018. struct snd_ctl_elem_value *ucontrol)
  3019. {
  3020. int idx = spdif_get_port_idx(kcontrol);
  3021. if (idx < 0)
  3022. return idx;
  3023. spdif_tx_cfg[idx].bit_format =
  3024. spdif_get_format(ucontrol->value.enumerated.item[0]);
  3025. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  3026. idx, spdif_tx_cfg[idx].bit_format,
  3027. ucontrol->value.enumerated.item[0]);
  3028. return 0;
  3029. }
  3030. static int afe_lb_tx_ch_get(struct snd_kcontrol *kcontrol,
  3031. struct snd_ctl_elem_value *ucontrol)
  3032. {
  3033. pr_debug("%s: afe_lb_tx_ch = %d\n", __func__,
  3034. afe_lb_tx_cfg.channels);
  3035. ucontrol->value.integer.value[0] = afe_lb_tx_cfg.channels - 1;
  3036. return 0;
  3037. }
  3038. static int afe_lb_tx_ch_put(struct snd_kcontrol *kcontrol,
  3039. struct snd_ctl_elem_value *ucontrol)
  3040. {
  3041. afe_lb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  3042. pr_debug("%s: afe_lb_tx_ch = %d\n", __func__, afe_lb_tx_cfg.channels);
  3043. return 0;
  3044. }
  3045. static int afe_lb_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  3046. struct snd_ctl_elem_value *ucontrol)
  3047. {
  3048. int sample_rate_val;
  3049. switch (afe_lb_tx_cfg.sample_rate) {
  3050. case SAMPLING_RATE_384KHZ:
  3051. sample_rate_val = 12;
  3052. break;
  3053. case SAMPLING_RATE_352P8KHZ:
  3054. sample_rate_val = 11;
  3055. break;
  3056. case SAMPLING_RATE_192KHZ:
  3057. sample_rate_val = 10;
  3058. break;
  3059. case SAMPLING_RATE_176P4KHZ:
  3060. sample_rate_val = 9;
  3061. break;
  3062. case SAMPLING_RATE_96KHZ:
  3063. sample_rate_val = 8;
  3064. break;
  3065. case SAMPLING_RATE_88P2KHZ:
  3066. sample_rate_val = 7;
  3067. break;
  3068. case SAMPLING_RATE_48KHZ:
  3069. sample_rate_val = 6;
  3070. break;
  3071. case SAMPLING_RATE_44P1KHZ:
  3072. sample_rate_val = 5;
  3073. break;
  3074. case SAMPLING_RATE_32KHZ:
  3075. sample_rate_val = 4;
  3076. break;
  3077. case SAMPLING_RATE_22P05KHZ:
  3078. sample_rate_val = 3;
  3079. break;
  3080. case SAMPLING_RATE_16KHZ:
  3081. sample_rate_val = 2;
  3082. break;
  3083. case SAMPLING_RATE_11P025KHZ:
  3084. sample_rate_val = 1;
  3085. break;
  3086. case SAMPLING_RATE_8KHZ:
  3087. sample_rate_val = 0;
  3088. break;
  3089. default:
  3090. sample_rate_val = 6;
  3091. break;
  3092. }
  3093. ucontrol->value.integer.value[0] = sample_rate_val;
  3094. pr_debug("%s: afe_lb_tx_sample_rate = %d\n", __func__,
  3095. afe_lb_tx_cfg.sample_rate);
  3096. return 0;
  3097. }
  3098. static int afe_lb_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  3099. struct snd_ctl_elem_value *ucontrol)
  3100. {
  3101. switch (ucontrol->value.integer.value[0]) {
  3102. case 12:
  3103. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  3104. break;
  3105. case 11:
  3106. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  3107. break;
  3108. case 10:
  3109. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  3110. break;
  3111. case 9:
  3112. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  3113. break;
  3114. case 8:
  3115. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  3116. break;
  3117. case 7:
  3118. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  3119. break;
  3120. case 6:
  3121. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  3122. break;
  3123. case 5:
  3124. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  3125. break;
  3126. case 4:
  3127. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  3128. break;
  3129. case 3:
  3130. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  3131. break;
  3132. case 2:
  3133. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  3134. break;
  3135. case 1:
  3136. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  3137. break;
  3138. case 0:
  3139. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  3140. break;
  3141. default:
  3142. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  3143. break;
  3144. }
  3145. pr_debug("%s: control value = %ld, afe_lb_tx_sample_rate = %d\n",
  3146. __func__, ucontrol->value.integer.value[0],
  3147. afe_lb_tx_cfg.sample_rate);
  3148. return 0;
  3149. }
  3150. static int afe_lb_tx_format_get(struct snd_kcontrol *kcontrol,
  3151. struct snd_ctl_elem_value *ucontrol)
  3152. {
  3153. switch (afe_lb_tx_cfg.bit_format) {
  3154. case SNDRV_PCM_FORMAT_S32_LE:
  3155. ucontrol->value.integer.value[0] = 3;
  3156. break;
  3157. case SNDRV_PCM_FORMAT_S24_3LE:
  3158. ucontrol->value.integer.value[0] = 2;
  3159. break;
  3160. case SNDRV_PCM_FORMAT_S24_LE:
  3161. ucontrol->value.integer.value[0] = 1;
  3162. break;
  3163. case SNDRV_PCM_FORMAT_S16_LE:
  3164. default:
  3165. ucontrol->value.integer.value[0] = 0;
  3166. break;
  3167. }
  3168. pr_debug("%s: afe_lb_tx_format = %d, ucontrol value = %ld\n",
  3169. __func__, afe_lb_tx_cfg.bit_format,
  3170. ucontrol->value.integer.value[0]);
  3171. return 0;
  3172. }
  3173. static int afe_lb_tx_format_put(struct snd_kcontrol *kcontrol,
  3174. struct snd_ctl_elem_value *ucontrol)
  3175. {
  3176. switch (ucontrol->value.integer.value[0]) {
  3177. case 3:
  3178. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  3179. break;
  3180. case 2:
  3181. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  3182. break;
  3183. case 1:
  3184. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  3185. break;
  3186. case 0:
  3187. default:
  3188. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  3189. break;
  3190. }
  3191. pr_debug("%s: afe_lb_tx_format = %d, ucontrol value = %ld\n",
  3192. __func__, afe_lb_tx_cfg.bit_format,
  3193. ucontrol->value.integer.value[0]);
  3194. return 0;
  3195. }
  3196. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  3197. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  3198. slim_rx_ch_get, slim_rx_ch_put),
  3199. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  3200. slim_rx_ch_get, slim_rx_ch_put),
  3201. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  3202. slim_tx_ch_get, slim_tx_ch_put),
  3203. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  3204. slim_tx_ch_get, slim_tx_ch_put),
  3205. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  3206. slim_rx_ch_get, slim_rx_ch_put),
  3207. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  3208. slim_rx_ch_get, slim_rx_ch_put),
  3209. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  3210. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3211. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  3212. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3213. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  3214. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3215. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  3216. slim_tx_bit_format_get, slim_tx_bit_format_put),
  3217. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  3218. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3219. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  3220. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3221. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  3222. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  3223. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  3224. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3225. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  3226. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3227. };
  3228. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  3229. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  3230. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3231. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  3232. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3233. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  3234. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3235. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  3236. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3237. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3238. va_cdc_dma_tx_0_sample_rate,
  3239. cdc_dma_tx_sample_rate_get,
  3240. cdc_dma_tx_sample_rate_put),
  3241. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3242. va_cdc_dma_tx_1_sample_rate,
  3243. cdc_dma_tx_sample_rate_get,
  3244. cdc_dma_tx_sample_rate_put),
  3245. };
  3246. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  3247. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3248. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3249. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  3250. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3251. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  3252. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3253. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  3254. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3255. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  3256. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3257. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  3258. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3259. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  3260. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3261. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  3262. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3263. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  3264. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3265. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  3266. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3267. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  3268. wsa_cdc_dma_rx_0_sample_rate,
  3269. cdc_dma_rx_sample_rate_get,
  3270. cdc_dma_rx_sample_rate_put),
  3271. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  3272. wsa_cdc_dma_rx_1_sample_rate,
  3273. cdc_dma_rx_sample_rate_get,
  3274. cdc_dma_rx_sample_rate_put),
  3275. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  3276. wsa_cdc_dma_tx_0_sample_rate,
  3277. cdc_dma_tx_sample_rate_get,
  3278. cdc_dma_tx_sample_rate_put),
  3279. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  3280. wsa_cdc_dma_tx_1_sample_rate,
  3281. cdc_dma_tx_sample_rate_get,
  3282. cdc_dma_tx_sample_rate_put),
  3283. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  3284. wsa_cdc_dma_tx_2_sample_rate,
  3285. cdc_dma_tx_sample_rate_get,
  3286. cdc_dma_tx_sample_rate_put),
  3287. };
  3288. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3289. SOC_ENUM_EXT("BT_TX SampleRate", bt_sample_rate_sink,
  3290. msm_bt_sample_rate_sink_get,
  3291. msm_bt_sample_rate_sink_put),
  3292. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3293. msm_bt_sample_rate_get,
  3294. msm_bt_sample_rate_put),
  3295. SOC_ENUM_EXT("BT_RX SampleRate", bt_sample_rate,
  3296. msm_bt_sample_rate_get,
  3297. msm_bt_sample_rate_put),
  3298. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3299. proxy_rx_ch_get, proxy_rx_ch_put),
  3300. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3301. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3302. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3303. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3304. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3305. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3306. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3307. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3308. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3309. usb_audio_rx_sample_rate_get,
  3310. usb_audio_rx_sample_rate_put),
  3311. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3312. usb_audio_tx_sample_rate_get,
  3313. usb_audio_tx_sample_rate_put),
  3314. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3315. tdm_rx_sample_rate_get,
  3316. tdm_rx_sample_rate_put),
  3317. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3318. tdm_tx_sample_rate_get,
  3319. tdm_tx_sample_rate_put),
  3320. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3321. tdm_rx_format_get,
  3322. tdm_rx_format_put),
  3323. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3324. tdm_tx_format_get,
  3325. tdm_tx_format_put),
  3326. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3327. tdm_rx_ch_get,
  3328. tdm_rx_ch_put),
  3329. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3330. tdm_tx_ch_get,
  3331. tdm_tx_ch_put),
  3332. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3333. tdm_rx_sample_rate_get,
  3334. tdm_rx_sample_rate_put),
  3335. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3336. tdm_tx_sample_rate_get,
  3337. tdm_tx_sample_rate_put),
  3338. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3339. tdm_rx_format_get,
  3340. tdm_rx_format_put),
  3341. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3342. tdm_tx_format_get,
  3343. tdm_tx_format_put),
  3344. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3345. tdm_rx_ch_get,
  3346. tdm_rx_ch_put),
  3347. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3348. tdm_tx_ch_get,
  3349. tdm_tx_ch_put),
  3350. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3351. tdm_rx_sample_rate_get,
  3352. tdm_rx_sample_rate_put),
  3353. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3354. tdm_tx_sample_rate_get,
  3355. tdm_tx_sample_rate_put),
  3356. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3357. tdm_rx_format_get,
  3358. tdm_rx_format_put),
  3359. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3360. tdm_tx_format_get,
  3361. tdm_tx_format_put),
  3362. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3363. tdm_rx_ch_get,
  3364. tdm_rx_ch_put),
  3365. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3366. tdm_tx_ch_get,
  3367. tdm_tx_ch_put),
  3368. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3369. tdm_rx_sample_rate_get,
  3370. tdm_rx_sample_rate_put),
  3371. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3372. tdm_tx_sample_rate_get,
  3373. tdm_tx_sample_rate_put),
  3374. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3375. tdm_rx_format_get,
  3376. tdm_rx_format_put),
  3377. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3378. tdm_tx_format_get,
  3379. tdm_tx_format_put),
  3380. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3381. tdm_rx_ch_get,
  3382. tdm_rx_ch_put),
  3383. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3384. tdm_tx_ch_get,
  3385. tdm_tx_ch_put),
  3386. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3387. tdm_rx_sample_rate_get,
  3388. tdm_rx_sample_rate_put),
  3389. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3390. tdm_tx_sample_rate_get,
  3391. tdm_tx_sample_rate_put),
  3392. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3393. tdm_rx_format_get,
  3394. tdm_rx_format_put),
  3395. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3396. tdm_tx_format_get,
  3397. tdm_tx_format_put),
  3398. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3399. tdm_rx_ch_get,
  3400. tdm_rx_ch_put),
  3401. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3402. tdm_tx_ch_get,
  3403. tdm_tx_ch_put),
  3404. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3405. aux_pcm_rx_sample_rate_get,
  3406. aux_pcm_rx_sample_rate_put),
  3407. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3408. aux_pcm_rx_sample_rate_get,
  3409. aux_pcm_rx_sample_rate_put),
  3410. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3411. aux_pcm_rx_sample_rate_get,
  3412. aux_pcm_rx_sample_rate_put),
  3413. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3414. aux_pcm_rx_sample_rate_get,
  3415. aux_pcm_rx_sample_rate_put),
  3416. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3417. aux_pcm_rx_sample_rate_get,
  3418. aux_pcm_rx_sample_rate_put),
  3419. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3420. aux_pcm_tx_sample_rate_get,
  3421. aux_pcm_tx_sample_rate_put),
  3422. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3423. aux_pcm_tx_sample_rate_get,
  3424. aux_pcm_tx_sample_rate_put),
  3425. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3426. aux_pcm_tx_sample_rate_get,
  3427. aux_pcm_tx_sample_rate_put),
  3428. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3429. aux_pcm_tx_sample_rate_get,
  3430. aux_pcm_tx_sample_rate_put),
  3431. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3432. aux_pcm_tx_sample_rate_get,
  3433. aux_pcm_tx_sample_rate_put),
  3434. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3435. aux_pcm_tx_sample_rate_get,
  3436. aux_pcm_tx_sample_rate_put),
  3437. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3438. mi2s_rx_sample_rate_get,
  3439. mi2s_rx_sample_rate_put),
  3440. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3441. mi2s_rx_sample_rate_get,
  3442. mi2s_rx_sample_rate_put),
  3443. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3444. mi2s_rx_sample_rate_get,
  3445. mi2s_rx_sample_rate_put),
  3446. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3447. mi2s_rx_sample_rate_get,
  3448. mi2s_rx_sample_rate_put),
  3449. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3450. mi2s_rx_sample_rate_get,
  3451. mi2s_rx_sample_rate_put),
  3452. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3453. mi2s_rx_sample_rate_get,
  3454. mi2s_rx_sample_rate_put),
  3455. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3456. mi2s_tx_sample_rate_get,
  3457. mi2s_tx_sample_rate_put),
  3458. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3459. mi2s_tx_sample_rate_get,
  3460. mi2s_tx_sample_rate_put),
  3461. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3462. mi2s_tx_sample_rate_get,
  3463. mi2s_tx_sample_rate_put),
  3464. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3465. mi2s_tx_sample_rate_get,
  3466. mi2s_tx_sample_rate_put),
  3467. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3468. mi2s_tx_sample_rate_get,
  3469. mi2s_tx_sample_rate_put),
  3470. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3471. mi2s_tx_sample_rate_get,
  3472. mi2s_tx_sample_rate_put),
  3473. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3474. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3475. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3476. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3477. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3478. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3479. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3480. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3481. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3482. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3483. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3484. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3485. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3486. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3487. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3488. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3489. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3490. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3491. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3492. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3493. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3494. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3495. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3496. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3497. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3498. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3499. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3500. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3501. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3502. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3503. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3504. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3505. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3506. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3507. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3508. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3509. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3510. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3511. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3512. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3513. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3514. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3515. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3516. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3517. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3518. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3519. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3520. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3521. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3522. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3523. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3524. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3525. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3526. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3527. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3528. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3529. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3530. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3531. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3532. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3533. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3534. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3535. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3536. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3537. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3538. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3539. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3540. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3541. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3542. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3543. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3544. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3545. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3546. msm_snd_vad_cfg_put),
  3547. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3548. msm_spdif_rx_sample_rate_get,
  3549. msm_spdif_rx_sample_rate_put),
  3550. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3551. msm_spdif_tx_sample_rate_get,
  3552. msm_spdif_tx_sample_rate_put),
  3553. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3554. msm_spdif_rx_sample_rate_get,
  3555. msm_spdif_rx_sample_rate_put),
  3556. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3557. msm_spdif_tx_sample_rate_get,
  3558. msm_spdif_tx_sample_rate_put),
  3559. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3560. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3561. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3562. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3563. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3564. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3565. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3566. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3567. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3568. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3569. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3570. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3571. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3572. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3573. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3574. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3575. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_lb_tx_chs,
  3576. afe_lb_tx_ch_get, afe_lb_tx_ch_put),
  3577. SOC_ENUM_EXT("AFE_LOOPBACK_TX Format", afe_lb_tx_format,
  3578. afe_lb_tx_format_get, afe_lb_tx_format_put),
  3579. SOC_ENUM_EXT("AFE_LOOPBACK_TX SampleRate", afe_lb_tx_sample_rate,
  3580. afe_lb_tx_sample_rate_get,
  3581. afe_lb_tx_sample_rate_put),
  3582. };
  3583. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  3584. int enable, bool dapm)
  3585. {
  3586. int ret = 0;
  3587. if (!strcmp(component.name, "tasha_codec")) {
  3588. ret = tasha_cdc_mclk_enable(component, enable, dapm);
  3589. } else {
  3590. dev_err(component->dev, "%s: unknown codec to enable ext clk\n",
  3591. __func__);
  3592. ret = -EINVAL;
  3593. }
  3594. return ret;
  3595. }
  3596. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_component *component,
  3597. int enable, bool dapm)
  3598. {
  3599. int ret = 0;
  3600. if (!strcmp(component.name, "tasha_codec")) {
  3601. ret = tasha_cdc_mclk_tx_enable(component, enable, dapm);
  3602. } else {
  3603. dev_err(component->dev, "%s: unknown codec to enable TX ext clk\n",
  3604. __func__);
  3605. ret = -EINVAL;
  3606. }
  3607. return ret;
  3608. }
  3609. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  3610. struct snd_kcontrol *kcontrol, int event)
  3611. {
  3612. struct snd_soc_component *component =
  3613. snd_soc_dapm_to_component(w->dapm);
  3614. pr_debug("%s: event = %d\n", __func__, event);
  3615. switch (event) {
  3616. case SND_SOC_DAPM_PRE_PMU:
  3617. return msm_snd_enable_codec_ext_tx_clk(component, 1, true);
  3618. case SND_SOC_DAPM_POST_PMD:
  3619. return msm_snd_enable_codec_ext_tx_clk(component, 0, true);
  3620. }
  3621. return 0;
  3622. }
  3623. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  3624. struct snd_kcontrol *kcontrol, int event)
  3625. {
  3626. struct snd_soc_component *component =
  3627. snd_soc_dapm_to_component(w->dapm);
  3628. pr_debug("%s: event = %d\n", __func__, event);
  3629. switch (event) {
  3630. case SND_SOC_DAPM_PRE_PMU:
  3631. return msm_snd_enable_codec_ext_clk(component, 1, true);
  3632. case SND_SOC_DAPM_POST_PMD:
  3633. return msm_snd_enable_codec_ext_clk(component, 0, true);
  3634. }
  3635. return 0;
  3636. }
  3637. static int msm_lineout_booster_ctrl_event(struct snd_soc_dapm_widget *w,
  3638. struct snd_kcontrol *k, int event)
  3639. {
  3640. struct snd_soc_component *component =
  3641. snd_soc_dapm_to_component(w->dapm);
  3642. struct snd_soc_card *card = component->card;
  3643. struct msm_asoc_mach_data *pdata =
  3644. snd_soc_card_get_drvdata(card);
  3645. pr_debug("%s: event = %d\n", __func__, event);
  3646. switch (event) {
  3647. case SND_SOC_DAPM_POST_PMU:
  3648. msm_cdc_pinctrl_select_active_state(
  3649. pdata->lineout_booster_gpio_p);
  3650. break;
  3651. case SND_SOC_DAPM_PRE_PMD:
  3652. msm_cdc_pinctrl_select_sleep_state(
  3653. pdata->lineout_booster_gpio_p);
  3654. break;
  3655. }
  3656. return 0;
  3657. }
  3658. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  3659. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  3660. msm_mclk_event,
  3661. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3662. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  3663. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3664. SND_SOC_DAPM_SPK("lineout booster", msm_lineout_booster_ctrl_event),
  3665. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3666. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3667. };
  3668. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3669. struct snd_kcontrol *kcontrol, int event)
  3670. {
  3671. struct msm_asoc_mach_data *pdata = NULL;
  3672. struct snd_soc_component *component =
  3673. snd_soc_dapm_to_component(w->dapm);
  3674. int ret = 0;
  3675. uint32_t dmic_idx;
  3676. int *dmic_gpio_cnt;
  3677. struct device_node *dmic_gpio;
  3678. char *wname;
  3679. wname = strpbrk(w->name, "01234567");
  3680. if (!wname) {
  3681. dev_err(component->dev, "%s: widget not found\n", __func__);
  3682. return -EINVAL;
  3683. }
  3684. ret = kstrtouint(wname, 10, &dmic_idx);
  3685. if (ret < 0) {
  3686. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  3687. __func__);
  3688. return -EINVAL;
  3689. }
  3690. pdata = snd_soc_card_get_drvdata(component->card);
  3691. switch (dmic_idx) {
  3692. case 0:
  3693. case 1:
  3694. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  3695. dmic_gpio = pdata->dmic_01_gpio_p;
  3696. break;
  3697. case 2:
  3698. case 3:
  3699. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  3700. dmic_gpio = pdata->dmic_23_gpio_p;
  3701. break;
  3702. case 4:
  3703. case 5:
  3704. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  3705. dmic_gpio = pdata->dmic_45_gpio_p;
  3706. break;
  3707. case 6:
  3708. case 7:
  3709. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  3710. dmic_gpio = pdata->dmic_67_gpio_p;
  3711. break;
  3712. default:
  3713. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  3714. __func__);
  3715. return -EINVAL;
  3716. }
  3717. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3718. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3719. switch (event) {
  3720. case SND_SOC_DAPM_PRE_PMU:
  3721. (*dmic_gpio_cnt)++;
  3722. if (*dmic_gpio_cnt == 1) {
  3723. ret = msm_cdc_pinctrl_select_active_state(
  3724. dmic_gpio);
  3725. if (ret < 0) {
  3726. dev_err(component->dev, "%s: gpio set cannot be activated %sd\n",
  3727. __func__, "dmic_gpio");
  3728. return ret;
  3729. }
  3730. }
  3731. break;
  3732. case SND_SOC_DAPM_POST_PMD:
  3733. (*dmic_gpio_cnt)--;
  3734. if (*dmic_gpio_cnt == 0) {
  3735. ret = msm_cdc_pinctrl_select_sleep_state(
  3736. dmic_gpio);
  3737. if (ret < 0) {
  3738. dev_err(component->dev, "%s: gpio set cannot be de-activated %sd\n",
  3739. __func__, "dmic_gpio");
  3740. return ret;
  3741. }
  3742. }
  3743. break;
  3744. default:
  3745. dev_err(component->dev, "%s: invalid DAPM event %d\n",
  3746. __func__, event);
  3747. return -EINVAL;
  3748. }
  3749. return 0;
  3750. }
  3751. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3752. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3753. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3754. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3755. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3756. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3757. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3758. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3759. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3760. };
  3761. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3762. };
  3763. static inline int param_is_mask(int p)
  3764. {
  3765. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3766. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3767. }
  3768. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3769. int n)
  3770. {
  3771. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3772. }
  3773. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3774. unsigned int bit)
  3775. {
  3776. if (bit >= SNDRV_MASK_MAX)
  3777. return;
  3778. if (param_is_mask(n)) {
  3779. struct snd_mask *m = param_to_mask(p, n);
  3780. m->bits[0] = 0;
  3781. m->bits[1] = 0;
  3782. m->bits[bit >> 5] |= (1 << (bit & 31));
  3783. }
  3784. }
  3785. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3786. {
  3787. int ch_id = 0;
  3788. switch (be_id) {
  3789. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3790. ch_id = SLIM_RX_0;
  3791. break;
  3792. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3793. ch_id = SLIM_RX_1;
  3794. break;
  3795. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3796. ch_id = SLIM_RX_2;
  3797. break;
  3798. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3799. ch_id = SLIM_RX_3;
  3800. break;
  3801. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3802. ch_id = SLIM_RX_4;
  3803. break;
  3804. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3805. ch_id = SLIM_RX_6;
  3806. break;
  3807. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3808. ch_id = SLIM_TX_0;
  3809. break;
  3810. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3811. ch_id = SLIM_TX_3;
  3812. break;
  3813. default:
  3814. ch_id = SLIM_RX_0;
  3815. break;
  3816. }
  3817. return ch_id;
  3818. }
  3819. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3820. {
  3821. int idx = 0;
  3822. switch (be_id) {
  3823. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3824. idx = WSA_CDC_DMA_RX_0;
  3825. break;
  3826. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3827. idx = WSA_CDC_DMA_TX_0;
  3828. break;
  3829. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3830. idx = WSA_CDC_DMA_RX_1;
  3831. break;
  3832. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3833. idx = WSA_CDC_DMA_TX_1;
  3834. break;
  3835. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3836. idx = WSA_CDC_DMA_TX_2;
  3837. break;
  3838. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3839. idx = VA_CDC_DMA_TX_0;
  3840. break;
  3841. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3842. idx = VA_CDC_DMA_TX_1;
  3843. break;
  3844. default:
  3845. idx = VA_CDC_DMA_TX_0;
  3846. break;
  3847. }
  3848. return idx;
  3849. }
  3850. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3851. struct snd_pcm_hw_params *params)
  3852. {
  3853. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3854. struct snd_interval *rate = hw_param_interval(params,
  3855. SNDRV_PCM_HW_PARAM_RATE);
  3856. struct snd_interval *channels = hw_param_interval(params,
  3857. SNDRV_PCM_HW_PARAM_CHANNELS);
  3858. int rc = 0;
  3859. int idx;
  3860. void *config = NULL;
  3861. struct snd_soc_component *component = NULL;
  3862. pr_debug("%s: format = %d, rate = %d\n",
  3863. __func__, params_format(params), params_rate(params));
  3864. switch (dai_link->id) {
  3865. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3866. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3867. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3868. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3869. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3870. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3871. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3872. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3873. slim_rx_cfg[idx].bit_format);
  3874. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3875. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3876. break;
  3877. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3878. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3879. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3880. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3881. slim_tx_cfg[idx].bit_format);
  3882. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3883. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3884. break;
  3885. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3886. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3887. slim_tx_cfg[1].bit_format);
  3888. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3889. channels->min = channels->max = slim_tx_cfg[1].channels;
  3890. break;
  3891. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3892. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3893. SNDRV_PCM_FORMAT_S32_LE);
  3894. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3895. channels->min = channels->max = msm_vi_feed_tx_ch;
  3896. break;
  3897. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3898. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3899. slim_rx_cfg[5].bit_format);
  3900. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3901. channels->min = channels->max = slim_rx_cfg[5].channels;
  3902. break;
  3903. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3904. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  3905. if (!component) {
  3906. pr_err("%s: component is NULL\n", __func__);
  3907. return -EINVAL;
  3908. }
  3909. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3910. channels->min = channels->max = 1;
  3911. config = msm_codec_fn.get_afe_config_fn(component,
  3912. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3913. if (config) {
  3914. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3915. config, SLIMBUS_5_TX);
  3916. if (rc)
  3917. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3918. __func__, rc);
  3919. }
  3920. break;
  3921. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3922. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3923. slim_rx_cfg[SLIM_RX_7].bit_format);
  3924. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3925. channels->min = channels->max =
  3926. slim_rx_cfg[SLIM_RX_7].channels;
  3927. break;
  3928. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3929. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3930. channels->min = channels->max =
  3931. slim_tx_cfg[SLIM_TX_7].channels;
  3932. break;
  3933. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3934. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3935. channels->min = channels->max =
  3936. slim_tx_cfg[SLIM_TX_8].channels;
  3937. break;
  3938. case MSM_BACKEND_DAI_SLIMBUS_9_TX:
  3939. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3940. slim_tx_cfg[SLIM_TX_9].bit_format);
  3941. rate->min = rate->max = slim_tx_cfg[SLIM_TX_9].sample_rate;
  3942. channels->min = channels->max =
  3943. slim_tx_cfg[SLIM_TX_9].channels;
  3944. break;
  3945. case MSM_BACKEND_DAI_USB_RX:
  3946. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3947. usb_rx_cfg.bit_format);
  3948. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3949. channels->min = channels->max = usb_rx_cfg.channels;
  3950. break;
  3951. case MSM_BACKEND_DAI_USB_TX:
  3952. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3953. usb_tx_cfg.bit_format);
  3954. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3955. channels->min = channels->max = usb_tx_cfg.channels;
  3956. break;
  3957. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3958. channels->min = channels->max = proxy_rx_cfg.channels;
  3959. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3960. break;
  3961. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3962. channels->min = channels->max =
  3963. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3964. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3965. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3966. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3967. break;
  3968. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3969. channels->min = channels->max =
  3970. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3971. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3972. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3973. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3974. break;
  3975. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3976. channels->min = channels->max =
  3977. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3978. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3979. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3980. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3981. break;
  3982. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3983. channels->min = channels->max =
  3984. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3985. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3986. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3987. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3988. break;
  3989. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3990. channels->min = channels->max =
  3991. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3992. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3993. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3994. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3995. break;
  3996. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3997. channels->min = channels->max =
  3998. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3999. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4000. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  4001. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  4002. break;
  4003. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  4004. channels->min = channels->max =
  4005. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4006. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4007. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4008. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4009. break;
  4010. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  4011. channels->min = channels->max =
  4012. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4013. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4014. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  4015. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4016. break;
  4017. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  4018. channels->min = channels->max =
  4019. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4020. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4021. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4022. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4023. break;
  4024. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  4025. channels->min = channels->max =
  4026. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4027. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4028. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  4029. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4030. break;
  4031. case MSM_BACKEND_DAI_AUXPCM_RX:
  4032. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4033. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  4034. rate->min = rate->max =
  4035. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  4036. channels->min = channels->max =
  4037. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  4038. break;
  4039. case MSM_BACKEND_DAI_AUXPCM_TX:
  4040. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4041. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  4042. rate->min = rate->max =
  4043. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  4044. channels->min = channels->max =
  4045. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  4046. break;
  4047. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  4048. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4049. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  4050. rate->min = rate->max =
  4051. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  4052. channels->min = channels->max =
  4053. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  4054. break;
  4055. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  4056. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4057. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  4058. rate->min = rate->max =
  4059. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  4060. channels->min = channels->max =
  4061. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  4062. break;
  4063. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  4064. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4065. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  4066. rate->min = rate->max =
  4067. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  4068. channels->min = channels->max =
  4069. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  4070. break;
  4071. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  4072. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4073. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  4074. rate->min = rate->max =
  4075. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  4076. channels->min = channels->max =
  4077. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  4078. break;
  4079. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  4080. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4081. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  4082. rate->min = rate->max =
  4083. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  4084. channels->min = channels->max =
  4085. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  4086. break;
  4087. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  4088. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4089. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  4090. rate->min = rate->max =
  4091. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  4092. channels->min = channels->max =
  4093. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  4094. break;
  4095. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  4096. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4097. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  4098. rate->min = rate->max =
  4099. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  4100. channels->min = channels->max =
  4101. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  4102. break;
  4103. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  4104. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4105. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  4106. rate->min = rate->max =
  4107. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  4108. channels->min = channels->max =
  4109. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  4110. break;
  4111. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  4112. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4113. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  4114. rate->min = rate->max =
  4115. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  4116. channels->min = channels->max =
  4117. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  4118. break;
  4119. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  4120. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4121. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  4122. rate->min = rate->max =
  4123. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  4124. channels->min = channels->max =
  4125. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  4126. break;
  4127. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4128. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4129. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  4130. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  4131. channels->min = channels->max =
  4132. mi2s_rx_cfg[PRIM_MI2S].channels;
  4133. break;
  4134. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4135. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4136. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  4137. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  4138. channels->min = channels->max =
  4139. mi2s_tx_cfg[PRIM_MI2S].channels;
  4140. break;
  4141. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4142. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4143. mi2s_rx_cfg[SEC_MI2S].bit_format);
  4144. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  4145. channels->min = channels->max =
  4146. mi2s_rx_cfg[SEC_MI2S].channels;
  4147. break;
  4148. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4149. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4150. mi2s_tx_cfg[SEC_MI2S].bit_format);
  4151. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  4152. channels->min = channels->max =
  4153. mi2s_tx_cfg[SEC_MI2S].channels;
  4154. break;
  4155. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4156. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4157. mi2s_rx_cfg[TERT_MI2S].bit_format);
  4158. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  4159. channels->min = channels->max =
  4160. mi2s_rx_cfg[TERT_MI2S].channels;
  4161. break;
  4162. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4163. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4164. mi2s_tx_cfg[TERT_MI2S].bit_format);
  4165. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  4166. channels->min = channels->max =
  4167. mi2s_tx_cfg[TERT_MI2S].channels;
  4168. break;
  4169. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4170. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4171. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  4172. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  4173. channels->min = channels->max =
  4174. mi2s_rx_cfg[QUAT_MI2S].channels;
  4175. break;
  4176. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4177. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4178. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  4179. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  4180. channels->min = channels->max =
  4181. mi2s_tx_cfg[QUAT_MI2S].channels;
  4182. break;
  4183. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4184. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4185. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  4186. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  4187. channels->min = channels->max =
  4188. mi2s_rx_cfg[QUIN_MI2S].channels;
  4189. break;
  4190. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4191. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4192. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  4193. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  4194. channels->min = channels->max =
  4195. mi2s_tx_cfg[QUIN_MI2S].channels;
  4196. break;
  4197. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  4198. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4199. mi2s_rx_cfg[SEN_MI2S].bit_format);
  4200. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  4201. channels->min = channels->max =
  4202. mi2s_rx_cfg[SEN_MI2S].channels;
  4203. break;
  4204. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4205. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4206. mi2s_tx_cfg[SEN_MI2S].bit_format);
  4207. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  4208. channels->min = channels->max =
  4209. mi2s_tx_cfg[SEN_MI2S].channels;
  4210. break;
  4211. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4212. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4213. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4214. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4215. cdc_dma_rx_cfg[idx].bit_format);
  4216. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  4217. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  4218. break;
  4219. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4220. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4221. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4222. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4223. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4224. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4225. cdc_dma_tx_cfg[idx].bit_format);
  4226. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  4227. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  4228. break;
  4229. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4230. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4231. SNDRV_PCM_FORMAT_S32_LE);
  4232. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  4233. channels->min = channels->max = msm_vi_feed_tx_ch;
  4234. break;
  4235. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  4236. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4237. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  4238. rate->min = rate->max =
  4239. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  4240. channels->min = channels->max =
  4241. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  4242. break;
  4243. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  4244. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4245. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  4246. rate->min = rate->max =
  4247. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  4248. channels->min = channels->max =
  4249. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  4250. break;
  4251. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  4252. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4253. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  4254. rate->min = rate->max =
  4255. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  4256. channels->min = channels->max =
  4257. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  4258. break;
  4259. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  4260. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4261. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  4262. rate->min = rate->max =
  4263. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  4264. channels->min = channels->max =
  4265. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  4266. break;
  4267. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  4268. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4269. afe_lb_tx_cfg.bit_format);
  4270. rate->min = rate->max = afe_lb_tx_cfg.sample_rate;
  4271. channels->min = channels->max = afe_lb_tx_cfg.channels;
  4272. break;
  4273. default:
  4274. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  4275. break;
  4276. }
  4277. return rc;
  4278. }
  4279. static int msm_afe_set_config(struct snd_soc_component *component)
  4280. {
  4281. int ret = 0;
  4282. void *config_data = NULL;
  4283. if (!msm_codec_fn.get_afe_config_fn) {
  4284. dev_err(component->dev, "%s: codec get afe config not init'ed\n",
  4285. __func__);
  4286. return -EINVAL;
  4287. }
  4288. config_data = msm_codec_fn.get_afe_config_fn(component,
  4289. AFE_CDC_REGISTERS_CONFIG);
  4290. if (config_data) {
  4291. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  4292. if (ret) {
  4293. dev_err(component->dev,
  4294. "%s: Failed to set codec registers config %d\n",
  4295. __func__, ret);
  4296. return ret;
  4297. }
  4298. }
  4299. config_data = msm_codec_fn.get_afe_config_fn(component,
  4300. AFE_CDC_REGISTER_PAGE_CONFIG);
  4301. if (config_data) {
  4302. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  4303. 0);
  4304. if (ret)
  4305. dev_err(component->dev,
  4306. "%s: Failed to set cdc register page config\n",
  4307. __func__);
  4308. }
  4309. config_data = msm_codec_fn.get_afe_config_fn(component,
  4310. AFE_SLIMBUS_SLAVE_CONFIG);
  4311. if (config_data) {
  4312. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  4313. if (ret) {
  4314. dev_err(component->dev,
  4315. "%s: Failed to set slimbus slave config %d\n",
  4316. __func__, ret);
  4317. return ret;
  4318. }
  4319. }
  4320. return 0;
  4321. }
  4322. static void msm_afe_clear_config(void)
  4323. {
  4324. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  4325. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  4326. }
  4327. static int msm_adsp_power_up_config(struct snd_soc_component *component,
  4328. struct snd_card *card)
  4329. {
  4330. int ret = 0;
  4331. unsigned long timeout;
  4332. int adsp_ready = 0;
  4333. bool snd_card_online = 0;
  4334. timeout = jiffies +
  4335. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  4336. do {
  4337. if (!snd_card_online) {
  4338. snd_card_online = snd_card_is_online_state(card);
  4339. pr_debug("%s: Sound card is %s\n", __func__,
  4340. snd_card_online ? "Online" : "Offline");
  4341. }
  4342. if (!adsp_ready) {
  4343. adsp_ready = q6core_is_adsp_ready();
  4344. pr_debug("%s: ADSP Audio is %s\n", __func__,
  4345. adsp_ready ? "ready" : "not ready");
  4346. }
  4347. if (snd_card_online && adsp_ready)
  4348. break;
  4349. /*
  4350. * Sound card/ADSP will be coming up after subsystem restart and
  4351. * it might not be fully up when the control reaches
  4352. * here. So, wait for 50msec before checking ADSP state
  4353. */
  4354. msleep(50);
  4355. } while (time_after(timeout, jiffies));
  4356. if (!snd_card_online || !adsp_ready) {
  4357. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  4358. __func__,
  4359. snd_card_online ? "Online" : "Offline",
  4360. adsp_ready ? "ready" : "not ready");
  4361. ret = -ETIMEDOUT;
  4362. goto err;
  4363. }
  4364. ret = msm_afe_set_config(component);
  4365. if (ret)
  4366. pr_err("%s: Failed to set AFE config. err %d\n",
  4367. __func__, ret);
  4368. return 0;
  4369. err:
  4370. return ret;
  4371. }
  4372. static int qcs405_notifier_service_cb(struct notifier_block *this,
  4373. unsigned long opcode, void *ptr)
  4374. {
  4375. int ret;
  4376. struct snd_soc_card *card = NULL;
  4377. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  4378. struct snd_soc_pcm_runtime *rtd;
  4379. struct snd_soc_dai *codec_dai;
  4380. struct snd_soc_component *component;
  4381. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  4382. switch (opcode) {
  4383. case AUDIO_NOTIFIER_SERVICE_DOWN:
  4384. /*
  4385. * Use flag to ignore initial boot notifications
  4386. * On initial boot msm_adsp_power_up_config is
  4387. * called on init. There is no need to clear
  4388. * and set the config again on initial boot.
  4389. */
  4390. if (is_initial_boot)
  4391. break;
  4392. msm_afe_clear_config();
  4393. break;
  4394. case AUDIO_NOTIFIER_SERVICE_UP:
  4395. if (is_initial_boot) {
  4396. is_initial_boot = false;
  4397. break;
  4398. }
  4399. if (!spdev)
  4400. return -EINVAL;
  4401. card = platform_get_drvdata(spdev);
  4402. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  4403. if (!rtd) {
  4404. dev_err(card->dev,
  4405. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  4406. __func__, be_dl_name);
  4407. ret = -EINVAL;
  4408. goto err;
  4409. }
  4410. codec_dai = rtd->codec_dai;
  4411. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec"))
  4412. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4413. ret = msm_adsp_power_up_config(component, card->snd_card);
  4414. if (ret < 0) {
  4415. dev_err(card->dev,
  4416. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  4417. __func__, ret);
  4418. goto err;
  4419. }
  4420. break;
  4421. default:
  4422. break;
  4423. }
  4424. err:
  4425. return NOTIFY_OK;
  4426. }
  4427. static struct notifier_block service_nb = {
  4428. .notifier_call = qcs405_notifier_service_cb,
  4429. .priority = -INT_MAX,
  4430. };
  4431. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4432. {
  4433. int ret = 0;
  4434. void *config_data;
  4435. struct snd_soc_component *component;
  4436. struct snd_soc_dapm_context *dapm;
  4437. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4438. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4439. struct snd_card *card;
  4440. struct msm_asoc_mach_data *pdata =
  4441. snd_soc_card_get_drvdata(rtd->card);
  4442. /*
  4443. * Codec SLIMBUS configuration
  4444. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4445. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4446. * TX14, TX15, TX16
  4447. */
  4448. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4449. 151, 152, 153, 154, 155, 156};
  4450. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4451. 134, 135, 136, 137, 138, 139,
  4452. 140, 141, 142, 143};
  4453. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4454. rtd->pmdown_time = 0;
  4455. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) {
  4456. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4457. dapm = snd_soc_component_get_dapm(component);
  4458. }
  4459. ret = snd_soc_add_component_controls(component, msm_snd_sb_controls,
  4460. ARRAY_SIZE(msm_snd_sb_controls));
  4461. if (ret < 0) {
  4462. pr_err("%s: add_codec_controls failed, err %d\n",
  4463. __func__, ret);
  4464. return ret;
  4465. }
  4466. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4467. ARRAY_SIZE(msm_dapm_widgets));
  4468. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4469. ARRAY_SIZE(wcd_audio_paths));
  4470. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4471. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4472. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4473. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4474. snd_soc_dapm_sync(dapm);
  4475. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4476. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4477. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4478. ret = msm_adsp_power_up_config(component, rtd->card->snd_card);
  4479. if (ret) {
  4480. dev_err(component->dev, "%s: Failed to set AFE config %d\n",
  4481. __func__, ret);
  4482. goto err;
  4483. }
  4484. config_data = msm_codec_fn.get_afe_config_fn(component,
  4485. AFE_AANC_VERSION);
  4486. if (config_data) {
  4487. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4488. if (ret) {
  4489. dev_err(component->dev, "%s: Failed to set aanc version %d\n",
  4490. __func__, ret);
  4491. goto err;
  4492. }
  4493. }
  4494. card = rtd->card->snd_card;
  4495. if (!pdata->codec_root)
  4496. pdata->codec_root = snd_info_create_subdir(card->module,
  4497. "codecs", card->proc_root);
  4498. if (!pdata->codec_root) {
  4499. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4500. __func__);
  4501. ret = 0;
  4502. goto err;
  4503. }
  4504. tasha_codec_info_create_codec_entry(pdata->codec_root, component);
  4505. codec_reg_done = true;
  4506. return 0;
  4507. err:
  4508. return ret;
  4509. }
  4510. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4511. {
  4512. int ret = 0;
  4513. struct snd_soc_component *component;
  4514. struct snd_soc_dapm_context *dapm;
  4515. struct snd_card *card;
  4516. struct msm_asoc_mach_data *pdata =
  4517. snd_soc_card_get_drvdata(rtd->card);
  4518. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4519. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4520. if (!component) {
  4521. pr_err("%s: component is NULL\n", __func__);
  4522. return -EINVAL;
  4523. }
  4524. dapm = snd_soc_component_get_dapm(component);
  4525. ret = snd_soc_add_component_controls(component, msm_snd_va_controls,
  4526. ARRAY_SIZE(msm_snd_va_controls));
  4527. if (ret < 0) {
  4528. dev_err(component->dev, "%s: add_component_controls for va failed, err %d\n",
  4529. __func__, ret);
  4530. return ret;
  4531. }
  4532. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4533. ARRAY_SIZE(msm_va_dapm_widgets));
  4534. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4535. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4536. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4537. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4538. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4539. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4540. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4541. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4542. snd_soc_dapm_sync(dapm);
  4543. card = rtd->card->snd_card;
  4544. if (!pdata->codec_root)
  4545. pdata->codec_root = snd_info_create_subdir(card->module,
  4546. "codecs", card->proc_root);
  4547. if (!pdata->codec_root) {
  4548. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4549. __func__);
  4550. ret = 0;
  4551. goto done;
  4552. }
  4553. bolero_info_create_codec_entry(pdata->codec_root, component);
  4554. done:
  4555. return ret;
  4556. }
  4557. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4558. {
  4559. int ret = 0;
  4560. struct snd_soc_component *component = NULL;
  4561. struct snd_soc_dapm_context *dapm = NULL;
  4562. struct snd_soc_component *aux_comp = NULL;
  4563. struct snd_card *card = NULL;
  4564. struct msm_asoc_mach_data *pdata =
  4565. snd_soc_card_get_drvdata(rtd->card);
  4566. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4567. if (!component) {
  4568. pr_err("%s: component is NULL\n", __func__);
  4569. return -EINVAL;
  4570. }
  4571. dapm = snd_soc_component_get_dapm(component);
  4572. ret = snd_soc_add_component_controls(component, msm_snd_wsa_controls,
  4573. ARRAY_SIZE(msm_snd_wsa_controls));
  4574. if (ret < 0) {
  4575. dev_err(component->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  4576. __func__, ret);
  4577. return ret;
  4578. }
  4579. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  4580. ARRAY_SIZE(msm_wsa_dapm_widgets));
  4581. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4582. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4583. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4584. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4585. snd_soc_dapm_sync(dapm);
  4586. /*
  4587. * Send speaker configuration only for WSA8810.
  4588. * Default configuration is for WSA8815.
  4589. */
  4590. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4591. __func__, rtd->card->num_aux_devs);
  4592. if (rtd->card->num_aux_devs &&
  4593. !list_empty(&rtd->card->component_dev_list)) {
  4594. aux_comp = list_first_entry(
  4595. &rtd->card->component_dev_list,
  4596. struct snd_soc_component,
  4597. card_aux_list);
  4598. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4599. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4600. wsa_macro_set_spkr_mode(component,
  4601. WSA_MACRO_SPKR_MODE_1);
  4602. wsa_macro_set_spkr_gain_offset(component,
  4603. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4604. }
  4605. }
  4606. card = rtd->card->snd_card;
  4607. if (!pdata->codec_root)
  4608. pdata->codec_root = snd_info_create_subdir(card->module,
  4609. "codecs", card->proc_root);
  4610. if (!pdata->codec_root) {
  4611. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  4612. __func__);
  4613. ret = 0;
  4614. goto done;
  4615. }
  4616. bolero_info_create_codec_entry(pdata->codec_root, component);
  4617. done:
  4618. return ret;
  4619. }
  4620. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4621. {
  4622. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4623. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161, 162};
  4624. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4625. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4626. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4627. }
  4628. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  4629. struct snd_pcm_hw_params *params)
  4630. {
  4631. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4632. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4633. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4634. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4635. int ret = 0;
  4636. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  4637. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4638. u32 user_set_tx_ch = 0;
  4639. u32 rx_ch_count;
  4640. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4641. ret = snd_soc_dai_get_channel_map(codec_dai,
  4642. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4643. if (ret < 0) {
  4644. pr_err("%s: failed to get codec chan map, err:%d\n",
  4645. __func__, ret);
  4646. goto err;
  4647. }
  4648. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  4649. pr_debug("%s: rx_5_ch=%d\n", __func__,
  4650. slim_rx_cfg[5].channels);
  4651. rx_ch_count = slim_rx_cfg[5].channels;
  4652. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  4653. pr_debug("%s: rx_2_ch=%d\n", __func__,
  4654. slim_rx_cfg[2].channels);
  4655. rx_ch_count = slim_rx_cfg[2].channels;
  4656. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  4657. pr_debug("%s: rx_6_ch=%d\n", __func__,
  4658. slim_rx_cfg[6].channels);
  4659. rx_ch_count = slim_rx_cfg[6].channels;
  4660. } else {
  4661. pr_debug("%s: rx_0_ch=%d\n", __func__,
  4662. slim_rx_cfg[0].channels);
  4663. rx_ch_count = slim_rx_cfg[0].channels;
  4664. }
  4665. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4666. rx_ch_count, rx_ch);
  4667. if (ret < 0) {
  4668. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4669. __func__, ret);
  4670. goto err;
  4671. }
  4672. } else {
  4673. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  4674. codec_dai->name, codec_dai->id, user_set_tx_ch);
  4675. ret = snd_soc_dai_get_channel_map(codec_dai,
  4676. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4677. if (ret < 0) {
  4678. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  4679. __func__, ret);
  4680. goto err;
  4681. }
  4682. /* For <codec>_tx1 case */
  4683. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  4684. user_set_tx_ch = slim_tx_cfg[0].channels;
  4685. /* For <codec>_tx3 case */
  4686. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  4687. user_set_tx_ch = slim_tx_cfg[1].channels;
  4688. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  4689. user_set_tx_ch = msm_vi_feed_tx_ch;
  4690. else
  4691. user_set_tx_ch = tx_ch_cnt;
  4692. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  4693. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  4694. tx_ch_cnt, dai_link->id);
  4695. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4696. user_set_tx_ch, tx_ch, 0, 0);
  4697. if (ret < 0)
  4698. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  4699. __func__, ret);
  4700. }
  4701. err:
  4702. return ret;
  4703. }
  4704. static int msm_snd_auxpcm_startup(struct snd_pcm_substream *substream)
  4705. {
  4706. int ret = 0;
  4707. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4708. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4709. ret = qcs405_send_island_vad_config(dai_link->id);
  4710. if (ret) {
  4711. pr_err("%s: send island/vad cfg failed, err = %d\n",
  4712. __func__, ret);
  4713. }
  4714. return ret;
  4715. }
  4716. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  4717. {
  4718. int ret = 0;
  4719. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4720. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4721. ret = qcs405_send_island_vad_config(dai_link->id);
  4722. if (ret) {
  4723. pr_err("%s: send island/vad cfg failed, err = %d\n",
  4724. __func__, ret);
  4725. }
  4726. return ret;
  4727. }
  4728. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4729. struct snd_pcm_hw_params *params)
  4730. {
  4731. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4732. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4733. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4734. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4735. int ret = 0;
  4736. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4737. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4738. u32 user_set_tx_ch = 0;
  4739. u32 user_set_rx_ch = 0;
  4740. u32 ch_id;
  4741. ret = snd_soc_dai_get_channel_map(codec_dai,
  4742. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4743. &rx_ch_cdc_dma);
  4744. if (ret < 0) {
  4745. pr_err("%s: failed to get codec chan map, err:%d\n",
  4746. __func__, ret);
  4747. goto err;
  4748. }
  4749. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4750. switch (dai_link->id) {
  4751. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4752. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4753. {
  4754. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4755. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4756. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4757. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4758. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4759. user_set_rx_ch, &rx_ch_cdc_dma);
  4760. if (ret < 0) {
  4761. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4762. __func__, ret);
  4763. goto err;
  4764. }
  4765. }
  4766. break;
  4767. }
  4768. } else {
  4769. switch (dai_link->id) {
  4770. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4771. {
  4772. user_set_tx_ch = msm_vi_feed_tx_ch;
  4773. }
  4774. break;
  4775. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4776. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4777. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4778. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4779. {
  4780. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4781. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4782. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4783. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4784. }
  4785. break;
  4786. }
  4787. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4788. &tx_ch_cdc_dma, 0, 0);
  4789. if (ret < 0) {
  4790. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4791. __func__, ret);
  4792. goto err;
  4793. }
  4794. }
  4795. err:
  4796. return ret;
  4797. }
  4798. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4799. struct snd_pcm_hw_params *params)
  4800. {
  4801. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4802. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4803. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4804. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4805. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4806. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4807. int ret;
  4808. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4809. codec_dai->name, codec_dai->id);
  4810. ret = snd_soc_dai_get_channel_map(codec_dai,
  4811. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4812. if (ret) {
  4813. dev_err(rtd->dev,
  4814. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4815. __func__, ret);
  4816. goto err;
  4817. }
  4818. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4819. __func__, tx_ch_cnt, dai_link->id);
  4820. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4821. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4822. if (ret)
  4823. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4824. __func__, ret);
  4825. err:
  4826. return ret;
  4827. }
  4828. static int msm_get_port_id(int be_id)
  4829. {
  4830. int afe_port_id;
  4831. switch (be_id) {
  4832. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4833. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  4834. break;
  4835. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4836. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  4837. break;
  4838. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4839. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  4840. break;
  4841. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4842. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4843. break;
  4844. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4845. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4846. break;
  4847. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4848. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4849. break;
  4850. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4851. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4852. break;
  4853. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4854. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4855. break;
  4856. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4857. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4858. break;
  4859. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4860. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4861. break;
  4862. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  4863. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  4864. break;
  4865. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4866. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  4867. break;
  4868. default:
  4869. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4870. afe_port_id = -EINVAL;
  4871. }
  4872. return afe_port_id;
  4873. }
  4874. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4875. {
  4876. u32 bit_per_sample;
  4877. switch (bit_format) {
  4878. case SNDRV_PCM_FORMAT_S32_LE:
  4879. case SNDRV_PCM_FORMAT_S24_3LE:
  4880. case SNDRV_PCM_FORMAT_S24_LE:
  4881. bit_per_sample = 32;
  4882. break;
  4883. case SNDRV_PCM_FORMAT_S16_LE:
  4884. default:
  4885. bit_per_sample = 16;
  4886. break;
  4887. }
  4888. return bit_per_sample;
  4889. }
  4890. static void update_mi2s_clk_val(int dai_id, int stream)
  4891. {
  4892. u32 bit_per_sample;
  4893. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4894. bit_per_sample =
  4895. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4896. mi2s_clk[dai_id].clk_freq_in_hz =
  4897. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4898. } else {
  4899. bit_per_sample =
  4900. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4901. mi2s_clk[dai_id].clk_freq_in_hz =
  4902. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4903. }
  4904. }
  4905. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4906. {
  4907. int ret = 0;
  4908. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4909. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4910. int port_id = 0;
  4911. int index = cpu_dai->id;
  4912. port_id = msm_get_port_id(rtd->dai_link->id);
  4913. if (port_id < 0) {
  4914. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4915. ret = port_id;
  4916. goto err;
  4917. }
  4918. if (enable) {
  4919. update_mi2s_clk_val(index, substream->stream);
  4920. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4921. mi2s_clk[index].clk_freq_in_hz);
  4922. }
  4923. mi2s_clk[index].enable = enable;
  4924. ret = afe_set_lpass_clock_v2(port_id,
  4925. &mi2s_clk[index]);
  4926. if (ret < 0) {
  4927. dev_err(rtd->card->dev,
  4928. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4929. __func__, port_id, ret);
  4930. goto err;
  4931. }
  4932. err:
  4933. return ret;
  4934. }
  4935. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4936. struct snd_pcm_hw_params *params)
  4937. {
  4938. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4939. struct snd_interval *rate = hw_param_interval(params,
  4940. SNDRV_PCM_HW_PARAM_RATE);
  4941. struct snd_interval *channels = hw_param_interval(params,
  4942. SNDRV_PCM_HW_PARAM_CHANNELS);
  4943. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4944. channels->min = channels->max =
  4945. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4946. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4947. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4948. rate->min = rate->max =
  4949. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4950. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4951. channels->min = channels->max =
  4952. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4953. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4954. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4955. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4956. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4957. channels->min = channels->max =
  4958. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4959. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4960. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4961. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4962. } else {
  4963. pr_err("%s: dai id 0x%x not supported\n",
  4964. __func__, cpu_dai->id);
  4965. return -EINVAL;
  4966. }
  4967. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4968. __func__, cpu_dai->id, channels->max, rate->max,
  4969. params_format(params));
  4970. return 0;
  4971. }
  4972. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4973. struct snd_pcm_hw_params *params)
  4974. {
  4975. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4976. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4977. int ret = 0;
  4978. int slot_width = 32;
  4979. int channels, slots = 8;
  4980. unsigned int slot_mask, rate, clk_freq;
  4981. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4982. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4983. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4984. switch (cpu_dai->id) {
  4985. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4986. channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4987. break;
  4988. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4989. channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4990. break;
  4991. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4992. channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4993. break;
  4994. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4995. channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4996. break;
  4997. case AFE_PORT_ID_QUINARY_TDM_RX:
  4998. channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4999. break;
  5000. case AFE_PORT_ID_PRIMARY_TDM_TX:
  5001. channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  5002. break;
  5003. case AFE_PORT_ID_SECONDARY_TDM_TX:
  5004. channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  5005. break;
  5006. case AFE_PORT_ID_TERTIARY_TDM_TX:
  5007. channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  5008. break;
  5009. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  5010. channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  5011. break;
  5012. case AFE_PORT_ID_QUINARY_TDM_TX:
  5013. channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  5014. break;
  5015. default:
  5016. pr_err("%s: dai id 0x%x not supported\n",
  5017. __func__, cpu_dai->id);
  5018. return -EINVAL;
  5019. }
  5020. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  5021. /*2 slot config - bits 0 and 1 set for the first two slots */
  5022. slot_mask = 0x0000FFFF >> (16-channels);
  5023. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  5024. __func__, slot_width, slots);
  5025. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  5026. slots, slot_width);
  5027. if (ret < 0) {
  5028. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  5029. __func__, ret);
  5030. goto end;
  5031. }
  5032. ret = snd_soc_dai_set_channel_map(cpu_dai,
  5033. 0, NULL, channels, slot_offset);
  5034. if (ret < 0) {
  5035. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  5036. __func__, ret);
  5037. goto end;
  5038. }
  5039. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  5040. /*2 slot config - bits 0 and 1 set for the first two slots */
  5041. slot_mask = 0x0000FFFF >> (16-channels);
  5042. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  5043. __func__, slot_width, slots);
  5044. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  5045. slots, slot_width);
  5046. if (ret < 0) {
  5047. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  5048. __func__, ret);
  5049. goto end;
  5050. }
  5051. ret = snd_soc_dai_set_channel_map(cpu_dai,
  5052. channels, slot_offset, 0, NULL);
  5053. if (ret < 0) {
  5054. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  5055. __func__, ret);
  5056. goto end;
  5057. }
  5058. } else {
  5059. ret = -EINVAL;
  5060. pr_err("%s: invalid use case, err:%d\n",
  5061. __func__, ret);
  5062. goto end;
  5063. }
  5064. rate = params_rate(params);
  5065. clk_freq = rate * slot_width * slots;
  5066. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  5067. if (ret < 0)
  5068. pr_err("%s: failed to set tdm clk, err:%d\n",
  5069. __func__, ret);
  5070. end:
  5071. return ret;
  5072. }
  5073. static int msm_get_tdm_mode(u32 port_id)
  5074. {
  5075. u32 tdm_mode;
  5076. switch (port_id) {
  5077. case AFE_PORT_ID_PRIMARY_TDM_RX:
  5078. case AFE_PORT_ID_PRIMARY_TDM_TX:
  5079. tdm_mode = TDM_PRI;
  5080. break;
  5081. case AFE_PORT_ID_SECONDARY_TDM_RX:
  5082. case AFE_PORT_ID_SECONDARY_TDM_TX:
  5083. tdm_mode = TDM_SEC;
  5084. break;
  5085. case AFE_PORT_ID_TERTIARY_TDM_RX:
  5086. case AFE_PORT_ID_TERTIARY_TDM_TX:
  5087. tdm_mode = TDM_TERT;
  5088. break;
  5089. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  5090. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  5091. tdm_mode = TDM_QUAT;
  5092. break;
  5093. case AFE_PORT_ID_QUINARY_TDM_RX:
  5094. case AFE_PORT_ID_QUINARY_TDM_TX:
  5095. tdm_mode = TDM_QUIN;
  5096. break;
  5097. default:
  5098. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  5099. tdm_mode = -EINVAL;
  5100. }
  5101. return tdm_mode;
  5102. }
  5103. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  5104. {
  5105. int ret = 0;
  5106. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5107. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5108. struct snd_soc_card *card = rtd->card;
  5109. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5110. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5111. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  5112. if (tdm_mode >= TDM_INTERFACE_MAX) {
  5113. ret = -EINVAL;
  5114. pr_err("%s: Invalid TDM interface %d\n",
  5115. __func__, ret);
  5116. return ret;
  5117. }
  5118. if (pdata->mi2s_gpio_p[tdm_mode]) {
  5119. ret = msm_cdc_pinctrl_select_active_state(
  5120. pdata->mi2s_gpio_p[tdm_mode]);
  5121. if (ret)
  5122. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  5123. __func__, ret);
  5124. }
  5125. /* Enable Mic bias for TDM Mics */
  5126. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  5127. if (pdata->tdm_micb_supply) {
  5128. ret = regulator_set_voltage(pdata->tdm_micb_supply,
  5129. pdata->tdm_micb_voltage,
  5130. pdata->tdm_micb_voltage);
  5131. if (ret) {
  5132. pr_err("%s: Setting voltage failed, err = %d\n",
  5133. __func__, ret);
  5134. return ret;
  5135. }
  5136. ret = regulator_set_load(pdata->tdm_micb_supply,
  5137. pdata->tdm_micb_current);
  5138. if (ret) {
  5139. pr_err("%s: Setting current failed, err = %d\n",
  5140. __func__, ret);
  5141. return ret;
  5142. }
  5143. ret = regulator_enable(pdata->tdm_micb_supply);
  5144. if (ret) {
  5145. pr_err("%s: regulator enable failed, err = %d\n",
  5146. __func__, ret);
  5147. return ret;
  5148. }
  5149. }
  5150. }
  5151. ret = qcs405_send_island_vad_config(dai_link->id);
  5152. if (ret) {
  5153. pr_err("%s: send island/vad cfg failed, err = %d\n",
  5154. __func__, ret);
  5155. return ret;
  5156. }
  5157. return ret;
  5158. }
  5159. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  5160. {
  5161. int ret = 0;
  5162. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5163. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5164. struct snd_soc_card *card = rtd->card;
  5165. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5166. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  5167. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  5168. if (pdata->tdm_micb_supply) {
  5169. ret = regulator_disable(pdata->tdm_micb_supply);
  5170. if (ret)
  5171. pr_err("%s: regulator disable failed, err = %d\n",
  5172. __func__, ret);
  5173. regulator_set_voltage(pdata->tdm_micb_supply, 0,
  5174. pdata->tdm_micb_voltage);
  5175. regulator_set_load(pdata->tdm_micb_supply, 0);
  5176. }
  5177. }
  5178. if (pdata->mi2s_gpio_p[tdm_mode]) {
  5179. ret = msm_cdc_pinctrl_select_sleep_state(
  5180. pdata->mi2s_gpio_p[tdm_mode]);
  5181. if (ret)
  5182. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  5183. __func__, ret);
  5184. }
  5185. }
  5186. static struct snd_soc_ops qcs405_tdm_be_ops = {
  5187. .hw_params = qcs405_tdm_snd_hw_params,
  5188. .startup = qcs405_tdm_snd_startup,
  5189. .shutdown = qcs405_tdm_snd_shutdown
  5190. };
  5191. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  5192. {
  5193. cpumask_t mask;
  5194. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  5195. pm_qos_remove_request(&substream->latency_pm_qos_req);
  5196. cpumask_clear(&mask);
  5197. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  5198. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  5199. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  5200. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  5201. pm_qos_add_request(&substream->latency_pm_qos_req,
  5202. PM_QOS_CPU_DMA_LATENCY,
  5203. MSM_LL_QOS_VALUE);
  5204. return 0;
  5205. }
  5206. static struct snd_soc_ops msm_fe_qos_ops = {
  5207. .prepare = msm_fe_qos_prepare,
  5208. };
  5209. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  5210. {
  5211. int ret = 0;
  5212. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5213. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5214. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5215. int index = cpu_dai->id;
  5216. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  5217. struct snd_soc_card *card = rtd->card;
  5218. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5219. dev_dbg(rtd->card->dev,
  5220. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5221. __func__, substream->name, substream->stream,
  5222. cpu_dai->name, cpu_dai->id);
  5223. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5224. ret = -EINVAL;
  5225. dev_err(rtd->card->dev,
  5226. "%s: CPU DAI id (%d) out of range\n",
  5227. __func__, cpu_dai->id);
  5228. goto err;
  5229. }
  5230. /*
  5231. * Mutex protection in case the same MI2S
  5232. * interface using for both TX and RX so
  5233. * that the same clock won't be enable twice.
  5234. */
  5235. mutex_lock(&mi2s_intf_conf[index].lock);
  5236. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  5237. /* Check if msm needs to provide the clock to the interface */
  5238. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  5239. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  5240. fmt = SND_SOC_DAIFMT_CBM_CFM;
  5241. }
  5242. ret = msm_mi2s_set_sclk(substream, true);
  5243. if (ret < 0) {
  5244. dev_err(rtd->card->dev,
  5245. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  5246. __func__, ret);
  5247. goto clean_up;
  5248. }
  5249. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  5250. if (ret < 0) {
  5251. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  5252. __func__, index, ret);
  5253. goto clk_off;
  5254. }
  5255. if (pdata->mi2s_gpio_p[index])
  5256. msm_cdc_pinctrl_select_active_state(
  5257. pdata->mi2s_gpio_p[index]);
  5258. }
  5259. ret = qcs405_send_island_vad_config(dai_link->id);
  5260. if (ret) {
  5261. pr_err("%s: send island/vad cfg failed, err = %d\n",
  5262. __func__, ret);
  5263. return ret;
  5264. }
  5265. clk_off:
  5266. if (ret < 0)
  5267. msm_mi2s_set_sclk(substream, false);
  5268. clean_up:
  5269. if (ret < 0)
  5270. mi2s_intf_conf[index].ref_cnt--;
  5271. mutex_unlock(&mi2s_intf_conf[index].lock);
  5272. err:
  5273. return ret;
  5274. }
  5275. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  5276. {
  5277. int ret;
  5278. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5279. int index = rtd->cpu_dai->id;
  5280. struct snd_soc_card *card = rtd->card;
  5281. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5282. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5283. substream->name, substream->stream);
  5284. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5285. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  5286. return;
  5287. }
  5288. mutex_lock(&mi2s_intf_conf[index].lock);
  5289. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  5290. if (pdata->mi2s_gpio_p[index])
  5291. msm_cdc_pinctrl_select_sleep_state(
  5292. pdata->mi2s_gpio_p[index]);
  5293. ret = msm_mi2s_set_sclk(substream, false);
  5294. if (ret < 0)
  5295. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  5296. __func__, index, ret);
  5297. }
  5298. mutex_unlock(&mi2s_intf_conf[index].lock);
  5299. }
  5300. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  5301. {
  5302. int ret = 0;
  5303. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5304. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5305. int port_id = cpu_dai->id;
  5306. struct afe_clk_set clk_cfg;
  5307. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  5308. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  5309. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  5310. clk_cfg.enable = enable;
  5311. /* Set core clock (based on sample rate for RX, fixed for TX) */
  5312. switch (port_id) {
  5313. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5314. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  5315. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  5316. clk_cfg.clk_freq_in_hz =
  5317. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5318. break;
  5319. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5320. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  5321. clk_cfg.clk_freq_in_hz =
  5322. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5323. break;
  5324. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  5325. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  5326. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5327. break;
  5328. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  5329. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  5330. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  5331. break;
  5332. }
  5333. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5334. if (ret < 0) {
  5335. dev_err(rtd->card->dev,
  5336. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  5337. __func__, port_id, ret);
  5338. goto err;
  5339. }
  5340. /* Set NPL clock for RX in addition */
  5341. switch (port_id) {
  5342. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5343. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  5344. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5345. if (ret < 0) {
  5346. dev_err(rtd->card->dev,
  5347. "%s: afe NPL failed port 0x%x, err:%d\n",
  5348. __func__, port_id, ret);
  5349. goto err;
  5350. }
  5351. break;
  5352. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5353. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  5354. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  5355. if (ret < 0) {
  5356. dev_err(rtd->card->dev,
  5357. "%s: afe NPL failed for port 0x%x, err:%d\n",
  5358. __func__, port_id, ret);
  5359. goto err;
  5360. }
  5361. break;
  5362. }
  5363. if (enable) {
  5364. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  5365. clk_cfg.clk_freq_in_hz);
  5366. }
  5367. err:
  5368. return ret;
  5369. }
  5370. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  5371. {
  5372. int ret = 0;
  5373. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5374. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5375. int port_id = cpu_dai->id;
  5376. dev_dbg(rtd->card->dev,
  5377. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5378. __func__, substream->name, substream->stream,
  5379. cpu_dai->name, cpu_dai->id);
  5380. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5381. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5382. ret = -EINVAL;
  5383. dev_err(rtd->card->dev,
  5384. "%s: CPU DAI id (%d) out of range\n",
  5385. __func__, cpu_dai->id);
  5386. goto err;
  5387. }
  5388. ret = msm_spdif_set_clk(substream, true);
  5389. if (ret < 0) {
  5390. dev_err(rtd->card->dev,
  5391. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  5392. __func__, port_id, ret);
  5393. }
  5394. err:
  5395. return ret;
  5396. }
  5397. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  5398. {
  5399. int ret;
  5400. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5401. int port_id = rtd->cpu_dai->id;
  5402. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5403. substream->name, substream->stream);
  5404. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  5405. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  5406. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  5407. return;
  5408. }
  5409. ret = msm_spdif_set_clk(substream, false);
  5410. if (ret < 0)
  5411. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  5412. __func__, port_id, ret);
  5413. }
  5414. static struct snd_soc_ops msm_mi2s_be_ops = {
  5415. .startup = msm_mi2s_snd_startup,
  5416. .shutdown = msm_mi2s_snd_shutdown,
  5417. };
  5418. static struct snd_soc_ops msm_auxpcm_be_ops = {
  5419. .startup = msm_snd_auxpcm_startup,
  5420. };
  5421. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  5422. .startup = msm_snd_cdc_dma_startup,
  5423. .hw_params = msm_snd_cdc_dma_hw_params,
  5424. };
  5425. static struct snd_soc_ops msm_be_ops = {
  5426. .hw_params = msm_snd_hw_params,
  5427. };
  5428. static struct snd_soc_ops msm_wcn_ops = {
  5429. .hw_params = msm_wcn_hw_params,
  5430. };
  5431. static struct snd_soc_ops msm_spdif_be_ops = {
  5432. .startup = msm_spdif_snd_startup,
  5433. .shutdown = msm_spdif_snd_shutdown,
  5434. };
  5435. /* Digital audio interface glue - connects codec <---> CPU */
  5436. static struct snd_soc_dai_link msm_common_dai_links[] = {
  5437. /* FrontEnd DAI Links */
  5438. {
  5439. .name = MSM_DAILINK_NAME(Media1),
  5440. .stream_name = "MultiMedia1",
  5441. .cpu_dai_name = "MultiMedia1",
  5442. .platform_name = "msm-pcm-dsp.0",
  5443. .dynamic = 1,
  5444. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5445. .dpcm_playback = 1,
  5446. .dpcm_capture = 1,
  5447. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5448. SND_SOC_DPCM_TRIGGER_POST},
  5449. .codec_dai_name = "snd-soc-dummy-dai",
  5450. .codec_name = "snd-soc-dummy",
  5451. .ignore_suspend = 1,
  5452. /* this dainlink has playback support */
  5453. .ignore_pmdown_time = 1,
  5454. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5455. },
  5456. {
  5457. .name = MSM_DAILINK_NAME(Media2),
  5458. .stream_name = "MultiMedia2",
  5459. .cpu_dai_name = "MultiMedia2",
  5460. .platform_name = "msm-pcm-dsp.0",
  5461. .dynamic = 1,
  5462. .dpcm_playback = 1,
  5463. .dpcm_capture = 1,
  5464. .codec_dai_name = "snd-soc-dummy-dai",
  5465. .codec_name = "snd-soc-dummy",
  5466. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5467. SND_SOC_DPCM_TRIGGER_POST},
  5468. .ignore_suspend = 1,
  5469. /* this dainlink has playback support */
  5470. .ignore_pmdown_time = 1,
  5471. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  5472. },
  5473. {
  5474. .name = "VoiceMMode1",
  5475. .stream_name = "VoiceMMode1",
  5476. .cpu_dai_name = "VoiceMMode1",
  5477. .platform_name = "msm-pcm-voice",
  5478. .dynamic = 1,
  5479. .dpcm_playback = 1,
  5480. .dpcm_capture = 1,
  5481. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5482. SND_SOC_DPCM_TRIGGER_POST},
  5483. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5484. .ignore_suspend = 1,
  5485. .ignore_pmdown_time = 1,
  5486. .codec_dai_name = "snd-soc-dummy-dai",
  5487. .codec_name = "snd-soc-dummy",
  5488. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  5489. },
  5490. {
  5491. .name = "MSM VoIP",
  5492. .stream_name = "VoIP",
  5493. .cpu_dai_name = "VoIP",
  5494. .platform_name = "msm-voip-dsp",
  5495. .dynamic = 1,
  5496. .dpcm_playback = 1,
  5497. .dpcm_capture = 1,
  5498. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5499. SND_SOC_DPCM_TRIGGER_POST},
  5500. .codec_dai_name = "snd-soc-dummy-dai",
  5501. .codec_name = "snd-soc-dummy",
  5502. .ignore_suspend = 1,
  5503. /* this dainlink has playback support */
  5504. .ignore_pmdown_time = 1,
  5505. .id = MSM_FRONTEND_DAI_VOIP,
  5506. },
  5507. {
  5508. .name = MSM_DAILINK_NAME(ULL),
  5509. .stream_name = "MultiMedia3",
  5510. .cpu_dai_name = "MultiMedia3",
  5511. .platform_name = "msm-pcm-dsp.2",
  5512. .dynamic = 1,
  5513. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5514. .dpcm_playback = 1,
  5515. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5516. SND_SOC_DPCM_TRIGGER_POST},
  5517. .codec_dai_name = "snd-soc-dummy-dai",
  5518. .codec_name = "snd-soc-dummy",
  5519. .ignore_suspend = 1,
  5520. /* this dainlink has playback support */
  5521. .ignore_pmdown_time = 1,
  5522. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  5523. },
  5524. /* Hostless PCM purpose */
  5525. {
  5526. .name = "SLIMBUS_0 Hostless",
  5527. .stream_name = "SLIMBUS_0 Hostless",
  5528. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  5529. .platform_name = "msm-pcm-hostless",
  5530. .dynamic = 1,
  5531. .dpcm_playback = 1,
  5532. .dpcm_capture = 1,
  5533. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5534. SND_SOC_DPCM_TRIGGER_POST},
  5535. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5536. .ignore_suspend = 1,
  5537. /* this dailink has playback support */
  5538. .ignore_pmdown_time = 1,
  5539. .codec_dai_name = "snd-soc-dummy-dai",
  5540. .codec_name = "snd-soc-dummy",
  5541. },
  5542. {
  5543. .name = "MSM AFE-PCM RX",
  5544. .stream_name = "AFE-PROXY RX",
  5545. .cpu_dai_name = "msm-dai-q6-dev.241",
  5546. .codec_name = "msm-stub-codec.1",
  5547. .codec_dai_name = "msm-stub-rx",
  5548. .platform_name = "msm-pcm-afe",
  5549. .dpcm_playback = 1,
  5550. .ignore_suspend = 1,
  5551. /* this dainlink has playback support */
  5552. .ignore_pmdown_time = 1,
  5553. },
  5554. {
  5555. .name = "MSM AFE-PCM TX",
  5556. .stream_name = "AFE-PROXY TX",
  5557. .cpu_dai_name = "msm-dai-q6-dev.240",
  5558. .codec_name = "msm-stub-codec.1",
  5559. .codec_dai_name = "msm-stub-tx",
  5560. .platform_name = "msm-pcm-afe",
  5561. .dpcm_capture = 1,
  5562. .ignore_suspend = 1,
  5563. },
  5564. {
  5565. .name = MSM_DAILINK_NAME(Compress1),
  5566. .stream_name = "Compress1",
  5567. .cpu_dai_name = "MultiMedia4",
  5568. .platform_name = "msm-compress-dsp",
  5569. .dynamic = 1,
  5570. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5571. .dpcm_playback = 1,
  5572. .dpcm_capture = 1,
  5573. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5574. SND_SOC_DPCM_TRIGGER_POST},
  5575. .codec_dai_name = "snd-soc-dummy-dai",
  5576. .codec_name = "snd-soc-dummy",
  5577. .ignore_suspend = 1,
  5578. .ignore_pmdown_time = 1,
  5579. /* this dainlink has playback support */
  5580. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  5581. },
  5582. {
  5583. .name = "AUXPCM Hostless",
  5584. .stream_name = "AUXPCM Hostless",
  5585. .cpu_dai_name = "AUXPCM_HOSTLESS",
  5586. .platform_name = "msm-pcm-hostless",
  5587. .dynamic = 1,
  5588. .dpcm_playback = 1,
  5589. .dpcm_capture = 1,
  5590. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5591. SND_SOC_DPCM_TRIGGER_POST},
  5592. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5593. .ignore_suspend = 1,
  5594. /* this dainlink has playback support */
  5595. .ignore_pmdown_time = 1,
  5596. .codec_dai_name = "snd-soc-dummy-dai",
  5597. .codec_name = "snd-soc-dummy",
  5598. },
  5599. {
  5600. .name = "SLIMBUS_1 Hostless",
  5601. .stream_name = "SLIMBUS_1 Hostless",
  5602. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  5603. .platform_name = "msm-pcm-hostless",
  5604. .dynamic = 1,
  5605. .dpcm_playback = 1,
  5606. .dpcm_capture = 1,
  5607. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5608. SND_SOC_DPCM_TRIGGER_POST},
  5609. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5610. .ignore_suspend = 1,
  5611. /* this dailink has playback support */
  5612. .ignore_pmdown_time = 1,
  5613. .codec_dai_name = "snd-soc-dummy-dai",
  5614. .codec_name = "snd-soc-dummy",
  5615. },
  5616. {
  5617. .name = "SLIMBUS_3 Hostless",
  5618. .stream_name = "SLIMBUS_3 Hostless",
  5619. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  5620. .platform_name = "msm-pcm-hostless",
  5621. .dynamic = 1,
  5622. .dpcm_playback = 1,
  5623. .dpcm_capture = 1,
  5624. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5625. SND_SOC_DPCM_TRIGGER_POST},
  5626. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5627. .ignore_suspend = 1,
  5628. /* this dailink has playback support */
  5629. .ignore_pmdown_time = 1,
  5630. .codec_dai_name = "snd-soc-dummy-dai",
  5631. .codec_name = "snd-soc-dummy",
  5632. },
  5633. {
  5634. .name = "SLIMBUS_4 Hostless",
  5635. .stream_name = "SLIMBUS_4 Hostless",
  5636. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  5637. .platform_name = "msm-pcm-hostless",
  5638. .dynamic = 1,
  5639. .dpcm_playback = 1,
  5640. .dpcm_capture = 1,
  5641. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5642. SND_SOC_DPCM_TRIGGER_POST},
  5643. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5644. .ignore_suspend = 1,
  5645. /* this dailink has playback support */
  5646. .ignore_pmdown_time = 1,
  5647. .codec_dai_name = "snd-soc-dummy-dai",
  5648. .codec_name = "snd-soc-dummy",
  5649. },
  5650. {
  5651. .name = MSM_DAILINK_NAME(LowLatency),
  5652. .stream_name = "MultiMedia5",
  5653. .cpu_dai_name = "MultiMedia5",
  5654. .platform_name = "msm-pcm-dsp.1",
  5655. .dynamic = 1,
  5656. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5657. .dpcm_playback = 1,
  5658. .dpcm_capture = 1,
  5659. .codec_dai_name = "snd-soc-dummy-dai",
  5660. .codec_name = "snd-soc-dummy",
  5661. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5662. SND_SOC_DPCM_TRIGGER_POST},
  5663. .ignore_suspend = 1,
  5664. /* this dainlink has playback support */
  5665. .ignore_pmdown_time = 1,
  5666. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  5667. .ops = &msm_fe_qos_ops,
  5668. },
  5669. {
  5670. .name = "Listen 1 Audio Service",
  5671. .stream_name = "Listen 1 Audio Service",
  5672. .cpu_dai_name = "LSM1",
  5673. .platform_name = "msm-lsm-client",
  5674. .dynamic = 1,
  5675. .dpcm_capture = 1,
  5676. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5677. SND_SOC_DPCM_TRIGGER_POST },
  5678. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5679. .ignore_suspend = 1,
  5680. .codec_dai_name = "snd-soc-dummy-dai",
  5681. .codec_name = "snd-soc-dummy",
  5682. .id = MSM_FRONTEND_DAI_LSM1,
  5683. },
  5684. /* Multiple Tunnel instances */
  5685. {
  5686. .name = MSM_DAILINK_NAME(Compress2),
  5687. .stream_name = "Compress2",
  5688. .cpu_dai_name = "MultiMedia7",
  5689. .platform_name = "msm-compress-dsp",
  5690. .dynamic = 1,
  5691. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5692. .dpcm_playback = 1,
  5693. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5694. SND_SOC_DPCM_TRIGGER_POST},
  5695. .codec_dai_name = "snd-soc-dummy-dai",
  5696. .codec_name = "snd-soc-dummy",
  5697. .ignore_suspend = 1,
  5698. .ignore_pmdown_time = 1,
  5699. /* this dainlink has playback support */
  5700. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  5701. },
  5702. {
  5703. .name = MSM_DAILINK_NAME(MultiMedia10),
  5704. .stream_name = "MultiMedia10",
  5705. .cpu_dai_name = "MultiMedia10",
  5706. .platform_name = "msm-pcm-dsp.1",
  5707. .dynamic = 1,
  5708. .dpcm_playback = 1,
  5709. .dpcm_capture = 1,
  5710. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5711. SND_SOC_DPCM_TRIGGER_POST},
  5712. .codec_dai_name = "snd-soc-dummy-dai",
  5713. .codec_name = "snd-soc-dummy",
  5714. .ignore_suspend = 1,
  5715. .ignore_pmdown_time = 1,
  5716. /* this dainlink has playback support */
  5717. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  5718. },
  5719. {
  5720. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  5721. .stream_name = "MM_NOIRQ",
  5722. .cpu_dai_name = "MultiMedia8",
  5723. .platform_name = "msm-pcm-dsp-noirq",
  5724. .dynamic = 1,
  5725. .dpcm_playback = 1,
  5726. .dpcm_capture = 1,
  5727. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5728. SND_SOC_DPCM_TRIGGER_POST},
  5729. .codec_dai_name = "snd-soc-dummy-dai",
  5730. .codec_name = "snd-soc-dummy",
  5731. .ignore_suspend = 1,
  5732. .ignore_pmdown_time = 1,
  5733. /* this dainlink has playback support */
  5734. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  5735. .ops = &msm_fe_qos_ops,
  5736. },
  5737. /* HDMI Hostless */
  5738. {
  5739. .name = "HDMI_RX_HOSTLESS",
  5740. .stream_name = "HDMI_RX_HOSTLESS",
  5741. .cpu_dai_name = "HDMI_HOSTLESS",
  5742. .platform_name = "msm-pcm-hostless",
  5743. .dynamic = 1,
  5744. .dpcm_playback = 1,
  5745. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5746. SND_SOC_DPCM_TRIGGER_POST},
  5747. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5748. .ignore_suspend = 1,
  5749. .ignore_pmdown_time = 1,
  5750. .codec_dai_name = "snd-soc-dummy-dai",
  5751. .codec_name = "snd-soc-dummy",
  5752. },
  5753. {
  5754. .name = "VoiceMMode2",
  5755. .stream_name = "VoiceMMode2",
  5756. .cpu_dai_name = "VoiceMMode2",
  5757. .platform_name = "msm-pcm-voice",
  5758. .dynamic = 1,
  5759. .dpcm_playback = 1,
  5760. .dpcm_capture = 1,
  5761. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5762. SND_SOC_DPCM_TRIGGER_POST},
  5763. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5764. .ignore_suspend = 1,
  5765. .ignore_pmdown_time = 1,
  5766. .codec_dai_name = "snd-soc-dummy-dai",
  5767. .codec_name = "snd-soc-dummy",
  5768. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  5769. },
  5770. /* LSM FE */
  5771. {
  5772. .name = "Listen 2 Audio Service",
  5773. .stream_name = "Listen 2 Audio Service",
  5774. .cpu_dai_name = "LSM2",
  5775. .platform_name = "msm-lsm-client",
  5776. .dynamic = 1,
  5777. .dpcm_capture = 1,
  5778. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5779. SND_SOC_DPCM_TRIGGER_POST },
  5780. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5781. .ignore_suspend = 1,
  5782. .codec_dai_name = "snd-soc-dummy-dai",
  5783. .codec_name = "snd-soc-dummy",
  5784. .id = MSM_FRONTEND_DAI_LSM2,
  5785. },
  5786. {
  5787. .name = "Listen 3 Audio Service",
  5788. .stream_name = "Listen 3 Audio Service",
  5789. .cpu_dai_name = "LSM3",
  5790. .platform_name = "msm-lsm-client",
  5791. .dynamic = 1,
  5792. .dpcm_capture = 1,
  5793. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5794. SND_SOC_DPCM_TRIGGER_POST },
  5795. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5796. .ignore_suspend = 1,
  5797. .codec_dai_name = "snd-soc-dummy-dai",
  5798. .codec_name = "snd-soc-dummy",
  5799. .id = MSM_FRONTEND_DAI_LSM3,
  5800. },
  5801. {
  5802. .name = "Listen 4 Audio Service",
  5803. .stream_name = "Listen 4 Audio Service",
  5804. .cpu_dai_name = "LSM4",
  5805. .platform_name = "msm-lsm-client",
  5806. .dynamic = 1,
  5807. .dpcm_capture = 1,
  5808. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5809. SND_SOC_DPCM_TRIGGER_POST },
  5810. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5811. .ignore_suspend = 1,
  5812. .codec_dai_name = "snd-soc-dummy-dai",
  5813. .codec_name = "snd-soc-dummy",
  5814. .id = MSM_FRONTEND_DAI_LSM4,
  5815. },
  5816. {
  5817. .name = "Listen 5 Audio Service",
  5818. .stream_name = "Listen 5 Audio Service",
  5819. .cpu_dai_name = "LSM5",
  5820. .platform_name = "msm-lsm-client",
  5821. .dynamic = 1,
  5822. .dpcm_capture = 1,
  5823. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5824. SND_SOC_DPCM_TRIGGER_POST },
  5825. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5826. .ignore_suspend = 1,
  5827. .codec_dai_name = "snd-soc-dummy-dai",
  5828. .codec_name = "snd-soc-dummy",
  5829. .id = MSM_FRONTEND_DAI_LSM5,
  5830. },
  5831. {
  5832. .name = "Listen 6 Audio Service",
  5833. .stream_name = "Listen 6 Audio Service",
  5834. .cpu_dai_name = "LSM6",
  5835. .platform_name = "msm-lsm-client",
  5836. .dynamic = 1,
  5837. .dpcm_capture = 1,
  5838. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5839. SND_SOC_DPCM_TRIGGER_POST },
  5840. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5841. .ignore_suspend = 1,
  5842. .codec_dai_name = "snd-soc-dummy-dai",
  5843. .codec_name = "snd-soc-dummy",
  5844. .id = MSM_FRONTEND_DAI_LSM6,
  5845. },
  5846. {
  5847. .name = "Listen 7 Audio Service",
  5848. .stream_name = "Listen 7 Audio Service",
  5849. .cpu_dai_name = "LSM7",
  5850. .platform_name = "msm-lsm-client",
  5851. .dynamic = 1,
  5852. .dpcm_capture = 1,
  5853. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5854. SND_SOC_DPCM_TRIGGER_POST },
  5855. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5856. .ignore_suspend = 1,
  5857. .codec_dai_name = "snd-soc-dummy-dai",
  5858. .codec_name = "snd-soc-dummy",
  5859. .id = MSM_FRONTEND_DAI_LSM7,
  5860. },
  5861. {
  5862. .name = "Listen 8 Audio Service",
  5863. .stream_name = "Listen 8 Audio Service",
  5864. .cpu_dai_name = "LSM8",
  5865. .platform_name = "msm-lsm-client",
  5866. .dynamic = 1,
  5867. .dpcm_capture = 1,
  5868. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  5869. SND_SOC_DPCM_TRIGGER_POST },
  5870. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5871. .ignore_suspend = 1,
  5872. .codec_dai_name = "snd-soc-dummy-dai",
  5873. .codec_name = "snd-soc-dummy",
  5874. .id = MSM_FRONTEND_DAI_LSM8,
  5875. },
  5876. {
  5877. .name = MSM_DAILINK_NAME(Media9),
  5878. .stream_name = "MultiMedia9",
  5879. .cpu_dai_name = "MultiMedia9",
  5880. .platform_name = "msm-pcm-dsp.0",
  5881. .dynamic = 1,
  5882. .dpcm_playback = 1,
  5883. .dpcm_capture = 1,
  5884. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5885. SND_SOC_DPCM_TRIGGER_POST},
  5886. .codec_dai_name = "snd-soc-dummy-dai",
  5887. .codec_name = "snd-soc-dummy",
  5888. .ignore_suspend = 1,
  5889. /* this dainlink has playback support */
  5890. .ignore_pmdown_time = 1,
  5891. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5892. },
  5893. {
  5894. .name = MSM_DAILINK_NAME(Compress4),
  5895. .stream_name = "Compress4",
  5896. .cpu_dai_name = "MultiMedia11",
  5897. .platform_name = "msm-compress-dsp",
  5898. .dynamic = 1,
  5899. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5900. .dpcm_playback = 1,
  5901. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5902. SND_SOC_DPCM_TRIGGER_POST},
  5903. .codec_dai_name = "snd-soc-dummy-dai",
  5904. .codec_name = "snd-soc-dummy",
  5905. .ignore_suspend = 1,
  5906. .ignore_pmdown_time = 1,
  5907. /* this dainlink has playback support */
  5908. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5909. },
  5910. {
  5911. .name = MSM_DAILINK_NAME(Compress5),
  5912. .stream_name = "Compress5",
  5913. .cpu_dai_name = "MultiMedia12",
  5914. .platform_name = "msm-compress-dsp",
  5915. .dynamic = 1,
  5916. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5917. .dpcm_playback = 1,
  5918. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5919. SND_SOC_DPCM_TRIGGER_POST},
  5920. .codec_dai_name = "snd-soc-dummy-dai",
  5921. .codec_name = "snd-soc-dummy",
  5922. .ignore_suspend = 1,
  5923. .ignore_pmdown_time = 1,
  5924. /* this dainlink has playback support */
  5925. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5926. },
  5927. {
  5928. .name = MSM_DAILINK_NAME(Compress6),
  5929. .stream_name = "Compress6",
  5930. .cpu_dai_name = "MultiMedia13",
  5931. .platform_name = "msm-compress-dsp",
  5932. .dynamic = 1,
  5933. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5934. .dpcm_playback = 1,
  5935. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5936. SND_SOC_DPCM_TRIGGER_POST},
  5937. .codec_dai_name = "snd-soc-dummy-dai",
  5938. .codec_name = "snd-soc-dummy",
  5939. .ignore_suspend = 1,
  5940. .ignore_pmdown_time = 1,
  5941. /* this dainlink has playback support */
  5942. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5943. },
  5944. {
  5945. .name = MSM_DAILINK_NAME(Compress7),
  5946. .stream_name = "Compress7",
  5947. .cpu_dai_name = "MultiMedia14",
  5948. .platform_name = "msm-compress-dsp",
  5949. .dynamic = 1,
  5950. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5951. .dpcm_playback = 1,
  5952. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5953. SND_SOC_DPCM_TRIGGER_POST},
  5954. .codec_dai_name = "snd-soc-dummy-dai",
  5955. .codec_name = "snd-soc-dummy",
  5956. .ignore_suspend = 1,
  5957. .ignore_pmdown_time = 1,
  5958. /* this dainlink has playback support */
  5959. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5960. },
  5961. {
  5962. .name = MSM_DAILINK_NAME(Compress8),
  5963. .stream_name = "Compress8",
  5964. .cpu_dai_name = "MultiMedia15",
  5965. .platform_name = "msm-compress-dsp",
  5966. .dynamic = 1,
  5967. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  5968. .dpcm_playback = 1,
  5969. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5970. SND_SOC_DPCM_TRIGGER_POST},
  5971. .codec_dai_name = "snd-soc-dummy-dai",
  5972. .codec_name = "snd-soc-dummy",
  5973. .ignore_suspend = 1,
  5974. .ignore_pmdown_time = 1,
  5975. /* this dainlink has playback support */
  5976. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5977. },
  5978. {
  5979. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5980. .stream_name = "MM_NOIRQ_2",
  5981. .cpu_dai_name = "MultiMedia16",
  5982. .platform_name = "msm-pcm-dsp-noirq",
  5983. .dynamic = 1,
  5984. .dpcm_playback = 1,
  5985. .dpcm_capture = 1,
  5986. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5987. SND_SOC_DPCM_TRIGGER_POST},
  5988. .codec_dai_name = "snd-soc-dummy-dai",
  5989. .codec_name = "snd-soc-dummy",
  5990. .ignore_suspend = 1,
  5991. .ignore_pmdown_time = 1,
  5992. /* this dainlink has playback support */
  5993. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5994. },
  5995. {
  5996. .name = "SLIMBUS_8 Hostless",
  5997. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5998. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5999. .platform_name = "msm-pcm-hostless",
  6000. .dynamic = 1,
  6001. .dpcm_capture = 1,
  6002. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6003. SND_SOC_DPCM_TRIGGER_POST},
  6004. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6005. .ignore_suspend = 1,
  6006. .codec_dai_name = "snd-soc-dummy-dai",
  6007. .codec_name = "snd-soc-dummy",
  6008. },
  6009. /* Hostless PCM purpose */
  6010. {
  6011. .name = "CDC_DMA Hostless",
  6012. .stream_name = "CDC_DMA Hostless",
  6013. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  6014. .platform_name = "msm-pcm-hostless",
  6015. .dynamic = 1,
  6016. .dpcm_playback = 1,
  6017. .dpcm_capture = 1,
  6018. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6019. SND_SOC_DPCM_TRIGGER_POST},
  6020. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6021. .ignore_suspend = 1,
  6022. /* this dailink has playback support */
  6023. .ignore_pmdown_time = 1,
  6024. .codec_dai_name = "snd-soc-dummy-dai",
  6025. .codec_name = "snd-soc-dummy",
  6026. },
  6027. };
  6028. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  6029. {
  6030. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  6031. .stream_name = "WSA CDC DMA0 Capture",
  6032. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  6033. .platform_name = "msm-pcm-hostless",
  6034. .codec_name = "bolero_codec",
  6035. .codec_dai_name = "wsa_macro_vifeedback",
  6036. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  6037. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6038. .ignore_suspend = 1,
  6039. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6040. .ops = &msm_cdc_dma_be_ops,
  6041. },
  6042. };
  6043. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  6044. {
  6045. .name = MSM_DAILINK_NAME(ASM Loopback),
  6046. .stream_name = "MultiMedia6",
  6047. .cpu_dai_name = "MultiMedia6",
  6048. .platform_name = "msm-pcm-loopback",
  6049. .dynamic = 1,
  6050. .dpcm_playback = 1,
  6051. .dpcm_capture = 1,
  6052. .codec_dai_name = "snd-soc-dummy-dai",
  6053. .codec_name = "snd-soc-dummy",
  6054. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6055. SND_SOC_DPCM_TRIGGER_POST},
  6056. .ignore_suspend = 1,
  6057. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6058. .ignore_pmdown_time = 1,
  6059. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  6060. },
  6061. {
  6062. .name = "USB Audio Hostless",
  6063. .stream_name = "USB Audio Hostless",
  6064. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  6065. .platform_name = "msm-pcm-hostless",
  6066. .dynamic = 1,
  6067. .dpcm_playback = 1,
  6068. .dpcm_capture = 1,
  6069. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6070. SND_SOC_DPCM_TRIGGER_POST},
  6071. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6072. .ignore_suspend = 1,
  6073. .ignore_pmdown_time = 1,
  6074. .codec_dai_name = "snd-soc-dummy-dai",
  6075. .codec_name = "snd-soc-dummy",
  6076. },
  6077. {
  6078. .name = "SLIMBUS_7 Hostless",
  6079. .stream_name = "SLIMBUS_7 Hostless",
  6080. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  6081. .platform_name = "msm-pcm-hostless",
  6082. .dynamic = 1,
  6083. .dpcm_capture = 1,
  6084. .dpcm_playback = 1,
  6085. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6086. SND_SOC_DPCM_TRIGGER_POST},
  6087. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6088. .ignore_suspend = 1,
  6089. .ignore_pmdown_time = 1,
  6090. .codec_dai_name = "snd-soc-dummy-dai",
  6091. .codec_name = "snd-soc-dummy",
  6092. },
  6093. {
  6094. .name = MSM_DAILINK_NAME(Compr Capture2),
  6095. .stream_name = "Compr Capture2",
  6096. .cpu_dai_name = "MultiMedia18",
  6097. .platform_name = "msm-compress-dsp",
  6098. .dynamic = 1,
  6099. .dpcm_capture = 1,
  6100. .codec_dai_name = "snd-soc-dummy-dai",
  6101. .codec_name = "snd-soc-dummy",
  6102. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6103. SND_SOC_DPCM_TRIGGER_POST},
  6104. .ignore_pmdown_time = 1,
  6105. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  6106. },
  6107. {
  6108. .name = MSM_DAILINK_NAME(Transcode Loopback Playback),
  6109. .stream_name = "Transcode Loopback Playback",
  6110. .cpu_dai_name = "MultiMedia26",
  6111. .platform_name = "msm-transcode-loopback",
  6112. .dynamic = 1,
  6113. .dpcm_playback = 1,
  6114. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6115. SND_SOC_DPCM_TRIGGER_POST},
  6116. .codec_dai_name = "snd-soc-dummy-dai",
  6117. .codec_name = "snd-soc-dummy",
  6118. .ignore_suspend = 1,
  6119. .ignore_pmdown_time = 1,
  6120. /* this dailink has playback support */
  6121. .id = MSM_FRONTEND_DAI_MULTIMEDIA26,
  6122. },
  6123. {
  6124. .name = MSM_DAILINK_NAME(Transcode Loopback Capture),
  6125. .stream_name = "Transcode Loopback Capture",
  6126. .cpu_dai_name = "MultiMedia27",
  6127. .platform_name = "msm-transcode-loopback",
  6128. .dynamic = 1,
  6129. .dpcm_capture = 1,
  6130. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6131. SND_SOC_DPCM_TRIGGER_POST},
  6132. .codec_dai_name = "snd-soc-dummy-dai",
  6133. .codec_name = "snd-soc-dummy",
  6134. .ignore_suspend = 1,
  6135. .ignore_pmdown_time = 1,
  6136. .id = MSM_FRONTEND_DAI_MULTIMEDIA27,
  6137. },
  6138. {
  6139. .name = MSM_DAILINK_NAME(Compr Capture3),
  6140. .stream_name = "Compr Capture3",
  6141. .cpu_dai_name = "MultiMedia19",
  6142. .platform_name = "msm-compress-dsp",
  6143. .dynamic = 1,
  6144. .dpcm_capture = 1,
  6145. .codec_dai_name = "snd-soc-dummy-dai",
  6146. .codec_name = "snd-soc-dummy",
  6147. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6148. SND_SOC_DPCM_TRIGGER_POST},
  6149. .ignore_pmdown_time = 1,
  6150. .id = MSM_FRONTEND_DAI_MULTIMEDIA19,
  6151. },
  6152. {
  6153. .name = MSM_DAILINK_NAME(Compr Capture4),
  6154. .stream_name = "Compr Capture4",
  6155. .cpu_dai_name = "MultiMedia28",
  6156. .platform_name = "msm-compress-dsp",
  6157. .dynamic = 1,
  6158. .dpcm_capture = 1,
  6159. .codec_dai_name = "snd-soc-dummy-dai",
  6160. .codec_name = "snd-soc-dummy",
  6161. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6162. SND_SOC_DPCM_TRIGGER_POST},
  6163. .ignore_pmdown_time = 1,
  6164. .id = MSM_FRONTEND_DAI_MULTIMEDIA28,
  6165. },
  6166. {
  6167. .name = MSM_DAILINK_NAME(Compr Capture5),
  6168. .stream_name = "Compr Capture5",
  6169. .cpu_dai_name = "MultiMedia29",
  6170. .platform_name = "msm-compress-dsp",
  6171. .dynamic = 1,
  6172. .dpcm_capture = 1,
  6173. .codec_dai_name = "snd-soc-dummy-dai",
  6174. .codec_name = "snd-soc-dummy",
  6175. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6176. SND_SOC_DPCM_TRIGGER_POST},
  6177. .ignore_pmdown_time = 1,
  6178. .id = MSM_FRONTEND_DAI_MULTIMEDIA29,
  6179. },
  6180. {
  6181. .name = MSM_DAILINK_NAME(Compr Capture6),
  6182. .stream_name = "Compr Capture6",
  6183. .cpu_dai_name = "MultiMedia30",
  6184. .platform_name = "msm-compress-dsp",
  6185. .dynamic = 1,
  6186. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6187. .dpcm_capture = 1,
  6188. .codec_dai_name = "snd-soc-dummy-dai",
  6189. .codec_name = "snd-soc-dummy",
  6190. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6191. SND_SOC_DPCM_TRIGGER_POST},
  6192. .ignore_pmdown_time = 1,
  6193. .id = MSM_FRONTEND_DAI_MULTIMEDIA30,
  6194. },
  6195. };
  6196. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  6197. /* Backend AFE DAI Links */
  6198. {
  6199. .name = LPASS_BE_AFE_PCM_RX,
  6200. .stream_name = "AFE Playback",
  6201. .cpu_dai_name = "msm-dai-q6-dev.224",
  6202. .platform_name = "msm-pcm-routing",
  6203. .codec_name = "msm-stub-codec.1",
  6204. .codec_dai_name = "msm-stub-rx",
  6205. .no_pcm = 1,
  6206. .dpcm_playback = 1,
  6207. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  6208. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6209. /* this dainlink has playback support */
  6210. .ignore_pmdown_time = 1,
  6211. .ignore_suspend = 1,
  6212. },
  6213. {
  6214. .name = LPASS_BE_AFE_PCM_TX,
  6215. .stream_name = "AFE Capture",
  6216. .cpu_dai_name = "msm-dai-q6-dev.225",
  6217. .platform_name = "msm-pcm-routing",
  6218. .codec_name = "msm-stub-codec.1",
  6219. .codec_dai_name = "msm-stub-tx",
  6220. .no_pcm = 1,
  6221. .dpcm_capture = 1,
  6222. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  6223. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6224. .ignore_suspend = 1,
  6225. },
  6226. /* Incall Record Uplink BACK END DAI Link */
  6227. {
  6228. .name = LPASS_BE_INCALL_RECORD_TX,
  6229. .stream_name = "Voice Uplink Capture",
  6230. .cpu_dai_name = "msm-dai-q6-dev.32772",
  6231. .platform_name = "msm-pcm-routing",
  6232. .codec_name = "msm-stub-codec.1",
  6233. .codec_dai_name = "msm-stub-tx",
  6234. .no_pcm = 1,
  6235. .dpcm_capture = 1,
  6236. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  6237. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6238. .ignore_suspend = 1,
  6239. },
  6240. /* Incall Record Downlink BACK END DAI Link */
  6241. {
  6242. .name = LPASS_BE_INCALL_RECORD_RX,
  6243. .stream_name = "Voice Downlink Capture",
  6244. .cpu_dai_name = "msm-dai-q6-dev.32771",
  6245. .platform_name = "msm-pcm-routing",
  6246. .codec_name = "msm-stub-codec.1",
  6247. .codec_dai_name = "msm-stub-tx",
  6248. .no_pcm = 1,
  6249. .dpcm_capture = 1,
  6250. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  6251. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6252. .ignore_suspend = 1,
  6253. },
  6254. /* Incall Music BACK END DAI Link */
  6255. {
  6256. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  6257. .stream_name = "Voice Farend Playback",
  6258. .cpu_dai_name = "msm-dai-q6-dev.32773",
  6259. .platform_name = "msm-pcm-routing",
  6260. .codec_name = "msm-stub-codec.1",
  6261. .codec_dai_name = "msm-stub-rx",
  6262. .no_pcm = 1,
  6263. .dpcm_playback = 1,
  6264. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  6265. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6266. .ignore_suspend = 1,
  6267. .ignore_pmdown_time = 1,
  6268. },
  6269. /* Incall Music 2 BACK END DAI Link */
  6270. {
  6271. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  6272. .stream_name = "Voice2 Farend Playback",
  6273. .cpu_dai_name = "msm-dai-q6-dev.32770",
  6274. .platform_name = "msm-pcm-routing",
  6275. .codec_name = "msm-stub-codec.1",
  6276. .codec_dai_name = "msm-stub-rx",
  6277. .no_pcm = 1,
  6278. .dpcm_playback = 1,
  6279. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  6280. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6281. .ignore_suspend = 1,
  6282. .ignore_pmdown_time = 1,
  6283. },
  6284. {
  6285. .name = LPASS_BE_USB_AUDIO_RX,
  6286. .stream_name = "USB Audio Playback",
  6287. .cpu_dai_name = "msm-dai-q6-dev.28672",
  6288. .platform_name = "msm-pcm-routing",
  6289. .codec_name = "msm-stub-codec.1",
  6290. .codec_dai_name = "msm-stub-rx",
  6291. .no_pcm = 1,
  6292. .dpcm_playback = 1,
  6293. .id = MSM_BACKEND_DAI_USB_RX,
  6294. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6295. .ignore_pmdown_time = 1,
  6296. .ignore_suspend = 1,
  6297. },
  6298. {
  6299. .name = LPASS_BE_USB_AUDIO_TX,
  6300. .stream_name = "USB Audio Capture",
  6301. .cpu_dai_name = "msm-dai-q6-dev.28673",
  6302. .platform_name = "msm-pcm-routing",
  6303. .codec_name = "msm-stub-codec.1",
  6304. .codec_dai_name = "msm-stub-tx",
  6305. .no_pcm = 1,
  6306. .dpcm_capture = 1,
  6307. .id = MSM_BACKEND_DAI_USB_TX,
  6308. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6309. .ignore_suspend = 1,
  6310. },
  6311. {
  6312. .name = LPASS_BE_PRI_TDM_RX_0,
  6313. .stream_name = "Primary TDM0 Playback",
  6314. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  6315. .platform_name = "msm-pcm-routing",
  6316. .codec_name = "msm-stub-codec.1",
  6317. .codec_dai_name = "msm-stub-rx",
  6318. .no_pcm = 1,
  6319. .dpcm_playback = 1,
  6320. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  6321. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6322. .ops = &qcs405_tdm_be_ops,
  6323. .ignore_suspend = 1,
  6324. .ignore_pmdown_time = 1,
  6325. },
  6326. {
  6327. .name = LPASS_BE_PRI_TDM_TX_0,
  6328. .stream_name = "Primary TDM0 Capture",
  6329. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  6330. .platform_name = "msm-pcm-routing",
  6331. .codec_name = "msm-stub-codec.1",
  6332. .codec_dai_name = "msm-stub-tx",
  6333. .no_pcm = 1,
  6334. .dpcm_capture = 1,
  6335. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  6336. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6337. .ops = &qcs405_tdm_be_ops,
  6338. .ignore_suspend = 1,
  6339. },
  6340. {
  6341. .name = LPASS_BE_SEC_TDM_RX_0,
  6342. .stream_name = "Secondary TDM0 Playback",
  6343. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  6344. .platform_name = "msm-pcm-routing",
  6345. .codec_name = "msm-stub-codec.1",
  6346. .codec_dai_name = "msm-stub-rx",
  6347. .no_pcm = 1,
  6348. .dpcm_playback = 1,
  6349. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  6350. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6351. .ops = &qcs405_tdm_be_ops,
  6352. .ignore_suspend = 1,
  6353. .ignore_pmdown_time = 1,
  6354. },
  6355. {
  6356. .name = LPASS_BE_SEC_TDM_TX_0,
  6357. .stream_name = "Secondary TDM0 Capture",
  6358. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  6359. .platform_name = "msm-pcm-routing",
  6360. .codec_name = "msm-stub-codec.1",
  6361. .codec_dai_name = "msm-stub-tx",
  6362. .no_pcm = 1,
  6363. .dpcm_capture = 1,
  6364. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  6365. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6366. .ops = &qcs405_tdm_be_ops,
  6367. .ignore_suspend = 1,
  6368. },
  6369. {
  6370. .name = LPASS_BE_TERT_TDM_RX_0,
  6371. .stream_name = "Tertiary TDM0 Playback",
  6372. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  6373. .platform_name = "msm-pcm-routing",
  6374. .codec_name = "msm-stub-codec.1",
  6375. .codec_dai_name = "msm-stub-rx",
  6376. .no_pcm = 1,
  6377. .dpcm_playback = 1,
  6378. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  6379. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6380. .ops = &qcs405_tdm_be_ops,
  6381. .ignore_suspend = 1,
  6382. .ignore_pmdown_time = 1,
  6383. },
  6384. {
  6385. .name = LPASS_BE_TERT_TDM_TX_0,
  6386. .stream_name = "Tertiary TDM0 Capture",
  6387. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  6388. .platform_name = "msm-pcm-routing",
  6389. .codec_name = "msm-stub-codec.1",
  6390. .codec_dai_name = "msm-stub-tx",
  6391. .no_pcm = 1,
  6392. .dpcm_capture = 1,
  6393. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  6394. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6395. .ops = &qcs405_tdm_be_ops,
  6396. .ignore_suspend = 1,
  6397. },
  6398. {
  6399. .name = LPASS_BE_QUAT_TDM_RX_0,
  6400. .stream_name = "Quaternary TDM0 Playback",
  6401. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  6402. .platform_name = "msm-pcm-routing",
  6403. .codec_name = "msm-stub-codec.1",
  6404. .codec_dai_name = "msm-stub-rx",
  6405. .no_pcm = 1,
  6406. .dpcm_playback = 1,
  6407. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  6408. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6409. .ops = &qcs405_tdm_be_ops,
  6410. .ignore_suspend = 1,
  6411. .ignore_pmdown_time = 1,
  6412. },
  6413. {
  6414. .name = LPASS_BE_QUAT_TDM_TX_0,
  6415. .stream_name = "Quaternary TDM0 Capture",
  6416. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  6417. .platform_name = "msm-pcm-routing",
  6418. .codec_name = "msm-stub-codec.1",
  6419. .codec_dai_name = "msm-stub-tx",
  6420. .no_pcm = 1,
  6421. .dpcm_capture = 1,
  6422. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  6423. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6424. .ops = &qcs405_tdm_be_ops,
  6425. .ignore_suspend = 1,
  6426. },
  6427. {
  6428. .name = LPASS_BE_QUIN_TDM_RX_0,
  6429. .stream_name = "Quinary TDM0 Playback",
  6430. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  6431. .platform_name = "msm-pcm-routing",
  6432. .codec_name = "msm-stub-codec.1",
  6433. .codec_dai_name = "msm-stub-rx",
  6434. .no_pcm = 1,
  6435. .dpcm_playback = 1,
  6436. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  6437. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  6438. .ops = &qcs405_tdm_be_ops,
  6439. .ignore_suspend = 1,
  6440. .ignore_pmdown_time = 1,
  6441. },
  6442. {
  6443. .name = LPASS_BE_QUIN_TDM_TX_0,
  6444. .stream_name = "Quinary TDM0 Capture",
  6445. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  6446. .platform_name = "msm-pcm-routing",
  6447. .codec_name = "msm-stub-codec.1",
  6448. .codec_dai_name = "msm-stub-tx",
  6449. .no_pcm = 1,
  6450. .dpcm_capture = 1,
  6451. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  6452. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6453. .ops = &qcs405_tdm_be_ops,
  6454. .ignore_suspend = 1,
  6455. },
  6456. };
  6457. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  6458. {
  6459. .name = LPASS_BE_SLIMBUS_0_RX,
  6460. .stream_name = "Slimbus Playback",
  6461. .cpu_dai_name = "msm-dai-q6-dev.16384",
  6462. .platform_name = "msm-pcm-routing",
  6463. .codec_name = "tasha_codec",
  6464. .codec_dai_name = "tasha_mix_rx1",
  6465. .no_pcm = 1,
  6466. .dpcm_playback = 1,
  6467. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  6468. .init = &msm_audrx_init,
  6469. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6470. /* this dainlink has playback support */
  6471. .ignore_pmdown_time = 1,
  6472. .ignore_suspend = 1,
  6473. .ops = &msm_be_ops,
  6474. },
  6475. {
  6476. .name = LPASS_BE_SLIMBUS_0_TX,
  6477. .stream_name = "Slimbus Capture",
  6478. .cpu_dai_name = "msm-dai-q6-dev.16385",
  6479. .platform_name = "msm-pcm-routing",
  6480. .codec_name = "tasha_codec",
  6481. .codec_dai_name = "tasha_tx1",
  6482. .no_pcm = 1,
  6483. .dpcm_capture = 1,
  6484. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  6485. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6486. .ignore_suspend = 1,
  6487. .ops = &msm_be_ops,
  6488. },
  6489. {
  6490. .name = LPASS_BE_SLIMBUS_1_RX,
  6491. .stream_name = "Slimbus1 Playback",
  6492. .cpu_dai_name = "msm-dai-q6-dev.16386",
  6493. .platform_name = "msm-pcm-routing",
  6494. .codec_name = "tasha_codec",
  6495. .codec_dai_name = "tasha_mix_rx1",
  6496. .no_pcm = 1,
  6497. .dpcm_playback = 1,
  6498. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  6499. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6500. .ops = &msm_be_ops,
  6501. /* dai link has playback support */
  6502. .ignore_pmdown_time = 1,
  6503. .ignore_suspend = 1,
  6504. },
  6505. {
  6506. .name = LPASS_BE_SLIMBUS_1_TX,
  6507. .stream_name = "Slimbus1 Capture",
  6508. .cpu_dai_name = "msm-dai-q6-dev.16387",
  6509. .platform_name = "msm-pcm-routing",
  6510. .codec_name = "tasha_codec",
  6511. .codec_dai_name = "tasha_tx3",
  6512. .no_pcm = 1,
  6513. .dpcm_capture = 1,
  6514. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  6515. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6516. .ops = &msm_be_ops,
  6517. .ignore_suspend = 1,
  6518. },
  6519. {
  6520. .name = LPASS_BE_SLIMBUS_2_RX,
  6521. .stream_name = "Slimbus2 Playback",
  6522. .cpu_dai_name = "msm-dai-q6-dev.16388",
  6523. .platform_name = "msm-pcm-routing",
  6524. .codec_name = "tasha_codec",
  6525. .codec_dai_name = "tasha_rx2",
  6526. .no_pcm = 1,
  6527. .dpcm_playback = 1,
  6528. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  6529. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6530. .ops = &msm_be_ops,
  6531. .ignore_pmdown_time = 1,
  6532. .ignore_suspend = 1,
  6533. },
  6534. {
  6535. .name = LPASS_BE_SLIMBUS_3_RX,
  6536. .stream_name = "Slimbus3 Playback",
  6537. .cpu_dai_name = "msm-dai-q6-dev.16390",
  6538. .platform_name = "msm-pcm-routing",
  6539. .codec_name = "tasha_codec",
  6540. .codec_dai_name = "tasha_mix_rx1",
  6541. .no_pcm = 1,
  6542. .dpcm_playback = 1,
  6543. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  6544. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6545. .ops = &msm_be_ops,
  6546. /* dai link has playback support */
  6547. .ignore_pmdown_time = 1,
  6548. .ignore_suspend = 1,
  6549. },
  6550. {
  6551. .name = LPASS_BE_SLIMBUS_3_TX,
  6552. .stream_name = "Slimbus3 Capture",
  6553. .cpu_dai_name = "msm-dai-q6-dev.16391",
  6554. .platform_name = "msm-pcm-routing",
  6555. .codec_name = "tasha_codec",
  6556. .codec_dai_name = "tasha_tx1",
  6557. .no_pcm = 1,
  6558. .dpcm_capture = 1,
  6559. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  6560. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6561. .ops = &msm_be_ops,
  6562. .ignore_suspend = 1,
  6563. },
  6564. {
  6565. .name = LPASS_BE_SLIMBUS_4_RX,
  6566. .stream_name = "Slimbus4 Playback",
  6567. .cpu_dai_name = "msm-dai-q6-dev.16392",
  6568. .platform_name = "msm-pcm-routing",
  6569. .codec_name = "tasha_codec",
  6570. .codec_dai_name = "tasha_mix_rx1",
  6571. .no_pcm = 1,
  6572. .dpcm_playback = 1,
  6573. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  6574. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6575. .ops = &msm_be_ops,
  6576. /* dai link has playback support */
  6577. .ignore_pmdown_time = 1,
  6578. .ignore_suspend = 1,
  6579. },
  6580. {
  6581. .name = LPASS_BE_SLIMBUS_5_RX,
  6582. .stream_name = "Slimbus5 Playback",
  6583. .cpu_dai_name = "msm-dai-q6-dev.16394",
  6584. .platform_name = "msm-pcm-routing",
  6585. .codec_name = "tasha_codec",
  6586. .codec_dai_name = "tasha_rx3",
  6587. .no_pcm = 1,
  6588. .dpcm_playback = 1,
  6589. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  6590. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6591. .ops = &msm_be_ops,
  6592. /* dai link has playback support */
  6593. .ignore_pmdown_time = 1,
  6594. .ignore_suspend = 1,
  6595. },
  6596. {
  6597. .name = LPASS_BE_SLIMBUS_6_RX,
  6598. .stream_name = "Slimbus6 Playback",
  6599. .cpu_dai_name = "msm-dai-q6-dev.16396",
  6600. .platform_name = "msm-pcm-routing",
  6601. .codec_name = "tasha_codec",
  6602. .codec_dai_name = "tasha_rx4",
  6603. .no_pcm = 1,
  6604. .dpcm_playback = 1,
  6605. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  6606. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6607. .ops = &msm_be_ops,
  6608. /* dai link has playback support */
  6609. .ignore_pmdown_time = 1,
  6610. .ignore_suspend = 1,
  6611. },
  6612. /* Slimbus VI Recording */
  6613. {
  6614. .name = LPASS_BE_SLIMBUS_TX_VI,
  6615. .stream_name = "Slimbus4 Capture",
  6616. .cpu_dai_name = "msm-dai-q6-dev.16393",
  6617. .platform_name = "msm-pcm-routing",
  6618. .codec_name = "tasha_codec",
  6619. .codec_dai_name = "tasha_vifeedback",
  6620. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  6621. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6622. .ops = &msm_be_ops,
  6623. .ignore_suspend = 1,
  6624. .no_pcm = 1,
  6625. .dpcm_capture = 1,
  6626. .ignore_pmdown_time = 1,
  6627. },
  6628. };
  6629. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  6630. {
  6631. .name = LPASS_BE_SLIMBUS_7_RX,
  6632. .stream_name = "Slimbus7 Playback",
  6633. .cpu_dai_name = "msm-dai-q6-dev.16398",
  6634. .platform_name = "msm-pcm-routing",
  6635. .codec_name = "btfmslim_slave",
  6636. /* BT codec driver determines capabilities based on
  6637. * dai name, bt codecdai name should always contains
  6638. * supported usecase information
  6639. */
  6640. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  6641. .no_pcm = 1,
  6642. .dpcm_playback = 1,
  6643. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  6644. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6645. .ops = &msm_wcn_ops,
  6646. /* dai link has playback support */
  6647. .ignore_pmdown_time = 1,
  6648. .ignore_suspend = 1,
  6649. },
  6650. {
  6651. .name = LPASS_BE_SLIMBUS_7_TX,
  6652. .stream_name = "Slimbus7 Capture",
  6653. .cpu_dai_name = "msm-dai-q6-dev.16399",
  6654. .platform_name = "msm-pcm-routing",
  6655. .codec_name = "btfmslim_slave",
  6656. .codec_dai_name = "btfm_bt_sco_slim_tx",
  6657. .no_pcm = 1,
  6658. .dpcm_capture = 1,
  6659. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  6660. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6661. .ops = &msm_wcn_ops,
  6662. .ignore_suspend = 1,
  6663. },
  6664. {
  6665. .name = LPASS_BE_SLIMBUS_8_TX,
  6666. .stream_name = "Slimbus8 Capture",
  6667. .cpu_dai_name = "msm-dai-q6-dev.16401",
  6668. .platform_name = "msm-pcm-routing",
  6669. .codec_name = "btfmslim_slave",
  6670. .codec_dai_name = "btfm_fm_slim_tx",
  6671. .no_pcm = 1,
  6672. .dpcm_capture = 1,
  6673. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  6674. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6675. .init = &msm_wcn_init,
  6676. .ops = &msm_wcn_ops,
  6677. .ignore_suspend = 1,
  6678. },
  6679. {
  6680. .name = LPASS_BE_SLIMBUS_9_TX,
  6681. .stream_name = "Slimbus9 Capture",
  6682. .cpu_dai_name = "msm-dai-q6-dev.16403",
  6683. .platform_name = "msm-pcm-routing",
  6684. .codec_name = "btfmslim_slave",
  6685. .codec_dai_name = "btfm_bt_split_a2dp_slim_tx",
  6686. .no_pcm = 1,
  6687. .dpcm_capture = 1,
  6688. .id = MSM_BACKEND_DAI_SLIMBUS_9_TX,
  6689. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6690. .ops = &msm_wcn_ops,
  6691. .ignore_suspend = 1,
  6692. },
  6693. };
  6694. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  6695. {
  6696. .name = LPASS_BE_PRI_MI2S_RX,
  6697. .stream_name = "Primary MI2S Playback",
  6698. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6699. .platform_name = "msm-pcm-routing",
  6700. .codec_name = "msm-stub-codec.1",
  6701. .codec_dai_name = "msm-stub-rx",
  6702. .no_pcm = 1,
  6703. .dpcm_playback = 1,
  6704. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  6705. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6706. .ops = &msm_mi2s_be_ops,
  6707. .ignore_suspend = 1,
  6708. .ignore_pmdown_time = 1,
  6709. },
  6710. {
  6711. .name = LPASS_BE_PRI_MI2S_TX,
  6712. .stream_name = "Primary MI2S Capture",
  6713. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  6714. .platform_name = "msm-pcm-routing",
  6715. .codec_name = "msm-stub-codec.1",
  6716. .codec_dai_name = "msm-stub-tx",
  6717. .no_pcm = 1,
  6718. .dpcm_capture = 1,
  6719. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  6720. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6721. .ops = &msm_mi2s_be_ops,
  6722. .ignore_suspend = 1,
  6723. },
  6724. {
  6725. .name = LPASS_BE_SEC_MI2S_RX,
  6726. .stream_name = "Secondary MI2S Playback",
  6727. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6728. .platform_name = "msm-pcm-routing",
  6729. .codec_name = "msm-stub-codec.1",
  6730. .codec_dai_name = "msm-stub-rx",
  6731. .no_pcm = 1,
  6732. .dpcm_playback = 1,
  6733. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  6734. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6735. .ops = &msm_mi2s_be_ops,
  6736. .ignore_suspend = 1,
  6737. .ignore_pmdown_time = 1,
  6738. },
  6739. {
  6740. .name = LPASS_BE_SEC_MI2S_TX,
  6741. .stream_name = "Secondary MI2S Capture",
  6742. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  6743. .platform_name = "msm-pcm-routing",
  6744. .codec_name = "msm-stub-codec.1",
  6745. .codec_dai_name = "msm-stub-tx",
  6746. .no_pcm = 1,
  6747. .dpcm_capture = 1,
  6748. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  6749. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6750. .ops = &msm_mi2s_be_ops,
  6751. .ignore_suspend = 1,
  6752. },
  6753. {
  6754. .name = LPASS_BE_TERT_MI2S_RX,
  6755. .stream_name = "Tertiary MI2S Playback",
  6756. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6757. .platform_name = "msm-pcm-routing",
  6758. .codec_name = "msm-stub-codec.1",
  6759. .codec_dai_name = "msm-stub-rx",
  6760. .no_pcm = 1,
  6761. .dpcm_playback = 1,
  6762. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  6763. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6764. .ops = &msm_mi2s_be_ops,
  6765. .ignore_suspend = 1,
  6766. .ignore_pmdown_time = 1,
  6767. },
  6768. {
  6769. .name = LPASS_BE_TERT_MI2S_TX,
  6770. .stream_name = "Tertiary MI2S Capture",
  6771. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  6772. .platform_name = "msm-pcm-routing",
  6773. .codec_name = "msm-stub-codec.1",
  6774. .codec_dai_name = "msm-stub-tx",
  6775. .no_pcm = 1,
  6776. .dpcm_capture = 1,
  6777. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  6778. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6779. .ops = &msm_mi2s_be_ops,
  6780. .ignore_suspend = 1,
  6781. },
  6782. {
  6783. .name = LPASS_BE_QUAT_MI2S_RX,
  6784. .stream_name = "Quaternary MI2S Playback",
  6785. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6786. .platform_name = "msm-pcm-routing",
  6787. .codec_name = "msm-stub-codec.1",
  6788. .codec_dai_name = "msm-stub-rx",
  6789. .no_pcm = 1,
  6790. .dpcm_playback = 1,
  6791. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  6792. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6793. .ops = &msm_mi2s_be_ops,
  6794. .ignore_suspend = 1,
  6795. .ignore_pmdown_time = 1,
  6796. },
  6797. {
  6798. .name = LPASS_BE_QUAT_MI2S_TX,
  6799. .stream_name = "Quaternary MI2S Capture",
  6800. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  6801. .platform_name = "msm-pcm-routing",
  6802. .codec_name = "msm-stub-codec.1",
  6803. .codec_dai_name = "msm-stub-tx",
  6804. .no_pcm = 1,
  6805. .dpcm_capture = 1,
  6806. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  6807. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6808. .ops = &msm_mi2s_be_ops,
  6809. .ignore_suspend = 1,
  6810. },
  6811. {
  6812. .name = LPASS_BE_QUIN_MI2S_RX,
  6813. .stream_name = "Quinary MI2S Playback",
  6814. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6815. .platform_name = "msm-pcm-routing",
  6816. .codec_name = "msm-stub-codec.1",
  6817. .codec_dai_name = "msm-stub-rx",
  6818. .no_pcm = 1,
  6819. .dpcm_playback = 1,
  6820. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  6821. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6822. .ops = &msm_mi2s_be_ops,
  6823. .ignore_suspend = 1,
  6824. .ignore_pmdown_time = 1,
  6825. },
  6826. {
  6827. .name = LPASS_BE_QUIN_MI2S_TX,
  6828. .stream_name = "Quinary MI2S Capture",
  6829. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  6830. .platform_name = "msm-pcm-routing",
  6831. .codec_name = "msm-stub-codec.1",
  6832. .codec_dai_name = "msm-stub-tx",
  6833. .no_pcm = 1,
  6834. .dpcm_capture = 1,
  6835. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  6836. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6837. .ops = &msm_mi2s_be_ops,
  6838. .ignore_suspend = 1,
  6839. },
  6840. };
  6841. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  6842. /* Primary AUX PCM Backend DAI Links */
  6843. {
  6844. .name = LPASS_BE_AUXPCM_RX,
  6845. .stream_name = "AUX PCM Playback",
  6846. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6847. .platform_name = "msm-pcm-routing",
  6848. .codec_name = "msm-stub-codec.1",
  6849. .codec_dai_name = "msm-stub-rx",
  6850. .no_pcm = 1,
  6851. .dpcm_playback = 1,
  6852. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6853. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6854. .ops = &msm_auxpcm_be_ops,
  6855. .ignore_pmdown_time = 1,
  6856. .ignore_suspend = 1,
  6857. },
  6858. {
  6859. .name = LPASS_BE_AUXPCM_TX,
  6860. .stream_name = "AUX PCM Capture",
  6861. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6862. .platform_name = "msm-pcm-routing",
  6863. .codec_name = "msm-stub-codec.1",
  6864. .codec_dai_name = "msm-stub-tx",
  6865. .no_pcm = 1,
  6866. .dpcm_capture = 1,
  6867. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6868. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6869. .ops = &msm_auxpcm_be_ops,
  6870. .ignore_suspend = 1,
  6871. },
  6872. /* Secondary AUX PCM Backend DAI Links */
  6873. {
  6874. .name = LPASS_BE_SEC_AUXPCM_RX,
  6875. .stream_name = "Sec AUX PCM Playback",
  6876. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6877. .platform_name = "msm-pcm-routing",
  6878. .codec_name = "msm-stub-codec.1",
  6879. .codec_dai_name = "msm-stub-rx",
  6880. .no_pcm = 1,
  6881. .dpcm_playback = 1,
  6882. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  6883. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6884. .ops = &msm_auxpcm_be_ops,
  6885. .ignore_pmdown_time = 1,
  6886. .ignore_suspend = 1,
  6887. },
  6888. {
  6889. .name = LPASS_BE_SEC_AUXPCM_TX,
  6890. .stream_name = "Sec AUX PCM Capture",
  6891. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  6892. .platform_name = "msm-pcm-routing",
  6893. .codec_name = "msm-stub-codec.1",
  6894. .codec_dai_name = "msm-stub-tx",
  6895. .no_pcm = 1,
  6896. .dpcm_capture = 1,
  6897. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  6898. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6899. .ops = &msm_auxpcm_be_ops,
  6900. .ignore_suspend = 1,
  6901. },
  6902. /* Tertiary AUX PCM Backend DAI Links */
  6903. {
  6904. .name = LPASS_BE_TERT_AUXPCM_RX,
  6905. .stream_name = "Tert AUX PCM Playback",
  6906. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6907. .platform_name = "msm-pcm-routing",
  6908. .codec_name = "msm-stub-codec.1",
  6909. .codec_dai_name = "msm-stub-rx",
  6910. .no_pcm = 1,
  6911. .dpcm_playback = 1,
  6912. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  6913. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6914. .ops = &msm_auxpcm_be_ops,
  6915. .ignore_suspend = 1,
  6916. },
  6917. {
  6918. .name = LPASS_BE_TERT_AUXPCM_TX,
  6919. .stream_name = "Tert AUX PCM Capture",
  6920. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  6921. .platform_name = "msm-pcm-routing",
  6922. .codec_name = "msm-stub-codec.1",
  6923. .codec_dai_name = "msm-stub-tx",
  6924. .no_pcm = 1,
  6925. .dpcm_capture = 1,
  6926. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  6927. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6928. .ops = &msm_auxpcm_be_ops,
  6929. .ignore_suspend = 1,
  6930. },
  6931. /* Quaternary AUX PCM Backend DAI Links */
  6932. {
  6933. .name = LPASS_BE_QUAT_AUXPCM_RX,
  6934. .stream_name = "Quat AUX PCM Playback",
  6935. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6936. .platform_name = "msm-pcm-routing",
  6937. .codec_name = "msm-stub-codec.1",
  6938. .codec_dai_name = "msm-stub-rx",
  6939. .no_pcm = 1,
  6940. .dpcm_playback = 1,
  6941. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  6942. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6943. .ops = &msm_auxpcm_be_ops,
  6944. .ignore_pmdown_time = 1,
  6945. .ignore_suspend = 1,
  6946. },
  6947. {
  6948. .name = LPASS_BE_QUAT_AUXPCM_TX,
  6949. .stream_name = "Quat AUX PCM Capture",
  6950. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  6951. .platform_name = "msm-pcm-routing",
  6952. .codec_name = "msm-stub-codec.1",
  6953. .codec_dai_name = "msm-stub-tx",
  6954. .no_pcm = 1,
  6955. .dpcm_capture = 1,
  6956. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  6957. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6958. .ops = &msm_auxpcm_be_ops,
  6959. .ignore_suspend = 1,
  6960. },
  6961. /* Quinary AUX PCM Backend DAI Links */
  6962. {
  6963. .name = LPASS_BE_QUIN_AUXPCM_RX,
  6964. .stream_name = "Quin AUX PCM Playback",
  6965. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6966. .platform_name = "msm-pcm-routing",
  6967. .codec_name = "msm-stub-codec.1",
  6968. .codec_dai_name = "msm-stub-rx",
  6969. .no_pcm = 1,
  6970. .dpcm_playback = 1,
  6971. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  6972. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6973. .ops = &msm_auxpcm_be_ops,
  6974. .ignore_pmdown_time = 1,
  6975. .ignore_suspend = 1,
  6976. },
  6977. {
  6978. .name = LPASS_BE_QUIN_AUXPCM_TX,
  6979. .stream_name = "Quin AUX PCM Capture",
  6980. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  6981. .platform_name = "msm-pcm-routing",
  6982. .codec_name = "msm-stub-codec.1",
  6983. .codec_dai_name = "msm-stub-tx",
  6984. .no_pcm = 1,
  6985. .dpcm_capture = 1,
  6986. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  6987. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6988. .ops = &msm_auxpcm_be_ops,
  6989. .ignore_suspend = 1,
  6990. },
  6991. };
  6992. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  6993. /* WSA CDC DMA Backend DAI Links */
  6994. {
  6995. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  6996. .stream_name = "WSA CDC DMA0 Playback",
  6997. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  6998. .platform_name = "msm-pcm-routing",
  6999. .codec_name = "bolero_codec",
  7000. .codec_dai_name = "wsa_macro_rx1",
  7001. .no_pcm = 1,
  7002. .dpcm_playback = 1,
  7003. .init = &msm_wsa_cdc_dma_init,
  7004. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  7005. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7006. .ignore_pmdown_time = 1,
  7007. .ignore_suspend = 1,
  7008. .ops = &msm_cdc_dma_be_ops,
  7009. },
  7010. {
  7011. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  7012. .stream_name = "WSA CDC DMA1 Playback",
  7013. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  7014. .platform_name = "msm-pcm-routing",
  7015. .codec_name = "bolero_codec",
  7016. .codec_dai_name = "wsa_macro_rx_mix",
  7017. .no_pcm = 1,
  7018. .dpcm_playback = 1,
  7019. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  7020. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7021. .ignore_pmdown_time = 1,
  7022. .ignore_suspend = 1,
  7023. .ops = &msm_cdc_dma_be_ops,
  7024. },
  7025. {
  7026. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  7027. .stream_name = "WSA CDC DMA1 Capture",
  7028. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  7029. .platform_name = "msm-pcm-routing",
  7030. .codec_name = "bolero_codec",
  7031. .codec_dai_name = "wsa_macro_echo",
  7032. .no_pcm = 1,
  7033. .dpcm_capture = 1,
  7034. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  7035. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7036. .ignore_suspend = 1,
  7037. .ops = &msm_cdc_dma_be_ops,
  7038. },
  7039. };
  7040. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  7041. {
  7042. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  7043. .stream_name = "VA CDC DMA0 Capture",
  7044. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  7045. .platform_name = "msm-pcm-routing",
  7046. .codec_name = "bolero_codec",
  7047. .codec_dai_name = "va_macro_tx1",
  7048. .no_pcm = 1,
  7049. .dpcm_capture = 1,
  7050. .init = &msm_va_cdc_dma_init,
  7051. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  7052. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7053. .ignore_suspend = 1,
  7054. .ops = &msm_cdc_dma_be_ops,
  7055. },
  7056. {
  7057. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  7058. .stream_name = "VA CDC DMA1 Capture",
  7059. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  7060. .platform_name = "msm-pcm-routing",
  7061. .codec_name = "bolero_codec",
  7062. .codec_dai_name = "va_macro_tx2",
  7063. .no_pcm = 1,
  7064. .dpcm_capture = 1,
  7065. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  7066. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7067. .ignore_suspend = 1,
  7068. .ops = &msm_cdc_dma_be_ops,
  7069. },
  7070. };
  7071. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  7072. {
  7073. .name = LPASS_BE_PRI_SPDIF_RX,
  7074. .stream_name = "Primary SPDIF Playback",
  7075. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  7076. .platform_name = "msm-pcm-routing",
  7077. .codec_name = "msm-stub-codec.1",
  7078. .codec_dai_name = "msm-stub-rx",
  7079. .no_pcm = 1,
  7080. .dpcm_playback = 1,
  7081. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  7082. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7083. .ops = &msm_spdif_be_ops,
  7084. .ignore_suspend = 1,
  7085. .ignore_pmdown_time = 1,
  7086. },
  7087. {
  7088. .name = LPASS_BE_PRI_SPDIF_TX,
  7089. .stream_name = "Primary SPDIF Capture",
  7090. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  7091. .platform_name = "msm-pcm-routing",
  7092. .codec_name = "msm-stub-codec.1",
  7093. .codec_dai_name = "msm-stub-tx",
  7094. .no_pcm = 1,
  7095. .dpcm_capture = 1,
  7096. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  7097. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7098. .ops = &msm_spdif_be_ops,
  7099. .ignore_suspend = 1,
  7100. },
  7101. {
  7102. .name = LPASS_BE_SEC_SPDIF_RX,
  7103. .stream_name = "Secondary SPDIF Playback",
  7104. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  7105. .platform_name = "msm-pcm-routing",
  7106. .codec_name = "msm-stub-codec.1",
  7107. .codec_dai_name = "msm-stub-rx",
  7108. .no_pcm = 1,
  7109. .dpcm_playback = 1,
  7110. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  7111. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7112. .ops = &msm_spdif_be_ops,
  7113. .ignore_suspend = 1,
  7114. .ignore_pmdown_time = 1,
  7115. },
  7116. {
  7117. .name = LPASS_BE_SEC_SPDIF_TX,
  7118. .stream_name = "Secondary SPDIF Capture",
  7119. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  7120. .platform_name = "msm-pcm-routing",
  7121. .codec_name = "msm-stub-codec.1",
  7122. .codec_dai_name = "msm-stub-tx",
  7123. .no_pcm = 1,
  7124. .dpcm_capture = 1,
  7125. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  7126. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7127. .ops = &msm_spdif_be_ops,
  7128. .ignore_suspend = 1,
  7129. },
  7130. };
  7131. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  7132. {
  7133. .name = LPASS_BE_AFE_LOOPBACK_TX,
  7134. .stream_name = "AFE Loopback Capture",
  7135. .cpu_dai_name = "msm-dai-q6-dev.24577",
  7136. .platform_name = "msm-pcm-routing",
  7137. .codec_name = "msm-stub-codec.1",
  7138. .codec_dai_name = "msm-stub-tx",
  7139. .no_pcm = 1,
  7140. .dpcm_capture = 1,
  7141. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  7142. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7143. .ignore_pmdown_time = 1,
  7144. .ignore_suspend = 1,
  7145. },
  7146. };
  7147. static struct snd_soc_dai_link msm_qcs405_dai_links[
  7148. ARRAY_SIZE(msm_common_dai_links) +
  7149. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  7150. ARRAY_SIZE(msm_common_be_dai_links) +
  7151. ARRAY_SIZE(msm_tasha_be_dai_links) +
  7152. ARRAY_SIZE(msm_wcn_be_dai_links) +
  7153. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  7154. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  7155. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  7156. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  7157. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  7158. ARRAY_SIZE(msm_spdif_be_dai_links) +
  7159. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link)];
  7160. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  7161. {
  7162. int ret = 0;
  7163. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  7164. &service_nb);
  7165. if (ret < 0)
  7166. pr_err("%s: Audio notifier register failed ret = %d\n",
  7167. __func__, ret);
  7168. return ret;
  7169. }
  7170. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  7171. struct snd_ctl_elem_value *ucontrol)
  7172. {
  7173. int ret = 0;
  7174. int port_id;
  7175. uint32_t vad_enable = ucontrol->value.integer.value[0];
  7176. uint32_t preroll_config = ucontrol->value.integer.value[1];
  7177. uint32_t vad_intf = ucontrol->value.integer.value[2];
  7178. if ((preroll_config < 0) || (preroll_config > 1000) ||
  7179. (vad_enable < 0) || (vad_enable > 1) ||
  7180. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  7181. pr_err("%s: Invalid arguments\n", __func__);
  7182. ret = -EINVAL;
  7183. goto done;
  7184. }
  7185. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  7186. vad_enable, preroll_config, vad_intf);
  7187. ret = msm_island_vad_get_portid_from_beid(vad_intf, &port_id);
  7188. if (ret) {
  7189. pr_err("%s: Invalid vad interface\n", __func__);
  7190. goto done;
  7191. }
  7192. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  7193. done:
  7194. return ret;
  7195. }
  7196. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  7197. {
  7198. int ret = 0;
  7199. uint32_t tasha_codec = 0;
  7200. ret = afe_cal_init_hwdep(card);
  7201. if (ret) {
  7202. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  7203. ret = 0;
  7204. }
  7205. /* tasha late probe when it is present */
  7206. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  7207. &tasha_codec);
  7208. if (ret) {
  7209. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  7210. ret = 0;
  7211. } else {
  7212. if (tasha_codec) {
  7213. ret = msm_snd_card_tasha_late_probe(card);
  7214. if (ret)
  7215. dev_err(card->dev, "%s: tasha late probe err\n",
  7216. __func__);
  7217. }
  7218. }
  7219. return ret;
  7220. }
  7221. struct snd_soc_card snd_soc_card_qcs405_msm = {
  7222. .name = "qcs405-snd-card",
  7223. .controls = msm_snd_controls,
  7224. .num_controls = ARRAY_SIZE(msm_snd_controls),
  7225. .late_probe = msm_snd_card_codec_late_probe,
  7226. };
  7227. static int msm_populate_dai_link_component_of_node(
  7228. struct snd_soc_card *card)
  7229. {
  7230. int i, index, ret = 0;
  7231. struct device *cdev = card->dev;
  7232. struct snd_soc_dai_link *dai_link = card->dai_link;
  7233. struct device_node *np;
  7234. if (!cdev) {
  7235. pr_err("%s: Sound card device memory NULL\n", __func__);
  7236. return -ENODEV;
  7237. }
  7238. for (i = 0; i < card->num_links; i++) {
  7239. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  7240. continue;
  7241. /* populate platform_of_node for snd card dai links */
  7242. if (dai_link[i].platform_name &&
  7243. !dai_link[i].platform_of_node) {
  7244. index = of_property_match_string(cdev->of_node,
  7245. "asoc-platform-names",
  7246. dai_link[i].platform_name);
  7247. if (index < 0) {
  7248. pr_err("%s: No match found for platform name: %s\n",
  7249. __func__, dai_link[i].platform_name);
  7250. ret = index;
  7251. goto err;
  7252. }
  7253. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  7254. index);
  7255. if (!np) {
  7256. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  7257. __func__, dai_link[i].platform_name,
  7258. index);
  7259. ret = -ENODEV;
  7260. goto err;
  7261. }
  7262. dai_link[i].platform_of_node = np;
  7263. dai_link[i].platform_name = NULL;
  7264. }
  7265. /* populate cpu_of_node for snd card dai links */
  7266. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  7267. index = of_property_match_string(cdev->of_node,
  7268. "asoc-cpu-names",
  7269. dai_link[i].cpu_dai_name);
  7270. if (index >= 0) {
  7271. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  7272. index);
  7273. if (!np) {
  7274. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  7275. __func__,
  7276. dai_link[i].cpu_dai_name);
  7277. ret = -ENODEV;
  7278. goto err;
  7279. }
  7280. dai_link[i].cpu_of_node = np;
  7281. dai_link[i].cpu_dai_name = NULL;
  7282. }
  7283. }
  7284. /* populate codec_of_node for snd card dai links */
  7285. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  7286. index = of_property_match_string(cdev->of_node,
  7287. "asoc-codec-names",
  7288. dai_link[i].codec_name);
  7289. if (index < 0)
  7290. continue;
  7291. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  7292. index);
  7293. if (!np) {
  7294. pr_err("%s: retrieving phandle for codec %s failed\n",
  7295. __func__, dai_link[i].codec_name);
  7296. ret = -ENODEV;
  7297. goto err;
  7298. }
  7299. dai_link[i].codec_of_node = np;
  7300. dai_link[i].codec_name = NULL;
  7301. }
  7302. }
  7303. err:
  7304. return ret;
  7305. }
  7306. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  7307. /* FrontEnd DAI Links */
  7308. {
  7309. .name = "MSMSTUB Media1",
  7310. .stream_name = "MultiMedia1",
  7311. .cpu_dai_name = "MultiMedia1",
  7312. .platform_name = "msm-pcm-dsp.0",
  7313. .dynamic = 1,
  7314. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  7315. .dpcm_playback = 1,
  7316. .dpcm_capture = 1,
  7317. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  7318. SND_SOC_DPCM_TRIGGER_POST},
  7319. .codec_dai_name = "snd-soc-dummy-dai",
  7320. .codec_name = "snd-soc-dummy",
  7321. .ignore_suspend = 1,
  7322. /* this dainlink has playback support */
  7323. .ignore_pmdown_time = 1,
  7324. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  7325. },
  7326. };
  7327. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  7328. /* Backend DAI Links */
  7329. {
  7330. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  7331. .stream_name = "VA CDC DMA0 Capture",
  7332. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  7333. .platform_name = "msm-pcm-routing",
  7334. .codec_name = "bolero_codec",
  7335. .codec_dai_name = "va_macro_tx1",
  7336. .no_pcm = 1,
  7337. .dpcm_capture = 1,
  7338. .init = &msm_va_cdc_dma_init,
  7339. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  7340. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7341. .ignore_suspend = 1,
  7342. .ops = &msm_cdc_dma_be_ops,
  7343. },
  7344. {
  7345. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  7346. .stream_name = "VA CDC DMA1 Capture",
  7347. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  7348. .platform_name = "msm-pcm-routing",
  7349. .codec_name = "bolero_codec",
  7350. .codec_dai_name = "va_macro_tx2",
  7351. .no_pcm = 1,
  7352. .dpcm_capture = 1,
  7353. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  7354. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7355. .ignore_suspend = 1,
  7356. .ops = &msm_cdc_dma_be_ops,
  7357. },
  7358. };
  7359. static struct snd_soc_dai_link msm_stub_dai_links[
  7360. ARRAY_SIZE(msm_stub_fe_dai_links) +
  7361. ARRAY_SIZE(msm_stub_be_dai_links)];
  7362. struct snd_soc_card snd_soc_card_stub_msm = {
  7363. .name = "qcs405-stub-snd-card",
  7364. };
  7365. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  7366. { .compatible = "qcom,qcs405-asoc-snd",
  7367. .data = "codec"},
  7368. { .compatible = "qcom,qcs405-asoc-snd-stub",
  7369. .data = "stub_codec"},
  7370. {},
  7371. };
  7372. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  7373. {
  7374. struct snd_soc_card *card = NULL;
  7375. struct snd_soc_dai_link *dailink;
  7376. int total_links = 0;
  7377. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  7378. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  7379. uint32_t spdif_audio_intf = 0, wcn_audio_intf = 0;
  7380. uint32_t afe_loopback_intf = 0;
  7381. const struct of_device_id *match;
  7382. char __iomem *spdif_cfg, *spdif_pin_ctl;
  7383. int rc = 0;
  7384. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  7385. if (!match) {
  7386. dev_err(dev, "%s: No DT match found for sound card\n",
  7387. __func__);
  7388. return NULL;
  7389. }
  7390. if (!strcmp(match->data, "codec")) {
  7391. card = &snd_soc_card_qcs405_msm;
  7392. memcpy(msm_qcs405_dai_links + total_links,
  7393. msm_common_dai_links,
  7394. sizeof(msm_common_dai_links));
  7395. total_links += ARRAY_SIZE(msm_common_dai_links);
  7396. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  7397. &wsa_bolero_codec);
  7398. if (rc) {
  7399. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  7400. __func__);
  7401. } else {
  7402. if (wsa_bolero_codec) {
  7403. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  7404. __func__);
  7405. memcpy(msm_qcs405_dai_links + total_links,
  7406. msm_bolero_fe_dai_links,
  7407. sizeof(msm_bolero_fe_dai_links));
  7408. total_links +=
  7409. ARRAY_SIZE(msm_bolero_fe_dai_links);
  7410. }
  7411. }
  7412. memcpy(msm_qcs405_dai_links + total_links,
  7413. msm_common_misc_fe_dai_links,
  7414. sizeof(msm_common_misc_fe_dai_links));
  7415. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  7416. memcpy(msm_qcs405_dai_links + total_links,
  7417. msm_common_be_dai_links,
  7418. sizeof(msm_common_be_dai_links));
  7419. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  7420. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  7421. &tasha_codec);
  7422. if (rc) {
  7423. dev_dbg(dev, "%s: No DT match tasha codec\n",
  7424. __func__);
  7425. } else {
  7426. if (tasha_codec) {
  7427. memcpy(msm_qcs405_dai_links + total_links,
  7428. msm_tasha_be_dai_links,
  7429. sizeof(msm_tasha_be_dai_links));
  7430. total_links +=
  7431. ARRAY_SIZE(msm_tasha_be_dai_links);
  7432. }
  7433. }
  7434. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  7435. &va_bolero_codec);
  7436. if (rc) {
  7437. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  7438. __func__);
  7439. } else {
  7440. if (va_bolero_codec) {
  7441. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  7442. __func__);
  7443. memcpy(msm_qcs405_dai_links + total_links,
  7444. msm_va_cdc_dma_be_dai_links,
  7445. sizeof(msm_va_cdc_dma_be_dai_links));
  7446. total_links +=
  7447. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  7448. }
  7449. }
  7450. if (wsa_bolero_codec) {
  7451. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  7452. __func__);
  7453. memcpy(msm_qcs405_dai_links + total_links,
  7454. msm_wsa_cdc_dma_be_dai_links,
  7455. sizeof(msm_wsa_cdc_dma_be_dai_links));
  7456. total_links +=
  7457. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  7458. }
  7459. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  7460. &mi2s_audio_intf);
  7461. if (rc) {
  7462. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  7463. __func__);
  7464. } else {
  7465. if (mi2s_audio_intf) {
  7466. memcpy(msm_qcs405_dai_links + total_links,
  7467. msm_mi2s_be_dai_links,
  7468. sizeof(msm_mi2s_be_dai_links));
  7469. total_links +=
  7470. ARRAY_SIZE(msm_mi2s_be_dai_links);
  7471. }
  7472. }
  7473. rc = of_property_read_u32(dev->of_node,
  7474. "qcom,auxpcm-audio-intf",
  7475. &auxpcm_audio_intf);
  7476. if (rc) {
  7477. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  7478. __func__);
  7479. } else {
  7480. if (auxpcm_audio_intf) {
  7481. memcpy(msm_qcs405_dai_links + total_links,
  7482. msm_auxpcm_be_dai_links,
  7483. sizeof(msm_auxpcm_be_dai_links));
  7484. total_links +=
  7485. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  7486. }
  7487. }
  7488. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  7489. &spdif_audio_intf);
  7490. if (rc) {
  7491. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  7492. __func__);
  7493. } else {
  7494. if (spdif_audio_intf) {
  7495. memcpy(msm_qcs405_dai_links + total_links,
  7496. msm_spdif_be_dai_links,
  7497. sizeof(msm_spdif_be_dai_links));
  7498. total_links +=
  7499. ARRAY_SIZE(msm_spdif_be_dai_links);
  7500. /* enable spdif coax pins */
  7501. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  7502. spdif_pin_ctl =
  7503. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  7504. iowrite32(0xc0, spdif_cfg);
  7505. iowrite32(0x2220, spdif_pin_ctl);
  7506. }
  7507. }
  7508. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  7509. &wcn_audio_intf);
  7510. if (rc) {
  7511. dev_dbg(dev, "%s: No DT match WCN audio interface\n",
  7512. __func__);
  7513. } else {
  7514. if (wcn_audio_intf) {
  7515. memcpy(msm_qcs405_dai_links + total_links,
  7516. msm_wcn_be_dai_links,
  7517. sizeof(msm_wcn_be_dai_links));
  7518. total_links +=
  7519. ARRAY_SIZE(msm_wcn_be_dai_links);
  7520. }
  7521. }
  7522. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  7523. &afe_loopback_intf);
  7524. if (rc) {
  7525. dev_dbg(dev, "%s: No DT match AFE loopback audio interface\n",
  7526. __func__);
  7527. } else {
  7528. if (afe_loopback_intf) {
  7529. memcpy(msm_qcs405_dai_links + total_links,
  7530. msm_afe_rxtx_lb_be_dai_link,
  7531. sizeof(msm_afe_rxtx_lb_be_dai_link));
  7532. total_links +=
  7533. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  7534. }
  7535. }
  7536. dailink = msm_qcs405_dai_links;
  7537. } else if (!strcmp(match->data, "stub_codec")) {
  7538. card = &snd_soc_card_stub_msm;
  7539. memcpy(msm_stub_dai_links + total_links,
  7540. msm_stub_fe_dai_links,
  7541. sizeof(msm_stub_fe_dai_links));
  7542. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  7543. memcpy(msm_stub_dai_links + total_links,
  7544. msm_stub_be_dai_links,
  7545. sizeof(msm_stub_be_dai_links));
  7546. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  7547. dailink = msm_stub_dai_links;
  7548. }
  7549. if (card) {
  7550. card->dai_link = dailink;
  7551. card->num_links = total_links;
  7552. }
  7553. return card;
  7554. }
  7555. static int msm_wsa881x_init(struct snd_soc_component *component)
  7556. {
  7557. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7558. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  7559. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  7560. SPKR_L_BOOST, SPKR_L_VI};
  7561. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  7562. SPKR_R_BOOST, SPKR_R_VI};
  7563. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  7564. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  7565. struct msm_asoc_mach_data *pdata;
  7566. struct snd_soc_dapm_context *dapm;
  7567. int ret = 0;
  7568. if (!component) {
  7569. pr_err("%s component is NULL\n", __func__);
  7570. return -EINVAL;
  7571. }
  7572. dapm = snd_soc_component_get_dapm(component);
  7573. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  7574. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  7575. __func__, component->name);
  7576. wsa881x_set_channel_map(component, &spkleft_ports[0],
  7577. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7578. &ch_rate[0], &spkleft_port_types[0]);
  7579. if (dapm->component) {
  7580. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  7581. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  7582. }
  7583. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  7584. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  7585. __func__, component->name);
  7586. wsa881x_set_channel_map(component, &spkright_ports[0],
  7587. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  7588. &ch_rate[0], &spkright_port_types[0]);
  7589. if (dapm->component) {
  7590. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  7591. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  7592. }
  7593. } else {
  7594. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  7595. component->name);
  7596. ret = -EINVAL;
  7597. goto err;
  7598. }
  7599. pdata = snd_soc_card_get_drvdata(component->card);
  7600. if (pdata && pdata->codec_root)
  7601. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  7602. component);
  7603. err:
  7604. return ret;
  7605. }
  7606. static int msm_init_wsa_dev(struct platform_device *pdev,
  7607. struct snd_soc_card *card)
  7608. {
  7609. struct device_node *wsa_of_node;
  7610. u32 wsa_max_devs;
  7611. u32 wsa_dev_cnt;
  7612. int i;
  7613. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  7614. const char *wsa_auxdev_name_prefix[1];
  7615. char *dev_name_str = NULL;
  7616. int found = 0;
  7617. int ret = 0;
  7618. /* Get maximum WSA device count for this platform */
  7619. ret = of_property_read_u32(pdev->dev.of_node,
  7620. "qcom,wsa-max-devs", &wsa_max_devs);
  7621. if (ret) {
  7622. dev_info(&pdev->dev,
  7623. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  7624. __func__, pdev->dev.of_node->full_name, ret);
  7625. card->num_aux_devs = 0;
  7626. return 0;
  7627. }
  7628. if (wsa_max_devs == 0) {
  7629. dev_warn(&pdev->dev,
  7630. "%s: Max WSA devices is 0 for this target?\n",
  7631. __func__);
  7632. card->num_aux_devs = 0;
  7633. return 0;
  7634. }
  7635. /* Get count of WSA device phandles for this platform */
  7636. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7637. "qcom,wsa-devs", NULL);
  7638. if (wsa_dev_cnt == -ENOENT) {
  7639. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  7640. __func__);
  7641. goto err;
  7642. } else if (wsa_dev_cnt <= 0) {
  7643. dev_err(&pdev->dev,
  7644. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  7645. __func__, wsa_dev_cnt);
  7646. ret = -EINVAL;
  7647. goto err;
  7648. }
  7649. /*
  7650. * Expect total phandles count to be NOT less than maximum possible
  7651. * WSA count. However, if it is less, then assign same value to
  7652. * max count as well.
  7653. */
  7654. if (wsa_dev_cnt < wsa_max_devs) {
  7655. dev_dbg(&pdev->dev,
  7656. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  7657. __func__, wsa_max_devs, wsa_dev_cnt);
  7658. wsa_max_devs = wsa_dev_cnt;
  7659. }
  7660. /* Make sure prefix string passed for each WSA device */
  7661. ret = of_property_count_strings(pdev->dev.of_node,
  7662. "qcom,wsa-aux-dev-prefix");
  7663. if (ret != wsa_dev_cnt) {
  7664. dev_err(&pdev->dev,
  7665. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  7666. __func__, wsa_dev_cnt, ret);
  7667. ret = -EINVAL;
  7668. goto err;
  7669. }
  7670. /*
  7671. * Alloc mem to store phandle and index info of WSA device, if already
  7672. * registered with ALSA core
  7673. */
  7674. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  7675. sizeof(struct msm_wsa881x_dev_info),
  7676. GFP_KERNEL);
  7677. if (!wsa881x_dev_info) {
  7678. ret = -ENOMEM;
  7679. goto err;
  7680. }
  7681. /*
  7682. * search and check whether all WSA devices are already
  7683. * registered with ALSA core or not. If found a node, store
  7684. * the node and the index in a local array of struct for later
  7685. * use.
  7686. */
  7687. for (i = 0; i < wsa_dev_cnt; i++) {
  7688. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  7689. "qcom,wsa-devs", i);
  7690. if (unlikely(!wsa_of_node)) {
  7691. /* we should not be here */
  7692. dev_err(&pdev->dev,
  7693. "%s: wsa dev node is not present\n",
  7694. __func__);
  7695. ret = -EINVAL;
  7696. goto err_free_dev_info;
  7697. }
  7698. if (soc_find_component(wsa_of_node, NULL)) {
  7699. /* WSA device registered with ALSA core */
  7700. wsa881x_dev_info[found].of_node = wsa_of_node;
  7701. wsa881x_dev_info[found].index = i;
  7702. found++;
  7703. if (found == wsa_max_devs)
  7704. break;
  7705. }
  7706. }
  7707. if (found < wsa_max_devs) {
  7708. dev_err(&pdev->dev,
  7709. "%s: failed to find %d components. Found only %d\n",
  7710. __func__, wsa_max_devs, found);
  7711. return -EPROBE_DEFER;
  7712. }
  7713. dev_info(&pdev->dev,
  7714. "%s: found %d wsa881x devices registered with ALSA core\n",
  7715. __func__, found);
  7716. card->num_aux_devs = wsa_max_devs;
  7717. card->num_configs = wsa_max_devs;
  7718. /* Alloc array of AUX devs struct */
  7719. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7720. sizeof(struct snd_soc_aux_dev),
  7721. GFP_KERNEL);
  7722. if (!msm_aux_dev) {
  7723. ret = -ENOMEM;
  7724. goto err_free_dev_info;
  7725. }
  7726. /* Alloc array of codec conf struct */
  7727. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7728. sizeof(struct snd_soc_codec_conf),
  7729. GFP_KERNEL);
  7730. if (!msm_codec_conf) {
  7731. ret = -ENOMEM;
  7732. goto err_free_aux_dev;
  7733. }
  7734. for (i = 0; i < card->num_aux_devs; i++) {
  7735. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7736. GFP_KERNEL);
  7737. if (!dev_name_str) {
  7738. ret = -ENOMEM;
  7739. goto err_free_cdc_conf;
  7740. }
  7741. ret = of_property_read_string_index(pdev->dev.of_node,
  7742. "qcom,wsa-aux-dev-prefix",
  7743. wsa881x_dev_info[i].index,
  7744. wsa_auxdev_name_prefix);
  7745. if (ret) {
  7746. dev_err(&pdev->dev,
  7747. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  7748. __func__, ret);
  7749. ret = -EINVAL;
  7750. goto err_free_dev_name_str;
  7751. }
  7752. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  7753. msm_aux_dev[i].name = dev_name_str;
  7754. msm_aux_dev[i].codec_name = NULL;
  7755. msm_aux_dev[i].codec_of_node =
  7756. wsa881x_dev_info[i].of_node;
  7757. msm_aux_dev[i].init = msm_wsa881x_init;
  7758. msm_codec_conf[i].dev_name = NULL;
  7759. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  7760. msm_codec_conf[i].of_node =
  7761. wsa881x_dev_info[i].of_node;
  7762. }
  7763. card->codec_conf = msm_codec_conf;
  7764. card->aux_dev = msm_aux_dev;
  7765. return 0;
  7766. err_free_dev_name_str:
  7767. devm_kfree(&pdev->dev, dev_name_str);
  7768. err_free_cdc_conf:
  7769. devm_kfree(&pdev->dev, msm_codec_conf);
  7770. err_free_aux_dev:
  7771. devm_kfree(&pdev->dev, msm_aux_dev);
  7772. err_free_dev_info:
  7773. devm_kfree(&pdev->dev, wsa881x_dev_info);
  7774. err:
  7775. return ret;
  7776. }
  7777. static int msm_csra66x0_init(struct snd_soc_component *component)
  7778. {
  7779. if (!component) {
  7780. pr_err("%s component is NULL\n", __func__);
  7781. return -EINVAL;
  7782. }
  7783. return 0;
  7784. }
  7785. static int msm_init_csra_dev(struct platform_device *pdev,
  7786. struct snd_soc_card *card)
  7787. {
  7788. struct device_node *csra_of_node;
  7789. u32 csra_max_devs;
  7790. u32 csra_dev_cnt;
  7791. char *dev_name_str = NULL;
  7792. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  7793. const char *csra_auxdev_name_prefix[1];
  7794. int i;
  7795. int found = 0;
  7796. int ret = 0;
  7797. /* Get maximum CSRA device count for this platform */
  7798. ret = of_property_read_u32(pdev->dev.of_node,
  7799. "qcom,csra-max-devs", &csra_max_devs);
  7800. if (ret) {
  7801. dev_info(&pdev->dev,
  7802. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  7803. __func__, pdev->dev.of_node->full_name, ret);
  7804. card->num_aux_devs = 0;
  7805. return 0;
  7806. }
  7807. if (csra_max_devs == 0) {
  7808. dev_warn(&pdev->dev,
  7809. "%s: Max CSRA devices is 0 for this target?\n",
  7810. __func__);
  7811. return 0;
  7812. }
  7813. /* Get count of CSRA device phandles for this platform */
  7814. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  7815. "qcom,csra-devs", NULL);
  7816. if (csra_dev_cnt == -ENOENT) {
  7817. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  7818. __func__);
  7819. goto err;
  7820. } else if (csra_dev_cnt <= 0) {
  7821. dev_err(&pdev->dev,
  7822. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  7823. __func__, csra_dev_cnt);
  7824. ret = -EINVAL;
  7825. goto err;
  7826. }
  7827. /*
  7828. * Expect total phandles count to be NOT less than maximum possible
  7829. * CSRA count. However, if it is less, then assign same value to
  7830. * max count as well.
  7831. */
  7832. if (csra_dev_cnt < csra_max_devs) {
  7833. dev_dbg(&pdev->dev,
  7834. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  7835. __func__, csra_max_devs, csra_dev_cnt);
  7836. csra_max_devs = csra_dev_cnt;
  7837. }
  7838. /* Make sure prefix string passed for each CSRA device */
  7839. ret = of_property_count_strings(pdev->dev.of_node,
  7840. "qcom,csra-aux-dev-prefix");
  7841. if (ret != csra_dev_cnt) {
  7842. dev_err(&pdev->dev,
  7843. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  7844. __func__, csra_dev_cnt, ret);
  7845. ret = -EINVAL;
  7846. goto err;
  7847. }
  7848. /*
  7849. * Alloc mem to store phandle and index info of CSRA device, if already
  7850. * registered with ALSA core
  7851. */
  7852. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  7853. sizeof(struct msm_csra66x0_dev_info),
  7854. GFP_KERNEL);
  7855. if (!csra66x0_dev_info) {
  7856. ret = -ENOMEM;
  7857. goto err;
  7858. }
  7859. /*
  7860. * search and check whether all CSRA devices are already
  7861. * registered with ALSA core or not. If found a node, store
  7862. * the node and the index in a local array of struct for later
  7863. * use.
  7864. */
  7865. for (i = 0; i < csra_dev_cnt; i++) {
  7866. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  7867. "qcom,csra-devs", i);
  7868. if (unlikely(!csra_of_node)) {
  7869. /* we should not be here */
  7870. dev_err(&pdev->dev,
  7871. "%s: csra dev node is not present\n",
  7872. __func__);
  7873. ret = -EINVAL;
  7874. goto err_free_dev_info;
  7875. }
  7876. if (soc_find_component(csra_of_node, NULL)) {
  7877. /* CSRA device registered with ALSA core */
  7878. csra66x0_dev_info[found].of_node = csra_of_node;
  7879. csra66x0_dev_info[found].index = i;
  7880. found++;
  7881. if (found == csra_max_devs)
  7882. break;
  7883. }
  7884. }
  7885. if (found < csra_max_devs) {
  7886. dev_dbg(&pdev->dev,
  7887. "%s: failed to find %d components. Found only %d\n",
  7888. __func__, csra_max_devs, found);
  7889. return -EPROBE_DEFER;
  7890. }
  7891. dev_info(&pdev->dev,
  7892. "%s: found %d csra66x0 devices registered with ALSA core\n",
  7893. __func__, found);
  7894. card->num_aux_devs = csra_max_devs;
  7895. card->num_configs = csra_max_devs;
  7896. /* Alloc array of AUX devs struct */
  7897. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7898. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  7899. if (!msm_aux_dev) {
  7900. ret = -ENOMEM;
  7901. goto err_free_dev_info;
  7902. }
  7903. /* Alloc array of codec conf struct */
  7904. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  7905. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  7906. if (!msm_codec_conf) {
  7907. ret = -ENOMEM;
  7908. goto err_free_aux_dev;
  7909. }
  7910. for (i = 0; i < card->num_aux_devs; i++) {
  7911. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  7912. GFP_KERNEL);
  7913. if (!dev_name_str) {
  7914. ret = -ENOMEM;
  7915. goto err_free_cdc_conf;
  7916. }
  7917. ret = of_property_read_string_index(pdev->dev.of_node,
  7918. "qcom,csra-aux-dev-prefix",
  7919. csra66x0_dev_info[i].index,
  7920. csra_auxdev_name_prefix);
  7921. if (ret) {
  7922. dev_err(&pdev->dev,
  7923. "%s: failed to read csra aux dev prefix, ret = %d\n",
  7924. __func__, ret);
  7925. ret = -EINVAL;
  7926. goto err_free_dev_name_str;
  7927. }
  7928. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  7929. msm_aux_dev[i].name = dev_name_str;
  7930. msm_aux_dev[i].codec_name = NULL;
  7931. msm_aux_dev[i].codec_of_node =
  7932. csra66x0_dev_info[i].of_node;
  7933. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  7934. msm_codec_conf[i].dev_name = NULL;
  7935. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  7936. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  7937. }
  7938. card->codec_conf = msm_codec_conf;
  7939. card->aux_dev = msm_aux_dev;
  7940. return 0;
  7941. err_free_dev_name_str:
  7942. devm_kfree(&pdev->dev, dev_name_str);
  7943. err_free_cdc_conf:
  7944. devm_kfree(&pdev->dev, msm_codec_conf);
  7945. err_free_aux_dev:
  7946. devm_kfree(&pdev->dev, msm_aux_dev);
  7947. err_free_dev_info:
  7948. devm_kfree(&pdev->dev, csra66x0_dev_info);
  7949. err:
  7950. return ret;
  7951. }
  7952. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  7953. {
  7954. int count;
  7955. u32 mi2s_master_slave[MI2S_MAX];
  7956. int ret;
  7957. for (count = 0; count < MI2S_MAX; count++) {
  7958. mutex_init(&mi2s_intf_conf[count].lock);
  7959. mi2s_intf_conf[count].ref_cnt = 0;
  7960. }
  7961. ret = of_property_read_u32_array(pdev->dev.of_node,
  7962. "qcom,msm-mi2s-master",
  7963. mi2s_master_slave, MI2S_MAX);
  7964. if (ret) {
  7965. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  7966. __func__);
  7967. } else {
  7968. for (count = 0; count < MI2S_MAX; count++) {
  7969. mi2s_intf_conf[count].msm_is_mi2s_master =
  7970. mi2s_master_slave[count];
  7971. }
  7972. }
  7973. }
  7974. static void msm_i2s_auxpcm_deinit(void)
  7975. {
  7976. int count;
  7977. for (count = 0; count < MI2S_MAX; count++) {
  7978. mutex_destroy(&mi2s_intf_conf[count].lock);
  7979. mi2s_intf_conf[count].ref_cnt = 0;
  7980. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  7981. }
  7982. }
  7983. static int msm_scan_i2c_addr(struct platform_device *pdev,
  7984. uint32_t busnum, uint32_t addr)
  7985. {
  7986. struct i2c_adapter *adap;
  7987. u8 rbuf;
  7988. struct i2c_msg msg;
  7989. int status = 0;
  7990. adap = i2c_get_adapter(busnum);
  7991. if (!adap) {
  7992. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  7993. __func__, busnum);
  7994. return -EBUSY;
  7995. }
  7996. /* to test presence, read one byte from device */
  7997. msg.addr = addr;
  7998. msg.flags = I2C_M_RD;
  7999. msg.len = 1;
  8000. msg.buf = &rbuf;
  8001. status = i2c_transfer(adap, &msg, 1);
  8002. i2c_put_adapter(adap);
  8003. if (status != 1) {
  8004. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  8005. __func__, addr);
  8006. return -ENODEV;
  8007. }
  8008. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  8009. __func__, addr);
  8010. return 0;
  8011. }
  8012. static int msm_detect_ep92_dev(struct platform_device *pdev,
  8013. struct snd_soc_card *card)
  8014. {
  8015. int i;
  8016. uint32_t ep92_busnum = 0;
  8017. uint32_t ep92_reg = 0;
  8018. const char *ep92_name = NULL;
  8019. struct snd_soc_dai_link *dai;
  8020. int rc = 0;
  8021. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  8022. &ep92_busnum);
  8023. if (rc) {
  8024. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  8025. return 0;
  8026. }
  8027. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  8028. &ep92_reg);
  8029. if (rc) {
  8030. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  8031. return 0;
  8032. }
  8033. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  8034. &ep92_name);
  8035. if (rc) {
  8036. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  8037. return 0;
  8038. }
  8039. /* check I2C bus for connected ep92 chip */
  8040. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  8041. /* check a second time after a short delay */
  8042. msleep(20);
  8043. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  8044. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  8045. __func__);
  8046. /* continue with snd_card registration without ep92 */
  8047. return 0;
  8048. }
  8049. }
  8050. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  8051. /* update codec info in MI2S dai link */
  8052. dai = &msm_mi2s_be_dai_links[0];
  8053. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  8054. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  8055. dev_dbg(&pdev->dev,
  8056. "%s: Set Sec MI2S dai to ep92 codec\n",
  8057. __func__);
  8058. dai->codec_name = ep92_name;
  8059. dai->codec_dai_name = "ep92-hdmi";
  8060. break;
  8061. }
  8062. dai++;
  8063. }
  8064. /* update codec info in SPDIF dai link */
  8065. dai = &msm_spdif_be_dai_links[0];
  8066. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  8067. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  8068. dev_dbg(&pdev->dev,
  8069. "%s: Set Sec SPDIF dai to ep92 codec\n",
  8070. __func__);
  8071. dai->codec_name = ep92_name;
  8072. dai->codec_dai_name = "ep92-arc";
  8073. break;
  8074. }
  8075. dai++;
  8076. }
  8077. return 0;
  8078. }
  8079. static int msm_asoc_machine_probe(struct platform_device *pdev)
  8080. {
  8081. struct snd_soc_card *card;
  8082. struct msm_asoc_mach_data *pdata;
  8083. int ret;
  8084. u32 val;
  8085. const char *micb_supply_str = "tdm-vdd-micb-supply";
  8086. const char *micb_supply_str1 = "tdm-vdd-micb";
  8087. const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage";
  8088. const char *micb_current_str = "qcom,tdm-vdd-micb-current";
  8089. if (!pdev->dev.of_node) {
  8090. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  8091. return -EINVAL;
  8092. }
  8093. pdata = devm_kzalloc(&pdev->dev,
  8094. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  8095. if (!pdata)
  8096. return -ENOMEM;
  8097. /* test for ep92 HDMI bridge and update dai links accordingly */
  8098. ret = msm_detect_ep92_dev(pdev, card);
  8099. if (ret)
  8100. goto err;
  8101. card = populate_snd_card_dailinks(&pdev->dev);
  8102. if (!card) {
  8103. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  8104. ret = -EINVAL;
  8105. goto err;
  8106. }
  8107. card->dev = &pdev->dev;
  8108. platform_set_drvdata(pdev, card);
  8109. snd_soc_card_set_drvdata(card, pdata);
  8110. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  8111. if (ret) {
  8112. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  8113. ret);
  8114. goto err;
  8115. }
  8116. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  8117. if (ret) {
  8118. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  8119. ret);
  8120. goto err;
  8121. }
  8122. ret = msm_populate_dai_link_component_of_node(card);
  8123. if (ret) {
  8124. ret = -EPROBE_DEFER;
  8125. goto err;
  8126. }
  8127. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  8128. if (ret) {
  8129. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  8130. val = 0;
  8131. }
  8132. if (val) {
  8133. pdata->codec_is_csra = true;
  8134. mi2s_rx_cfg[PRIM_MI2S].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  8135. ret = msm_init_csra_dev(pdev, card);
  8136. if (ret)
  8137. goto err;
  8138. } else {
  8139. pdata->codec_is_csra = false;
  8140. ret = msm_init_wsa_dev(pdev, card);
  8141. if (ret)
  8142. goto err;
  8143. }
  8144. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8145. "qcom,cdc-dmic01-gpios", 0);
  8146. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8147. "qcom,cdc-dmic23-gpios", 0);
  8148. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8149. "qcom,cdc-dmic45-gpios", 0);
  8150. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8151. "qcom,cdc-dmic67-gpios", 0);
  8152. pdata->lineout_booster_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8153. "qcom,lineout-booster-gpio", 0);
  8154. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8155. "qcom,pri-mi2s-gpios", 0);
  8156. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8157. "qcom,sec-mi2s-gpios", 0);
  8158. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8159. "qcom,tert-mi2s-gpios", 0);
  8160. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8161. "qcom,quat-mi2s-gpios", 0);
  8162. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  8163. "qcom,quin-mi2s-gpios", 0);
  8164. if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) {
  8165. pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev,
  8166. micb_supply_str1);
  8167. if (IS_ERR(pdata->tdm_micb_supply)) {
  8168. ret = PTR_ERR(pdata->tdm_micb_supply);
  8169. dev_err(&pdev->dev,
  8170. "%s:Failed to get micbias supply for TDM Mic %d\n",
  8171. __func__, ret);
  8172. }
  8173. ret = of_property_read_u32(pdev->dev.of_node,
  8174. micb_voltage_str,
  8175. &pdata->tdm_micb_voltage);
  8176. if (ret) {
  8177. dev_err(&pdev->dev,
  8178. "%s:Looking up %s property in node %s failed\n",
  8179. __func__, micb_voltage_str,
  8180. pdev->dev.of_node->full_name);
  8181. }
  8182. ret = of_property_read_u32(pdev->dev.of_node,
  8183. micb_current_str,
  8184. &pdata->tdm_micb_current);
  8185. if (ret) {
  8186. dev_err(&pdev->dev,
  8187. "%s:Looking up %s property in node %s failed\n",
  8188. __func__, micb_current_str,
  8189. pdev->dev.of_node->full_name);
  8190. }
  8191. }
  8192. ret = devm_snd_soc_register_card(&pdev->dev, card);
  8193. if (ret == -EPROBE_DEFER) {
  8194. if (codec_reg_done)
  8195. ret = -EINVAL;
  8196. goto err;
  8197. } else if (ret) {
  8198. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  8199. ret);
  8200. goto err;
  8201. }
  8202. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  8203. spdev = pdev;
  8204. ret = msm_mdf_mem_init();
  8205. if (ret)
  8206. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  8207. ret);
  8208. msm_i2s_auxpcm_init(pdev);
  8209. is_initial_boot = true;
  8210. return 0;
  8211. err:
  8212. return ret;
  8213. }
  8214. static int msm_asoc_machine_remove(struct platform_device *pdev)
  8215. {
  8216. audio_notifier_deregister("qcs405");
  8217. msm_i2s_auxpcm_deinit();
  8218. msm_mdf_mem_deinit();
  8219. return 0;
  8220. }
  8221. static struct platform_driver qcs405_asoc_machine_driver = {
  8222. .driver = {
  8223. .name = DRV_NAME,
  8224. .owner = THIS_MODULE,
  8225. .pm = &snd_soc_pm_ops,
  8226. .of_match_table = qcs405_asoc_machine_of_match,
  8227. .suppress_bind_attrs = true,
  8228. },
  8229. .probe = msm_asoc_machine_probe,
  8230. .remove = msm_asoc_machine_remove,
  8231. };
  8232. module_platform_driver(qcs405_asoc_machine_driver);
  8233. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  8234. MODULE_LICENSE("GPL v2");
  8235. MODULE_ALIAS("platform:" DRV_NAME);
  8236. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);