swr-mstr-ctrl.c 104 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/irq.h>
  6. #include <linux/kernel.h>
  7. #include <linux/init.h>
  8. #include <linux/slab.h>
  9. #include <linux/io.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/delay.h>
  13. #include <linux/kthread.h>
  14. #include <linux/bitops.h>
  15. #include <linux/clk.h>
  16. #include <linux/gpio.h>
  17. #include <linux/of_gpio.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/of.h>
  20. #include <soc/soundwire.h>
  21. #include <soc/swr-common.h>
  22. #include <linux/regmap.h>
  23. #include <dsp/msm-audio-event-notify.h>
  24. #include "swr-mstr-registers.h"
  25. #include "swr-slave-registers.h"
  26. #include <dsp/digital-cdc-rsc-mgr.h>
  27. #include "swr-mstr-ctrl.h"
  28. #define SWR_NUM_PORTS 4 /* TODO - Get this info from DT */
  29. #define SWRM_FRAME_SYNC_SEL 4000 /* 4KHz */
  30. #define SWRM_FRAME_SYNC_SEL_NATIVE 3675 /* 3.675KHz */
  31. #define SWRM_PCM_OUT 0
  32. #define SWRM_PCM_IN 1
  33. #define SWRM_SYSTEM_RESUME_TIMEOUT_MS 700
  34. #define SWRM_SYS_SUSPEND_WAIT 1
  35. #define SWRM_DSD_PARAMS_PORT 4
  36. #define SWR_BROADCAST_CMD_ID 0x0F
  37. #define SWR_DEV_ID_MASK 0xFFFFFFFFFFFF
  38. #define SWR_REG_VAL_PACK(data, dev, id, reg) \
  39. ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
  40. #define SWR_INVALID_PARAM 0xFF
  41. #define SWR_HSTOP_MAX_VAL 0xF
  42. #define SWR_HSTART_MIN_VAL 0x0
  43. #define ERR_AUTO_SUSPEND_TIMER_VAL 0x1
  44. #define SWRM_INTERRUPT_STATUS_MASK 0x1FDFD
  45. #define SWRM_LINK_STATUS_RETRY_CNT 100
  46. #define SWRM_ROW_48 48
  47. #define SWRM_ROW_50 50
  48. #define SWRM_ROW_64 64
  49. #define SWRM_COL_02 02
  50. #define SWRM_COL_16 16
  51. #define SWRS_SCP_INT_STATUS_CLEAR_1 0x40
  52. #define SWRS_SCP_INT_STATUS_MASK_1 0x41
  53. #define SWRM_MCP_SLV_STATUS_MASK 0x03
  54. #define SWRM_ROW_CTRL_MASK 0xF8
  55. #define SWRM_COL_CTRL_MASK 0x07
  56. #define SWRM_CLK_DIV_MASK 0x700
  57. #define SWRM_SSP_PERIOD_MASK 0xff0000
  58. #define SWRM_NUM_PINGS_MASK 0x3E0000
  59. #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT 3
  60. #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT 0
  61. #define SWRM_MCP_FRAME_CTRL_BANK_CLK_DIV_VALUE_SHFT 8
  62. #define SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT 16
  63. #define SWRM_NUM_PINGS_POS 0x11
  64. #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
  65. #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
  66. #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
  67. #define SWR_OVERFLOW_RETRY_COUNT 30
  68. #define CPU_IDLE_LATENCY 10
  69. /* pm runtime auto suspend timer in msecs */
  70. static int auto_suspend_timer = 500;
  71. module_param(auto_suspend_timer, int, 0664);
  72. MODULE_PARM_DESC(auto_suspend_timer, "timer for auto suspend");
  73. enum {
  74. SWR_NOT_PRESENT, /* Device is detached/not present on the bus */
  75. SWR_ATTACHED_OK, /* Device is attached */
  76. SWR_ALERT, /* Device alters master for any interrupts */
  77. SWR_RESERVED, /* Reserved */
  78. };
  79. enum {
  80. MASTER_ID_WSA = 1,
  81. MASTER_ID_RX,
  82. MASTER_ID_TX
  83. };
  84. enum {
  85. ENABLE_PENDING,
  86. DISABLE_PENDING
  87. };
  88. enum {
  89. LPASS_HW_CORE,
  90. LPASS_AUDIO_CORE,
  91. };
  92. enum {
  93. SWRM_WR_CHECK_AVAIL,
  94. SWRM_RD_CHECK_AVAIL,
  95. };
  96. #define TRUE 1
  97. #define FALSE 0
  98. #define SWRM_MAX_PORT_REG 120
  99. #define SWRM_MAX_INIT_REG 12
  100. #define MAX_FIFO_RD_FAIL_RETRY 3
  101. static bool swrm_lock_sleep(struct swr_mstr_ctrl *swrm);
  102. static void swrm_unlock_sleep(struct swr_mstr_ctrl *swrm);
  103. static u32 swr_master_read(struct swr_mstr_ctrl *swrm, unsigned int reg_addr);
  104. static void swr_master_write(struct swr_mstr_ctrl *swrm, u16 reg_addr, u32 val);
  105. static int swrm_runtime_resume(struct device *dev);
  106. static u8 swrm_get_clk_div(int mclk_freq, int bus_clk_freq)
  107. {
  108. int clk_div = 0;
  109. u8 div_val = 0;
  110. if (!mclk_freq || !bus_clk_freq)
  111. return 0;
  112. clk_div = (mclk_freq / bus_clk_freq);
  113. switch (clk_div) {
  114. case 32:
  115. div_val = 5;
  116. break;
  117. case 16:
  118. div_val = 4;
  119. break;
  120. case 8:
  121. div_val = 3;
  122. break;
  123. case 4:
  124. div_val = 2;
  125. break;
  126. case 2:
  127. div_val = 1;
  128. break;
  129. case 1:
  130. default:
  131. div_val = 0;
  132. break;
  133. }
  134. return div_val;
  135. }
  136. static bool swrm_is_msm_variant(int val)
  137. {
  138. return (val == SWRM_VERSION_1_3);
  139. }
  140. #ifdef CONFIG_DEBUG_FS
  141. static int swrm_debug_open(struct inode *inode, struct file *file)
  142. {
  143. file->private_data = inode->i_private;
  144. return 0;
  145. }
  146. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  147. {
  148. char *token;
  149. int base, cnt;
  150. token = strsep(&buf, " ");
  151. for (cnt = 0; cnt < num_of_par; cnt++) {
  152. if (token) {
  153. if ((token[1] == 'x') || (token[1] == 'X'))
  154. base = 16;
  155. else
  156. base = 10;
  157. if (kstrtou32(token, base, &param1[cnt]) != 0)
  158. return -EINVAL;
  159. token = strsep(&buf, " ");
  160. } else
  161. return -EINVAL;
  162. }
  163. return 0;
  164. }
  165. static ssize_t swrm_reg_show(struct swr_mstr_ctrl *swrm, char __user *ubuf,
  166. size_t count, loff_t *ppos)
  167. {
  168. int i, reg_val, len;
  169. ssize_t total = 0;
  170. char tmp_buf[SWR_MSTR_MAX_BUF_LEN];
  171. int rem = 0;
  172. if (!ubuf || !ppos)
  173. return 0;
  174. i = ((int) *ppos + SWRM_BASE);
  175. rem = i%4;
  176. if (rem)
  177. i = (i - rem);
  178. for (; i <= SWRM_MAX_REGISTER; i += 4) {
  179. usleep_range(100, 150);
  180. reg_val = swr_master_read(swrm, i);
  181. len = snprintf(tmp_buf, 25, "0x%.3x: 0x%.2x\n", i, reg_val);
  182. if (len < 0) {
  183. pr_err("%s: fail to fill the buffer\n", __func__);
  184. total = -EFAULT;
  185. goto copy_err;
  186. }
  187. if ((total + len) >= count - 1)
  188. break;
  189. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  190. pr_err("%s: fail to copy reg dump\n", __func__);
  191. total = -EFAULT;
  192. goto copy_err;
  193. }
  194. *ppos += len;
  195. total += len;
  196. }
  197. copy_err:
  198. return total;
  199. }
  200. static ssize_t swrm_debug_reg_dump(struct file *file, char __user *ubuf,
  201. size_t count, loff_t *ppos)
  202. {
  203. struct swr_mstr_ctrl *swrm;
  204. if (!count || !file || !ppos || !ubuf)
  205. return -EINVAL;
  206. swrm = file->private_data;
  207. if (!swrm)
  208. return -EINVAL;
  209. if (*ppos < 0)
  210. return -EINVAL;
  211. return swrm_reg_show(swrm, ubuf, count, ppos);
  212. }
  213. static ssize_t swrm_debug_read(struct file *file, char __user *ubuf,
  214. size_t count, loff_t *ppos)
  215. {
  216. char lbuf[SWR_MSTR_RD_BUF_LEN];
  217. struct swr_mstr_ctrl *swrm = NULL;
  218. if (!count || !file || !ppos || !ubuf)
  219. return -EINVAL;
  220. swrm = file->private_data;
  221. if (!swrm)
  222. return -EINVAL;
  223. if (*ppos < 0)
  224. return -EINVAL;
  225. snprintf(lbuf, sizeof(lbuf), "0x%x\n", swrm->read_data);
  226. return simple_read_from_buffer(ubuf, count, ppos, lbuf,
  227. strnlen(lbuf, 7));
  228. }
  229. static ssize_t swrm_debug_peek_write(struct file *file, const char __user *ubuf,
  230. size_t count, loff_t *ppos)
  231. {
  232. char lbuf[SWR_MSTR_RD_BUF_LEN];
  233. int rc;
  234. u32 param[5];
  235. struct swr_mstr_ctrl *swrm = NULL;
  236. if (!count || !file || !ppos || !ubuf)
  237. return -EINVAL;
  238. swrm = file->private_data;
  239. if (!swrm)
  240. return -EINVAL;
  241. if (*ppos < 0)
  242. return -EINVAL;
  243. if (count > sizeof(lbuf) - 1)
  244. return -EINVAL;
  245. rc = copy_from_user(lbuf, ubuf, count);
  246. if (rc)
  247. return -EFAULT;
  248. lbuf[count] = '\0';
  249. rc = get_parameters(lbuf, param, 1);
  250. if ((param[0] <= SWRM_MAX_REGISTER) && (rc == 0))
  251. swrm->read_data = swr_master_read(swrm, param[0]);
  252. else
  253. rc = -EINVAL;
  254. if (rc == 0)
  255. rc = count;
  256. else
  257. dev_err(swrm->dev, "%s: rc = %d\n", __func__, rc);
  258. return rc;
  259. }
  260. static ssize_t swrm_debug_write(struct file *file,
  261. const char __user *ubuf, size_t count, loff_t *ppos)
  262. {
  263. char lbuf[SWR_MSTR_WR_BUF_LEN];
  264. int rc;
  265. u32 param[5];
  266. struct swr_mstr_ctrl *swrm;
  267. if (!file || !ppos || !ubuf)
  268. return -EINVAL;
  269. swrm = file->private_data;
  270. if (!swrm)
  271. return -EINVAL;
  272. if (count > sizeof(lbuf) - 1)
  273. return -EINVAL;
  274. rc = copy_from_user(lbuf, ubuf, count);
  275. if (rc)
  276. return -EFAULT;
  277. lbuf[count] = '\0';
  278. rc = get_parameters(lbuf, param, 2);
  279. if ((param[0] <= SWRM_MAX_REGISTER) &&
  280. (param[1] <= 0xFFFFFFFF) &&
  281. (rc == 0))
  282. swr_master_write(swrm, param[0], param[1]);
  283. else
  284. rc = -EINVAL;
  285. if (rc == 0)
  286. rc = count;
  287. else
  288. pr_err("%s: rc = %d\n", __func__, rc);
  289. return rc;
  290. }
  291. static const struct file_operations swrm_debug_read_ops = {
  292. .open = swrm_debug_open,
  293. .write = swrm_debug_peek_write,
  294. .read = swrm_debug_read,
  295. };
  296. static const struct file_operations swrm_debug_write_ops = {
  297. .open = swrm_debug_open,
  298. .write = swrm_debug_write,
  299. };
  300. static const struct file_operations swrm_debug_dump_ops = {
  301. .open = swrm_debug_open,
  302. .read = swrm_debug_reg_dump,
  303. };
  304. #endif
  305. static void swrm_reg_dump(struct swr_mstr_ctrl *swrm,
  306. u32 *reg, u32 *val, int len, const char* func)
  307. {
  308. int i = 0;
  309. for (i = 0; i < len; i++)
  310. dev_dbg(swrm->dev, "%s: reg = 0x%x val = 0x%x\n",
  311. func, reg[i], val[i]);
  312. }
  313. static bool is_swr_clk_needed(struct swr_mstr_ctrl *swrm)
  314. {
  315. return ((swrm->version <= SWRM_VERSION_1_5_1) ? true : false);
  316. }
  317. static int swrm_request_hw_vote(struct swr_mstr_ctrl *swrm,
  318. int core_type, bool enable)
  319. {
  320. int ret = 0;
  321. mutex_lock(&swrm->devlock);
  322. if (core_type == LPASS_HW_CORE) {
  323. if (swrm->lpass_core_hw_vote) {
  324. if (enable) {
  325. if (!swrm->dev_up) {
  326. dev_dbg(swrm->dev, "%s: device is down or SSR state\n",
  327. __func__);
  328. trace_printk("%s: device is down or SSR state\n",
  329. __func__);
  330. mutex_unlock(&swrm->devlock);
  331. return -ENODEV;
  332. }
  333. if (++swrm->hw_core_clk_en == 1) {
  334. ret =
  335. digital_cdc_rsc_mgr_hw_vote_enable(
  336. swrm->lpass_core_hw_vote);
  337. if (ret < 0) {
  338. dev_err(swrm->dev,
  339. "%s:lpass core hw enable failed\n",
  340. __func__);
  341. --swrm->hw_core_clk_en;
  342. }
  343. }
  344. } else {
  345. --swrm->hw_core_clk_en;
  346. if (swrm->hw_core_clk_en < 0)
  347. swrm->hw_core_clk_en = 0;
  348. else if (swrm->hw_core_clk_en == 0)
  349. digital_cdc_rsc_mgr_hw_vote_disable(
  350. swrm->lpass_core_hw_vote);
  351. }
  352. }
  353. }
  354. if (core_type == LPASS_AUDIO_CORE) {
  355. if (swrm->lpass_core_audio) {
  356. if (enable) {
  357. if (!swrm->dev_up) {
  358. dev_dbg(swrm->dev, "%s: device is down or SSR state\n",
  359. __func__);
  360. trace_printk("%s: device is down or SSR state\n",
  361. __func__);
  362. mutex_unlock(&swrm->devlock);
  363. return -ENODEV;
  364. }
  365. if (++swrm->aud_core_clk_en == 1) {
  366. ret =
  367. digital_cdc_rsc_mgr_hw_vote_enable(
  368. swrm->lpass_core_audio);
  369. if (ret < 0) {
  370. dev_err(swrm->dev,
  371. "%s:lpass audio hw enable failed\n",
  372. __func__);
  373. --swrm->aud_core_clk_en;
  374. }
  375. }
  376. } else {
  377. --swrm->aud_core_clk_en;
  378. if (swrm->aud_core_clk_en < 0)
  379. swrm->aud_core_clk_en = 0;
  380. else if (swrm->aud_core_clk_en == 0)
  381. digital_cdc_rsc_mgr_hw_vote_disable(
  382. swrm->lpass_core_audio);
  383. }
  384. }
  385. }
  386. mutex_unlock(&swrm->devlock);
  387. dev_dbg(swrm->dev, "%s: hw_clk_en: %d audio_core_clk_en: %d\n",
  388. __func__, swrm->hw_core_clk_en, swrm->aud_core_clk_en);
  389. trace_printk("%s: hw_clk_en: %d audio_core_clk_en: %d\n",
  390. __func__, swrm->hw_core_clk_en, swrm->aud_core_clk_en);
  391. return ret;
  392. }
  393. static int swrm_get_ssp_period(struct swr_mstr_ctrl *swrm,
  394. int row, int col,
  395. int frame_sync)
  396. {
  397. if (!swrm || !row || !col || !frame_sync)
  398. return 1;
  399. return ((swrm->bus_clk * 2) / ((row * col) * frame_sync));
  400. }
  401. static int swrm_core_vote_request(struct swr_mstr_ctrl *swrm, bool enable)
  402. {
  403. int ret = 0;
  404. if (!swrm->handle)
  405. return -EINVAL;
  406. mutex_lock(&swrm->clklock);
  407. if (!swrm->dev_up) {
  408. ret = -ENODEV;
  409. goto exit;
  410. }
  411. if (swrm->core_vote) {
  412. ret = swrm->core_vote(swrm->handle, enable);
  413. if (ret)
  414. dev_err_ratelimited(swrm->dev,
  415. "%s: core vote request failed\n", __func__);
  416. }
  417. exit:
  418. mutex_unlock(&swrm->clklock);
  419. return ret;
  420. }
  421. static int swrm_clk_request(struct swr_mstr_ctrl *swrm, bool enable)
  422. {
  423. int ret = 0;
  424. if (!swrm->clk || !swrm->handle)
  425. return -EINVAL;
  426. mutex_lock(&swrm->clklock);
  427. if (enable) {
  428. if (!swrm->dev_up) {
  429. ret = -ENODEV;
  430. goto exit;
  431. }
  432. if (is_swr_clk_needed(swrm)) {
  433. if (swrm->core_vote) {
  434. ret = swrm->core_vote(swrm->handle, true);
  435. if (ret) {
  436. dev_err_ratelimited(swrm->dev,
  437. "%s: core vote request failed\n",
  438. __func__);
  439. swrm->core_vote(swrm->handle, false);
  440. goto exit;
  441. }
  442. ret = swrm->core_vote(swrm->handle, false);
  443. }
  444. }
  445. swrm->clk_ref_count++;
  446. if (swrm->clk_ref_count == 1) {
  447. trace_printk("%s: clock enable count %d",
  448. __func__, swrm->clk_ref_count);
  449. ret = swrm->clk(swrm->handle, true);
  450. if (ret) {
  451. dev_err_ratelimited(swrm->dev,
  452. "%s: clock enable req failed",
  453. __func__);
  454. --swrm->clk_ref_count;
  455. }
  456. }
  457. } else if (--swrm->clk_ref_count == 0) {
  458. trace_printk("%s: clock disable count %d",
  459. __func__, swrm->clk_ref_count);
  460. swrm->clk(swrm->handle, false);
  461. complete(&swrm->clk_off_complete);
  462. }
  463. if (swrm->clk_ref_count < 0) {
  464. dev_err(swrm->dev, "%s: swrm clk count mismatch\n", __func__);
  465. swrm->clk_ref_count = 0;
  466. }
  467. exit:
  468. mutex_unlock(&swrm->clklock);
  469. return ret;
  470. }
  471. static int swrm_ahb_write(struct swr_mstr_ctrl *swrm,
  472. u16 reg, u32 *value)
  473. {
  474. u32 temp = (u32)(*value);
  475. int ret = 0;
  476. int vote_ret = 0;
  477. mutex_lock(&swrm->devlock);
  478. if (!swrm->dev_up)
  479. goto err;
  480. if (is_swr_clk_needed(swrm)) {
  481. ret = swrm_clk_request(swrm, TRUE);
  482. if (ret) {
  483. dev_err_ratelimited(swrm->dev,
  484. "%s: clock request failed\n",
  485. __func__);
  486. goto err;
  487. }
  488. } else {
  489. vote_ret = swrm_core_vote_request(swrm, true);
  490. if (vote_ret == -ENOTSYNC)
  491. goto err_vote;
  492. else if (vote_ret)
  493. goto err;
  494. }
  495. iowrite32(temp, swrm->swrm_dig_base + reg);
  496. if (is_swr_clk_needed(swrm))
  497. swrm_clk_request(swrm, FALSE);
  498. err_vote:
  499. if (!is_swr_clk_needed(swrm))
  500. swrm_core_vote_request(swrm, false);
  501. err:
  502. mutex_unlock(&swrm->devlock);
  503. return ret;
  504. }
  505. static int swrm_ahb_read(struct swr_mstr_ctrl *swrm,
  506. u16 reg, u32 *value)
  507. {
  508. u32 temp = 0;
  509. int ret = 0;
  510. int vote_ret = 0;
  511. mutex_lock(&swrm->devlock);
  512. if (!swrm->dev_up)
  513. goto err;
  514. if (is_swr_clk_needed(swrm)) {
  515. ret = swrm_clk_request(swrm, TRUE);
  516. if (ret) {
  517. dev_err_ratelimited(swrm->dev, "%s: clock request failed\n",
  518. __func__);
  519. goto err;
  520. }
  521. } else {
  522. vote_ret = swrm_core_vote_request(swrm, true);
  523. if (vote_ret == -ENOTSYNC)
  524. goto err_vote;
  525. else if (vote_ret)
  526. goto err;
  527. }
  528. temp = ioread32(swrm->swrm_dig_base + reg);
  529. *value = temp;
  530. if (is_swr_clk_needed(swrm))
  531. swrm_clk_request(swrm, FALSE);
  532. err_vote:
  533. if (!is_swr_clk_needed(swrm))
  534. swrm_core_vote_request(swrm, false);
  535. err:
  536. mutex_unlock(&swrm->devlock);
  537. return ret;
  538. }
  539. static u32 swr_master_read(struct swr_mstr_ctrl *swrm, unsigned int reg_addr)
  540. {
  541. u32 val = 0;
  542. if (swrm->read)
  543. val = swrm->read(swrm->handle, reg_addr);
  544. else
  545. swrm_ahb_read(swrm, reg_addr, &val);
  546. return val;
  547. }
  548. static void swr_master_write(struct swr_mstr_ctrl *swrm, u16 reg_addr, u32 val)
  549. {
  550. if (swrm->write)
  551. swrm->write(swrm->handle, reg_addr, val);
  552. else
  553. swrm_ahb_write(swrm, reg_addr, &val);
  554. }
  555. static int swr_master_bulk_write(struct swr_mstr_ctrl *swrm, u32 *reg_addr,
  556. u32 *val, unsigned int length)
  557. {
  558. int i = 0;
  559. if (swrm->bulk_write)
  560. swrm->bulk_write(swrm->handle, reg_addr, val, length);
  561. else {
  562. mutex_lock(&swrm->iolock);
  563. for (i = 0; i < length; i++) {
  564. /* wait for FIFO WR command to complete to avoid overflow */
  565. /*
  566. * Reduce sleep from 100us to 50us to meet KPIs
  567. * This still meets the hardware spec
  568. */
  569. usleep_range(50, 55);
  570. swr_master_write(swrm, reg_addr[i], val[i]);
  571. }
  572. usleep_range(100, 110);
  573. mutex_unlock(&swrm->iolock);
  574. }
  575. return 0;
  576. }
  577. static bool swrm_check_link_status(struct swr_mstr_ctrl *swrm, bool active)
  578. {
  579. int retry = SWRM_LINK_STATUS_RETRY_CNT;
  580. int ret = false;
  581. int status = active ? 0x1 : 0x0;
  582. int comp_sts = 0x0;
  583. if ((swrm->version <= SWRM_VERSION_1_5_1))
  584. return true;
  585. do {
  586. comp_sts = swr_master_read(swrm, SWRM_COMP_STATUS) & 0x01;
  587. /* check comp status and status requested met */
  588. if ((comp_sts && status) || (!comp_sts && !status)) {
  589. ret = true;
  590. break;
  591. }
  592. retry--;
  593. usleep_range(500, 510);
  594. } while (retry);
  595. if (retry == 0)
  596. dev_err(swrm->dev, "%s: link status not %s\n", __func__,
  597. active ? "connected" : "disconnected");
  598. return ret;
  599. }
  600. static bool swrm_is_port_en(struct swr_master *mstr)
  601. {
  602. return !!(mstr->num_port);
  603. }
  604. static void copy_port_tables(struct swr_mstr_ctrl *swrm,
  605. struct port_params *params)
  606. {
  607. u8 i;
  608. struct port_params *config = params;
  609. for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
  610. /* wsa uses single frame structure for all configurations */
  611. if (!swrm->mport_cfg[i].port_en)
  612. continue;
  613. swrm->mport_cfg[i].sinterval = config[i].si;
  614. swrm->mport_cfg[i].offset1 = config[i].off1;
  615. swrm->mport_cfg[i].offset2 = config[i].off2;
  616. swrm->mport_cfg[i].hstart = config[i].hstart;
  617. swrm->mport_cfg[i].hstop = config[i].hstop;
  618. swrm->mport_cfg[i].blk_pack_mode = config[i].bp_mode;
  619. swrm->mport_cfg[i].blk_grp_count = config[i].bgp_ctrl;
  620. swrm->mport_cfg[i].word_length = config[i].wd_len;
  621. swrm->mport_cfg[i].lane_ctrl = config[i].lane_ctrl;
  622. swrm->mport_cfg[i].dir = config[i].dir;
  623. swrm->mport_cfg[i].stream_type = config[i].stream_type;
  624. }
  625. }
  626. static int swrm_get_port_config(struct swr_mstr_ctrl *swrm)
  627. {
  628. struct port_params *params;
  629. u32 usecase = 0;
  630. if (swrm->master_id == MASTER_ID_TX)
  631. return 0;
  632. /* TODO - Send usecase information to avoid checking for master_id */
  633. if (swrm->mport_cfg[SWRM_DSD_PARAMS_PORT].port_en &&
  634. (swrm->master_id == MASTER_ID_RX))
  635. usecase = 1;
  636. else if ((swrm->master_id == MASTER_ID_RX) &&
  637. (swrm->bus_clk == SWR_CLK_RATE_11P2896MHZ))
  638. usecase = 2;
  639. params = swrm->port_param[usecase];
  640. copy_port_tables(swrm, params);
  641. return 0;
  642. }
  643. static int swrm_pcm_port_config(struct swr_mstr_ctrl *swrm, u8 port_num,
  644. u8 stream_type, bool dir, bool enable)
  645. {
  646. u16 reg_addr = 0;
  647. u32 reg_val = SWRM_COMP_FEATURE_CFG_DEFAULT_VAL;
  648. if (!port_num || port_num > SWR_MSTR_PORT_LEN) {
  649. dev_err(swrm->dev, "%s: invalid port: %d\n",
  650. __func__, port_num);
  651. return -EINVAL;
  652. }
  653. switch (stream_type) {
  654. case SWR_PCM:
  655. reg_addr = ((dir) ? SWRM_DIN_DP_PCM_PORT_CTRL(port_num) : \
  656. SWRM_DOUT_DP_PCM_PORT_CTRL(port_num));
  657. swr_master_write(swrm, reg_addr, enable);
  658. break;
  659. case SWR_PDM_32:
  660. break;
  661. case SWR_PDM:
  662. default:
  663. return 0;
  664. }
  665. if (swrm->version >= SWRM_VERSION_1_7)
  666. reg_val = SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V1P7;
  667. if (enable)
  668. reg_val |= SWRM_COMP_FEATURE_CFG_PCM_EN_MASK;
  669. swr_master_write(swrm, SWRM_COMP_FEATURE_CFG, reg_val);
  670. return 0;
  671. }
  672. static int swrm_get_master_port(struct swr_mstr_ctrl *swrm, u8 *mstr_port_id,
  673. u8 *mstr_ch_mask, u8 mstr_prt_type,
  674. u8 slv_port_id)
  675. {
  676. int i, j;
  677. *mstr_port_id = 0;
  678. for (i = 1; i <= swrm->num_ports; i++) {
  679. for (j = 0; j < SWR_MAX_CH_PER_PORT; j++) {
  680. if (swrm->port_mapping[i][j].port_type == mstr_prt_type)
  681. goto found;
  682. }
  683. }
  684. found:
  685. if (i > swrm->num_ports || j == SWR_MAX_CH_PER_PORT) {
  686. dev_err(swrm->dev, "%s: port type not supported by master\n",
  687. __func__);
  688. return -EINVAL;
  689. }
  690. /* id 0 corresponds to master port 1 */
  691. *mstr_port_id = i - 1;
  692. *mstr_ch_mask = swrm->port_mapping[i][j].ch_mask;
  693. return 0;
  694. }
  695. static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
  696. u8 dev_addr, u16 reg_addr)
  697. {
  698. u32 val;
  699. u8 id = *cmd_id;
  700. if (id != SWR_BROADCAST_CMD_ID) {
  701. if (id < 14)
  702. id += 1;
  703. else
  704. id = 0;
  705. *cmd_id = id;
  706. }
  707. val = SWR_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
  708. return val;
  709. }
  710. static void swrm_wait_for_fifo_avail(struct swr_mstr_ctrl *swrm, int swrm_rd_wr)
  711. {
  712. u32 fifo_outstanding_cmd;
  713. u32 fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
  714. if (swrm_rd_wr) {
  715. /* Check for fifo underflow during read */
  716. /* Check no of outstanding commands in fifo before read */
  717. fifo_outstanding_cmd = ((swr_master_read(swrm,
  718. SWRM_CMD_FIFO_STATUS) & 0x001F0000) >> 16);
  719. if (fifo_outstanding_cmd == 0) {
  720. while (fifo_retry_count) {
  721. usleep_range(500, 510);
  722. fifo_outstanding_cmd =
  723. ((swr_master_read (swrm,
  724. SWRM_CMD_FIFO_STATUS) & 0x001F0000)
  725. >> 16);
  726. fifo_retry_count--;
  727. if (fifo_outstanding_cmd > 0)
  728. break;
  729. }
  730. }
  731. if (fifo_outstanding_cmd == 0)
  732. dev_err_ratelimited(swrm->dev,
  733. "%s err read underflow\n", __func__);
  734. } else {
  735. /* Check for fifo overflow during write */
  736. /* Check no of outstanding commands in fifo before write */
  737. fifo_outstanding_cmd = ((swr_master_read(swrm,
  738. SWRM_CMD_FIFO_STATUS) & 0x00001F00)
  739. >> 8);
  740. if (fifo_outstanding_cmd == swrm->wr_fifo_depth) {
  741. while (fifo_retry_count) {
  742. usleep_range(500, 510);
  743. fifo_outstanding_cmd =
  744. ((swr_master_read(swrm, SWRM_CMD_FIFO_STATUS)
  745. & 0x00001F00) >> 8);
  746. fifo_retry_count--;
  747. if (fifo_outstanding_cmd < swrm->wr_fifo_depth)
  748. break;
  749. }
  750. }
  751. if (fifo_outstanding_cmd == swrm->wr_fifo_depth)
  752. dev_err_ratelimited(swrm->dev,
  753. "%s err write overflow\n", __func__);
  754. }
  755. }
  756. static int swrm_cmd_fifo_rd_cmd(struct swr_mstr_ctrl *swrm, int *cmd_data,
  757. u8 dev_addr, u8 cmd_id, u16 reg_addr,
  758. u32 len)
  759. {
  760. u32 val;
  761. u32 retry_attempt = 0;
  762. mutex_lock(&swrm->iolock);
  763. val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
  764. if (swrm->read) {
  765. /* skip delay if read is handled in platform driver */
  766. swr_master_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
  767. } else {
  768. /*
  769. * Check for outstanding cmd wrt. write fifo depth to avoid
  770. * overflow as read will also increase write fifo cnt.
  771. */
  772. swrm_wait_for_fifo_avail(swrm, SWRM_WR_CHECK_AVAIL);
  773. /* wait for FIFO RD to complete to avoid overflow */
  774. usleep_range(100, 105);
  775. swr_master_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
  776. /* wait for FIFO RD CMD complete to avoid overflow */
  777. usleep_range(250, 255);
  778. }
  779. /* Check if slave responds properly after FIFO RD is complete */
  780. swrm_wait_for_fifo_avail(swrm, SWRM_RD_CHECK_AVAIL);
  781. retry_read:
  782. *cmd_data = swr_master_read(swrm, SWRM_CMD_FIFO_RD_FIFO);
  783. dev_dbg(swrm->dev, "%s: reg: 0x%x, cmd_id: 0x%x, rcmd_id: 0x%x, \
  784. dev_num: 0x%x, cmd_data: 0x%x\n", __func__, reg_addr,
  785. cmd_id, swrm->rcmd_id, dev_addr, *cmd_data);
  786. if ((((*cmd_data) & 0xF00) >> 8) != swrm->rcmd_id) {
  787. if (retry_attempt < MAX_FIFO_RD_FAIL_RETRY) {
  788. /* wait 500 us before retry on fifo read failure */
  789. usleep_range(500, 505);
  790. if (retry_attempt == (MAX_FIFO_RD_FAIL_RETRY - 1)) {
  791. swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
  792. swr_master_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
  793. }
  794. retry_attempt++;
  795. goto retry_read;
  796. } else {
  797. dev_err_ratelimited(swrm->dev, "%s: reg: 0x%x, cmd_id: 0x%x, \
  798. rcmd_id: 0x%x, dev_num: 0x%x, cmd_data: 0x%x\n",
  799. __func__, reg_addr, cmd_id, swrm->rcmd_id,
  800. dev_addr, *cmd_data);
  801. dev_err_ratelimited(swrm->dev,
  802. "%s: failed to read fifo\n", __func__);
  803. }
  804. }
  805. mutex_unlock(&swrm->iolock);
  806. return 0;
  807. }
  808. static int swrm_cmd_fifo_wr_cmd(struct swr_mstr_ctrl *swrm, u8 cmd_data,
  809. u8 dev_addr, u8 cmd_id, u16 reg_addr)
  810. {
  811. u32 val;
  812. int ret = 0;
  813. mutex_lock(&swrm->iolock);
  814. if (!cmd_id)
  815. val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
  816. dev_addr, reg_addr);
  817. else
  818. val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
  819. dev_addr, reg_addr);
  820. dev_dbg(swrm->dev, "%s: reg: 0x%x, cmd_id: 0x%x,wcmd_id: 0x%x, \
  821. dev_num: 0x%x, cmd_data: 0x%x\n", __func__,
  822. reg_addr, cmd_id, swrm->wcmd_id,dev_addr, cmd_data);
  823. /*
  824. * Check for outstanding cmd wrt. write fifo depth to avoid
  825. * overflow.
  826. */
  827. swrm_wait_for_fifo_avail(swrm, SWRM_WR_CHECK_AVAIL);
  828. swr_master_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
  829. /*
  830. * wait for FIFO WR command to complete to avoid overflow
  831. * skip delay if write is handled in platform driver.
  832. */
  833. if(!swrm->write)
  834. usleep_range(150, 155);
  835. if (cmd_id == 0xF) {
  836. /*
  837. * sleep for 10ms for MSM soundwire variant to allow broadcast
  838. * command to complete.
  839. */
  840. if (swrm_is_msm_variant(swrm->version))
  841. usleep_range(10000, 10100);
  842. else
  843. wait_for_completion_timeout(&swrm->broadcast,
  844. (2 * HZ/10));
  845. }
  846. mutex_unlock(&swrm->iolock);
  847. return ret;
  848. }
  849. static int swrm_read(struct swr_master *master, u8 dev_num, u16 reg_addr,
  850. void *buf, u32 len)
  851. {
  852. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  853. int ret = 0;
  854. int val;
  855. u8 *reg_val = (u8 *)buf;
  856. if (!swrm) {
  857. dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
  858. return -EINVAL;
  859. }
  860. if (!dev_num) {
  861. dev_err(&master->dev, "%s: invalid slave dev num\n", __func__);
  862. return -EINVAL;
  863. }
  864. mutex_lock(&swrm->devlock);
  865. if (!swrm->dev_up) {
  866. mutex_unlock(&swrm->devlock);
  867. return 0;
  868. }
  869. mutex_unlock(&swrm->devlock);
  870. pm_runtime_get_sync(swrm->dev);
  871. if (swrm->req_clk_switch)
  872. swrm_runtime_resume(swrm->dev);
  873. ret = swrm_cmd_fifo_rd_cmd(swrm, &val, dev_num, 0, reg_addr, len);
  874. if (!ret)
  875. *reg_val = (u8)val;
  876. pm_runtime_put_autosuspend(swrm->dev);
  877. pm_runtime_mark_last_busy(swrm->dev);
  878. return ret;
  879. }
  880. static int swrm_write(struct swr_master *master, u8 dev_num, u16 reg_addr,
  881. const void *buf)
  882. {
  883. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  884. int ret = 0;
  885. u8 reg_val = *(u8 *)buf;
  886. if (!swrm) {
  887. dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
  888. return -EINVAL;
  889. }
  890. if (!dev_num) {
  891. dev_err(&master->dev, "%s: invalid slave dev num\n", __func__);
  892. return -EINVAL;
  893. }
  894. mutex_lock(&swrm->devlock);
  895. if (!swrm->dev_up) {
  896. mutex_unlock(&swrm->devlock);
  897. return 0;
  898. }
  899. mutex_unlock(&swrm->devlock);
  900. pm_runtime_get_sync(swrm->dev);
  901. if (swrm->req_clk_switch)
  902. swrm_runtime_resume(swrm->dev);
  903. ret = swrm_cmd_fifo_wr_cmd(swrm, reg_val, dev_num, 0, reg_addr);
  904. pm_runtime_put_autosuspend(swrm->dev);
  905. pm_runtime_mark_last_busy(swrm->dev);
  906. return ret;
  907. }
  908. static int swrm_bulk_write(struct swr_master *master, u8 dev_num, void *reg,
  909. const void *buf, size_t len)
  910. {
  911. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  912. int ret = 0;
  913. int i;
  914. u32 *val;
  915. u32 *swr_fifo_reg;
  916. if (!swrm || !swrm->handle) {
  917. dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
  918. return -EINVAL;
  919. }
  920. if (len <= 0)
  921. return -EINVAL;
  922. mutex_lock(&swrm->devlock);
  923. if (!swrm->dev_up) {
  924. mutex_unlock(&swrm->devlock);
  925. return 0;
  926. }
  927. mutex_unlock(&swrm->devlock);
  928. pm_runtime_get_sync(swrm->dev);
  929. if (dev_num) {
  930. swr_fifo_reg = kcalloc(len, sizeof(u32), GFP_KERNEL);
  931. if (!swr_fifo_reg) {
  932. ret = -ENOMEM;
  933. goto err;
  934. }
  935. val = kcalloc(len, sizeof(u32), GFP_KERNEL);
  936. if (!val) {
  937. ret = -ENOMEM;
  938. goto mem_fail;
  939. }
  940. for (i = 0; i < len; i++) {
  941. val[i] = swrm_get_packed_reg_val(&swrm->wcmd_id,
  942. ((u8 *)buf)[i],
  943. dev_num,
  944. ((u16 *)reg)[i]);
  945. swr_fifo_reg[i] = SWRM_CMD_FIFO_WR_CMD;
  946. }
  947. ret = swr_master_bulk_write(swrm, swr_fifo_reg, val, len);
  948. if (ret) {
  949. dev_err(&master->dev, "%s: bulk write failed\n",
  950. __func__);
  951. ret = -EINVAL;
  952. }
  953. } else {
  954. dev_err(&master->dev,
  955. "%s: No support of Bulk write for master regs\n",
  956. __func__);
  957. ret = -EINVAL;
  958. goto err;
  959. }
  960. kfree(val);
  961. mem_fail:
  962. kfree(swr_fifo_reg);
  963. err:
  964. pm_runtime_put_autosuspend(swrm->dev);
  965. pm_runtime_mark_last_busy(swrm->dev);
  966. return ret;
  967. }
  968. static u8 get_inactive_bank_num(struct swr_mstr_ctrl *swrm)
  969. {
  970. return (swr_master_read(swrm, SWRM_MCP_STATUS) & 0x01) ? 0 : 1;
  971. }
  972. static void enable_bank_switch(struct swr_mstr_ctrl *swrm, u8 bank,
  973. u8 row, u8 col)
  974. {
  975. swrm_cmd_fifo_wr_cmd(swrm, ((row << 3) | col), 0xF, 0xF,
  976. SWRS_SCP_FRAME_CTRL_BANK(bank));
  977. }
  978. static void swrm_switch_frame_shape(struct swr_mstr_ctrl *swrm, int mclk_freq)
  979. {
  980. u8 bank;
  981. u32 n_row, n_col;
  982. u32 value = 0;
  983. u32 row = 0, col = 0;
  984. u8 ssp_period = 0;
  985. int frame_sync = SWRM_FRAME_SYNC_SEL;
  986. if (mclk_freq == MCLK_FREQ_NATIVE) {
  987. n_col = SWR_MAX_COL;
  988. col = SWRM_COL_16;
  989. n_row = SWR_ROW_64;
  990. row = SWRM_ROW_64;
  991. frame_sync = SWRM_FRAME_SYNC_SEL_NATIVE;
  992. } else {
  993. n_col = SWR_MIN_COL;
  994. col = SWRM_COL_02;
  995. n_row = SWR_ROW_50;
  996. row = SWRM_ROW_50;
  997. frame_sync = SWRM_FRAME_SYNC_SEL;
  998. }
  999. bank = get_inactive_bank_num(swrm);
  1000. ssp_period = swrm_get_ssp_period(swrm, row, col, frame_sync);
  1001. dev_dbg(swrm->dev, "%s: ssp_period: %d\n", __func__, ssp_period);
  1002. value = ((n_row << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) |
  1003. (n_col << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) |
  1004. ((ssp_period - 1) << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT));
  1005. swr_master_write(swrm, SWRM_MCP_FRAME_CTRL_BANK(bank), value);
  1006. enable_bank_switch(swrm, bank, n_row, n_col);
  1007. }
  1008. static struct swr_port_info *swrm_get_port_req(struct swrm_mports *mport,
  1009. u8 slv_port, u8 dev_num)
  1010. {
  1011. struct swr_port_info *port_req = NULL;
  1012. list_for_each_entry(port_req, &mport->port_req_list, list) {
  1013. /* Store dev_id instead of dev_num if enumeration is changed run_time */
  1014. if ((port_req->slave_port_id == slv_port)
  1015. && (port_req->dev_num == dev_num))
  1016. return port_req;
  1017. }
  1018. return NULL;
  1019. }
  1020. static bool swrm_remove_from_group(struct swr_master *master)
  1021. {
  1022. struct swr_device *swr_dev;
  1023. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1024. bool is_removed = false;
  1025. if (!swrm)
  1026. goto end;
  1027. mutex_lock(&swrm->mlock);
  1028. if (swrm->num_rx_chs > 1) {
  1029. list_for_each_entry(swr_dev, &master->devices,
  1030. dev_list) {
  1031. swr_dev->group_id = SWR_GROUP_NONE;
  1032. master->gr_sid = 0;
  1033. }
  1034. is_removed = true;
  1035. }
  1036. mutex_unlock(&swrm->mlock);
  1037. end:
  1038. return is_removed;
  1039. }
  1040. int swrm_get_clk_div_rate(int mclk_freq, int bus_clk_freq)
  1041. {
  1042. if (!bus_clk_freq)
  1043. return mclk_freq;
  1044. if (mclk_freq == SWR_CLK_RATE_9P6MHZ) {
  1045. if (bus_clk_freq <= SWR_CLK_RATE_0P6MHZ)
  1046. bus_clk_freq = SWR_CLK_RATE_0P6MHZ;
  1047. else if (bus_clk_freq <= SWR_CLK_RATE_1P2MHZ)
  1048. bus_clk_freq = SWR_CLK_RATE_4P8MHZ;
  1049. else if (bus_clk_freq <= SWR_CLK_RATE_2P4MHZ)
  1050. bus_clk_freq = SWR_CLK_RATE_4P8MHZ;
  1051. else if(bus_clk_freq <= SWR_CLK_RATE_4P8MHZ)
  1052. bus_clk_freq = SWR_CLK_RATE_4P8MHZ;
  1053. else if(bus_clk_freq <= SWR_CLK_RATE_9P6MHZ)
  1054. bus_clk_freq = SWR_CLK_RATE_9P6MHZ;
  1055. else
  1056. bus_clk_freq = SWR_CLK_RATE_9P6MHZ;
  1057. } else if (mclk_freq == SWR_CLK_RATE_11P2896MHZ)
  1058. bus_clk_freq = SWR_CLK_RATE_11P2896MHZ;
  1059. return bus_clk_freq;
  1060. }
  1061. static int swrm_update_bus_clk(struct swr_mstr_ctrl *swrm)
  1062. {
  1063. int ret = 0;
  1064. int agg_clk = 0;
  1065. int i;
  1066. for (i = 0; i < SWR_MSTR_PORT_LEN; i++)
  1067. agg_clk += swrm->mport_cfg[i].ch_rate;
  1068. if (agg_clk)
  1069. swrm->bus_clk = swrm_get_clk_div_rate(swrm->mclk_freq,
  1070. agg_clk);
  1071. else
  1072. swrm->bus_clk = swrm->mclk_freq;
  1073. dev_dbg(swrm->dev, "%s: all_port_clk: %d, bus_clk: %d\n",
  1074. __func__, agg_clk, swrm->bus_clk);
  1075. return ret;
  1076. }
  1077. static void swrm_disable_ports(struct swr_master *master,
  1078. u8 bank)
  1079. {
  1080. u32 value;
  1081. struct swr_port_info *port_req;
  1082. int i;
  1083. struct swrm_mports *mport;
  1084. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1085. if (!swrm) {
  1086. pr_err("%s: swrm is null\n", __func__);
  1087. return;
  1088. }
  1089. dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__,
  1090. master->num_port);
  1091. for (i = 0; i < SWR_MSTR_PORT_LEN ; i++) {
  1092. mport = &(swrm->mport_cfg[i]);
  1093. if (!mport->port_en)
  1094. continue;
  1095. list_for_each_entry(port_req, &mport->port_req_list, list) {
  1096. /* skip ports with no change req's*/
  1097. if (port_req->req_ch == port_req->ch_en)
  1098. continue;
  1099. swrm_cmd_fifo_wr_cmd(swrm, port_req->req_ch,
  1100. port_req->dev_num, 0x00,
  1101. SWRS_DP_CHANNEL_ENABLE_BANK(port_req->slave_port_id,
  1102. bank));
  1103. dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x\n",
  1104. __func__, i,
  1105. (SWRM_DP_PORT_CTRL_BANK((i + 1), bank)));
  1106. }
  1107. value = ((mport->req_ch)
  1108. << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
  1109. value |= ((mport->offset2)
  1110. << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
  1111. value |= ((mport->offset1)
  1112. << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
  1113. value |= mport->sinterval;
  1114. swr_master_write(swrm,
  1115. SWRM_DP_PORT_CTRL_BANK((i + 1), bank),
  1116. value);
  1117. dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x, val: 0x%x\n",
  1118. __func__, i,
  1119. (SWRM_DP_PORT_CTRL_BANK((i + 1), bank)), value);
  1120. swrm_pcm_port_config(swrm, (i + 1),
  1121. mport->stream_type, mport->dir, false);
  1122. }
  1123. }
  1124. static void swrm_cleanup_disabled_port_reqs(struct swr_master *master)
  1125. {
  1126. struct swr_port_info *port_req, *next;
  1127. int i;
  1128. struct swrm_mports *mport;
  1129. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1130. if (!swrm) {
  1131. pr_err("%s: swrm is null\n", __func__);
  1132. return;
  1133. }
  1134. dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__,
  1135. master->num_port);
  1136. for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
  1137. mport = &(swrm->mport_cfg[i]);
  1138. list_for_each_entry_safe(port_req, next,
  1139. &mport->port_req_list, list) {
  1140. /* skip ports without new ch req */
  1141. if (port_req->ch_en == port_req->req_ch)
  1142. continue;
  1143. /* remove new ch req's*/
  1144. port_req->ch_en = port_req->req_ch;
  1145. /* If no streams enabled on port, remove the port req */
  1146. if (port_req->ch_en == 0) {
  1147. list_del(&port_req->list);
  1148. kfree(port_req);
  1149. }
  1150. }
  1151. /* remove new ch req's on mport*/
  1152. mport->ch_en = mport->req_ch;
  1153. if (!(mport->ch_en)) {
  1154. mport->port_en = false;
  1155. master->port_en_mask &= ~i;
  1156. }
  1157. }
  1158. }
  1159. static u8 swrm_get_controller_offset1(struct swr_mstr_ctrl *swrm,
  1160. u8* dev_offset, u8 off1)
  1161. {
  1162. u8 offset1 = 0x0F;
  1163. int i = 0;
  1164. if (swrm->master_id == MASTER_ID_TX) {
  1165. for (i = 1; i < SWRM_NUM_AUTO_ENUM_SLAVES; i++) {
  1166. pr_debug("%s: dev offset: %d\n",
  1167. __func__, dev_offset[i]);
  1168. if (offset1 > dev_offset[i])
  1169. offset1 = dev_offset[i];
  1170. }
  1171. } else {
  1172. offset1 = off1;
  1173. }
  1174. pr_debug("%s: offset: %d\n", __func__, offset1);
  1175. return offset1;
  1176. }
  1177. static int swrm_get_uc(int bus_clk)
  1178. {
  1179. switch (bus_clk) {
  1180. case SWR_CLK_RATE_4P8MHZ:
  1181. return SWR_UC1;
  1182. case SWR_CLK_RATE_1P2MHZ:
  1183. return SWR_UC2;
  1184. case SWR_CLK_RATE_0P6MHZ:
  1185. return SWR_UC3;
  1186. case SWR_CLK_RATE_9P6MHZ:
  1187. default:
  1188. return SWR_UC0;
  1189. }
  1190. return SWR_UC0;
  1191. }
  1192. static void swrm_get_device_frame_shape(struct swr_mstr_ctrl *swrm,
  1193. struct swrm_mports *mport,
  1194. struct swr_port_info *port_req)
  1195. {
  1196. u32 uc = SWR_UC0;
  1197. u32 port_id_offset = 0;
  1198. if (swrm->master_id == MASTER_ID_TX) {
  1199. uc = swrm_get_uc(swrm->bus_clk);
  1200. port_id_offset = (port_req->dev_num - 1) *
  1201. SWR_MAX_DEV_PORT_NUM +
  1202. port_req->slave_port_id;
  1203. port_req->sinterval =
  1204. ((swrm->bus_clk * 2) / port_req->ch_rate) - 1;
  1205. port_req->offset1 = swrm->pp[uc][port_id_offset].offset1;
  1206. port_req->offset2 = 0x00;
  1207. port_req->hstart = 0xFF;
  1208. port_req->hstop = 0xFF;
  1209. port_req->word_length = 0xFF;
  1210. port_req->blk_pack_mode = 0xFF;
  1211. port_req->blk_grp_count = 0xFF;
  1212. port_req->lane_ctrl = swrm->pp[uc][port_id_offset].lane_ctrl;
  1213. } else {
  1214. /* copy master port config to slave */
  1215. port_req->sinterval = mport->sinterval;
  1216. port_req->offset1 = mport->offset1;
  1217. port_req->offset2 = mport->offset2;
  1218. port_req->hstart = mport->hstart;
  1219. port_req->hstop = mport->hstop;
  1220. port_req->word_length = mport->word_length;
  1221. port_req->blk_pack_mode = mport->blk_pack_mode;
  1222. port_req->blk_grp_count = mport->blk_grp_count;
  1223. port_req->lane_ctrl = mport->lane_ctrl;
  1224. }
  1225. }
  1226. static void swrm_copy_data_port_config(struct swr_master *master, u8 bank)
  1227. {
  1228. u32 value = 0, slv_id = 0;
  1229. struct swr_port_info *port_req;
  1230. int i, j;
  1231. u16 sinterval = 0xFFFF;
  1232. u8 lane_ctrl = 0;
  1233. struct swrm_mports *mport;
  1234. u32 reg[SWRM_MAX_PORT_REG];
  1235. u32 val[SWRM_MAX_PORT_REG];
  1236. int len = 0;
  1237. u8 hparams = 0;
  1238. u32 controller_offset = 0;
  1239. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1240. u8 dev_offset[SWRM_NUM_AUTO_ENUM_SLAVES];
  1241. if (!swrm) {
  1242. pr_err("%s: swrm is null\n", __func__);
  1243. return;
  1244. }
  1245. memset(dev_offset, 0xff, SWRM_NUM_AUTO_ENUM_SLAVES);
  1246. dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__,
  1247. master->num_port);
  1248. for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
  1249. mport = &(swrm->mport_cfg[i]);
  1250. if (!mport->port_en)
  1251. continue;
  1252. swrm_pcm_port_config(swrm, (i + 1),
  1253. mport->stream_type, mport->dir, true);
  1254. j = 0;
  1255. lane_ctrl = 0;
  1256. sinterval = 0xFFFF;
  1257. list_for_each_entry(port_req, &mport->port_req_list, list) {
  1258. j++;
  1259. slv_id = port_req->slave_port_id;
  1260. /* Assumption: If different channels in the same port
  1261. * on master is enabled for different slaves, then each
  1262. * slave offset should be configured differently.
  1263. */
  1264. swrm_get_device_frame_shape(swrm, mport, port_req);
  1265. if (j == 1) {
  1266. sinterval = port_req->sinterval;
  1267. lane_ctrl = port_req->lane_ctrl;
  1268. } else if (sinterval != port_req->sinterval ||
  1269. lane_ctrl != port_req->lane_ctrl) {
  1270. dev_err(swrm->dev,
  1271. "%s:slaves/slave ports attaching to mport%d"\
  1272. " are not using same SI or data lane, update slave tables,"\
  1273. "bailing out without setting port config\n",
  1274. __func__, i);
  1275. return;
  1276. }
  1277. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1278. val[len++] = SWR_REG_VAL_PACK(port_req->req_ch,
  1279. port_req->dev_num, 0x00,
  1280. SWRS_DP_CHANNEL_ENABLE_BANK(slv_id,
  1281. bank));
  1282. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1283. val[len++] = SWR_REG_VAL_PACK(
  1284. port_req->sinterval & 0xFF,
  1285. port_req->dev_num, 0x00,
  1286. SWRS_DP_SAMPLE_CONTROL_1_BANK(slv_id,
  1287. bank));
  1288. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1289. val[len++] = SWR_REG_VAL_PACK(
  1290. (port_req->sinterval >> 8)& 0xFF,
  1291. port_req->dev_num, 0x00,
  1292. SWRS_DP_SAMPLE_CONTROL_2_BANK(slv_id,
  1293. bank));
  1294. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1295. val[len++] = SWR_REG_VAL_PACK(port_req->offset1,
  1296. port_req->dev_num, 0x00,
  1297. SWRS_DP_OFFSET_CONTROL_1_BANK(slv_id,
  1298. bank));
  1299. if (port_req->offset2 != SWR_INVALID_PARAM) {
  1300. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1301. val[len++] = SWR_REG_VAL_PACK(port_req->offset2,
  1302. port_req->dev_num, 0x00,
  1303. SWRS_DP_OFFSET_CONTROL_2_BANK(
  1304. slv_id, bank));
  1305. }
  1306. if (port_req->hstart != SWR_INVALID_PARAM
  1307. && port_req->hstop != SWR_INVALID_PARAM) {
  1308. hparams = (port_req->hstart << 4) |
  1309. port_req->hstop;
  1310. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1311. val[len++] = SWR_REG_VAL_PACK(hparams,
  1312. port_req->dev_num, 0x00,
  1313. SWRS_DP_HCONTROL_BANK(slv_id,
  1314. bank));
  1315. }
  1316. if (port_req->word_length != SWR_INVALID_PARAM) {
  1317. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1318. val[len++] =
  1319. SWR_REG_VAL_PACK(port_req->word_length,
  1320. port_req->dev_num, 0x00,
  1321. SWRS_DP_BLOCK_CONTROL_1(slv_id));
  1322. }
  1323. if (port_req->blk_pack_mode != SWR_INVALID_PARAM
  1324. && swrm->master_id != MASTER_ID_WSA) {
  1325. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1326. val[len++] =
  1327. SWR_REG_VAL_PACK(
  1328. port_req->blk_pack_mode,
  1329. port_req->dev_num, 0x00,
  1330. SWRS_DP_BLOCK_CONTROL_3_BANK(slv_id,
  1331. bank));
  1332. }
  1333. if (port_req->blk_grp_count != SWR_INVALID_PARAM) {
  1334. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1335. val[len++] =
  1336. SWR_REG_VAL_PACK(
  1337. port_req->blk_grp_count,
  1338. port_req->dev_num, 0x00,
  1339. SWRS_DP_BLOCK_CONTROL_2_BANK(
  1340. slv_id, bank));
  1341. }
  1342. if (port_req->lane_ctrl != SWR_INVALID_PARAM) {
  1343. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1344. val[len++] =
  1345. SWR_REG_VAL_PACK(port_req->lane_ctrl,
  1346. port_req->dev_num, 0x00,
  1347. SWRS_DP_LANE_CONTROL_BANK(
  1348. slv_id, bank));
  1349. }
  1350. port_req->ch_en = port_req->req_ch;
  1351. dev_offset[port_req->dev_num] = port_req->offset1;
  1352. }
  1353. if (swrm->master_id == MASTER_ID_TX) {
  1354. mport->sinterval = sinterval;
  1355. mport->lane_ctrl = lane_ctrl;
  1356. }
  1357. value = ((mport->req_ch)
  1358. << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
  1359. if (mport->offset2 != SWR_INVALID_PARAM)
  1360. value |= ((mport->offset2)
  1361. << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
  1362. controller_offset = (swrm_get_controller_offset1(swrm,
  1363. dev_offset, mport->offset1));
  1364. value |= (controller_offset << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
  1365. mport->offset1 = controller_offset;
  1366. value |= (mport->sinterval & 0xFF);
  1367. reg[len] = SWRM_DP_PORT_CTRL_BANK((i + 1), bank);
  1368. val[len++] = value;
  1369. dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x, val: 0x%x\n",
  1370. __func__, (i + 1),
  1371. (SWRM_DP_PORT_CTRL_BANK((i + 1), bank)), value);
  1372. reg[len] = SWRM_DP_SAMPLECTRL2_BANK((i + 1), bank);
  1373. val[len++] = ((mport->sinterval >> 8) & 0xFF);
  1374. if (mport->lane_ctrl != SWR_INVALID_PARAM) {
  1375. reg[len] = SWRM_DP_PORT_CTRL_2_BANK((i + 1), bank);
  1376. val[len++] = mport->lane_ctrl;
  1377. }
  1378. if (mport->word_length != SWR_INVALID_PARAM) {
  1379. reg[len] = SWRM_DP_BLOCK_CTRL_1((i + 1));
  1380. val[len++] = mport->word_length;
  1381. }
  1382. if (mport->blk_grp_count != SWR_INVALID_PARAM) {
  1383. reg[len] = SWRM_DP_BLOCK_CTRL2_BANK((i + 1), bank);
  1384. val[len++] = mport->blk_grp_count;
  1385. }
  1386. if (mport->hstart != SWR_INVALID_PARAM
  1387. && mport->hstop != SWR_INVALID_PARAM) {
  1388. reg[len] = SWRM_DP_PORT_HCTRL_BANK((i + 1), bank);
  1389. hparams = (mport->hstop << 4) | mport->hstart;
  1390. val[len++] = hparams;
  1391. } else {
  1392. reg[len] = SWRM_DP_PORT_HCTRL_BANK((i + 1), bank);
  1393. hparams = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
  1394. val[len++] = hparams;
  1395. }
  1396. if (mport->blk_pack_mode != SWR_INVALID_PARAM) {
  1397. reg[len] = SWRM_DP_BLOCK_CTRL3_BANK((i + 1), bank);
  1398. val[len++] = mport->blk_pack_mode;
  1399. }
  1400. mport->ch_en = mport->req_ch;
  1401. }
  1402. swrm_reg_dump(swrm, reg, val, len, __func__);
  1403. swr_master_bulk_write(swrm, reg, val, len);
  1404. }
  1405. static void swrm_apply_port_config(struct swr_master *master)
  1406. {
  1407. u8 bank;
  1408. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1409. if (!swrm) {
  1410. pr_err("%s: Invalid handle to swr controller\n",
  1411. __func__);
  1412. return;
  1413. }
  1414. bank = get_inactive_bank_num(swrm);
  1415. dev_dbg(swrm->dev, "%s: enter bank: %d master_ports: %d\n",
  1416. __func__, bank, master->num_port);
  1417. if (!swrm->disable_div2_clk_switch)
  1418. swrm_cmd_fifo_wr_cmd(swrm, 0x01, 0xF, 0x00,
  1419. SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank));
  1420. swrm_copy_data_port_config(master, bank);
  1421. }
  1422. static int swrm_slvdev_datapath_control(struct swr_master *master, bool enable)
  1423. {
  1424. u8 bank;
  1425. u32 value = 0, n_row = 0, n_col = 0;
  1426. u32 row = 0, col = 0;
  1427. int bus_clk_div_factor;
  1428. int ret;
  1429. u8 ssp_period = 0;
  1430. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1431. int mask = (SWRM_ROW_CTRL_MASK | SWRM_COL_CTRL_MASK |
  1432. SWRM_CLK_DIV_MASK | SWRM_SSP_PERIOD_MASK);
  1433. u8 inactive_bank;
  1434. int frame_sync = SWRM_FRAME_SYNC_SEL;
  1435. if (!swrm) {
  1436. pr_err("%s: swrm is null\n", __func__);
  1437. return -EFAULT;
  1438. }
  1439. mutex_lock(&swrm->mlock);
  1440. /*
  1441. * During disable if master is already down, which implies an ssr/pdr
  1442. * scenario, just mark ports as disabled and exit
  1443. */
  1444. if (swrm->state == SWR_MSTR_SSR && !enable) {
  1445. if (!test_bit(DISABLE_PENDING, &swrm->port_req_pending)) {
  1446. dev_dbg(swrm->dev, "%s:No pending disconn port req\n",
  1447. __func__);
  1448. goto exit;
  1449. }
  1450. clear_bit(DISABLE_PENDING, &swrm->port_req_pending);
  1451. swrm_cleanup_disabled_port_reqs(master);
  1452. if (!swrm_is_port_en(master)) {
  1453. dev_dbg(&master->dev, "%s: pm_runtime auto suspend triggered\n",
  1454. __func__);
  1455. pm_runtime_mark_last_busy(swrm->dev);
  1456. pm_runtime_put_autosuspend(swrm->dev);
  1457. }
  1458. goto exit;
  1459. }
  1460. bank = get_inactive_bank_num(swrm);
  1461. if (enable) {
  1462. if (!test_bit(ENABLE_PENDING, &swrm->port_req_pending)) {
  1463. dev_dbg(swrm->dev, "%s:No pending connect port req\n",
  1464. __func__);
  1465. goto exit;
  1466. }
  1467. clear_bit(ENABLE_PENDING, &swrm->port_req_pending);
  1468. ret = swrm_get_port_config(swrm);
  1469. if (ret) {
  1470. /* cannot accommodate ports */
  1471. swrm_cleanup_disabled_port_reqs(master);
  1472. mutex_unlock(&swrm->mlock);
  1473. return -EINVAL;
  1474. }
  1475. swr_master_write(swrm, SWRM_CPU1_INTERRUPT_EN,
  1476. SWRM_INTERRUPT_STATUS_MASK);
  1477. /* apply the new port config*/
  1478. swrm_apply_port_config(master);
  1479. } else {
  1480. if (!test_bit(DISABLE_PENDING, &swrm->port_req_pending)) {
  1481. dev_dbg(swrm->dev, "%s:No pending disconn port req\n",
  1482. __func__);
  1483. goto exit;
  1484. }
  1485. clear_bit(DISABLE_PENDING, &swrm->port_req_pending);
  1486. swrm_disable_ports(master, bank);
  1487. }
  1488. dev_dbg(swrm->dev, "%s: enable: %d, cfg_devs: %d freq %d\n",
  1489. __func__, enable, swrm->num_cfg_devs, swrm->mclk_freq);
  1490. if (enable) {
  1491. /* set col = 16 */
  1492. n_col = SWR_MAX_COL;
  1493. col = SWRM_COL_16;
  1494. if (swrm->bus_clk == MCLK_FREQ_LP) {
  1495. n_col = SWR_MIN_COL;
  1496. col = SWRM_COL_02;
  1497. }
  1498. } else {
  1499. /*
  1500. * Do not change to col = 2 if there are still active ports
  1501. */
  1502. if (!master->num_port) {
  1503. n_col = SWR_MIN_COL;
  1504. col = SWRM_COL_02;
  1505. } else {
  1506. n_col = SWR_MAX_COL;
  1507. col = SWRM_COL_16;
  1508. }
  1509. }
  1510. /* Use default 50 * x, frame shape. Change based on mclk */
  1511. if (swrm->mclk_freq == MCLK_FREQ_NATIVE) {
  1512. dev_dbg(swrm->dev, "setting 64 x %d frameshape\n", col);
  1513. n_row = SWR_ROW_64;
  1514. row = SWRM_ROW_64;
  1515. frame_sync = SWRM_FRAME_SYNC_SEL_NATIVE;
  1516. } else {
  1517. dev_dbg(swrm->dev, "setting 50 x %d frameshape\n", col);
  1518. n_row = SWR_ROW_50;
  1519. row = SWRM_ROW_50;
  1520. frame_sync = SWRM_FRAME_SYNC_SEL;
  1521. }
  1522. ssp_period = swrm_get_ssp_period(swrm, row, col, frame_sync);
  1523. bus_clk_div_factor = swrm_get_clk_div(swrm->mclk_freq, swrm->bus_clk);
  1524. dev_dbg(swrm->dev, "%s: ssp_period: %d, bus_clk_div:%d \n", __func__,
  1525. ssp_period, bus_clk_div_factor);
  1526. value = swr_master_read(swrm, SWRM_MCP_FRAME_CTRL_BANK(bank));
  1527. value &= (~mask);
  1528. value |= ((n_row << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) |
  1529. (n_col << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) |
  1530. (bus_clk_div_factor <<
  1531. SWRM_MCP_FRAME_CTRL_BANK_CLK_DIV_VALUE_SHFT) |
  1532. ((ssp_period - 1) << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT));
  1533. swr_master_write(swrm, SWRM_MCP_FRAME_CTRL_BANK(bank), value);
  1534. dev_dbg(swrm->dev, "%s: regaddr: 0x%x, value: 0x%x\n", __func__,
  1535. SWRM_MCP_FRAME_CTRL_BANK(bank), value);
  1536. enable_bank_switch(swrm, bank, n_row, n_col);
  1537. inactive_bank = bank ? 0 : 1;
  1538. if (enable)
  1539. swrm_copy_data_port_config(master, inactive_bank);
  1540. else {
  1541. swrm_disable_ports(master, inactive_bank);
  1542. swrm_cleanup_disabled_port_reqs(master);
  1543. }
  1544. if (!swrm_is_port_en(master)) {
  1545. dev_dbg(&master->dev, "%s: pm_runtime auto suspend triggered\n",
  1546. __func__);
  1547. pm_runtime_mark_last_busy(swrm->dev);
  1548. pm_runtime_put_autosuspend(swrm->dev);
  1549. }
  1550. exit:
  1551. mutex_unlock(&swrm->mlock);
  1552. return 0;
  1553. }
  1554. static int swrm_connect_port(struct swr_master *master,
  1555. struct swr_params *portinfo)
  1556. {
  1557. int i;
  1558. struct swr_port_info *port_req;
  1559. int ret = 0;
  1560. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1561. struct swrm_mports *mport;
  1562. u8 mstr_port_id, mstr_ch_msk;
  1563. dev_dbg(&master->dev, "%s: enter\n", __func__);
  1564. if (!portinfo)
  1565. return -EINVAL;
  1566. if (!swrm) {
  1567. dev_err(&master->dev,
  1568. "%s: Invalid handle to swr controller\n",
  1569. __func__);
  1570. return -EINVAL;
  1571. }
  1572. mutex_lock(&swrm->mlock);
  1573. mutex_lock(&swrm->devlock);
  1574. if (!swrm->dev_up) {
  1575. swr_port_response(master, portinfo->tid);
  1576. mutex_unlock(&swrm->devlock);
  1577. mutex_unlock(&swrm->mlock);
  1578. return -EINVAL;
  1579. }
  1580. mutex_unlock(&swrm->devlock);
  1581. if (!swrm_is_port_en(master))
  1582. pm_runtime_get_sync(swrm->dev);
  1583. for (i = 0; i < portinfo->num_port; i++) {
  1584. ret = swrm_get_master_port(swrm, &mstr_port_id, &mstr_ch_msk,
  1585. portinfo->port_type[i],
  1586. portinfo->port_id[i]);
  1587. if (ret) {
  1588. dev_err(&master->dev,
  1589. "%s: mstr portid for slv port %d not found\n",
  1590. __func__, portinfo->port_id[i]);
  1591. goto port_fail;
  1592. }
  1593. mport = &(swrm->mport_cfg[mstr_port_id]);
  1594. /* get port req */
  1595. port_req = swrm_get_port_req(mport, portinfo->port_id[i],
  1596. portinfo->dev_num);
  1597. if (!port_req) {
  1598. dev_dbg(&master->dev, "%s: new req:port id %d dev %d\n",
  1599. __func__, portinfo->port_id[i],
  1600. portinfo->dev_num);
  1601. port_req = kzalloc(sizeof(struct swr_port_info),
  1602. GFP_KERNEL);
  1603. if (!port_req) {
  1604. ret = -ENOMEM;
  1605. goto mem_fail;
  1606. }
  1607. port_req->dev_num = portinfo->dev_num;
  1608. port_req->slave_port_id = portinfo->port_id[i];
  1609. port_req->num_ch = portinfo->num_ch[i];
  1610. port_req->ch_rate = portinfo->ch_rate[i];
  1611. port_req->ch_en = 0;
  1612. port_req->master_port_id = mstr_port_id;
  1613. list_add(&port_req->list, &mport->port_req_list);
  1614. }
  1615. port_req->req_ch |= portinfo->ch_en[i];
  1616. dev_dbg(&master->dev,
  1617. "%s: mstr port %d, slv port %d ch_rate %d num_ch %d\n",
  1618. __func__, port_req->master_port_id,
  1619. port_req->slave_port_id, port_req->ch_rate,
  1620. port_req->num_ch);
  1621. /* Put the port req on master port */
  1622. mport = &(swrm->mport_cfg[mstr_port_id]);
  1623. mport->port_en = true;
  1624. mport->req_ch |= mstr_ch_msk;
  1625. master->port_en_mask |= (1 << mstr_port_id);
  1626. if (swrm->clk_stop_mode0_supp &&
  1627. swrm->dynamic_port_map_supported) {
  1628. mport->ch_rate += portinfo->ch_rate[i];
  1629. swrm_update_bus_clk(swrm);
  1630. }
  1631. }
  1632. master->num_port += portinfo->num_port;
  1633. set_bit(ENABLE_PENDING, &swrm->port_req_pending);
  1634. swr_port_response(master, portinfo->tid);
  1635. mutex_unlock(&swrm->mlock);
  1636. return 0;
  1637. port_fail:
  1638. mem_fail:
  1639. swr_port_response(master, portinfo->tid);
  1640. /* cleanup port reqs in error condition */
  1641. swrm_cleanup_disabled_port_reqs(master);
  1642. mutex_unlock(&swrm->mlock);
  1643. return ret;
  1644. }
  1645. static int swrm_disconnect_port(struct swr_master *master,
  1646. struct swr_params *portinfo)
  1647. {
  1648. int i, ret = 0;
  1649. struct swr_port_info *port_req;
  1650. struct swrm_mports *mport;
  1651. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1652. u8 mstr_port_id, mstr_ch_mask;
  1653. if (!swrm) {
  1654. dev_err(&master->dev,
  1655. "%s: Invalid handle to swr controller\n",
  1656. __func__);
  1657. return -EINVAL;
  1658. }
  1659. if (!portinfo) {
  1660. dev_err(&master->dev, "%s: portinfo is NULL\n", __func__);
  1661. return -EINVAL;
  1662. }
  1663. mutex_lock(&swrm->mlock);
  1664. for (i = 0; i < portinfo->num_port; i++) {
  1665. ret = swrm_get_master_port(swrm, &mstr_port_id, &mstr_ch_mask,
  1666. portinfo->port_type[i], portinfo->port_id[i]);
  1667. if (ret) {
  1668. dev_err(&master->dev,
  1669. "%s: mstr portid for slv port %d not found\n",
  1670. __func__, portinfo->port_id[i]);
  1671. goto err;
  1672. }
  1673. mport = &(swrm->mport_cfg[mstr_port_id]);
  1674. /* get port req */
  1675. port_req = swrm_get_port_req(mport, portinfo->port_id[i],
  1676. portinfo->dev_num);
  1677. if (!port_req) {
  1678. dev_err(&master->dev, "%s:port not enabled : port %d\n",
  1679. __func__, portinfo->port_id[i]);
  1680. goto err;
  1681. }
  1682. port_req->req_ch &= ~portinfo->ch_en[i];
  1683. mport->req_ch &= ~mstr_ch_mask;
  1684. if (swrm->clk_stop_mode0_supp &&
  1685. swrm->dynamic_port_map_supported &&
  1686. !mport->req_ch) {
  1687. mport->ch_rate = 0;
  1688. swrm_update_bus_clk(swrm);
  1689. }
  1690. }
  1691. master->num_port -= portinfo->num_port;
  1692. set_bit(DISABLE_PENDING, &swrm->port_req_pending);
  1693. swr_port_response(master, portinfo->tid);
  1694. mutex_unlock(&swrm->mlock);
  1695. return 0;
  1696. err:
  1697. swr_port_response(master, portinfo->tid);
  1698. mutex_unlock(&swrm->mlock);
  1699. return -EINVAL;
  1700. }
  1701. static int swrm_find_alert_slave(struct swr_mstr_ctrl *swrm,
  1702. int status, u8 *devnum)
  1703. {
  1704. int i;
  1705. bool found = false;
  1706. for (i = 0; i < (swrm->num_dev + 1); i++) {
  1707. if ((status & SWRM_MCP_SLV_STATUS_MASK) == SWR_ALERT) {
  1708. *devnum = i;
  1709. found = true;
  1710. break;
  1711. }
  1712. status >>= 2;
  1713. }
  1714. if (found)
  1715. return 0;
  1716. else
  1717. return -EINVAL;
  1718. }
  1719. static void swrm_enable_slave_irq(struct swr_mstr_ctrl *swrm)
  1720. {
  1721. int i;
  1722. int status = 0;
  1723. u32 temp;
  1724. status = swr_master_read(swrm, SWRM_MCP_SLV_STATUS);
  1725. if (!status) {
  1726. dev_dbg_ratelimited(swrm->dev, "%s: slaves status is 0x%x\n",
  1727. __func__, status);
  1728. return;
  1729. }
  1730. dev_dbg(swrm->dev, "%s: slave status: 0x%x\n", __func__, status);
  1731. for (i = 0; i < (swrm->num_dev + 1); i++) {
  1732. if (status & SWRM_MCP_SLV_STATUS_MASK) {
  1733. swrm_cmd_fifo_rd_cmd(swrm, &temp, i, 0x0,
  1734. SWRS_SCP_INT_STATUS_CLEAR_1, 1);
  1735. swrm_cmd_fifo_wr_cmd(swrm, 0xFF, i, 0x0,
  1736. SWRS_SCP_INT_STATUS_CLEAR_1);
  1737. swrm_cmd_fifo_wr_cmd(swrm, 0x4, i, 0x0,
  1738. SWRS_SCP_INT_STATUS_MASK_1);
  1739. }
  1740. status >>= 2;
  1741. }
  1742. }
  1743. static int swrm_check_slave_change_status(struct swr_mstr_ctrl *swrm,
  1744. int status, u8 *devnum)
  1745. {
  1746. int i;
  1747. int new_sts = status;
  1748. int ret = SWR_NOT_PRESENT;
  1749. if (status != swrm->slave_status) {
  1750. for (i = 0; i < (swrm->num_dev + 1); i++) {
  1751. if ((status & SWRM_MCP_SLV_STATUS_MASK) !=
  1752. (swrm->slave_status & SWRM_MCP_SLV_STATUS_MASK)) {
  1753. ret = (status & SWRM_MCP_SLV_STATUS_MASK);
  1754. *devnum = i;
  1755. break;
  1756. }
  1757. status >>= 2;
  1758. swrm->slave_status >>= 2;
  1759. }
  1760. swrm->slave_status = new_sts;
  1761. }
  1762. return ret;
  1763. }
  1764. static irqreturn_t swr_mstr_interrupt(int irq, void *dev)
  1765. {
  1766. struct swr_mstr_ctrl *swrm = dev;
  1767. u32 value, intr_sts, intr_sts_masked;
  1768. u32 temp = 0;
  1769. u32 status, chg_sts, i;
  1770. u8 devnum = 0;
  1771. int ret = IRQ_HANDLED;
  1772. struct swr_device *swr_dev;
  1773. struct swr_master *mstr = &swrm->master;
  1774. int retry = 5;
  1775. trace_printk("%s enter\n", __func__);
  1776. if (unlikely(swrm_lock_sleep(swrm) == false)) {
  1777. dev_err(swrm->dev, "%s Failed to hold suspend\n", __func__);
  1778. return IRQ_NONE;
  1779. }
  1780. mutex_lock(&swrm->reslock);
  1781. if (swrm_request_hw_vote(swrm, LPASS_HW_CORE, true)) {
  1782. ret = IRQ_NONE;
  1783. goto exit;
  1784. }
  1785. if (swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, true)) {
  1786. ret = IRQ_NONE;
  1787. goto err_audio_hw_vote;
  1788. }
  1789. ret = swrm_clk_request(swrm, true);
  1790. if (ret) {
  1791. dev_err(dev, "%s: swrm clk failed\n", __func__);
  1792. ret = IRQ_NONE;
  1793. goto err_audio_core_vote;
  1794. }
  1795. mutex_unlock(&swrm->reslock);
  1796. intr_sts = swr_master_read(swrm, SWRM_INTERRUPT_STATUS);
  1797. intr_sts_masked = intr_sts & swrm->intr_mask;
  1798. dev_dbg(swrm->dev, "%s: status: 0x%x \n", __func__, intr_sts_masked);
  1799. trace_printk("%s: status: 0x%x \n", __func__, intr_sts_masked);
  1800. handle_irq:
  1801. for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
  1802. value = intr_sts_masked & (1 << i);
  1803. if (!value)
  1804. continue;
  1805. switch (value) {
  1806. case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
  1807. dev_dbg(swrm->dev, "%s: Trigger irq to slave device\n",
  1808. __func__);
  1809. status = swr_master_read(swrm, SWRM_MCP_SLV_STATUS);
  1810. ret = swrm_find_alert_slave(swrm, status, &devnum);
  1811. if (ret) {
  1812. dev_err_ratelimited(swrm->dev,
  1813. "%s: no slave alert found.spurious interrupt\n",
  1814. __func__);
  1815. break;
  1816. }
  1817. swrm_cmd_fifo_rd_cmd(swrm, &temp, devnum, 0x0,
  1818. SWRS_SCP_INT_STATUS_CLEAR_1, 1);
  1819. swrm_cmd_fifo_wr_cmd(swrm, 0x4, devnum, 0x0,
  1820. SWRS_SCP_INT_STATUS_CLEAR_1);
  1821. swrm_cmd_fifo_wr_cmd(swrm, 0x0, devnum, 0x0,
  1822. SWRS_SCP_INT_STATUS_CLEAR_1);
  1823. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  1824. if (swr_dev->dev_num != devnum)
  1825. continue;
  1826. if (swr_dev->slave_irq) {
  1827. do {
  1828. swr_dev->slave_irq_pending = 0;
  1829. handle_nested_irq(
  1830. irq_find_mapping(
  1831. swr_dev->slave_irq, 0));
  1832. } while (swr_dev->slave_irq_pending);
  1833. }
  1834. }
  1835. break;
  1836. case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
  1837. dev_dbg(swrm->dev, "%s: SWR new slave attached\n",
  1838. __func__);
  1839. break;
  1840. case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
  1841. status = swr_master_read(swrm, SWRM_MCP_SLV_STATUS);
  1842. swrm_enable_slave_irq(swrm);
  1843. if (status == swrm->slave_status) {
  1844. dev_dbg(swrm->dev,
  1845. "%s: No change in slave status: 0x%x\n",
  1846. __func__, status);
  1847. break;
  1848. }
  1849. chg_sts = swrm_check_slave_change_status(swrm, status,
  1850. &devnum);
  1851. switch (chg_sts) {
  1852. case SWR_NOT_PRESENT:
  1853. dev_dbg(swrm->dev,
  1854. "%s: device %d got detached\n",
  1855. __func__, devnum);
  1856. if (devnum == 0) {
  1857. /*
  1858. * enable host irq if device 0 detached
  1859. * as hw will mask host_irq at slave
  1860. * but will not unmask it afterwards.
  1861. */
  1862. swrm->enable_slave_irq = true;
  1863. }
  1864. break;
  1865. case SWR_ATTACHED_OK:
  1866. dev_dbg(swrm->dev,
  1867. "%s: device %d got attached\n",
  1868. __func__, devnum);
  1869. /* enable host irq from slave device*/
  1870. swrm->enable_slave_irq = true;
  1871. break;
  1872. case SWR_ALERT:
  1873. dev_dbg(swrm->dev,
  1874. "%s: device %d has pending interrupt\n",
  1875. __func__, devnum);
  1876. break;
  1877. }
  1878. break;
  1879. case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
  1880. dev_err_ratelimited(swrm->dev,
  1881. "%s: SWR bus clsh detected\n",
  1882. __func__);
  1883. swrm->intr_mask &=
  1884. ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
  1885. swr_master_write(swrm,
  1886. SWRM_CPU1_INTERRUPT_EN,
  1887. swrm->intr_mask);
  1888. break;
  1889. case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
  1890. value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS);
  1891. dev_err(swrm->dev,
  1892. "%s: SWR read FIFO overflow fifo status %x\n",
  1893. __func__, value);
  1894. break;
  1895. case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
  1896. value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS);
  1897. dev_err(swrm->dev,
  1898. "%s: SWR read FIFO underflow fifo status %x\n",
  1899. __func__, value);
  1900. break;
  1901. case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
  1902. value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS);
  1903. dev_err(swrm->dev,
  1904. "%s: SWR write FIFO overflow fifo status %x\n",
  1905. __func__, value);
  1906. swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
  1907. break;
  1908. case SWRM_INTERRUPT_STATUS_CMD_ERROR:
  1909. value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS);
  1910. dev_err_ratelimited(swrm->dev,
  1911. "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
  1912. __func__, value);
  1913. swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
  1914. break;
  1915. case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
  1916. dev_err_ratelimited(swrm->dev,
  1917. "%s: SWR Port collision detected\n",
  1918. __func__);
  1919. swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
  1920. swr_master_write(swrm,
  1921. SWRM_CPU1_INTERRUPT_EN, swrm->intr_mask);
  1922. break;
  1923. case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
  1924. dev_dbg(swrm->dev,
  1925. "%s: SWR read enable valid mismatch\n",
  1926. __func__);
  1927. swrm->intr_mask &=
  1928. ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
  1929. swr_master_write(swrm,
  1930. SWRM_CPU1_INTERRUPT_EN, swrm->intr_mask);
  1931. break;
  1932. case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
  1933. complete(&swrm->broadcast);
  1934. dev_dbg(swrm->dev, "%s: SWR cmd id finished\n",
  1935. __func__);
  1936. break;
  1937. case SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED:
  1938. swr_master_write(swrm, SWRM_ENUMERATOR_CFG, 0);
  1939. while (swr_master_read(swrm, SWRM_ENUMERATOR_STATUS)) {
  1940. if (!retry) {
  1941. dev_dbg(swrm->dev,
  1942. "%s: ENUM status is not idle\n",
  1943. __func__);
  1944. break;
  1945. }
  1946. retry--;
  1947. }
  1948. swr_master_write(swrm, SWRM_ENUMERATOR_CFG, 1);
  1949. break;
  1950. case SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL:
  1951. break;
  1952. case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED:
  1953. swrm_check_link_status(swrm, 0x1);
  1954. break;
  1955. case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED:
  1956. break;
  1957. case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
  1958. if (swrm->state == SWR_MSTR_UP) {
  1959. dev_dbg(swrm->dev,
  1960. "%s:SWR Master is already up\n",
  1961. __func__);
  1962. } else {
  1963. dev_err_ratelimited(swrm->dev,
  1964. "%s: SWR wokeup during clock stop\n",
  1965. __func__);
  1966. /* It might be possible the slave device gets
  1967. * reset and slave interrupt gets missed. So
  1968. * re-enable Host IRQ and process slave pending
  1969. * interrupts, if any.
  1970. */
  1971. swrm_enable_slave_irq(swrm);
  1972. }
  1973. break;
  1974. default:
  1975. dev_err_ratelimited(swrm->dev,
  1976. "%s: SWR unknown interrupt value: %d\n",
  1977. __func__, value);
  1978. ret = IRQ_NONE;
  1979. break;
  1980. }
  1981. }
  1982. swr_master_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
  1983. swr_master_write(swrm, SWRM_INTERRUPT_CLEAR, 0x0);
  1984. if (swrm->enable_slave_irq) {
  1985. /* Enable slave irq here */
  1986. swrm_enable_slave_irq(swrm);
  1987. swrm->enable_slave_irq = false;
  1988. }
  1989. intr_sts = swr_master_read(swrm, SWRM_INTERRUPT_STATUS);
  1990. intr_sts_masked = intr_sts & swrm->intr_mask;
  1991. if (intr_sts_masked) {
  1992. dev_dbg(swrm->dev, "%s: new interrupt received 0x%x\n",
  1993. __func__, intr_sts_masked);
  1994. goto handle_irq;
  1995. }
  1996. mutex_lock(&swrm->reslock);
  1997. swrm_clk_request(swrm, false);
  1998. err_audio_core_vote:
  1999. swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, false);
  2000. err_audio_hw_vote:
  2001. swrm_request_hw_vote(swrm, LPASS_HW_CORE, false);
  2002. exit:
  2003. mutex_unlock(&swrm->reslock);
  2004. swrm_unlock_sleep(swrm);
  2005. trace_printk("%s exit\n", __func__);
  2006. return ret;
  2007. }
  2008. static irqreturn_t swrm_wakeup_interrupt(int irq, void *dev)
  2009. {
  2010. struct swr_mstr_ctrl *swrm = dev;
  2011. int ret = IRQ_HANDLED;
  2012. if (!swrm || !(swrm->dev)) {
  2013. pr_err("%s: swrm or dev is null\n", __func__);
  2014. return IRQ_NONE;
  2015. }
  2016. trace_printk("%s enter\n", __func__);
  2017. mutex_lock(&swrm->devlock);
  2018. if (swrm->state == SWR_MSTR_SSR || !swrm->dev_up) {
  2019. if (swrm->wake_irq > 0) {
  2020. if (unlikely(!irq_get_irq_data(swrm->wake_irq))) {
  2021. pr_err("%s: irq data is NULL\n", __func__);
  2022. mutex_unlock(&swrm->devlock);
  2023. return IRQ_NONE;
  2024. }
  2025. mutex_lock(&swrm->irq_lock);
  2026. if (!irqd_irq_disabled(
  2027. irq_get_irq_data(swrm->wake_irq)))
  2028. disable_irq_nosync(swrm->wake_irq);
  2029. mutex_unlock(&swrm->irq_lock);
  2030. }
  2031. mutex_unlock(&swrm->devlock);
  2032. return ret;
  2033. }
  2034. mutex_unlock(&swrm->devlock);
  2035. if (unlikely(swrm_lock_sleep(swrm) == false)) {
  2036. dev_err(swrm->dev, "%s Failed to hold suspend\n", __func__);
  2037. goto exit;
  2038. }
  2039. if (swrm->wake_irq > 0) {
  2040. if (unlikely(!irq_get_irq_data(swrm->wake_irq))) {
  2041. pr_err("%s: irq data is NULL\n", __func__);
  2042. return IRQ_NONE;
  2043. }
  2044. mutex_lock(&swrm->irq_lock);
  2045. if (!irqd_irq_disabled(
  2046. irq_get_irq_data(swrm->wake_irq)))
  2047. disable_irq_nosync(swrm->wake_irq);
  2048. mutex_unlock(&swrm->irq_lock);
  2049. }
  2050. pm_runtime_get_sync(swrm->dev);
  2051. pm_runtime_mark_last_busy(swrm->dev);
  2052. pm_runtime_put_autosuspend(swrm->dev);
  2053. swrm_unlock_sleep(swrm);
  2054. exit:
  2055. trace_printk("%s exit\n", __func__);
  2056. return ret;
  2057. }
  2058. static void swrm_wakeup_work(struct work_struct *work)
  2059. {
  2060. struct swr_mstr_ctrl *swrm;
  2061. swrm = container_of(work, struct swr_mstr_ctrl,
  2062. wakeup_work);
  2063. if (!swrm || !(swrm->dev)) {
  2064. pr_err("%s: swrm or dev is null\n", __func__);
  2065. return;
  2066. }
  2067. trace_printk("%s enter\n", __func__);
  2068. mutex_lock(&swrm->devlock);
  2069. if (!swrm->dev_up) {
  2070. mutex_unlock(&swrm->devlock);
  2071. goto exit;
  2072. }
  2073. mutex_unlock(&swrm->devlock);
  2074. if (unlikely(swrm_lock_sleep(swrm) == false)) {
  2075. dev_err(swrm->dev, "%s Failed to hold suspend\n", __func__);
  2076. goto exit;
  2077. }
  2078. pm_runtime_get_sync(swrm->dev);
  2079. pm_runtime_mark_last_busy(swrm->dev);
  2080. pm_runtime_put_autosuspend(swrm->dev);
  2081. swrm_unlock_sleep(swrm);
  2082. exit:
  2083. trace_printk("%s exit\n", __func__);
  2084. pm_relax(swrm->dev);
  2085. }
  2086. static int swrm_get_device_status(struct swr_mstr_ctrl *swrm, u8 devnum)
  2087. {
  2088. u32 val;
  2089. swrm->slave_status = swr_master_read(swrm, SWRM_MCP_SLV_STATUS);
  2090. val = (swrm->slave_status >> (devnum * 2));
  2091. val &= SWRM_MCP_SLV_STATUS_MASK;
  2092. return val;
  2093. }
  2094. static int swrm_get_logical_dev_num(struct swr_master *mstr, u64 dev_id,
  2095. u8 *dev_num)
  2096. {
  2097. int i;
  2098. u64 id = 0;
  2099. int ret = -EINVAL;
  2100. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(mstr);
  2101. struct swr_device *swr_dev;
  2102. u32 num_dev = 0;
  2103. if (!swrm) {
  2104. pr_err("%s: Invalid handle to swr controller\n",
  2105. __func__);
  2106. return ret;
  2107. }
  2108. num_dev = swrm->num_dev;
  2109. mutex_lock(&swrm->devlock);
  2110. if (!swrm->dev_up) {
  2111. mutex_unlock(&swrm->devlock);
  2112. return ret;
  2113. }
  2114. mutex_unlock(&swrm->devlock);
  2115. pm_runtime_get_sync(swrm->dev);
  2116. for (i = 1; i < (num_dev + 1); i++) {
  2117. id = ((u64)(swr_master_read(swrm,
  2118. SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i))) << 32);
  2119. id |= swr_master_read(swrm,
  2120. SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i));
  2121. /*
  2122. * As pm_runtime_get_sync() brings all slaves out of reset
  2123. * update logical device number for all slaves.
  2124. */
  2125. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  2126. if (swr_dev->addr == (id & SWR_DEV_ID_MASK)) {
  2127. u32 status = swrm_get_device_status(swrm, i);
  2128. if ((status == 0x01) || (status == 0x02)) {
  2129. swr_dev->dev_num = i;
  2130. if ((id & SWR_DEV_ID_MASK) == dev_id) {
  2131. *dev_num = i;
  2132. ret = 0;
  2133. dev_info(swrm->dev,
  2134. "%s: devnum %d assigned for dev %llx\n",
  2135. __func__, i,
  2136. swr_dev->addr);
  2137. }
  2138. }
  2139. }
  2140. }
  2141. }
  2142. if (ret)
  2143. dev_err_ratelimited(swrm->dev,
  2144. "%s: device 0x%llx is not ready\n",
  2145. __func__, dev_id);
  2146. pm_runtime_mark_last_busy(swrm->dev);
  2147. pm_runtime_put_autosuspend(swrm->dev);
  2148. return ret;
  2149. }
  2150. static int swrm_init_port_params(struct swr_master *mstr, u32 dev_num,
  2151. u32 num_ports,
  2152. struct swr_dev_frame_config *uc_arr)
  2153. {
  2154. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(mstr);
  2155. int i, j, port_id_offset;
  2156. if (!swrm) {
  2157. pr_err("%s: Invalid handle to swr controller\n", __func__);
  2158. return 0;
  2159. }
  2160. for (i = 0; i < SWR_UC_MAX; i++) {
  2161. for (j = 0; j < num_ports; j++) {
  2162. port_id_offset = (dev_num - 1) * SWR_MAX_DEV_PORT_NUM + j;
  2163. swrm->pp[i][port_id_offset].offset1 = uc_arr[i].pp[j].offset1;
  2164. swrm->pp[i][port_id_offset].lane_ctrl = uc_arr[i].pp[j].lane_ctrl;
  2165. }
  2166. }
  2167. return 0;
  2168. }
  2169. static void swrm_device_wakeup_vote(struct swr_master *mstr)
  2170. {
  2171. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(mstr);
  2172. if (!swrm) {
  2173. pr_err("%s: Invalid handle to swr controller\n",
  2174. __func__);
  2175. return;
  2176. }
  2177. if (unlikely(swrm_lock_sleep(swrm) == false)) {
  2178. dev_err(swrm->dev, "%s Failed to hold suspend\n", __func__);
  2179. return;
  2180. }
  2181. if (swrm_request_hw_vote(swrm, LPASS_HW_CORE, true))
  2182. dev_err(swrm->dev, "%s:lpass core hw enable failed\n",
  2183. __func__);
  2184. if (swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, true))
  2185. dev_err(swrm->dev, "%s:lpass audio hw enable failed\n",
  2186. __func__);
  2187. pm_runtime_get_sync(swrm->dev);
  2188. }
  2189. static void swrm_device_wakeup_unvote(struct swr_master *mstr)
  2190. {
  2191. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(mstr);
  2192. if (!swrm) {
  2193. pr_err("%s: Invalid handle to swr controller\n",
  2194. __func__);
  2195. return;
  2196. }
  2197. pm_runtime_mark_last_busy(swrm->dev);
  2198. pm_runtime_put_autosuspend(swrm->dev);
  2199. swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, false);
  2200. swrm_request_hw_vote(swrm, LPASS_HW_CORE, false);
  2201. swrm_unlock_sleep(swrm);
  2202. }
  2203. static int swrm_master_init(struct swr_mstr_ctrl *swrm)
  2204. {
  2205. int ret = 0, i = 0;
  2206. u32 val;
  2207. u8 row_ctrl = SWR_ROW_50;
  2208. u8 col_ctrl = SWR_MIN_COL;
  2209. u8 ssp_period = 1;
  2210. u8 retry_cmd_num = 3;
  2211. u32 reg[SWRM_MAX_INIT_REG];
  2212. u32 value[SWRM_MAX_INIT_REG];
  2213. u32 temp = 0;
  2214. int len = 0;
  2215. /* SW workaround to gate hw_ctl for SWR version >=1.6 */
  2216. if (swrm->version >= SWRM_VERSION_1_6) {
  2217. if (swrm->swrm_hctl_reg) {
  2218. temp = ioread32(swrm->swrm_hctl_reg);
  2219. temp &= 0xFFFFFFFD;
  2220. iowrite32(temp, swrm->swrm_hctl_reg);
  2221. usleep_range(500, 505);
  2222. temp = ioread32(swrm->swrm_hctl_reg);
  2223. dev_dbg(swrm->dev, "%s: hctl_reg val: 0x%x\n",
  2224. __func__, temp);
  2225. }
  2226. }
  2227. ssp_period = swrm_get_ssp_period(swrm, SWRM_ROW_50,
  2228. SWRM_COL_02, SWRM_FRAME_SYNC_SEL);
  2229. dev_dbg(swrm->dev, "%s: ssp_period: %d\n", __func__, ssp_period);
  2230. /* Clear Rows and Cols */
  2231. val = ((row_ctrl << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) |
  2232. (col_ctrl << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) |
  2233. ((ssp_period - 1) << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT));
  2234. reg[len] = SWRM_MCP_FRAME_CTRL_BANK(0);
  2235. value[len++] = val;
  2236. /* Set Auto enumeration flag */
  2237. reg[len] = SWRM_ENUMERATOR_CFG;
  2238. value[len++] = 1;
  2239. /* Configure No pings */
  2240. val = swr_master_read(swrm, SWRM_MCP_CFG);
  2241. val &= ~SWRM_NUM_PINGS_MASK;
  2242. val |= (0x1f << SWRM_NUM_PINGS_POS);
  2243. reg[len] = SWRM_MCP_CFG;
  2244. value[len++] = val;
  2245. /* Configure number of retries of a read/write cmd */
  2246. val = (retry_cmd_num);
  2247. reg[len] = SWRM_CMD_FIFO_CFG;
  2248. value[len++] = val;
  2249. if (swrm->version >= SWRM_VERSION_1_7) {
  2250. reg[len] = SWRM_LINK_MANAGER_EE;
  2251. value[len++] = swrm->ee_val;
  2252. }
  2253. reg[len] = SWRM_MCP_BUS_CTRL;
  2254. if (swrm->version < SWRM_VERSION_1_7)
  2255. value[len++] = 0x2;
  2256. else
  2257. value[len++] = 0x2 << swrm->ee_val;
  2258. /* Set IRQ to PULSE */
  2259. reg[len] = SWRM_COMP_CFG;
  2260. value[len++] = 0x02;
  2261. reg[len] = SWRM_INTERRUPT_CLEAR;
  2262. value[len++] = 0xFFFFFFFF;
  2263. swrm->intr_mask = SWRM_INTERRUPT_STATUS_MASK;
  2264. /* Mask soundwire interrupts */
  2265. reg[len] = SWRM_INTERRUPT_EN;
  2266. value[len++] = swrm->intr_mask;
  2267. reg[len] = SWRM_CPU1_INTERRUPT_EN;
  2268. value[len++] = swrm->intr_mask;
  2269. reg[len] = SWRM_COMP_CFG;
  2270. value[len++] = 0x03;
  2271. swr_master_bulk_write(swrm, reg, value, len);
  2272. if (!swrm_check_link_status(swrm, 0x1)) {
  2273. dev_err(swrm->dev,
  2274. "%s: swr link failed to connect\n",
  2275. __func__);
  2276. for (i = 0; i < len; i++) {
  2277. usleep_range(50, 55);
  2278. dev_err(swrm->dev,
  2279. "%s:reg:0x%x val:0x%x\n",
  2280. __func__,
  2281. reg[i], swr_master_read(swrm, reg[i]));
  2282. }
  2283. return -EINVAL;
  2284. }
  2285. /* Execute it for versions >= 1.5.1 */
  2286. if (swrm->version >= SWRM_VERSION_1_5_1)
  2287. swr_master_write(swrm, SWRM_CMD_FIFO_CFG,
  2288. (swr_master_read(swrm,
  2289. SWRM_CMD_FIFO_CFG) | 0x80000000));
  2290. return ret;
  2291. }
  2292. static int swrm_event_notify(struct notifier_block *self,
  2293. unsigned long action, void *data)
  2294. {
  2295. struct swr_mstr_ctrl *swrm = container_of(self, struct swr_mstr_ctrl,
  2296. event_notifier);
  2297. if (!swrm || !(swrm->dev)) {
  2298. pr_err("%s: swrm or dev is NULL\n", __func__);
  2299. return -EINVAL;
  2300. }
  2301. switch (action) {
  2302. case MSM_AUD_DC_EVENT:
  2303. schedule_work(&(swrm->dc_presence_work));
  2304. break;
  2305. case SWR_WAKE_IRQ_EVENT:
  2306. if (swrm->ipc_wakeup && !swrm->ipc_wakeup_triggered) {
  2307. swrm->ipc_wakeup_triggered = true;
  2308. pm_stay_awake(swrm->dev);
  2309. schedule_work(&swrm->wakeup_work);
  2310. }
  2311. break;
  2312. default:
  2313. dev_err(swrm->dev, "%s: invalid event type: %lu\n",
  2314. __func__, action);
  2315. return -EINVAL;
  2316. }
  2317. return 0;
  2318. }
  2319. static void swrm_notify_work_fn(struct work_struct *work)
  2320. {
  2321. struct swr_mstr_ctrl *swrm = container_of(work, struct swr_mstr_ctrl,
  2322. dc_presence_work);
  2323. if (!swrm || !swrm->pdev) {
  2324. pr_err("%s: swrm or pdev is NULL\n", __func__);
  2325. return;
  2326. }
  2327. swrm_wcd_notify(swrm->pdev, SWR_DEVICE_DOWN, NULL);
  2328. }
  2329. static int swrm_probe(struct platform_device *pdev)
  2330. {
  2331. struct swr_mstr_ctrl *swrm;
  2332. struct swr_ctrl_platform_data *pdata;
  2333. u32 i, num_ports, port_num, port_type, ch_mask, swrm_hctl_reg = 0;
  2334. u32 *temp, map_size, map_length, ch_iter = 0, old_port_num = 0;
  2335. int ret = 0;
  2336. struct clk *lpass_core_hw_vote = NULL;
  2337. struct clk *lpass_core_audio = NULL;
  2338. u32 swrm_hw_ver = 0;
  2339. /* Allocate soundwire master driver structure */
  2340. swrm = devm_kzalloc(&pdev->dev, sizeof(struct swr_mstr_ctrl),
  2341. GFP_KERNEL);
  2342. if (!swrm) {
  2343. ret = -ENOMEM;
  2344. goto err_memory_fail;
  2345. }
  2346. swrm->pdev = pdev;
  2347. swrm->dev = &pdev->dev;
  2348. platform_set_drvdata(pdev, swrm);
  2349. swr_set_ctrl_data(&swrm->master, swrm);
  2350. pdata = dev_get_platdata(&pdev->dev);
  2351. if (!pdata) {
  2352. dev_err(&pdev->dev, "%s: pdata from parent is NULL\n",
  2353. __func__);
  2354. ret = -EINVAL;
  2355. goto err_pdata_fail;
  2356. }
  2357. swrm->handle = (void *)pdata->handle;
  2358. if (!swrm->handle) {
  2359. dev_err(&pdev->dev, "%s: swrm->handle is NULL\n",
  2360. __func__);
  2361. ret = -EINVAL;
  2362. goto err_pdata_fail;
  2363. }
  2364. ret = of_property_read_u32(pdev->dev.of_node, "qcom,swr-master-ee-val",
  2365. &swrm->ee_val);
  2366. if (ret) {
  2367. dev_dbg(&pdev->dev,
  2368. "%s: ee_val not specified, initialize with default val\n",
  2369. __func__);
  2370. swrm->ee_val = 0x1;
  2371. }
  2372. ret = of_property_read_u32(pdev->dev.of_node,
  2373. "qcom,swr-master-version",
  2374. &swrm->version);
  2375. if (ret) {
  2376. dev_dbg(&pdev->dev, "%s: swrm version not defined, use default\n",
  2377. __func__);
  2378. swrm->version = SWRM_VERSION_1_7;
  2379. }
  2380. ret = of_property_read_u32(pdev->dev.of_node, "qcom,swr_master_id",
  2381. &swrm->master_id);
  2382. if (ret) {
  2383. dev_err(&pdev->dev, "%s: failed to get master id\n", __func__);
  2384. goto err_pdata_fail;
  2385. }
  2386. ret = of_property_read_u32(pdev->dev.of_node, "qcom,dynamic-port-map-supported",
  2387. &swrm->dynamic_port_map_supported);
  2388. if (ret) {
  2389. dev_dbg(&pdev->dev,
  2390. "%s: failed to get dynamic port map support, use default\n",
  2391. __func__);
  2392. swrm->dynamic_port_map_supported = 1;
  2393. }
  2394. if (!(of_property_read_u32(pdev->dev.of_node,
  2395. "swrm-io-base", &swrm->swrm_base_reg)))
  2396. ret = of_property_read_u32(pdev->dev.of_node,
  2397. "swrm-io-base", &swrm->swrm_base_reg);
  2398. if (!swrm->swrm_base_reg) {
  2399. swrm->read = pdata->read;
  2400. if (!swrm->read) {
  2401. dev_err(&pdev->dev, "%s: swrm->read is NULL\n",
  2402. __func__);
  2403. ret = -EINVAL;
  2404. goto err_pdata_fail;
  2405. }
  2406. swrm->write = pdata->write;
  2407. if (!swrm->write) {
  2408. dev_err(&pdev->dev, "%s: swrm->write is NULL\n",
  2409. __func__);
  2410. ret = -EINVAL;
  2411. goto err_pdata_fail;
  2412. }
  2413. swrm->bulk_write = pdata->bulk_write;
  2414. if (!swrm->bulk_write) {
  2415. dev_err(&pdev->dev, "%s: swrm->bulk_write is NULL\n",
  2416. __func__);
  2417. ret = -EINVAL;
  2418. goto err_pdata_fail;
  2419. }
  2420. } else {
  2421. swrm->swrm_dig_base = devm_ioremap(&pdev->dev,
  2422. swrm->swrm_base_reg, SWRM_MAX_REGISTER);
  2423. }
  2424. swrm->core_vote = pdata->core_vote;
  2425. if (!(of_property_read_u32(pdev->dev.of_node,
  2426. "qcom,swrm-hctl-reg", &swrm_hctl_reg)))
  2427. swrm->swrm_hctl_reg = devm_ioremap(&pdev->dev,
  2428. swrm_hctl_reg, 0x4);
  2429. swrm->clk = pdata->clk;
  2430. if (!swrm->clk) {
  2431. dev_err(&pdev->dev, "%s: swrm->clk is NULL\n",
  2432. __func__);
  2433. ret = -EINVAL;
  2434. goto err_pdata_fail;
  2435. }
  2436. if (of_property_read_u32(pdev->dev.of_node,
  2437. "qcom,swr-clock-stop-mode0",
  2438. &swrm->clk_stop_mode0_supp)) {
  2439. swrm->clk_stop_mode0_supp = FALSE;
  2440. }
  2441. /* Parse soundwire port mapping */
  2442. ret = of_property_read_u32(pdev->dev.of_node, "qcom,swr-num-ports",
  2443. &num_ports);
  2444. if (ret) {
  2445. dev_err(swrm->dev, "%s: Failed to get num_ports\n", __func__);
  2446. goto err_pdata_fail;
  2447. }
  2448. swrm->num_ports = num_ports;
  2449. if (!of_find_property(pdev->dev.of_node, "qcom,swr-port-mapping",
  2450. &map_size)) {
  2451. dev_err(swrm->dev, "missing port mapping\n");
  2452. goto err_pdata_fail;
  2453. }
  2454. map_length = map_size / (3 * sizeof(u32));
  2455. if (num_ports > SWR_MSTR_PORT_LEN) {
  2456. dev_err(&pdev->dev, "%s:invalid number of swr ports\n",
  2457. __func__);
  2458. ret = -EINVAL;
  2459. goto err_pdata_fail;
  2460. }
  2461. temp = devm_kzalloc(&pdev->dev, map_size, GFP_KERNEL);
  2462. if (!temp) {
  2463. ret = -ENOMEM;
  2464. goto err_pdata_fail;
  2465. }
  2466. ret = of_property_read_u32_array(pdev->dev.of_node,
  2467. "qcom,swr-port-mapping", temp, 3 * map_length);
  2468. if (ret) {
  2469. dev_err(swrm->dev, "%s: Failed to read port mapping\n",
  2470. __func__);
  2471. goto err_pdata_fail;
  2472. }
  2473. for (i = 0; i < map_length; i++) {
  2474. port_num = temp[3 * i];
  2475. port_type = temp[3 * i + 1];
  2476. ch_mask = temp[3 * i + 2];
  2477. if (port_num != old_port_num)
  2478. ch_iter = 0;
  2479. if (port_num > SWR_MSTR_PORT_LEN ||
  2480. ch_iter >= SWR_MAX_CH_PER_PORT) {
  2481. dev_err(&pdev->dev,
  2482. "%s:invalid port_num %d or ch_iter %d\n",
  2483. __func__, port_num, ch_iter);
  2484. goto err_pdata_fail;
  2485. }
  2486. swrm->port_mapping[port_num][ch_iter].port_type = port_type;
  2487. swrm->port_mapping[port_num][ch_iter++].ch_mask = ch_mask;
  2488. old_port_num = port_num;
  2489. }
  2490. devm_kfree(&pdev->dev, temp);
  2491. ret = of_property_read_u32(pdev->dev.of_node, "qcom,is-always-on",
  2492. &swrm->is_always_on);
  2493. if (ret)
  2494. dev_dbg(&pdev->dev, "%s: failed to get is_always_on flag\n", __func__);
  2495. swrm->reg_irq = pdata->reg_irq;
  2496. swrm->master.read = swrm_read;
  2497. swrm->master.write = swrm_write;
  2498. swrm->master.bulk_write = swrm_bulk_write;
  2499. swrm->master.get_logical_dev_num = swrm_get_logical_dev_num;
  2500. swrm->master.init_port_params = swrm_init_port_params;
  2501. swrm->master.connect_port = swrm_connect_port;
  2502. swrm->master.disconnect_port = swrm_disconnect_port;
  2503. swrm->master.slvdev_datapath_control = swrm_slvdev_datapath_control;
  2504. swrm->master.remove_from_group = swrm_remove_from_group;
  2505. swrm->master.device_wakeup_vote = swrm_device_wakeup_vote;
  2506. swrm->master.device_wakeup_unvote = swrm_device_wakeup_unvote;
  2507. swrm->master.dev.parent = &pdev->dev;
  2508. swrm->master.dev.of_node = pdev->dev.of_node;
  2509. swrm->master.num_port = 0;
  2510. swrm->rcmd_id = 0;
  2511. swrm->wcmd_id = 0;
  2512. swrm->slave_status = 0;
  2513. swrm->num_rx_chs = 0;
  2514. swrm->clk_ref_count = 0;
  2515. swrm->swr_irq_wakeup_capable = 0;
  2516. swrm->mclk_freq = MCLK_FREQ;
  2517. swrm->bus_clk = MCLK_FREQ;
  2518. swrm->dev_up = true;
  2519. swrm->state = SWR_MSTR_UP;
  2520. swrm->ipc_wakeup = false;
  2521. swrm->ipc_wakeup_triggered = false;
  2522. swrm->disable_div2_clk_switch = FALSE;
  2523. init_completion(&swrm->reset);
  2524. init_completion(&swrm->broadcast);
  2525. init_completion(&swrm->clk_off_complete);
  2526. mutex_init(&swrm->irq_lock);
  2527. mutex_init(&swrm->mlock);
  2528. mutex_init(&swrm->reslock);
  2529. mutex_init(&swrm->force_down_lock);
  2530. mutex_init(&swrm->iolock);
  2531. mutex_init(&swrm->clklock);
  2532. mutex_init(&swrm->devlock);
  2533. mutex_init(&swrm->pm_lock);
  2534. swrm->wlock_holders = 0;
  2535. swrm->pm_state = SWRM_PM_SLEEPABLE;
  2536. init_waitqueue_head(&swrm->pm_wq);
  2537. for (i = 0 ; i < SWR_MSTR_PORT_LEN; i++) {
  2538. INIT_LIST_HEAD(&swrm->mport_cfg[i].port_req_list);
  2539. if (swrm->master_id == MASTER_ID_TX) {
  2540. swrm->mport_cfg[i].sinterval = 0xFFFF;
  2541. swrm->mport_cfg[i].offset1 = 0x00;
  2542. swrm->mport_cfg[i].offset2 = 0x00;
  2543. swrm->mport_cfg[i].hstart = 0xFF;
  2544. swrm->mport_cfg[i].hstop = 0xFF;
  2545. swrm->mport_cfg[i].blk_pack_mode = 0xFF;
  2546. swrm->mport_cfg[i].blk_grp_count = 0xFF;
  2547. swrm->mport_cfg[i].word_length = 0xFF;
  2548. swrm->mport_cfg[i].lane_ctrl = 0x00;
  2549. swrm->mport_cfg[i].dir = 0x00;
  2550. swrm->mport_cfg[i].stream_type = 0x00;
  2551. }
  2552. }
  2553. if (of_property_read_u32(pdev->dev.of_node,
  2554. "qcom,disable-div2-clk-switch",
  2555. &swrm->disable_div2_clk_switch)) {
  2556. swrm->disable_div2_clk_switch = FALSE;
  2557. }
  2558. /* Register LPASS core hw vote */
  2559. lpass_core_hw_vote = devm_clk_get(&pdev->dev, "lpass_core_hw_vote");
  2560. if (IS_ERR(lpass_core_hw_vote)) {
  2561. ret = PTR_ERR(lpass_core_hw_vote);
  2562. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  2563. __func__, "lpass_core_hw_vote", ret);
  2564. lpass_core_hw_vote = NULL;
  2565. ret = 0;
  2566. }
  2567. swrm->lpass_core_hw_vote = lpass_core_hw_vote;
  2568. /* Register LPASS audio core vote */
  2569. lpass_core_audio = devm_clk_get(&pdev->dev, "lpass_audio_hw_vote");
  2570. if (IS_ERR(lpass_core_audio)) {
  2571. ret = PTR_ERR(lpass_core_audio);
  2572. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  2573. __func__, "lpass_core_audio", ret);
  2574. lpass_core_audio = NULL;
  2575. ret = 0;
  2576. }
  2577. swrm->lpass_core_audio = lpass_core_audio;
  2578. if (swrm->reg_irq) {
  2579. ret = swrm->reg_irq(swrm->handle, swr_mstr_interrupt, swrm,
  2580. SWR_IRQ_REGISTER);
  2581. if (ret) {
  2582. dev_err(&pdev->dev, "%s: IRQ register failed ret %d\n",
  2583. __func__, ret);
  2584. goto err_irq_fail;
  2585. }
  2586. } else {
  2587. swrm->irq = platform_get_irq_byname(pdev, "swr_master_irq");
  2588. if (swrm->irq < 0) {
  2589. dev_err(swrm->dev, "%s() error getting irq hdle: %d\n",
  2590. __func__, swrm->irq);
  2591. goto err_irq_fail;
  2592. }
  2593. ret = request_threaded_irq(swrm->irq, NULL,
  2594. swr_mstr_interrupt,
  2595. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  2596. "swr_master_irq", swrm);
  2597. if (ret) {
  2598. dev_err(swrm->dev, "%s: Failed to request irq %d\n",
  2599. __func__, ret);
  2600. goto err_irq_fail;
  2601. }
  2602. }
  2603. /* Make inband tx interrupts as wakeup capable for slave irq */
  2604. ret = of_property_read_u32(pdev->dev.of_node,
  2605. "qcom,swr-mstr-irq-wakeup-capable",
  2606. &swrm->swr_irq_wakeup_capable);
  2607. if (ret)
  2608. dev_dbg(swrm->dev, "%s: swrm irq wakeup capable not defined\n",
  2609. __func__);
  2610. if (swrm->swr_irq_wakeup_capable)
  2611. irq_set_irq_wake(swrm->irq, 1);
  2612. ret = swr_register_master(&swrm->master);
  2613. if (ret) {
  2614. dev_err(&pdev->dev, "%s: error adding swr master\n", __func__);
  2615. goto err_mstr_fail;
  2616. }
  2617. /* Add devices registered with board-info as the
  2618. * controller will be up now
  2619. */
  2620. swr_master_add_boarddevices(&swrm->master);
  2621. if (!swrm->is_always_on && swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, true))
  2622. dev_dbg(&pdev->dev, "%s: Audio HW Vote is failed\n", __func__);
  2623. mutex_lock(&swrm->mlock);
  2624. swrm_clk_request(swrm, true);
  2625. swrm->rd_fifo_depth = ((swr_master_read(swrm, SWRM_COMP_PARAMS)
  2626. & SWRM_COMP_PARAMS_RD_FIFO_DEPTH) >> 15);
  2627. swrm->wr_fifo_depth = ((swr_master_read(swrm, SWRM_COMP_PARAMS)
  2628. & SWRM_COMP_PARAMS_WR_FIFO_DEPTH) >> 10);
  2629. swrm_hw_ver = swr_master_read(swrm, SWRM_COMP_HW_VERSION);
  2630. if (swrm->version != swrm_hw_ver)
  2631. dev_info(&pdev->dev,
  2632. "%s: version specified in dtsi: 0x%x not match with HW read version 0x%x\n",
  2633. __func__, swrm->version, swrm_hw_ver);
  2634. swrm->num_auto_enum = ((swr_master_read(swrm, SWRM_COMP_PARAMS)
  2635. & SWRM_COMP_PARAMS_AUTO_ENUM_SLAVES) >> 20);
  2636. ret = of_property_read_u32(swrm->dev->of_node, "qcom,swr-num-dev",
  2637. &swrm->num_dev);
  2638. if (ret) {
  2639. dev_err(&pdev->dev, "%s: Looking up %s property failed\n",
  2640. __func__, "qcom,swr-num-dev");
  2641. mutex_unlock(&swrm->mlock);
  2642. goto err_parse_num_dev;
  2643. } else {
  2644. if (swrm->num_dev > swrm->num_auto_enum) {
  2645. dev_err(&pdev->dev, "%s: num_dev %d > max limit %d\n",
  2646. __func__, swrm->num_dev,
  2647. swrm->num_auto_enum);
  2648. ret = -EINVAL;
  2649. mutex_unlock(&swrm->mlock);
  2650. goto err_parse_num_dev;
  2651. } else {
  2652. dev_dbg(&pdev->dev,
  2653. "max swr devices expected to attach - %d, supported auto_enum - %d\n",
  2654. swrm->num_dev, swrm->num_auto_enum);
  2655. }
  2656. }
  2657. ret = swrm_master_init(swrm);
  2658. if (ret < 0) {
  2659. dev_err(&pdev->dev,
  2660. "%s: Error in master Initialization , err %d\n",
  2661. __func__, ret);
  2662. mutex_unlock(&swrm->mlock);
  2663. ret = -EPROBE_DEFER;
  2664. goto err_mstr_init_fail;
  2665. }
  2666. mutex_unlock(&swrm->mlock);
  2667. INIT_WORK(&swrm->wakeup_work, swrm_wakeup_work);
  2668. if (pdev->dev.of_node)
  2669. of_register_swr_devices(&swrm->master);
  2670. #ifdef CONFIG_DEBUG_FS
  2671. swrm->debugfs_swrm_dent = debugfs_create_dir(dev_name(&pdev->dev), 0);
  2672. if (!IS_ERR(swrm->debugfs_swrm_dent)) {
  2673. swrm->debugfs_peek = debugfs_create_file("swrm_peek",
  2674. S_IFREG | 0444, swrm->debugfs_swrm_dent,
  2675. (void *) swrm, &swrm_debug_read_ops);
  2676. swrm->debugfs_poke = debugfs_create_file("swrm_poke",
  2677. S_IFREG | 0444, swrm->debugfs_swrm_dent,
  2678. (void *) swrm, &swrm_debug_write_ops);
  2679. swrm->debugfs_reg_dump = debugfs_create_file("swrm_reg_dump",
  2680. S_IFREG | 0444, swrm->debugfs_swrm_dent,
  2681. (void *) swrm,
  2682. &swrm_debug_dump_ops);
  2683. }
  2684. #endif
  2685. ret = device_init_wakeup(swrm->dev, true);
  2686. if (ret) {
  2687. dev_err(swrm->dev, "Device wakeup init failed: %d\n", ret);
  2688. goto err_irq_wakeup_fail;
  2689. }
  2690. pm_runtime_set_autosuspend_delay(&pdev->dev, auto_suspend_timer);
  2691. pm_runtime_use_autosuspend(&pdev->dev);
  2692. pm_runtime_set_active(&pdev->dev);
  2693. pm_runtime_enable(&pdev->dev);
  2694. pm_runtime_mark_last_busy(&pdev->dev);
  2695. INIT_WORK(&swrm->dc_presence_work, swrm_notify_work_fn);
  2696. swrm->event_notifier.notifier_call = swrm_event_notify;
  2697. //msm_aud_evt_register_client(&swrm->event_notifier);
  2698. return 0;
  2699. err_irq_wakeup_fail:
  2700. device_init_wakeup(swrm->dev, false);
  2701. err_parse_num_dev:
  2702. err_mstr_init_fail:
  2703. swr_unregister_master(&swrm->master);
  2704. err_mstr_fail:
  2705. if (swrm->reg_irq) {
  2706. swrm->reg_irq(swrm->handle, swr_mstr_interrupt,
  2707. swrm, SWR_IRQ_FREE);
  2708. } else if (swrm->irq) {
  2709. if (irq_get_irq_data(swrm->irq) != NULL)
  2710. irqd_set_trigger_type(
  2711. irq_get_irq_data(swrm->irq),
  2712. IRQ_TYPE_NONE);
  2713. if (swrm->swr_irq_wakeup_capable)
  2714. irq_set_irq_wake(swrm->irq, 0);
  2715. free_irq(swrm->irq, swrm);
  2716. }
  2717. err_irq_fail:
  2718. mutex_destroy(&swrm->irq_lock);
  2719. mutex_destroy(&swrm->mlock);
  2720. mutex_destroy(&swrm->reslock);
  2721. mutex_destroy(&swrm->force_down_lock);
  2722. mutex_destroy(&swrm->iolock);
  2723. mutex_destroy(&swrm->clklock);
  2724. mutex_destroy(&swrm->pm_lock);
  2725. err_pdata_fail:
  2726. err_memory_fail:
  2727. return ret;
  2728. }
  2729. static int swrm_remove(struct platform_device *pdev)
  2730. {
  2731. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  2732. if (swrm->reg_irq) {
  2733. swrm->reg_irq(swrm->handle, swr_mstr_interrupt,
  2734. swrm, SWR_IRQ_FREE);
  2735. } else if (swrm->irq) {
  2736. if (irq_get_irq_data(swrm->irq) != NULL)
  2737. irqd_set_trigger_type(
  2738. irq_get_irq_data(swrm->irq),
  2739. IRQ_TYPE_NONE);
  2740. if (swrm->swr_irq_wakeup_capable)
  2741. irq_set_irq_wake(swrm->irq, 0);
  2742. free_irq(swrm->irq, swrm);
  2743. } else if (swrm->wake_irq > 0) {
  2744. free_irq(swrm->wake_irq, swrm);
  2745. }
  2746. cancel_work_sync(&swrm->wakeup_work);
  2747. pm_runtime_disable(&pdev->dev);
  2748. pm_runtime_set_suspended(&pdev->dev);
  2749. swr_unregister_master(&swrm->master);
  2750. //msm_aud_evt_unregister_client(&swrm->event_notifier);
  2751. device_init_wakeup(swrm->dev, false);
  2752. mutex_destroy(&swrm->irq_lock);
  2753. mutex_destroy(&swrm->mlock);
  2754. mutex_destroy(&swrm->reslock);
  2755. mutex_destroy(&swrm->iolock);
  2756. mutex_destroy(&swrm->clklock);
  2757. mutex_destroy(&swrm->force_down_lock);
  2758. mutex_destroy(&swrm->pm_lock);
  2759. devm_kfree(&pdev->dev, swrm);
  2760. return 0;
  2761. }
  2762. static int swrm_clk_pause(struct swr_mstr_ctrl *swrm)
  2763. {
  2764. u32 val;
  2765. dev_dbg(swrm->dev, "%s: state: %d\n", __func__, swrm->state);
  2766. swr_master_write(swrm, SWRM_INTERRUPT_EN, 0x1FDFD);
  2767. val = swr_master_read(swrm, SWRM_MCP_CFG);
  2768. val |= 0x02;
  2769. swr_master_write(swrm, SWRM_MCP_CFG, val);
  2770. return 0;
  2771. }
  2772. #ifdef CONFIG_PM
  2773. static int swrm_runtime_resume(struct device *dev)
  2774. {
  2775. struct platform_device *pdev = to_platform_device(dev);
  2776. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  2777. int ret = 0;
  2778. bool swrm_clk_req_err = false;
  2779. bool hw_core_err = false, aud_core_err = false;
  2780. struct swr_master *mstr = &swrm->master;
  2781. struct swr_device *swr_dev;
  2782. u32 temp = 0, val = 0;
  2783. dev_dbg(dev, "%s: pm_runtime: resume, state:%d\n",
  2784. __func__, swrm->state);
  2785. trace_printk("%s: pm_runtime: resume, state:%d\n",
  2786. __func__, swrm->state);
  2787. mutex_lock(&swrm->reslock);
  2788. if (swrm_request_hw_vote(swrm, LPASS_HW_CORE, true)) {
  2789. dev_err(dev, "%s:lpass core hw enable failed\n",
  2790. __func__);
  2791. hw_core_err = true;
  2792. }
  2793. if (swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, true)) {
  2794. dev_err(dev, "%s:lpass audio hw enable failed\n",
  2795. __func__);
  2796. aud_core_err = true;
  2797. }
  2798. if ((swrm->state == SWR_MSTR_DOWN) ||
  2799. (swrm->state == SWR_MSTR_SSR && swrm->dev_up)) {
  2800. if (swrm->clk_stop_mode0_supp) {
  2801. if (swrm->wake_irq > 0) {
  2802. if (unlikely(!irq_get_irq_data
  2803. (swrm->wake_irq))) {
  2804. pr_err("%s: irq data is NULL\n",
  2805. __func__);
  2806. mutex_unlock(&swrm->reslock);
  2807. return IRQ_NONE;
  2808. }
  2809. mutex_lock(&swrm->irq_lock);
  2810. if (!irqd_irq_disabled(
  2811. irq_get_irq_data(swrm->wake_irq)))
  2812. disable_irq_nosync(swrm->wake_irq);
  2813. mutex_unlock(&swrm->irq_lock);
  2814. }
  2815. if (swrm->ipc_wakeup)
  2816. dev_err(dev, "%s:notifications disabled\n", __func__);
  2817. // msm_aud_evt_blocking_notifier_call_chain(
  2818. // SWR_WAKE_IRQ_DEREGISTER, (void *)swrm);
  2819. }
  2820. if (swrm_clk_request(swrm, true)) {
  2821. /*
  2822. * Set autosuspend timer to 1 for
  2823. * master to enter into suspend.
  2824. */
  2825. swrm_clk_req_err = true;
  2826. goto exit;
  2827. }
  2828. if (!swrm->clk_stop_mode0_supp || swrm->state == SWR_MSTR_SSR) {
  2829. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  2830. ret = swr_device_up(swr_dev);
  2831. if (ret == -ENODEV) {
  2832. dev_dbg(dev,
  2833. "%s slave device up not implemented\n",
  2834. __func__);
  2835. trace_printk(
  2836. "%s slave device up not implemented\n",
  2837. __func__);
  2838. ret = 0;
  2839. } else if (ret) {
  2840. dev_err(dev,
  2841. "%s: failed to wakeup swr dev %d\n",
  2842. __func__, swr_dev->dev_num);
  2843. swrm_clk_request(swrm, false);
  2844. goto exit;
  2845. }
  2846. }
  2847. swr_master_write(swrm, SWRM_COMP_SW_RESET, 0x01);
  2848. swr_master_write(swrm, SWRM_COMP_SW_RESET, 0x01);
  2849. swr_master_write(swrm, SWRM_MCP_BUS_CTRL, 0x01);
  2850. swrm_master_init(swrm);
  2851. /* wait for hw enumeration to complete */
  2852. usleep_range(100, 105);
  2853. if (!swrm_check_link_status(swrm, 0x1))
  2854. dev_dbg(dev, "%s:failed in connecting, ssr?\n",
  2855. __func__);
  2856. swrm_cmd_fifo_wr_cmd(swrm, 0x4, 0xF, 0x0,
  2857. SWRS_SCP_INT_STATUS_MASK_1);
  2858. if (swrm->state == SWR_MSTR_SSR) {
  2859. mutex_unlock(&swrm->reslock);
  2860. enable_bank_switch(swrm, 0, SWR_ROW_50, SWR_MIN_COL);
  2861. mutex_lock(&swrm->reslock);
  2862. }
  2863. } else {
  2864. if (swrm->swrm_hctl_reg) {
  2865. temp = ioread32(swrm->swrm_hctl_reg);
  2866. temp &= 0xFFFFFFFD;
  2867. iowrite32(temp, swrm->swrm_hctl_reg);
  2868. }
  2869. if (swrm->version < SWRM_VERSION_1_7)
  2870. val = 0x2;
  2871. else
  2872. val = 0x2 << swrm->ee_val;
  2873. /*wake up from clock stop*/
  2874. swr_master_write(swrm, SWRM_MCP_BUS_CTRL, val);
  2875. /* clear and enable bus clash interrupt */
  2876. swr_master_write(swrm, SWRM_INTERRUPT_CLEAR, 0x08);
  2877. swrm->intr_mask |= 0x08;
  2878. swr_master_write(swrm, SWRM_INTERRUPT_EN,
  2879. swrm->intr_mask);
  2880. swr_master_write(swrm,
  2881. SWRM_CPU1_INTERRUPT_EN,
  2882. swrm->intr_mask);
  2883. usleep_range(100, 105);
  2884. if (!swrm_check_link_status(swrm, 0x1))
  2885. dev_dbg(dev, "%s:failed in connecting, ssr?\n",
  2886. __func__);
  2887. }
  2888. swrm->state = SWR_MSTR_UP;
  2889. }
  2890. exit:
  2891. if (swrm->is_always_on && !aud_core_err)
  2892. swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, false);
  2893. if (!hw_core_err)
  2894. swrm_request_hw_vote(swrm, LPASS_HW_CORE, false);
  2895. if (swrm_clk_req_err)
  2896. pm_runtime_set_autosuspend_delay(&pdev->dev,
  2897. ERR_AUTO_SUSPEND_TIMER_VAL);
  2898. else
  2899. pm_runtime_set_autosuspend_delay(&pdev->dev,
  2900. auto_suspend_timer);
  2901. if (swrm->req_clk_switch)
  2902. swrm->req_clk_switch = false;
  2903. mutex_unlock(&swrm->reslock);
  2904. trace_printk("%s: pm_runtime: resume done, state:%d\n",
  2905. __func__, swrm->state);
  2906. return ret;
  2907. }
  2908. static int swrm_runtime_suspend(struct device *dev)
  2909. {
  2910. struct platform_device *pdev = to_platform_device(dev);
  2911. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  2912. int ret = 0;
  2913. bool hw_core_err = false, aud_core_err = false;
  2914. struct swr_master *mstr = &swrm->master;
  2915. struct swr_device *swr_dev;
  2916. int current_state = 0;
  2917. trace_printk("%s: pm_runtime: suspend state: %d\n",
  2918. __func__, swrm->state);
  2919. dev_dbg(dev, "%s: pm_runtime: suspend state: %d\n",
  2920. __func__, swrm->state);
  2921. mutex_lock(&swrm->reslock);
  2922. mutex_lock(&swrm->force_down_lock);
  2923. current_state = swrm->state;
  2924. mutex_unlock(&swrm->force_down_lock);
  2925. if (swrm_request_hw_vote(swrm, LPASS_HW_CORE, true)) {
  2926. dev_err(dev, "%s:lpass core hw enable failed\n",
  2927. __func__);
  2928. hw_core_err = true;
  2929. }
  2930. if (swrm->is_always_on && swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, true))
  2931. aud_core_err = true;
  2932. if ((current_state == SWR_MSTR_UP) ||
  2933. (current_state == SWR_MSTR_SSR)) {
  2934. if ((current_state != SWR_MSTR_SSR) &&
  2935. swrm_is_port_en(&swrm->master)) {
  2936. dev_dbg(dev, "%s ports are enabled\n", __func__);
  2937. trace_printk("%s ports are enabled\n", __func__);
  2938. ret = -EBUSY;
  2939. goto exit;
  2940. }
  2941. if (!swrm->clk_stop_mode0_supp || swrm->state == SWR_MSTR_SSR) {
  2942. dev_err(dev, "%s: clk stop mode not supported or SSR entry\n",
  2943. __func__);
  2944. mutex_unlock(&swrm->reslock);
  2945. enable_bank_switch(swrm, 0, SWR_ROW_50, SWR_MIN_COL);
  2946. mutex_lock(&swrm->reslock);
  2947. swrm_clk_pause(swrm);
  2948. swr_master_write(swrm, SWRM_COMP_CFG, 0x00);
  2949. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  2950. ret = swr_device_down(swr_dev);
  2951. if (ret == -ENODEV) {
  2952. dev_dbg_ratelimited(dev,
  2953. "%s slave device down not implemented\n",
  2954. __func__);
  2955. trace_printk(
  2956. "%s slave device down not implemented\n",
  2957. __func__);
  2958. ret = 0;
  2959. } else if (ret) {
  2960. dev_err(dev,
  2961. "%s: failed to shutdown swr dev %d\n",
  2962. __func__, swr_dev->dev_num);
  2963. trace_printk(
  2964. "%s: failed to shutdown swr dev %d\n",
  2965. __func__, swr_dev->dev_num);
  2966. goto exit;
  2967. }
  2968. }
  2969. trace_printk("%s: clk stop mode not supported or SSR exit\n",
  2970. __func__);
  2971. } else {
  2972. /* Mask bus clash interrupt */
  2973. swrm->intr_mask &= ~((u32)0x08);
  2974. swr_master_write(swrm, SWRM_INTERRUPT_EN,
  2975. swrm->intr_mask);
  2976. swr_master_write(swrm,
  2977. SWRM_CPU1_INTERRUPT_EN,
  2978. swrm->intr_mask);
  2979. mutex_unlock(&swrm->reslock);
  2980. /* clock stop sequence */
  2981. swrm_cmd_fifo_wr_cmd(swrm, 0x2, 0xF, 0xF,
  2982. SWRS_SCP_CONTROL);
  2983. mutex_lock(&swrm->reslock);
  2984. usleep_range(100, 105);
  2985. }
  2986. if (!swrm_check_link_status(swrm, 0x0))
  2987. dev_dbg(dev, "%s:failed in disconnecting, ssr?\n",
  2988. __func__);
  2989. ret = swrm_clk_request(swrm, false);
  2990. if (ret) {
  2991. dev_err(dev, "%s: swrmn clk failed\n", __func__);
  2992. ret = 0;
  2993. goto exit;
  2994. }
  2995. if (swrm->clk_stop_mode0_supp) {
  2996. if ((swrm->wake_irq > 0) &&
  2997. (irqd_irq_disabled(
  2998. irq_get_irq_data(swrm->wake_irq)))) {
  2999. enable_irq(swrm->wake_irq);
  3000. } else if (swrm->ipc_wakeup) {
  3001. //msm_aud_evt_blocking_notifier_call_chain(
  3002. // SWR_WAKE_IRQ_REGISTER, (void *)swrm);
  3003. dev_err(dev, "%s:notifications disabled\n", __func__);
  3004. swrm->ipc_wakeup_triggered = false;
  3005. }
  3006. }
  3007. }
  3008. /* Retain SSR state until resume */
  3009. if (current_state != SWR_MSTR_SSR)
  3010. swrm->state = SWR_MSTR_DOWN;
  3011. exit:
  3012. if (!swrm->is_always_on && swrm->state != SWR_MSTR_UP) {
  3013. if (swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, false))
  3014. dev_dbg(dev, "%s:lpass audio hw enable failed\n",
  3015. __func__);
  3016. } else if (swrm->is_always_on && !aud_core_err)
  3017. swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, false);
  3018. if (!hw_core_err)
  3019. swrm_request_hw_vote(swrm, LPASS_HW_CORE, false);
  3020. mutex_unlock(&swrm->reslock);
  3021. trace_printk("%s: pm_runtime: suspend done state: %d\n",
  3022. __func__, swrm->state);
  3023. return ret;
  3024. }
  3025. #endif /* CONFIG_PM */
  3026. static int swrm_device_suspend(struct device *dev)
  3027. {
  3028. struct platform_device *pdev = to_platform_device(dev);
  3029. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  3030. int ret = 0;
  3031. dev_dbg(dev, "%s: swrm state: %d\n", __func__, swrm->state);
  3032. trace_printk("%s: swrm state: %d\n", __func__, swrm->state);
  3033. if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
  3034. ret = swrm_runtime_suspend(dev);
  3035. if (!ret) {
  3036. pm_runtime_disable(dev);
  3037. pm_runtime_set_suspended(dev);
  3038. pm_runtime_enable(dev);
  3039. }
  3040. }
  3041. return 0;
  3042. }
  3043. static int swrm_device_down(struct device *dev)
  3044. {
  3045. struct platform_device *pdev = to_platform_device(dev);
  3046. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  3047. dev_dbg(dev, "%s: swrm state: %d\n", __func__, swrm->state);
  3048. trace_printk("%s: swrm state: %d\n", __func__, swrm->state);
  3049. mutex_lock(&swrm->force_down_lock);
  3050. swrm->state = SWR_MSTR_SSR;
  3051. mutex_unlock(&swrm->force_down_lock);
  3052. swrm_device_suspend(dev);
  3053. return 0;
  3054. }
  3055. int swrm_register_wake_irq(struct swr_mstr_ctrl *swrm)
  3056. {
  3057. int ret = 0;
  3058. int irq, dir_apps_irq;
  3059. if (!swrm->ipc_wakeup) {
  3060. irq = of_get_named_gpio(swrm->dev->of_node,
  3061. "qcom,swr-wakeup-irq", 0);
  3062. if (gpio_is_valid(irq)) {
  3063. swrm->wake_irq = gpio_to_irq(irq);
  3064. if (swrm->wake_irq < 0) {
  3065. dev_err(swrm->dev,
  3066. "Unable to configure irq\n");
  3067. return swrm->wake_irq;
  3068. }
  3069. } else {
  3070. dir_apps_irq = platform_get_irq_byname(swrm->pdev,
  3071. "swr_wake_irq");
  3072. if (dir_apps_irq < 0) {
  3073. dev_err(swrm->dev,
  3074. "TLMM connect gpio not found\n");
  3075. return -EINVAL;
  3076. }
  3077. swrm->wake_irq = dir_apps_irq;
  3078. }
  3079. ret = request_threaded_irq(swrm->wake_irq, NULL,
  3080. swrm_wakeup_interrupt,
  3081. IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
  3082. "swr_wake_irq", swrm);
  3083. if (ret) {
  3084. dev_err(swrm->dev, "%s: Failed to request irq %d\n",
  3085. __func__, ret);
  3086. return -EINVAL;
  3087. }
  3088. irq_set_irq_wake(swrm->wake_irq, 1);
  3089. }
  3090. return ret;
  3091. }
  3092. static int swrm_alloc_port_mem(struct device *dev, struct swr_mstr_ctrl *swrm,
  3093. u32 uc, u32 size)
  3094. {
  3095. if (!swrm->port_param) {
  3096. swrm->port_param = devm_kzalloc(dev,
  3097. sizeof(swrm->port_param) * SWR_UC_MAX,
  3098. GFP_KERNEL);
  3099. if (!swrm->port_param)
  3100. return -ENOMEM;
  3101. }
  3102. if (!swrm->port_param[uc]) {
  3103. swrm->port_param[uc] = devm_kcalloc(dev, size,
  3104. sizeof(struct port_params),
  3105. GFP_KERNEL);
  3106. if (!swrm->port_param[uc])
  3107. return -ENOMEM;
  3108. } else {
  3109. dev_err_ratelimited(swrm->dev, "%s: called more than once\n",
  3110. __func__);
  3111. }
  3112. return 0;
  3113. }
  3114. static int swrm_copy_port_config(struct swr_mstr_ctrl *swrm,
  3115. struct swrm_port_config *port_cfg,
  3116. u32 size)
  3117. {
  3118. int idx;
  3119. struct port_params *params;
  3120. int uc = port_cfg->uc;
  3121. int ret = 0;
  3122. for (idx = 0; idx < size; idx++) {
  3123. params = &((struct port_params *)port_cfg->params)[idx];
  3124. if (!params) {
  3125. dev_err(swrm->dev, "%s: Invalid params\n", __func__);
  3126. ret = -EINVAL;
  3127. break;
  3128. }
  3129. memcpy(&swrm->port_param[uc][idx], params,
  3130. sizeof(struct port_params));
  3131. }
  3132. return ret;
  3133. }
  3134. /**
  3135. * swrm_wcd_notify - parent device can notify to soundwire master through
  3136. * this function
  3137. * @pdev: pointer to platform device structure
  3138. * @id: command id from parent to the soundwire master
  3139. * @data: data from parent device to soundwire master
  3140. */
  3141. int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data)
  3142. {
  3143. struct swr_mstr_ctrl *swrm;
  3144. int ret = 0;
  3145. struct swr_master *mstr;
  3146. struct swr_device *swr_dev;
  3147. struct swrm_port_config *port_cfg;
  3148. if (!pdev) {
  3149. pr_err("%s: pdev is NULL\n", __func__);
  3150. return -EINVAL;
  3151. }
  3152. swrm = platform_get_drvdata(pdev);
  3153. if (!swrm) {
  3154. dev_err(&pdev->dev, "%s: swrm is NULL\n", __func__);
  3155. return -EINVAL;
  3156. }
  3157. mstr = &swrm->master;
  3158. switch (id) {
  3159. case SWR_REQ_CLK_SWITCH:
  3160. /* This will put soundwire in clock stop mode and disable the
  3161. * clocks, if there is no active usecase running, so that the
  3162. * next activity on soundwire will request clock from new clock
  3163. * source.
  3164. */
  3165. if (!data) {
  3166. dev_err(swrm->dev, "%s: data is NULL for id:%d\n",
  3167. __func__, id);
  3168. ret = -EINVAL;
  3169. break;
  3170. }
  3171. mutex_lock(&swrm->mlock);
  3172. if (swrm->clk_src != *(int *)data) {
  3173. if (swrm->state == SWR_MSTR_UP) {
  3174. swrm->req_clk_switch = true;
  3175. swrm_device_suspend(&pdev->dev);
  3176. if (swrm->state == SWR_MSTR_UP)
  3177. swrm->req_clk_switch = false;
  3178. }
  3179. swrm->clk_src = *(int *)data;
  3180. }
  3181. mutex_unlock(&swrm->mlock);
  3182. break;
  3183. case SWR_CLK_FREQ:
  3184. if (!data) {
  3185. dev_err(swrm->dev, "%s: data is NULL\n", __func__);
  3186. ret = -EINVAL;
  3187. } else {
  3188. mutex_lock(&swrm->mlock);
  3189. if (swrm->mclk_freq != *(int *)data) {
  3190. dev_dbg(swrm->dev, "%s: freq change: force mstr down\n", __func__);
  3191. if (swrm->state == SWR_MSTR_DOWN)
  3192. dev_dbg(swrm->dev, "%s:SWR master is already Down:%d\n",
  3193. __func__, swrm->state);
  3194. else {
  3195. swrm->mclk_freq = *(int *)data;
  3196. swrm->bus_clk = swrm->mclk_freq;
  3197. swrm_switch_frame_shape(swrm,
  3198. swrm->bus_clk);
  3199. swrm_device_suspend(&pdev->dev);
  3200. }
  3201. /*
  3202. * add delay to ensure clk release happen
  3203. * if interrupt triggered for clk stop,
  3204. * wait for it to exit
  3205. */
  3206. usleep_range(10000, 10500);
  3207. }
  3208. swrm->mclk_freq = *(int *)data;
  3209. swrm->bus_clk = swrm->mclk_freq;
  3210. mutex_unlock(&swrm->mlock);
  3211. }
  3212. break;
  3213. case SWR_DEVICE_SSR_DOWN:
  3214. trace_printk("%s: swr device down called\n", __func__);
  3215. mutex_lock(&swrm->mlock);
  3216. if (swrm->state == SWR_MSTR_DOWN)
  3217. dev_dbg(swrm->dev, "%s:SWR master is already Down:%d\n",
  3218. __func__, swrm->state);
  3219. else
  3220. swrm_device_down(&pdev->dev);
  3221. mutex_lock(&swrm->devlock);
  3222. swrm->dev_up = false;
  3223. swrm->hw_core_clk_en = 0;
  3224. swrm->aud_core_clk_en = 0;
  3225. mutex_unlock(&swrm->devlock);
  3226. mutex_lock(&swrm->reslock);
  3227. swrm->state = SWR_MSTR_SSR;
  3228. mutex_unlock(&swrm->reslock);
  3229. mutex_unlock(&swrm->mlock);
  3230. break;
  3231. case SWR_DEVICE_SSR_UP:
  3232. /* wait for clk voting to be zero */
  3233. trace_printk("%s: swr device up called\n", __func__);
  3234. reinit_completion(&swrm->clk_off_complete);
  3235. if (swrm->clk_ref_count &&
  3236. !wait_for_completion_timeout(&swrm->clk_off_complete,
  3237. msecs_to_jiffies(500)))
  3238. dev_err(swrm->dev, "%s: clock voting not zero\n",
  3239. __func__);
  3240. mutex_lock(&swrm->devlock);
  3241. swrm->dev_up = true;
  3242. mutex_unlock(&swrm->devlock);
  3243. break;
  3244. case SWR_DEVICE_DOWN:
  3245. dev_dbg(swrm->dev, "%s: swr master down called\n", __func__);
  3246. trace_printk("%s: swr master down called\n", __func__);
  3247. mutex_lock(&swrm->mlock);
  3248. if (swrm->state == SWR_MSTR_DOWN)
  3249. dev_dbg(swrm->dev, "%s:SWR master is already Down:%d\n",
  3250. __func__, swrm->state);
  3251. else
  3252. swrm_device_down(&pdev->dev);
  3253. mutex_unlock(&swrm->mlock);
  3254. break;
  3255. case SWR_DEVICE_UP:
  3256. dev_dbg(swrm->dev, "%s: swr master up called\n", __func__);
  3257. trace_printk("%s: swr master up called\n", __func__);
  3258. mutex_lock(&swrm->devlock);
  3259. if (!swrm->dev_up) {
  3260. dev_dbg(swrm->dev, "SSR not complete yet\n");
  3261. mutex_unlock(&swrm->devlock);
  3262. return -EBUSY;
  3263. }
  3264. mutex_unlock(&swrm->devlock);
  3265. mutex_lock(&swrm->mlock);
  3266. pm_runtime_mark_last_busy(&pdev->dev);
  3267. pm_runtime_get_sync(&pdev->dev);
  3268. mutex_lock(&swrm->reslock);
  3269. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  3270. ret = swr_reset_device(swr_dev);
  3271. if (ret == -ENODEV) {
  3272. dev_dbg_ratelimited(swrm->dev,
  3273. "%s slave reset not implemented\n",
  3274. __func__);
  3275. ret = 0;
  3276. } else if (ret) {
  3277. dev_err(swrm->dev,
  3278. "%s: failed to reset swr device %d\n",
  3279. __func__, swr_dev->dev_num);
  3280. swrm_clk_request(swrm, false);
  3281. }
  3282. }
  3283. pm_runtime_mark_last_busy(&pdev->dev);
  3284. pm_runtime_put_autosuspend(&pdev->dev);
  3285. mutex_unlock(&swrm->reslock);
  3286. mutex_unlock(&swrm->mlock);
  3287. break;
  3288. case SWR_SET_NUM_RX_CH:
  3289. if (!data) {
  3290. dev_err(swrm->dev, "%s: data is NULL\n", __func__);
  3291. ret = -EINVAL;
  3292. } else {
  3293. mutex_lock(&swrm->mlock);
  3294. swrm->num_rx_chs = *(int *)data;
  3295. if ((swrm->num_rx_chs > 1) && !swrm->num_cfg_devs) {
  3296. list_for_each_entry(swr_dev, &mstr->devices,
  3297. dev_list) {
  3298. ret = swr_set_device_group(swr_dev,
  3299. SWR_BROADCAST);
  3300. if (ret)
  3301. dev_err(swrm->dev,
  3302. "%s: set num ch failed\n",
  3303. __func__);
  3304. }
  3305. } else {
  3306. list_for_each_entry(swr_dev, &mstr->devices,
  3307. dev_list) {
  3308. ret = swr_set_device_group(swr_dev,
  3309. SWR_GROUP_NONE);
  3310. if (ret)
  3311. dev_err(swrm->dev,
  3312. "%s: set num ch failed\n",
  3313. __func__);
  3314. }
  3315. }
  3316. mutex_unlock(&swrm->mlock);
  3317. }
  3318. break;
  3319. case SWR_REGISTER_WAKE_IRQ:
  3320. if (!data) {
  3321. dev_err(swrm->dev, "%s: reg wake irq data is NULL\n",
  3322. __func__);
  3323. ret = -EINVAL;
  3324. } else {
  3325. mutex_lock(&swrm->mlock);
  3326. swrm->ipc_wakeup = *(u32 *)data;
  3327. ret = swrm_register_wake_irq(swrm);
  3328. if (ret)
  3329. dev_err(swrm->dev, "%s: register wake_irq failed\n",
  3330. __func__);
  3331. mutex_unlock(&swrm->mlock);
  3332. }
  3333. break;
  3334. case SWR_REGISTER_WAKEUP:
  3335. //msm_aud_evt_blocking_notifier_call_chain(
  3336. // SWR_WAKE_IRQ_REGISTER, (void *)swrm);
  3337. break;
  3338. case SWR_DEREGISTER_WAKEUP:
  3339. //msm_aud_evt_blocking_notifier_call_chain(
  3340. // SWR_WAKE_IRQ_DEREGISTER, (void *)swrm);
  3341. break;
  3342. case SWR_SET_PORT_MAP:
  3343. if (!data) {
  3344. dev_err(swrm->dev, "%s: data is NULL for id=%d\n",
  3345. __func__, id);
  3346. ret = -EINVAL;
  3347. } else {
  3348. mutex_lock(&swrm->mlock);
  3349. port_cfg = (struct swrm_port_config *)data;
  3350. if (!port_cfg->size) {
  3351. ret = -EINVAL;
  3352. goto done;
  3353. }
  3354. ret = swrm_alloc_port_mem(&pdev->dev, swrm,
  3355. port_cfg->uc, port_cfg->size);
  3356. if (!ret)
  3357. swrm_copy_port_config(swrm, port_cfg,
  3358. port_cfg->size);
  3359. done:
  3360. mutex_unlock(&swrm->mlock);
  3361. }
  3362. break;
  3363. default:
  3364. dev_err(swrm->dev, "%s: swr master unknown id %d\n",
  3365. __func__, id);
  3366. break;
  3367. }
  3368. return ret;
  3369. }
  3370. EXPORT_SYMBOL(swrm_wcd_notify);
  3371. /*
  3372. * swrm_pm_cmpxchg:
  3373. * Check old state and exchange with pm new state
  3374. * if old state matches with current state
  3375. *
  3376. * @swrm: pointer to wcd core resource
  3377. * @o: pm old state
  3378. * @n: pm new state
  3379. *
  3380. * Returns old state
  3381. */
  3382. static enum swrm_pm_state swrm_pm_cmpxchg(
  3383. struct swr_mstr_ctrl *swrm,
  3384. enum swrm_pm_state o,
  3385. enum swrm_pm_state n)
  3386. {
  3387. enum swrm_pm_state old;
  3388. if (!swrm)
  3389. return o;
  3390. mutex_lock(&swrm->pm_lock);
  3391. old = swrm->pm_state;
  3392. if (old == o)
  3393. swrm->pm_state = n;
  3394. mutex_unlock(&swrm->pm_lock);
  3395. return old;
  3396. }
  3397. static bool swrm_lock_sleep(struct swr_mstr_ctrl *swrm)
  3398. {
  3399. enum swrm_pm_state os;
  3400. /*
  3401. * swrm_{lock/unlock}_sleep will be called by swr irq handler
  3402. * and slave wake up requests..
  3403. *
  3404. * If system didn't resume, we can simply return false so
  3405. * IRQ handler can return without handling IRQ.
  3406. */
  3407. mutex_lock(&swrm->pm_lock);
  3408. if (swrm->wlock_holders++ == 0) {
  3409. dev_dbg(swrm->dev, "%s: holding wake lock\n", __func__);
  3410. pm_stay_awake(swrm->dev);
  3411. }
  3412. mutex_unlock(&swrm->pm_lock);
  3413. if (!wait_event_timeout(swrm->pm_wq,
  3414. ((os = swrm_pm_cmpxchg(swrm,
  3415. SWRM_PM_SLEEPABLE,
  3416. SWRM_PM_AWAKE)) ==
  3417. SWRM_PM_SLEEPABLE ||
  3418. (os == SWRM_PM_AWAKE)),
  3419. msecs_to_jiffies(
  3420. SWRM_SYSTEM_RESUME_TIMEOUT_MS))) {
  3421. dev_err(swrm->dev, "%s: system didn't resume within %dms, s %d, w %d\n",
  3422. __func__, SWRM_SYSTEM_RESUME_TIMEOUT_MS, swrm->pm_state,
  3423. swrm->wlock_holders);
  3424. swrm_unlock_sleep(swrm);
  3425. return false;
  3426. }
  3427. wake_up_all(&swrm->pm_wq);
  3428. return true;
  3429. }
  3430. static void swrm_unlock_sleep(struct swr_mstr_ctrl *swrm)
  3431. {
  3432. mutex_lock(&swrm->pm_lock);
  3433. if (--swrm->wlock_holders == 0) {
  3434. dev_dbg(swrm->dev, "%s: releasing wake lock pm_state %d -> %d\n",
  3435. __func__, swrm->pm_state, SWRM_PM_SLEEPABLE);
  3436. /*
  3437. * if swrm_lock_sleep failed, pm_state would be still
  3438. * swrm_PM_ASLEEP, don't overwrite
  3439. */
  3440. if (likely(swrm->pm_state == SWRM_PM_AWAKE))
  3441. swrm->pm_state = SWRM_PM_SLEEPABLE;
  3442. pm_relax(swrm->dev);
  3443. }
  3444. mutex_unlock(&swrm->pm_lock);
  3445. wake_up_all(&swrm->pm_wq);
  3446. }
  3447. #ifdef CONFIG_PM_SLEEP
  3448. static int swrm_suspend(struct device *dev)
  3449. {
  3450. int ret = -EBUSY;
  3451. struct platform_device *pdev = to_platform_device(dev);
  3452. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  3453. dev_dbg(dev, "%s: system suspend, state: %d\n", __func__, swrm->state);
  3454. mutex_lock(&swrm->pm_lock);
  3455. if (swrm->pm_state == SWRM_PM_SLEEPABLE) {
  3456. dev_dbg(swrm->dev, "%s: suspending system, state %d, wlock %d\n",
  3457. __func__, swrm->pm_state,
  3458. swrm->wlock_holders);
  3459. swrm->pm_state = SWRM_PM_ASLEEP;
  3460. } else if (swrm->pm_state == SWRM_PM_AWAKE) {
  3461. /*
  3462. * unlock to wait for pm_state == SWRM_PM_SLEEPABLE
  3463. * then set to SWRM_PM_ASLEEP
  3464. */
  3465. dev_dbg(swrm->dev, "%s: waiting to suspend system, state %d, wlock %d\n",
  3466. __func__, swrm->pm_state,
  3467. swrm->wlock_holders);
  3468. mutex_unlock(&swrm->pm_lock);
  3469. if (!(wait_event_timeout(swrm->pm_wq, swrm_pm_cmpxchg(
  3470. swrm, SWRM_PM_SLEEPABLE,
  3471. SWRM_PM_ASLEEP) ==
  3472. SWRM_PM_SLEEPABLE,
  3473. msecs_to_jiffies(
  3474. SWRM_SYS_SUSPEND_WAIT)))) {
  3475. dev_dbg(swrm->dev, "%s: suspend failed state %d, wlock %d\n",
  3476. __func__, swrm->pm_state,
  3477. swrm->wlock_holders);
  3478. return -EBUSY;
  3479. } else {
  3480. dev_dbg(swrm->dev,
  3481. "%s: done, state %d, wlock %d\n",
  3482. __func__, swrm->pm_state,
  3483. swrm->wlock_holders);
  3484. }
  3485. mutex_lock(&swrm->pm_lock);
  3486. } else if (swrm->pm_state == SWRM_PM_ASLEEP) {
  3487. dev_dbg(swrm->dev, "%s: system is already suspended, state %d, wlock %d\n",
  3488. __func__, swrm->pm_state,
  3489. swrm->wlock_holders);
  3490. }
  3491. mutex_unlock(&swrm->pm_lock);
  3492. if ((!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev))) {
  3493. ret = swrm_runtime_suspend(dev);
  3494. if (!ret) {
  3495. /*
  3496. * Synchronize runtime-pm and system-pm states:
  3497. * At this point, we are already suspended. If
  3498. * runtime-pm still thinks its active, then
  3499. * make sure its status is in sync with HW
  3500. * status. The three below calls let the
  3501. * runtime-pm know that we are suspended
  3502. * already without re-invoking the suspend
  3503. * callback
  3504. */
  3505. pm_runtime_disable(dev);
  3506. pm_runtime_set_suspended(dev);
  3507. pm_runtime_enable(dev);
  3508. }
  3509. }
  3510. if (ret == -EBUSY) {
  3511. /*
  3512. * There is a possibility that some audio stream is active
  3513. * during suspend. We dont want to return suspend failure in
  3514. * that case so that display and relevant components can still
  3515. * go to suspend.
  3516. * If there is some other error, then it should be passed-on
  3517. * to system level suspend
  3518. */
  3519. ret = 0;
  3520. }
  3521. return ret;
  3522. }
  3523. static int swrm_resume(struct device *dev)
  3524. {
  3525. int ret = 0;
  3526. struct platform_device *pdev = to_platform_device(dev);
  3527. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  3528. dev_dbg(dev, "%s: system resume, state: %d\n", __func__, swrm->state);
  3529. if (!pm_runtime_enabled(dev) || !pm_runtime_suspend(dev)) {
  3530. ret = swrm_runtime_resume(dev);
  3531. if (!ret) {
  3532. pm_runtime_mark_last_busy(dev);
  3533. pm_request_autosuspend(dev);
  3534. }
  3535. }
  3536. mutex_lock(&swrm->pm_lock);
  3537. if (swrm->pm_state == SWRM_PM_ASLEEP) {
  3538. dev_dbg(swrm->dev,
  3539. "%s: resuming system, state %d, wlock %d\n",
  3540. __func__, swrm->pm_state,
  3541. swrm->wlock_holders);
  3542. swrm->pm_state = SWRM_PM_SLEEPABLE;
  3543. } else {
  3544. dev_dbg(swrm->dev, "%s: system is already awake, state %d wlock %d\n",
  3545. __func__, swrm->pm_state,
  3546. swrm->wlock_holders);
  3547. }
  3548. mutex_unlock(&swrm->pm_lock);
  3549. wake_up_all(&swrm->pm_wq);
  3550. return ret;
  3551. }
  3552. #endif /* CONFIG_PM_SLEEP */
  3553. static const struct dev_pm_ops swrm_dev_pm_ops = {
  3554. SET_SYSTEM_SLEEP_PM_OPS(
  3555. swrm_suspend,
  3556. swrm_resume
  3557. )
  3558. SET_RUNTIME_PM_OPS(
  3559. swrm_runtime_suspend,
  3560. swrm_runtime_resume,
  3561. NULL
  3562. )
  3563. };
  3564. static const struct of_device_id swrm_dt_match[] = {
  3565. {
  3566. .compatible = "qcom,swr-mstr",
  3567. },
  3568. {}
  3569. };
  3570. static struct platform_driver swr_mstr_driver = {
  3571. .probe = swrm_probe,
  3572. .remove = swrm_remove,
  3573. .driver = {
  3574. .name = SWR_WCD_NAME,
  3575. .owner = THIS_MODULE,
  3576. .pm = &swrm_dev_pm_ops,
  3577. .of_match_table = swrm_dt_match,
  3578. .suppress_bind_attrs = true,
  3579. },
  3580. };
  3581. static int __init swrm_init(void)
  3582. {
  3583. return platform_driver_register(&swr_mstr_driver);
  3584. }
  3585. module_init(swrm_init);
  3586. static void __exit swrm_exit(void)
  3587. {
  3588. platform_driver_unregister(&swr_mstr_driver);
  3589. }
  3590. module_exit(swrm_exit);
  3591. MODULE_LICENSE("GPL v2");
  3592. MODULE_DESCRIPTION("SoundWire Master Controller");
  3593. MODULE_ALIAS("platform:swr-mstr");