b5f74912c1
In the case of WCN6450, WBM HW block is removed in the UMAC. TX completions come via HTT messages. Add logic to handle HTT TX completion messages from the firmware. Changes are specific to WCN6450 and hence implement the logic in the arch specific code. Change-Id: I447020354ce26e8948e4b49648c434fb2ed302cd CRs-Fixed: 3381814
168 行
5.3 KiB
C
168 行
5.3 KiB
C
/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __DP_RH_TX_H
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#define __DP_RH_TX_H
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#include <dp_types.h>
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#define DP_RH_TX_HDR_SIZE_NATIVE_WIFI 30
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#define DP_RH_TX_HDR_SIZE_802_11_RAW 36
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#define DP_RH_TX_HDR_SIZE_ETHERNET 14
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#define DP_RH_TX_HDR_SIZE_IP 16
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#define DP_RH_TX_HDR_SIZE_802_1Q 4
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#define DP_RH_TX_HDR_SIZE_LLC_SNAP 8
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#define DP_RH_TX_HDR_SIZE_OUTER_HDR_MAX DP_RH_TX_HDR_SIZE_802_11_RAW
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#define DP_RH_TX_TLV_HDR_SIZE sizeof(struct tlv_32_hdr)
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#define DP_RH_TX_TCL_DESC_SIZE (HAL_TX_DESC_LEN_BYTES + DP_RH_TX_TLV_HDR_SIZE)
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/*
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* NB: intentionally not using kernel-doc comment because the kernel-doc
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* script does not handle the qdf_dma_mem_context macro
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* struct dp_tx_tcl_desc_pool_s - Tx Extension Descriptor Pool
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* @elem_count: Number of descriptors in the pool
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* @elem_size: Size of each descriptor
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* @desc_pages: multiple page allocation information for actual descriptors
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* @freelist: freelist of TCL descriptors
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* @memctx:
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*/
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struct dp_tx_tcl_desc_pool_s {
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uint16_t elem_count;
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int elem_size;
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struct qdf_mem_multi_page_t desc_pages;
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uint32_t *freelist;
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qdf_dma_mem_context(memctx);
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};
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/**
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* dp_tx_hw_enqueue_rh() - Enqueue to TCL HW for transmit
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* @soc: DP Soc Handle
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* @vdev: DP vdev handle
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* @tx_desc: Tx Descriptor Handle
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* @fw_metadata: Metadata to send to Target Firmware along with frame
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* @tx_exc_metadata: Handle that holds exception path meta data
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* @msdu_info: Holds the MSDU information to be transmitted
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*
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* Gets the next free TCL HW DMA descriptor and sets up required parameters
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* from software Tx descriptor
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*
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* Return: QDF_STATUS_SUCCESS: success
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* QDF_STATUS_E_RESOURCES: Error return
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*/
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QDF_STATUS
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dp_tx_hw_enqueue_rh(struct dp_soc *soc, struct dp_vdev *vdev,
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struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
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struct cdp_tx_exception_metadata *tx_exc_metadata,
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struct dp_tx_msdu_info_s *msdu_info);
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/**
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* dp_tx_comp_get_params_from_hal_desc_rh() - Get TX desc from HAL comp desc
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* @soc: DP soc handle
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* @tx_comp_hal_desc: HAL TX Comp Descriptor
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* @r_tx_desc: SW Tx Descriptor retrieved from HAL desc.
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*
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* Return: None
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*/
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void dp_tx_comp_get_params_from_hal_desc_rh(struct dp_soc *soc,
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void *tx_comp_hal_desc,
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struct dp_tx_desc_s **r_tx_desc);
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/**
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* dp_tx_process_htt_completion_rh() - Tx HTT Completion Indication Handler
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* @soc: Handle to DP soc structure
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* @tx_desc: software descriptor head pointer
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* @status : Tx completion status from HTT descriptor
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* @ring_id: ring number
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*
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* This function will process HTT Tx indication messages from Target
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*
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* Return: none
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*/
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void dp_tx_process_htt_completion_rh(struct dp_soc *soc,
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struct dp_tx_desc_s *tx_desc,
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uint8_t *status,
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uint8_t ring_id);
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/**
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* dp_tx_desc_pool_init_rh() - Initialize Tx Descriptor pool(s)
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* @soc: Handle to DP Soc structure
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* @num_elem: pool descriptor number
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* @pool_id: pool to allocate
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*
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* Return: QDF_STATUS_SUCCESS - success, others - failure
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*/
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QDF_STATUS dp_tx_desc_pool_init_rh(struct dp_soc *soc,
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uint32_t num_elem,
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uint8_t pool_id);
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/**
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* dp_tx_desc_pool_deinit_rh() - De-initialize Tx Descriptor pool(s)
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* @soc: Handle to DP Soc structure
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* @tx_desc_pool: Tx descriptor pool handler
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* @pool_id: pool to deinit
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*
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* Return: None.
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*/
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void dp_tx_desc_pool_deinit_rh(struct dp_soc *soc,
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struct dp_tx_desc_pool_s *tx_desc_pool,
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uint8_t pool_id);
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/**
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* dp_tx_compute_tx_delay_rh() - Compute HW Tx completion delay
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* @soc: Handle to DP Soc structure
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* @vdev: vdev
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* @ts: Tx completion status
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* @delay_us: Delay to be calculated in microseconds
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*
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* Return: QDF_STATUS
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*/
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QDF_STATUS dp_tx_compute_tx_delay_rh(struct dp_soc *soc,
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struct dp_vdev *vdev,
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struct hal_tx_completion_status *ts,
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uint32_t *delay_us);
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/**
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* dp_tx_desc_pool_alloc_rh() - Allocate coherent memory for TCL descriptors
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* @soc: Handle to DP Soc structure
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* @num_elem: Number of elements to allocate
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* @pool_id: TCL descriptor pool ID
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*
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* Return: QDF_STATUS_SUCCESS - success, others - failure
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*/
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QDF_STATUS dp_tx_desc_pool_alloc_rh(struct dp_soc *soc, uint32_t num_elem,
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uint8_t pool_id);
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/**
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* dp_tx_desc_pool_free_rh() - Free TCL descriptor memory
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* @soc: Handle to DP Soc structure
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* @pool_id: TCL descriptor pool ID
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*
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* Return: none
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*/
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void dp_tx_desc_pool_free_rh(struct dp_soc *soc, uint8_t pool_id);
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/**
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* dp_tx_compl_handler_rh() - TX completion handler for Rhine
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* @soc: Handle to DP Soc structure
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* @htt_msg: TX completion HTT message
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*
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* Return: none
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*/
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void dp_tx_compl_handler_rh(struct dp_soc *soc, qdf_nbuf_t htt_msg);
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#endif
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