dp_tx.c 112 KB

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  1. /*
  2. * Copyright (c) 2015-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "enet.h"
  33. #include "dp_internal.h"
  34. #define DP_TX_QUEUE_MASK 0x3
  35. /* TODO Add support in TSO */
  36. #define DP_DESC_NUM_FRAG(x) 0
  37. /* disable TQM_BYPASS */
  38. #define TQM_BYPASS_WAR 0
  39. /* invalid peer id for reinject*/
  40. #define DP_INVALID_PEER 0XFFFE
  41. /*mapping between hal encrypt type and cdp_sec_type*/
  42. #define MAX_CDP_SEC_TYPE 12
  43. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  44. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  45. HAL_TX_ENCRYPT_TYPE_WEP_128,
  46. HAL_TX_ENCRYPT_TYPE_WEP_104,
  47. HAL_TX_ENCRYPT_TYPE_WEP_40,
  48. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  49. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  50. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  51. HAL_TX_ENCRYPT_TYPE_WAPI,
  52. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  53. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  54. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  55. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  56. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  57. #include "dp_tx_capture.h"
  58. #endif
  59. /**
  60. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  61. * @vdev: DP Virtual device handle
  62. * @nbuf: Buffer pointer
  63. * @queue: queue ids container for nbuf
  64. *
  65. * TX packet queue has 2 instances, software descriptors id and dma ring id
  66. * Based on tx feature and hardware configuration queue id combination could be
  67. * different.
  68. * For example -
  69. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  70. * With no XPS,lock based resource protection, Descriptor pool ids are different
  71. * for each vdev, dma ring id will be same as single pdev id
  72. *
  73. * Return: None
  74. */
  75. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  76. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  77. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  78. {
  79. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  80. queue->desc_pool_id = queue_offset;
  81. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  82. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  83. "%s, pool_id:%d ring_id: %d",
  84. __func__, queue->desc_pool_id, queue->ring_id);
  85. return;
  86. }
  87. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  88. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  89. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  90. {
  91. /* get flow id */
  92. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  93. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  94. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  95. "%s, pool_id:%d ring_id: %d",
  96. __func__, queue->desc_pool_id, queue->ring_id);
  97. return;
  98. }
  99. #endif
  100. #if defined(FEATURE_TSO)
  101. /**
  102. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  103. *
  104. * @soc - core txrx main context
  105. * @seg_desc - tso segment descriptor
  106. * @num_seg_desc - tso number segment descriptor
  107. */
  108. static void dp_tx_tso_unmap_segment(
  109. struct dp_soc *soc,
  110. struct qdf_tso_seg_elem_t *seg_desc,
  111. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  112. {
  113. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  114. if (qdf_unlikely(!seg_desc)) {
  115. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  116. __func__, __LINE__);
  117. qdf_assert(0);
  118. } else if (qdf_unlikely(!num_seg_desc)) {
  119. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  120. __func__, __LINE__);
  121. qdf_assert(0);
  122. } else {
  123. bool is_last_seg;
  124. /* no tso segment left to do dma unmap */
  125. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  126. return;
  127. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  128. true : false;
  129. qdf_nbuf_unmap_tso_segment(soc->osdev,
  130. seg_desc, is_last_seg);
  131. num_seg_desc->num_seg.tso_cmn_num_seg--;
  132. }
  133. }
  134. /**
  135. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  136. * back to the freelist
  137. *
  138. * @soc - soc device handle
  139. * @tx_desc - Tx software descriptor
  140. */
  141. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  142. struct dp_tx_desc_s *tx_desc)
  143. {
  144. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  145. if (qdf_unlikely(!tx_desc->tso_desc)) {
  146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  147. "%s %d TSO desc is NULL!",
  148. __func__, __LINE__);
  149. qdf_assert(0);
  150. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  151. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  152. "%s %d TSO num desc is NULL!",
  153. __func__, __LINE__);
  154. qdf_assert(0);
  155. } else {
  156. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  157. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  158. /* Add the tso num segment into the free list */
  159. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  160. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  161. tx_desc->tso_num_desc);
  162. tx_desc->tso_num_desc = NULL;
  163. }
  164. /* Add the tso segment into the free list*/
  165. dp_tx_tso_desc_free(soc,
  166. tx_desc->pool_id, tx_desc->tso_desc);
  167. tx_desc->tso_desc = NULL;
  168. }
  169. }
  170. #else
  171. static void dp_tx_tso_unmap_segment(
  172. struct dp_soc *soc,
  173. struct qdf_tso_seg_elem_t *seg_desc,
  174. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  175. {
  176. }
  177. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  178. struct dp_tx_desc_s *tx_desc)
  179. {
  180. }
  181. #endif
  182. /**
  183. * dp_tx_desc_release() - Release Tx Descriptor
  184. * @tx_desc : Tx Descriptor
  185. * @desc_pool_id: Descriptor Pool ID
  186. *
  187. * Deallocate all resources attached to Tx descriptor and free the Tx
  188. * descriptor.
  189. *
  190. * Return:
  191. */
  192. void
  193. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  194. {
  195. struct dp_pdev *pdev = tx_desc->pdev;
  196. struct dp_soc *soc;
  197. uint8_t comp_status = 0;
  198. qdf_assert(pdev);
  199. soc = pdev->soc;
  200. if (tx_desc->frm_type == dp_tx_frm_tso)
  201. dp_tx_tso_desc_release(soc, tx_desc);
  202. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  203. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  204. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  205. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  206. qdf_atomic_dec(&pdev->num_tx_outstanding);
  207. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  208. qdf_atomic_dec(&pdev->num_tx_exception);
  209. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  210. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  211. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  212. soc->hal_soc);
  213. else
  214. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  215. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  216. "Tx Completion Release desc %d status %d outstanding %d",
  217. tx_desc->id, comp_status,
  218. qdf_atomic_read(&pdev->num_tx_outstanding));
  219. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  220. return;
  221. }
  222. /**
  223. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  224. * @vdev: DP vdev Handle
  225. * @nbuf: skb
  226. *
  227. * Prepares and fills HTT metadata in the frame pre-header for special frames
  228. * that should be transmitted using varying transmit parameters.
  229. * There are 2 VDEV modes that currently needs this special metadata -
  230. * 1) Mesh Mode
  231. * 2) DSRC Mode
  232. *
  233. * Return: HTT metadata size
  234. *
  235. */
  236. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  237. uint32_t *meta_data)
  238. {
  239. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  240. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  241. uint8_t htt_desc_size;
  242. /* Size rounded of multiple of 8 bytes */
  243. uint8_t htt_desc_size_aligned;
  244. uint8_t *hdr = NULL;
  245. /*
  246. * Metadata - HTT MSDU Extension header
  247. */
  248. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  249. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  250. if (vdev->mesh_vdev) {
  251. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  252. htt_desc_size_aligned)) {
  253. DP_STATS_INC(vdev,
  254. tx_i.dropped.headroom_insufficient, 1);
  255. return 0;
  256. }
  257. /* Fill and add HTT metaheader */
  258. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  259. if (!hdr) {
  260. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  261. "Error in filling HTT metadata");
  262. return 0;
  263. }
  264. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  265. } else if (vdev->opmode == wlan_op_mode_ocb) {
  266. /* Todo - Add support for DSRC */
  267. }
  268. return htt_desc_size_aligned;
  269. }
  270. /**
  271. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  272. * @tso_seg: TSO segment to process
  273. * @ext_desc: Pointer to MSDU extension descriptor
  274. *
  275. * Return: void
  276. */
  277. #if defined(FEATURE_TSO)
  278. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  279. void *ext_desc)
  280. {
  281. uint8_t num_frag;
  282. uint32_t tso_flags;
  283. /*
  284. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  285. * tcp_flag_mask
  286. *
  287. * Checksum enable flags are set in TCL descriptor and not in Extension
  288. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  289. */
  290. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  291. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  292. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  293. tso_seg->tso_flags.ip_len);
  294. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  295. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  296. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  297. uint32_t lo = 0;
  298. uint32_t hi = 0;
  299. qdf_dmaaddr_to_32s(
  300. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  301. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  302. tso_seg->tso_frags[num_frag].length);
  303. }
  304. return;
  305. }
  306. #else
  307. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  308. void *ext_desc)
  309. {
  310. return;
  311. }
  312. #endif
  313. #if defined(FEATURE_TSO)
  314. /**
  315. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  316. * allocated and free them
  317. *
  318. * @soc: soc handle
  319. * @free_seg: list of tso segments
  320. * @msdu_info: msdu descriptor
  321. *
  322. * Return - void
  323. */
  324. static void dp_tx_free_tso_seg_list(
  325. struct dp_soc *soc,
  326. struct qdf_tso_seg_elem_t *free_seg,
  327. struct dp_tx_msdu_info_s *msdu_info)
  328. {
  329. struct qdf_tso_seg_elem_t *next_seg;
  330. while (free_seg) {
  331. next_seg = free_seg->next;
  332. dp_tx_tso_desc_free(soc,
  333. msdu_info->tx_queue.desc_pool_id,
  334. free_seg);
  335. free_seg = next_seg;
  336. }
  337. }
  338. /**
  339. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  340. * allocated and free them
  341. *
  342. * @soc: soc handle
  343. * @free_num_seg: list of tso number segments
  344. * @msdu_info: msdu descriptor
  345. * Return - void
  346. */
  347. static void dp_tx_free_tso_num_seg_list(
  348. struct dp_soc *soc,
  349. struct qdf_tso_num_seg_elem_t *free_num_seg,
  350. struct dp_tx_msdu_info_s *msdu_info)
  351. {
  352. struct qdf_tso_num_seg_elem_t *next_num_seg;
  353. while (free_num_seg) {
  354. next_num_seg = free_num_seg->next;
  355. dp_tso_num_seg_free(soc,
  356. msdu_info->tx_queue.desc_pool_id,
  357. free_num_seg);
  358. free_num_seg = next_num_seg;
  359. }
  360. }
  361. /**
  362. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  363. * do dma unmap for each segment
  364. *
  365. * @soc: soc handle
  366. * @free_seg: list of tso segments
  367. * @num_seg_desc: tso number segment descriptor
  368. *
  369. * Return - void
  370. */
  371. static void dp_tx_unmap_tso_seg_list(
  372. struct dp_soc *soc,
  373. struct qdf_tso_seg_elem_t *free_seg,
  374. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  375. {
  376. struct qdf_tso_seg_elem_t *next_seg;
  377. if (qdf_unlikely(!num_seg_desc)) {
  378. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  379. return;
  380. }
  381. while (free_seg) {
  382. next_seg = free_seg->next;
  383. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  384. free_seg = next_seg;
  385. }
  386. }
  387. /**
  388. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  389. * free the tso segments descriptor and
  390. * tso num segments descriptor
  391. *
  392. * @soc: soc handle
  393. * @msdu_info: msdu descriptor
  394. * @tso_seg_unmap: flag to show if dma unmap is necessary
  395. *
  396. * Return - void
  397. */
  398. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  399. struct dp_tx_msdu_info_s *msdu_info,
  400. bool tso_seg_unmap)
  401. {
  402. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  403. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  404. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  405. tso_info->tso_num_seg_list;
  406. /* do dma unmap for each segment */
  407. if (tso_seg_unmap)
  408. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  409. /* free all tso number segment descriptor though looks only have 1 */
  410. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  411. /* free all tso segment descriptor */
  412. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  413. }
  414. /**
  415. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  416. * @vdev: virtual device handle
  417. * @msdu: network buffer
  418. * @msdu_info: meta data associated with the msdu
  419. *
  420. * Return: QDF_STATUS_SUCCESS success
  421. */
  422. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  423. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  424. {
  425. struct qdf_tso_seg_elem_t *tso_seg;
  426. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  427. struct dp_soc *soc = vdev->pdev->soc;
  428. struct qdf_tso_info_t *tso_info;
  429. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  430. tso_info = &msdu_info->u.tso_info;
  431. tso_info->curr_seg = NULL;
  432. tso_info->tso_seg_list = NULL;
  433. tso_info->num_segs = num_seg;
  434. msdu_info->frm_type = dp_tx_frm_tso;
  435. tso_info->tso_num_seg_list = NULL;
  436. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  437. while (num_seg) {
  438. tso_seg = dp_tx_tso_desc_alloc(
  439. soc, msdu_info->tx_queue.desc_pool_id);
  440. if (tso_seg) {
  441. tso_seg->next = tso_info->tso_seg_list;
  442. tso_info->tso_seg_list = tso_seg;
  443. num_seg--;
  444. } else {
  445. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  446. __func__);
  447. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  448. return QDF_STATUS_E_NOMEM;
  449. }
  450. }
  451. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  452. tso_num_seg = dp_tso_num_seg_alloc(soc,
  453. msdu_info->tx_queue.desc_pool_id);
  454. if (tso_num_seg) {
  455. tso_num_seg->next = tso_info->tso_num_seg_list;
  456. tso_info->tso_num_seg_list = tso_num_seg;
  457. } else {
  458. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  459. __func__);
  460. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  461. return QDF_STATUS_E_NOMEM;
  462. }
  463. msdu_info->num_seg =
  464. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  465. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  466. msdu_info->num_seg);
  467. if (!(msdu_info->num_seg)) {
  468. /*
  469. * Free allocated TSO seg desc and number seg desc,
  470. * do unmap for segments if dma map has done.
  471. */
  472. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  473. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  474. return QDF_STATUS_E_INVAL;
  475. }
  476. tso_info->curr_seg = tso_info->tso_seg_list;
  477. return QDF_STATUS_SUCCESS;
  478. }
  479. #else
  480. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  481. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  482. {
  483. return QDF_STATUS_E_NOMEM;
  484. }
  485. #endif
  486. /**
  487. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  488. * @vdev: DP Vdev handle
  489. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  490. * @desc_pool_id: Descriptor Pool ID
  491. *
  492. * Return:
  493. */
  494. static
  495. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  496. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  497. {
  498. uint8_t i;
  499. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  500. struct dp_tx_seg_info_s *seg_info;
  501. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  502. struct dp_soc *soc = vdev->pdev->soc;
  503. /* Allocate an extension descriptor */
  504. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  505. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  506. if (!msdu_ext_desc) {
  507. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  508. return NULL;
  509. }
  510. if (msdu_info->exception_fw &&
  511. qdf_unlikely(vdev->mesh_vdev)) {
  512. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  513. &msdu_info->meta_data[0],
  514. sizeof(struct htt_tx_msdu_desc_ext2_t));
  515. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  516. }
  517. switch (msdu_info->frm_type) {
  518. case dp_tx_frm_sg:
  519. case dp_tx_frm_me:
  520. case dp_tx_frm_raw:
  521. seg_info = msdu_info->u.sg_info.curr_seg;
  522. /* Update the buffer pointers in MSDU Extension Descriptor */
  523. for (i = 0; i < seg_info->frag_cnt; i++) {
  524. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  525. seg_info->frags[i].paddr_lo,
  526. seg_info->frags[i].paddr_hi,
  527. seg_info->frags[i].len);
  528. }
  529. break;
  530. case dp_tx_frm_tso:
  531. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  532. &cached_ext_desc[0]);
  533. break;
  534. default:
  535. break;
  536. }
  537. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  538. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  539. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  540. msdu_ext_desc->vaddr);
  541. return msdu_ext_desc;
  542. }
  543. /**
  544. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  545. *
  546. * @skb: skb to be traced
  547. * @msdu_id: msdu_id of the packet
  548. * @vdev_id: vdev_id of the packet
  549. *
  550. * Return: None
  551. */
  552. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  553. uint8_t vdev_id)
  554. {
  555. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  556. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  557. DPTRACE(qdf_dp_trace_ptr(skb,
  558. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  559. QDF_TRACE_DEFAULT_PDEV_ID,
  560. qdf_nbuf_data_addr(skb),
  561. sizeof(qdf_nbuf_data(skb)),
  562. msdu_id, vdev_id));
  563. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  564. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  565. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  566. msdu_id, QDF_TX));
  567. }
  568. #ifdef QCA_512M_CONFIG
  569. /**
  570. * dp_tx_pdev_pflow_control - Check if allocated tx descriptors reached max
  571. * tx descriptor configured value
  572. * @vdev: DP vdev handle
  573. *
  574. * Return: true if allocated tx descriptors reached max configured value, else
  575. * false.
  576. */
  577. static inline bool
  578. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  579. {
  580. struct dp_pdev *pdev = vdev->pdev;
  581. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  582. pdev->num_tx_allowed) {
  583. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  584. "%s: queued packets are more than max tx, drop the frame",
  585. __func__);
  586. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  587. return true;
  588. }
  589. return false;
  590. }
  591. #else
  592. static inline bool
  593. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  594. {
  595. return false;
  596. }
  597. #endif
  598. /**
  599. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  600. * @vdev: DP vdev handle
  601. * @nbuf: skb
  602. * @desc_pool_id: Descriptor pool ID
  603. * @meta_data: Metadata to the fw
  604. * @tx_exc_metadata: Handle that holds exception path metadata
  605. * Allocate and prepare Tx descriptor with msdu information.
  606. *
  607. * Return: Pointer to Tx Descriptor on success,
  608. * NULL on failure
  609. */
  610. static
  611. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  612. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  613. struct dp_tx_msdu_info_s *msdu_info,
  614. struct cdp_tx_exception_metadata *tx_exc_metadata)
  615. {
  616. uint8_t align_pad;
  617. uint8_t is_exception = 0;
  618. uint8_t htt_hdr_size;
  619. qdf_ether_header_t *eh;
  620. struct dp_tx_desc_s *tx_desc;
  621. struct dp_pdev *pdev = vdev->pdev;
  622. struct dp_soc *soc = pdev->soc;
  623. if (dp_tx_pdev_pflow_control(vdev))
  624. return NULL;
  625. /* Allocate software Tx descriptor */
  626. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  627. if (qdf_unlikely(!tx_desc)) {
  628. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  629. return NULL;
  630. }
  631. /* Flow control/Congestion Control counters */
  632. qdf_atomic_inc(&pdev->num_tx_outstanding);
  633. /* Initialize the SW tx descriptor */
  634. tx_desc->nbuf = nbuf;
  635. tx_desc->frm_type = dp_tx_frm_std;
  636. tx_desc->tx_encap_type = (tx_exc_metadata ?
  637. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  638. tx_desc->vdev = vdev;
  639. tx_desc->pdev = pdev;
  640. tx_desc->msdu_ext_desc = NULL;
  641. tx_desc->pkt_offset = 0;
  642. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  643. /*
  644. * For special modes (vdev_type == ocb or mesh), data frames should be
  645. * transmitted using varying transmit parameters (tx spec) which include
  646. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  647. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  648. * These frames are sent as exception packets to firmware.
  649. *
  650. * HW requirement is that metadata should always point to a
  651. * 8-byte aligned address. So we add alignment pad to start of buffer.
  652. * HTT Metadata should be ensured to be multiple of 8-bytes,
  653. * to get 8-byte aligned start address along with align_pad added
  654. *
  655. * |-----------------------------|
  656. * | |
  657. * |-----------------------------| <-----Buffer Pointer Address given
  658. * | | ^ in HW descriptor (aligned)
  659. * | HTT Metadata | |
  660. * | | |
  661. * | | | Packet Offset given in descriptor
  662. * | | |
  663. * |-----------------------------| |
  664. * | Alignment Pad | v
  665. * |-----------------------------| <----- Actual buffer start address
  666. * | SKB Data | (Unaligned)
  667. * | |
  668. * | |
  669. * | |
  670. * | |
  671. * | |
  672. * |-----------------------------|
  673. */
  674. if (qdf_unlikely((msdu_info->exception_fw)) ||
  675. (vdev->opmode == wlan_op_mode_ocb)) {
  676. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  677. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  678. DP_STATS_INC(vdev,
  679. tx_i.dropped.headroom_insufficient, 1);
  680. goto failure;
  681. }
  682. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  683. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  684. "qdf_nbuf_push_head failed");
  685. goto failure;
  686. }
  687. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  688. msdu_info->meta_data);
  689. if (htt_hdr_size == 0)
  690. goto failure;
  691. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  692. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  693. is_exception = 1;
  694. }
  695. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  696. qdf_nbuf_map(soc->osdev, nbuf,
  697. QDF_DMA_TO_DEVICE))) {
  698. /* Handle failure */
  699. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  700. "qdf_nbuf_map failed");
  701. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  702. goto failure;
  703. }
  704. if (qdf_unlikely(vdev->nawds_enabled)) {
  705. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  706. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  707. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  708. is_exception = 1;
  709. }
  710. }
  711. #if !TQM_BYPASS_WAR
  712. if (is_exception || tx_exc_metadata)
  713. #endif
  714. {
  715. /* Temporary WAR due to TQM VP issues */
  716. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  717. qdf_atomic_inc(&pdev->num_tx_exception);
  718. }
  719. return tx_desc;
  720. failure:
  721. dp_tx_desc_release(tx_desc, desc_pool_id);
  722. return NULL;
  723. }
  724. /**
  725. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  726. * @vdev: DP vdev handle
  727. * @nbuf: skb
  728. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  729. * @desc_pool_id : Descriptor Pool ID
  730. *
  731. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  732. * information. For frames wth fragments, allocate and prepare
  733. * an MSDU extension descriptor
  734. *
  735. * Return: Pointer to Tx Descriptor on success,
  736. * NULL on failure
  737. */
  738. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  739. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  740. uint8_t desc_pool_id)
  741. {
  742. struct dp_tx_desc_s *tx_desc;
  743. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  744. struct dp_pdev *pdev = vdev->pdev;
  745. struct dp_soc *soc = pdev->soc;
  746. if (dp_tx_pdev_pflow_control(vdev))
  747. return NULL;
  748. /* Allocate software Tx descriptor */
  749. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  750. if (!tx_desc) {
  751. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  752. return NULL;
  753. }
  754. /* Flow control/Congestion Control counters */
  755. qdf_atomic_inc(&pdev->num_tx_outstanding);
  756. /* Initialize the SW tx descriptor */
  757. tx_desc->nbuf = nbuf;
  758. tx_desc->frm_type = msdu_info->frm_type;
  759. tx_desc->tx_encap_type = vdev->tx_encap_type;
  760. tx_desc->vdev = vdev;
  761. tx_desc->pdev = pdev;
  762. tx_desc->pkt_offset = 0;
  763. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  764. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  765. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  766. /* Handle scattered frames - TSO/SG/ME */
  767. /* Allocate and prepare an extension descriptor for scattered frames */
  768. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  769. if (!msdu_ext_desc) {
  770. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  771. "%s Tx Extension Descriptor Alloc Fail",
  772. __func__);
  773. goto failure;
  774. }
  775. #if TQM_BYPASS_WAR
  776. /* Temporary WAR due to TQM VP issues */
  777. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  778. qdf_atomic_inc(&pdev->num_tx_exception);
  779. #endif
  780. if (qdf_unlikely(msdu_info->exception_fw))
  781. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  782. tx_desc->msdu_ext_desc = msdu_ext_desc;
  783. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  784. return tx_desc;
  785. failure:
  786. dp_tx_desc_release(tx_desc, desc_pool_id);
  787. return NULL;
  788. }
  789. /**
  790. * dp_tx_prepare_raw() - Prepare RAW packet TX
  791. * @vdev: DP vdev handle
  792. * @nbuf: buffer pointer
  793. * @seg_info: Pointer to Segment info Descriptor to be prepared
  794. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  795. * descriptor
  796. *
  797. * Return:
  798. */
  799. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  800. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  801. {
  802. qdf_nbuf_t curr_nbuf = NULL;
  803. uint16_t total_len = 0;
  804. qdf_dma_addr_t paddr;
  805. int32_t i;
  806. int32_t mapped_buf_num = 0;
  807. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  808. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  809. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  810. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  811. if (vdev->raw_mode_war &&
  812. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS))
  813. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  814. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  815. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  816. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  817. QDF_DMA_TO_DEVICE)) {
  818. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  819. "%s dma map error ", __func__);
  820. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  821. mapped_buf_num = i;
  822. goto error;
  823. }
  824. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  825. seg_info->frags[i].paddr_lo = paddr;
  826. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  827. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  828. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  829. total_len += qdf_nbuf_len(curr_nbuf);
  830. }
  831. seg_info->frag_cnt = i;
  832. seg_info->total_len = total_len;
  833. seg_info->next = NULL;
  834. sg_info->curr_seg = seg_info;
  835. msdu_info->frm_type = dp_tx_frm_raw;
  836. msdu_info->num_seg = 1;
  837. return nbuf;
  838. error:
  839. i = 0;
  840. while (nbuf) {
  841. curr_nbuf = nbuf;
  842. if (i < mapped_buf_num) {
  843. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  844. i++;
  845. }
  846. nbuf = qdf_nbuf_next(nbuf);
  847. qdf_nbuf_free(curr_nbuf);
  848. }
  849. return NULL;
  850. }
  851. /**
  852. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  853. * @soc: DP Soc Handle
  854. * @vdev: DP vdev handle
  855. * @tx_desc: Tx Descriptor Handle
  856. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  857. * @fw_metadata: Metadata to send to Target Firmware along with frame
  858. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  859. * @tx_exc_metadata: Handle that holds exception path meta data
  860. *
  861. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  862. * from software Tx descriptor
  863. *
  864. * Return:
  865. */
  866. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  867. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  868. uint16_t fw_metadata, uint8_t ring_id,
  869. struct cdp_tx_exception_metadata
  870. *tx_exc_metadata)
  871. {
  872. uint8_t type;
  873. uint16_t length;
  874. void *hal_tx_desc, *hal_tx_desc_cached;
  875. qdf_dma_addr_t dma_addr;
  876. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  877. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  878. tx_exc_metadata->sec_type : vdev->sec_type);
  879. /* Return Buffer Manager ID */
  880. uint8_t bm_id = ring_id;
  881. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  882. hal_tx_desc_cached = (void *) cached_desc;
  883. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  884. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  885. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  886. type = HAL_TX_BUF_TYPE_EXT_DESC;
  887. dma_addr = tx_desc->msdu_ext_desc->paddr;
  888. } else {
  889. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  890. type = HAL_TX_BUF_TYPE_BUFFER;
  891. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  892. }
  893. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  894. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  895. dma_addr, bm_id, tx_desc->id,
  896. type, soc->hal_soc);
  897. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  898. return QDF_STATUS_E_RESOURCES;
  899. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  900. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  901. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  902. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  903. vdev->pdev->lmac_id);
  904. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  905. vdev->search_type);
  906. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  907. vdev->bss_ast_hash);
  908. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  909. vdev->dscp_tid_map_id);
  910. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  911. sec_type_map[sec_type]);
  912. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  913. length, type, (uint64_t)dma_addr,
  914. tx_desc->pkt_offset, tx_desc->id);
  915. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  916. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  917. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  918. vdev->hal_desc_addr_search_flags);
  919. /* verify checksum offload configuration*/
  920. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  921. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  922. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  923. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  924. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  925. }
  926. if (tid != HTT_TX_EXT_TID_INVALID)
  927. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  928. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  929. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  930. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  931. /* Sync cached descriptor with HW */
  932. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  933. if (!hal_tx_desc) {
  934. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  935. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  936. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  937. return QDF_STATUS_E_RESOURCES;
  938. }
  939. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  940. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  941. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  942. return QDF_STATUS_SUCCESS;
  943. }
  944. /**
  945. * dp_cce_classify() - Classify the frame based on CCE rules
  946. * @vdev: DP vdev handle
  947. * @nbuf: skb
  948. *
  949. * Classify frames based on CCE rules
  950. * Return: bool( true if classified,
  951. * else false)
  952. */
  953. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  954. {
  955. qdf_ether_header_t *eh = NULL;
  956. uint16_t ether_type;
  957. qdf_llc_t *llcHdr;
  958. qdf_nbuf_t nbuf_clone = NULL;
  959. qdf_dot3_qosframe_t *qos_wh = NULL;
  960. /* for mesh packets don't do any classification */
  961. if (qdf_unlikely(vdev->mesh_vdev))
  962. return false;
  963. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  964. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  965. ether_type = eh->ether_type;
  966. llcHdr = (qdf_llc_t *)(nbuf->data +
  967. sizeof(qdf_ether_header_t));
  968. } else {
  969. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  970. /* For encrypted packets don't do any classification */
  971. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  972. return false;
  973. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  974. if (qdf_unlikely(
  975. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  976. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  977. ether_type = *(uint16_t *)(nbuf->data
  978. + QDF_IEEE80211_4ADDR_HDR_LEN
  979. + sizeof(qdf_llc_t)
  980. - sizeof(ether_type));
  981. llcHdr = (qdf_llc_t *)(nbuf->data +
  982. QDF_IEEE80211_4ADDR_HDR_LEN);
  983. } else {
  984. ether_type = *(uint16_t *)(nbuf->data
  985. + QDF_IEEE80211_3ADDR_HDR_LEN
  986. + sizeof(qdf_llc_t)
  987. - sizeof(ether_type));
  988. llcHdr = (qdf_llc_t *)(nbuf->data +
  989. QDF_IEEE80211_3ADDR_HDR_LEN);
  990. }
  991. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  992. && (ether_type ==
  993. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  994. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  995. return true;
  996. }
  997. }
  998. return false;
  999. }
  1000. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1001. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1002. sizeof(*llcHdr));
  1003. nbuf_clone = qdf_nbuf_clone(nbuf);
  1004. if (qdf_unlikely(nbuf_clone)) {
  1005. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1006. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1007. qdf_nbuf_pull_head(nbuf_clone,
  1008. sizeof(qdf_net_vlanhdr_t));
  1009. }
  1010. }
  1011. } else {
  1012. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1013. nbuf_clone = qdf_nbuf_clone(nbuf);
  1014. if (qdf_unlikely(nbuf_clone)) {
  1015. qdf_nbuf_pull_head(nbuf_clone,
  1016. sizeof(qdf_net_vlanhdr_t));
  1017. }
  1018. }
  1019. }
  1020. if (qdf_unlikely(nbuf_clone))
  1021. nbuf = nbuf_clone;
  1022. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1023. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1024. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1025. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1026. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1027. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1028. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1029. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1030. if (qdf_unlikely(nbuf_clone))
  1031. qdf_nbuf_free(nbuf_clone);
  1032. return true;
  1033. }
  1034. if (qdf_unlikely(nbuf_clone))
  1035. qdf_nbuf_free(nbuf_clone);
  1036. return false;
  1037. }
  1038. /**
  1039. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1040. * @vdev: DP vdev handle
  1041. * @nbuf: skb
  1042. *
  1043. * Extract the DSCP or PCP information from frame and map into TID value.
  1044. *
  1045. * Return: void
  1046. */
  1047. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1048. struct dp_tx_msdu_info_s *msdu_info)
  1049. {
  1050. uint8_t tos = 0, dscp_tid_override = 0;
  1051. uint8_t *hdr_ptr, *L3datap;
  1052. uint8_t is_mcast = 0;
  1053. qdf_ether_header_t *eh = NULL;
  1054. qdf_ethervlan_header_t *evh = NULL;
  1055. uint16_t ether_type;
  1056. qdf_llc_t *llcHdr;
  1057. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1058. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1059. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1060. eh = (qdf_ether_header_t *)nbuf->data;
  1061. hdr_ptr = eh->ether_dhost;
  1062. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1063. } else {
  1064. qdf_dot3_qosframe_t *qos_wh =
  1065. (qdf_dot3_qosframe_t *) nbuf->data;
  1066. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1067. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1068. return;
  1069. }
  1070. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1071. ether_type = eh->ether_type;
  1072. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1073. /*
  1074. * Check if packet is dot3 or eth2 type.
  1075. */
  1076. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1077. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1078. sizeof(*llcHdr));
  1079. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1080. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1081. sizeof(*llcHdr);
  1082. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1083. + sizeof(*llcHdr) +
  1084. sizeof(qdf_net_vlanhdr_t));
  1085. } else {
  1086. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1087. sizeof(*llcHdr);
  1088. }
  1089. } else {
  1090. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1091. evh = (qdf_ethervlan_header_t *) eh;
  1092. ether_type = evh->ether_type;
  1093. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1094. }
  1095. }
  1096. /*
  1097. * Find priority from IP TOS DSCP field
  1098. */
  1099. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1100. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1101. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1102. /* Only for unicast frames */
  1103. if (!is_mcast) {
  1104. /* send it on VO queue */
  1105. msdu_info->tid = DP_VO_TID;
  1106. }
  1107. } else {
  1108. /*
  1109. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1110. * from TOS byte.
  1111. */
  1112. tos = ip->ip_tos;
  1113. dscp_tid_override = 1;
  1114. }
  1115. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1116. /* TODO
  1117. * use flowlabel
  1118. *igmpmld cases to be handled in phase 2
  1119. */
  1120. unsigned long ver_pri_flowlabel;
  1121. unsigned long pri;
  1122. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1123. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1124. DP_IPV6_PRIORITY_SHIFT;
  1125. tos = pri;
  1126. dscp_tid_override = 1;
  1127. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1128. msdu_info->tid = DP_VO_TID;
  1129. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1130. /* Only for unicast frames */
  1131. if (!is_mcast) {
  1132. /* send ucast arp on VO queue */
  1133. msdu_info->tid = DP_VO_TID;
  1134. }
  1135. }
  1136. /*
  1137. * Assign all MCAST packets to BE
  1138. */
  1139. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1140. if (is_mcast) {
  1141. tos = 0;
  1142. dscp_tid_override = 1;
  1143. }
  1144. }
  1145. if (dscp_tid_override == 1) {
  1146. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1147. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1148. }
  1149. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1150. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1151. return;
  1152. }
  1153. /**
  1154. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1155. * @vdev: DP vdev handle
  1156. * @nbuf: skb
  1157. *
  1158. * Software based TID classification is required when more than 2 DSCP-TID
  1159. * mapping tables are needed.
  1160. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1161. *
  1162. * Return: void
  1163. */
  1164. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1165. struct dp_tx_msdu_info_s *msdu_info)
  1166. {
  1167. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1168. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1169. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1170. return;
  1171. /* for mesh packets don't do any classification */
  1172. if (qdf_unlikely(vdev->mesh_vdev))
  1173. return;
  1174. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1175. }
  1176. #ifdef FEATURE_WLAN_TDLS
  1177. /**
  1178. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1179. * @tx_desc: TX descriptor
  1180. *
  1181. * Return: None
  1182. */
  1183. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1184. {
  1185. if (tx_desc->vdev) {
  1186. if (tx_desc->vdev->is_tdls_frame) {
  1187. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1188. tx_desc->vdev->is_tdls_frame = false;
  1189. }
  1190. }
  1191. }
  1192. /**
  1193. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1194. * @tx_desc: TX descriptor
  1195. * @vdev: datapath vdev handle
  1196. *
  1197. * Return: None
  1198. */
  1199. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1200. struct dp_vdev *vdev)
  1201. {
  1202. struct hal_tx_completion_status ts = {0};
  1203. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1204. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1205. if (vdev->tx_non_std_data_callback.func) {
  1206. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1207. vdev->tx_non_std_data_callback.func(
  1208. vdev->tx_non_std_data_callback.ctxt,
  1209. nbuf, ts.status);
  1210. return;
  1211. }
  1212. }
  1213. #else
  1214. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1215. {
  1216. }
  1217. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1218. struct dp_vdev *vdev)
  1219. {
  1220. }
  1221. #endif
  1222. /**
  1223. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1224. * @vdev: DP vdev handle
  1225. * @nbuf: skb
  1226. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1227. * @meta_data: Metadata to the fw
  1228. * @tx_q: Tx queue to be used for this Tx frame
  1229. * @peer_id: peer_id of the peer in case of NAWDS frames
  1230. * @tx_exc_metadata: Handle that holds exception path metadata
  1231. *
  1232. * Return: NULL on success,
  1233. * nbuf when it fails to send
  1234. */
  1235. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1236. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1237. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1238. {
  1239. struct dp_pdev *pdev = vdev->pdev;
  1240. struct dp_soc *soc = pdev->soc;
  1241. struct dp_tx_desc_s *tx_desc;
  1242. QDF_STATUS status;
  1243. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1244. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1245. uint16_t htt_tcl_metadata = 0;
  1246. uint8_t tid = msdu_info->tid;
  1247. struct cdp_tid_tx_stats *tid_stats = NULL;
  1248. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1249. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1250. msdu_info, tx_exc_metadata);
  1251. if (!tx_desc) {
  1252. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1253. vdev, tx_q->desc_pool_id);
  1254. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1255. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1256. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1257. return nbuf;
  1258. }
  1259. if (qdf_unlikely(soc->cce_disable)) {
  1260. if (dp_cce_classify(vdev, nbuf) == true) {
  1261. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1262. tid = DP_VO_TID;
  1263. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1264. }
  1265. }
  1266. dp_tx_update_tdls_flags(tx_desc);
  1267. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1268. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1269. "%s %d : HAL RING Access Failed -- %pK",
  1270. __func__, __LINE__, hal_srng);
  1271. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1272. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1273. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1274. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1275. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1276. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1277. goto fail_return;
  1278. }
  1279. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1280. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1281. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1282. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1283. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1284. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1285. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1286. peer_id);
  1287. } else
  1288. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1289. if (msdu_info->exception_fw) {
  1290. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1291. }
  1292. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1293. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1294. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1295. if (status != QDF_STATUS_SUCCESS) {
  1296. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1297. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1298. __func__, tx_desc, tx_q->ring_id);
  1299. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1300. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1301. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1302. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1303. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1304. goto fail_return;
  1305. }
  1306. nbuf = NULL;
  1307. fail_return:
  1308. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1309. hal_srng_access_end(soc->hal_soc, hal_srng);
  1310. hif_pm_runtime_put(soc->hif_handle);
  1311. } else {
  1312. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1313. }
  1314. return nbuf;
  1315. }
  1316. /**
  1317. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1318. * @vdev: DP vdev handle
  1319. * @nbuf: skb
  1320. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1321. *
  1322. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1323. *
  1324. * Return: NULL on success,
  1325. * nbuf when it fails to send
  1326. */
  1327. #if QDF_LOCK_STATS
  1328. static noinline
  1329. #else
  1330. static
  1331. #endif
  1332. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1333. struct dp_tx_msdu_info_s *msdu_info)
  1334. {
  1335. uint8_t i;
  1336. struct dp_pdev *pdev = vdev->pdev;
  1337. struct dp_soc *soc = pdev->soc;
  1338. struct dp_tx_desc_s *tx_desc;
  1339. bool is_cce_classified = false;
  1340. QDF_STATUS status;
  1341. uint16_t htt_tcl_metadata = 0;
  1342. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1343. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1344. struct cdp_tid_tx_stats *tid_stats = NULL;
  1345. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1346. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1347. "%s %d : HAL RING Access Failed -- %pK",
  1348. __func__, __LINE__, hal_srng);
  1349. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1350. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1351. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1352. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1353. return nbuf;
  1354. }
  1355. if (qdf_unlikely(soc->cce_disable)) {
  1356. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1357. if (is_cce_classified) {
  1358. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1359. msdu_info->tid = DP_VO_TID;
  1360. }
  1361. }
  1362. if (msdu_info->frm_type == dp_tx_frm_me)
  1363. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1364. i = 0;
  1365. /* Print statement to track i and num_seg */
  1366. /*
  1367. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1368. * descriptors using information in msdu_info
  1369. */
  1370. while (i < msdu_info->num_seg) {
  1371. /*
  1372. * Setup Tx descriptor for an MSDU, and MSDU extension
  1373. * descriptor
  1374. */
  1375. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1376. tx_q->desc_pool_id);
  1377. if (!tx_desc) {
  1378. if (msdu_info->frm_type == dp_tx_frm_me) {
  1379. dp_tx_me_free_buf(pdev,
  1380. (void *)(msdu_info->u.sg_info
  1381. .curr_seg->frags[0].vaddr));
  1382. }
  1383. goto done;
  1384. }
  1385. if (msdu_info->frm_type == dp_tx_frm_me) {
  1386. tx_desc->me_buffer =
  1387. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1388. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1389. }
  1390. if (is_cce_classified)
  1391. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1392. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1393. if (msdu_info->exception_fw) {
  1394. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1395. }
  1396. /*
  1397. * Enqueue the Tx MSDU descriptor to HW for transmit
  1398. */
  1399. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1400. htt_tcl_metadata, tx_q->ring_id, NULL);
  1401. if (status != QDF_STATUS_SUCCESS) {
  1402. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1403. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1404. __func__, tx_desc, tx_q->ring_id);
  1405. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1406. tid_stats = &pdev->stats.tid_stats.
  1407. tid_tx_stats[msdu_info->tid];
  1408. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1409. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1410. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1411. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1412. goto done;
  1413. }
  1414. /*
  1415. * TODO
  1416. * if tso_info structure can be modified to have curr_seg
  1417. * as first element, following 2 blocks of code (for TSO and SG)
  1418. * can be combined into 1
  1419. */
  1420. /*
  1421. * For frames with multiple segments (TSO, ME), jump to next
  1422. * segment.
  1423. */
  1424. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1425. if (msdu_info->u.tso_info.curr_seg->next) {
  1426. msdu_info->u.tso_info.curr_seg =
  1427. msdu_info->u.tso_info.curr_seg->next;
  1428. /*
  1429. * If this is a jumbo nbuf, then increment the number of
  1430. * nbuf users for each additional segment of the msdu.
  1431. * This will ensure that the skb is freed only after
  1432. * receiving tx completion for all segments of an nbuf
  1433. */
  1434. qdf_nbuf_inc_users(nbuf);
  1435. /* Check with MCL if this is needed */
  1436. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1437. }
  1438. }
  1439. /*
  1440. * For Multicast-Unicast converted packets,
  1441. * each converted frame (for a client) is represented as
  1442. * 1 segment
  1443. */
  1444. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1445. (msdu_info->frm_type == dp_tx_frm_me)) {
  1446. if (msdu_info->u.sg_info.curr_seg->next) {
  1447. msdu_info->u.sg_info.curr_seg =
  1448. msdu_info->u.sg_info.curr_seg->next;
  1449. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1450. }
  1451. }
  1452. i++;
  1453. }
  1454. nbuf = NULL;
  1455. done:
  1456. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1457. hal_srng_access_end(soc->hal_soc, hal_srng);
  1458. hif_pm_runtime_put(soc->hif_handle);
  1459. } else {
  1460. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1461. }
  1462. return nbuf;
  1463. }
  1464. /**
  1465. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1466. * for SG frames
  1467. * @vdev: DP vdev handle
  1468. * @nbuf: skb
  1469. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1470. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1471. *
  1472. * Return: NULL on success,
  1473. * nbuf when it fails to send
  1474. */
  1475. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1476. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1477. {
  1478. uint32_t cur_frag, nr_frags;
  1479. qdf_dma_addr_t paddr;
  1480. struct dp_tx_sg_info_s *sg_info;
  1481. sg_info = &msdu_info->u.sg_info;
  1482. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1483. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1484. QDF_DMA_TO_DEVICE)) {
  1485. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1486. "dma map error");
  1487. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1488. qdf_nbuf_free(nbuf);
  1489. return NULL;
  1490. }
  1491. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1492. seg_info->frags[0].paddr_lo = paddr;
  1493. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1494. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1495. seg_info->frags[0].vaddr = (void *) nbuf;
  1496. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1497. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1498. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1499. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1500. "frag dma map error");
  1501. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1502. qdf_nbuf_free(nbuf);
  1503. return NULL;
  1504. }
  1505. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1506. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1507. seg_info->frags[cur_frag + 1].paddr_hi =
  1508. ((uint64_t) paddr) >> 32;
  1509. seg_info->frags[cur_frag + 1].len =
  1510. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1511. }
  1512. seg_info->frag_cnt = (cur_frag + 1);
  1513. seg_info->total_len = qdf_nbuf_len(nbuf);
  1514. seg_info->next = NULL;
  1515. sg_info->curr_seg = seg_info;
  1516. msdu_info->frm_type = dp_tx_frm_sg;
  1517. msdu_info->num_seg = 1;
  1518. return nbuf;
  1519. }
  1520. #ifdef MESH_MODE_SUPPORT
  1521. /**
  1522. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1523. and prepare msdu_info for mesh frames.
  1524. * @vdev: DP vdev handle
  1525. * @nbuf: skb
  1526. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1527. *
  1528. * Return: NULL on failure,
  1529. * nbuf when extracted successfully
  1530. */
  1531. static
  1532. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1533. struct dp_tx_msdu_info_s *msdu_info)
  1534. {
  1535. struct meta_hdr_s *mhdr;
  1536. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1537. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1538. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1539. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1540. msdu_info->exception_fw = 0;
  1541. goto remove_meta_hdr;
  1542. }
  1543. msdu_info->exception_fw = 1;
  1544. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1545. meta_data->host_tx_desc_pool = 1;
  1546. meta_data->update_peer_cache = 1;
  1547. meta_data->learning_frame = 1;
  1548. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1549. meta_data->power = mhdr->power;
  1550. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1551. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1552. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1553. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1554. meta_data->dyn_bw = 1;
  1555. meta_data->valid_pwr = 1;
  1556. meta_data->valid_mcs_mask = 1;
  1557. meta_data->valid_nss_mask = 1;
  1558. meta_data->valid_preamble_type = 1;
  1559. meta_data->valid_retries = 1;
  1560. meta_data->valid_bw_info = 1;
  1561. }
  1562. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1563. meta_data->encrypt_type = 0;
  1564. meta_data->valid_encrypt_type = 1;
  1565. meta_data->learning_frame = 0;
  1566. }
  1567. meta_data->valid_key_flags = 1;
  1568. meta_data->key_flags = (mhdr->keyix & 0x3);
  1569. remove_meta_hdr:
  1570. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1571. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1572. "qdf_nbuf_pull_head failed");
  1573. qdf_nbuf_free(nbuf);
  1574. return NULL;
  1575. }
  1576. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1577. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1578. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1579. " tid %d to_fw %d",
  1580. __func__, msdu_info->meta_data[0],
  1581. msdu_info->meta_data[1],
  1582. msdu_info->meta_data[2],
  1583. msdu_info->meta_data[3],
  1584. msdu_info->meta_data[4],
  1585. msdu_info->meta_data[5],
  1586. msdu_info->tid, msdu_info->exception_fw);
  1587. return nbuf;
  1588. }
  1589. #else
  1590. static
  1591. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1592. struct dp_tx_msdu_info_s *msdu_info)
  1593. {
  1594. return nbuf;
  1595. }
  1596. #endif
  1597. /**
  1598. * dp_check_exc_metadata() - Checks if parameters are valid
  1599. * @tx_exc - holds all exception path parameters
  1600. *
  1601. * Returns true when all the parameters are valid else false
  1602. *
  1603. */
  1604. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1605. {
  1606. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1607. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1608. tx_exc->sec_type > cdp_num_sec_types) {
  1609. return false;
  1610. }
  1611. return true;
  1612. }
  1613. /**
  1614. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1615. * @vap_dev: DP vdev handle
  1616. * @nbuf: skb
  1617. * @tx_exc_metadata: Handle that holds exception path meta data
  1618. *
  1619. * Entry point for Core Tx layer (DP_TX) invoked from
  1620. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1621. *
  1622. * Return: NULL on success,
  1623. * nbuf when it fails to send
  1624. */
  1625. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1626. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1627. {
  1628. qdf_ether_header_t *eh = NULL;
  1629. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1630. struct dp_tx_msdu_info_s msdu_info;
  1631. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1632. msdu_info.tid = tx_exc_metadata->tid;
  1633. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1634. dp_verbose_debug("skb %pM", nbuf->data);
  1635. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1636. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1637. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1638. "Invalid parameters in exception path");
  1639. goto fail;
  1640. }
  1641. /* Basic sanity checks for unsupported packets */
  1642. /* MESH mode */
  1643. if (qdf_unlikely(vdev->mesh_vdev)) {
  1644. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1645. "Mesh mode is not supported in exception path");
  1646. goto fail;
  1647. }
  1648. /* TSO or SG */
  1649. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1650. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1651. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1652. "TSO and SG are not supported in exception path");
  1653. goto fail;
  1654. }
  1655. /* RAW */
  1656. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1657. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1658. "Raw frame is not supported in exception path");
  1659. goto fail;
  1660. }
  1661. /* Mcast enhancement*/
  1662. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1663. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1664. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1665. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1666. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1667. }
  1668. }
  1669. /*
  1670. * Get HW Queue to use for this frame.
  1671. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1672. * dedicated for data and 1 for command.
  1673. * "queue_id" maps to one hardware ring.
  1674. * With each ring, we also associate a unique Tx descriptor pool
  1675. * to minimize lock contention for these resources.
  1676. */
  1677. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1678. /* Single linear frame */
  1679. /*
  1680. * If nbuf is a simple linear frame, use send_single function to
  1681. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1682. * SRNG. There is no need to setup a MSDU extension descriptor.
  1683. */
  1684. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1685. tx_exc_metadata->peer_id, tx_exc_metadata);
  1686. return nbuf;
  1687. fail:
  1688. dp_verbose_debug("pkt send failed");
  1689. return nbuf;
  1690. }
  1691. /**
  1692. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1693. * @vap_dev: DP vdev handle
  1694. * @nbuf: skb
  1695. *
  1696. * Entry point for Core Tx layer (DP_TX) invoked from
  1697. * hard_start_xmit in OSIF/HDD
  1698. *
  1699. * Return: NULL on success,
  1700. * nbuf when it fails to send
  1701. */
  1702. #ifdef MESH_MODE_SUPPORT
  1703. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1704. {
  1705. struct meta_hdr_s *mhdr;
  1706. qdf_nbuf_t nbuf_mesh = NULL;
  1707. qdf_nbuf_t nbuf_clone = NULL;
  1708. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1709. uint8_t no_enc_frame = 0;
  1710. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1711. if (!nbuf_mesh) {
  1712. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1713. "qdf_nbuf_unshare failed");
  1714. return nbuf;
  1715. }
  1716. nbuf = nbuf_mesh;
  1717. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1718. if ((vdev->sec_type != cdp_sec_type_none) &&
  1719. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1720. no_enc_frame = 1;
  1721. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1722. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1723. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1724. !no_enc_frame) {
  1725. nbuf_clone = qdf_nbuf_clone(nbuf);
  1726. if (!nbuf_clone) {
  1727. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1728. "qdf_nbuf_clone failed");
  1729. return nbuf;
  1730. }
  1731. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1732. }
  1733. if (nbuf_clone) {
  1734. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1735. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1736. } else {
  1737. qdf_nbuf_free(nbuf_clone);
  1738. }
  1739. }
  1740. if (no_enc_frame)
  1741. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1742. else
  1743. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1744. nbuf = dp_tx_send(vap_dev, nbuf);
  1745. if ((!nbuf) && no_enc_frame) {
  1746. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1747. }
  1748. return nbuf;
  1749. }
  1750. #else
  1751. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1752. {
  1753. return dp_tx_send(vap_dev, nbuf);
  1754. }
  1755. #endif
  1756. /**
  1757. * dp_tx_send() - Transmit a frame on a given VAP
  1758. * @vap_dev: DP vdev handle
  1759. * @nbuf: skb
  1760. *
  1761. * Entry point for Core Tx layer (DP_TX) invoked from
  1762. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1763. * cases
  1764. *
  1765. * Return: NULL on success,
  1766. * nbuf when it fails to send
  1767. */
  1768. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1769. {
  1770. qdf_ether_header_t *eh = NULL;
  1771. struct dp_tx_msdu_info_s msdu_info;
  1772. struct dp_tx_seg_info_s seg_info;
  1773. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1774. uint16_t peer_id = HTT_INVALID_PEER;
  1775. qdf_nbuf_t nbuf_mesh = NULL;
  1776. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1777. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1778. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1779. dp_verbose_debug("skb %pM", nbuf->data);
  1780. /*
  1781. * Set Default Host TID value to invalid TID
  1782. * (TID override disabled)
  1783. */
  1784. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1785. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1786. if (qdf_unlikely(vdev->mesh_vdev)) {
  1787. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1788. &msdu_info);
  1789. if (!nbuf_mesh) {
  1790. dp_verbose_debug("Extracting mesh metadata failed");
  1791. return nbuf;
  1792. }
  1793. nbuf = nbuf_mesh;
  1794. }
  1795. /*
  1796. * Get HW Queue to use for this frame.
  1797. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1798. * dedicated for data and 1 for command.
  1799. * "queue_id" maps to one hardware ring.
  1800. * With each ring, we also associate a unique Tx descriptor pool
  1801. * to minimize lock contention for these resources.
  1802. */
  1803. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1804. /*
  1805. * TCL H/W supports 2 DSCP-TID mapping tables.
  1806. * Table 1 - Default DSCP-TID mapping table
  1807. * Table 2 - 1 DSCP-TID override table
  1808. *
  1809. * If we need a different DSCP-TID mapping for this vap,
  1810. * call tid_classify to extract DSCP/ToS from frame and
  1811. * map to a TID and store in msdu_info. This is later used
  1812. * to fill in TCL Input descriptor (per-packet TID override).
  1813. */
  1814. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1815. /*
  1816. * Classify the frame and call corresponding
  1817. * "prepare" function which extracts the segment (TSO)
  1818. * and fragmentation information (for TSO , SG, ME, or Raw)
  1819. * into MSDU_INFO structure which is later used to fill
  1820. * SW and HW descriptors.
  1821. */
  1822. if (qdf_nbuf_is_tso(nbuf)) {
  1823. dp_verbose_debug("TSO frame %pK", vdev);
  1824. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1825. qdf_nbuf_len(nbuf));
  1826. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1827. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1828. qdf_nbuf_len(nbuf));
  1829. return nbuf;
  1830. }
  1831. goto send_multiple;
  1832. }
  1833. /* SG */
  1834. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1835. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1836. if (!nbuf)
  1837. return NULL;
  1838. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1839. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1840. qdf_nbuf_len(nbuf));
  1841. goto send_multiple;
  1842. }
  1843. #ifdef ATH_SUPPORT_IQUE
  1844. /* Mcast to Ucast Conversion*/
  1845. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1846. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1847. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1848. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1849. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1850. DP_STATS_INC_PKT(vdev,
  1851. tx_i.mcast_en.mcast_pkt, 1,
  1852. qdf_nbuf_len(nbuf));
  1853. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1854. QDF_STATUS_SUCCESS) {
  1855. return NULL;
  1856. }
  1857. }
  1858. }
  1859. #endif
  1860. /* RAW */
  1861. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1862. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1863. if (!nbuf)
  1864. return NULL;
  1865. dp_verbose_debug("Raw frame %pK", vdev);
  1866. goto send_multiple;
  1867. }
  1868. /* Single linear frame */
  1869. /*
  1870. * If nbuf is a simple linear frame, use send_single function to
  1871. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1872. * SRNG. There is no need to setup a MSDU extension descriptor.
  1873. */
  1874. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1875. return nbuf;
  1876. send_multiple:
  1877. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1878. return nbuf;
  1879. }
  1880. /**
  1881. * dp_tx_reinject_handler() - Tx Reinject Handler
  1882. * @tx_desc: software descriptor head pointer
  1883. * @status : Tx completion status from HTT descriptor
  1884. *
  1885. * This function reinjects frames back to Target.
  1886. * Todo - Host queue needs to be added
  1887. *
  1888. * Return: none
  1889. */
  1890. static
  1891. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1892. {
  1893. struct dp_vdev *vdev;
  1894. struct dp_peer *peer = NULL;
  1895. uint32_t peer_id = HTT_INVALID_PEER;
  1896. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1897. qdf_nbuf_t nbuf_copy = NULL;
  1898. struct dp_tx_msdu_info_s msdu_info;
  1899. struct dp_peer *sa_peer = NULL;
  1900. struct dp_ast_entry *ast_entry = NULL;
  1901. struct dp_soc *soc = NULL;
  1902. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1903. #ifdef WDS_VENDOR_EXTENSION
  1904. int is_mcast = 0, is_ucast = 0;
  1905. int num_peers_3addr = 0;
  1906. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  1907. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1908. #endif
  1909. vdev = tx_desc->vdev;
  1910. soc = vdev->pdev->soc;
  1911. qdf_assert(vdev);
  1912. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1913. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1914. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1915. "%s Tx reinject path", __func__);
  1916. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1917. qdf_nbuf_len(tx_desc->nbuf));
  1918. qdf_spin_lock_bh(&(soc->ast_lock));
  1919. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1920. (soc,
  1921. (uint8_t *)(eh->ether_shost),
  1922. vdev->pdev->pdev_id);
  1923. if (ast_entry)
  1924. sa_peer = ast_entry->peer;
  1925. qdf_spin_unlock_bh(&(soc->ast_lock));
  1926. #ifdef WDS_VENDOR_EXTENSION
  1927. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1928. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1929. } else {
  1930. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1931. }
  1932. is_ucast = !is_mcast;
  1933. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1934. if (peer->bss_peer)
  1935. continue;
  1936. /* Detect wds peers that use 3-addr framing for mcast.
  1937. * if there are any, the bss_peer is used to send the
  1938. * the mcast frame using 3-addr format. all wds enabled
  1939. * peers that use 4-addr framing for mcast frames will
  1940. * be duplicated and sent as 4-addr frames below.
  1941. */
  1942. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1943. num_peers_3addr = 1;
  1944. break;
  1945. }
  1946. }
  1947. #endif
  1948. if (qdf_unlikely(vdev->mesh_vdev)) {
  1949. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1950. } else {
  1951. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1952. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1953. #ifdef WDS_VENDOR_EXTENSION
  1954. /*
  1955. * . if 3-addr STA, then send on BSS Peer
  1956. * . if Peer WDS enabled and accept 4-addr mcast,
  1957. * send mcast on that peer only
  1958. * . if Peer WDS enabled and accept 4-addr ucast,
  1959. * send ucast on that peer only
  1960. */
  1961. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1962. (peer->wds_enabled &&
  1963. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1964. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1965. #else
  1966. ((peer->bss_peer &&
  1967. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1968. peer->nawds_enabled)) {
  1969. #endif
  1970. peer_id = DP_INVALID_PEER;
  1971. if (peer->nawds_enabled) {
  1972. peer_id = peer->peer_ids[0];
  1973. if (sa_peer == peer) {
  1974. QDF_TRACE(
  1975. QDF_MODULE_ID_DP,
  1976. QDF_TRACE_LEVEL_DEBUG,
  1977. " %s: multicast packet",
  1978. __func__);
  1979. DP_STATS_INC(peer,
  1980. tx.nawds_mcast_drop, 1);
  1981. continue;
  1982. }
  1983. }
  1984. nbuf_copy = qdf_nbuf_copy(nbuf);
  1985. if (!nbuf_copy) {
  1986. QDF_TRACE(QDF_MODULE_ID_DP,
  1987. QDF_TRACE_LEVEL_DEBUG,
  1988. FL("nbuf copy failed"));
  1989. break;
  1990. }
  1991. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1992. nbuf_copy,
  1993. &msdu_info,
  1994. peer_id,
  1995. NULL);
  1996. if (nbuf_copy) {
  1997. QDF_TRACE(QDF_MODULE_ID_DP,
  1998. QDF_TRACE_LEVEL_DEBUG,
  1999. FL("pkt send failed"));
  2000. qdf_nbuf_free(nbuf_copy);
  2001. } else {
  2002. if (peer_id != DP_INVALID_PEER)
  2003. DP_STATS_INC_PKT(peer,
  2004. tx.nawds_mcast,
  2005. 1, qdf_nbuf_len(nbuf));
  2006. }
  2007. }
  2008. }
  2009. }
  2010. if (vdev->nawds_enabled) {
  2011. peer_id = DP_INVALID_PEER;
  2012. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2013. 1, qdf_nbuf_len(nbuf));
  2014. nbuf = dp_tx_send_msdu_single(vdev,
  2015. nbuf,
  2016. &msdu_info,
  2017. peer_id, NULL);
  2018. if (nbuf) {
  2019. QDF_TRACE(QDF_MODULE_ID_DP,
  2020. QDF_TRACE_LEVEL_DEBUG,
  2021. FL("pkt send failed"));
  2022. qdf_nbuf_free(nbuf);
  2023. }
  2024. } else
  2025. qdf_nbuf_free(nbuf);
  2026. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2027. }
  2028. /**
  2029. * dp_tx_inspect_handler() - Tx Inspect Handler
  2030. * @tx_desc: software descriptor head pointer
  2031. * @status : Tx completion status from HTT descriptor
  2032. *
  2033. * Handles Tx frames sent back to Host for inspection
  2034. * (ProxyARP)
  2035. *
  2036. * Return: none
  2037. */
  2038. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2039. {
  2040. struct dp_soc *soc;
  2041. struct dp_pdev *pdev = tx_desc->pdev;
  2042. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2043. "%s Tx inspect path",
  2044. __func__);
  2045. qdf_assert(pdev);
  2046. soc = pdev->soc;
  2047. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2048. qdf_nbuf_len(tx_desc->nbuf));
  2049. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2050. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2051. }
  2052. #ifdef FEATURE_PERPKT_INFO
  2053. /**
  2054. * dp_get_completion_indication_for_stack() - send completion to stack
  2055. * @soc : dp_soc handle
  2056. * @pdev: dp_pdev handle
  2057. * @peer: dp peer handle
  2058. * @ts: transmit completion status structure
  2059. * @netbuf: Buffer pointer for free
  2060. *
  2061. * This function is used for indication whether buffer needs to be
  2062. * sent to stack for freeing or not
  2063. */
  2064. QDF_STATUS
  2065. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2066. struct dp_pdev *pdev,
  2067. struct dp_peer *peer,
  2068. struct hal_tx_completion_status *ts,
  2069. qdf_nbuf_t netbuf,
  2070. uint64_t time_latency)
  2071. {
  2072. struct tx_capture_hdr *ppdu_hdr;
  2073. uint16_t peer_id = ts->peer_id;
  2074. uint32_t ppdu_id = ts->ppdu_id;
  2075. uint8_t first_msdu = ts->first_msdu;
  2076. uint8_t last_msdu = ts->last_msdu;
  2077. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2078. !pdev->latency_capture_enable))
  2079. return QDF_STATUS_E_NOSUPPORT;
  2080. if (!peer) {
  2081. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2082. FL("Peer Invalid"));
  2083. return QDF_STATUS_E_INVAL;
  2084. }
  2085. if (pdev->mcopy_mode) {
  2086. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2087. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2088. return QDF_STATUS_E_INVAL;
  2089. }
  2090. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2091. pdev->m_copy_id.tx_peer_id = peer_id;
  2092. }
  2093. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2094. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2095. FL("No headroom"));
  2096. return QDF_STATUS_E_NOMEM;
  2097. }
  2098. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2099. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2100. QDF_MAC_ADDR_SIZE);
  2101. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2102. QDF_MAC_ADDR_SIZE);
  2103. ppdu_hdr->ppdu_id = ppdu_id;
  2104. ppdu_hdr->peer_id = peer_id;
  2105. ppdu_hdr->first_msdu = first_msdu;
  2106. ppdu_hdr->last_msdu = last_msdu;
  2107. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2108. ppdu_hdr->tsf = ts->tsf;
  2109. ppdu_hdr->time_latency = time_latency;
  2110. }
  2111. return QDF_STATUS_SUCCESS;
  2112. }
  2113. /**
  2114. * dp_send_completion_to_stack() - send completion to stack
  2115. * @soc : dp_soc handle
  2116. * @pdev: dp_pdev handle
  2117. * @peer_id: peer_id of the peer for which completion came
  2118. * @ppdu_id: ppdu_id
  2119. * @netbuf: Buffer pointer for free
  2120. *
  2121. * This function is used to send completion to stack
  2122. * to free buffer
  2123. */
  2124. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2125. uint16_t peer_id, uint32_t ppdu_id,
  2126. qdf_nbuf_t netbuf)
  2127. {
  2128. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2129. netbuf, peer_id,
  2130. WDI_NO_VAL, pdev->pdev_id);
  2131. }
  2132. #else
  2133. static QDF_STATUS
  2134. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2135. struct dp_pdev *pdev,
  2136. struct dp_peer *peer,
  2137. struct hal_tx_completion_status *ts,
  2138. qdf_nbuf_t netbuf,
  2139. uint64_t time_latency)
  2140. {
  2141. return QDF_STATUS_E_NOSUPPORT;
  2142. }
  2143. static void
  2144. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2145. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2146. {
  2147. }
  2148. #endif
  2149. /**
  2150. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2151. * @soc: Soc handle
  2152. * @desc: software Tx descriptor to be processed
  2153. *
  2154. * Return: none
  2155. */
  2156. void dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2157. {
  2158. struct dp_vdev *vdev = desc->vdev;
  2159. qdf_nbuf_t nbuf = desc->nbuf;
  2160. /* nbuf already freed in vdev detach path */
  2161. if (!nbuf)
  2162. return;
  2163. /* If it is TDLS mgmt, don't unmap or free the frame */
  2164. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2165. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2166. /* 0 : MSDU buffer, 1 : MLE */
  2167. if (desc->msdu_ext_desc) {
  2168. /* TSO free */
  2169. if (hal_tx_ext_desc_get_tso_enable(
  2170. desc->msdu_ext_desc->vaddr)) {
  2171. /* unmap eash TSO seg before free the nbuf */
  2172. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2173. desc->tso_num_desc);
  2174. qdf_nbuf_free(nbuf);
  2175. return;
  2176. }
  2177. }
  2178. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2179. if (qdf_likely(!vdev->mesh_vdev))
  2180. qdf_nbuf_free(nbuf);
  2181. else {
  2182. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2183. qdf_nbuf_free(nbuf);
  2184. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2185. } else
  2186. vdev->osif_tx_free_ext((nbuf));
  2187. }
  2188. }
  2189. /**
  2190. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2191. * @vdev: pointer to dp dev handler
  2192. * @status : Tx completion status from HTT descriptor
  2193. *
  2194. * Handles MEC notify event sent from fw to Host
  2195. *
  2196. * Return: none
  2197. */
  2198. #ifdef FEATURE_WDS
  2199. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2200. {
  2201. struct dp_soc *soc;
  2202. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2203. struct dp_peer *peer;
  2204. uint8_t mac_addr[QDF_MAC_ADDR_SIZE], i;
  2205. if (!vdev->mec_enabled)
  2206. return;
  2207. /* MEC required only in STA mode */
  2208. if (vdev->opmode != wlan_op_mode_sta)
  2209. return;
  2210. soc = vdev->pdev->soc;
  2211. peer = vdev->vap_bss_peer;
  2212. if (!peer) {
  2213. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2214. FL("peer is NULL"));
  2215. return;
  2216. }
  2217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2218. "%s Tx MEC Handler",
  2219. __func__);
  2220. for (i = 0; i < QDF_MAC_ADDR_SIZE; i++)
  2221. mac_addr[(QDF_MAC_ADDR_SIZE - 1) - i] =
  2222. status[(QDF_MAC_ADDR_SIZE - 2) + i];
  2223. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  2224. dp_peer_add_ast(soc,
  2225. peer,
  2226. mac_addr,
  2227. CDP_TXRX_AST_TYPE_MEC,
  2228. flags);
  2229. }
  2230. #endif
  2231. #ifdef MESH_MODE_SUPPORT
  2232. /**
  2233. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2234. * in mesh meta header
  2235. * @tx_desc: software descriptor head pointer
  2236. * @ts: pointer to tx completion stats
  2237. * Return: none
  2238. */
  2239. static
  2240. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2241. struct hal_tx_completion_status *ts)
  2242. {
  2243. struct meta_hdr_s *mhdr;
  2244. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2245. if (!tx_desc->msdu_ext_desc) {
  2246. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2247. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2248. "netbuf %pK offset %d",
  2249. netbuf, tx_desc->pkt_offset);
  2250. return;
  2251. }
  2252. }
  2253. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2254. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2255. "netbuf %pK offset %lu", netbuf,
  2256. sizeof(struct meta_hdr_s));
  2257. return;
  2258. }
  2259. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2260. mhdr->rssi = ts->ack_frame_rssi;
  2261. mhdr->channel = tx_desc->pdev->operating_channel;
  2262. }
  2263. #else
  2264. static
  2265. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2266. struct hal_tx_completion_status *ts)
  2267. {
  2268. }
  2269. #endif
  2270. /**
  2271. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2272. * to pass in correct fields
  2273. *
  2274. * @vdev: pdev handle
  2275. * @tx_desc: tx descriptor
  2276. * @tid: tid value
  2277. * Return: none
  2278. */
  2279. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2280. struct dp_tx_desc_s *tx_desc, uint8_t tid)
  2281. {
  2282. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2283. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2284. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2285. return;
  2286. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2287. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2288. timestamp_hw_enqueue = tx_desc->timestamp;
  2289. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2290. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2291. timestamp_hw_enqueue);
  2292. interframe_delay = (uint32_t)(timestamp_ingress -
  2293. vdev->prev_tx_enq_tstamp);
  2294. /*
  2295. * Delay in software enqueue
  2296. */
  2297. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2298. CDP_DELAY_STATS_SW_ENQ);
  2299. /*
  2300. * Delay between packet enqueued to HW and Tx completion
  2301. */
  2302. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2303. CDP_DELAY_STATS_FW_HW_TRANSMIT);
  2304. /*
  2305. * Update interframe delay stats calculated at hardstart receive point.
  2306. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2307. * interframe delay will not be calculate correctly for 1st frame.
  2308. * On the other side, this will help in avoiding extra per packet check
  2309. * of !vdev->prev_tx_enq_tstamp.
  2310. */
  2311. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2312. CDP_DELAY_STATS_TX_INTERFRAME);
  2313. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2314. }
  2315. /**
  2316. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2317. * @tx_desc: software descriptor head pointer
  2318. * @ts: Tx completion status
  2319. * @peer: peer handle
  2320. *
  2321. * Return: None
  2322. */
  2323. static inline void
  2324. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2325. struct hal_tx_completion_status *ts,
  2326. struct dp_peer *peer)
  2327. {
  2328. struct dp_pdev *pdev = peer->vdev->pdev;
  2329. struct dp_soc *soc = NULL;
  2330. uint8_t mcs, pkt_type;
  2331. uint8_t tid = ts->tid;
  2332. uint32_t length;
  2333. struct cdp_tid_tx_stats *tid_stats;
  2334. if (!pdev)
  2335. return;
  2336. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2337. tid = CDP_MAX_DATA_TIDS - 1;
  2338. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[tid];
  2339. soc = pdev->soc;
  2340. mcs = ts->mcs;
  2341. pkt_type = ts->pkt_type;
  2342. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2343. dp_err("Release source is not from TQM");
  2344. return;
  2345. }
  2346. length = qdf_nbuf_len(tx_desc->nbuf);
  2347. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2348. if (qdf_unlikely(pdev->delay_stats_flag))
  2349. dp_tx_compute_delay(peer->vdev, tx_desc, tid);
  2350. tid_stats->complete_cnt++;
  2351. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2352. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2353. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2354. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2355. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2356. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2357. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2358. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2359. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2360. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2361. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2362. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2363. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2364. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2365. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2366. tid_stats->comp_fail_cnt++;
  2367. return;
  2368. }
  2369. tid_stats->success_cnt++;
  2370. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2371. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2372. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2373. /*
  2374. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2375. * Return from here if HTT PPDU events are enabled.
  2376. */
  2377. if (!(soc->process_tx_status))
  2378. return;
  2379. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2380. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2381. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2382. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2383. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2384. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2385. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2386. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2387. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2388. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2389. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2390. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2391. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2392. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2393. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2394. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2395. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2396. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2397. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2398. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2399. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2400. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2401. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2402. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2403. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2404. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2405. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2406. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2407. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2408. &peer->stats, ts->peer_id,
  2409. UPDATE_PEER_STATS, pdev->pdev_id);
  2410. #endif
  2411. }
  2412. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2413. /**
  2414. * dp_tx_flow_pool_lock() - take flow pool lock
  2415. * @soc: core txrx main context
  2416. * @tx_desc: tx desc
  2417. *
  2418. * Return: None
  2419. */
  2420. static inline
  2421. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2422. struct dp_tx_desc_s *tx_desc)
  2423. {
  2424. struct dp_tx_desc_pool_s *pool;
  2425. uint8_t desc_pool_id;
  2426. desc_pool_id = tx_desc->pool_id;
  2427. pool = &soc->tx_desc[desc_pool_id];
  2428. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2429. }
  2430. /**
  2431. * dp_tx_flow_pool_unlock() - release flow pool lock
  2432. * @soc: core txrx main context
  2433. * @tx_desc: tx desc
  2434. *
  2435. * Return: None
  2436. */
  2437. static inline
  2438. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2439. struct dp_tx_desc_s *tx_desc)
  2440. {
  2441. struct dp_tx_desc_pool_s *pool;
  2442. uint8_t desc_pool_id;
  2443. desc_pool_id = tx_desc->pool_id;
  2444. pool = &soc->tx_desc[desc_pool_id];
  2445. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2446. }
  2447. #else
  2448. static inline
  2449. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2450. {
  2451. }
  2452. static inline
  2453. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2454. {
  2455. }
  2456. #endif
  2457. /**
  2458. * dp_tx_notify_completion() - Notify tx completion for this desc
  2459. * @soc: core txrx main context
  2460. * @tx_desc: tx desc
  2461. * @netbuf: buffer
  2462. *
  2463. * Return: none
  2464. */
  2465. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2466. struct dp_tx_desc_s *tx_desc,
  2467. qdf_nbuf_t netbuf)
  2468. {
  2469. void *osif_dev;
  2470. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2471. qdf_assert(tx_desc);
  2472. dp_tx_flow_pool_lock(soc, tx_desc);
  2473. if (!tx_desc->vdev ||
  2474. !tx_desc->vdev->osif_vdev) {
  2475. dp_tx_flow_pool_unlock(soc, tx_desc);
  2476. return;
  2477. }
  2478. osif_dev = tx_desc->vdev->osif_vdev;
  2479. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2480. dp_tx_flow_pool_unlock(soc, tx_desc);
  2481. if (tx_compl_cbk)
  2482. tx_compl_cbk(netbuf, osif_dev);
  2483. }
  2484. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2485. * @pdev: pdev handle
  2486. * @tid: tid value
  2487. * @txdesc_ts: timestamp from txdesc
  2488. * @ppdu_id: ppdu id
  2489. *
  2490. * Return: none
  2491. */
  2492. #ifdef FEATURE_PERPKT_INFO
  2493. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2494. struct dp_peer *peer,
  2495. uint8_t tid,
  2496. uint64_t txdesc_ts,
  2497. uint32_t ppdu_id)
  2498. {
  2499. uint64_t delta_ms;
  2500. struct cdp_tx_sojourn_stats *sojourn_stats;
  2501. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2502. return;
  2503. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2504. tid >= CDP_DATA_TID_MAX))
  2505. return;
  2506. if (qdf_unlikely(!pdev->sojourn_buf))
  2507. return;
  2508. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2509. qdf_nbuf_data(pdev->sojourn_buf);
  2510. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2511. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2512. txdesc_ts;
  2513. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2514. delta_ms);
  2515. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2516. sojourn_stats->num_msdus[tid] = 1;
  2517. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2518. peer->avg_sojourn_msdu[tid].internal;
  2519. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2520. pdev->sojourn_buf, HTT_INVALID_PEER,
  2521. WDI_NO_VAL, pdev->pdev_id);
  2522. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2523. sojourn_stats->num_msdus[tid] = 0;
  2524. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2525. }
  2526. #else
  2527. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2528. uint8_t tid,
  2529. uint64_t txdesc_ts,
  2530. uint32_t ppdu_id)
  2531. {
  2532. }
  2533. #endif
  2534. /**
  2535. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2536. * @soc: DP Soc handle
  2537. * @tx_desc: software Tx descriptor
  2538. * @ts : Tx completion status from HAL/HTT descriptor
  2539. *
  2540. * Return: none
  2541. */
  2542. static inline void
  2543. dp_tx_comp_process_desc(struct dp_soc *soc,
  2544. struct dp_tx_desc_s *desc,
  2545. struct hal_tx_completion_status *ts,
  2546. struct dp_peer *peer)
  2547. {
  2548. uint64_t time_latency = 0;
  2549. /*
  2550. * m_copy/tx_capture modes are not supported for
  2551. * scatter gather packets
  2552. */
  2553. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2554. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2555. desc->timestamp);
  2556. }
  2557. if (!(desc->msdu_ext_desc)) {
  2558. if (QDF_STATUS_SUCCESS ==
  2559. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2560. return;
  2561. }
  2562. if (QDF_STATUS_SUCCESS ==
  2563. dp_get_completion_indication_for_stack(soc,
  2564. desc->pdev,
  2565. peer, ts,
  2566. desc->nbuf,
  2567. time_latency)) {
  2568. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2569. QDF_DMA_TO_DEVICE);
  2570. dp_send_completion_to_stack(soc,
  2571. desc->pdev,
  2572. ts->peer_id,
  2573. ts->ppdu_id,
  2574. desc->nbuf);
  2575. return;
  2576. }
  2577. }
  2578. dp_tx_comp_free_buf(soc, desc);
  2579. }
  2580. /**
  2581. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2582. * @tx_desc: software descriptor head pointer
  2583. * @ts: Tx completion status
  2584. * @peer: peer handle
  2585. *
  2586. * Return: none
  2587. */
  2588. static inline
  2589. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2590. struct hal_tx_completion_status *ts,
  2591. struct dp_peer *peer)
  2592. {
  2593. uint32_t length;
  2594. qdf_ether_header_t *eh;
  2595. struct dp_soc *soc = NULL;
  2596. struct dp_vdev *vdev = tx_desc->vdev;
  2597. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2598. if (!vdev || !nbuf) {
  2599. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2600. "invalid tx descriptor. vdev or nbuf NULL");
  2601. goto out;
  2602. }
  2603. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2604. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2605. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2606. QDF_TRACE_DEFAULT_PDEV_ID,
  2607. qdf_nbuf_data_addr(nbuf),
  2608. sizeof(qdf_nbuf_data(nbuf)),
  2609. tx_desc->id,
  2610. ts->status));
  2611. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2612. "-------------------- \n"
  2613. "Tx Completion Stats: \n"
  2614. "-------------------- \n"
  2615. "ack_frame_rssi = %d \n"
  2616. "first_msdu = %d \n"
  2617. "last_msdu = %d \n"
  2618. "msdu_part_of_amsdu = %d \n"
  2619. "rate_stats valid = %d \n"
  2620. "bw = %d \n"
  2621. "pkt_type = %d \n"
  2622. "stbc = %d \n"
  2623. "ldpc = %d \n"
  2624. "sgi = %d \n"
  2625. "mcs = %d \n"
  2626. "ofdma = %d \n"
  2627. "tones_in_ru = %d \n"
  2628. "tsf = %d \n"
  2629. "ppdu_id = %d \n"
  2630. "transmit_cnt = %d \n"
  2631. "tid = %d \n"
  2632. "peer_id = %d\n",
  2633. ts->ack_frame_rssi, ts->first_msdu,
  2634. ts->last_msdu, ts->msdu_part_of_amsdu,
  2635. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2636. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2637. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2638. ts->transmit_cnt, ts->tid, ts->peer_id);
  2639. soc = vdev->pdev->soc;
  2640. /* Update SoC level stats */
  2641. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2642. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2643. /* Update per-packet stats for mesh mode */
  2644. if (qdf_unlikely(vdev->mesh_vdev) &&
  2645. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2646. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2647. length = qdf_nbuf_len(nbuf);
  2648. /* Update peer level stats */
  2649. if (!peer) {
  2650. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2651. "peer is null or deletion in progress");
  2652. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2653. goto out;
  2654. }
  2655. if (qdf_likely(!peer->bss_peer)) {
  2656. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2657. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2658. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2659. } else {
  2660. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2661. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2662. if ((peer->vdev->tx_encap_type ==
  2663. htt_cmn_pkt_type_ethernet) &&
  2664. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2665. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2666. }
  2667. }
  2668. }
  2669. dp_tx_update_peer_stats(tx_desc, ts, peer);
  2670. #ifdef QCA_SUPPORT_RDK_STATS
  2671. if (soc->wlanstats_enabled)
  2672. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2673. tx_desc->timestamp,
  2674. ts->ppdu_id);
  2675. #endif
  2676. out:
  2677. return;
  2678. }
  2679. /**
  2680. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2681. * @soc: core txrx main context
  2682. * @comp_head: software descriptor head pointer
  2683. *
  2684. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2685. * and release the software descriptors after processing is complete
  2686. *
  2687. * Return: none
  2688. */
  2689. static void
  2690. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2691. struct dp_tx_desc_s *comp_head)
  2692. {
  2693. struct dp_tx_desc_s *desc;
  2694. struct dp_tx_desc_s *next;
  2695. struct hal_tx_completion_status ts = {0};
  2696. struct dp_peer *peer;
  2697. qdf_nbuf_t netbuf;
  2698. desc = comp_head;
  2699. while (desc) {
  2700. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2701. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2702. dp_tx_comp_process_tx_status(desc, &ts, peer);
  2703. netbuf = desc->nbuf;
  2704. /* check tx complete notification */
  2705. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2706. dp_tx_notify_completion(soc, desc, netbuf);
  2707. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2708. if (peer)
  2709. dp_peer_unref_del_find_by_id(peer);
  2710. next = desc->next;
  2711. dp_tx_desc_release(desc, desc->pool_id);
  2712. desc = next;
  2713. }
  2714. }
  2715. /**
  2716. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2717. * @tx_desc: software descriptor head pointer
  2718. * @status : Tx completion status from HTT descriptor
  2719. *
  2720. * This function will process HTT Tx indication messages from Target
  2721. *
  2722. * Return: none
  2723. */
  2724. static
  2725. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2726. {
  2727. uint8_t tx_status;
  2728. struct dp_pdev *pdev;
  2729. struct dp_vdev *vdev;
  2730. struct dp_soc *soc;
  2731. struct hal_tx_completion_status ts = {0};
  2732. uint32_t *htt_desc = (uint32_t *)status;
  2733. struct dp_peer *peer;
  2734. struct cdp_tid_tx_stats *tid_stats = NULL;
  2735. qdf_assert(tx_desc->pdev);
  2736. pdev = tx_desc->pdev;
  2737. vdev = tx_desc->vdev;
  2738. soc = pdev->soc;
  2739. if (!vdev)
  2740. return;
  2741. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2742. switch (tx_status) {
  2743. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2744. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2745. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2746. {
  2747. uint8_t tid;
  2748. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2749. ts.peer_id =
  2750. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2751. htt_desc[2]);
  2752. ts.tid =
  2753. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2754. htt_desc[2]);
  2755. } else {
  2756. ts.peer_id = HTT_INVALID_PEER;
  2757. ts.tid = HTT_INVALID_TID;
  2758. }
  2759. ts.ppdu_id =
  2760. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2761. htt_desc[1]);
  2762. ts.ack_frame_rssi =
  2763. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2764. htt_desc[1]);
  2765. ts.first_msdu = 1;
  2766. ts.last_msdu = 1;
  2767. tid = ts.tid;
  2768. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2769. tid = CDP_MAX_DATA_TIDS - 1;
  2770. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[tid];
  2771. if (qdf_unlikely(pdev->delay_stats_flag))
  2772. dp_tx_compute_delay(vdev, tx_desc, tid);
  2773. tid_stats->complete_cnt++;
  2774. if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
  2775. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2776. tid_stats->comp_fail_cnt++;
  2777. } else {
  2778. tid_stats->success_cnt++;
  2779. }
  2780. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2781. if (qdf_likely(peer))
  2782. dp_peer_unref_del_find_by_id(peer);
  2783. dp_tx_comp_process_tx_status(tx_desc, &ts, peer);
  2784. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2785. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2786. break;
  2787. }
  2788. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2789. {
  2790. dp_tx_reinject_handler(tx_desc, status);
  2791. break;
  2792. }
  2793. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2794. {
  2795. dp_tx_inspect_handler(tx_desc, status);
  2796. break;
  2797. }
  2798. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2799. {
  2800. dp_tx_mec_handler(vdev, status);
  2801. break;
  2802. }
  2803. default:
  2804. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2805. "%s Invalid HTT tx_status %d\n",
  2806. __func__, tx_status);
  2807. break;
  2808. }
  2809. }
  2810. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2811. static inline
  2812. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2813. {
  2814. bool limit_hit = false;
  2815. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2816. limit_hit =
  2817. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2818. if (limit_hit)
  2819. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2820. return limit_hit;
  2821. }
  2822. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2823. {
  2824. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2825. }
  2826. #else
  2827. static inline
  2828. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2829. {
  2830. return false;
  2831. }
  2832. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2833. {
  2834. return false;
  2835. }
  2836. #endif
  2837. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2838. void *hal_srng, uint32_t quota)
  2839. {
  2840. void *tx_comp_hal_desc;
  2841. uint8_t buffer_src;
  2842. uint8_t pool_id;
  2843. uint32_t tx_desc_id;
  2844. struct dp_tx_desc_s *tx_desc = NULL;
  2845. struct dp_tx_desc_s *head_desc = NULL;
  2846. struct dp_tx_desc_s *tail_desc = NULL;
  2847. uint32_t num_processed = 0;
  2848. uint32_t count = 0;
  2849. bool force_break = false;
  2850. DP_HIST_INIT();
  2851. more_data:
  2852. /* Re-initialize local variables to be re-used */
  2853. head_desc = NULL;
  2854. tail_desc = NULL;
  2855. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2856. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2857. "%s %d : HAL RING Access Failed -- %pK",
  2858. __func__, __LINE__, hal_srng);
  2859. return 0;
  2860. }
  2861. /* Find head descriptor from completion ring */
  2862. while (qdf_likely(tx_comp_hal_desc =
  2863. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2864. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2865. /* If this buffer was not released by TQM or FW, then it is not
  2866. * Tx completion indication, assert */
  2867. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2868. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2869. QDF_TRACE(QDF_MODULE_ID_DP,
  2870. QDF_TRACE_LEVEL_FATAL,
  2871. "Tx comp release_src != TQM | FW but from %d",
  2872. buffer_src);
  2873. hal_dump_comp_desc(tx_comp_hal_desc);
  2874. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  2875. qdf_assert_always(0);
  2876. }
  2877. /* Get descriptor id */
  2878. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2879. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2880. DP_TX_DESC_ID_POOL_OS;
  2881. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2882. continue;
  2883. /* Find Tx descriptor */
  2884. tx_desc = dp_tx_desc_find(soc, pool_id,
  2885. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2886. DP_TX_DESC_ID_PAGE_OS,
  2887. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2888. DP_TX_DESC_ID_OFFSET_OS);
  2889. /*
  2890. * If the descriptor is already freed in vdev_detach,
  2891. * continue to next descriptor
  2892. */
  2893. if (!tx_desc->vdev) {
  2894. QDF_TRACE(QDF_MODULE_ID_DP,
  2895. QDF_TRACE_LEVEL_INFO,
  2896. "Descriptor freed in vdev_detach %d",
  2897. tx_desc_id);
  2898. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2899. count++;
  2900. continue;
  2901. }
  2902. /*
  2903. * If the release source is FW, process the HTT status
  2904. */
  2905. if (qdf_unlikely(buffer_src ==
  2906. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2907. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2908. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2909. htt_tx_status);
  2910. dp_tx_process_htt_completion(tx_desc,
  2911. htt_tx_status);
  2912. } else {
  2913. /* Pool id is not matching. Error */
  2914. if (tx_desc->pool_id != pool_id) {
  2915. QDF_TRACE(QDF_MODULE_ID_DP,
  2916. QDF_TRACE_LEVEL_FATAL,
  2917. "Tx Comp pool id %d not matched %d",
  2918. pool_id, tx_desc->pool_id);
  2919. qdf_assert_always(0);
  2920. }
  2921. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2922. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2923. QDF_TRACE(QDF_MODULE_ID_DP,
  2924. QDF_TRACE_LEVEL_FATAL,
  2925. "Txdesc invalid, flgs = %x,id = %d",
  2926. tx_desc->flags, tx_desc_id);
  2927. qdf_assert_always(0);
  2928. }
  2929. /* First ring descriptor on the cycle */
  2930. if (!head_desc) {
  2931. head_desc = tx_desc;
  2932. tail_desc = tx_desc;
  2933. }
  2934. tail_desc->next = tx_desc;
  2935. tx_desc->next = NULL;
  2936. tail_desc = tx_desc;
  2937. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  2938. /* Collect hw completion contents */
  2939. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2940. &tx_desc->comp, 1);
  2941. }
  2942. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2943. /*
  2944. * Processed packet count is more than given quota
  2945. * stop to processing
  2946. */
  2947. if (num_processed >= quota) {
  2948. force_break = true;
  2949. break;
  2950. }
  2951. count++;
  2952. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  2953. break;
  2954. }
  2955. hal_srng_access_end(soc->hal_soc, hal_srng);
  2956. /* Process the reaped descriptors */
  2957. if (head_desc)
  2958. dp_tx_comp_process_desc_list(soc, head_desc);
  2959. if (dp_tx_comp_enable_eol_data_check(soc)) {
  2960. if (!force_break &&
  2961. hal_srng_dst_peek_sync_locked(soc, hal_srng)) {
  2962. DP_STATS_INC(soc, tx.hp_oos2, 1);
  2963. if (!hif_exec_should_yield(soc->hif_handle,
  2964. int_ctx->dp_intr_id))
  2965. goto more_data;
  2966. }
  2967. }
  2968. DP_TX_HIST_STATS_PER_PDEV();
  2969. return num_processed;
  2970. }
  2971. #ifdef FEATURE_WLAN_TDLS
  2972. /**
  2973. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2974. *
  2975. * @data_vdev - which vdev should transmit the tx data frames
  2976. * @tx_spec - what non-standard handling to apply to the tx data frames
  2977. * @msdu_list - NULL-terminated list of tx MSDUs
  2978. *
  2979. * Return: NULL on success,
  2980. * nbuf when it fails to send
  2981. */
  2982. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2983. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2984. {
  2985. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2986. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2987. vdev->is_tdls_frame = true;
  2988. return dp_tx_send(vdev_handle, msdu_list);
  2989. }
  2990. #endif
  2991. /**
  2992. * dp_tx_vdev_attach() - attach vdev to dp tx
  2993. * @vdev: virtual device instance
  2994. *
  2995. * Return: QDF_STATUS_SUCCESS: success
  2996. * QDF_STATUS_E_RESOURCES: Error return
  2997. */
  2998. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2999. {
  3000. /*
  3001. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3002. */
  3003. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3004. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3005. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3006. vdev->vdev_id);
  3007. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3008. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3009. /*
  3010. * Set HTT Extension Valid bit to 0 by default
  3011. */
  3012. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3013. dp_tx_vdev_update_search_flags(vdev);
  3014. return QDF_STATUS_SUCCESS;
  3015. }
  3016. #ifdef FEATURE_WDS
  3017. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3018. {
  3019. struct dp_soc *soc = vdev->pdev->soc;
  3020. /*
  3021. * If AST index override support is available (HKv2 etc),
  3022. * DA search flag be enabled always
  3023. *
  3024. * If AST index override support is not available (HKv1),
  3025. * DA search flag should be used for all modes except QWRAP
  3026. */
  3027. if (soc->ast_override_support || !vdev->proxysta_vdev)
  3028. return true;
  3029. return false;
  3030. }
  3031. #else
  3032. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3033. {
  3034. return false;
  3035. }
  3036. #endif
  3037. /**
  3038. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3039. * @vdev: virtual device instance
  3040. *
  3041. * Return: void
  3042. *
  3043. */
  3044. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3045. {
  3046. struct dp_soc *soc = vdev->pdev->soc;
  3047. /*
  3048. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3049. * for TDLS link
  3050. *
  3051. * Enable AddrY (SA based search) only for non-WDS STA and
  3052. * ProxySTA VAP (in HKv1) modes.
  3053. *
  3054. * In all other VAP modes, only DA based search should be
  3055. * enabled
  3056. */
  3057. if (vdev->opmode == wlan_op_mode_sta &&
  3058. vdev->tdls_link_connected)
  3059. vdev->hal_desc_addr_search_flags =
  3060. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3061. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3062. !dp_tx_da_search_override(vdev))
  3063. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3064. else
  3065. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3066. /* Set search type only when peer map v2 messaging is enabled
  3067. * as we will have the search index (AST hash) only when v2 is
  3068. * enabled
  3069. */
  3070. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3071. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3072. else
  3073. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3074. }
  3075. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3076. /* dp_tx_desc_flush() - release resources associated
  3077. * to tx_desc
  3078. * @vdev: virtual device instance
  3079. *
  3080. * This function will free all outstanding Tx buffers,
  3081. * including ME buffer for which either free during
  3082. * completion didn't happened or completion is not
  3083. * received.
  3084. */
  3085. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  3086. {
  3087. uint8_t i;
  3088. uint32_t j;
  3089. uint32_t num_desc, page_id, offset;
  3090. uint16_t num_desc_per_page;
  3091. struct dp_soc *soc = vdev->pdev->soc;
  3092. struct dp_tx_desc_s *tx_desc = NULL;
  3093. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3094. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3095. tx_desc_pool = &soc->tx_desc[i];
  3096. if (!(tx_desc_pool->pool_size) ||
  3097. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3098. !(tx_desc_pool->desc_pages.cacheable_pages))
  3099. continue;
  3100. num_desc = tx_desc_pool->pool_size;
  3101. num_desc_per_page =
  3102. tx_desc_pool->desc_pages.num_element_per_page;
  3103. for (j = 0; j < num_desc; j++) {
  3104. page_id = j / num_desc_per_page;
  3105. offset = j % num_desc_per_page;
  3106. if (qdf_unlikely(!(tx_desc_pool->
  3107. desc_pages.cacheable_pages)))
  3108. break;
  3109. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3110. if (tx_desc && (tx_desc->vdev == vdev) &&
  3111. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  3112. dp_tx_comp_free_buf(soc, tx_desc);
  3113. dp_tx_desc_release(tx_desc, i);
  3114. }
  3115. }
  3116. }
  3117. }
  3118. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3119. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  3120. {
  3121. uint8_t i, num_pool;
  3122. uint32_t j;
  3123. uint32_t num_desc, page_id, offset;
  3124. uint16_t num_desc_per_page;
  3125. struct dp_soc *soc = vdev->pdev->soc;
  3126. struct dp_tx_desc_s *tx_desc = NULL;
  3127. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3128. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3129. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3130. for (i = 0; i < num_pool; i++) {
  3131. tx_desc_pool = &soc->tx_desc[i];
  3132. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3133. continue;
  3134. num_desc_per_page =
  3135. tx_desc_pool->desc_pages.num_element_per_page;
  3136. for (j = 0; j < num_desc; j++) {
  3137. page_id = j / num_desc_per_page;
  3138. offset = j % num_desc_per_page;
  3139. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3140. if (tx_desc && (tx_desc->vdev == vdev) &&
  3141. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  3142. dp_tx_comp_free_buf(soc, tx_desc);
  3143. dp_tx_desc_release(tx_desc, i);
  3144. }
  3145. }
  3146. }
  3147. }
  3148. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3149. /**
  3150. * dp_tx_vdev_detach() - detach vdev from dp tx
  3151. * @vdev: virtual device instance
  3152. *
  3153. * Return: QDF_STATUS_SUCCESS: success
  3154. * QDF_STATUS_E_RESOURCES: Error return
  3155. */
  3156. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3157. {
  3158. dp_tx_desc_flush(vdev);
  3159. return QDF_STATUS_SUCCESS;
  3160. }
  3161. /**
  3162. * dp_tx_pdev_attach() - attach pdev to dp tx
  3163. * @pdev: physical device instance
  3164. *
  3165. * Return: QDF_STATUS_SUCCESS: success
  3166. * QDF_STATUS_E_RESOURCES: Error return
  3167. */
  3168. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3169. {
  3170. struct dp_soc *soc = pdev->soc;
  3171. /* Initialize Flow control counters */
  3172. qdf_atomic_init(&pdev->num_tx_exception);
  3173. qdf_atomic_init(&pdev->num_tx_outstanding);
  3174. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3175. /* Initialize descriptors in TCL Ring */
  3176. hal_tx_init_data_ring(soc->hal_soc,
  3177. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3178. }
  3179. return QDF_STATUS_SUCCESS;
  3180. }
  3181. /**
  3182. * dp_tx_pdev_detach() - detach pdev from dp tx
  3183. * @pdev: physical device instance
  3184. *
  3185. * Return: QDF_STATUS_SUCCESS: success
  3186. * QDF_STATUS_E_RESOURCES: Error return
  3187. */
  3188. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3189. {
  3190. dp_tx_me_exit(pdev);
  3191. return QDF_STATUS_SUCCESS;
  3192. }
  3193. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3194. /* Pools will be allocated dynamically */
  3195. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3196. int num_desc)
  3197. {
  3198. uint8_t i;
  3199. for (i = 0; i < num_pool; i++) {
  3200. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3201. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3202. }
  3203. return 0;
  3204. }
  3205. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3206. {
  3207. uint8_t i;
  3208. for (i = 0; i < num_pool; i++)
  3209. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3210. }
  3211. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3212. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3213. int num_desc)
  3214. {
  3215. uint8_t i;
  3216. /* Allocate software Tx descriptor pools */
  3217. for (i = 0; i < num_pool; i++) {
  3218. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3219. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3220. "%s Tx Desc Pool alloc %d failed %pK",
  3221. __func__, i, soc);
  3222. return ENOMEM;
  3223. }
  3224. }
  3225. return 0;
  3226. }
  3227. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3228. {
  3229. uint8_t i;
  3230. for (i = 0; i < num_pool; i++) {
  3231. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3232. if (dp_tx_desc_pool_free(soc, i)) {
  3233. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3234. "%s Tx Desc Pool Free failed", __func__);
  3235. }
  3236. }
  3237. }
  3238. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3239. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3240. /**
  3241. * dp_tso_attach_wifi3() - TSO attach handler
  3242. * @txrx_soc: Opaque Dp handle
  3243. *
  3244. * Reserve TSO descriptor buffers
  3245. *
  3246. * Return: QDF_STATUS_E_FAILURE on failure or
  3247. * QDF_STATUS_SUCCESS on success
  3248. */
  3249. static
  3250. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3251. {
  3252. return dp_tso_soc_attach(txrx_soc);
  3253. }
  3254. /**
  3255. * dp_tso_detach_wifi3() - TSO Detach handler
  3256. * @txrx_soc: Opaque Dp handle
  3257. *
  3258. * Deallocate TSO descriptor buffers
  3259. *
  3260. * Return: QDF_STATUS_E_FAILURE on failure or
  3261. * QDF_STATUS_SUCCESS on success
  3262. */
  3263. static
  3264. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3265. {
  3266. return dp_tso_soc_detach(txrx_soc);
  3267. }
  3268. #else
  3269. static
  3270. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3271. {
  3272. return QDF_STATUS_SUCCESS;
  3273. }
  3274. static
  3275. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3276. {
  3277. return QDF_STATUS_SUCCESS;
  3278. }
  3279. #endif
  3280. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3281. {
  3282. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3283. uint8_t i;
  3284. uint8_t num_pool;
  3285. uint32_t num_desc;
  3286. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3287. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3288. for (i = 0; i < num_pool; i++)
  3289. dp_tx_tso_desc_pool_free(soc, i);
  3290. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3291. __func__, num_pool, num_desc);
  3292. for (i = 0; i < num_pool; i++)
  3293. dp_tx_tso_num_seg_pool_free(soc, i);
  3294. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3295. __func__, num_pool, num_desc);
  3296. return QDF_STATUS_SUCCESS;
  3297. }
  3298. /**
  3299. * dp_tso_attach() - TSO attach handler
  3300. * @txrx_soc: Opaque Dp handle
  3301. *
  3302. * Reserve TSO descriptor buffers
  3303. *
  3304. * Return: QDF_STATUS_E_FAILURE on failure or
  3305. * QDF_STATUS_SUCCESS on success
  3306. */
  3307. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3308. {
  3309. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3310. uint8_t i;
  3311. uint8_t num_pool;
  3312. uint32_t num_desc;
  3313. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3314. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3315. for (i = 0; i < num_pool; i++) {
  3316. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3317. dp_err("TSO Desc Pool alloc %d failed %pK",
  3318. i, soc);
  3319. return QDF_STATUS_E_FAILURE;
  3320. }
  3321. }
  3322. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3323. __func__, num_pool, num_desc);
  3324. for (i = 0; i < num_pool; i++) {
  3325. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3326. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3327. i, soc);
  3328. return QDF_STATUS_E_FAILURE;
  3329. }
  3330. }
  3331. return QDF_STATUS_SUCCESS;
  3332. }
  3333. /**
  3334. * dp_tx_soc_detach() - detach soc from dp tx
  3335. * @soc: core txrx main context
  3336. *
  3337. * This function will detach dp tx into main device context
  3338. * will free dp tx resource and initialize resources
  3339. *
  3340. * Return: QDF_STATUS_SUCCESS: success
  3341. * QDF_STATUS_E_RESOURCES: Error return
  3342. */
  3343. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3344. {
  3345. uint8_t num_pool;
  3346. uint16_t num_desc;
  3347. uint16_t num_ext_desc;
  3348. uint8_t i;
  3349. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3350. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3351. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3352. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3353. dp_tx_flow_control_deinit(soc);
  3354. dp_tx_delete_static_pools(soc, num_pool);
  3355. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3356. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3357. __func__, num_pool, num_desc);
  3358. for (i = 0; i < num_pool; i++) {
  3359. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3360. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3361. "%s Tx Ext Desc Pool Free failed",
  3362. __func__);
  3363. return QDF_STATUS_E_RESOURCES;
  3364. }
  3365. }
  3366. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3367. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3368. __func__, num_pool, num_ext_desc);
  3369. status = dp_tso_detach_wifi3(soc);
  3370. if (status != QDF_STATUS_SUCCESS)
  3371. return status;
  3372. return QDF_STATUS_SUCCESS;
  3373. }
  3374. /**
  3375. * dp_tx_soc_attach() - attach soc to dp tx
  3376. * @soc: core txrx main context
  3377. *
  3378. * This function will attach dp tx into main device context
  3379. * will allocate dp tx resource and initialize resources
  3380. *
  3381. * Return: QDF_STATUS_SUCCESS: success
  3382. * QDF_STATUS_E_RESOURCES: Error return
  3383. */
  3384. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3385. {
  3386. uint8_t i;
  3387. uint8_t num_pool;
  3388. uint32_t num_desc;
  3389. uint32_t num_ext_desc;
  3390. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3391. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3392. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3393. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3394. if (num_pool > MAX_TXDESC_POOLS)
  3395. goto fail;
  3396. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3397. goto fail;
  3398. dp_tx_flow_control_init(soc);
  3399. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3400. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3401. __func__, num_pool, num_desc);
  3402. /* Allocate extension tx descriptor pools */
  3403. for (i = 0; i < num_pool; i++) {
  3404. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3405. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3406. "MSDU Ext Desc Pool alloc %d failed %pK",
  3407. i, soc);
  3408. goto fail;
  3409. }
  3410. }
  3411. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3412. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3413. __func__, num_pool, num_ext_desc);
  3414. status = dp_tso_attach_wifi3((void *)soc);
  3415. if (status != QDF_STATUS_SUCCESS)
  3416. goto fail;
  3417. /* Initialize descriptors in TCL Rings */
  3418. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3419. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3420. hal_tx_init_data_ring(soc->hal_soc,
  3421. soc->tcl_data_ring[i].hal_srng);
  3422. }
  3423. }
  3424. /*
  3425. * todo - Add a runtime config option to enable this.
  3426. */
  3427. /*
  3428. * Due to multiple issues on NPR EMU, enable it selectively
  3429. * only for NPR EMU, should be removed, once NPR platforms
  3430. * are stable.
  3431. */
  3432. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3433. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3434. "%s HAL Tx init Success", __func__);
  3435. return QDF_STATUS_SUCCESS;
  3436. fail:
  3437. /* Detach will take care of freeing only allocated resources */
  3438. dp_tx_soc_detach(soc);
  3439. return QDF_STATUS_E_RESOURCES;
  3440. }
  3441. /*
  3442. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3443. * pdev: pointer to DP PDEV structure
  3444. * seg_info_head: Pointer to the head of list
  3445. *
  3446. * return: void
  3447. */
  3448. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3449. struct dp_tx_seg_info_s *seg_info_head)
  3450. {
  3451. struct dp_tx_me_buf_t *mc_uc_buf;
  3452. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3453. qdf_nbuf_t nbuf = NULL;
  3454. uint64_t phy_addr;
  3455. while (seg_info_head) {
  3456. nbuf = seg_info_head->nbuf;
  3457. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3458. seg_info_head->frags[0].vaddr;
  3459. phy_addr = seg_info_head->frags[0].paddr_hi;
  3460. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3461. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3462. phy_addr,
  3463. QDF_DMA_TO_DEVICE , QDF_MAC_ADDR_SIZE);
  3464. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3465. qdf_nbuf_free(nbuf);
  3466. seg_info_new = seg_info_head;
  3467. seg_info_head = seg_info_head->next;
  3468. qdf_mem_free(seg_info_new);
  3469. }
  3470. }
  3471. /**
  3472. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3473. * @vdev: DP VDEV handle
  3474. * @nbuf: Multicast nbuf
  3475. * @newmac: Table of the clients to which packets have to be sent
  3476. * @new_mac_cnt: No of clients
  3477. *
  3478. * return: no of converted packets
  3479. */
  3480. uint16_t
  3481. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3482. uint8_t newmac[][QDF_MAC_ADDR_SIZE], uint8_t new_mac_cnt)
  3483. {
  3484. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3485. struct dp_pdev *pdev = vdev->pdev;
  3486. qdf_ether_header_t *eh;
  3487. uint8_t *data;
  3488. uint16_t len;
  3489. /* reference to frame dst addr */
  3490. uint8_t *dstmac;
  3491. /* copy of original frame src addr */
  3492. uint8_t srcmac[QDF_MAC_ADDR_SIZE];
  3493. /* local index into newmac */
  3494. uint8_t new_mac_idx = 0;
  3495. struct dp_tx_me_buf_t *mc_uc_buf;
  3496. qdf_nbuf_t nbuf_clone;
  3497. struct dp_tx_msdu_info_s msdu_info;
  3498. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3499. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3500. struct dp_tx_seg_info_s *seg_info_new;
  3501. qdf_dma_addr_t paddr_data;
  3502. qdf_dma_addr_t paddr_mcbuf = 0;
  3503. uint8_t empty_entry_mac[QDF_MAC_ADDR_SIZE] = {0};
  3504. QDF_STATUS status;
  3505. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3506. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3507. eh = (qdf_ether_header_t *)nbuf;
  3508. qdf_mem_copy(srcmac, eh->ether_shost, QDF_MAC_ADDR_SIZE);
  3509. len = qdf_nbuf_len(nbuf);
  3510. data = qdf_nbuf_data(nbuf);
  3511. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3512. QDF_DMA_TO_DEVICE);
  3513. if (status) {
  3514. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3515. "Mapping failure Error:%d", status);
  3516. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3517. qdf_nbuf_free(nbuf);
  3518. return 1;
  3519. }
  3520. paddr_data = qdf_nbuf_mapped_paddr_get(nbuf) + QDF_MAC_ADDR_SIZE;
  3521. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3522. dstmac = newmac[new_mac_idx];
  3523. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3524. "added mac addr (%pM)", dstmac);
  3525. /* Check for NULL Mac Address */
  3526. if (!qdf_mem_cmp(dstmac, empty_entry_mac, QDF_MAC_ADDR_SIZE))
  3527. continue;
  3528. /* frame to self mac. skip */
  3529. if (!qdf_mem_cmp(dstmac, srcmac, QDF_MAC_ADDR_SIZE))
  3530. continue;
  3531. /*
  3532. * TODO: optimize to avoid malloc in per-packet path
  3533. * For eg. seg_pool can be made part of vdev structure
  3534. */
  3535. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3536. if (!seg_info_new) {
  3537. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3538. "alloc failed");
  3539. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3540. goto fail_seg_alloc;
  3541. }
  3542. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3543. if (!mc_uc_buf)
  3544. goto fail_buf_alloc;
  3545. /*
  3546. * TODO: Check if we need to clone the nbuf
  3547. * Or can we just use the reference for all cases
  3548. */
  3549. if (new_mac_idx < (new_mac_cnt - 1)) {
  3550. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3551. if (!nbuf_clone) {
  3552. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3553. goto fail_clone;
  3554. }
  3555. } else {
  3556. /*
  3557. * Update the ref
  3558. * to account for frame sent without cloning
  3559. */
  3560. qdf_nbuf_ref(nbuf);
  3561. nbuf_clone = nbuf;
  3562. }
  3563. qdf_mem_copy(mc_uc_buf->data, dstmac, QDF_MAC_ADDR_SIZE);
  3564. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3565. QDF_DMA_TO_DEVICE, QDF_MAC_ADDR_SIZE,
  3566. &paddr_mcbuf);
  3567. if (status) {
  3568. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3569. "Mapping failure Error:%d", status);
  3570. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3571. goto fail_map;
  3572. }
  3573. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3574. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3575. seg_info_new->frags[0].paddr_hi =
  3576. (uint16_t)((uint64_t)paddr_mcbuf >> 32);
  3577. seg_info_new->frags[0].len = QDF_MAC_ADDR_SIZE;
  3578. /*preparing data fragment*/
  3579. seg_info_new->frags[1].vaddr =
  3580. qdf_nbuf_data(nbuf) + QDF_MAC_ADDR_SIZE;
  3581. seg_info_new->frags[1].paddr_lo = (uint32_t)paddr_data;
  3582. seg_info_new->frags[1].paddr_hi =
  3583. (uint16_t)(((uint64_t)paddr_data) >> 32);
  3584. seg_info_new->frags[1].len = len - QDF_MAC_ADDR_SIZE;
  3585. seg_info_new->nbuf = nbuf_clone;
  3586. seg_info_new->frag_cnt = 2;
  3587. seg_info_new->total_len = len;
  3588. seg_info_new->next = NULL;
  3589. if (!seg_info_head)
  3590. seg_info_head = seg_info_new;
  3591. else
  3592. seg_info_tail->next = seg_info_new;
  3593. seg_info_tail = seg_info_new;
  3594. }
  3595. if (!seg_info_head) {
  3596. goto free_return;
  3597. }
  3598. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3599. msdu_info.num_seg = new_mac_cnt;
  3600. msdu_info.frm_type = dp_tx_frm_me;
  3601. msdu_info.tid = HTT_INVALID_TID;
  3602. if (qdf_unlikely(vdev->mcast_enhancement_en > 0) &&
  3603. qdf_unlikely(pdev->hmmc_tid_override_en))
  3604. msdu_info.tid = pdev->hmmc_tid;
  3605. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3606. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3607. while (seg_info_head->next) {
  3608. seg_info_new = seg_info_head;
  3609. seg_info_head = seg_info_head->next;
  3610. qdf_mem_free(seg_info_new);
  3611. }
  3612. qdf_mem_free(seg_info_head);
  3613. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3614. qdf_nbuf_free(nbuf);
  3615. return new_mac_cnt;
  3616. fail_map:
  3617. qdf_nbuf_free(nbuf_clone);
  3618. fail_clone:
  3619. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3620. fail_buf_alloc:
  3621. qdf_mem_free(seg_info_new);
  3622. fail_seg_alloc:
  3623. dp_tx_me_mem_free(pdev, seg_info_head);
  3624. free_return:
  3625. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3626. qdf_nbuf_free(nbuf);
  3627. return 1;
  3628. }